On 5/7/20 1:48 PM, Nicholas Piggin wrote: > Commit a77fed5bd926 ("ppc/pnv: Add support for NMI interface") got the > SRR1 setting wrong for sresets that hit outside of power-save states. > > Fix this, better documenting the source for the bit definitions. > > Fixes: a77fed5bd926 ("ppc/pnv: Add support for NMI interface") got the > Cc: Cédric Le Goater <c...@kaod.org> > Cc: David Gibson <da...@gibson.dropbear.id.au> > Signed-off-by: Nicholas Piggin <npig...@gmail.com>
We should introduce some defines like the SRR1_WAKE ones in Linux and cleanup powerpc_reset_wakeup(). This function uses cryptic values. That can be done later on as a followup. Reviewed-by: Cédric Le Goater <c...@kaod.org> > --- > > Thanks to Cedric for pointing out concerns with a previous MCE patch > that unearthed this as well. Linux does not actually care what these > SRR1[42:45] bits look like for non-powersave sresets, but we should > follow documented behaviour as far as possible. We should introduce some defines like the SRR1_WAKE ones in Linux and cleanup powerpc_reset_wakeup(). This function uses cryptic values. That can be done later on as a followup. I am currently after a bug which results in a CPU hard lockup because of a pending interrupt. It occurs on a SMP PowerNV machine when it is stressed with IO, such as scp of a big file. I am suspecting more and more an issue with an interrupt being handled when the CPU is coming out of idle. I haven't seen anything wrong in the models. Unless this maybe : /* Pretend to be returning from doze always as we don't lose state */ *msr |= (0x1ull << (63 - 47)); I am not sure how in sync it is with PSSCR. Thanks, C. > hw/ppc/pnv.c | 26 ++++++++++++++++++++------ > 1 file changed, 20 insertions(+), 6 deletions(-) > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index a3b7a8d0ff..1b4748ce6d 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -1986,12 +1986,26 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, > run_on_cpu_data arg) > > cpu_synchronize_state(cs); > ppc_cpu_do_system_reset(cs); > - /* > - * SRR1[42:45] is set to 0100 which the ISA defines as implementation > - * dependent. POWER processors use this for xscom triggered interrupts, > - * which come from the BMC or NMI IPIs. > - */ > - env->spr[SPR_SRR1] |= PPC_BIT(43); > + if (env->spr[SPR_SRR1] & PPC_BITMASK(46, 47)) { > + /* > + * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the > + * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 > + * (PPC_BIT(43)). > + */ > + if (!(env->spr[SPR_SRR1] & PPC_BIT(43))) { > + warn_report("ppc_cpu_do_system_reset does not set system reset > wakeup reason"); > + env->spr[SPR_SRR1] |= PPC_BIT(43); > + } > + } else { > + /* > + * For non-powersave system resets, SRR1[42:45] are defined to be > + * implementation-dependent. The POWER9 User Manual specifies that > + * an external (SCOM driven, which may come from a BMC nmi command or > + * another CPU requesting a NMI IPI) system reset exception should be > + * 0b0010 (PPC_BIT(44)). > + */ > + env->spr[SPR_SRR1] |= PPC_BIT(44); > + } > } > > static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) >