On Fri, May 08, 2020 at 10:43:05AM +0200, Greg Kurz wrote:
> On Thu, 7 May 2020 23:51:54 +1000
> David Gibson <da...@gibson.dropbear.id.au> wrote:
>
> > On Thu, May 07, 2020 at 09:48:24PM +1000, Nicholas Piggin wrote:
> > > Commit a77fed5bd926 ("ppc/pnv: Add support for NMI interface") got the
>
> Please note that the culprit patch was merged with a different SHA1:
>
> https://git.qemu.org/?p=qemu.git;a=commit;h=01b552b05b0f21f8ff57a508f7ad26f7abbcd123
>
> > > SRR1 setting wrong for sresets that hit outside of power-save states.
> > >
> > > Fix this, better documenting the source for the bit definitions.
> > >
> > > Fixes: a77fed5bd926 ("ppc/pnv: Add support for NMI interface") got the
>
> Fixes: 01b552b05b0f ("ppc/pnv: Add support for NMI interface")
Updated in my tree, thanks.
>
> > > Cc: Cédric Le Goater <c...@kaod.org>
> > > Cc: David Gibson <da...@gibson.dropbear.id.au>
> > > Signed-off-by: Nicholas Piggin <npig...@gmail.com>
> >
> > Applied to ppc-for-5.1, thanks.
> > > ---
> > >
> > > Thanks to Cedric for pointing out concerns with a previous MCE patch
> > > that unearthed this as well. Linux does not actually care what these
> > > SRR1[42:45] bits look like for non-powersave sresets, but we should
> > > follow documented behaviour as far as possible.
> > >
> > > hw/ppc/pnv.c | 26 ++++++++++++++++++++------
> > > 1 file changed, 20 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> > > index a3b7a8d0ff..1b4748ce6d 100644
> > > --- a/hw/ppc/pnv.c
> > > +++ b/hw/ppc/pnv.c
> > > @@ -1986,12 +1986,26 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs,
> > > run_on_cpu_data arg)
> > >
> > > cpu_synchronize_state(cs);
> > > ppc_cpu_do_system_reset(cs);
> > > - /*
> > > - * SRR1[42:45] is set to 0100 which the ISA defines as implementation
> > > - * dependent. POWER processors use this for xscom triggered
> > > interrupts,
> > > - * which come from the BMC or NMI IPIs.
> > > - */
> > > - env->spr[SPR_SRR1] |= PPC_BIT(43);
> > > + if (env->spr[SPR_SRR1] & PPC_BITMASK(46, 47)) {
> > > + /*
> > > + * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
> > > + * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
> > > + * (PPC_BIT(43)).
> > > + */
> > > + if (!(env->spr[SPR_SRR1] & PPC_BIT(43))) {
> > > + warn_report("ppc_cpu_do_system_reset does not set system
> > > reset wakeup reason");
> > > + env->spr[SPR_SRR1] |= PPC_BIT(43);
> > > + }
> > > + } else {
> > > + /*
> > > + * For non-powersave system resets, SRR1[42:45] are defined to be
> > > + * implementation-dependent. The POWER9 User Manual specifies that
> > > + * an external (SCOM driven, which may come from a BMC nmi command or
> > > + * another CPU requesting a NMI IPI) system reset exception should be
> > > + * 0b0010 (PPC_BIT(44)).
> > > + */
> > > + env->spr[SPR_SRR1] |= PPC_BIT(44);
> > > + }
> > > }
> > >
> > > static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
> >
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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