Implement the MVE VCADD insn, which performs a complex add with
rotate. Note that the size=0b11 encoding is VSBC.
The architecture grants some leeway for the "destination and Vm
source overlap" case for the size MO_32 case, but we choose not to
make use of it, instead always calculating all 16 bytes worth of
results before setting the destination register.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
target/arm/helper-mve.h | 8 ++++++++
target/arm/mve.decode | 7 ++++++-
target/arm/mve_helper.c | 31 +++++++++++++++++++++++++++++++
target/arm/translate-mve.c | 7 +++++++
4 files changed, 52 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 686e5d9a39b..6e345470cbb 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -251,6 +251,14 @@ DEF_HELPER_FLAGS_4(mve_vrhadduw, TCG_CALL_NO_WG, void,
env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_5(mve_vadc, TCG_CALL_NO_WG, i32, env, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(mve_vsbc, TCG_CALL_NO_WG, i32, env, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vcadd90b, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vcadd90h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vcadd90w, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vcadd270b, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vcadd270h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vcadd270w, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 6a4aae7a1fc..c0979f3941b 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -164,7 +164,12 @@ VRHADD_S 111 0 1111 0 . .. ... 0 ... 0 0001 . 1 .
0 ... 0 @2op
VRHADD_U 111 1 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op
VADC 1110 1110 0 . 11 ... 0 ... . 1111 . 0 . 0 ... 0 @vadc
-VSBC 1111 1110 0 . 11 ... 0 ... . 1111 . 0 . 0 ... 0 @vadc
+
+{
+ VCADD90 1111 1110 0 . .. ... 0 ... 0 1111 . 0 . 0 ... 0 @2op
+ VCADD270 1111 1110 0 . .. ... 0 ... 1 1111 . 0 . 0 ... 0 @2op
+ VSBC 1111 1110 0 . 11 ... 0 ... . 1111 . 0 . 0 ... 0 @vadc
+}
# Vector miscellaneous
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index e07f12c8389..2c8ef25b208 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -610,6 +610,37 @@ DO_2OP_U(vrhaddu, DO_RHADD_U)
DO_VADC(vadc, )
DO_VADC(vsbc, DO_NOT)
+#define DO_VCADD(OP, ESIZE, TYPE, H, FN0, FN1) \
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void
*vm) \
+ { \
+ TYPE *d = vd, *n = vn, *m = vm; \
+ uint16_t mask = mve_element_mask(env); \
+ unsigned e; \
+ TYPE r[16 / ESIZE]; \
+ /* Calculate all results first to avoid overwriting inputs */ \
+ for (e = 0; e < 16 / ESIZE; e++) { \
+ if (!(e & 1)) { \
+ r[e] = FN0(n[H(e)], m[H(e + 1)]); \
+ } else { \
+ r[e] = FN1(n[H(e)], m[H(e - 1)]); \
+ } \
+ } \
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
+ uint64_t bytemask = mask_to_bytemask##ESIZE(mask); \
+ d[H(e)] &= ~bytemask; \
+ d[H(e)] |= (r[e] & bytemask); \
+ } \
+ mve_advance_vpt(env); \
+ }
+
+#define DO_VCADD_ALL(OP, FN0, FN1) \
+ DO_VCADD(OP##b, 1, int8_t, H1, FN0, FN1) \
+ DO_VCADD(OP##h, 2, int16_t, H1, FN0, FN1) \
+ DO_VCADD(OP##w, 4, int32_t, H1, FN0, FN1)
+
+DO_VCADD_ALL(vcadd90, DO_SUB, DO_ADD)
+DO_VCADD_ALL(vcadd270, DO_ADD, DO_SUB)
+
static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool
*s)
{
if (val > max) {
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 2ed499a6de2..8e3989b0176 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -440,6 +440,13 @@ DO_2OP(VQRDMLSDH, vqrdmlsdh)
DO_2OP(VQRDMLSDHX, vqrdmlsdhx)
DO_2OP(VRHADD_S, vrhadds)
DO_2OP(VRHADD_U, vrhaddu)
+/*
+ * VCADD Qd == Qm at size MO_32 is UNPREDICTABLE; we choose not to diagnose
+ * so we can reuse the DO_2OP macro. (Our implementation calculates the
+ * "expected" results in this case.)
+ */
+DO_2OP(VCADD90, vcadd90)
+DO_2OP(VCADD270, vcadd270)
static bool trans_VQDMULLB(DisasContext *s, arg_2op *a)
{
--
2.20.1
