Signed-off-by: liweiwei <liwei...@iscas.ac.cn>
Signed-off-by: wangjunqiang <wangjunqi...@iscas.ac.cn>
---
target/riscv/cpu.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 961c5f4334..6575ec8cfa 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -668,6 +668,19 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+ DEFINE_PROP_BOOL("x-zbkb", RISCVCPU, cfg.ext_zbkb, false),
+ DEFINE_PROP_BOOL("x-zbkc", RISCVCPU, cfg.ext_zbkc, false),
+ DEFINE_PROP_BOOL("x-zbkx", RISCVCPU, cfg.ext_zbkx, false),
+ DEFINE_PROP_BOOL("x-zk", RISCVCPU, cfg.ext_zk, false),
+ DEFINE_PROP_BOOL("x-zkn", RISCVCPU, cfg.ext_zkn, false),
+ DEFINE_PROP_BOOL("x-zknd", RISCVCPU, cfg.ext_zknd, false),
+ DEFINE_PROP_BOOL("x-zkne", RISCVCPU, cfg.ext_zkne, false),
+ DEFINE_PROP_BOOL("x-zknh", RISCVCPU, cfg.ext_zknh, false),
+ DEFINE_PROP_BOOL("x-zkr", RISCVCPU, cfg.ext_zkr, false),
+ DEFINE_PROP_BOOL("x-zks", RISCVCPU, cfg.ext_zks, false),
+ DEFINE_PROP_BOOL("x-zksed", RISCVCPU, cfg.ext_zksed, false),
+ DEFINE_PROP_BOOL("x-zksh", RISCVCPU, cfg.ext_zksh, false),
+ DEFINE_PROP_BOOL("x-zkt", RISCVCPU, cfg.ext_zkt, false),