Hi, I just wanted to notify you of some progress that's been made with the partial reconfiguration features of ReconOS. I've managed to create a set of partial bitstreams using the 12.3 tools (esp. PlanAhead) and the ReconOS tool chain. I've also been able to partially reconfigure single hardware threads manually via JTAG on the ML605.
Things missing / to do: 1. Proper tool chain support: This will probably involve scripting PlanAhead to create the necessary configurations. I've been able to create a valid partially reconfigurable PlanAhead project using only the bitstreams generated by the ReconOS EAPR Makefile. Also, some renaming and cleanup of the "master" Makefile would be in order. Interestingly enough, the clocking magic we had to do with the old EAPR tool chain seems no longer necessary. 2. OSIF interface logic: Since the new PR tool flow does not use bus macros but instantiates the necessary Partition Pins automatically, we need to replicate some of the functionality of the former bus macros within the OSIF: - registers for all non-RAM (i.e. synchronous) signals to improve timing closure - enable signals for all outgoing signals (hardware thread to OSIF) to prevent accidental activity on reconfiguration 3. ICAP support for eCos: There is a new HWICAP IP core in EDK 12.3, which I hope to be faster and easier to use than the 9.02 versions. If there are any changes to the API we need to patch our hardware scheduling code accordingly. Also, a new reference design (ml605_light_pr) with the ICAP core should be created. Any comments, suggestions or questions are welcome. This list needs more traffic. :) Best regards - Enno _______________________________________________ Reconos-devel_lists.reconos.de mailing list reconos-devel@lists.reconos.de https://ml01.ispgateway.de/mailman/listinfo/reconos-devel_lists.reconos.de
