Hi Ariane,
2. OSIF interface logic:
For point two: Are you thinking about just redefining the busmacros
(as suggested in some xilinx documentation) or would you re-write
the actual osif code?
Probably the latter. Though timing is always a possible issue, I
suggest that we first just replicate the 'enable' functionality of the
bus macros within the OSIF and leave the additional register stages
for later. The ML605/Virtex-6's fabric is significantly faster, so
that inserting Partition Pins doesn't seem to impede the timing
closure of our paltry 100MHz designs that much.
The new PR tool chain seems to be able to work with the netlist of a
plain ReconOS reference design without manual tweaking of clock buffer
assignments or bus macro placement. This could lead to a much
simplfied ReconOS tool chain. Putting the 'enable' modifications
directly into the OSIF would also go some way towards simplifying the
tool chain. I'll give it a try and keep you updated.
Best
- Enno
_______________________________________________
Reconos-devel_lists.reconos.de mailing list
reconos-devel@lists.reconos.de
https://ml01.ispgateway.de/mailman/listinfo/reconos-devel_lists.reconos.de
