Wed, 05 Jul 2000 Norm Dresner wrote:
> At 08:42 PM 7/4/2000 +0200, Andrew Tuckey wrote:
> [SNIP]
> >One of the main delays I want to avoid is getting data from the A/Ds.
> >currently I'm using a couple of C40s, and I have to slow down the bus speed
> >(currently using 5 wait states) to get the data from the analogue or digital
> >I/O boards. With a 10kHz sample rate I don't get much time to move data over
> >the backplane so I figure that I could do it faster with the chips closer
> >i.e. on the main board. Again, I'm not sure of the details.
>
> Why aren't you using an ADC board which supports DMA? If you did, you
> wouldn't be worried about the CPU's response time to interrupts.
Might be that DMA isn't particularly helpful if you have a control cycle of a
single sample. For most applications, it would still make sense to use hardware
FIFOs or latches triggered from a sample rate clock (to eliminate CPU/software
induced jitter), but it's possible that the output signal in this case is less
sensitive to jitter than it is to latency; ie it's better to get the result out
ASAP, rather than clocking it out exactly one sample period later.
Of course, if there are no such requirements on input->output latency, DMA (or
possibly hardware FIFOs) is the way to go. Handling a few samples per IRQ saves
*lots* of CPU power, especially on x86 and other workstation/PC CPUs (deep
pipelines, prediction, slow RAM/fast cache etc).
David Olofson
Programmer
Reologica Instruments AB
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