On Wed, Jul 13, 2022 at 03:25:17AM +0200, Petr Cvek wrote: > ASPI2DOS.SYS and KEYB.COM from Win 98 SE installation CD (and most likely > other DOS versions too) depend on I/O port 0x61 bit 4 to be toggled. This > requires timer 1 (I/O 0x41, legacy DRAM refresh) to be correctly set. > Also Intel ICH7 Family Datasheet, chapter 5.8 states: > > Programming the counter to anything other than Mode 2 will result in > undefined behavior for the REF_TOGGLE bit. > > Failing to have the timer 1 configured indeed causes affected OSes to > freeze during the boot.
Thanks. In general, I don't see an issue with initializing standard hardware. However, a change like this could have a subtle impact on existing installations. So, I'd like to have a better understanding of this change. Did the above compatibility issue occur on coreboot or on QEMU? If on coreboot, can you check if the problem exists on QEMU? If it isn't an issue on QEMU, do you know why? Finally, have you found any documents that describe how timer1 is intended to be configured on legacy systems? Thanks again, -Kevin > > Signed-off-by: Petr Cvek <petrcve...@gmail.com> > --- > src/hw/timer.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/src/hw/timer.c b/src/hw/timer.c > index b6f102e..b272f44 100644 > --- a/src/hw/timer.c > +++ b/src/hw/timer.c > @@ -280,4 +280,10 @@ pit_setup(void) > // maximum count of 0000H = 18.2Hz > outb(0x0, PORT_PIT_COUNTER0); > outb(0x0, PORT_PIT_COUNTER0); > + > + // timer1: binary count, 16bit count, mode 2 > + outb(PM_SEL_TIMER1|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE); > + // maximum count of 0012H = 66.3kHz > + outb(0x12, PORT_PIT_COUNTER1); > + outb(0x0, PORT_PIT_COUNTER1); > } > -- > 2.37.0 > > _______________________________________________ > SeaBIOS mailing list -- seabios@seabios.org > To unsubscribe send an email to seabios-le...@seabios.org _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-le...@seabios.org
