Dne 05. 08. 22 v 20:18 Kevin O'Connor napsal(a): > On Wed, Jul 13, 2022 at 03:25:17AM +0200, Petr Cvek wrote: >> ASPI2DOS.SYS and KEYB.COM from Win 98 SE installation CD (and most likely >> other DOS versions too) depend on I/O port 0x61 bit 4 to be toggled. This >> requires timer 1 (I/O 0x41, legacy DRAM refresh) to be correctly set. >> Also Intel ICH7 Family Datasheet, chapter 5.8 states: >> >> Programming the counter to anything other than Mode 2 will result in >> undefined behavior for the REF_TOGGLE bit. >> >> Failing to have the timer 1 configured indeed causes affected OSes to >> freeze during the boot. > > Thanks. In general, I don't see an issue with initializing standard > hardware. However, a change like this could have a subtle impact on > existing installations. So, I'd like to have a better understanding > of this change. > > Did the above compatibility issue occur on coreboot or on QEMU? If on > coreboot, can you check if the problem exists on QEMU? If it isn't an > issue on QEMU, do you know why? Finally, have you found any documents > that describe how timer1 is intended to be configured on legacy > systems? >
I've found it when trying to boot windows 98 SE installation under coreboot. Inside QEMU the test for I/O port 0x61 bit 4 succeeds (no hang up). It seems the QEMU has the timer 1 already enabled. One of the multiple checks in KEYB.COM 00000F44 E461 in al,0x61 00000F46 2410 and al,0x10 00000F48 3AC4 cmp al,ah 00000F4A 74F8 jz 0xf44 If the timer is disabled (and other bit state is required by cmp) the test will spin forever. I've tried to check on a real hardware if the timer is stopped and indeed it was. After a manual configuration in a debugger the KEYB.COM succeeded to run. So far I've found the timer 1 description in the ICH7 datasheet: Intel® I/O Controller Hub 7 (ICH7) Family Section 5.8 8254 Timers (D31:F0) The REF_TOGGLE bit will have a square wave behavior (alternate between 0 and 1) and will toggle at a rate based on the value in the counter. Programming the counter to anything other than Mode 2 will result in undefined behavior for the REF_TOGGLE bit. (the alternation between 0 and 1 is used by those DOS programs) There is actually a setup function in coreboot, but it is called in a specific case, when video bios is executed in a realmode environment. The divider value is taken from there (also I've seen the same value in MSDOS age documentation). https://elixir.bootlin.com/coreboot/4.17/source/src/drivers/pc80/pc/i8254.c#L20 (I'm not sure the values there are correct too, ICH7 datasheet says MODE2 and maybe MSB should be erased also, I've set WIP patch at https://review.coreboot.org/c/coreboot/+/65809 but that's slightly OT) Petr > Thanks again, > -Kevin > > >> >> Signed-off-by: Petr Cvek <petrcve...@gmail.com> >> --- >> src/hw/timer.c | 6 ++++++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/src/hw/timer.c b/src/hw/timer.c >> index b6f102e..b272f44 100644 >> --- a/src/hw/timer.c >> +++ b/src/hw/timer.c >> @@ -280,4 +280,10 @@ pit_setup(void) >> // maximum count of 0000H = 18.2Hz >> outb(0x0, PORT_PIT_COUNTER0); >> outb(0x0, PORT_PIT_COUNTER0); >> + >> + // timer1: binary count, 16bit count, mode 2 >> + outb(PM_SEL_TIMER1|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, >> PORT_PIT_MODE); >> + // maximum count of 0012H = 66.3kHz >> + outb(0x12, PORT_PIT_COUNTER1); >> + outb(0x0, PORT_PIT_COUNTER1); >> } >> -- >> 2.37.0 >> >> _______________________________________________ >> SeaBIOS mailing list -- seabios@seabios.org >> To unsubscribe send an email to seabios-le...@seabios.org _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-le...@seabios.org
