[PATCH] drm/amd/amdgpu: Add SQ debug registers to GFX10 headers

[Tom St Denis]

Requested for UMR support.

Signed-off-by: Tom St Denis 
---
 .../include/asic_reg/gc/gc_10_1_0_offset.h|  1 +
 .../include/asic_reg/gc/gc_10_1_0_sh_mask.h   | 20 +++
 .../include/asic_reg/gc/gc_10_3_0_offset.h|  1 +
 .../include/asic_reg/gc/gc_10_3_0_sh_mask.h   | 19 ++
 4 files changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
index 075867d4b1da..791dc2b3d74a 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
@@ -11151,6 +11151,7 @@
 
 // addressBlock: sqind
 // base address: 0x0
+#define ixSQ_DEBUG_STS_LOCAL   
0x0008
 #define ixSQ_WAVE_MODE 
0x0101
 #define ixSQ_WAVE_STATUS   
0x0102
 #define ixSQ_WAVE_TRAPSTS  
0x0103
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
index 8b0b9a2a8fed..355e61bed291 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
@@ -42546,6 +42546,26 @@
 
 
 // addressBlock: sqind
+//SQ_DEBUG_STS_LOCAL
+#define SQ_DEBUG_STS_LOCAL__BUSY_MASK  
   0x0001L
+#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT
   0x
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK
   0x03f0L
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT  
   0x0004
+#define SQ_DEBUG_STS_LOCAL__SQ_BUSY_MASK   
   0x1000L
+#define SQ_DEBUG_STS_LOCAL__SQ_BUSY__SHIFT 
   0x000C
+#define SQ_DEBUG_STS_LOCAL__IS_BUSY_MASK   
   0x2000L
+#define SQ_DEBUG_STS_LOCAL__IS_BUSY__SHIFT 
   0x000D
+#define SQ_DEBUG_STS_LOCAL__IB_BUSY_MASK   
   0x4000L
+#define SQ_DEBUG_STS_LOCAL__IB_BUSY__SHIFT 
   0x000E
+#define SQ_DEBUG_STS_LOCAL__ARB_BUSY_MASK  
   0x8000L
+#define SQ_DEBUG_STS_LOCAL__ARB_BUSY__SHIFT
   0x000F
+#define SQ_DEBUG_STS_LOCAL__EXP_BUSY_MASK  
   0x0001L
+#define SQ_DEBUG_STS_LOCAL__EXP_BUSY__SHIFT
   0x0010
+#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY_MASK
   0x0002L
+#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY__SHIFT  
   0x0011
+#define SQ_DEBUG_STS_LOCAL__VM_BUSY_MASK   
   0x0004L
+#define SQ_DEBUG_STS_LOCAL__VM_BUSY__SHIFT 
   0x0018
+
 //SQ_WAVE_MODE
 #define SQ_WAVE_MODE__FP_ROUND__SHIFT  
   0x0
 #define SQ_WAVE_MODE__FP_DENORM__SHIFT 
   0x4
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
index 71c787d66132..a9a66371b75e 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
@@ -13277,6 +13277,7 @@
 
 // addressBlock: sqind
 // base address: 0x0
+#define ixSQ_DEBUG_STS_LOCAL   
0x0008
 #define ixSQ_WAVE_ACTIVE   
0x000a
 #define ixSQ_WAVE_VALID_AND_IDLE   
0x000b
 #define ixSQ_WAVE_MODE 
0x0101
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
index

[PATCH] drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits

[Tom St Denis]

Even though they are technically MMIO registers I put the bits with the sqind 
block
for organizational purposes.

Requested for UMR debugging.

Signed-off-by: Tom St Denis 
---
 .../include/asic_reg/gc/gc_10_1_0_offset.h|  3 ++-
 .../include/asic_reg/gc/gc_10_1_0_sh_mask.h   | 16 ++
 .../include/asic_reg/gc/gc_10_3_0_offset.h|  3 ++-
 .../include/asic_reg/gc/gc_10_3_0_sh_mask.h   | 16 ++
 .../amd/include/asic_reg/gc/gc_9_0_offset.h   |  4 +++-
 .../amd/include/asic_reg/gc/gc_9_0_sh_mask.h  | 22 +++
 .../amd/include/asic_reg/gc/gc_9_1_offset.h   |  4 +++-
 .../amd/include/asic_reg/gc/gc_9_1_sh_mask.h  | 21 ++
 .../amd/include/asic_reg/gc/gc_9_2_1_offset.h |  4 +++-
 .../include/asic_reg/gc/gc_9_2_1_sh_mask.h| 21 ++
 10 files changed, 109 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
index 791dc2b3d74a..aab3d22c3b0f 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
@@ -21,7 +21,8 @@
 #ifndef _gc_10_1_0_OFFSET_HEADER
 #define _gc_10_1_0_OFFSET_HEADER
 
-
+#define mmSQ_DEBUG_STS_GLOBAL  
0x2309
+#define mmSQ_DEBUG_STS_GLOBAL2 
0x2310
 
 // addressBlock: gc_sdma0_sdma0dec
 // base address: 0x4980
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
index 355e61bed291..4127896ffcdf 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
@@ -42546,6 +42546,22 @@
 
 
 // addressBlock: sqind
+//SQ_DEBUG_STS_GLOBAL
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x00ffL
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0xff00L
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x0008
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE_MASK 0xffL
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE__SHIFT 0x0010
+#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x0001L
+#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x
+#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x0002L
+#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x0001
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0_MASK 0xfff0L
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0__SHIFT 0x0004
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1_MASK 0x0fffL
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1__SHIFT 0x0010
+
 //SQ_DEBUG_STS_LOCAL
 #define SQ_DEBUG_STS_LOCAL__BUSY_MASK  
   0x0001L
 #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT
   0x
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
index a9a66371b75e..16c7f6f2467e 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
@@ -22,7 +22,8 @@
 #ifndef _gc_10_3_0_OFFSET_HEADER
 #define _gc_10_3_0_OFFSET_HEADER
 
-
+#define mmSQ_DEBUG_STS_GLOBAL  
0x2309
+#define mmSQ_DEBUG_STS_GLOBAL2 
0x2310
 
 // addressBlock: gc_sdma0_sdma0dec
 // base address: 0x4980
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
index 499a8c3c2693..aac57f714cf1 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
@@ -46269,6 +46269,22 @@
 
 
 // addressBlock: sqind
+//SQ_DEBUG_STS_GLOBAL
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x00ffL
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0xff00L
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x0008
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE_MASK 0xffL
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE__SHIFT 0x0010
+#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x0001L
+#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x
+#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x0002L
+#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x0001
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0_MASK 0xfff0L
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0__SHIFT 0x0004
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1_MASK 0x0fffL
+#define

[PATCH] drm/amd/amdgpu: Fix SQ_DEBUG_STS_GLOBAL* registers

[Tom St Denis]

Forgot to subtract the SOC15 IP offsetand add the BASE_IDX values.

Signed-off-by: Tom St Denis 
---
 .../gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h   | 6 --
 .../gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h   | 6 --
 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h  | 9 ++---
 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h  | 9 ++---
 .../gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h| 9 ++---
 5 files changed, 26 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
index aab3d22c3b0f..baac40fa70e7 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
@@ -21,8 +21,10 @@
 #ifndef _gc_10_1_0_OFFSET_HEADER
 #define _gc_10_1_0_OFFSET_HEADER
 
-#define mmSQ_DEBUG_STS_GLOBAL  
0x2309
-#define mmSQ_DEBUG_STS_GLOBAL2 
0x2310
+#define mmSQ_DEBUG_STS_GLOBAL  
0x0309
+#define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 
0
+#define mmSQ_DEBUG_STS_GLOBAL2 
0x0310
+#define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX
0
 
 // addressBlock: gc_sdma0_sdma0dec
 // base address: 0x4980
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
index 16c7f6f2467e..0bde3b4e9567 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
@@ -22,8 +22,10 @@
 #ifndef _gc_10_3_0_OFFSET_HEADER
 #define _gc_10_3_0_OFFSET_HEADER
 
-#define mmSQ_DEBUG_STS_GLOBAL  
0x2309
-#define mmSQ_DEBUG_STS_GLOBAL2 
0x2310
+#define mmSQ_DEBUG_STS_GLOBAL  
0x0309
+#define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 
0
+#define mmSQ_DEBUG_STS_GLOBAL2 
0x0310
+#define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX
0
 
 // addressBlock: gc_sdma0_sdma0dec
 // base address: 0x4980
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
index e3e1a9c1153b..12d451e5475b 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
@@ -21,9 +21,12 @@
 #ifndef _gc_9_0_OFFSET_HEADER
 #define _gc_9_0_OFFSET_HEADER
 
-#define mmSQ_DEBUG_STS_GLOBAL  
0x2309
-#define mmSQ_DEBUG_STS_GLOBAL2 
0x2310
-#define mmSQ_DEBUG_STS_GLOBAL3 
0x2311
+#define mmSQ_DEBUG_STS_GLOBAL  
0x0309
+#define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 
0
+#define mmSQ_DEBUG_STS_GLOBAL2 
0x0310
+#define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX
0
+#define mmSQ_DEBUG_STS_GLOBAL3 
0x0311
+#define mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX
0
 
 // addressBlock: gc_grbmdec
 // base address: 0x8000
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
index 6b1ad9082a2c..d17d1e622e4f 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
@@ -21,9 +21,12 @@
 #ifndef _gc_9_1_OFFSET_HEADER
 #define _gc_9_1_OFFSET_HEADER
 
-#define mmSQ_DEBUG_STS_GLOBAL  
0x2309
-#define mmSQ_DEBUG_STS_GLOBAL2 
0x2310
-#define mmSQ_DEBUG_STS_GLOBAL3 
0x2311
+#define mmSQ_DEBUG_STS_GLOBAL  
0x0309

[PATCH] drm/amd/amdgpu: Fix offset for SQ_DEBUG_STS_GLOBAL on gfx10

[Tom St Denis]

Despite having different IP offsets the computed address of the register(s)
are the same between gfx7..gfx10.  This patch fixes the offset relative
to the GC block on gfx10.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h | 4 ++--
 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
index baac40fa70e7..c737d90a8d31 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
@@ -21,9 +21,9 @@
 #ifndef _gc_10_1_0_OFFSET_HEADER
 #define _gc_10_1_0_OFFSET_HEADER
 
-#define mmSQ_DEBUG_STS_GLOBAL  
0x0309
+#define mmSQ_DEBUG_STS_GLOBAL  
0x10A9
 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 
0
-#define mmSQ_DEBUG_STS_GLOBAL2 
0x0310
+#define mmSQ_DEBUG_STS_GLOBAL2 
0x10AA
 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX
0
 
 // addressBlock: gc_sdma0_sdma0dec
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
index 0bde3b4e9567..09ad21dc2d8c 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
@@ -22,9 +22,9 @@
 #ifndef _gc_10_3_0_OFFSET_HEADER
 #define _gc_10_3_0_OFFSET_HEADER
 
-#define mmSQ_DEBUG_STS_GLOBAL  
0x0309
+#define mmSQ_DEBUG_STS_GLOBAL  
0x10A9
 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 
0
-#define mmSQ_DEBUG_STS_GLOBAL2 
0x0310
+#define mmSQ_DEBUG_STS_GLOBAL2 
0x10AA
 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX
0
 
 // addressBlock: gc_sdma0_sdma0dec
-- 
2.26.2

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[PATCH] drm/amd/amdgpu: Fix offset for SQ_DEBUG_STS_GLOBAL on gfx10 (v2)

[Tom St Denis]

Despite having different IP offsets the computed address of the register(s)
are the same between gfx7..gfx10.  This patch fixes the offset relative
to the GC block on gfx10.

(v2): SQ_DEBUG_STS_GLOBAL2 is 0x10 higher ...

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h | 4 ++--
 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
index baac40fa70e7..18d34bbceebe 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
@@ -21,9 +21,9 @@
 #ifndef _gc_10_1_0_OFFSET_HEADER
 #define _gc_10_1_0_OFFSET_HEADER
 
-#define mmSQ_DEBUG_STS_GLOBAL  
0x0309
+#define mmSQ_DEBUG_STS_GLOBAL  
0x10A9
 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 
0
-#define mmSQ_DEBUG_STS_GLOBAL2 
0x0310
+#define mmSQ_DEBUG_STS_GLOBAL2 
0x10B0
 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX
0
 
 // addressBlock: gc_sdma0_sdma0dec
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
index 0bde3b4e9567..05d1b0a5f6d2 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
@@ -22,9 +22,9 @@
 #ifndef _gc_10_3_0_OFFSET_HEADER
 #define _gc_10_3_0_OFFSET_HEADER
 
-#define mmSQ_DEBUG_STS_GLOBAL  
0x0309
+#define mmSQ_DEBUG_STS_GLOBAL  
0x10A9
 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 
0
-#define mmSQ_DEBUG_STS_GLOBAL2 
0x0310
+#define mmSQ_DEBUG_STS_GLOBAL2 
0x10B0
 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX
0
 
 // addressBlock: gc_sdma0_sdma0dec
-- 
2.26.2

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[PATCH] drm/amd/amdgpu: Fix compiler warning in df driver

[Tom St Denis]

Fix this warning:

  CC [M]  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.o
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h:29,
 from drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h:26,
 from drivers/gpu/drm/amd/amdgpu/amdgpu.h:43,
 from drivers/gpu/drm/amd/amdgpu/df_v3_6.c:23:
drivers/gpu/drm/amd/amdgpu/df_v3_6.c: In function ‘df_v3_6_pmc_get_count’:
./include/drm/drm_print.h:487:2: warning: ‘hi_base_addr’ may be used 
uninitialized in this function [-Wmaybe-uninitialized]
  487 |  __drm_dbg(DRM_UT_DRIVER, fmt, ##__VA_ARGS__)
  |  ^
drivers/gpu/drm/amd/amdgpu/df_v3_6.c:649:25: note: ‘hi_base_addr’ was declared 
here
  649 |  uint32_t lo_base_addr, hi_base_addr, lo_val = 0, hi_val = 0;
  | ^~~~
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h:29,
 from drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h:26,
 from drivers/gpu/drm/amd/amdgpu/amdgpu.h:43,
 from drivers/gpu/drm/amd/amdgpu/df_v3_6.c:23:
./include/drm/drm_print.h:487:2: warning: ‘lo_base_addr’ may be used 
uninitialized in this function [-Wmaybe-uninitialized]
  487 |  __drm_dbg(DRM_UT_DRIVER, fmt, ##__VA_ARGS__)
  |  ^
drivers/gpu/drm/amd/amdgpu/df_v3_6.c:649:11: note: ‘lo_base_addr’ was declared 
here
  649 |  uint32_t lo_base_addr, hi_base_addr, lo_val = 0, hi_val = 0;

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c 
b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
index 1ab261836983..0aa1ac1accd6 100644
--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
@@ -646,7 +646,7 @@ static void df_v3_6_pmc_get_count(struct amdgpu_device 
*adev,
  uint64_t config,
  uint64_t *count)
 {
-   uint32_t lo_base_addr, hi_base_addr, lo_val = 0, hi_val = 0;
+   uint32_t lo_base_addr = 0, hi_base_addr = 0, lo_val = 0, hi_val = 0;
*count = 0;
 
switch (adev->asic_type) {
-- 
2.26.2

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[PATCH] drm/amd/powerplay: Fix uninitialized warning in arcturus ppt driver

[Tom St Denis]

Fixes:

  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_mst_types.o
drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c: In function 
‘arcturus_log_thermal_throttling_event’:
drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c:2223:24: warning: 
‘throttler_status’ may be used uninitialized in this function 
[-Wmaybe-uninitialized]
 2223 |   if (throttler_status & logging_label[throttler_idx].feature_mask) {

by making arcturus_get_smu_metrics_data() assign a default value
(of zero) before any possible return point as well as simply error
out of arcturus_log_thermal_throttling_event() if it fails.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 8b1025dc54fd..78f7ec95e4f5 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -551,6 +551,9 @@ static int arcturus_get_smu_metrics_data(struct smu_context 
*smu,
 
mutex_lock(&smu->metrics_lock);
 
+   // assign default value
+   *value = 0;
+
ret = smu_cmn_get_metrics_table_locked(smu,
   NULL,
   false);
@@ -2208,15 +2211,20 @@ static const struct throttling_logging_label {
 };
 static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
 {
-   int throttler_idx, throtting_events = 0, buf_idx = 0;
+   int throttler_idx, throtting_events = 0, buf_idx = 0, ret;
struct amdgpu_device *adev = smu->adev;
uint32_t throttler_status;
char log_buf[256];
 
-   arcturus_get_smu_metrics_data(smu,
+   ret = arcturus_get_smu_metrics_data(smu,
  METRICS_THROTTLER_STATUS,
  &throttler_status);
 
+   if (ret) {
+   dev_err(adev->dev, "Could not read from 
arcturus_get_smu_metrics_data()\n");
+   return;
+   }
+
memset(log_buf, 0, sizeof(log_buf));
for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
 throttler_idx++) {
-- 
2.26.2

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[PATCH] drm/amd/powerplay: Fix uninitialized warning in arcturus ppt driver (v2)

[Tom St Denis]

Fixes:

  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_mst_types.o
drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c: In function 
‘arcturus_log_thermal_throttling_event’:
drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c:2223:24: warning: 
‘throttler_status’ may be used uninitialized in this function 
[-Wmaybe-uninitialized]
 2223 |   if (throttler_status & logging_label[throttler_idx].feature_mask) {

By assigning an initial value and also checking for errors on the call to
arcturus_get_smu_metrics_data().

(v2): don't set default in arcturus_get_smu_metrics_data()

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 8b1025dc54fd..f6fe8e0ff977 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -2208,15 +2208,20 @@ static const struct throttling_logging_label {
 };
 static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
 {
-   int throttler_idx, throtting_events = 0, buf_idx = 0;
+   int throttler_idx, throtting_events = 0, buf_idx = 0, ret;
struct amdgpu_device *adev = smu->adev;
-   uint32_t throttler_status;
+   uint32_t throttler_status = 0;
char log_buf[256];
 
-   arcturus_get_smu_metrics_data(smu,
+   ret = arcturus_get_smu_metrics_data(smu,
  METRICS_THROTTLER_STATUS,
  &throttler_status);
 
+   if (ret) {
+   dev_err(adev->dev, "Could not read from 
arcturus_get_smu_metrics_data()\n");
+   return;
+   }
+
memset(log_buf, 0, sizeof(log_buf));
for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
 throttler_idx++) {
-- 
2.26.2

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Re: [PATCH 1/2] drm/amd/pm: correct gpu metrics related data structures

[Tom St Denis]

This is why I advocated for the sysfs output to be either standard packed
or serialized.  It was a hack as it is anyways.

On Mon, Feb 22, 2021 at 4:46 PM Alex Deucher  wrote:

> On Sun, Feb 21, 2021 at 11:03 PM Evan Quan  wrote:
> >
> > To make sure they are naturally aligned.
> >
> > Change-Id: I496a5b79158bdbd2e17f179098939e050b2ad489
> > Signed-off-by: Evan Quan 
>
> Won't this break existing apps that query this info?  We need to make
> sure umr and rocm-smi can handle this.
>
> Alex
>
>
> > ---
> >  drivers/gpu/drm/amd/include/kgd_pp_interface.h| 11 ++-
> >  drivers/gpu/drm/amd/pm/inc/smu_v11_0.h|  4 ++--
> >  drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c |  8 
> >  drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c |  8 
> >  drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c|  8 
> >  5 files changed, 20 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > index 828513412e20..3a8f64e1a10c 100644
> > --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > @@ -332,9 +332,9 @@ struct amd_pm_funcs {
> >  };
> >
> >  struct metrics_table_header {
> > -   uint16_tstructure_size;
> > -   uint8_t format_revision;
> > -   uint8_t content_revision;
> > +   uint32_tstructure_size;
> > +   uint16_tformat_revision;
> > +   uint16_tcontent_revision;
> >  };
> >
> >  struct gpu_metrics_v1_0 {
> > @@ -385,8 +385,9 @@ struct gpu_metrics_v1_0 {
> > uint16_tcurrent_fan_speed;
> >
> > /* Link width/speed */
> > -   uint8_t pcie_link_width;
> > -   uint8_t pcie_link_speed; // in 0.1 GT/s
> > +   uint16_tpcie_link_width;
> > +   uint16_tpcie_link_speed; // in 0.1 GT/s
> > +   uint8_t padding[2];
> >  };
> >
> >  struct gpu_metrics_v2_0 {
> > diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> > index 50dd1529b994..f4e7a330f67f 100644
> > --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> > +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> > @@ -284,11 +284,11 @@ int smu_v11_0_get_dpm_level_range(struct
> smu_context *smu,
> >
> >  int smu_v11_0_get_current_pcie_link_width_level(struct smu_context
> *smu);
> >
> > -int smu_v11_0_get_current_pcie_link_width(struct smu_context *smu);
> > +uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu);
> >
> >  int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context
> *smu);
> >
> > -int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu);
> > +uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu);
> >
> >  int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
> >   bool enablement);
> > diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
> > index c0753029a8e2..95e905d8418d 100644
> > --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
> > +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c
> > @@ -52,8 +52,8 @@
> >
> >  #define LINK_WIDTH_MAX 6
> >  #define LINK_SPEED_MAX 3
> > -static int link_width[] = {0, 1, 2, 4, 8, 12, 16};
> > -static int link_speed[] = {25, 50, 80, 160};
> > +static uint16_t link_width[] = {0, 1, 2, 4, 8, 12, 16};
> > +static uint16_t link_speed[] = {25, 50, 80, 160};
> >
> >  static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
> > enum pp_clock_type type, uint32_t mask);
> > @@ -2117,7 +2117,7 @@ static int
> vega12_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr)
> > >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
> >  }
> >
> > -static int vega12_get_current_pcie_link_width(struct pp_hwmgr *hwmgr)
> > +static uint16_t vega12_get_current_pcie_link_width(struct pp_hwmgr
> *hwmgr)
> >  {
> > uint32_t width_level;
> >
> > @@ -2137,7 +2137,7 @@ static int
> vega12_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr)
> > >>
> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
> >  }
> >
> > -static int vega12_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr)
> > +static uint16_t vega12_get_current_pcie_link_speed(struct pp_hwmgr
> *hwmgr)
> >  {
> > uint32_t speed_level;
> >
> > diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> > index 87811b005b85..3d462405b572 100644
> > --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> > +++ b/drivers/gpu/drm/amd/pm

[PATCH] drm/amd/amdgpu: Add CP_IB1_BASE_* to gc_10_3_0 headers

[Tom St Denis]

Signed-off-by: Tom St Denis 
---
 .../gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h   | 6 ++
 .../gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h  | 9 +
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
index 0102487a2c5f..f21554a1c86c 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
@@ -6955,6 +6955,12 @@
 #define mmCP_CE_IB2_BASE_HI_BASE_IDX   
1
 #define mmCP_CE_IB2_BUFSZ  
0x20cb
 #define mmCP_CE_IB2_BUFSZ_BASE_IDX 
1
+#define mmCP_IB1_BASE_LO   
0x20cc
+#define mmCP_IB1_BASE_LO_BASE_IDX  
1
+#define mmCP_IB1_BASE_HI   
0x20cd
+#define mmCP_IB1_BASE_HI_BASE_IDX  
1
+#define mmCP_IB1_BUFSZ 
0x20ce
+#define mmCP_IB1_BUFSZ_BASE_IDX
1
 #define mmCP_IB2_BASE_LO   
0x20cf
 #define mmCP_IB2_BASE_LO_BASE_IDX  
1
 #define mmCP_IB2_BASE_HI   
0x20d0
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
index 4d2a1432c121..a827b0ff8905 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
@@ -25818,6 +25818,15 @@
 //CP_CE_IB2_BUFSZ
 #define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT  
   0x0
 #define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK
   0x000FL
+//CP_IB1_BASE_LO
+#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 
   0x2
+#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK   
   0xFFFCL
+//CP_IB1_BASE_HI
+#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 
   0x0
+#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK   
   0xL
+//CP_IB1_BUFSZ
+#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 
   0x0
+#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK   
   0x000FL
 //CP_IB2_BASE_LO
 #define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 
   0x2
 #define CP_IB2_BASE_LO__IB2_BASE_LO_MASK   
   0xFFFCL
-- 
2.30.2

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Re: [PATCH 1/1] register refresh to add mmGC_CAC_INDEX_AUTO_INCR_EN

[Tom St Denis]

Hi,

This update doesn't match the gc_9_0_0 headers from the drm-next branch as
such cannot be made to umr.  You need to first update the kernel headers
and then we circle back to umr.

Tom

On Tue, Jan 26, 2021 at 12:43 AM  wrote:

> From: Guo Lei 
>
> sync form drm-next
>
> Signed-off-by: Guo Lei 
> ---
>  src/lib/ip/gfx90_bits.i | 7 ++-
>  src/lib/ip/gfx90_regs.i | 2 +-
>  2 files changed, 3 insertions(+), 6 deletions(-)
>
> diff --git a/src/lib/ip/gfx90_bits.i b/src/lib/ip/gfx90_bits.i
> index 6741947..8aabb8a 100644
> --- a/src/lib/ip/gfx90_bits.i
> +++ b/src/lib/ip/gfx90_bits.i
> @@ -8711,11 +8711,8 @@ static struct umr_bitfield mmGC_CAC_CTRL_2[] = {
>  { "CAC_SOFT_CTRL_ENABLE", 1, 1, &umr_bitfield_default },
>  { "UNUSED_0", 2, 31, &umr_bitfield_default },
>  };
> -static struct umr_bitfield mmGC_CAC_CGTT_CLK_CTRL[] = {
> -{ "ON_DELAY", 0, 3, &umr_bitfield_default },
> -{ "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
> -{ "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
> -{ "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
> +static struct umr_bitfield mmGC_CAC_INDEX_AUTO_INCR_EN[] = {
> +{ "GC_CAC_INDEX_AUTO_INCR_EN", 0, 0, &umr_bitfield_default },
>  };
>  static struct umr_bitfield mmGC_CAC_AGGR_LOWER[] = {
>  { "AGGR_31_0", 0, 31, &umr_bitfield_default },
> diff --git a/src/lib/ip/gfx90_regs.i b/src/lib/ip/gfx90_regs.i
> index 1342a66..a9ef9c6 100644
> --- a/src/lib/ip/gfx90_regs.i
> +++ b/src/lib/ip/gfx90_regs.i
> @@ -1418,7 +1418,7 @@
> { "mmDIDT_IND_DATA", REG_MMIO, 0x1281, 0, &mmDIDT_IND_DATA[0],
> sizeof(mmDIDT_IND_DATA)/sizeof(mmDIDT_IND_DATA[0]), 0, 0 },
> { "mmGC_CAC_CTRL_1", REG_MMIO, 0x1284, 0, &mmGC_CAC_CTRL_1[0],
> sizeof(mmGC_CAC_CTRL_1)/sizeof(mmGC_CAC_CTRL_1[0]), 0, 0 },
> { "mmGC_CAC_CTRL_2", REG_MMIO, 0x1285, 0, &mmGC_CAC_CTRL_2[0],
> sizeof(mmGC_CAC_CTRL_2)/sizeof(mmGC_CAC_CTRL_2[0]), 0, 0 },
> -   { "mmGC_CAC_CGTT_CLK_CTRL", REG_MMIO, 0x1286, 0,
> &mmGC_CAC_CGTT_CLK_CTRL[0],
> sizeof(mmGC_CAC_CGTT_CLK_CTRL)/sizeof(mmGC_CAC_CGTT_CLK_CTRL[0]), 0, 0 },
> +   { "mmGC_CAC_INDEX_AUTO_INCR_EN", REG_MMIO, 0x1286, 0,
> &mmGC_CAC_INDEX_AUTO_INCR_EN[0],
> sizeof(mmGC_CAC_INDEX_AUTO_INCR_EN)/sizeof(mmGC_CAC_INDEX_AUTO_INCR_EN[0]),
> 0, 0 },
> { "mmGC_CAC_AGGR_LOWER", REG_MMIO, 0x1287, 0,
> &mmGC_CAC_AGGR_LOWER[0],
> sizeof(mmGC_CAC_AGGR_LOWER)/sizeof(mmGC_CAC_AGGR_LOWER[0]), 0, 0 },
> { "mmGC_CAC_AGGR_UPPER", REG_MMIO, 0x1288, 0,
> &mmGC_CAC_AGGR_UPPER[0],
> sizeof(mmGC_CAC_AGGR_UPPER)/sizeof(mmGC_CAC_AGGR_UPPER[0]), 0, 0 },
> { "mmGC_CAC_SOFT_CTRL", REG_MMIO, 0x128d, 0,
> &mmGC_CAC_SOFT_CTRL[0],
> sizeof(mmGC_CAC_SOFT_CTRL)/sizeof(mmGC_CAC_SOFT_CTRL[0]), 0, 0 },
> --
> 2.17.1
>
>
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[PATCH 2/2] drm/amd/amdgpu: Move PWR_MISC_CNTL_STATUS to its own header

[Tom St Denis]

The register is part of the PWR block not the GC block.  Move to
its own header.

Signed-off-by: Tom St Denis 
---
 .../amd/include/asic_reg/gc/gc_9_1_offset.h   |  2 --
 .../amd/include/asic_reg/gc/gc_9_1_sh_mask.h  |  5 
 .../include/asic_reg/pwr/pwr_10_0_offset.h| 27 +
 .../include/asic_reg/pwr/pwr_10_0_sh_mask.h   | 30 +++
 4 files changed, 57 insertions(+), 7 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_offset.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_sh_mask.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
index ad61ffb0fd97..030e0020902b 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
@@ -159,8 +159,6 @@
 #define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX  
0
 #define mmCP_DE_DE_COUNT   
0x00c4
 #define mmCP_DE_DE_COUNT_BASE_IDX  
0
-#define mmPWR_MISC_CNTL_STATUS 
0x0183
-#define mmPWR_MISC_CNTL_STATUS_BASE_IDX
0
 #define mmCP_STALLED_STAT3 
0x019c
 #define mmCP_STALLED_STAT3_BASE_IDX
0
 #define mmCP_STALLED_STAT1 
0x019d
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
index 6cc63562fd55..13bfc2e6e16f 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
@@ -801,11 +801,6 @@
 //CP_DE_DE_COUNT
 #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT   
   0x0
 #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 
   0xL
-//PWR_MISC_CNTL_STATUS
-#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT   
   0x0
-#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 
   0x1
-#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 
   0x0001L
-#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK   
   0x0006L
 //CP_STALLED_STAT3
 #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT  
   0x0
 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 
   0x1
diff --git a/drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_offset.h
new file mode 100644
index ..e87c359ea1fe
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_offset.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _pwr_10_0_OFFSET_HEADER
+#define _pwr_10_0_OFFSET_HEADER
+
+#define mmPWR_MISC_CNTL_STATUS 
0x0183
+#define mmPWR_MISC_CNTL_STATUS_BASE_IDX
0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_sh_mask.h
new fi

[PATCH 1/2] drm/amd/amdgpu: Add missing SMUIO v12 register to headers

[Tom St Denis]

This register is needed by umr.

Signed-off-by: Tom St Denis 
---
 .../asic_reg/smuio/smuio_12_0_0_offset.h  | 27 ++
 .../asic_reg/smuio/smuio_12_0_0_sh_mask.h | 28 +++
 2 files changed, 55 insertions(+)
 create mode 100644 
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
 create mode 100644 
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
new file mode 100644
index ..327b4d09f66d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _smuio_12_0_0_OFFSET_HEADER
+#define _smuio_12_0_0_OFFSET_HEADER
+
+#define mmSMUIO_GFX_MISC_CNTL  
0x00c8
+#define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 
0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
new file mode 100644
index ..d815452cfd15
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _smuio_12_0_0_SH_MASK_HEADER
+#define _smuio_12_0_0_SH_MASK_HEADER
+
+//SMUIO_GFX_MISC_CNTL
+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK
   0x0006L
+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT  
   0x1
+
+#endif
-- 
2.25.1

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[PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion

[Tom St Denis]

The PWR block was merged into the SMUIO block by revision 12 so we add
that to the smuio_12_0_0 headers and then create a new smio_10_0_0 that
raven1 can use in conjunction with the pwr_10_0 headers.

Signed-off-by: Tom St Denis 
---
 .../asic_reg/smuio/smuio_10_0_0_offset.h  | 27 ++
 .../asic_reg/smuio/smuio_10_0_0_sh_mask.h | 28 +++
 .../asic_reg/smuio/smuio_12_0_0_offset.h  |  3 ++
 .../asic_reg/smuio/smuio_12_0_0_sh_mask.h |  5 
 4 files changed, 63 insertions(+)
 create mode 100644 
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_0_offset.h
 create mode 100644 
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_0_sh_mask.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_0_offset.h
new file mode 100644
index ..cad22fe8134b
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_0_offset.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _smuio_10_0_0_OFFSET_HEADER
+#define _smuio_10_0_0_OFFSET_HEADER
+
+#define mmSMUIO_GFX_MISC_CNTL  
0x00c8
+#define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 
0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_0_sh_mask.h
new file mode 100644
index ..f4cddb9a16b0
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_0_sh_mask.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _smuio_10_0_0_SH_MASK_HEADER
+#define _smuio_10_0_0_SH_MASK_HEADER
+
+//SMUIO_GFX_MISC_CNTL
+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK
   0x0006L
+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT  
   0x1
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
index 327b4d09f66d..9bf73284ad73 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
@@ -24,4 +24,7 @@
 #define mmSMUIO_GFX_MISC_CNTL  
0x00c8
 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 
0
 
+#define mmPWR_MISC_CNTL_STATUS 
0x0183

[PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)

[Tom St Denis]

The PWR block was merged into the SMUIO block by revision 12 so we add
that to the smuio_12_0_0 headers.

(v2): Drop nonsensical smuio_10_0_0 header

Signed-off-by: Tom St Denis 
---
 .../gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h | 3 +++
 .../drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h| 5 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
index 327b4d09f66d..9bf73284ad73 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
@@ -24,4 +24,7 @@
 #define mmSMUIO_GFX_MISC_CNTL  
0x00c8
 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 
0
 
+#define mmPWR_MISC_CNTL_STATUS 
0x0183
+#define mmPWR_MISC_CNTL_STATUS_BASE_IDX
1
+
 #endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
index d815452cfd15..26556fa3d054 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
@@ -24,5 +24,10 @@
 //SMUIO_GFX_MISC_CNTL
 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK
   0x0006L
 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT  
   0x1
+//PWR_MISC_CNTL_STATUS
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT   
   0x0
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 
   0x1
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 
   0x0001L
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK   
   0x0006L
 
 #endif
-- 
2.25.1

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Re: [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)

[Tom St Denis]

  


On 2020-03-25 3:28 p.m., Deucher,
  Alexander wrote:


  
  
  
[AMD Public Use]
  
  
  

  While you are at it, can you clean up the local defines of
  these registers in

  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

  drivers/gpu/drm/amd/powerplay/smu_v12_0.c

  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

  and verify that the appropriate offset is used for both Renoir
  and raven?
  



I can absolutely do that tomorrow.  I'd like to get my (v2) patch
  out though since it's gating an update to umr which an internal
  team is waiting on.


As for the PWR register through um how shall I say "sheer luck"
  it actually pans out fine.  The Renoir code paths use the vega10
  IP offsets and the PWR block's offset.  Segment 0 of the PWR block
  from vega10 matches segment 1 of the SMUIO (v12) block.  So on the
  face of it the CGCG code for renoir is "wrong" but because it's
  using the wrong IP table (which happens to have the right offsets)
  it works out alright.


int soc15_set_ip_blocks(struct amdgpu_device *adev)
  {
      /* Set IP register base before any HW register access */
      switch (adev->asic_type) {
      case CHIP_VEGA10:
      case CHIP_VEGA12:
      case CHIP_RAVEN:
      case CHIP_RENOIR:
          vega10_reg_base_init(adev);
          break;
  

Strictly speaking this is wrong since renoir has its own IP
  offset table but because it reuses a lot of the KGD
  implementations from earlier hardware (and the registers happen to
  be at the same locations) this works out fine.


Tom






  

  


  Alex


  


From:
            amd-gfx  on
behalf of Tom St Denis 
Sent: Wednesday, March 25, 2020 3:22 PM
To: amd-gfx@lists.freedesktop.org

Cc: StDenis, Tom 
Subject: [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR
Confusion (v2)
   


  The PWR block was merged into the
SMUIO block by revision 12 so we add
that to the smuio_12_0_0 headers.

(v2): Drop nonsensical smuio_10_0_0 header
        
Signed-off-by: Tom St Denis 
---
 .../gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h | 3 +++
 .../drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h    | 5 +
 2 files changed, 8 insertions(+)

diff --git
a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
index 327b4d09f66d..9bf73284ad73 100644
---
a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
+++
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
@@ -24,4 +24,7 @@
 #define
mmSMUIO_GFX_MISC_CNTL 
0x00c8
 #define
mmSMUIO_GFX_MISC_CNTL_BASE_IDX
0
 
+#define
mmPWR_MISC_CNTL_STATUS
0x0183
+#define
mmPWR_MISC_CNTL_STATUS_BASE_IDX   
1
+
 #endif
diff --git
a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
index d815452cfd15..26556fa3d054 100644
---
a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
+++
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
@@ -24,5 +24,10 @@
 //SMUIO_GFX_MISC_CNTL
 #define
SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK  
0x0006L
 #define
SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT
0x1
+//PWR_MISC_CNTL_STATUS
+#define
PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 
0x0
+#define
PWR

[PATCH] drm/amd/amdgpu: Include headers for PWR and SMUIO registers

[Tom St Denis]

Clean up the smu10, smu12, and gfx9 drivers to use headers for
registers instead of hardcoding in the C source files.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +++---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c |  9 ++---
 drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 12 +++-
 3 files changed, 12 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 7d98dc1d452e..619dc0f8071f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -50,18 +50,14 @@
 
 #include "gfx_v9_4.h"
 
+#include "asic_reg/pwr/pwr_10_0_offset.h"
+#include "asic_reg/pwr/pwr_10_0_sh_mask.h"
+
 #define GFX9_NUM_GFX_RINGS 1
 #define GFX9_MEC_HPD_SIZE 4096
 #define RLCG_UCODE_LOADING_START_ADDRESS 0x2000L
 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0xL
 
-#define mmPWR_MISC_CNTL_STATUS 0x0183
-#define mmPWR_MISC_CNTL_STATUS_BASE_IDX0
-#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT   0x0
-#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
-#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x0001L
-#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK   0x0006L
-
 #define mmGCEA_PROBE_MAP0x070c
 #define mmGCEA_PROBE_MAP_BASE_IDX   0
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 689072a312a7..69afdd24a0f0 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -36,6 +36,8 @@
 #include "power_state.h"
 #include "soc15_common.h"
 #include "smu10.h"
+#include "asic_reg/pwr/pwr_10_0_offset.h"
+#include "asic_reg/pwr/pwr_10_0_sh_mask.h"
 
 #define SMU10_MAX_DEEPSLEEP_DIVIDER_ID 5
 #define SMU10_MINIMUM_ENGINE_CLOCK 800   /* 8Mhz, the low boundary of 
engine clock allowed on this chip */
@@ -43,13 +45,6 @@
 #define SMU10_DISPCLK_BYPASS_THRESHOLD 1 /* 100Mhz */
 #define SMC_RAM_END 0x4
 
-#define mmPWR_MISC_CNTL_STATUS 0x0183
-#define mmPWR_MISC_CNTL_STATUS_BASE_IDX0
-#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT   0x0
-#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
-#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x0001L
-#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK   0x0006L
-
 static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic;
 
 
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index 169ebdad87b8..4fc68d4600e0 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -32,13 +32,15 @@
 
 #include "asic_reg/mp/mp_12_0_0_offset.h"
 #include "asic_reg/mp/mp_12_0_0_sh_mask.h"
+#include "asic_reg/smuio/smuio_12_0_0_offset.h"
+#include "asic_reg/smuio/smuio_12_0_0_sh_mask.h"
 
-#define smnMP1_FIRMWARE_FLAGS0x3010024
+// because some SMU12 based ASICs use older ip offset tables
+// we should undefine this register from the smuio12 header
+// to prevent confusion down the road
+#undef mmPWR_MISC_CNTL_STATUS
 
-#define mmSMUIO_GFX_MISC_CNTL0x00c8
-#define mmSMUIO_GFX_MISC_CNTL_BASE_IDX   0
-#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK  0x0006L
-#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT0x1
+#define smnMP1_FIRMWARE_FLAGS0x3010024
 
 int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
  uint16_t msg)
-- 
2.25.1

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[PATCH] drm/amd/amdgpu: add raven1 part to the gfxoff quirk list

[Tom St Denis]

On my raven1 system (rev c6) with VBIOS 113-RAVEN-114 GFXOFF is
not stable (resulting in large block tiling noise in some applications).

Disabling GFXOFF via the quirk list fixes the problems for me.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index fbd54d347d91..1573ac1f03b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1233,6 +1233,8 @@ static const struct amdgpu_gfxoff_quirk 
amdgpu_gfxoff_quirk_list[] = {
{ 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
/* https://bugzilla.kernel.org/show_bug.cgi?id=207171 */
{ 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 },
+   /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */
+   { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 },
{ 0, 0, 0, 0, 0 },
 };
 
-- 
2.26.2

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[PATCH] drm/amd/amdgpu: Add missing GRBM bits for GFX 10.1

[Tom St Denis]

Requested bits for UMR support

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
index e7db6f9f9c86..8b0b9a2a8fed 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
@@ -5599,6 +5599,7 @@
 #define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 
   0x8000L
 //GRBM_STATUS
 #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 
   0x0
+#define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT
   0x5
 #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 
   0x7
 #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 
   0x8
 #define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 
   0x9
@@ -5619,6 +5620,7 @@
 #define GRBM_STATUS__CB_BUSY__SHIFT
   0x1e
 #define GRBM_STATUS__GUI_ACTIVE__SHIFT 
   0x1f
 #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK   
   0x000FL
+#define GRBM_STATUS__RSMU_RQ_PENDING_MASK  
   0x0020L
 #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK   
   0x0080L
 #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK   
   0x0100L
 #define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK   
   0x0200L
@@ -5832,6 +5834,7 @@
 #define GRBM_READ_ERROR__READ_ERROR_MASK   
   0x8000L
 //GRBM_READ_ERROR2
 #define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT
   0x10
+#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT   
   0x11
 #define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT
   0x12
 #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT
   0x13
 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT
   0x14
@@ -5847,6 +5850,7 @@
 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT   
   0x1e
 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT   
   0x1f
 #define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK  
   0x0001L
+#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 
   0x0002L
 #define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK  
   0x0004L
 #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK  
   0x0008L
 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK  
   0x0010L
-- 
2.26.2

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Re: Fix a memory leak bug for umr tool.

[Tom St Denis]

Sorry I missed this.  I've applied it (with whitespace fixes) and pushed it
out to main yesterday.

Cheers,
Tom

On Thu, Aug 13, 2020 at 10:57 PM 张二东  wrote:

> Hi:
>The function umr_pm4_decode_ring_is_halted call umr_read_ring_data
>
> to get ringdata, umr_read_ring_data will alloc memory to store ring
>
> data and return the memory pointer to umr_pm4_decode_ring_is_halted, So
> the memory should be free in umr_pm4_decode_ring_is_halted.
>
> Thanks.
>
>
>
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Re: 0001-Fix-a-array-bound-overflow-bug-in-function-umr_clock

[Tom St Denis]

isn't a better fix to simply delete the line?  The print seems redundant to
me.

Tom

On Thu, Aug 27, 2020 at 9:27 AM 张二东  wrote:

>
>
>
>
> ___
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>
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Re: Re: 0001-Fix-a-array-bound-overflow-bug-in-function-umr_clock

[Tom St Denis]

Thanks, applied!

In future patches can you please add a Signed-off line (e.g. use "-s" with
git when forming the commit).

Tom

On Thu, Aug 27, 2020 at 9:43 PM 张二东  wrote:

> Yes, you are right. New patch is in attachment.
>
> thanks.
>
>
>
>
>
>
> 在 2020-08-28 01:14:02，"Tom St Denis"  写道：
>
> isn't a better fix to simply delete the line?  The print seems redundant
> to me.
>
> Tom
>
> On Thu, Aug 27, 2020 at 9:27 AM 张二东  wrote:
>
>>
>>
>>
>>
>> ___
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>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>
>
>
>
>
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[PATCH] drm/amd/amdgpu: add mmUVD_FW_STATUS register to uvd700

[Tom St Denis]

This register was requested for umr debugging support.

Signed-off-by: Tom St Denis 
---
 .../amd/include/asic_reg/uvd/uvd_7_0_offset.h |  3 +++
 .../include/asic_reg/uvd/uvd_7_0_sh_mask.h| 20 +++
 2 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h
index 07aceffb108a..524ba4421c17 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h
@@ -151,6 +151,8 @@
 #define mmUVD_LMI_CTRL2_BASE_IDX   
1
 #define mmUVD_MASTINT_EN   
0x0540
 #define mmUVD_MASTINT_EN_BASE_IDX  
1
+#define mmUVD_FW_STATUS
0x0557
+#define mmUVD_FW_STATUS_BASE_IDX   
1
 #define mmJPEG_CGC_CTRL
0x0565
 #define mmJPEG_CGC_CTRL_BASE_IDX   
1
 #define mmUVD_LMI_CTRL 
0x0566
@@ -219,4 +221,5 @@
 #define mmUVD_CONTEXT_ID2_BASE_IDX 
1
 
 
+
 #endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h
index b427f73bd536..919be1842bd5 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h
@@ -807,5 +807,25 @@
 #define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT
   0x0
 #define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK  
   0xL
 
+//UVD_FW_STATUS
+#define UVD_FW_STATUS__BUSY__SHIFT 
   0x0
+#define UVD_FW_STATUS__ACTIVE__SHIFT   
   0x1
+#define UVD_FW_STATUS__SEND_EFUSE_REQ__SHIFT   
   0x2
+#define UVD_FW_STATUS__DONE__SHIFT 
   0x8
+#define UVD_FW_STATUS__PASS__SHIFT 
   0x10
+#define UVD_FW_STATUS__FAIL__SHIFT 
   0x11
+#define UVD_FW_STATUS__INVALID_LEN__SHIFT  
   0x12
+#define UVD_FW_STATUS__INVALID_0_PADDING__SHIFT
   0x13
+#define UVD_FW_STATUS__INVALID_NONCE__SHIFT
   0x14
+#define UVD_FW_STATUS__BUSY_MASK   
   0x0001L
+#define UVD_FW_STATUS__ACTIVE_MASK 
   0x0002L
+#define UVD_FW_STATUS__SEND_EFUSE_REQ_MASK 
   0x0004L
+#define UVD_FW_STATUS__DONE_MASK   
   0x0100L
+#define UVD_FW_STATUS__PASS_MASK   
   0x0001L
+#define UVD_FW_STATUS__FAIL_MASK   
   0x0002L
+#define UVD_FW_STATUS__INVALID_LEN_MASK
   0x0004L
+#define UVD_FW_STATUS__INVALID_0_PADDING_MASK  
   0x0008L
+#define UVD_FW_STATUS__INVALID_NONCE_MASK  
   0x0010L
+
 
 #endif
-- 
2.26.2

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Re: [PATCH] Fix bug to get average GPU power

[Tom St Denis]

For whatever reason when I download this message and try to add it with
"git am" it says the patch is empty.

Can you attach the patch as an attachment please?

Thanks,
Tom

On Mon, Oct 26, 2020 at 11:29 PM Quan, Evan  wrote:

> [AMD Official Use Only - Internal Distribution Only]
>
> Reviewed-by: Evan Quan 
>
>
>
> *From:* amd-gfx  *On Behalf Of *Lei
> Guo
> *Sent:* Friday, October 23, 2020 11:03 AM
> *To:* amd-gfx@lists.freedesktop.org
> *Subject:* [PATCH] Fix bug to get average GPU power
>
>
>
> From 0277318fc1799d17878d9f407254773fc2bb964c Mon Sep 17 00:00:00 2001
>
> From: Guo Lei 
>
> Date: Fri, 16 Oct 2020 17:03:44 +0800
>
> Subject: [PATCH] Fix bug to get average GPU power
>
>
>
> Synchronize emu amd_pp_sensors with kgd_pp_interface.h
>
>
>
> Signed-off-by: Guo Lei 
>
> Change-Id: I531fa006ecdd1d42e589bbfe79a7d6699ae5b2b6
>
> ---
>
>  src/umr.h | 3 +++
>
>  1 file changed, 3 insertions(+)
>
>
>
> diff --git a/src/umr.h b/src/umr.h
>
> index c928fad..8c45f12 100644
>
> --- a/src/umr.h
>
> +++ b/src/umr.h
>
> @@ -79,6 +79,9 @@ enum amd_pp_sensors {
>
>   AMDGPU_PP_SENSOR_MEM_LOAD,
>
>   AMDGPU_PP_SENSOR_GFX_MCLK,
>
>   AMDGPU_PP_SENSOR_GPU_TEMP,
>
> +AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
>
> +AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
>
> +AMDGPU_PP_SENSOR_MEM_TEMP,
>
>   AMDGPU_PP_SENSOR_VCE_POWER,
>
>   AMDGPU_PP_SENSOR_UVD_POWER,
>
>   AMDGPU_PP_SENSOR_GPU_POWER,
>
> --
>
> 2.17.1
>
>
>
>
>
>
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[PATCH] drm/amd/amdgpu: Update mmio read/write access via debugfs

[Tom St Denis]

This patch adds support for wide MMIO addresses (upto 32-bits wide)
at the expense of dropping bank switching support for these addresses.

The patch also moves the PG guard bit to bit 59 which breaks compatibility
with older versions of umr but only if they are running the "--top" command.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 68 +++--
 1 file changed, 37 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 41ca13f0acd5..dd9df90a3bff 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -171,13 +171,14 @@ static void amdgpu_debugfs_autodump_init(struct 
amdgpu_device *adev)
  * Bit 62:  Indicates a GRBM bank switch is needed
  * Bit 61:  Indicates a SRBM bank switch is needed (implies bit 62 is
  * zero)
+ * Bit 60:  Indicates wide MMIO (32-bit address), disables other features
+ * Bit 59:  Indicates that the PM power gating lock should be held
+ * This is necessary to read registers that might be
+ * unreliable during a power gating transistion.
  * Bits 24..33: The SE or ME selector if needed
  * Bits 34..43: The SH (or SA) or PIPE selector if needed
  * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed
  *
- * Bit 23:  Indicates that the PM power gating lock should be held
- * This is necessary to read registers that might be
- * unreliable during a power gating transistion.
  *
  * The lower bits are the BYTE offset of the register to read.  This
  * allows reading multiple registers in a single call and having
@@ -189,45 +190,50 @@ static int  amdgpu_debugfs_process_reg_op(bool read, 
struct file *f,
struct amdgpu_device *adev = file_inode(f)->i_private;
ssize_t result = 0;
int r;
-   bool pm_pg_lock, use_bank, use_ring;
+   bool pm_pg_lock, use_bank, use_ring, use_wide;
unsigned instance_bank, sh_bank, se_bank, me, pipe, queue, vmid;
 
-   pm_pg_lock = use_bank = use_ring = false;
+   use_wide = pm_pg_lock = use_bank = use_ring = false;
instance_bank = sh_bank = se_bank = me = pipe = queue = vmid = 0;
 
if (size & 0x3 || *pos & 0x3 ||
((*pos & (1ULL << 62)) && (*pos & (1ULL << 61
return -EINVAL;
 
-   /* are we reading registers for which a PG lock is necessary? */
-   pm_pg_lock = (*pos >> 23) & 1;
-
-   if (*pos & (1ULL << 62)) {
-   se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
-   sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
-   instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
-
-   if (se_bank == 0x3FF)
-   se_bank = 0x;
-   if (sh_bank == 0x3FF)
-   sh_bank = 0x;
-   if (instance_bank == 0x3FF)
-   instance_bank = 0x;
-   use_bank = true;
-   } else if (*pos & (1ULL << 61)) {
-
-   me = (*pos & GENMASK_ULL(33, 24)) >> 24;
-   pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
-   queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
-   vmid = (*pos & GENMASK_ULL(58, 54)) >> 54;
-
-   use_ring = true;
+   /* is this a wide request? */
+   use_wide = (*pos >> 60) & 1;
+
+   if (!use_wide) {
+   /* are we reading registers for which a PG lock is necessary? */
+   pm_pg_lock = (*pos >> 59) & 1;
+
+   if (*pos & (1ULL << 62)) {
+   se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
+   sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
+   instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
+
+   if (se_bank == 0x3FF)
+   se_bank = 0x;
+   if (sh_bank == 0x3FF)
+   sh_bank = 0x;
+   if (instance_bank == 0x3FF)
+   instance_bank = 0x;
+   use_bank = true;
+   } else if (*pos & (1ULL << 61)) {
+   me = (*pos & GENMASK_ULL(33, 24)) >> 24;
+   pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
+   queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
+   vmid = (*pos & GENMASK_ULL(58, 54)) >> 54;
+   use_ring = true;
+   } else {
+   use_bank = use_ring = false;
+   }
+
+   *pos &= (1ULL << 22) - 1ULL;
} else {

Re: [PATCH] drm/amdgpu: improve MSI-X handling (v3)

[Tom St Denis]

Tested-by: Tom St Denis 

Cheers,
Tom

On Thu, Oct 3, 2019 at 1:30 PM Alex Deucher  wrote:

> Check the number of supported vectors and fall back to MSI if
> we return or error or 0 MSI-X vectors.
>
> v2: only allocate one vector.  We can't currently use more than
> one anyway.
>
> v3: install the irq on vector 0.
>
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 17 +
>  1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> index 50771b2757dc..6f3b03f6224f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> @@ -245,11 +245,19 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
> adev->irq.msi_enabled = false;
>
> if (amdgpu_msi_ok(adev)) {
> -   int nvec = pci_alloc_irq_vectors(adev->pdev, 1,
> pci_msix_vec_count(adev->pdev),
> -   PCI_IRQ_MSI | PCI_IRQ_MSIX);
> +   int nvec = pci_msix_vec_count(adev->pdev);
> +   unsigned int flags;
> +
> +   if (nvec <= 0) {
> +   flags = PCI_IRQ_MSI;
> +   } else {
> +   flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
> +   }
> +   /* we only need one vector */
> +   nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
> if (nvec > 0) {
> adev->irq.msi_enabled = true;
> -   dev_dbg(adev->dev, "amdgpu: using MSI.\n");
> +   dev_dbg(adev->dev, "amdgpu: using MSI/MSI-X.\n");
> }
> }
>
> @@ -272,7 +280,8 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
> INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);
>
> adev->irq.installed = true;
> -   r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
> +   /* Use vector 0 for MSI-X */
> +   r = drm_irq_install(adev->ddev, pci_irq_vector(adev->pdev, 0));
> if (r) {
> adev->irq.installed = false;
> if (!amdgpu_device_has_dc_support(adev))
> --
> 2.20.1
>
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[PATCH] drm/amd/amdgpu: add missing umc_6_1_2_sh_mask.h header file

[Tom St Denis]

Signed-off-by: Tom St Denis 
---
 .../include/asic_reg/umc/umc_6_1_2_sh_mask.h  | 91 +++
 1 file changed, 91 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_sh_mask.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_sh_mask.h
new file mode 100644
index ..7c3c6d405259
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_sh_mask.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _umc_6_1_1_SH_MASK_HEADER
+#define _umc_6_1_1_SH_MASK_HEADER
+
+//UMCCH0_0_EccErrCntSel_ARCT
+#define UMCCH0_0_EccErrCntSel_ARCT__EccErrCntCsSel__SHIFT  
0x0
+#define UMCCH0_0_EccErrCntSel_ARCT__EccErrInt__SHIFT   
0xc
+#define UMCCH0_0_EccErrCntSel_ARCT__EccErrCntEn__SHIFT 
0xf
+#define UMCCH0_0_EccErrCntSel_ARCT__EccErrCntCsSel_MASK
0x000FL
+#define UMCCH0_0_EccErrCntSel_ARCT__EccErrInt_MASK 
0x3000L
+#define UMCCH0_0_EccErrCntSel_ARCT__EccErrCntEn_MASK   
0x8000L
+//UMCCH0_0_EccErrCnt_ARCT
+#define UMCCH0_0_EccErrCnt_ARCT__EccErrCnt__SHIFT  
0x0
+#define UMCCH0_0_EccErrCnt_ARCT__EccErrCnt_MASK
0xL
+//MCA_UMC_UMC0_MCUMC_STATUST0_ARCT
+#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrorCode__SHIFT 
0x0
+#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrorCodeExt__SHIFT  
0x10
+#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV0__SHIFT   
0x16
+#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrCoreId__SHIFT 
0x20
+#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV1__SHIFT   
0x26
+#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Scrub__SHIFT 
0x28
+#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV2__SHIFT   
0x29
+#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Poison__SHIFT
0x2b
+#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Deferred__SHIFT  
0x2c
+#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__UECC__SHIFT  
0x2d
+#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__CECC__SHIFT  
0x2e
+#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV3__SHIFT   
0x2f
+#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Transparent__SHIFT   
0x34
+#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__SyndV__SHIFT 
0x35
+#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV4__SHIFT   
0x36
+#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__TCC__SHIFT   
0x37
+#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrCoreIdVal__SHIFT  
0x38
+#define MCA_UMC_UMC0_MCUMC_STATU

Re: [PATCH] drm/amd/amdgpu: add missing umc_6_1_2_sh_mask.h header file

[Tom St Denis]

note: I have since fixed the #ifndef/#define lines for when I eventually
push it out

On Thu, Jan 9, 2020 at 10:40 AM Tom St Denis  wrote:

> Signed-off-by: Tom St Denis 
> ---
>  .../include/asic_reg/umc/umc_6_1_2_sh_mask.h  | 91 +++
>  1 file changed, 91 insertions(+)
>  create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_sh_mask.h
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_sh_mask.h
> b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_sh_mask.h
> new file mode 100644
> index ..7c3c6d405259
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_2_sh_mask.h
> @@ -0,0 +1,91 @@
> +/*
> + * Copyright (C) 2020  Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without
> limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included
> + * in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
> + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT
> SHALL
> + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> LIABILITY, WHETHER IN
> + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> SOFTWARE.
> + */
> +#ifndef _umc_6_1_1_SH_MASK_HEADER
> +#define _umc_6_1_1_SH_MASK_HEADER
> +
> +//UMCCH0_0_EccErrCntSel_ARCT
> +#define UMCCH0_0_EccErrCntSel_ARCT__EccErrCntCsSel__SHIFT
>   0x0
> +#define UMCCH0_0_EccErrCntSel_ARCT__EccErrInt__SHIFT
>  0xc
> +#define UMCCH0_0_EccErrCntSel_ARCT__EccErrCntEn__SHIFT
>  0xf
> +#define UMCCH0_0_EccErrCntSel_ARCT__EccErrCntCsSel_MASK
>   0x000FL
> +#define UMCCH0_0_EccErrCntSel_ARCT__EccErrInt_MASK
>  0x3000L
> +#define UMCCH0_0_EccErrCntSel_ARCT__EccErrCntEn_MASK
>  0x8000L
> +//UMCCH0_0_EccErrCnt_ARCT
> +#define UMCCH0_0_EccErrCnt_ARCT__EccErrCnt__SHIFT
>   0x0
> +#define UMCCH0_0_EccErrCnt_ARCT__EccErrCnt_MASK
>   0xL
> +//MCA_UMC_UMC0_MCUMC_STATUST0_ARCT
> +#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrorCode__SHIFT
>  0x0
> +#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrorCodeExt__SHIFT
>   0x10
> +#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV0__SHIFT
>  0x16
> +#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__ErrCoreId__SHIFT
>  0x20
> +#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV1__SHIFT
>  0x26
> +#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Scrub__SHIFT
>  0x28
> +#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV2__SHIFT
>  0x29
> +#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Poison__SHIFT
>   0x2b
> +#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Deferred__SHIFT
>   0x2c
> +#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__UECC__SHIFT
>   0x2d
> +#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__CECC__SHIFT
>   0x2e
> +#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV3__SHIFT
>  0x2f
> +#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__Transparent__SHIFT
>  0x34
> +#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__SyndV__SHIFT
>  0x35
> +#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__RESERV4__SHIFT
>  0x36
> +#define MCA_UMC_UMC0_MCUMC_STATUST0_ARCT__TCC__SHIFT
>  0x37
> +#define MCA_UMC_UMC0_MC

Re: [PATCH] drm/amdgpu: revert "rework synchronization of VM updates v2"

[Tom St Denis]

Tested-by: Tom St Denis 

On 2020-01-15 9:34 a.m., Christian König wrote:

This reverts commit 75a0d3f5e4a8dc70c22842ec1fde2866f27f48b9.

It's causing VM page faults, revert until further investigated.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c  | 37 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h  |  3 ---
  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c|  7 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 38 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  |  4 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c  | 22 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 15 +---
  7 files changed, 61 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index c70bbdda078c..46c76e2e1281 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1403,49 +1403,28 @@ void amdgpu_bo_fence(struct amdgpu_bo *bo, struct 
dma_fence *fence,
  }
  
  /**

- * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences
+ * amdgpu_sync_wait_resv - Wait for BO reservation fences
   *
- * @adev: amdgpu device pointer
- * @resv: reservation object to sync to
- * @sync_mode: synchronization mode
+ * @bo: buffer object
   * @owner: fence owner
   * @intr: Whether the wait is interruptible
   *
- * Extract the fences from the reservation object and waits for them to finish.
- *
   * Returns:
   * 0 on success, errno otherwise.
   */
-int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
-enum amdgpu_sync_mode sync_mode, void *owner,
-bool intr)
+int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
  {
+   struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
struct amdgpu_sync sync;
int r;
  
  	amdgpu_sync_create(&sync);

-   amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner);
-   r = amdgpu_sync_wait(&sync, true);
+   amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv,
+AMDGPU_SYNC_NE_OWNER, owner);
+   r = amdgpu_sync_wait(&sync, intr);
amdgpu_sync_free(&sync);
-   return r;
-}
  
-/**

- * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv
- * @bo: buffer object to wait for
- * @owner: fence owner
- * @intr: Whether the wait is interruptible
- *
- * Wrapper to wait for fences in a BO.
- * Returns:
- * 0 on success, errno otherwise.
- */
-int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
-{
-   struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
-
-   return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv,
-   AMDGPU_SYNC_NE_OWNER, owner, intr);
+   return r;
  }
  
  /**

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 96d805889e8d..2eeafc77c9c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -283,9 +283,6 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
  int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
  void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
 bool shared);
-int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
-enum amdgpu_sync_mode sync_mode, void *owner,
-bool intr);
  int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr);
  u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
  int amdgpu_bo_validate(struct amdgpu_bo *bo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index 5816df9f8531..c124f64e7aae 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -240,6 +240,13 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, struct 
amdgpu_sync *sync,
owner != AMDGPU_FENCE_OWNER_UNDEFINED)
continue;
  
+		/* VM updates only sync with moves but not with user

+* command submissions or KFD evictions fences
+*/
+   if (fence_owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
+   owner == AMDGPU_FENCE_OWNER_VM)
+   continue;
+
/* Ignore fences depending on the sync mode */
switch (mode) {
case AMDGPU_SYNC_ALWAYS:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index a74cafa0e09e..5cb182231f5d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -797,7 +797,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
params.vm 

Re: [PATCH] drm/amdgpu: skip unallocated PDs/PTs while invalidating

[Tom St Denis]

I'll test it out in a minute.


Tom

On 2020-01-16 10:28 a.m., Christian König wrote:

We don't need to return an error in this case.

Signed-off-by: Christian König 
Fixes: d6932a4d86e4 drm/amdgpu: make sure to never allocate PDs/PTs for 
invalidations
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 ++--
  1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 5cb182231f5d..6cf407aab279 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1467,8 +1467,12 @@ static int amdgpu_vm_update_ptes(struct 
amdgpu_vm_update_params *params,
 * smaller than the address shift. Go to the next
 * child entry and try again.
 */
-   if (!amdgpu_vm_pt_descendant(adev, &cursor))
-   return -ENOENT;
+   if (!amdgpu_vm_pt_descendant(adev, &cursor)) {
+   if (flags & AMDGPU_PTE_VALID)
+   return -ENOENT;
+   else
+   amdgpu_vm_pt_next(adev, &cursor);
+   }
continue;
} else if (frag >= parent_shift) {
/* If the fragment size is even larger than the parent

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 4/4] drm/amdgpu: rework synchronization of VM updates v3

[Tom St Denis]

Just applied these now, trying them out will report back in ~20 mins.

On 2020-01-23 9:21 a.m., Christian König wrote:

If provided we only sync to the BOs reservation
object and no longer to the root PD.

v2: update comment, cleanup amdgpu_bo_sync_wait_resv
v3: use correct reservation object while clearing

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c  | 37 --
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h  |  3 +++
  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c|  7 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 41 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  |  4 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c  | 22 
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 15 +++
  7 files changed, 67 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 46c76e2e1281..c70bbdda078c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1403,30 +1403,51 @@ void amdgpu_bo_fence(struct amdgpu_bo *bo, struct 
dma_fence *fence,
  }
  
  /**

- * amdgpu_sync_wait_resv - Wait for BO reservation fences
+ * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences
   *
- * @bo: buffer object
+ * @adev: amdgpu device pointer
+ * @resv: reservation object to sync to
+ * @sync_mode: synchronization mode
   * @owner: fence owner
   * @intr: Whether the wait is interruptible
   *
+ * Extract the fences from the reservation object and waits for them to finish.
+ *
   * Returns:
   * 0 on success, errno otherwise.
   */
-int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
+int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
+enum amdgpu_sync_mode sync_mode, void *owner,
+bool intr)
  {
-   struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
struct amdgpu_sync sync;
int r;
  
  	amdgpu_sync_create(&sync);

-   amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv,
-AMDGPU_SYNC_NE_OWNER, owner);
-   r = amdgpu_sync_wait(&sync, intr);
+   amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner);
+   r = amdgpu_sync_wait(&sync, true);
amdgpu_sync_free(&sync);
-
return r;
  }
  
+/**

+ * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv
+ * @bo: buffer object to wait for
+ * @owner: fence owner
+ * @intr: Whether the wait is interruptible
+ *
+ * Wrapper to wait for fences in a BO.
+ * Returns:
+ * 0 on success, errno otherwise.
+ */
+int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
+{
+   struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+
+   return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv,
+   AMDGPU_SYNC_NE_OWNER, owner, intr);
+}
+
  /**
   * amdgpu_bo_gpu_offset - return GPU offset of bo
   * @bo:   amdgpu object for which we query the offset
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 2eeafc77c9c1..96d805889e8d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -283,6 +283,9 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
  int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
  void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
 bool shared);
+int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
+enum amdgpu_sync_mode sync_mode, void *owner,
+bool intr);
  int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr);
  u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
  int amdgpu_bo_validate(struct amdgpu_bo *bo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index 9f42032676da..b86392253696 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -249,13 +249,6 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, struct 
amdgpu_sync *sync,
owner != AMDGPU_FENCE_OWNER_UNDEFINED)
continue;
  
-		/* VM updates only sync with moves but not with user

-* command submissions or KFD evictions fences
-*/
-   if (fence_owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
-   owner == AMDGPU_FENCE_OWNER_VM)
-   continue;
-
/* Ignore fences depending on the sync mode */
switch (mode) {
case AMDGPU_SYNC_ALWAYS:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 0f79c17118bf..c268aa14381e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

Re: [PATCH 4/4] drm/amdgpu: rework synchronization of VM updates v3

[Tom St Denis]

On the tip of drm-next (as of this morning) I was still getting

[  983.891264] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)


type errors.  So I'm looking for that to stop.  At least LLVM was fixed 
so I can run a full run of piglit without gfx hangs.


Tom

On 2020-01-23 9:24 a.m., Christian König wrote:

Thanks, please give them a full round.

Took me a week to figure out that we accidentally pass in the 
reservation object as NULL for cleared BOs.


Thanks,
Christian.

Am 23.01.20 um 15:22 schrieb Tom St Denis:

Just applied these now, trying them out will report back in ~20 mins.

On 2020-01-23 9:21 a.m., Christian König wrote:

If provided we only sync to the BOs reservation
object and no longer to the root PD.

v2: update comment, cleanup amdgpu_bo_sync_wait_resv
v3: use correct reservation object while clearing

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c  | 37 
--

  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h  |  3 +++
  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c    |  7 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 41 
+

  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  |  4 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c  | 22 
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 15 +++
  7 files changed, 67 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

index 46c76e2e1281..c70bbdda078c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1403,30 +1403,51 @@ void amdgpu_bo_fence(struct amdgpu_bo *bo, 
struct dma_fence *fence,

  }
    /**
- * amdgpu_sync_wait_resv - Wait for BO reservation fences
+ * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences
   *
- * @bo: buffer object
+ * @adev: amdgpu device pointer
+ * @resv: reservation object to sync to
+ * @sync_mode: synchronization mode
   * @owner: fence owner
   * @intr: Whether the wait is interruptible
   *
+ * Extract the fences from the reservation object and waits for 
them to finish.

+ *
   * Returns:
   * 0 on success, errno otherwise.
   */
-int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
+int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct 
dma_resv *resv,

+ enum amdgpu_sync_mode sync_mode, void *owner,
+ bool intr)
  {
-    struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
  struct amdgpu_sync sync;
  int r;
    amdgpu_sync_create(&sync);
-    amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv,
- AMDGPU_SYNC_NE_OWNER, owner);
-    r = amdgpu_sync_wait(&sync, intr);
+    amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner);
+    r = amdgpu_sync_wait(&sync, true);
  amdgpu_sync_free(&sync);
-
  return r;
  }
  +/**
+ * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv
+ * @bo: buffer object to wait for
+ * @owner: fence owner
+ * @intr: Whether the wait is interruptible
+ *
+ * Wrapper to wait for fences in a BO.
+ * Returns:
+ * 0 on success, errno otherwise.
+ */
+int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
+{
+    struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+
+    return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv,
+    AMDGPU_SYNC_NE_OWNER, owner, intr);
+}
+
  /**
   * amdgpu_bo_gpu_offset - return GPU offset of bo
   * @bo:    amdgpu object for which we query the offset
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h

index 2eeafc77c9c1..96d805889e8d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -283,6 +283,9 @@ void amdgpu_bo_release_notify(struct 
ttm_buffer_object *bo);

  int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
  void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
   bool shared);
+int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct 
dma_resv *resv,

+ enum amdgpu_sync_mode sync_mode, void *owner,
+ bool intr);
  int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool 
intr);

  u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
  int amdgpu_bo_validate(struct amdgpu_bo *bo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c

index 9f42032676da..b86392253696 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -249,13 +249,6 @@ int amdgpu_sync_resv(struct amdgpu_device 
*adev, struct amdgpu_sync *sync,

  owner != AMDGPU_FENCE_OWNER_UNDEFINED)
  continue;
  -    /* VM updates only sync with moves but not with user
- * command submissions or KFD eviction

Re: [PATCH 4/4] drm/amdgpu: rework synchronization of VM updates v3

[Tom St Denis]

I've tested piglit, unigine-heaven, and video playback on my 
navi10/raven1 system.  All fine (as far as the kernel is concerned).  
You can add my



Tested-by: Tom St Denis 


Tom

On 2020-01-23 9:35 a.m., Christian König wrote:

That is fixed by patch #2 in this series.

Patch #4 is then re-applying the faulty synchronization cleanup.

Regards,
Christian.

Am 23.01.20 um 15:25 schrieb Tom St Denis:

On the tip of drm-next (as of this morning) I was still getting

[  983.891264] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)


type errors.  So I'm looking for that to stop.  At least LLVM was 
fixed so I can run a full run of piglit without gfx hangs.


Tom

On 2020-01-23 9:24 a.m., Christian König wrote:

Thanks, please give them a full round.

Took me a week to figure out that we accidentally pass in the 
reservation object as NULL for cleared BOs.


Thanks,
Christian.

Am 23.01.20 um 15:22 schrieb Tom St Denis:

Just applied these now, trying them out will report back in ~20 mins.

On 2020-01-23 9:21 a.m., Christian König wrote:

If provided we only sync to the BOs reservation
object and no longer to the root PD.

v2: update comment, cleanup amdgpu_bo_sync_wait_resv
v3: use correct reservation object while clearing

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c  | 37 
--

  drivers/gpu/drm/amd/amdgpu/amdgpu_object.h  |  3 +++
  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c    |  7 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 41 
+

  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  |  4 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c  | 22 
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 15 +++
  7 files changed, 67 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

index 46c76e2e1281..c70bbdda078c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1403,30 +1403,51 @@ void amdgpu_bo_fence(struct amdgpu_bo *bo, 
struct dma_fence *fence,

  }
    /**
- * amdgpu_sync_wait_resv - Wait for BO reservation fences
+ * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences
   *
- * @bo: buffer object
+ * @adev: amdgpu device pointer
+ * @resv: reservation object to sync to
+ * @sync_mode: synchronization mode
   * @owner: fence owner
   * @intr: Whether the wait is interruptible
   *
+ * Extract the fences from the reservation object and waits for 
them to finish.

+ *
   * Returns:
   * 0 on success, errno otherwise.
   */
-int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool 
intr)
+int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct 
dma_resv *resv,

+ enum amdgpu_sync_mode sync_mode, void *owner,
+ bool intr)
  {
-    struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
  struct amdgpu_sync sync;
  int r;
    amdgpu_sync_create(&sync);
-    amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv,
- AMDGPU_SYNC_NE_OWNER, owner);
-    r = amdgpu_sync_wait(&sync, intr);
+    amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner);
+    r = amdgpu_sync_wait(&sync, true);
  amdgpu_sync_free(&sync);
-
  return r;
  }
  +/**
+ * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv
+ * @bo: buffer object to wait for
+ * @owner: fence owner
+ * @intr: Whether the wait is interruptible
+ *
+ * Wrapper to wait for fences in a BO.
+ * Returns:
+ * 0 on success, errno otherwise.
+ */
+int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool 
intr)

+{
+    struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+
+    return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv,
+    AMDGPU_SYNC_NE_OWNER, owner, intr);
+}
+
  /**
   * amdgpu_bo_gpu_offset - return GPU offset of bo
   * @bo:    amdgpu object for which we query the offset
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h

index 2eeafc77c9c1..96d805889e8d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -283,6 +283,9 @@ void amdgpu_bo_release_notify(struct 
ttm_buffer_object *bo);

  int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
  void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
   bool shared);
+int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct 
dma_resv *resv,

+ enum amdgpu_sync_mode sync_mode, void *owner,
+ bool intr);
  int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool 
intr);

  u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
  int amdgpu_bo_validate(struct amdgpu_bo *bo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c

index 9f42032676da..b

Re: [PATCH 2/4] drm/amdgpu: allow higher level PD invalidations

[Tom St Denis]

Reverting this patch avoids the gmc_v8 errors (I previously sent kernel 
logs, here's one for convenience):


[  358.554335] [ cut here ]
[  358.554338] kernel BUG at drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c:725!
[  358.554351] invalid opcode:  [#1] SMP NOPTI
[  358.554354] CPU: 0 PID: 4551 Comm: Xwayland Not tainted 5.4.0-rc7+ #14
[  358.554355] Hardware name: System manufacturer System Product 
Name/TUF B350M-PLUS GAMING, BIOS 5220 09/12/2019

[  358.554452] RIP: 0010:gmc_v8_0_get_vm_pde+0x10/0x20 [amdgpu]
[  358.554455] Code: 31 f6 48 89 df e8 30 e9 ff ff e9 28 ff ff ff e8 16 
d6 21 f9 66 0f 1f 44 00 00 48 b8 ff 0f 00 00 00 ff ff ff 48 85 02 75 01 
c3 <0f> 0b 66 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 00 55 48 89 fd e8 c7

[  358.554456] RSP: 0018:a28142287a00 EFLAGS: 00010206
[  358.554458] RAX: ff000fff RBX:  RCX: 
a28142287a78
[  358.554459] RDX: a28142287a50 RSI: 0002 RDI: 
8b9be15e
[  358.554460] RBP: 0001 R08:  R09: 

[  358.554461] R10: 000f R11: 0406 R12: 
2030
[  358.554462] R13: 003efea0 R14: 00101c00 R15: 
a28142287af0
[  358.554464] FS:  7f180a48ba80() GS:8b9be6c0() 
knlGS:

[  358.554465] CS:  0010 DS:  ES:  CR0: 80050033
[  358.554466] CR2: 7f3de8f5dcc0 CR3: 0002170c8000 CR4: 
001406f0

[  358.554467] Call Trace:
[  358.554502]  amdgpu_vm_update_ptes+0x28a/0x7f0 [amdgpu]
[  358.554534]  ? amdgpu_sync_resv+0x34/0x190 [amdgpu]
[  358.554565]  amdgpu_vm_bo_update_mapping+0x12b/0x160 [amdgpu]
[  358.554596]  amdgpu_vm_bo_update+0x333/0x6a0 [amdgpu]
[  358.554626]  amdgpu_gem_va_ioctl+0x3c1/0x3e0 [amdgpu]
[  358.554658]  ? amdgpu_gem_va_map_flags+0x60/0x60 [amdgpu]
[  358.554663]  drm_ioctl_kernel+0xa5/0xf0
[  358.554665]  drm_ioctl+0x1df/0x366
[  358.554695]  ? amdgpu_gem_va_map_flags+0x60/0x60 [amdgpu]
[  358.554698]  ? __switch_to_asm+0x34/0x70
[  358.554699]  ? __switch_to_asm+0x40/0x70
[  358.554701]  ? __switch_to_asm+0x34/0x70
[  358.554702]  ? __switch_to_asm+0x40/0x70
[  358.554703]  ? __switch_to_asm+0x34/0x70
[  358.554704]  ? __switch_to_asm+0x40/0x70
[  358.554731]  amdgpu_drm_ioctl+0x44/0x80 [amdgpu]
[  358.554735]  do_vfs_ioctl+0x3f0/0x650
[  358.554737]  ? __schedule+0x28c/0x5a0
[  358.554738]  ksys_ioctl+0x59/0x90
[  358.554740]  __x64_sys_ioctl+0x11/0x20
[  358.554743]  do_syscall_64+0x43/0x110
[  358.554745]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[  358.554747] RIP: 0033:0x7f1809e6638b
[  358.554749] Code: 0f 1e fa 48 8b 05 fd 9a 0c 00 64 c7 00 26 00 00 00 
48 c7 c0 ff ff ff ff c3 66 0f 1f 44 00 00 f3 0f 1e fa b8 10 00 00 00 0f 
05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d cd 9a 0c 00 f7 d8 64 89 01 48
[  358.554750] RSP: 002b:7fffac20a638 EFLAGS: 0246 ORIG_RAX: 
0010
[  358.554751] RAX: ffda RBX: 7fffac20a690 RCX: 
7f1809e6638b
[  358.554752] RDX: 7fffac20a690 RSI: c0286448 RDI: 
000e
[  358.554753] RBP: c0286448 R08: 00010160 R09: 
000e
[  358.554754] R10: 00e0 R11: 0246 R12: 

[  358.554754] R13: 000e R14: 0001 R15: 
563d48bfd1f0

[  358.554756] Modules linked in: amdgpu gpu_sched ttm r8152 efivarfs
[  358.554790] ---[ end trace e0d54f6c49902356 ]---
[  358.554824] RIP: 0010:gmc_v8_0_get_vm_pde+0x10/0x20 [amdgpu]

(the gmc_v8 bug triggers regardless of whether I'm running piglit on my 
headless vega20 or directly on the carrizo).


However, with patch 2 of 4 reverted I then get:

[ 1471.338089] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.338647] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.339807] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.341699] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.342348] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.342474] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.342532] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.342583] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.342636] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.342694] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.342745] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.342796] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.343555] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.350270] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.350351] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.350395] [drm:amdgpu_gem_v

Re: [PATCH 2/4] drm/amdgpu: allow higher level PD invalidations

[Tom St Denis]

The offending PDE address is: "3eff60"

Which looks like it was sign extended into the "reserved" section 
between bits 40:58 (0x3fff) hence triggering the BUG() in the gmc_v8 driver.


Tom

On 2020-01-27 9:57 a.m., Tom St Denis wrote:
Reverting this patch avoids the gmc_v8 errors (I previously sent 
kernel logs, here's one for convenience):


[  358.554335] [ cut here ]
[  358.554338] kernel BUG at drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c:725!
[  358.554351] invalid opcode:  [#1] SMP NOPTI
[  358.554354] CPU: 0 PID: 4551 Comm: Xwayland Not tainted 5.4.0-rc7+ #14
[  358.554355] Hardware name: System manufacturer System Product 
Name/TUF B350M-PLUS GAMING, BIOS 5220 09/12/2019

[  358.554452] RIP: 0010:gmc_v8_0_get_vm_pde+0x10/0x20 [amdgpu]
[  358.554455] Code: 31 f6 48 89 df e8 30 e9 ff ff e9 28 ff ff ff e8 
16 d6 21 f9 66 0f 1f 44 00 00 48 b8 ff 0f 00 00 00 ff ff ff 48 85 02 
75 01 c3 <0f> 0b 66 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 00 55 48 89 fd 
e8 c7

[  358.554456] RSP: 0018:a28142287a00 EFLAGS: 00010206
[  358.554458] RAX: ff000fff RBX:  RCX: 
a28142287a78
[  358.554459] RDX: a28142287a50 RSI: 0002 RDI: 
8b9be15e
[  358.554460] RBP: 0001 R08:  R09: 

[  358.554461] R10: 000f R11: 0406 R12: 
2030
[  358.554462] R13: 003efea0 R14: 00101c00 R15: 
a28142287af0
[  358.554464] FS:  7f180a48ba80() GS:8b9be6c0() 
knlGS:

[  358.554465] CS:  0010 DS:  ES:  CR0: 80050033
[  358.554466] CR2: 7f3de8f5dcc0 CR3: 0002170c8000 CR4: 
001406f0

[  358.554467] Call Trace:
[  358.554502]  amdgpu_vm_update_ptes+0x28a/0x7f0 [amdgpu]
[  358.554534]  ? amdgpu_sync_resv+0x34/0x190 [amdgpu]
[  358.554565]  amdgpu_vm_bo_update_mapping+0x12b/0x160 [amdgpu]
[  358.554596]  amdgpu_vm_bo_update+0x333/0x6a0 [amdgpu]
[  358.554626]  amdgpu_gem_va_ioctl+0x3c1/0x3e0 [amdgpu]
[  358.554658]  ? amdgpu_gem_va_map_flags+0x60/0x60 [amdgpu]
[  358.554663]  drm_ioctl_kernel+0xa5/0xf0
[  358.554665]  drm_ioctl+0x1df/0x366
[  358.554695]  ? amdgpu_gem_va_map_flags+0x60/0x60 [amdgpu]
[  358.554698]  ? __switch_to_asm+0x34/0x70
[  358.554699]  ? __switch_to_asm+0x40/0x70
[  358.554701]  ? __switch_to_asm+0x34/0x70
[  358.554702]  ? __switch_to_asm+0x40/0x70
[  358.554703]  ? __switch_to_asm+0x34/0x70
[  358.554704]  ? __switch_to_asm+0x40/0x70
[  358.554731]  amdgpu_drm_ioctl+0x44/0x80 [amdgpu]
[  358.554735]  do_vfs_ioctl+0x3f0/0x650
[  358.554737]  ? __schedule+0x28c/0x5a0
[  358.554738]  ksys_ioctl+0x59/0x90
[  358.554740]  __x64_sys_ioctl+0x11/0x20
[  358.554743]  do_syscall_64+0x43/0x110
[  358.554745]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[  358.554747] RIP: 0033:0x7f1809e6638b
[  358.554749] Code: 0f 1e fa 48 8b 05 fd 9a 0c 00 64 c7 00 26 00 00 
00 48 c7 c0 ff ff ff ff c3 66 0f 1f 44 00 00 f3 0f 1e fa b8 10 00 00 
00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d cd 9a 0c 00 f7 d8 64 89 
01 48
[  358.554750] RSP: 002b:7fffac20a638 EFLAGS: 0246 ORIG_RAX: 
0010
[  358.554751] RAX: ffda RBX: 7fffac20a690 RCX: 
7f1809e6638b
[  358.554752] RDX: 7fffac20a690 RSI: c0286448 RDI: 
000e
[  358.554753] RBP: c0286448 R08: 00010160 R09: 
000e
[  358.554754] R10: 00e0 R11: 0246 R12: 

[  358.554754] R13: 000e R14: 0001 R15: 
563d48bfd1f0

[  358.554756] Modules linked in: amdgpu gpu_sched ttm r8152 efivarfs
[  358.554790] ---[ end trace e0d54f6c49902356 ]---
[  358.554824] RIP: 0010:gmc_v8_0_get_vm_pde+0x10/0x20 [amdgpu]

(the gmc_v8 bug triggers regardless of whether I'm running piglit on 
my headless vega20 or directly on the carrizo).


However, with patch 2 of 4 reverted I then get:

[ 1471.338089] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.338647] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.339807] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.341699] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.342348] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.342474] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.342532] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.342583] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.342636] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.342694] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.342745] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.342796] [drm:amdgpu_g

Re: [PATCH 2/4] drm/amdgpu: allow higher level PD invalidations

[Tom St Denis]

No problemo,  maybe we should split that BUG() statement to catch the 
two halves of the PDE address so next time it'll be more obvious.


For ref though your 4 patches have applied cleanly on top of drm-next 
every day and work fine on my navi10/raven1 system.  So it seems like 
just gmc8 is affected (I don't have any 6/7 hardware to test).


Tom


On 2020-01-27 2:14 p.m., Christian König wrote:
OH, thanks for that hint! I was staring at the code for a day now 
without having a clue what's going wrong.


Haven't realized that something could have been sign extended!

Probably going to figure it out by tomorrow now,
Christian.

Am 27.01.20 um 18:37 schrieb Tom St Denis:

The offending PDE address is: "3eff60"

Which looks like it was sign extended into the "reserved" section 
between bits 40:58 (0x3fff) hence triggering the BUG() in the gmc_v8 
driver.


Tom

On 2020-01-27 9:57 a.m., Tom St Denis wrote:
Reverting this patch avoids the gmc_v8 errors (I previously sent 
kernel logs, here's one for convenience):


[  358.554335] [ cut here ]
[  358.554338] kernel BUG at drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c:725!
[  358.554351] invalid opcode:  [#1] SMP NOPTI
[  358.554354] CPU: 0 PID: 4551 Comm: Xwayland Not tainted 
5.4.0-rc7+ #14
[  358.554355] Hardware name: System manufacturer System Product 
Name/TUF B350M-PLUS GAMING, BIOS 5220 09/12/2019

[  358.554452] RIP: 0010:gmc_v8_0_get_vm_pde+0x10/0x20 [amdgpu]
[  358.554455] Code: 31 f6 48 89 df e8 30 e9 ff ff e9 28 ff ff ff e8 
16 d6 21 f9 66 0f 1f 44 00 00 48 b8 ff 0f 00 00 00 ff ff ff 48 85 02 
75 01 c3 <0f> 0b 66 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 00 55 48 89 
fd e8 c7

[  358.554456] RSP: 0018:a28142287a00 EFLAGS: 00010206
[  358.554458] RAX: ff000fff RBX:  RCX: 
a28142287a78
[  358.554459] RDX: a28142287a50 RSI: 0002 RDI: 
8b9be15e
[  358.554460] RBP: 0001 R08:  R09: 

[  358.554461] R10: 000f R11: 0406 R12: 
2030
[  358.554462] R13: 003efea0 R14: 00101c00 R15: 
a28142287af0
[  358.554464] FS:  7f180a48ba80() GS:8b9be6c0() 
knlGS:

[  358.554465] CS:  0010 DS:  ES:  CR0: 80050033
[  358.554466] CR2: 7f3de8f5dcc0 CR3: 0002170c8000 CR4: 
001406f0

[  358.554467] Call Trace:
[  358.554502]  amdgpu_vm_update_ptes+0x28a/0x7f0 [amdgpu]
[  358.554534]  ? amdgpu_sync_resv+0x34/0x190 [amdgpu]
[  358.554565]  amdgpu_vm_bo_update_mapping+0x12b/0x160 [amdgpu]
[  358.554596]  amdgpu_vm_bo_update+0x333/0x6a0 [amdgpu]
[  358.554626]  amdgpu_gem_va_ioctl+0x3c1/0x3e0 [amdgpu]
[  358.554658]  ? amdgpu_gem_va_map_flags+0x60/0x60 [amdgpu]
[  358.554663]  drm_ioctl_kernel+0xa5/0xf0
[  358.554665]  drm_ioctl+0x1df/0x366
[  358.554695]  ? amdgpu_gem_va_map_flags+0x60/0x60 [amdgpu]
[  358.554698]  ? __switch_to_asm+0x34/0x70
[  358.554699]  ? __switch_to_asm+0x40/0x70
[  358.554701]  ? __switch_to_asm+0x34/0x70
[  358.554702]  ? __switch_to_asm+0x40/0x70
[  358.554703]  ? __switch_to_asm+0x34/0x70
[  358.554704]  ? __switch_to_asm+0x40/0x70
[  358.554731]  amdgpu_drm_ioctl+0x44/0x80 [amdgpu]
[  358.554735]  do_vfs_ioctl+0x3f0/0x650
[  358.554737]  ? __schedule+0x28c/0x5a0
[  358.554738]  ksys_ioctl+0x59/0x90
[  358.554740]  __x64_sys_ioctl+0x11/0x20
[  358.554743]  do_syscall_64+0x43/0x110
[  358.554745]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[  358.554747] RIP: 0033:0x7f1809e6638b
[  358.554749] Code: 0f 1e fa 48 8b 05 fd 9a 0c 00 64 c7 00 26 00 00 
00 48 c7 c0 ff ff ff ff c3 66 0f 1f 44 00 00 f3 0f 1e fa b8 10 00 00 
00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d cd 9a 0c 00 f7 d8 64 
89 01 48
[  358.554750] RSP: 002b:7fffac20a638 EFLAGS: 0246 ORIG_RAX: 
0010
[  358.554751] RAX: ffda RBX: 7fffac20a690 RCX: 
7f1809e6638b
[  358.554752] RDX: 7fffac20a690 RSI: c0286448 RDI: 
000e
[  358.554753] RBP: c0286448 R08: 00010160 R09: 
000e
[  358.554754] R10: 00e0 R11: 0246 R12: 

[  358.554754] R13: 000e R14: 0001 R15: 
563d48bfd1f0

[  358.554756] Modules linked in: amdgpu gpu_sched ttm r8152 efivarfs
[  358.554790] ---[ end trace e0d54f6c49902356 ]---
[  358.554824] RIP: 0010:gmc_v8_0_get_vm_pde+0x10/0x20 [amdgpu]

(the gmc_v8 bug triggers regardless of whether I'm running piglit on 
my headless vega20 or directly on the carrizo).


However, with patch 2 of 4 reverted I then get:

[ 1471.338089] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.338647] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.339807] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR* Couldn't 
update BO_VA (-2)
[ 1471.341699] [drm:amdgpu_gem_va_ioctl [amdgpu]] *ERROR

Re: [PATCH umr 1/2] rename mmBIF_BX_PF_MM_* for nbio 2.3

[Tom St Denis]

Hi,

Thanks for the patch however since the *.i files are machine generate 
I'd rather like to avoid patches like this (since they will need to be 
continually applied).


The ideal solution is to either patch src/lib/read_vram.c or to patch 
the kernel headers.  The kernel headers are also likewise machine 
generated so patching umr is probably the best.


I'll do this myself.

I will however apply patch #2 of the series.

Thanks,

Tom


On 2020-02-14 9:50 a.m., Xiaojie Yuan wrote:

Fixes following error while dumping gfx ring:

[BUG]: reg [mmMM_INDEX] not found on asic [navi10]
[BUG]: reg [mmMM_INDEX_HI] not found on asic [navi10]
[BUG]: reg [mmMM_DATA] not found on asic [navi10]
Cannot read from system memory: Operation not permitted
[ERROR]: Accessing system memory returned: -1
Cannot read from system memory: Bad address
[ERROR]: Accessing system memory returned: -1

Signed-off-by: Xiaojie Yuan 
---
  src/lib/ip/nbio230_bits.i | 6 +++---
  src/lib/ip/nbio230_regs.i | 6 +++---
  2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/lib/ip/nbio230_bits.i b/src/lib/ip/nbio230_bits.i
index 506ccba..fd5bad8 100644
--- a/src/lib/ip/nbio230_bits.i
+++ b/src/lib/ip/nbio230_bits.i
@@ -1,11 +1,11 @@
-static struct umr_bitfield mmBIF_BX_PF_MM_INDEX[] = {
+static struct umr_bitfield mmMM_INDEX[] = {
 { "MM_OFFSET", 0, 30, &umr_bitfield_default },
 { "MM_APER", 31, 31, &umr_bitfield_default },
  };
-static struct umr_bitfield mmBIF_BX_PF_MM_DATA[] = {
+static struct umr_bitfield mmMM_DATA[] = {
 { "MM_DATA", 0, 31, &umr_bitfield_default },
  };
-static struct umr_bitfield mmBIF_BX_PF_MM_INDEX_HI[] = {
+static struct umr_bitfield mmMM_INDEX_HI[] = {
 { "MM_OFFSET_HI", 0, 31, &umr_bitfield_default },
  };
  static struct umr_bitfield mmSYSHUB_INDEX_OVLP[] = {
diff --git a/src/lib/ip/nbio230_regs.i b/src/lib/ip/nbio230_regs.i
index ab57385..27a644b 100644
--- a/src/lib/ip/nbio230_regs.i
+++ b/src/lib/ip/nbio230_regs.i
@@ -1,6 +1,6 @@
-   { "mmBIF_BX_PF_MM_INDEX", REG_MMIO, 0x, 0, 
&mmBIF_BX_PF_MM_INDEX[0], sizeof(mmBIF_BX_PF_MM_INDEX)/sizeof(mmBIF_BX_PF_MM_INDEX[0]), 
0, 0 },
-   { "mmBIF_BX_PF_MM_DATA", REG_MMIO, 0x0001, 0, &mmBIF_BX_PF_MM_DATA[0], 
sizeof(mmBIF_BX_PF_MM_DATA)/sizeof(mmBIF_BX_PF_MM_DATA[0]), 0, 0 },
-   { "mmBIF_BX_PF_MM_INDEX_HI", REG_MMIO, 0x0006, 0, 
&mmBIF_BX_PF_MM_INDEX_HI[0], 
sizeof(mmBIF_BX_PF_MM_INDEX_HI)/sizeof(mmBIF_BX_PF_MM_INDEX_HI[0]), 0, 0 },
+   { "mmMM_INDEX", REG_MMIO, 0x, 0, &mmMM_INDEX[0], 
sizeof(mmMM_INDEX)/sizeof(mmMM_INDEX[0]), 0, 0 },
+   { "mmMM_DATA", REG_MMIO, 0x0001, 0, &mmMM_DATA[0], 
sizeof(mmMM_DATA)/sizeof(mmMM_DATA[0]), 0, 0 },
+   { "mmMM_INDEX_HI", REG_MMIO, 0x0006, 0, &mmMM_INDEX_HI[0], 
sizeof(mmMM_INDEX_HI)/sizeof(mmMM_INDEX_HI[0]), 0, 0 },
{ "mmSYSHUB_INDEX_OVLP", REG_MMIO, 0x0008, 0, &mmSYSHUB_INDEX_OVLP[0], 
sizeof(mmSYSHUB_INDEX_OVLP)/sizeof(mmSYSHUB_INDEX_OVLP[0]), 0, 0 },
{ "mmSYSHUB_DATA_OVLP", REG_MMIO, 0x0009, 0, &mmSYSHUB_DATA_OVLP[0], 
sizeof(mmSYSHUB_DATA_OVLP)/sizeof(mmSYSHUB_DATA_OVLP[0]), 0, 0 },
{ "mmPCIE_INDEX", REG_MMIO, 0x000c, 0, &mmPCIE_INDEX[0], 
sizeof(mmPCIE_INDEX)/sizeof(mmPCIE_INDEX[0]), 0, 0 },

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Re: [PATCH umr 1/2] rename mmBIF_BX_PF_MM_* for nbio 2.3

[Tom St Denis]

Both fixes pushed out to master (on gitlab)


Thanks again!


Tom

On 2020-02-14 10:06 a.m., Yuan, Xiaojie wrote:

Thanks Tom. I'm just publishing this quick fix so that I can continue my 
debugging with umr, and your solution sounds more reasonable ; )

BR,
Xiaojie


On Feb 14, 2020, at 10:55 PM, StDenis, Tom  wrote:

Hi,

Thanks for the patch however since the *.i files are machine generate I'd 
rather like to avoid patches like this (since they will need to be continually 
applied).

The ideal solution is to either patch src/lib/read_vram.c or to patch the 
kernel headers.  The kernel headers are also likewise machine generated so 
patching umr is probably the best.

I'll do this myself.

I will however apply patch #2 of the series.

Thanks,

Tom



On 2020-02-14 9:50 a.m., Xiaojie Yuan wrote:
Fixes following error while dumping gfx ring:

[BUG]: reg [mmMM_INDEX] not found on asic [navi10]
[BUG]: reg [mmMM_INDEX_HI] not found on asic [navi10]
[BUG]: reg [mmMM_DATA] not found on asic [navi10]
Cannot read from system memory: Operation not permitted
[ERROR]: Accessing system memory returned: -1
Cannot read from system memory: Bad address
[ERROR]: Accessing system memory returned: -1

Signed-off-by: Xiaojie Yuan 
---
  src/lib/ip/nbio230_bits.i | 6 +++---
  src/lib/ip/nbio230_regs.i | 6 +++---
  2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/lib/ip/nbio230_bits.i b/src/lib/ip/nbio230_bits.i
index 506ccba..fd5bad8 100644
--- a/src/lib/ip/nbio230_bits.i
+++ b/src/lib/ip/nbio230_bits.i
@@ -1,11 +1,11 @@
-static struct umr_bitfield mmBIF_BX_PF_MM_INDEX[] = {
+static struct umr_bitfield mmMM_INDEX[] = {
   { "MM_OFFSET", 0, 30, &umr_bitfield_default },
   { "MM_APER", 31, 31, &umr_bitfield_default },
  };
-static struct umr_bitfield mmBIF_BX_PF_MM_DATA[] = {
+static struct umr_bitfield mmMM_DATA[] = {
   { "MM_DATA", 0, 31, &umr_bitfield_default },
  };
-static struct umr_bitfield mmBIF_BX_PF_MM_INDEX_HI[] = {
+static struct umr_bitfield mmMM_INDEX_HI[] = {
   { "MM_OFFSET_HI", 0, 31, &umr_bitfield_default },
  };
  static struct umr_bitfield mmSYSHUB_INDEX_OVLP[] = {
diff --git a/src/lib/ip/nbio230_regs.i b/src/lib/ip/nbio230_regs.i
index ab57385..27a644b 100644
--- a/src/lib/ip/nbio230_regs.i
+++ b/src/lib/ip/nbio230_regs.i
@@ -1,6 +1,6 @@
-{ "mmBIF_BX_PF_MM_INDEX", REG_MMIO, 0x, 0, &mmBIF_BX_PF_MM_INDEX[0], 
sizeof(mmBIF_BX_PF_MM_INDEX)/sizeof(mmBIF_BX_PF_MM_INDEX[0]), 0, 0 },
-{ "mmBIF_BX_PF_MM_DATA", REG_MMIO, 0x0001, 0, &mmBIF_BX_PF_MM_DATA[0], 
sizeof(mmBIF_BX_PF_MM_DATA)/sizeof(mmBIF_BX_PF_MM_DATA[0]), 0, 0 },
-{ "mmBIF_BX_PF_MM_INDEX_HI", REG_MMIO, 0x0006, 0, 
&mmBIF_BX_PF_MM_INDEX_HI[0], 
sizeof(mmBIF_BX_PF_MM_INDEX_HI)/sizeof(mmBIF_BX_PF_MM_INDEX_HI[0]), 0, 0 },
+{ "mmMM_INDEX", REG_MMIO, 0x, 0, &mmMM_INDEX[0], 
sizeof(mmMM_INDEX)/sizeof(mmMM_INDEX[0]), 0, 0 },
+{ "mmMM_DATA", REG_MMIO, 0x0001, 0, &mmMM_DATA[0], 
sizeof(mmMM_DATA)/sizeof(mmMM_DATA[0]), 0, 0 },
+{ "mmMM_INDEX_HI", REG_MMIO, 0x0006, 0, &mmMM_INDEX_HI[0], 
sizeof(mmMM_INDEX_HI)/sizeof(mmMM_INDEX_HI[0]), 0, 0 },
  { "mmSYSHUB_INDEX_OVLP", REG_MMIO, 0x0008, 0, &mmSYSHUB_INDEX_OVLP[0], 
sizeof(mmSYSHUB_INDEX_OVLP)/sizeof(mmSYSHUB_INDEX_OVLP[0]), 0, 0 },
  { "mmSYSHUB_DATA_OVLP", REG_MMIO, 0x0009, 0, &mmSYSHUB_DATA_OVLP[0], 
sizeof(mmSYSHUB_DATA_OVLP)/sizeof(mmSYSHUB_DATA_OVLP[0]), 0, 0 },
  { "mmPCIE_INDEX", REG_MMIO, 0x000c, 0, &mmPCIE_INDEX[0], 
sizeof(mmPCIE_INDEX)/sizeof(mmPCIE_INDEX[0]), 0, 0 },

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Re: [PATCH umr] fix field names for INDIRECT_BUFFER_CONST/CIK for gfx9/gfx10

[Tom St Denis]

Yup, my bad.  We also need to fix the streaming version (line 432 of 
src/lib/umr_pm4_decode_opcodes.c).  Would you like to incorporate this 
into this patch?  Otherwise I can do it separately.


Thanks,

Tom

On 2020-02-19 6:26 a.m., Xiaojie Yuan wrote:

field names for INDIRECT_BUFFER_CONST/CIK of gfx9/gfx10 are the same.
fields like OFFLOAD_POLLING and VALID are defined in mec's
INDIRECT_BUFFER packet, so not applicable here.

Signed-off-by: Xiaojie Yuan 
---
  src/lib/ring_decode.c | 23 +++
  1 file changed, 7 insertions(+), 16 deletions(-)

diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c
index 250dfd7..fa44f27 100644
--- a/src/lib/ring_decode.c
+++ b/src/lib/ring_decode.c
@@ -617,22 +617,13 @@ static void print_decode_pm4_pkt3(struct umr_asic *asic, 
struct umr_ring_decoder
case 2: printf("IB_SIZE:%s%lu%s, VMID: 
%s%lu%s", BLUE, BITS(ib, 0, 20), RST, BLUE, BITS(ib, 24, 28), RST);
decoder->pm4.next_ib_state.ib_size = 
BITS(ib, 0, 20) * 4;
decoder->pm4.next_ib_state.ib_vmid = 
decoder->next_ib_info.vmid ? decoder->next_ib_info.vmid : BITS(ib, 24, 28);
-   if (decoder->pm4.cur_opcode == 0x33) {
-   if (asic->family >= FAMILY_NV) {
-   printf(", CHAIN: %s%u%s, 
PRE_ENA: %s%u%s, CACHE_POLICY: %s%u%s, PRE_RESUME: %s%u%s PRIV: %s%u%s",
-  BLUE, 
(unsigned)BITS(ib, 20, 21), RST,
-  BLUE, 
(unsigned)BITS(ib, 21, 22), RST,
-  BLUE, 
(unsigned)BITS(ib, 28, 30), RST,
-  BLUE, 
(unsigned)BITS(ib, 30, 31), RST,
-  BLUE, 
(unsigned)BITS(ib, 31, 32), RST);
-   } else if (asic->family >= 
FAMILY_AI) {
-   printf(", CHAIN: %s%u%s, 
OFFLOAD_POLLING: %s%u%s, VALID: %s%u%s, CACHE_POLICY: %s%u%s PRIV: %s%u%s",
-  BLUE, 
(unsigned)BITS(ib, 20, 21), RST,
-  BLUE, 
(unsigned)BITS(ib, 21, 22), RST,
-  BLUE, 
(unsigned)BITS(ib, 23, 24), RST,
-  BLUE, 
(unsigned)BITS(ib, 28, 30), RST,
-  BLUE, 
(unsigned)BITS(ib, 31, 32), RST);
-   }
+   if (asic->family >= FAMILY_AI) {
+   printf(", CHAIN: %s%u%s, PRE_ENA: 
%s%u%s, CACHE_POLICY: %s%u%s, PRE_RESUME: %s%u%s PRIV: %s%u%s",
+  BLUE, 
(unsigned)BITS(ib, 20, 21), RST,
+  BLUE, 
(unsigned)BITS(ib, 21, 22), RST,
+  BLUE, 
(unsigned)BITS(ib, 28, 30), RST,
+  BLUE, 
(unsigned)BITS(ib, 30, 31), RST,
+  BLUE, 
(unsigned)BITS(ib, 31, 32), RST);
}
if (!asic->options.no_follow_ib) {
if (umr_read_vram(asic, 
decoder->pm4.next_ib_state.ib_vmid,

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Re: [PATCH umr v2] fix field names for INDIRECT_BUFFER_CONST/CIK for gfx9/gfx10

[Tom St Denis]

Hmm it doesn't apply on top of the tip of master.  I'll just manually 
apply it.



Tom

On 2020-02-19 6:56 a.m., Xiaojie Yuan wrote:

field names for INDIRECT_BUFFER_CONST/CIK of gfx9/gfx10 are the same.
fields like OFFLOAD_POLLING and VALID are defined in mec's
INDIRECT_BUFFER packet, so not applicable here.

v2: fix umr_pm4_decode_opcodes.c as well

Signed-off-by: Xiaojie Yuan 
---
  src/lib/ring_decode.c| 23 +++
  src/lib/umr_pm4_decode_opcodes.c | 20 ++--
  2 files changed, 13 insertions(+), 30 deletions(-)

diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c
index 250dfd7..fa44f27 100644
--- a/src/lib/ring_decode.c
+++ b/src/lib/ring_decode.c
@@ -617,22 +617,13 @@ static void print_decode_pm4_pkt3(struct umr_asic *asic, 
struct umr_ring_decoder
case 2: printf("IB_SIZE:%s%lu%s, VMID: 
%s%lu%s", BLUE, BITS(ib, 0, 20), RST, BLUE, BITS(ib, 24, 28), RST);
decoder->pm4.next_ib_state.ib_size = 
BITS(ib, 0, 20) * 4;
decoder->pm4.next_ib_state.ib_vmid = 
decoder->next_ib_info.vmid ? decoder->next_ib_info.vmid : BITS(ib, 24, 28);
-   if (decoder->pm4.cur_opcode == 0x33) {
-   if (asic->family >= FAMILY_NV) {
-   printf(", CHAIN: %s%u%s, 
PRE_ENA: %s%u%s, CACHE_POLICY: %s%u%s, PRE_RESUME: %s%u%s PRIV: %s%u%s",
-  BLUE, 
(unsigned)BITS(ib, 20, 21), RST,
-  BLUE, 
(unsigned)BITS(ib, 21, 22), RST,
-  BLUE, 
(unsigned)BITS(ib, 28, 30), RST,
-  BLUE, 
(unsigned)BITS(ib, 30, 31), RST,
-  BLUE, 
(unsigned)BITS(ib, 31, 32), RST);
-   } else if (asic->family >= 
FAMILY_AI) {
-   printf(", CHAIN: %s%u%s, 
OFFLOAD_POLLING: %s%u%s, VALID: %s%u%s, CACHE_POLICY: %s%u%s PRIV: %s%u%s",
-  BLUE, 
(unsigned)BITS(ib, 20, 21), RST,
-  BLUE, 
(unsigned)BITS(ib, 21, 22), RST,
-  BLUE, 
(unsigned)BITS(ib, 23, 24), RST,
-  BLUE, 
(unsigned)BITS(ib, 28, 30), RST,
-  BLUE, 
(unsigned)BITS(ib, 31, 32), RST);
-   }
+   if (asic->family >= FAMILY_AI) {
+   printf(", CHAIN: %s%u%s, PRE_ENA: 
%s%u%s, CACHE_POLICY: %s%u%s, PRE_RESUME: %s%u%s PRIV: %s%u%s",
+  BLUE, 
(unsigned)BITS(ib, 20, 21), RST,
+  BLUE, 
(unsigned)BITS(ib, 21, 22), RST,
+  BLUE, 
(unsigned)BITS(ib, 28, 30), RST,
+  BLUE, 
(unsigned)BITS(ib, 30, 31), RST,
+  BLUE, 
(unsigned)BITS(ib, 31, 32), RST);
}
if (!asic->options.no_follow_ib) {
if (umr_read_vram(asic, 
decoder->pm4.next_ib_state.ib_vmid,
diff --git a/src/lib/umr_pm4_decode_opcodes.c b/src/lib/umr_pm4_decode_opcodes.c
index d7c1495..a823ecf 100644
--- a/src/lib/umr_pm4_decode_opcodes.c
+++ b/src/lib/umr_pm4_decode_opcodes.c
@@ -429,20 +429,12 @@ static void decode_pkt3(struct umr_asic *asic, struct 
umr_pm4_stream_decode_ui *
ui->add_field(ui, ib_addr + 8, ib_vmid, "IB_BASE_HI", 
BITS(stream->words[1], 0, 16), NULL, 16);
ui->add_field(ui, ib_addr + 12, ib_vmid, "IB_SIZE", 
BITS(stream->words[2], 0, 20), NULL, 10);
ui->add_field(ui, ib_addr + 12, ib_vmid, "IB_VMID", 
BITS(stream->words[2], 24, 28), NULL, 10);
-   if (stream->opcode == 0x33) {
-   if (asic->family >= FAMILY_NV) {
-   ui->add_field(ui, ib_addr + 12, ib_vmid, 
"CHAIN", BITS(stream->words[2], 20, 21), NULL, 10);
-   ui->add_field(ui, ib_addr + 12, ib_vmid, 
"PRE_ENA", BITS(stream->words[2], 21, 22), NULL, 10);
-   ui->add_field(ui, ib_addr + 12, ib_vmid, 
"CACHE_POLICY", BITS(stream->words[2], 2

Re: [PATCH] drm/amdgpu: add VM update fences back to the root PD

[Tom St Denis]

This doesn't apply on top of 7fd3b632e17e55c5ffd008f9f025754e7daa1b66 
which is the tip of drm-next



Tom

On 2020-02-19 9:20 a.m., Christian König wrote:

Add update fences to the root PD while mapping BOs.

Otherwise PDs freed during the mapping won't wait for
updates to finish and can cause corruptions.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 --
  1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index e7ab0c1e2793..dd63ccdbad2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -585,8 +585,8 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
  {
entry->priority = 0;
entry->tv.bo = &vm->root.base.bo->tbo;
-   /* One for TTM and one for the CS job */
-   entry->tv.num_shared = 2;
+   /* Two for VM updates, one for TTM and one for the CS job */
+   entry->tv.num_shared = 4;
entry->user_pages = NULL;
list_add(&entry->tv.head, validated);
  }
@@ -1619,6 +1619,16 @@ static int amdgpu_vm_bo_update_mapping(struct 
amdgpu_device *adev,
goto error_unlock;
}
  
+	if (flags & AMDGPU_PTE_VALID) {

+   struct amdgpu_bo *root = vm->root.base.bo;
+
+   if (!dma_fence_is_signaled(vm->last_direct))
+   amdgpu_bo_fence(root, vm->last_direct, true);
+
+   if (!dma_fence_is_signaled(vm->last_delayed))
+   amdgpu_bo_fence(root, vm->last_delayed, true);
+   }
+
r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
if (r)
goto error_unlock;

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[PATCH] drm/amd/amdgpu: disable GFXOFF around debugfs access to MMIO

[Tom St Denis]

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 7379910790c9..66f763300c96 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -169,6 +169,7 @@ static int  amdgpu_debugfs_process_reg_op(bool read, struct 
file *f,
if (pm_pg_lock)
mutex_lock(&adev->pm.mutex);
 
+   amdgpu_gfx_off_ctrl(adev, false);
while (size) {
uint32_t value;
 
@@ -192,6 +193,8 @@ static int  amdgpu_debugfs_process_reg_op(bool read, struct 
file *f,
}
 
 end:
+   amdgpu_gfx_off_ctrl(adev, true);
+
if (use_bank) {
amdgpu_gfx_select_se_sh(adev, 0x, 0x, 
0x);
mutex_unlock(&adev->grbm_idx_mutex);
-- 
2.24.1

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Re: [PATCH] drm/amdgpu: add VM update fences back to the root PD v2

[Tom St Denis]

I get this conflict on top of drm-next

++<<< HEAD
 +  r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
++===
+   if (flags & AMDGPU_PTE_VALID) {
+   struct amdgpu_bo *root = vm->root.base.bo;
+
+   if (!dma_fence_is_signaled(vm->last_direct))
+   amdgpu_bo_fence(root, vm->last_direct, true);
+
+   if (!dma_fence_is_signaled(vm->last_delayed))
+   amdgpu_bo_fence(root, vm->last_delayed, true);
+   }
+
+   r = vm->update_funcs->prepare(¶ms, owner, exclusive);
++>>> drm/amdgpu: add VM update fences back to the root PD v2

Should I keep the prepare call before or after your block?

Tom

On 2020-02-19 10:02 a.m., Christian König wrote:

Add update fences to the root PD while mapping BOs.

Otherwise PDs freed during the mapping won't wait for
updates to finish and can cause corruptions.

v2: rebased on drm-misc-next

Signed-off-by: Christian König 
Fixes: 90b69cdc5f159 drm/amdgpu: stop adding VM updates fences to the resv obj
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 --
  1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index d16231d6a790..ef73fa94f357 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -588,8 +588,8 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
  {
entry->priority = 0;
entry->tv.bo = &vm->root.base.bo->tbo;
-   /* One for TTM and one for the CS job */
-   entry->tv.num_shared = 2;
+   /* Two for VM updates, one for TTM and one for the CS job */
+   entry->tv.num_shared = 4;
entry->user_pages = NULL;
list_add(&entry->tv.head, validated);
  }
@@ -1591,6 +1591,16 @@ static int amdgpu_vm_bo_update_mapping(struct 
amdgpu_device *adev,
goto error_unlock;
}
  
+	if (flags & AMDGPU_PTE_VALID) {

+   struct amdgpu_bo *root = vm->root.base.bo;
+
+   if (!dma_fence_is_signaled(vm->last_direct))
+   amdgpu_bo_fence(root, vm->last_direct, true);
+
+   if (!dma_fence_is_signaled(vm->last_delayed))
+   amdgpu_bo_fence(root, vm->last_delayed, true);
+   }
+
r = vm->update_funcs->prepare(¶ms, owner, exclusive);
if (r)
goto error_unlock;

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Re: [PATCH] drm/amdgpu: add VM update fences back to the root PD v2

[Tom St Denis]

Ignore that my brain wasn't engaged in the process.  It's clear where 
you wanted the prepare call.



Tom

On 2020-02-19 10:06 a.m., Tom St Denis wrote:

I get this conflict on top of drm-next

++<<<<<<< HEAD
 +  r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
++===
+   if (flags & AMDGPU_PTE_VALID) {
+   struct amdgpu_bo *root = vm->root.base.bo;
+
+   if (!dma_fence_is_signaled(vm->last_direct))
+   amdgpu_bo_fence(root, vm->last_direct, true);
+
+   if (!dma_fence_is_signaled(vm->last_delayed))
+   amdgpu_bo_fence(root, vm->last_delayed, true);
+   }
+
+   r = vm->update_funcs->prepare(¶ms, owner, exclusive);
++>>>>>>> drm/amdgpu: add VM update fences back to the root PD v2

Should I keep the prepare call before or after your block?

Tom

On 2020-02-19 10:02 a.m., Christian König wrote:

Add update fences to the root PD while mapping BOs.

Otherwise PDs freed during the mapping won't wait for
updates to finish and can cause corruptions.

v2: rebased on drm-misc-next

Signed-off-by: Christian König 
Fixes: 90b69cdc5f159 drm/amdgpu: stop adding VM updates fences to the 
resv obj

---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 --
  1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

index d16231d6a790..ef73fa94f357 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -588,8 +588,8 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
  {
  entry->priority = 0;
  entry->tv.bo = &vm->root.base.bo->tbo;
-    /* One for TTM and one for the CS job */
-    entry->tv.num_shared = 2;
+    /* Two for VM updates, one for TTM and one for the CS job */
+    entry->tv.num_shared = 4;
  entry->user_pages = NULL;
  list_add(&entry->tv.head, validated);
  }
@@ -1591,6 +1591,16 @@ static int amdgpu_vm_bo_update_mapping(struct 
amdgpu_device *adev,

  goto error_unlock;
  }
  +    if (flags & AMDGPU_PTE_VALID) {
+    struct amdgpu_bo *root = vm->root.base.bo;
+
+    if (!dma_fence_is_signaled(vm->last_direct))
+    amdgpu_bo_fence(root, vm->last_direct, true);
+
+    if (!dma_fence_is_signaled(vm->last_delayed))
+    amdgpu_bo_fence(root, vm->last_delayed, true);
+    }
+
  r = vm->update_funcs->prepare(¶ms, owner, exclusive);
  if (r)
  goto error_unlock;

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Re: [PATCH] drm/amd/amdgpu: disable GFXOFF around debugfs access to MMIO

[Tom St Denis]

I got some messages after a while:

[  741.788564] Failed to send Message 8.
[  746.671509] Failed to send Message 8.
[  748.749673] Failed to send Message 2b.
[  759.245414] Failed to send Message 7.
[  763.216902] Failed to send Message 2a.

Are there any additional locks that should be held?  Because some 
commands like --top or --waves can do a lot of distinct read operations 
(causing a lot of enable/disable calls).


I'm going to sit on this a bit since I don't think the patch is ready 
for pushing out.



Tom

On 2020-02-19 10:07 a.m., Alex Deucher wrote:

On Wed, Feb 19, 2020 at 10:04 AM Tom St Denis  wrote:

Signed-off-by: Tom St Denis 

Please add a patch description.  With that fixed:
Reviewed-by: Alex Deucher 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 7379910790c9..66f763300c96 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -169,6 +169,7 @@ static int  amdgpu_debugfs_process_reg_op(bool read, struct 
file *f,
 if (pm_pg_lock)
 mutex_lock(&adev->pm.mutex);

+   amdgpu_gfx_off_ctrl(adev, false);
 while (size) {
 uint32_t value;

@@ -192,6 +193,8 @@ static int  amdgpu_debugfs_process_reg_op(bool read, struct 
file *f,
 }

  end:
+   amdgpu_gfx_off_ctrl(adev, true);
+
 if (use_bank) {
 amdgpu_gfx_select_se_sh(adev, 0x, 0x, 
0x);
 mutex_unlock(&adev->grbm_idx_mutex);
--
2.24.1

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Re: [PATCH] drm/amdgpu: add VM update fences back to the root PD v2

[Tom St Denis]

Doesn't build even with conflict resolved:

[root@raven linux]# make
  CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  DESCEND  objtool
  CHK include/generated/compile.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.o
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c: In function 
‘amdgpu_vm_bo_update_mapping’:
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1612:41: error: ‘owner’ 
undeclared (first use in this function)

 1612 |  r = vm->update_funcs->prepare(¶ms, owner, exclusive);
  | ^
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1612:41: note: each undeclared 
identifier is reported only once for each function it appears in
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1612:48: error: ‘exclusive’ 
undeclared (first use in this function)

 1612 |  r = vm->update_funcs->prepare(¶ms, owner, exclusive);
  |    ^
make[4]: *** [scripts/Makefile.build:266: 
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.o] Error 1
make[3]: *** [scripts/Makefile.build:509: drivers/gpu/drm/amd/amdgpu] 
Error 2

make[2]: *** [scripts/Makefile.build:509: drivers/gpu/drm] Error 2
make[1]: *** [scripts/Makefile.build:509: drivers/gpu] Error 2
make: *** [Makefile:1649: drivers] Error 2

Should I just move to drm-misc-next?

tom

On 2020-02-19 10:02 a.m., Christian König wrote:

Add update fences to the root PD while mapping BOs.

Otherwise PDs freed during the mapping won't wait for
updates to finish and can cause corruptions.

v2: rebased on drm-misc-next

Signed-off-by: Christian König 
Fixes: 90b69cdc5f159 drm/amdgpu: stop adding VM updates fences to the resv obj
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 --
  1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index d16231d6a790..ef73fa94f357 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -588,8 +588,8 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
  {
entry->priority = 0;
entry->tv.bo = &vm->root.base.bo->tbo;
-   /* One for TTM and one for the CS job */
-   entry->tv.num_shared = 2;
+   /* Two for VM updates, one for TTM and one for the CS job */
+   entry->tv.num_shared = 4;
entry->user_pages = NULL;
list_add(&entry->tv.head, validated);
  }
@@ -1591,6 +1591,16 @@ static int amdgpu_vm_bo_update_mapping(struct 
amdgpu_device *adev,
goto error_unlock;
}
  
+	if (flags & AMDGPU_PTE_VALID) {

+   struct amdgpu_bo *root = vm->root.base.bo;
+
+   if (!dma_fence_is_signaled(vm->last_direct))
+   amdgpu_bo_fence(root, vm->last_direct, true);
+
+   if (!dma_fence_is_signaled(vm->last_delayed))
+   amdgpu_bo_fence(root, vm->last_delayed, true);
+   }
+
r = vm->update_funcs->prepare(¶ms, owner, exclusive);
if (r)
goto error_unlock;

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Re: [PATCH] drm/amdgpu: add VM update fences back to the root PD v2

[Tom St Denis]

The tip of origin/amd-staging-drm-next for me is:

commit 7fd3b632e17e55c5ffd008f9f025754e7daa1b66
Refs: {origin/amd-staging-drm-next}, v5.4-rc7-2847-g7fd3b632e17e
Author: Monk Liu 
AuthorDate: Thu Feb 6 23:55:58 2020 +0800
Commit: Monk Liu 
CommitDate: Wed Feb 19 13:33:02 2020 +0800

    drm/amdgpu: fix colliding of preemption

    what:
    some os preemption path is messed up with world switch preemption

    fix:
    cleanup those logics so os preemption not mixed with world switch

    this patch is a general fix for issues comes from SRIOV MCBP, but
    there is still UMD side issues not resovlved yet, so this patch
    cannot fix all world switch bug.

    Signed-off-by: Monk Liu 
    Acked-by: Hawking Zhang 

Which I had fetched just an hour ago.

On 2020-02-19 10:41 a.m., Christian König wrote:

Well what branch are you trying to merge that into?

The conflict resolution should be simple, just keep the 
vm->update_funcs->prepare(...) line as it is in your branch.


When you get those errors then something went wrong in your rebase.

Christian.

Am 19.02.20 um 16:14 schrieb Tom St Denis:

Doesn't build even with conflict resolved:

[root@raven linux]# make
  CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  DESCEND  objtool
  CHK include/generated/compile.h
  CC [M]  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.o
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c: In function 
‘amdgpu_vm_bo_update_mapping’:
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1612:41: error: ‘owner’ 
undeclared (first use in this function)

 1612 |  r = vm->update_funcs->prepare(¶ms, owner, exclusive);
  | ^
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1612:41: note: each undeclared 
identifier is reported only once for each function it appears in
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1612:48: error: ‘exclusive’ 
undeclared (first use in this function)

 1612 |  r = vm->update_funcs->prepare(¶ms, owner, exclusive);
  |    ^
make[4]: *** [scripts/Makefile.build:266: 
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.o] Error 1
make[3]: *** [scripts/Makefile.build:509: drivers/gpu/drm/amd/amdgpu] 
Error 2

make[2]: *** [scripts/Makefile.build:509: drivers/gpu/drm] Error 2
make[1]: *** [scripts/Makefile.build:509: drivers/gpu] Error 2
make: *** [Makefile:1649: drivers] Error 2

Should I just move to drm-misc-next?

tom

On 2020-02-19 10:02 a.m., Christian König wrote:

Add update fences to the root PD while mapping BOs.

Otherwise PDs freed during the mapping won't wait for
updates to finish and can cause corruptions.

v2: rebased on drm-misc-next

Signed-off-by: Christian König 
Fixes: 90b69cdc5f159 drm/amdgpu: stop adding VM updates fences to 
the resv obj

---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 --
  1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

index d16231d6a790..ef73fa94f357 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -588,8 +588,8 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
  {
  entry->priority = 0;
  entry->tv.bo = &vm->root.base.bo->tbo;
-    /* One for TTM and one for the CS job */
-    entry->tv.num_shared = 2;
+    /* Two for VM updates, one for TTM and one for the CS job */
+    entry->tv.num_shared = 4;
  entry->user_pages = NULL;
  list_add(&entry->tv.head, validated);
  }
@@ -1591,6 +1591,16 @@ static int amdgpu_vm_bo_update_mapping(struct 
amdgpu_device *adev,

  goto error_unlock;
  }
  +    if (flags & AMDGPU_PTE_VALID) {
+    struct amdgpu_bo *root = vm->root.base.bo;
+
+    if (!dma_fence_is_signaled(vm->last_direct))
+    amdgpu_bo_fence(root, vm->last_direct, true);
+
+    if (!dma_fence_is_signaled(vm->last_delayed))
+    amdgpu_bo_fence(root, vm->last_delayed, true);
+    }
+
  r = vm->update_funcs->prepare(¶ms, owner, exclusive);
  if (r)
  goto error_unlock;



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Re: [PATCH] drm/amd/amdgpu: disable GFXOFF around debugfs access to MMIO

[Tom St Denis]

On 2020-02-21 9:34 a.m., Huang Rui wrote:

On Wed, Feb 19, 2020 at 10:09:46AM -0500, Tom St Denis wrote:

I got some messages after a while:

[  741.788564] Failed to send Message 8.
[  746.671509] Failed to send Message 8.
[  748.749673] Failed to send Message 2b.
[  759.245414] Failed to send Message 7.
[  763.216902] Failed to send Message 2a.

Are there any additional locks that should be held?  Because some commands
like --top or --waves can do a lot of distinct read operations (causing a
lot of enable/disable calls).

I'm going to sit on this a bit since I don't think the patch is ready for
pushing out.


How about use RREG32_KIQ and WREG32_KIQ?



For all register accesses (in the debugfs read/write method)? Can we use 
those on all ASICs?



Tom

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Re: 回复: [PATCH] drm/amd/amdgpu: disable GFXOFF around debugfs access to MMIO

[Tom St Denis]

Probably simpler just to do on/off and let userspace determine timing 
but other than that ya sounds good.



For things like umr's --top which runs indefinitely having a timer 
wouldn't work.  Similarly, --waves can take a long time depending on 
activity and the asic.



Tom



On 2020-02-21 11:04 a.m., Christian König wrote:

Ok how about this:

We add a debugfs file which when read returns the GFXOFF status and 
when written with a number disabled GFXOFF for N seconds with 0 
meaning forever.


Umr gets a new commandline option to write to that file before reading 
registers.


This way the user can still disable it if it causes any problems. Does 
that sounds like a plan?


Regards,
Christian.

Am 21.02.20 um 16:56 schrieb Deucher, Alexander:


[AMD Public Use]


Not at the moment.  But we could add a debugfs file which just wraps 
amdgpu_gfx_off_ctrl(). That said, maybe we just add a delay here or a 
use a timer to delay turning gfxoff back on again so that we aren't 
turning it on and off so rapidly.


Alex


*From:* Christian König 
*Sent:* Friday, February 21, 2020 10:43 AM
*To:* Deucher, Alexander ; Huang, Ray 
; Liu, Monk 
*Cc:* StDenis, Tom ; Alex Deucher 
; amd-gfx list 
*Subject:* Re: 回复: [PATCH] drm/amd/amdgpu: disable GFXOFF around 
debugfs access to MMIO

Do we have a way to disable GFXOFF on the fly?

If not maybe it would be a good idea to add a separate debugfs file 
to do this.


Christian.

Am 21.02.20 um 16:39 schrieb Deucher, Alexander:


[AMD Public Use]


If we are trying to debug a reproducible hang, probably best to just 
to disable gfxoff before messing with it to remove that as a 
factor.  Otherwise, the method included in this patch is the proper 
way to disable/enable GFXOFF dynamically.


Alex


*From:* amd-gfx  
<mailto:amd-gfx-boun...@lists.freedesktop.org> on behalf of 
Christian König  
<mailto:ckoenig.leichtzumer...@gmail.com>

*Sent:* Friday, February 21, 2020 10:27 AM
*To:* Huang, Ray  <mailto:ray.hu...@amd.com>; 
Liu, Monk  <mailto:monk@amd.com>
*Cc:* StDenis, Tom  
<mailto:tom.stde...@amd.com>; Alex Deucher  
<mailto:alexdeuc...@gmail.com>; amd-gfx list 
 <mailto:amd-gfx@lists.freedesktop.org>
*Subject:* Re: 回复: [PATCH] drm/amd/amdgpu: disable GFXOFF around 
debugfs access to MMIO

Am 21.02.20 um 16:23 schrieb Huang Rui:
> On Fri, Feb 21, 2020 at 11:18:07PM +0800, Liu, Monk wrote:
>> Better not use KIQ, because when you use debugfs to read register 
you usually hit a hang, and by that case KIQ probably already die
> If CP is busy, the gfx should be in "on" state at that time, we 
needn't use KIQ.


Yeah, but how do you detect that? Do we have a way to wake up the CP
without asking power management to do so?

Cause the register debug interface is meant to be used when the ASIC is
completed locked up. Sending messages to the SMU is not really going to
work in that situation.

Regards,
Christian.

>
> Thanks,
> Ray
>
>> -邮件原件-
>> 发件人: amd-gfx  
<mailto:amd-gfx-boun...@lists.freedesktop.org> 代表 Huang Rui

>> 发送时间: 2020年2月21日 22:34
>> 收件人: StDenis, Tom  
<mailto:tom.stde...@amd.com>
>> 抄送: Alex Deucher  
<mailto:alexdeuc...@gmail.com>; amd-gfx list 
 <mailto:amd-gfx@lists.freedesktop.org>
>> 主题: Re: [PATCH] drm/amd/amdgpu: disable GFXOFF around debugfs 
access to MMIO

>>
>> On Wed, Feb 19, 2020 at 10:09:46AM -0500, Tom St Denis wrote:
>>> I got some messages after a while:
>>>
>>> [  741.788564] Failed to send Message 8.
>>> [  746.671509] Failed to send Message 8.
>>> [  748.749673] Failed to send Message 2b.
>>> [  759.245414] Failed to send Message 7.
>>> [  763.216902] Failed to send Message 2a.
>>>
>>> Are there any additional locks that should be held?  Because some
>>> commands like --top or --waves can do a lot of distinct read
>>> operations (causing a lot of enable/disable calls).
>>>
>>> I'm going to sit on this a bit since I don't think the patch is 
ready

>>> for pushing out.
>>>
>> How about use RREG32_KIQ and WREG32_KIQ?
>>
>> Thanks,
>> Ray
>>
>>> Tom
>>>
>>> On 2020-02-19 10:07 a.m., Alex Deucher wrote:
>>>> On Wed, Feb 19, 2020 at 10:04 AM Tom St Denis 
 <mailto:tom.stde...@amd.com> wrote:
>>>>> Signed-off-by: Tom St Denis  
<mailto:tom.stde...@amd.com>

>>>> Please add a patch description.  With that fixed:
>>>> Reviewed-by: Alex Deucher  
<mailto:alexander.deuc...@amd.com>

>>>>
>>>>> ---
>>>>> drivers/gpu/drm/am

[PATCH] drm/amd/amdgpu: Add gfxoff debugfs entry

[Tom St Denis]

Write a 32-bit value of zero to disable GFXOFF and write a 32-bit
value of non-zero to enable GFXOFF.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 56 +
 1 file changed, 56 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 7379910790c9..3bb74056b9d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -842,6 +842,55 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, 
char __user *buf,
return result;
 }
 
+/**
+ * amdgpu_debugfs_regs_gfxoff_write - Enable/disable GFXOFF
+ *
+ * @f: open file handle
+ * @buf: User buffer to write data from
+ * @size: Number of bytes to write
+ * @pos:  Offset to seek to
+ *
+ * Write a 32-bit zero to disable or a 32-bit non-zero to enable
+ */
+static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user 
*buf,
+size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = file_inode(f)->i_private;
+   ssize_t result = 0;
+   int r;
+
+   if (size & 0x3 || *pos & 0x3)
+   return -EINVAL;
+
+   r = pm_runtime_get_sync(adev->ddev->dev);
+   if (r < 0)
+   return r;
+
+   while (size) {
+   uint32_t value;
+
+   r = get_user(value, (uint32_t *)buf);
+   if (r) {
+   pm_runtime_mark_last_busy(adev->ddev->dev);
+   pm_runtime_put_autosuspend(adev->ddev->dev);
+   return r;
+   }
+
+   amdgpu_gfx_off_ctrl(adev, value ? true : false);
+
+   result += 4;
+   buf += 4;
+   *pos += 4;
+   size -= 4;
+   }
+
+   pm_runtime_mark_last_busy(adev->ddev->dev);
+   pm_runtime_put_autosuspend(adev->ddev->dev);
+
+   return result;
+}
+
+
 static const struct file_operations amdgpu_debugfs_regs_fops = {
.owner = THIS_MODULE,
.read = amdgpu_debugfs_regs_read,
@@ -890,6 +939,11 @@ static const struct file_operations 
amdgpu_debugfs_gpr_fops = {
.llseek = default_llseek
 };
 
+static const struct file_operations amdgpu_debugfs_gfxoff_fops = {
+   .owner = THIS_MODULE,
+   .write = amdgpu_debugfs_gfxoff_write,
+};
+
 static const struct file_operations *debugfs_regs[] = {
&amdgpu_debugfs_regs_fops,
&amdgpu_debugfs_regs_didt_fops,
@@ -899,6 +953,7 @@ static const struct file_operations *debugfs_regs[] = {
&amdgpu_debugfs_sensors_fops,
&amdgpu_debugfs_wave_fops,
&amdgpu_debugfs_gpr_fops,
+   &amdgpu_debugfs_gfxoff_fops,
 };
 
 static const char *debugfs_regs_names[] = {
@@ -910,6 +965,7 @@ static const char *debugfs_regs_names[] = {
"amdgpu_sensors",
"amdgpu_wave",
"amdgpu_gpr",
+   "amdgpu_gfxoff",
 };
 
 /**
-- 
2.24.1

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Re: [PATCH 2/2] add DST_SEL=8 field name for WRITE_DATA packet

[Tom St Denis]

Thanks, both pushed out to the master branch.

Cheers,

Tom

On 2020-02-24 5:59 a.m., Xiaojie Yuan wrote:

otherwise we'll out-of-bound when accessing op_37_dst_sel[8]

Signed-off-by: Xiaojie Yuan 
---
  src/lib/ring_decode.c| 2 +-
  src/lib/umr_pm4_decode_opcodes.c | 2 +-
  2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c
index c5582f5..f26cf0d 100644
--- a/src/lib/ring_decode.c
+++ b/src/lib/ring_decode.c
@@ -465,7 +465,7 @@ static void print_decode_pm4_pkt3(struct umr_asic *asic, 
struct umr_ring_decoder
  {
static const char *op_3c_functions[] = { "true", "<", "<=", "==", "!=", ">=", 
">", "reserved" };
static const char *op_37_engines[] = { "ME", "PFP", "CE", "DE" };
-   static const char *op_37_dst_sel[] = { "mem-mapped reg", "memory sync", "TC/L2", "GDS", "reserved", 
"memory async", "reserved", "reserved" };
+   static const char *op_37_dst_sel[] = { "mem-mapped reg", "memory sync", "TC/L2", "GDS", "reserved", 
"memory async", "reserved", "reserved", "preemption meta memory" };
static const char *op_40_mem_sel[] = { "mem-mapped reg", "memory" "tc_l2", "gds", "perfcounters", "immediate data", 
"atomic return data", "gds_atomic_return_data_0", "gds_atomic_return_data1", "gpu_clock_count", "system_clock_count" };
static const char *op_84_cntr_sel[] = { "invalid", "ce", "cs", "ce and 
cs" };
static const char *op_7a_index_str[] = { "default", "prim_type", "index_type", "num_instance", 
"multi_vgt_param", "reserved", "reserved", "reserved" };
diff --git a/src/lib/umr_pm4_decode_opcodes.c b/src/lib/umr_pm4_decode_opcodes.c
index a823ecf..c4ad5ce 100644
--- a/src/lib/umr_pm4_decode_opcodes.c
+++ b/src/lib/umr_pm4_decode_opcodes.c
@@ -351,7 +351,7 @@ static void decode_pkt3(struct umr_asic *asic, struct 
umr_pm4_stream_decode_ui *
  {
static char *op_3c_functions[] = { "true", "<", "<=", "==", "!=", ">=", ">", 
"reserved" };
static char *op_37_engines[] = { "ME", "PFP", "CE", "DE" };
-   static char *op_37_dst_sel[] = { "mem-mapped reg", "memory sync", "TC/L2", "GDS", "reserved", 
"memory async", "reserved", "reserved" };
+   static char *op_37_dst_sel[] = { "mem-mapped reg", "memory sync", "TC/L2", "GDS", "reserved", "memory 
async", "reserved", "reserved", "preemption meta memory" };
static char *op_40_mem_sel[] = { "mem-mapped reg", "memory" "tc_l2", "gds", "perfcounters", "immediate data", 
"atomic return data", "gds_atomic_return_data_0", "gds_atomic_return_data1", "gpu_clock_count", "system_clock_count" };
static char *op_84_cntr_sel[] = { "invalid", "ce", "cs", "ce and cs" };
static char *op_7a_index_str[] = { "default", "prim_type", "index_type", "num_instance", 
"multi_vgt_param", "reserved", "reserved", "reserved" };

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Re: [PATCH] drm/amd/amdgpu: Add gfxoff debugfs entry

[Tom St Denis]

On 2020-02-21 1:59 p.m., Alex Deucher wrote:

On Fri, Feb 21, 2020 at 1:45 PM Tom St Denis  wrote:

Write a 32-bit value of zero to disable GFXOFF and write a 32-bit
value of non-zero to enable GFXOFF.

Signed-off-by: Tom St Denis 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 56 +
  1 file changed, 56 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 7379910790c9..3bb74056b9d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -842,6 +842,55 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, 
char __user *buf,
 return result;
  }

+/**
+ * amdgpu_debugfs_regs_gfxoff_write - Enable/disable GFXOFF
+ *
+ * @f: open file handle
+ * @buf: User buffer to write data from
+ * @size: Number of bytes to write
+ * @pos:  Offset to seek to
+ *
+ * Write a 32-bit zero to disable or a 32-bit non-zero to enable
+ */
+static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user 
*buf,
+size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = file_inode(f)->i_private;
+   ssize_t result = 0;
+   int r;
+
+   if (size & 0x3 || *pos & 0x3)
+   return -EINVAL;
+
+   r = pm_runtime_get_sync(adev->ddev->dev);

Not really directly related to this patch, but If you are using umr
for debugging, we should probably disable runtime pm, otherwise the
entire GPU may be powered down between accesses.  There is already an
interface to do that via the core kernel power subsystem in sysfs.
E.g.,
/sys/class/drm/card0/device/power/control
/sys/class/drm/card0/device/power/runtime_status
Something else to look at for umr.


We ran into something related to this for UVD/VCE access back in the 
day.  When powered down the MMIO registers are mirrored and accessible 
but while in transition they are not.  So we added a PG flag to the 
offset in the debugfs entry to flag when we need to take the pm mutex or 
not.







We don't store the state for when we dynamically turn it off like this
so if we get a GPU reset or a power management event (runtime pm or
S3), GFXOFF will be re-enabled at that point.  This is just for
debugging though so:
Acked-by: Alex Deucher 


Good to note.  Can I get a R-b from someone though so I can push this out?


Tom

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[PATCH] drm/amd/amdgpu: Fix GPR read from debugfs

[Tom St Denis]

The offset into the array was specified in bytes but should
be in terms of 32-bit words.  Also prevent large reads that
would also cause a buffer overread.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index c573edf02afc..e0f4ccd91fd4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -783,11 +783,11 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, 
char __user *buf,
ssize_t result = 0;
uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
 
-   if (size & 3 || *pos & 3)
+   if (size > 4096 || size & 3 || *pos & 3)
return -EINVAL;
 
/* decode offset */
-   offset = *pos & GENMASK_ULL(11, 0);
+   offset = (*pos & GENMASK_ULL(11, 0)) / 4;
se = (*pos & GENMASK_ULL(19, 12)) >> 12;
sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
-- 
2.24.1

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Re: [bug report] drm/amd/amdgpu: Add debugfs support for reading GPRs (v2)

[Tom St Denis]

Sorry about missing that.  A fix was sent to the list a few mins ago.  
It also highlighted a bug in umr's reading of trap registers.  It's a 
genuine two-fer!


Tom


On 2020-03-10 8:23 a.m., Dan Carpenter wrote:

On Tue, Nov 28, 2017 at 09:37:44AM -0500, Tom St Denis wrote:

On 28/11/17 09:29 AM, Dan Carpenter wrote:

Hello Tom St Denis,

The patch c5a60ce81b49: "drm/amd/amdgpu: Add debugfs support for
reading GPRs (v2)" from Dec 5, 2016, leads to the following static
checker warning:

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:3774 
amdgpu_debugfs_gpr_read()
error: buffer overflow 'data' 1024 <= 4095

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
3731  static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user 
*buf,
3732  size_t size, loff_t *pos)
3733  {
3734  struct amdgpu_device *adev = f->f_inode->i_private;
3735  int r;
3736  ssize_t result = 0;
3737  uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
3738
3739  if (size & 3 || *pos & 3)
3740  return -EINVAL;
3741
3742  /* decode offset */
3743  offset = *pos & GENMASK_ULL(11, 0);
  ^^
offset is set to 0-4095.

3744  se = (*pos & GENMASK_ULL(19, 12)) >> 12;
3745  sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
3746  cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
3747  wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
3748  simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
3749  thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
3750  bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
3751
3752  data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
   
data is a 1024 element array

3753  if (!data)
3754  return -ENOMEM;
3755
3756  /* switch to the specific se/sh/cu */
3757  mutex_lock(&adev->grbm_idx_mutex);
3758  amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3759
3760  if (bank == 0) {
3761  if (adev->gfx.funcs->read_wave_vgprs)
3762  adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, 
thread, offset, size>>2, data);
3763  } else {
3764  if (adev->gfx.funcs->read_wave_sgprs)
3765  adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, 
offset, size>>2, data);
3766  }
3767
3768  amdgpu_gfx_select_se_sh(adev, 0x, 0x, 
0x);
3769  mutex_unlock(&adev->grbm_idx_mutex);
3770
3771  while (size) {
3772  uint32_t value;
3773
3774  value = data[offset++];
  ^^
We're possibly reading beyond the end of the array.  Maybe we are
supposed to divide the offset /= sizeof(*data)?

Hi Dan,


umr only reads from offset zero but to be consistent I think yes the offset
should be /= 4 first since we ensure it's 4 byte aligned it's clearly a 4
byte offset.

Thanks for finding this, I'll craft up a patch shortly.


What ever happened with this?

regards,
dan carpenter


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Re: [PATCH] drm/amd/amdgpu: Fix GPR read from debugfs

[Tom St Denis]

On 2020-03-11 11:16 a.m., Alex Deucher wrote:

On Tue, Mar 10, 2020 at 8:53 AM Tom St Denis  wrote:

The offset into the array was specified in bytes but should
be in terms of 32-bit words.  Also prevent large reads that
would also cause a buffer overread.

Signed-off-by: Tom St Denis 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index c573edf02afc..e0f4ccd91fd4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -783,11 +783,11 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, 
char __user *buf,
 ssize_t result = 0;
 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;

-   if (size & 3 || *pos & 3)
+   if (size > 4096 || size & 3 || *pos & 3)

Is size in dwords as well?


Nope it's in bytes (as per the calling convention standards as well as 
later in the function we subtract 4 from it repeatedly).



Tom





Alex


 return -EINVAL;

 /* decode offset */
-   offset = *pos & GENMASK_ULL(11, 0);
+   offset = (*pos & GENMASK_ULL(11, 0)) / 4;
 se = (*pos & GENMASK_ULL(19, 12)) >> 12;
 sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
 cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
--
2.24.1

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[PATCH] drm/amd/amdgpu: Fix GPR read from debugfs (v2)

[Tom St Denis]

The offset into the array was specified in bytes but should
be in terms of 32-bit words.  Also prevent large reads that
would also cause a buffer overread.

v2:  Read from correct offset from internal storage buffer.

Signed-off-by: Tom St Denis 
Acked-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 00942afc4e13..02bb1be11ffe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -784,11 +784,11 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, 
char __user *buf,
ssize_t result = 0;
uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
 
-   if (size & 3 || *pos & 3)
+   if (size > 4096 || size & 3 || *pos & 3)
return -EINVAL;
 
/* decode offset */
-   offset = *pos & GENMASK_ULL(11, 0);
+   offset = (*pos & GENMASK_ULL(11, 0)) >> 2;
se = (*pos & GENMASK_ULL(19, 12)) >> 12;
sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
@@ -826,7 +826,7 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char 
__user *buf,
while (size) {
uint32_t value;
 
-   value = data[offset++];
+   value = data[result >> 2];
r = put_user(value, (uint32_t *)buf);
if (r) {
result = r;
-- 
2.24.1

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Re: [PATCH] drm/amd/amdgpu: Fix GPR read from debugfs

[Tom St Denis]

Hi Alex,

I sent out a v2 of the patch to the list that also addresses the fact we 
were reading from the wrong offset from the internal buffer.


This entry was really only tested with offset==0 which is why this 
didn't come up until now that people want those trap registers :-)


Tom

On 2020-03-11 11:16 a.m., Alex Deucher wrote:

On Tue, Mar 10, 2020 at 8:53 AM Tom St Denis  wrote:

The offset into the array was specified in bytes but should
be in terms of 32-bit words.  Also prevent large reads that
would also cause a buffer overread.

Signed-off-by: Tom St Denis 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index c573edf02afc..e0f4ccd91fd4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -783,11 +783,11 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, 
char __user *buf,
 ssize_t result = 0;
 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;

-   if (size & 3 || *pos & 3)
+   if (size > 4096 || size & 3 || *pos & 3)

Is size in dwords as well?

Alex


 return -EINVAL;

 /* decode offset */
-   offset = *pos & GENMASK_ULL(11, 0);
+   offset = (*pos & GENMASK_ULL(11, 0)) / 4;
 se = (*pos & GENMASK_ULL(19, 12)) >> 12;
 sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
 cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
--
2.24.1

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Remote UMR branch pushed out

[Tom St Denis]

Hello all,

I've pushed out the Remote UMR branch for people to take a look at before I
merge it into main in a couple of weeks.

https://gitlab.freedesktop.org/tomstdenis/umr/-/commit/712acea483cbbacb35cb1a431dea501f041065ff

This feature allows running the privileged side of umr elsewhere
(potentially on another host even) while preserving the common interface
people are used to.

Feel free to try it out.

Tom

[PATCH] drm/amd/amdgpu: Add SMUIO headers for 10.0.2

[Tom St Denis]

These were requested by a UMR user for debugging purposes.

Signed-off-by: Tom St Denis 
---
 .../asic_reg/smuio/smuio_10_0_2_offset.h  | 102 ++
 .../asic_reg/smuio/smuio_10_0_2_sh_mask.h | 184 ++
 2 files changed, 286 insertions(+)
 create mode 100644 
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_offset.h
 create mode 100644 
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_sh_mask.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_offset.h
new file mode 100644
index ..a4dd372c0541
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_10_0_2_offset.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2023  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _smuio_10_0_2_OFFSET_HEADER
+
+// addressBlock: smuio_smuio_misc_SmuSmuioDec
+// base address: 0x5a000
+#define mmSMUIO_MCM_CONFIG 
0x0023
+#define mmSMUIO_MCM_CONFIG_BASE_IDX
0
+#define mmIP_DISCOVERY_VERSION 
0x
+#define mmIP_DISCOVERY_VERSION_BASE_IDX
1
+#define mmIO_SMUIO_PINSTRAP
0x01b1
+#define mmIO_SMUIO_PINSTRAP_BASE_IDX   
1
+#define mmSCRATCH_REGISTER0
0x01b2
+#define mmSCRATCH_REGISTER0_BASE_IDX   
1
+#define mmSCRATCH_REGISTER1
0x01b3
+#define mmSCRATCH_REGISTER1_BASE_IDX   
1
+#define mmSCRATCH_REGISTER2
0x01b4
+#define mmSCRATCH_REGISTER2_BASE_IDX   
1
+#define mmSCRATCH_REGISTER3
0x01b5
+#define mmSCRATCH_REGISTER3_BASE_IDX   
1
+#define mmSCRATCH_REGISTER4
0x01b6
+#define mmSCRATCH_REGISTER4_BASE_IDX   
1
+#define mmSCRATCH_REGISTER5
0x01b7
+#define mmSCRATCH_REGISTER5_BASE_IDX   
1
+#define mmSCRATCH_REGISTER6
0x01b8
+#define mmSCRATCH_REGISTER6_BASE_IDX   
1
+#define mmSCRATCH_REGISTER7
0x01b9
+#define mmSCRATCH_REGISTER7_BASE_IDX   
1
+
+
+// addressBlock: smuio_smuio_reset_SmuSmuioDec
+// base address: 0x5a300
+#define mmSMUIO_MP_RESET_INTR  
0x00c1
+#define mmSMUIO_MP_RESET_INTR_BASE_IDX 
0
+#define mmSMUIO_SOC_HALT   
0x00c2
+#define mmSMUIO_SOC_HALT_BASE_IDX  
0
+#define m

[PATCH] drm/amd/amdgpu: Assign GART pages to AMD device mapping

[Tom St Denis]

This allows kernel mapped pages like the PDB and PTB to be
read via the iomem debugfs when there is no vram in the system.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index 73b8cca35bab..f0bdbcc7b1ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -121,6 +121,7 @@ int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev)
struct amdgpu_bo_param bp;
dma_addr_t dma_addr;
struct page *p;
+   unsigned long x;
int ret;
 
if (adev->gart.bo != NULL)
@@ -130,6 +131,11 @@ int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev)
if (!p)
return -ENOMEM;
 
+   /* assign pages to this device */
+   for (x = 0; x < (1UL << order); x++) {
+   p[x].mapping = adev->mman.bdev.dev_mapping;
+   }
+
/* If the hardware does not support UTCL2 snooping of the CPU caches
 * then set_memory_wc() could be used as a workaround to mark the pages
 * as write combine memory.
@@ -223,6 +229,7 @@ void amdgpu_gart_table_ram_free(struct amdgpu_device *adev)
unsigned int order = get_order(adev->gart.table_size);
struct sg_table *sg = adev->gart.bo->tbo.sg;
struct page *p;
+   unsigned long x;
int ret;
 
ret = amdgpu_bo_reserve(adev->gart.bo, false);
@@ -234,6 +241,9 @@ void amdgpu_gart_table_ram_free(struct amdgpu_device *adev)
sg_free_table(sg);
kfree(sg);
p = virt_to_page(adev->gart.ptr);
+   for (x = 0; x < (1UL << order); x++) {
+   p[x].mapping = NULL;
+   }
__free_pages(p, order);
 
adev->gart.ptr = NULL;
-- 
2.40.1

[PATCH] drm/amd/amdgpu: Widen mmio trace register address width

[Tom St Denis]

Support wider address spaces, make it 32-bit so we don't have to
revisit this for a while.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 067e5e683bb3..82c3d5aaca2b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -24,7 +24,7 @@ TRACE_EVENT(amdgpu_mm_rreg,
   __entry->reg = reg;
   __entry->value = value;
   ),
-   TP_printk("0x%04lx, 0x%04lx, 0x%08lx",
+   TP_printk("0x%04lx, 0x%08lx, 0x%08lx",
  (unsigned long)__entry->did,
  (unsigned long)__entry->reg,
  (unsigned long)__entry->value)
@@ -43,7 +43,7 @@ TRACE_EVENT(amdgpu_mm_wreg,
   __entry->reg = reg;
   __entry->value = value;
   ),
-   TP_printk("0x%04lx, 0x%04lx, 0x%08lx",
+   TP_printk("0x%04lx, 0x%08lx, 0x%08lx",
  (unsigned long)__entry->did,
  (unsigned long)__entry->reg,
  (unsigned long)__entry->value)
-- 
2.11.0

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[PATCH] drm/amd/amdgpu: De-numberify golden SI registers

[Tom St Denis]

Where possible replace numeric constants in the table
with their register names.

Compile tested + executed on a Tahiti.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/si.c | 975 
 1 file changed, 492 insertions(+), 483 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index c46b0159007d..9bf7afb2f74e 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -40,337 +40,343 @@
 #include "dce_v6_0.h"
 #include "si.h"
 #include "dce_virtual.h"
+#include "gca/gfx_6_0_d.h"
+#include "oss/oss_1_0_d.h"
+#include "gmc/gmc_6_0_d.h"
+#include "dce/dce_6_0_d.h"
+#include "uvd/uvd_4_0_d.h"
 
 static const u32 tahiti_golden_registers[] =
 {
-   0x17bc, 0x0030, 0x0011,
-   0x2684, 0x0001, 0x00018208,
-   0x260c, 0x, 0x,
-   0x260d, 0xf00f, 0x0400,
-   0x260e, 0x0002021c, 0x00020200,
-   0x031e, 0x0080, 0x,
+   mmAZALIA_SCLK_CONTROL, 0x0030, 0x0011,
+   mmCB_HW_CONTROL, 0x0001, 0x00018208,
+   mmDB_DEBUG, 0x, 0x,
+   mmDB_DEBUG2, 0xf00f, 0x0400,
+   mmDB_DEBUG3, 0x0002021c, 0x00020200,
+   mmDCI_CLK_CNTL, 0x0080, 0x,
0x340c, 0x00c0, 0x00800040,
0x360c, 0x00c0, 0x00800040,
-   0x16ec, 0x00f0, 0x0070,
-   0x16f0, 0x0020, 0x5010,
-   0x1c0c, 0x31000311, 0x0011,
-   0x09df, 0x0003, 0x07ff,
-   0x0903, 0x07ff, 0x,
-   0x2285, 0xf01f, 0x0007,
-   0x22c9, 0x, 0x00ff,
-   0x22c4, 0xff0f, 0x,
-   0xa293, 0x07ff, 0x4e00,
-   0xa0d4, 0x3f3f3fff, 0x2a00126a,
+   mmFBC_DEBUG_COMP, 0x00f0, 0x0070,
+   mmFBC_MISC, 0x0020, 0x5010,
+   mmDIG0_HDMI_CONTROL, 0x31000311, 0x0011,
+   mmMC_ARB_WTM_CNTL_RD, 0x0003, 0x07ff,
+   mmMC_XPB_P2P_BAR_CFG, 0x07ff, 0x,
+   mmPA_CL_ENHANCE, 0xf01f, 0x0007,
+   mmPA_SC_FORCE_EOV_MAX_CNTS, 0x, 0x00ff,
+   mmPA_SC_LINE_STIPPLE_STATE, 0xff0f, 0x,
+   mmPA_SC_MODE_CNTL_1, 0x07ff, 0x4e00,
+   mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x2a00126a,
0x000c, 0x, 0x0040,
0x000d, 0x0040, 0x4040,
-   0x2440, 0x07ff, 0x0300,
-   0x23a2, 0x01ff1f3f, 0x,
-   0x23a1, 0x01ff1f3f, 0x,
-   0x2418, 0x007f, 0x0020,
-   0x2542, 0x0001, 0x0001,
-   0x2b05, 0x0200, 0x02fb,
-   0x2b04, 0x, 0x543b,
-   0x2b03, 0x, 0xa9210876,
-   0x2234, 0x, 0x000fff40,
-   0x2235, 0x001f, 0x0010,
-   0x0504, 0x2000, 0x20fffed8,
-   0x0570, 0x000c0fc0, 0x000c0400,
-   0x052c, 0x0fff, 0x,
-   0x052d, 0x0fff, 0x0fff,
-   0x052e, 0x0fff, 0x0fff,
-   0x052f, 0x0fff, 0x0fff
+   mmSPI_CONFIG_CNTL, 0x07ff, 0x0300,
+   mmSQ_DED_CNT, 0x01ff1f3f, 0x,
+   mmSQ_SEC_CNT, 0x01ff1f3f, 0x,
+   mmSX_DEBUG_1, 0x007f, 0x0020,
+   mmTA_CNTL_AUX, 0x0001, 0x0001,
+   mmTCP_ADDR_CONFIG, 0x0200, 0x02fb,
+   mmTCP_CHAN_STEER_HI, 0x, 0x543b,
+   mmTCP_CHAN_STEER_LO, 0x, 0xa9210876,
+   mmVGT_FIFO_DEPTHS, 0x, 0x000fff40,
+   mmVGT_GS_VERTEX_REUSE, 0x001f, 0x0010,
+   mmVM_CONTEXT0_CNTL, 0x2000, 0x20fffed8,
+   mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
+   mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fff, 0x,
+   mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fff, 0x0fff,
+   mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fff, 0x0fff,
+   mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fff, 0x0fff,
 };
 
 static const u32 tahiti_golden_registers2[] =
 {
-   0x0319, 0x0001, 0x0001
+   mmMCIF_MEM_CONTROL, 0x0001, 0x0001,
 };
 
 static const u32 tahiti_golden_rlc_registers[] =
 {
-   0x263e, 0x, 0x12011003,
-   0x3109, 0x, 0x00601005,
+   mmGB_ADDR_CONFIG, 0x, 0x12011003,
+   mmRLC_LB_PARAMS, 0x, 0x00601005,
0x311f, 0x, 0x10104040,
0x3122, 0x, 0x010a,
-   0x30c5, 0x, 0x0800,
-   0x30c3, 0x, 0x80f4,
-   0x3d2a, 0x0008, 0x
+   mmRLC_LB_CNTR_MAX, 0x, 0x0800,
+   mmRLC_LB_CNTL, 0x, 0x80f4,
+   mmUVD_CGC_GATE, 0x0008, 0x,
 };
 
 static const u32 pitcairn_golden_registers[] =
 {
-   0x17bc, 0x0030, 0x0011,
-   0x2684, 0x0001, 0x00018208,
-   0x260c, 0x, 0x,
-   0x260d, 0xf00f, 0x0400,
-   0x260e, 0x0002021c, 0x00020200,
-   0x031e, 0x0080, 0x,
+   mmAZALIA_SCLK_

[PATCH] drm/amd/amdgpu: Add PCI info to gca_config debugfs

[Tom St Denis]

So we can determine which device the entry is before connecting
a display.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 28681286d57c..8640f9216d93 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2967,7 +2967,7 @@ static ssize_t amdgpu_debugfs_gca_config_read(struct file 
*f, char __user *buf,
return -ENOMEM;
 
/* version, increment each time something is added */
-   config[no_regs++] = 2;
+   config[no_regs++] = 3;
config[no_regs++] = adev->gfx.config.max_shader_engines;
config[no_regs++] = adev->gfx.config.max_tile_pipes;
config[no_regs++] = adev->gfx.config.max_cu_per_sh;
@@ -3001,6 +3001,12 @@ static ssize_t amdgpu_debugfs_gca_config_read(struct 
file *f, char __user *buf,
config[no_regs++] = adev->family;
config[no_regs++] = adev->external_rev_id;
 
+   /* rev==3 */
+   config[no_regs++] = adev->pdev->device;
+   config[no_regs++] = adev->pdev->revision;
+   config[no_regs++] = adev->pdev->subsystem_device;
+   config[no_regs++] = adev->pdev->subsystem_vendor;
+
while (size && (*pos < no_regs * 4)) {
uint32_t value;
 
-- 
2.11.0

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Add autodetect for libdrm to umr

[Tom St Denis]

While the cmake commits haven't been pushed yet I'd like to get feedback
on this patch which helps find the libdrm headers.

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[PATCH] autodetect path to libdrm

[Tom St Denis]

Signed-off-by: Tom St Denis 
---
 CMakeLists.txt  | 4 +++-
 src/lib/query_drm.c | 4 ++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index bef94fdba788..d2f393f0fa9b 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -25,6 +25,8 @@ include_directories(${CURSES_INCLUDE_DIRS})
 find_package(PCIAccess REQUIRED)
 include_directories(${PCIACCESS_INCLUDE_DIR})
 
+pkg_check_modules(DRM REQUIRED libdrm)
+
 set(REQUIRED_EXTERNAL_LIBS
   ${CURSES_LIBRARIES}
   ${PCIACCESS_LIBRARIES}
@@ -34,7 +36,7 @@ set(REQUIRED_EXTERNAL_LIBS
 set(CMAKE_POSITION_INDEPENDENT_CODE ON)
 
 # CFLAGS += -Wall -W -O2 -g3 -Isrc/ -DPIC -fPIC
-set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -W -O2 -g3")
+set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${DRM_CFLAGS} -Wall -W -O2 -g3")
 
 add_subdirectory(src)
 add_subdirectory(doc)
diff --git a/src/lib/query_drm.c b/src/lib/query_drm.c
index b9d80a8fc0c8..755c65fbc662 100644
--- a/src/lib/query_drm.c
+++ b/src/lib/query_drm.c
@@ -25,8 +25,8 @@
 #include "umr.h"
 #include 
 #include 
-#include 
-#include 
+#include 
+#include 
 
 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
 #define DRM_IOC_WRITE   _IOC_WRITE
-- 
2.11.0

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[PATCH] Autodetect libdrm path (v2)

[Tom St Denis]

(v2):  Use findLibDRM script instead of directly finding path

Signed-off-by: Tom St Denis 
---
 CMakeLists.txt |  3 +++
 cmake_modules/FindLibDRM.cmake | 35 +++
 src/lib/query_drm.c|  4 ++--
 3 files changed, 40 insertions(+), 2 deletions(-)
 create mode 100644 cmake_modules/FindLibDRM.cmake

diff --git a/CMakeLists.txt b/CMakeLists.txt
index bef94fdba788..ef78c97ad763 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -25,6 +25,9 @@ include_directories(${CURSES_INCLUDE_DIRS})
 find_package(PCIAccess REQUIRED)
 include_directories(${PCIACCESS_INCLUDE_DIR})
 
+find_package(LibDRM REQUIRED)
+include_directories(${LIBDRM_INCLUDE_DIR})
+
 set(REQUIRED_EXTERNAL_LIBS
   ${CURSES_LIBRARIES}
   ${PCIACCESS_LIBRARIES}
diff --git a/cmake_modules/FindLibDRM.cmake b/cmake_modules/FindLibDRM.cmake
new file mode 100644
index ..e840c4d1bfd0
--- /dev/null
+++ b/cmake_modules/FindLibDRM.cmake
@@ -0,0 +1,35 @@
+# Try to find libdrm
+#
+# Once done, this will define
+#
+# LIBDRM_FOUND
+# LIBDRM_INCLUDE_DIR
+# LIBDRM_LIBRARIES
+
+find_package(PkgConfig)
+
+pkg_check_modules(PC_LIBDRM QUIET libdrm)
+
+find_path(LIBDRM_INCLUDE_DIR NAMES amdgpu_drm.h
+HINTS
+${PC_LIBDRM_INCLUDEDIR}
+${PC_LIBDRM_INCLUDE_DIRS}
+/usr/include
+)
+
+find_library(LIBDRM_LIBRARY NAMES libdrm_amdgpu.so.1
+HINTS
+${PC_LIBDRM_LIBDIR}
+${PC_LIBDRM_LIBRARY_DIRS}
+/usr/lib64
+/usr/lib
+)
+
+SET(LIBDRM_LIBRARIES optimized ${LIBDRM_LIBRARY})
+
+include(FindPackageHandleStandardArgs)
+find_package_handle_standard_args(LIBDRM DEFAULT_MSG
+   LIBDRM_LIBRARIES LIBDRM_INCLUDE_DIR
+)
+
+mark_as_advanced(LIBDRM_INCLUDE_DIR LIBDRM_LIBRARIES)
diff --git a/src/lib/query_drm.c b/src/lib/query_drm.c
index b9d80a8fc0c8..755c65fbc662 100644
--- a/src/lib/query_drm.c
+++ b/src/lib/query_drm.c
@@ -25,8 +25,8 @@
 #include "umr.h"
 #include 
 #include 
-#include 
-#include 
+#include 
+#include 
 
 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
 #define DRM_IOC_WRITE   _IOC_WRITE
-- 
2.11.0

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[PATCH] Allow reading all of ring buffer and decode partial ranges

[Tom St Denis]

Fixes bug where say "-R gfx" would not actually dump the full
ring contents.

Adds feature where if you specify start and stop, e.g.,
"-R gfx[0:16]" will enable the decoder.

Signed-off-by: Tom St Denis 
---
 src/app/ring_read.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/app/ring_read.c b/src/app/ring_read.c
index 1726573a0396..970310b9bf52 100644
--- a/src/app/ring_read.c
+++ b/src/app/ring_read.c
@@ -78,13 +78,14 @@ void umr_read_ring(struct umr_asic *asic, char *ringpath)
drv_wptr = ring_data[2]<<2;
 
/* default to reading entire ring */
+   use_decoder = 0;
if (!from[0]) {
start = 0;
-   end   = ringsize;
+   end   = ringsize-4;
} else {
if (from[0] == '.' || !to[0] || to[0] == '.') {
/* start from 32 words prior to rptr up to wptr */
-   end = wptr+4;
+   end = wptr;
if (rptr < (31*4)) {
start = rptr - 31*4;
start += ringsize;
@@ -95,6 +96,7 @@ void umr_read_ring(struct umr_asic *asic, char *ringpath)
} else {
sscanf(from, "%"SCNu32, &start);
sscanf(to, "%"SCNu32, &end);
+   use_decoder = 1;
}
}
end %= ringsize;
@@ -106,8 +108,7 @@ void umr_read_ring(struct umr_asic *asic, char *ringpath)
asic->asicname, ringname, (unsigned long)wptr >> 2,
asic->asicname, ringname, (unsigned long)drv_wptr >> 2);
 
-   use_decoder = 0;
-   while (start != end) {
+   do {
value = ring_data[(start+12)>>2];
printf("%s.%s.ring[%4lu] == 0x%08lx   ", asic->asicname, 
ringname, (unsigned long)start >> 2, (unsigned long)value);
if (enable_decoder && start == rptr && start != wptr) {
@@ -123,7 +124,7 @@ void umr_read_ring(struct umr_asic *asic, char *ringpath)
printf("\n");
start += 4;
start %= ringsize;
-   }
+   } while (start != ((end + 4) % ringsize));
free(ring_data);
printf("\n");
 
-- 
2.11.0

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Re: [PATCH] Autodetect libdrm path (v2)

[Tom St Denis]

On 07/02/17 06:02 AM, Emil Velikov wrote:

On 6 February 2017 at 22:39, StDenis, Tom  wrote:


Apparently I missed the bottom of your reply (all of the clients I have 
outlook/gmail do top post only ...)

Both Outlook and Gmail can do inline replies and plain text. There
might be some magic required for the former though :-\
I would kindly suggest using inline/text when possible.


You'll be pleased to note I discovered (at some point) that AMD has 
re-enabled imap support and I can now use a more sensible client...


:-)


Ironically, I had the pkg_check originally but was told that's a faux-pas.


It's a common misconception, influenced by the sheer volume of copy/paste :-)



Unless this is breaking for actual users though it's not really a priority to 
bikeshed the build system of a 30 file project that is meant to work only on 
developer machines who are likely building for themselves


Up-to you really. FWIW using cmake/autoconf/etc. is a huge overkill.
The original makefile was missing a few things* worth 10-20 lines of
code while being noticeably smaller, quicker and easier to read ;-)


To be honest unless the cmake system gets in the way I'm happy if it 
makes others happy.  It's not easy to say the project is "open" if we 
NAK any and all harmless commits that the users advocate for.


The official stance from AMD (specifically the team I work for) is if 
cmake gets in the way of AMD work we will nuke the cmake system and go 
back to gmake (with pkg-config shell calls to get paths).


Personally I'm not a big fan of overly complicated config/build systems 
but since I don't do package building/etc for a living I'll defer to the 
opinions of others within reason.



Also umr can read/write registers via pci access without amdgpu loaded (handy 
if amdgpu fails to init properly).


Must have missed this part. Thanks for the correction.


Yup, you can force device + direct access, e.g.

umr -O use_pci -f fiji -r *.uvd5.mmFOO

Which is handy like I said if the module init fails.  Developers also 
use it in NPI bringup to poke things.


Cheers,
Tom
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Re: Staging kernel failing to build on 32bit

[Tom St Denis]

On 08/02/17 11:53 AM, Jeremy Newton wrote:

Hi,

Heads up to whoever is using or developing for the following kernel branch:

https://cgit.freedesktop.org/~agd5f/linux/tree/?h=amd-staging-4.9

It seems like a recent commit has caused 32bit builds to fail. I haven't
been able to look into it myself or do a bisect, but it seems like it
was something committed between Jan 25th (d0c15b8) and Feb 2nd (99eb22d)
caused it.

Here's the error output:

ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
Makefile:1200: recipe for target 'modules' failed
make[1]: *** [__modpost] Error 1
make: *** [modules] Error 2

After a quick glance, it seems similar to a previous kernel
commit: 
https://cgit.freedesktop.org/~agd5f/linux/commit/?id=1f827f5138292a6124430cdd37bcb68f30c05467


just a shot in the dark, but it could be caused by this commit:
https://cgit.freedesktop.org/~agd5f/linux/commit/?h=amd-staging-4.9&id=7adb2bbcdf7259533c5afc95c4a788b59bb59306

As it's the only one I see with 64 bit division in it. As I said, shot
in the dark here.


Thanks.  We have a patch in our internal stg-4.9 tree for this.  It 
should be promoted externally soonish.


Cheers,
Tom
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[PATCH] drm/amd/amdgpu: Update read_sensor calls to have size parameter

[Tom St Denis]

This update allows sensors to return more than 1 value and
indicates to the caller how many bytes are written.

The debugfs interface has been updated to handle reading all
of the values.  Simply seek to the enum value (multiplied
by 4) and then read as many bytes as the sensor provides.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 26 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h   |  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 28 +--
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c |  5 ++--
 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c|  8 ++-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c  | 11 -
 drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h |  2 +-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h |  2 +-
 8 files changed, 59 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 0d33bc94afb5..78d1f4045539 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3192,24 +3192,36 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file 
*f, char __user *buf,
size_t size, loff_t *pos)
 {
struct amdgpu_device *adev = f->f_inode->i_private;
-   int idx, r;
-   int32_t value;
+   int idx, x, outsize, r, valuesize;
+   uint32_t values[16];
 
-   if (size != 4 || *pos & 0x3)
+   if (size & 3 || *pos & 0x3)
return -EINVAL;
 
/* convert offset to sensor number */
idx = *pos >> 2;
 
+   valuesize = sizeof(values);
if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
-   r = 
adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &value);
+   r = 
adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, 
&values[0], &valuesize);
else
return -EINVAL;
 
-   if (!r)
-   r = put_user(value, (int32_t *)buf);
+   if (size > valuesize)
+   return -EINVAL;
+
+   outsize = 0;
+   x = 0;
+   if (!r) {
+   while (size) {
+   r = put_user(values[x++], (int32_t *)buf);
+   buf += 4;
+   size -= 4;
+   outsize += 4;
+   }
+   }
 
-   return !r ? 4 : r;
+   return !r ? outsize : r;
 }
 
 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 14fef5cf3566..98698dcf15c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -290,9 +290,9 @@ struct amdgpu_dpm_funcs {
 #define amdgpu_dpm_vblank_too_short(adev) 
(adev)->pm.funcs->vblank_too_short((adev))
 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), 
(e))
 
-#define amdgpu_dpm_read_sensor(adev, idx, value) \
+#define amdgpu_dpm_read_sensor(adev, idx, value, size) \
((adev)->pp_enabled ? \
-   
(adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), 
(value)) : \
+   
(adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), 
(value), (size)) : \
-EINVAL)
 
 #define amdgpu_dpm_get_temperature(adev) \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 392bc716e4bd..e27d2ef7531b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1532,6 +1532,7 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, 
struct amdgpu_device *a
 {
uint32_t value;
struct pp_gpu_power query = {0};
+   int size;
 
/* sanity check PP is enabled */
if (!(adev->powerplay.pp_funcs &&
@@ -1539,16 +1540,18 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file 
*m, struct amdgpu_device *a
  return -EINVAL;
 
/* GPU Clocks */
+   size = sizeof(value);
seq_printf(m, "GFX Clocks and Power:\n");
-   if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void 
*)&value))
+   if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void 
*)&value, &size))
seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
-   if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void 
*)&value))
+   if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void 
*)&value, &size))
seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
-   if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void 
*)&value))
+   if (!amd

[no subject]

[Tom St Denis]

Fix bug where GPU_POWER wasn't accessible because we wrote
to *size early...


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[PATCH] drm/amd/amdgpu: Update read_sensor calls to have size parameter (v2)

[Tom St Denis]

This update allows sensors to return more than 1 value and
indicates to the caller how many bytes are written.

The debugfs interface has been updated to handle reading all
of the values.  Simply seek to the enum value (multiplied
by 4) and then read as many bytes as the sensor provides.

(v2):  Don't set size to 4 before reading GPU_POWER

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 26 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h   |  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 28 +--
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c |  5 ++--
 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c|  8 ++-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c  | 16 -
 drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h |  2 +-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h |  2 +-
 8 files changed, 64 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 0d33bc94afb5..78d1f4045539 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3192,24 +3192,36 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file 
*f, char __user *buf,
size_t size, loff_t *pos)
 {
struct amdgpu_device *adev = f->f_inode->i_private;
-   int idx, r;
-   int32_t value;
+   int idx, x, outsize, r, valuesize;
+   uint32_t values[16];
 
-   if (size != 4 || *pos & 0x3)
+   if (size & 3 || *pos & 0x3)
return -EINVAL;
 
/* convert offset to sensor number */
idx = *pos >> 2;
 
+   valuesize = sizeof(values);
if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
-   r = 
adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &value);
+   r = 
adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, 
&values[0], &valuesize);
else
return -EINVAL;
 
-   if (!r)
-   r = put_user(value, (int32_t *)buf);
+   if (size > valuesize)
+   return -EINVAL;
+
+   outsize = 0;
+   x = 0;
+   if (!r) {
+   while (size) {
+   r = put_user(values[x++], (int32_t *)buf);
+   buf += 4;
+   size -= 4;
+   outsize += 4;
+   }
+   }
 
-   return !r ? 4 : r;
+   return !r ? outsize : r;
 }
 
 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 14fef5cf3566..98698dcf15c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -290,9 +290,9 @@ struct amdgpu_dpm_funcs {
 #define amdgpu_dpm_vblank_too_short(adev) 
(adev)->pm.funcs->vblank_too_short((adev))
 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), 
(e))
 
-#define amdgpu_dpm_read_sensor(adev, idx, value) \
+#define amdgpu_dpm_read_sensor(adev, idx, value, size) \
((adev)->pp_enabled ? \
-   
(adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), 
(value)) : \
+   
(adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), 
(value), (size)) : \
-EINVAL)
 
 #define amdgpu_dpm_get_temperature(adev) \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 392bc716e4bd..e27d2ef7531b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1532,6 +1532,7 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, 
struct amdgpu_device *a
 {
uint32_t value;
struct pp_gpu_power query = {0};
+   int size;
 
/* sanity check PP is enabled */
if (!(adev->powerplay.pp_funcs &&
@@ -1539,16 +1540,18 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file 
*m, struct amdgpu_device *a
  return -EINVAL;
 
/* GPU Clocks */
+   size = sizeof(value);
seq_printf(m, "GFX Clocks and Power:\n");
-   if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void 
*)&value))
+   if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void 
*)&value, &size))
seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
-   if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void 
*)&value))
+   if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void 
*)&value, &size))
seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
-   if (!amdgpu_dpm_read_sensor(ad

[UMR] Add GPU_POWER Sensors

[Tom St Denis]

This patch adds the ability to read GPU_POWER sensors on
smu7 hardware.  Because there is an incredibly high latency
on reading them I've added a pthread to handle that.  Hence 
the project now requires pthreads to build.


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[PATCH] Add GPU_POWER sensors

[Tom St Denis]

Add the ability to sample GPU_POWER sensors.  Because
the sensors have a high latency we read them from a background
thread which means we've added the requirement for pthreads.

Signed-off-by: Tom St Denis 
---
 CMakeLists.txt |  5 ++-
 README |  6 ++--
 src/app/top.c  | 88 +-
 src/lib/CMakeLists.txt |  1 +
 src/lib/read_sensor.c  | 37 +
 src/umr.h  |  5 +++
 6 files changed, 123 insertions(+), 19 deletions(-)
 create mode 100644 src/lib/read_sensor.c

diff --git a/CMakeLists.txt b/CMakeLists.txt
index ef78c97ad763..7b771d01919b 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -19,6 +19,9 @@ add_definitions(-DUMR_BUILD_REV=\"${GIT_REV}\")
 # Add local repository for FindXXX.cmake modules.
 SET(CMAKE_MODULE_PATH "${CMAKE_SOURCE_DIR}/cmake_modules/" 
${CMAKE_MODULE_PATH})
 
+find_package(Threads REQUIRED)
+include_directories(${THREADS_INCLUDE_DIRS})
+
 find_package(Curses REQUIRED)
 include_directories(${CURSES_INCLUDE_DIRS})
 
@@ -37,7 +40,7 @@ set(REQUIRED_EXTERNAL_LIBS
 set(CMAKE_POSITION_INDEPENDENT_CODE ON)
 
 # CFLAGS += -Wall -W -O2 -g3 -Isrc/ -DPIC -fPIC
-set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -W -O2 -g3")
+set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -pthread -Wall -W -O2 -g3")
 
 add_subdirectory(src)
 add_subdirectory(doc)
diff --git a/README b/README
index 13cdac663d20..8a8de8485ac7 100644
--- a/README
+++ b/README
@@ -28,9 +28,9 @@ mailing list at:
 Building
 -
 
-To build umr you will need pciaccess, ncurses, and libdrm headers and
-libraries.  Which are available in both Fedora and Ubuntu (as well as
-other distributions).  To build umr:
+To build umr you will need pciaccess, ncurses, libdrm, and pthread 
+headers and libraries.  Which are available in both Fedora and Ubuntu 
+(as well as other distributions).  To build umr:
 
 $ mkdir build && cd build/ && cmake ../
 $ make
diff --git a/src/app/top.c b/src/app/top.c
index b081515a5b40..60f629d247f3 100644
--- a/src/app/top.c
+++ b/src/app/top.c
@@ -54,6 +54,7 @@ enum sensor_maps {
SENSOR_IDENTITY=0, // x = x
SENSOR_D1000,// x = x/1000
SENSOR_D100,// x = x/100
+   SENSOR_WATT,
 };
 
 enum sensor_print {
@@ -61,6 +62,7 @@ enum sensor_print {
SENSOR_MHZ,
SENSOR_PERCENT,
SENSOR_TEMP,
+   SENSOR_POWER,
 };
 
 enum drm_print {
@@ -171,19 +173,14 @@ static struct umr_bitfield stat_uvd_pgfsm7_bits[] = {
 static struct umr_bitfield stat_mc_hub_bits[] = {
 { "OUTSTANDING_READ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_WRITE", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_ATOMIC", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_RDREQ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_RDRET", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_WRREQ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_WRRET", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_HUB_ATOMIC_REQ", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_HUB_ATOMIC_RET", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_RPB_READ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_RPB_WRITE", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_RPB_ATOMIC", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_MCD_READ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_MCD_WRITE", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_MCD_ATOMIC", 255, 255, &umr_bitfield_default },
 { NULL, 0, 0, NULL },
 };
 
@@ -227,6 +224,10 @@ static struct umr_bitfield stat_vi_sensor_bits[] = {
{ "GFX_MCLK", AMDGPU_PP_SENSOR_GFX_MCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
&umr_bitfield_default },
{ "GPU_LOAD", AMDGPU_PP_SENSOR_GPU_LOAD, SENSOR_PERCENT<<4, 
&umr_bitfield_default },
{ "GPU_TEMP", AMDGPU_PP_SENSOR_GPU_TEMP, SENSOR_D1000|(SENSOR_TEMP<<4), 
&umr_bitfield_default },
+   { "VDDC", AMDGPU_PP_SENSOR_GPU_POWER, 
SENSOR_WATT|(SENSOR_POWER<<4), &umr_bitfield_default },
+   { "VDDCI",AMDGPU_PP_SENSOR_GPU_POWER, 
SENSOR_WATT|(SENSOR_POWER<<4), &umr_bitfield_default },
+   { "MAX_GPU",  AMDGPU_PP_SENSOR_GPU_POWER, 
SENSOR_WATT|(SENSOR_POWER<<4), &umr_bitfield_default },
+   { "AVG_GPU",  AMDGPU_PP_SENSOR_GPU_POWER, 
SENSOR_WATT|(SENSOR_POWER<<4), &umr_bitfield_default },
{ NULL, 0, 0, NULL },
 };
 
@@ -256,6 +257,21 @@ static struct umr_bitfield stat_drm_bits[] = {
 
 static FILE *logfile

Re: [PATCH] Add GPU_POWER sensors

[Tom St Denis]

On 02/10/2017 07:25 PM, Edward O'Callaghan wrote:

Hey Tom,

On 02/11/2017 05:10 AM, Tom St Denis wrote:

Add the ability to sample GPU_POWER sensors.  Because
the sensors have a high latency we read them from a background
thread which means we've added the requirement for pthreads.

Signed-off-by: Tom St Denis 
---
 CMakeLists.txt |  5 ++-
 README |  6 ++--
 src/app/top.c  | 88 +-
 src/lib/CMakeLists.txt |  1 +
 src/lib/read_sensor.c  | 37 +
 src/umr.h  |  5 +++
 6 files changed, 123 insertions(+), 19 deletions(-)
 create mode 100644 src/lib/read_sensor.c

diff --git a/CMakeLists.txt b/CMakeLists.txt
index ef78c97ad763..7b771d01919b 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -19,6 +19,9 @@ add_definitions(-DUMR_BUILD_REV=\"${GIT_REV}\")
 # Add local repository for FindXXX.cmake modules.
 SET(CMAKE_MODULE_PATH "${CMAKE_SOURCE_DIR}/cmake_modules/" 
${CMAKE_MODULE_PATH})

+find_package(Threads REQUIRED)
+include_directories(${THREADS_INCLUDE_DIRS})

Do you need this include_directories() line?


+
 find_package(Curses REQUIRED)
 include_directories(${CURSES_INCLUDE_DIRS})

@@ -37,7 +40,7 @@ set(REQUIRED_EXTERNAL_LIBS
 set(CMAKE_POSITION_INDEPENDENT_CODE ON)

 # CFLAGS += -Wall -W -O2 -g3 -Isrc/ -DPIC -fPIC
-set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -W -O2 -g3")
+set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -pthread -Wall -W -O2 -g3")

You don't really want to have your linkage flags here, I think your
looking for ${CMAKE_THREAD_LIBS_INIT} to go into the
REQUIRED_EXTERNAL_LIBS list.


How does it "go into"?  Simple '+='?

Can you just send a quick patch I can squash into this?  The less I know 
about cmake the more room I have in my head for useful things :-) hehehe.



 enum drm_print {
@@ -171,19 +173,14 @@ static struct umr_bitfield stat_uvd_pgfsm7_bits[] = {
 static struct umr_bitfield stat_mc_hub_bits[] = {
 { "OUTSTANDING_READ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_WRITE", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_ATOMIC", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_RDREQ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_RDRET", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_WRREQ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_WRRET", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_HUB_ATOMIC_REQ", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_HUB_ATOMIC_RET", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_RPB_READ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_RPB_WRITE", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_RPB_ATOMIC", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_MCD_READ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_MCD_WRITE", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_MCD_ATOMIC", 255, 255, &umr_bitfield_default },
 { NULL, 0, 0, NULL },
 };

this hulk seems unrelated to this patch?


It is, but since there's no functional change I figured I'd just squash 
that in as house keeping.


Cheers,
tom
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[PATCH] Add GPU_POWER sensors (v2)

[Tom St Denis]

Add the ability to sample GPU_POWER sensors.  Because
the sensors have a high latency we read them from a background
thread which means we've added the requirement for pthreads.

Signed-off-by: Tom St Denis 

(v2) Cleaned up CMake around pthreads
---
 CMakeLists.txt |  4 +++
 README |  6 ++--
 src/app/top.c  | 88 +-
 src/lib/CMakeLists.txt |  1 +
 src/lib/read_sensor.c  | 37 +
 src/umr.h  |  5 +++
 6 files changed, 123 insertions(+), 18 deletions(-)
 create mode 100644 src/lib/read_sensor.c

diff --git a/CMakeLists.txt b/CMakeLists.txt
index ef78c97ad763..8d89445c39e3 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -19,6 +19,9 @@ add_definitions(-DUMR_BUILD_REV=\"${GIT_REV}\")
 # Add local repository for FindXXX.cmake modules.
 SET(CMAKE_MODULE_PATH "${CMAKE_SOURCE_DIR}/cmake_modules/" 
${CMAKE_MODULE_PATH})
 
+set(CMAKE_THREAD_PREFER_PTHREAD TRUE)
+find_package(Threads REQUIRED)
+
 find_package(Curses REQUIRED)
 include_directories(${CURSES_INCLUDE_DIRS})
 
@@ -31,6 +34,7 @@ include_directories(${LIBDRM_INCLUDE_DIR})
 set(REQUIRED_EXTERNAL_LIBS
   ${CURSES_LIBRARIES}
   ${PCIACCESS_LIBRARIES}
+  Threads::Threads
 )
 
 # Global setting: build everything position independent
diff --git a/README b/README
index 13cdac663d20..8a8de8485ac7 100644
--- a/README
+++ b/README
@@ -28,9 +28,9 @@ mailing list at:
 Building
 -
 
-To build umr you will need pciaccess, ncurses, and libdrm headers and
-libraries.  Which are available in both Fedora and Ubuntu (as well as
-other distributions).  To build umr:
+To build umr you will need pciaccess, ncurses, libdrm, and pthread 
+headers and libraries.  Which are available in both Fedora and Ubuntu 
+(as well as other distributions).  To build umr:
 
 $ mkdir build && cd build/ && cmake ../
 $ make
diff --git a/src/app/top.c b/src/app/top.c
index b081515a5b40..60f629d247f3 100644
--- a/src/app/top.c
+++ b/src/app/top.c
@@ -54,6 +54,7 @@ enum sensor_maps {
SENSOR_IDENTITY=0, // x = x
SENSOR_D1000,// x = x/1000
SENSOR_D100,// x = x/100
+   SENSOR_WATT,
 };
 
 enum sensor_print {
@@ -61,6 +62,7 @@ enum sensor_print {
SENSOR_MHZ,
SENSOR_PERCENT,
SENSOR_TEMP,
+   SENSOR_POWER,
 };
 
 enum drm_print {
@@ -171,19 +173,14 @@ static struct umr_bitfield stat_uvd_pgfsm7_bits[] = {
 static struct umr_bitfield stat_mc_hub_bits[] = {
 { "OUTSTANDING_READ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_WRITE", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_ATOMIC", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_RDREQ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_RDRET", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_WRREQ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_WRRET", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_HUB_ATOMIC_REQ", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_HUB_ATOMIC_RET", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_RPB_READ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_RPB_WRITE", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_RPB_ATOMIC", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_MCD_READ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_MCD_WRITE", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_MCD_ATOMIC", 255, 255, &umr_bitfield_default },
 { NULL, 0, 0, NULL },
 };
 
@@ -227,6 +224,10 @@ static struct umr_bitfield stat_vi_sensor_bits[] = {
{ "GFX_MCLK", AMDGPU_PP_SENSOR_GFX_MCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
&umr_bitfield_default },
{ "GPU_LOAD", AMDGPU_PP_SENSOR_GPU_LOAD, SENSOR_PERCENT<<4, 
&umr_bitfield_default },
{ "GPU_TEMP", AMDGPU_PP_SENSOR_GPU_TEMP, SENSOR_D1000|(SENSOR_TEMP<<4), 
&umr_bitfield_default },
+   { "VDDC", AMDGPU_PP_SENSOR_GPU_POWER, 
SENSOR_WATT|(SENSOR_POWER<<4), &umr_bitfield_default },
+   { "VDDCI",AMDGPU_PP_SENSOR_GPU_POWER, 
SENSOR_WATT|(SENSOR_POWER<<4), &umr_bitfield_default },
+   { "MAX_GPU",  AMDGPU_PP_SENSOR_GPU_POWER, 
SENSOR_WATT|(SENSOR_POWER<<4), &umr_bitfield_default },
+   { "AVG_GPU",  AMDGPU_PP_SENSOR_GPU_POWER, 
SENSOR_WATT|(SENSOR_POWER<<4), &umr_bitfield_default },
{ NULL, 0, 0, NULL },
 };
 
@@ -256,6 +257,21 @@ static struct umr_bitfield stat_drm_bits[] = {
 
 static FILE *logfile = NULL;
 
+static volatile int sensor_thread_quit = 0;
+

Re: [PATCH] Add GPU_POWER sensors

[Tom St Denis]

On 11/02/17 05:56 AM, Kai Wasserbäch wrote:

Hey Tom,
Tom St Denis wrote on 11.02.2017 02:02:

On 02/10/2017 07:25 PM, Edward O'Callaghan wrote:

Hey Tom,

On 02/11/2017 05:10 AM, Tom St Denis wrote:

Add the ability to sample GPU_POWER sensors.  Because
the sensors have a high latency we read them from a background
thread which means we've added the requirement for pthreads.

Signed-off-by: Tom St Denis 
---
 CMakeLists.txt |  5 ++-
 README |  6 ++--
 src/app/top.c  | 88 +-
 src/lib/CMakeLists.txt |  1 +
 src/lib/read_sensor.c  | 37 +
 src/umr.h  |  5 +++
 6 files changed, 123 insertions(+), 19 deletions(-)
 create mode 100644 src/lib/read_sensor.c

diff --git a/CMakeLists.txt b/CMakeLists.txt
index ef78c97ad763..7b771d01919b 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -19,6 +19,9 @@ add_definitions(-DUMR_BUILD_REV=\"${GIT_REV}\")
 # Add local repository for FindXXX.cmake modules.
 SET(CMAKE_MODULE_PATH "${CMAKE_SOURCE_DIR}/cmake_modules/"
${CMAKE_MODULE_PATH})

+find_package(Threads REQUIRED)
+include_directories(${THREADS_INCLUDE_DIRS})

Do you need this include_directories() line?


+
 find_package(Curses REQUIRED)
 include_directories(${CURSES_INCLUDE_DIRS})

@@ -37,7 +40,7 @@ set(REQUIRED_EXTERNAL_LIBS
 set(CMAKE_POSITION_INDEPENDENT_CODE ON)

 # CFLAGS += -Wall -W -O2 -g3 -Isrc/ -DPIC -fPIC
-set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -W -O2 -g3")
+set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -pthread -Wall -W -O2 -g3")

You don't really want to have your linkage flags here, I think your
looking for ${CMAKE_THREAD_LIBS_INIT} to go into the
REQUIRED_EXTERNAL_LIBS list.


How does it "go into"?  Simple '+='?

Can you just send a quick patch I can squash into this?  The less I know about
cmake the more room I have in my head for useful things :-) hehehe.


1. You might want to set
  set(CMAKE_THREAD_PREFER_PTHREAD TRUE)
at before the find_package() for Threads
2. Linking usually happens through target_link_*() calls, where you would add
Threads::Threads (special thing created by FindThreads.cmake) to the list of
your other variables.

See <https://cmake.org/cmake/help/v3.7/module/FindThreads.html> for details on
how FindThreads.cmake works. In your case you might want to set
THREADS_PREFER_PTHREAD_FLAG as well.


Thanks.  I've sent v2 to the list.

Cheers,
Tom
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[PATCH 2/2] Add GPU_POWER sensors (v3)

[Tom St Denis]

Add the ability to sample GPU_POWER sensors.  Because
the sensors have a high latency we read them from a background
thread which means we've added the requirement for pthreads.

Signed-off-by: Tom St Denis 

(v2) Cleaned up CMake around pthreads
(v3) Update readme, factor out some deletions, cleanup switch statement
---
 CMakeLists.txt |  4 +++
 README |  5 ++-
 src/app/top.c  | 90 --
 src/lib/CMakeLists.txt |  1 +
 src/lib/read_sensor.c  | 37 +
 src/umr.h  |  5 +++
 6 files changed, 129 insertions(+), 13 deletions(-)
 create mode 100644 src/lib/read_sensor.c

diff --git a/CMakeLists.txt b/CMakeLists.txt
index ef78c97ad763..8d89445c39e3 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -19,6 +19,9 @@ add_definitions(-DUMR_BUILD_REV=\"${GIT_REV}\")
 # Add local repository for FindXXX.cmake modules.
 SET(CMAKE_MODULE_PATH "${CMAKE_SOURCE_DIR}/cmake_modules/" 
${CMAKE_MODULE_PATH})
 
+set(CMAKE_THREAD_PREFER_PTHREAD TRUE)
+find_package(Threads REQUIRED)
+
 find_package(Curses REQUIRED)
 include_directories(${CURSES_INCLUDE_DIRS})
 
@@ -31,6 +34,7 @@ include_directories(${LIBDRM_INCLUDE_DIR})
 set(REQUIRED_EXTERNAL_LIBS
   ${CURSES_LIBRARIES}
   ${PCIACCESS_LIBRARIES}
+  Threads::Threads
 )
 
 # Global setting: build everything position independent
diff --git a/README b/README
index 13cdac663d20..8b75f05a13b5 100644
--- a/README
+++ b/README
@@ -28,9 +28,8 @@ mailing list at:
 Building
 -
 
-To build umr you will need pciaccess, ncurses, and libdrm headers and
-libraries.  Which are available in both Fedora and Ubuntu (as well as
-other distributions).  To build umr:
+To build umr you will need pciaccess, ncurses, libdrm, and pthread
+headers and libraries.  To build umr:
 
 $ mkdir build && cd build/ && cmake ../
 $ make
diff --git a/src/app/top.c b/src/app/top.c
index d9a474d78cf7..92ab8ab854af 100644
--- a/src/app/top.c
+++ b/src/app/top.c
@@ -54,6 +54,7 @@ enum sensor_maps {
SENSOR_IDENTITY=0, // x = x
SENSOR_D1000,// x = x/1000
SENSOR_D100,// x = x/100
+   SENSOR_WATT,
 };
 
 enum sensor_print {
@@ -61,6 +62,7 @@ enum sensor_print {
SENSOR_MHZ,
SENSOR_PERCENT,
SENSOR_TEMP,
+   SENSOR_POWER,
 };
 
 enum drm_print {
@@ -222,6 +224,10 @@ static struct umr_bitfield stat_vi_sensor_bits[] = {
{ "GFX_MCLK", AMDGPU_PP_SENSOR_GFX_MCLK, SENSOR_D100|(SENSOR_MHZ<<4), 
&umr_bitfield_default },
{ "GPU_LOAD", AMDGPU_PP_SENSOR_GPU_LOAD, SENSOR_PERCENT<<4, 
&umr_bitfield_default },
{ "GPU_TEMP", AMDGPU_PP_SENSOR_GPU_TEMP, SENSOR_D1000|(SENSOR_TEMP<<4), 
&umr_bitfield_default },
+   { "VDDC", AMDGPU_PP_SENSOR_GPU_POWER, 
SENSOR_WATT|(SENSOR_POWER<<4), &umr_bitfield_default },
+   { "VDDCI",AMDGPU_PP_SENSOR_GPU_POWER, 
SENSOR_WATT|(SENSOR_POWER<<4), &umr_bitfield_default },
+   { "MAX_GPU",  AMDGPU_PP_SENSOR_GPU_POWER, 
SENSOR_WATT|(SENSOR_POWER<<4), &umr_bitfield_default },
+   { "AVG_GPU",  AMDGPU_PP_SENSOR_GPU_POWER, 
SENSOR_WATT|(SENSOR_POWER<<4), &umr_bitfield_default },
{ NULL, 0, 0, NULL },
 };
 
@@ -251,6 +257,21 @@ static struct umr_bitfield stat_drm_bits[] = {
 
 static FILE *logfile = NULL;
 
+static volatile int sensor_thread_quit = 0;
+static uint32_t gpu_power_data[4];
+static void *vi_sensor_thread(void *data)
+{
+   struct umr_asic asic = *((struct umr_asic*)data);
+   int size = sizeof(gpu_power_data);
+   char fname[128];
+
+   snprintf(fname, sizeof(fname)-1, 
"/sys/kernel/debug/dri/%d/amdgpu_sensors", asic.instance);
+   asic.fd.sensors = open(fname, O_RDWR);
+   while (!sensor_thread_quit)
+   umr_read_sensor(&asic, AMDGPU_PP_SENSOR_GPU_POWER, 
gpu_power_data, &size);
+   close(asic.fd.sensors);
+   return NULL;
+}
 
 static unsigned long last_fence_emitted, last_fence_signaled, 
fence_signal_count, fence_emit_count;
 static void analyze_fence_info(struct umr_asic *asic)
@@ -423,6 +444,9 @@ static void print_sensors(struct umr_bitfield *bits, 
uint64_t *counts)
case SENSOR_TEMP:
printw("%5d C  ", counts[i]);
break;
+   case SENSOR_POWER:
+   printw("%3d.%02d W ", counts[i]/100, 
counts[i]%100);
+   break;
};
if ((++print_j & (top_options.wide ? 3 : 1)) != 0)
printw(" |");
@@ -491,8 +515,8 @@ static void parse_bits(struct umr_asic *asic, uint32_t 
addr, struct umr_bitfield
 
 static void parse_s

[PATCH 1/2] Remove unused bits from --top

[Tom St Denis]

Signed-off-by: Tom St Denis 
---
 src/app/top.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/src/app/top.c b/src/app/top.c
index b081515a5b40..d9a474d78cf7 100644
--- a/src/app/top.c
+++ b/src/app/top.c
@@ -171,19 +171,14 @@ static struct umr_bitfield stat_uvd_pgfsm7_bits[] = {
 static struct umr_bitfield stat_mc_hub_bits[] = {
 { "OUTSTANDING_READ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_WRITE", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_ATOMIC", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_RDREQ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_RDRET", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_WRREQ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_WRRET", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_HUB_ATOMIC_REQ", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_HUB_ATOMIC_RET", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_RPB_READ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_RPB_WRITE", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_RPB_ATOMIC", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_MCD_READ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_MCD_WRITE", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_MCD_ATOMIC", 255, 255, &umr_bitfield_default },
 { NULL, 0, 0, NULL },
 };
 
-- 
2.11.0

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[UMR] Add GPU_POWER (v3) + refactored cleanup

[Tom St Denis]

I split out the deletion of the unused bits in --top.


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Re: [PATCH] Add GPU_POWER sensors (v2)

[Tom St Denis]

On 02/11/2017 08:29 AM, Kai Wasserbäch wrote:

Hey Tom,
Tom St Denis wrote on 11.02.2017 12:26:

Add the ability to sample GPU_POWER sensors.  Because
the sensors have a high latency we read them from a background
thread which means we've added the requirement for pthreads.

Signed-off-by: Tom St Denis 

(v2) Cleaned up CMake around pthreads
---
 CMakeLists.txt |  4 +++
 README |  6 ++--
 src/app/top.c  | 88 +-
 src/lib/CMakeLists.txt |  1 +
 src/lib/read_sensor.c  | 37 +
 src/umr.h  |  5 +++
 6 files changed, 123 insertions(+), 18 deletions(-)
 create mode 100644 src/lib/read_sensor.c

diff --git a/CMakeLists.txt b/CMakeLists.txt
index ef78c97ad763..8d89445c39e3 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -19,6 +19,9 @@ add_definitions(-DUMR_BUILD_REV=\"${GIT_REV}\")
 # Add local repository for FindXXX.cmake modules.
 SET(CMAKE_MODULE_PATH "${CMAKE_SOURCE_DIR}/cmake_modules/" 
${CMAKE_MODULE_PATH})

+set(CMAKE_THREAD_PREFER_PTHREAD TRUE)
+find_package(Threads REQUIRED)
+
 find_package(Curses REQUIRED)
 include_directories(${CURSES_INCLUDE_DIRS})

@@ -31,6 +34,7 @@ include_directories(${LIBDRM_INCLUDE_DIR})
 set(REQUIRED_EXTERNAL_LIBS
   ${CURSES_LIBRARIES}
   ${PCIACCESS_LIBRARIES}
+  Threads::Threads
 )

 # Global setting: build everything position independent
diff --git a/README b/README
index 13cdac663d20..8a8de8485ac7 100644
--- a/README
+++ b/README
@@ -28,9 +28,9 @@ mailing list at:
 Building
 -

-To build umr you will need pciaccess, ncurses, and libdrm headers and
-libraries.  Which are available in both Fedora and Ubuntu (as well as
-other distributions).  To build umr:
+To build umr you will need pciaccess, ncurses, libdrm, and pthread
+headers and libraries.  Which are available in both Fedora and Ubuntu
+(as well as other distributions).  To build umr:


maybe just write "most distributions"? Since you're not giving package names I
don't really see a point in naming two distributions, especially where one is
just a derivative.


I can update that.  To be honest I do 99% of my testing with Fedora and 
Ubuntu is used quite a bit amongst AMDers.






 $ mkdir build && cd build/ && cmake ../
 $ make
diff --git a/src/app/top.c b/src/app/top.c
index b081515a5b40..60f629d247f3 100644
--- a/src/app/top.c
+++ b/src/app/top.c
@@ -54,6 +54,7 @@ enum sensor_maps {
SENSOR_IDENTITY=0, // x = x
SENSOR_D1000,// x = x/1000
SENSOR_D100,// x = x/100
+   SENSOR_WATT,
 };

 enum sensor_print {
@@ -61,6 +62,7 @@ enum sensor_print {
SENSOR_MHZ,
SENSOR_PERCENT,
SENSOR_TEMP,
+   SENSOR_POWER,
 };

 enum drm_print {
@@ -171,19 +173,14 @@ static struct umr_bitfield stat_uvd_pgfsm7_bits[] = {
 static struct umr_bitfield stat_mc_hub_bits[] = {
 { "OUTSTANDING_READ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_WRITE", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_ATOMIC", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_RDREQ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_RDRET", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_WRREQ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_HUB_WRRET", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_HUB_ATOMIC_REQ", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_HUB_ATOMIC_RET", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_RPB_READ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_RPB_WRITE", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_RPB_ATOMIC", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_MCD_READ", 255, 255, &umr_bitfield_default },
 { "OUTSTANDING_MCD_WRITE", 255, 255, &umr_bitfield_default },
-//  { "OUTSTANDING_MCD_ATOMIC", 255, 255, &umr_bitfield_default },
 { NULL, 0, 0, NULL },
 };


I would agree with Edward and rather have these in a separate clean-up patch.


It's interesting that you note this.


Could you put the assignment and break on their own lines? Would increase
readability IMHO. Also maybe add spaces between variables, operators and
constants? I'm imagining something like


Because of this.

I'm not disagreeing with your formatting suggestion it just seems at 
this point we're building a deluxe bike shed.  I already own a bike shed 
(which my daughter calls a mini house) and don't need another. :-)


If I revert the hunk about the removed comment lines I cannot logically 
include your formatting changes since they're not material to the 
functional changes introduced by thi

Re: [UMR] Add GPU_POWER (v3) + refactored cleanup

[Tom St Denis]

On 02/11/2017 01:57 PM, Kai Wasserbäch wrote:

Hey Tom,
Tom St Denis wrote on 11.02.2017 18:52:

I split out the deletion of the unused bits in --top.


thank you so much for bearing with me (and Edward, though I can't speak for him,
obviously)! You can still have my R-b. ;-)

Cheers,
Kai



No worries.  It's no secret I'm no fan of NFC re-submits but hard to get 
upset in the face of genuinely good feedback.  And it is a community 
project in the long run so it's not like community pushback/feedback is 
not welcomed (my rumblings notwithstanding).


Thanks to you and Edward for the feedback.

I've pushed them out.  You'll need a staging kernel to use GPU_POWER 
(with my and Eric's patches) to see any of this on a VI dGPU.


It's kinda interesting to see the power usage graphs (using umr's --top 
'logger' mode) comparing Polaris10 and fiji while running say 
unigine-heaven.  I think the sensors will help debug/optimize power 
usage going forward.


Cheers,
Tom
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Re: Initial Public Release of AMDGPU debugger

[Tom St Denis]

On 02/12/2017 09:39 PM, Dave Airlie wrote:

We're pleased to announce the initial public release of the AMDGPU User Mode
Register debugger (umr).  This tool allows privileged users to read and
write GPU registers in order to diagnose, debug, and aid in development of
AMDGPU features.  The tool supports a variety of other commands for actions
such as decoding ring contents, analyzing wavefronts, viewing machine
status, and more.  It supports SI through VI devices and requires a very
recent kernel (what will be 4.10).


The tool is released publicly under a MIT open source license and is hosted
at


https://cgit.freedesktop.org/amd/umr/


We welcome all developers to try it out and submit feedback, suggestions,
bug reports, and patches to this mailing list.


The project started internally as a debug aid last year and was the driving
force behind the debugfs changes over the last year.   The tool has matured
enough that we feel the community will be best served by having access to it
and after having been granted permission to release it I've squashed most of
our internal history down to a few commits which are now available to the
public.


Development of the tool has been alongside the AMD staging 4.9 tree which
has commits slotted for 4.10 and 4.11.  Most features should work with a 4.9
vanilla kernel but users are recommended to really use 4.10 or newer
kernels.   Within reason we will try to accommodate older kernels but it is
not our primary focus.


Future work will be done through patches submitted to the list to foster
community involvement.


Hi Tom,

Is there any plans or would it be possible to add some sort of info on what you
are looking at with UMR. Say the GRBM busy states what sort of meaning
can be extracted from the percentage values etc, can you say with how busy
some of the blocks are what should be done next to try and optimise things
or to look for problems etc.


Hi Dave,

Honestly it's a bit out of my field.  Adding the bits was the easy part 
:-).  Personally I've used the power/clock counters (as well as power) 
for the various work I've done on PG/CG.  Lately, I've used it to test 
patches from others.


You can kinda get a "broad" sense of performance deltas by tracking the 
deltas in percentages between various runs but that's ultimately not 
super useful for developers unless you know what you're looking at.


Generally speaking when looking at the GRBM/TA/VGT counters you would 
need to know the components of the core and how the shaders interact 
with them (the ISA of the GPU in question).


Presumably combined with GALLIUM_HUD performance trackers (which count 
things like cache misses for instance) you could perf where the GPU is 
being busy the most and get hints on where to optimize.


Ideally combined with UMR's "logger" mode in --top and a properly 
instrumented mesa test case developers could correlate the global bits 
umr tracks with the context specific perf counters mesa can capture.


Perhaps Alex and/or the Mesa folk could offer more insight.

Sorry I couldn't be of more help though.  If nobody else from AMD joins 
in the conversation I'll raise it privately on Monday.


Cheers,
Tom
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Re: Initial Public Release of AMDGPU debugger

[Tom St Denis]

On 13/02/17 05:00 AM, Nils Holland wrote:

On Sat, Feb 04, 2017 at 06:44:12PM +, StDenis, Tom wrote:

Hello all,


We're pleased to announce the initial public release of the AMDGPU
User Mode Register debugger (umr).  This tool allows privileged
users to read and write GPU registers in order to diagnose, debug,
and aid in development of AMDGPU features.  The tool supports a
variety of other commands for actions such as decoding ring
contents, analyzing wavefronts, viewing machine status, and more.
It supports SI through VI devices and requires a very recent kernel
(what will be 4.10).


Just a short question: Am I correct in noticing that the tool
currently only supports standalone GPUs and not the APUs, e.g. I have
a:

VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI]
Kabini [Radeon HD 8210]

as part of an AMD E1-2100 APU and the tool tells me:

nils@teela ~ $ umr -c
ERROR: Device 0x9834 not found in UMR device table
ASIC not found (instance=0, did=)

I also don't see any reference to kabini in the tool's code, so unless
I'm doing something wrong, this might be expected, right?


You're right that kabini hasn't been added (nor mullins or hawaii). 
That's purely an oversight.  The focus has been largely on VI devices 
during development but I can easily circle back and add the missing CIK 
devices today.


For ref, it does support APUs (Carrizo, Stoney, Kaveri) :-).

Tom
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[PATCH] Add missing CIK devices

[Tom St Denis]

Adds mullins, kabini, and hawaii ASICs to the library.

Signed-off-by: Tom St Denis 
---
 src/lib/asic/CMakeLists.txt |  3 +++
 src/lib/asic/hawaii.c   | 40 
 src/lib/asic/kabini.c   | 40 
 src/lib/asic/mullins.c  | 40 
 src/lib/discover_by_did.c   | 44 
 src/lib/discover_by_name.c  |  3 +++
 src/umr.h   |  3 +++
 7 files changed, 173 insertions(+)
 create mode 100644 src/lib/asic/hawaii.c
 create mode 100644 src/lib/asic/kabini.c
 create mode 100644 src/lib/asic/mullins.c

diff --git a/src/lib/asic/CMakeLists.txt b/src/lib/asic/CMakeLists.txt
index 6cfec309b6a5..07e9ad8cca4f 100644
--- a/src/lib/asic/CMakeLists.txt
+++ b/src/lib/asic/CMakeLists.txt
@@ -6,7 +6,10 @@ add_library(asic OBJECT
   carrizo.c
   fiji.c
   hainan.c
+  hawaii.c
+  kabini.c
   kaveri.c
+  mullins.c
   oland.c
   pitcairn.c
   polaris10.c
diff --git a/src/lib/asic/hawaii.c b/src/lib/asic/hawaii.c
new file mode 100644
index ..07cbcac31a07
--- /dev/null
+++ b/src/lib/asic/hawaii.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis 
+ *
+ */
+#include "umr.h"
+
+struct umr_asic *umr_create_hawaii(struct umr_options *options)
+{
+   return
+   umr_create_asic_helper("hawaii", FAMILY_CIK,
+   umr_create_uvd42(options),
+   umr_create_vce2(options),
+   umr_create_gmc70(options),
+   umr_create_dce80(options),
+   umr_create_gfx72(options),
+   umr_create_smu700(options),
+   umr_create_oss20(options),
+   umr_create_bif41(options),
+   NULL);
+}
diff --git a/src/lib/asic/kabini.c b/src/lib/asic/kabini.c
new file mode 100644
index ..08c3eb4da684
--- /dev/null
+++ b/src/lib/asic/kabini.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis 
+ *
+ */
+#include "umr.h"
+
+struct umr_asic *umr_create_kabini(struct umr_options *options)
+{
+   return
+   umr_create_asic_helper("kabini", FAMILY_CIK,
+   umr_create_uvd42(options),
+   umr_create_vce2(options),
+   umr_create_gmc70(options),
+   umr_create_dce80(options),
+   umr_create_gfx72(options),
+   umr_create_smu700(options),
+   umr_create_oss20(options),
+   umr_create_bif41(options),

Re: [PATCH] Add missing CIK devices

[Tom St Denis]

On 13/02/17 08:12 AM, Christian König wrote:

Am 13.02.2017 um 13:46 schrieb Tom St Denis:

Adds mullins, kabini, and hawaii ASICs to the library.

Signed-off-by: Tom St Denis 


Acked-by: Christian König .


Thanks.

If there are no objections I'll push it out in a couple hours.

Cheers,
Tom
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[PATCH] Add new gmc/smu registers

[Tom St Denis]

Signed-off-by: Tom St Denis 
---
 src/lib/ip/gmc60_bits.i  | 2 ++
 src/lib/ip/smu701_bits.i | 4 
 src/lib/ip/smu701_regs.i | 1 +
 src/lib/ip/smu711_bits.i | 4 
 src/lib/ip/smu711_regs.i | 1 +
 src/lib/ip/smu712_bits.i | 4 
 src/lib/ip/smu712_regs.i | 1 +
 src/lib/ip/smu713_bits.i | 4 
 src/lib/ip/smu713_regs.i | 1 +
 9 files changed, 22 insertions(+)

diff --git a/src/lib/ip/gmc60_bits.i b/src/lib/ip/gmc60_bits.i
index 746dd64fb392..4e4c052f6e79 100644
--- a/src/lib/ip/gmc60_bits.i
+++ b/src/lib/ip/gmc60_bits.i
@@ -3230,6 +3230,8 @@ static struct umr_bitfield mmVM_PRT_APERTURE3_HIGH_ADDR[] 
= {
 static struct umr_bitfield mmVM_PRT_CNTL[] = {
 { "L1_TLB_STORE_INVALID_ENTRIES", 3, 3, &umr_bitfield_default },
 { "L2_CACHE_STORE_INVALID_ENTRIES", 2, 2, &umr_bitfield_default },
+{ "CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS", 0, 0, &umr_bitfield_default },
+{ "TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS", 1, 1, &umr_bitfield_default },
 };
 static struct umr_bitfield mmVM_CONTEXTS_DISABLE[] = {
 { "DISABLE_CONTEXT_0", 0, 0, &umr_bitfield_default },
diff --git a/src/lib/ip/smu701_bits.i b/src/lib/ip/smu701_bits.i
index 972d8b74b5db..2f50eb9f0b67 100644
--- a/src/lib/ip/smu701_bits.i
+++ b/src/lib/ip/smu701_bits.i
@@ -4391,6 +4391,10 @@ static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_7[] = {
 static struct umr_bitfield ixCG_DISPLAY_GAP_CNTL2[] = {
 { "VBI_PREDICTION", 0, 31, &umr_bitfield_default },
 };
+static struct umr_bitfield ixCURRENT_PG_STATUS[] = {
+{ "VCE_PG_STATUS", 1, 1, &umr_bitfield_default },
+{ "UVD_PG_STATUS", 2, 2, &umr_bitfield_default },
+};
 static struct umr_bitfield ixSCLK_MIN_DIV[] = {
 { "FRACV", 0, 11, &umr_bitfield_default },
 { "INTV", 12, 18, &umr_bitfield_default },
diff --git a/src/lib/ip/smu701_regs.i b/src/lib/ip/smu701_regs.i
index 63f85e1173cc..3ff965359c89 100644
--- a/src/lib/ip/smu701_regs.i
+++ b/src/lib/ip/smu701_regs.i
@@ -1091,6 +1091,7 @@
{ "ixCG_FREQ_TRAN_VOTING_6", REG_SMC, 0xc02001c0, 
&ixCG_FREQ_TRAN_VOTING_6[0], 
sizeof(ixCG_FREQ_TRAN_VOTING_6)/sizeof(ixCG_FREQ_TRAN_VOTING_6[0]), 0, 0 },
{ "ixCG_FREQ_TRAN_VOTING_7", REG_SMC, 0xc02001c4, 
&ixCG_FREQ_TRAN_VOTING_7[0], 
sizeof(ixCG_FREQ_TRAN_VOTING_7)/sizeof(ixCG_FREQ_TRAN_VOTING_7[0]), 0, 0 },
{ "ixCG_DISPLAY_GAP_CNTL2", REG_SMC, 0xc0200230, 
&ixCG_DISPLAY_GAP_CNTL2[0], 
sizeof(ixCG_DISPLAY_GAP_CNTL2)/sizeof(ixCG_DISPLAY_GAP_CNTL2[0]), 0, 0 },
+   { "ixCURRENT_PG_STATUS", REG_SMC, 0xc020029c, &ixCURRENT_PG_STATUS[0], 
sizeof(ixCURRENT_PG_STATUS)/sizeof(ixCURRENT_PG_STATUS[0]), 0, 0 },
{ "ixSCLK_MIN_DIV", REG_SMC, 0xc0200308, &ixSCLK_MIN_DIV[0], 
sizeof(ixSCLK_MIN_DIV)/sizeof(ixSCLK_MIN_DIV[0]), 0, 0 },
{ "ixLCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xc0200310, 
&ixLCLK_DEEP_SLEEP_CNTL2[0], 
sizeof(ixLCLK_DEEP_SLEEP_CNTL2)/sizeof(ixLCLK_DEEP_SLEEP_CNTL2[0]), 0, 0 },
{ "ixCG_THERMAL_CTRL", REG_SMC, 0xc034, &ixCG_THERMAL_CTRL[0], 
sizeof(ixCG_THERMAL_CTRL)/sizeof(ixCG_THERMAL_CTRL[0]), 0, 0 },
diff --git a/src/lib/ip/smu711_bits.i b/src/lib/ip/smu711_bits.i
index 6d803259e970..afd90220d5d5 100644
--- a/src/lib/ip/smu711_bits.i
+++ b/src/lib/ip/smu711_bits.i
@@ -3577,6 +3577,10 @@ static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_7[] = {
 static struct umr_bitfield ixCG_DISPLAY_GAP_CNTL2[] = {
 { "VBI_PREDICTION", 0, 31, &umr_bitfield_default },
 };
+static struct umr_bitfield ixCURRENT_PG_STATUS[] = {
+{ "VCE_PG_STATUS", 1, 1, &umr_bitfield_default },
+{ "UVD_PG_STATUS", 2, 2, &umr_bitfield_default },
+};
 static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL2[] = {
 { "RFE_BUSY_MASK", 0, 0, &umr_bitfield_default },
 { "BIF_CG_LCLK_BUSY_MASK", 1, 1, &umr_bitfield_default },
diff --git a/src/lib/ip/smu711_regs.i b/src/lib/ip/smu711_regs.i
index 6e66ecd4ac09..efeac147288e 100644
--- a/src/lib/ip/smu711_regs.i
+++ b/src/lib/ip/smu711_regs.i
@@ -886,6 +886,7 @@
{ "ixCG_FREQ_TRAN_VOTING_6", REG_SMC, 0xc02001c0, 
&ixCG_FREQ_TRAN_VOTING_6[0], 
sizeof(ixCG_FREQ_TRAN_VOTING_6)/sizeof(ixCG_FREQ_TRAN_VOTING_6[0]), 0, 0 },
{ "ixCG_FREQ_TRAN_VOTING_7", REG_SMC, 0xc02001c4, 
&ixCG_FREQ_TRAN_VOTING_7[0], 
sizeof(ixCG_FREQ_TRAN_VOTING_7)/sizeof(ixCG_FREQ_TRAN_VOTING_7[0]), 0, 0 },
{ "ixCG_DISPLAY_GAP_CNTL2", REG_SMC, 0xc0200230, 
&ixCG_DISPLAY_GAP_CNTL2[0], 
sizeof(ixCG_DISPLAY_GAP_CNTL2)/sizeof(ixCG_DISPLAY_GAP_CNTL2[0]), 0, 0 },
+   { "ixCURRENT_PG_STATUS", REG_SMC, 0xc020029c, &ixCURRENT_PG_STATUS[0], 
sizeof(ixCURRENT_PG_STATUS)/sizeof(ixCURRENT_PG_STATUS[0]), 0, 0 },

Re: [PATCH] Add missing CIK devices

[Tom St Denis]

On 13/02/17 10:32 AM, Deucher, Alexander wrote:

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Tom St Denis
Sent: Monday, February 13, 2017 7:46 AM
To: amd-gfx@lists.freedesktop.org
Cc: StDenis, Tom
Subject: [PATCH] Add missing CIK devices

Adds mullins, kabini, and hawaii ASICs to the library.

Signed-off-by: Tom St Denis 


The smu blocks are slightly different on CI dGPUs vs. APUs.  Hawaii should 
follow Bonaire and kabini and mullins should follow kaveri.
Acked-by: Alex Deucher 


Thanks.  Corrected.  Bonaire also had the wrong version.  I've pushed 
out v2 of the patch with those corrections.


Cheers,
Tom
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[PATCH] Fix SMC read/write

[Tom St Denis]

The registers in umr are stored as byte addresses
(mm registers are word addresses).

Signed-off-by: Tom St Denis 
---
 src/app/scan.c| 2 +-
 src/app/set_bit.c | 2 +-
 src/app/set_reg.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/app/scan.c b/src/app/scan.c
index afcadc4c507e..19c97fe1499d 100644
--- a/src/app/scan.c
+++ b/src/app/scan.c
@@ -55,7 +55,7 @@ int umr_scan_asic(struct umr_asic *asic, char *asicname, char 
*ipname, char *reg
case REG_PCIE: fd = 
asic->fd.pcie; scale = 1; break;
case REG_SMC:
if 
(options.read_smc) {
-   fd = 
asic->fd.smc; scale = 4;
+   fd = 
asic->fd.smc; scale = 1;
} else {

continue;
}
diff --git a/src/app/set_bit.c b/src/app/set_bit.c
index 899bf1a17459..d9ee7d8f3a55 100644
--- a/src/app/set_bit.c
+++ b/src/app/set_bit.c
@@ -61,7 +61,7 @@ int umr_set_register_bit(struct umr_asic *asic, char 
*regpath, char *regvalue)
case REG_MMIO: 
fd = asic->fd.mmio; scale = 4; break;
case REG_DIDT: 
fd = asic->fd.didt; scale = 1; break;
case REG_PCIE: 
fd = asic->fd.pcie; scale = 1; break;
-   case REG_SMC:  
fd = asic->fd.smc; scale = 4; break;
+   case REG_SMC:  
fd = asic->fd.smc;  scale = 1; break;
default: return 
-1;
}
if 
(asic->blocks[i]->grant) {
diff --git a/src/app/set_reg.c b/src/app/set_reg.c
index 8c5060f2dbe8..9861170d55c3 100644
--- a/src/app/set_reg.c
+++ b/src/app/set_reg.c
@@ -57,7 +57,7 @@ int umr_set_register(struct umr_asic *asic, char *regpath, 
char *regvalue)
case REG_MMIO: fd = 
asic->fd.mmio; scale = 4; break;
case REG_DIDT: fd = 
asic->fd.didt; scale = 1; break;
case REG_PCIE: fd = 
asic->fd.pcie; scale = 1; break;
-   case REG_SMC:  fd = 
asic->fd.smc; scale = 4; break;
+   case REG_SMC:  fd = 
asic->fd.smc; scale = 1; break;
default: return -1;
}

-- 
2.11.0

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Re: [PATCH] Add new gmc/smu registers

[Tom St Denis]

On 13/02/17 11:35 AM, Nicolai Hähnle wrote:

Hi Tom,

it's probably a good idea to use subject prefixes for umr patches.

git config format.subjectPrefix "PATCH umr"

or edit .git/config accordingly, e.g. for libdrm I have this in
.git/config:

[format]
subjectPrefix = PATCH libdrm

Then format-patch and friends will automatically use [PATCH umr] as a
prefix by default. Makes it a bit easier to follow and grep mailing
lists. (And if you agree, you should then continue to tell other people
to do the same ;))


Ah that's useful.  Thanks. I've added it.

Cheers,
Tom
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[PATCH] drm/amd/amdgpu: Fix flow control in uvd_v4_2_stop()

[Tom St Denis]

Break out of outer loop properly.

Signed-off-by: Tom St Denis 
Reported-by: Dan Carpenter 
---
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 97af4827f652..b34cefc7ebd5 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -401,7 +401,8 @@ static void uvd_v4_2_stop(struct amdgpu_device *adev)
break;
mdelay(1);
}
-   break;
+   if (status & 2)
+   break;
}
 
for (i = 0; i < 10; ++i) {
@@ -411,7 +412,8 @@ static void uvd_v4_2_stop(struct amdgpu_device *adev)
break;
mdelay(1);
}
-   break;
+   if (status & 0xf)
+   break;
}
 
/* Stall UMC and register bus before resetting VCPU */
@@ -424,7 +426,8 @@ static void uvd_v4_2_stop(struct amdgpu_device *adev)
break;
mdelay(1);
}
-   break;
+   if (status & 0x240)
+   break;
}
 
WREG32_P(0x3D49, 0, ~(1 << 2));
-- 
2.11.0

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Re: [PATCH 1/2] drm/amdgpu: implement read_sensor() for pre-powerplay chips

[Tom St Denis]

On 02/13/2017 05:13 PM, Deucher, Alexander wrote:

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Samuel Pitoiset
Sent: Monday, February 13, 2017 5:02 PM
To: amd-gfx@lists.freedesktop.org
Cc: Samuel Pitoiset
Subject: [PATCH 1/2] drm/amdgpu: implement read_sensor() for pre-
powerplay chips

Currently, only the GPU temperature, the shader clock and
eventually the memory clock are implemented. The main goal
is to expose this info to the userspace like Radeon.

Signed-off-by: Samuel Pitoiset 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h |  4 +++-
 drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 26 +
 drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 34
+++
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 41
+
 4 files changed, 104 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 98698dcf15c7..f1876808ff58 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -270,6 +270,8 @@ struct amdgpu_dpm_funcs {
struct amdgpu_ps *cps,
struct amdgpu_ps *rps,
bool *equal);
+   int (*read_sensor)(struct amdgpu_device *adev, int idx, void *value,
+  int *size);

struct amd_vce_state* (*get_vce_clock_state)(struct
amdgpu_device *adev, unsigned idx);
int (*reset_power_profile_state)(struct amdgpu_device *adev,
@@ -293,7 +295,7 @@ struct amdgpu_dpm_funcs {
 #define amdgpu_dpm_read_sensor(adev, idx, value, size) \
((adev)->pp_enabled ? \
(adev)->powerplay.pp_funcs->read_sensor(adev-

powerplay.pp_handle, (idx), (value), (size)) : \

-   -EINVAL)
+   (adev)->pm.funcs->read_sensor((adev), (idx), (value),
(size)))

 #define amdgpu_dpm_get_temperature(adev) \
((adev)->pp_enabled ?\
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 578878d1d4c0..e3a06d6d9e99 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -6936,6 +6936,31 @@ static int ci_dpm_switch_power_profile(struct
amdgpu_device *adev,
return 0;
 }

+static int ci_dpm_read_sensor(struct amdgpu_device *adev, int idx,
+ void *value, int *size)
+{
+   /* size must be at least 4 bytes for all sensors */
+   if (*size < 4)
+   return -EINVAL;
+
+   switch (idx) {
+   case AMDGPU_PP_SENSOR_GFX_SCLK:
+   *((uint32_t *)value) = ci_get_average_sclk_freq(adev);
+   *size = 4;
+   return 0;
+   case AMDGPU_PP_SENSOR_GFX_MCLK:
+   *((uint32_t *)value) = ci_get_average_mclk_freq(adev);
+   *size = 4;
+   return 0;
+   case AMDGPU_PP_SENSOR_GPU_TEMP:
+   *((uint32_t *)value) = ci_dpm_get_temp(adev);
+   *size = 4;
+   return 0;


While you are here you could add AMDGPU_PP_SENSOR_GPU_LOAD.  See 
ci_dpm_debugfs_print_current_performance_level() for the activity percent  
calculations.

Either way:
Reviewed-by: Alex Deucher 


Once these land I can submit a patch to extend umr to read them.  Right 
now I only track sensors from ST/CZ and VI hardware.


Tom
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Re: [PATCH 1/2] drm/amdgpu: implement read_sensor() for pre-powerplay chips

[Tom St Denis]

Hi Samuel,

It would be helpful to modify amdgpu_debugfs_sensor_read() to support 
dpm based sensors as well.  This will let me add it to umr.


If you can swing that in here that would be helpful if not I can submit 
my own patch when this lands.


Cheers,
Tom



On 02/13/2017 05:01 PM, Samuel Pitoiset wrote:

Currently, only the GPU temperature, the shader clock and
eventually the memory clock are implemented. The main goal
is to expose this info to the userspace like Radeon.

Signed-off-by: Samuel Pitoiset 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h |  4 +++-
 drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 26 +
 drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 34 +++
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 41 +
 4 files changed, 104 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 98698dcf15c7..f1876808ff58 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -270,6 +270,8 @@ struct amdgpu_dpm_funcs {
struct amdgpu_ps *cps,
struct amdgpu_ps *rps,
bool *equal);
+   int (*read_sensor)(struct amdgpu_device *adev, int idx, void *value,
+  int *size);

struct amd_vce_state* (*get_vce_clock_state)(struct amdgpu_device 
*adev, unsigned idx);
int (*reset_power_profile_state)(struct amdgpu_device *adev,
@@ -293,7 +295,7 @@ struct amdgpu_dpm_funcs {
 #define amdgpu_dpm_read_sensor(adev, idx, value, size) \
((adev)->pp_enabled ? \

(adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), 
(value), (size)) : \
-   -EINVAL)
+   (adev)->pm.funcs->read_sensor((adev), (idx), (value), (size)))

 #define amdgpu_dpm_get_temperature(adev) \
((adev)->pp_enabled ?\
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 578878d1d4c0..e3a06d6d9e99 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -6936,6 +6936,31 @@ static int ci_dpm_switch_power_profile(struct 
amdgpu_device *adev,
return 0;
 }

+static int ci_dpm_read_sensor(struct amdgpu_device *adev, int idx,
+ void *value, int *size)
+{
+   /* size must be at least 4 bytes for all sensors */
+   if (*size < 4)
+   return -EINVAL;
+
+   switch (idx) {
+   case AMDGPU_PP_SENSOR_GFX_SCLK:
+   *((uint32_t *)value) = ci_get_average_sclk_freq(adev);
+   *size = 4;
+   return 0;
+   case AMDGPU_PP_SENSOR_GFX_MCLK:
+   *((uint32_t *)value) = ci_get_average_mclk_freq(adev);
+   *size = 4;
+   return 0;
+   case AMDGPU_PP_SENSOR_GPU_TEMP:
+   *((uint32_t *)value) = ci_dpm_get_temp(adev);
+   *size = 4;
+   return 0;
+   default:
+   return -EINVAL;
+   }
+}
+
 const struct amd_ip_funcs ci_dpm_ip_funcs = {
.name = "ci_dpm",
.early_init = ci_dpm_early_init,
@@ -6982,6 +7007,7 @@ static const struct amdgpu_dpm_funcs ci_dpm_funcs = {
.set_power_profile_state = ci_dpm_set_power_profile_state,
.reset_power_profile_state = ci_dpm_reset_power_profile_state,
.switch_power_profile = ci_dpm_switch_power_profile,
+   .read_sensor = ci_dpm_read_sensor,
 };

 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index f5a343cb0010..13f323745729 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -3260,6 +3260,39 @@ static int kv_check_state_equal(struct amdgpu_device 
*adev,
return 0;
 }

+static int kv_dpm_read_sensor(struct amdgpu_device *adev, int idx,
+ void *value, int *size)
+{
+   struct kv_power_info *pi = kv_get_pi(adev);
+   uint32_t sclk;
+   u32 pl_index =
+   (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
+   TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
+   TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
+
+   /* size must be at least 4 bytes for all sensors */
+   if (*size < 4)
+   return -EINVAL;
+
+   switch (idx) {
+   case AMDGPU_PP_SENSOR_GFX_SCLK:
+   if (pl_index < SMU__NUM_SCLK_DPM_STATE) {
+   sclk = be32_to_cpu(
+   pi->graphics_level[pl_index].SclkFrequency);
+   *((uint32_t *)value) = sclk;
+   *size = 4;
+   return 0;
+   }
+   return -EINVAL;
+   case AMDGPU_PP_SENSOR_GPU_TEMP

Re: [PATCH 1/2] drm/amdgpu: implement read_sensor() for pre-powerplay chips

[Tom St Denis]

On 02/13/2017 06:40 PM, Samuel Pitoiset wrote:



On 02/14/2017 12:17 AM, Tom St Denis wrote:

Hi Samuel,


Hi Tom,




It would be helpful to modify amdgpu_debugfs_sensor_read() to support
dpm based sensors as well.  This will let me add it to umr.


You mean removing the sanity check (for powerplay boards)? I can do that
in a follow-up patch yes.


As long as the path to or the pointer for read_sensor is not null.

It's been a while since I looked at the pm code but I wonder if a sanity 
check is still required even if you use the macro to read the sensor.


Tom






If you can swing that in here that would be helpful if not I can submit
my own patch when this lands.

Cheers,
Tom



On 02/13/2017 05:01 PM, Samuel Pitoiset wrote:

Currently, only the GPU temperature, the shader clock and
eventually the memory clock are implemented. The main goal
is to expose this info to the userspace like Radeon.

Signed-off-by: Samuel Pitoiset 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h |  4 +++-
 drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 26 +
 drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 34
+++
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 41
+
 4 files changed, 104 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 98698dcf15c7..f1876808ff58 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -270,6 +270,8 @@ struct amdgpu_dpm_funcs {
 struct amdgpu_ps *cps,
 struct amdgpu_ps *rps,
 bool *equal);
+int (*read_sensor)(struct amdgpu_device *adev, int idx, void
*value,
+   int *size);

 struct amd_vce_state* (*get_vce_clock_state)(struct amdgpu_device
*adev, unsigned idx);
 int (*reset_power_profile_state)(struct amdgpu_device *adev,
@@ -293,7 +295,7 @@ struct amdgpu_dpm_funcs {
 #define amdgpu_dpm_read_sensor(adev, idx, value, size) \
 ((adev)->pp_enabled ? \

(adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle,
(idx), (value), (size)) : \
--EINVAL)
+(adev)->pm.funcs->read_sensor((adev), (idx), (value), (size)))

 #define amdgpu_dpm_get_temperature(adev) \
 ((adev)->pp_enabled ?\
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 578878d1d4c0..e3a06d6d9e99 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -6936,6 +6936,31 @@ static int ci_dpm_switch_power_profile(struct
amdgpu_device *adev,
 return 0;
 }

+static int ci_dpm_read_sensor(struct amdgpu_device *adev, int idx,
+  void *value, int *size)
+{
+/* size must be at least 4 bytes for all sensors */
+if (*size < 4)
+return -EINVAL;
+
+switch (idx) {
+case AMDGPU_PP_SENSOR_GFX_SCLK:
+*((uint32_t *)value) = ci_get_average_sclk_freq(adev);
+*size = 4;
+return 0;
+case AMDGPU_PP_SENSOR_GFX_MCLK:
+*((uint32_t *)value) = ci_get_average_mclk_freq(adev);
+*size = 4;
+return 0;
+case AMDGPU_PP_SENSOR_GPU_TEMP:
+*((uint32_t *)value) = ci_dpm_get_temp(adev);
+*size = 4;
+return 0;
+default:
+return -EINVAL;
+}
+}
+
 const struct amd_ip_funcs ci_dpm_ip_funcs = {
 .name = "ci_dpm",
 .early_init = ci_dpm_early_init,
@@ -6982,6 +7007,7 @@ static const struct amdgpu_dpm_funcs
ci_dpm_funcs = {
 .set_power_profile_state = ci_dpm_set_power_profile_state,
 .reset_power_profile_state = ci_dpm_reset_power_profile_state,
 .switch_power_profile = ci_dpm_switch_power_profile,
+.read_sensor = ci_dpm_read_sensor,
 };

 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index f5a343cb0010..13f323745729 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -3260,6 +3260,39 @@ static int kv_check_state_equal(struct
amdgpu_device *adev,
 return 0;
 }

+static int kv_dpm_read_sensor(struct amdgpu_device *adev, int idx,
+  void *value, int *size)
+{
+struct kv_power_info *pi = kv_get_pi(adev);
+uint32_t sclk;
+u32 pl_index =
+(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
+TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
+TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
+
+/* size must be at least 4 bytes for all sensors */
+if (*size < 4)
+return -EINVAL;
+
+switch (idx) {
+case AMDGPU_PP_SENSOR_GFX_SCLK:
+if (pl_index < SMU__NUM_SCLK_DPM_STATE) {
+sclk = be32_to_cpu(
+pi->graphics_level[pl_index].SclkFrequency);
+*((uint32_t *)value) = sclk;
+*size = 4;
+ 

Re: [PATCH] drm/amdgpu: expose amdgpu_sensors on pre-powerplay chips

[Tom St Denis]

On 13/02/17 07:23 PM, Samuel Pitoiset wrote:

Totally untested but as long as read_sensor() has been recently
implemented for dpm based boards, amdgpu_sensors can now be
exposed.

Cc: Tom St Denis 
Signed-off-by: Samuel Pitoiset 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 6f021e70f15f..1a8e3b9a2268 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3202,10 +3202,7 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file 
*f, char __user *buf,
idx = *pos >> 2;

valuesize = sizeof(values);
-   if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
-   r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, 
idx, &values[0], &valuesize);
-   else
-   return -EINVAL;
+   r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);

if (size > valuesize)
return -EINVAL;



NAK, this will oops the kernel if amdgpu.dpm=0 and on powerplay systems 
if powerplay=0.


Otherwise, it seems to work though the GPU_TEMP reads as "5000" on my 
Kaveri (meaning temp of 5C which isn't true).


I suspect the dpm code is reading the wrong register to get the temp but 
we can fix that in another change later on.


Tom
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Re: [PATCH v2] drm/amdgpu: expose amdgpu_sensors on pre-powerplay chips

[Tom St Denis]

On 14/02/17 10:08 AM, Samuel Pitoiset wrote:

Totally untested but as long as read_sensor() has been recently
implemented for dpm based boards, amdgpu_sensors can now be
exposed.

v2: - make sure read_sensor is not NULL on dpm chips
- keep sanity check for powerplay chips

Cc: Tom St Denis 
Signed-off-by: Samuel Pitoiset 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 6f021e70f15f..80821b436aeb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3204,6 +3204,9 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file *f, 
char __user *buf,
valuesize = sizeof(values);
if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, 
idx, &values[0], &valuesize);
+   else if (adev->pm.funcs && adev->pm.funcs->read_sensor)
+   r = adev->pm.funcs->read_sensor(adev, idx, &values[0],
+   &valuesize);
else
return -EINVAL;




Sorry NAK again, even with dpm=0 those function pointers are set and you 
end up inside the dpm code trying to parse data structures that aren't 
initialized.


For instance, this oops on my Kaveri when trying to read SCLK.

[  729.616382] BUG: unable to handle kernel NULL pointer dereference at 
00c4
[  729.616467] IP: [] kv_dpm_read_sensor+0xa0/0xd0 
[amdgpu]

[  729.616619] PGD 232c58067
[  729.616644] PUD 232c4f067
[  729.616670] PMD 0

[  729.616697] Oops:  [#1] SMP
[  729.616726] Modules linked in: fuse amdkfd amd_iommu_v2 amdgpu 
i2c_algo_bit ttm drm_kms_helper drm xt_CHECKSUM iptable_mangle 
ipt_MASQUERADE nf_nat_masquerade_ipv4 iptable_nat nf_nat_ipv4 nf_nat 
nf_conntrack_ipv4 nf_defrag_ipv4 xt_conntrack nf_conntrack tun bridge 
ebtable_filter ebtables ip6table_filter ip6_tables rpcsec_gss_krb5 nfsv4 
dns_resolver nfs fscache bnep vfat fat edac_mce_amd arc4 edac_core 
kvm_amd iwlmvm snd_hda_codec_realtek mac80211 kvm snd_hda_codec_generic 
snd_hda_codec_hdmi snd_hda_intel snd_hda_codec snd_hda_core btusb btrtl 
btbcm btintel iwlwifi bluetooth snd_hwdep cfg80211 snd_seq 
snd_seq_device snd_pcm irqbypass joydev snd_timer snd crct10dif_pclmul 
crc32_pclmul pcspkr ghash_clmulni_intel rfkill fam15h_power sp5100_tco 
k10temp soundcore acpi_cpufreq tpm_tis i2c_piix4 tpm_tis_core
[  729.617499]  shpchp video tpm nfsd auth_rpcgss nfs_acl lockd grace 
sunrpc ata_generic pata_acpi 8021q crc32c_intel garp stp llc serio_raw 
mrp pata_atiixp r8169 mii fjes

[  729.617672] CPU: 0 PID: 1417 Comm: umr Not tainted 4.9.0+ #4
[  729.617720] Hardware name: Gigabyte Technology Co., Ltd. To be filled 
by O.E.M./F2A88XN-WIFI, BIOS F5 04/22/2015

[  729.617802] task: 8e43ef37d880 task.stack: 9d7501594000
[  729.617852] RIP: 0010:[]  [] 
kv_dpm_read_sensor+0xa0/0xd0 [amdgpu]

[  729.618000] RSP: 0018:9d7501597d60  EFLAGS: 00010246
[  729.618046] RAX:  RBX: 9d7501597d98 RCX: 

[  729.618104] RDX:  RSI: 0286 RDI: 
0286
[  729.618162] RBP: 9d7501597d80 R08:  R09: 

[  729.618221] R10:  R11: 8e43ef37d880 R12: 
9d7501597d98
[  729.618285] R13:  R14: 9d7501597d94 R15: 

[  729.618344] FS:  7f6525bfd700() GS:8e43fec0() 
knlGS:

[  729.618411] CS:  0010 DS:  ES:  CR0: 80050033
[  729.618458] CR2: 00c4 CR3: 0002261f6000 CR4: 
000406f0

[  729.618515] Stack:
[  729.618535]  0004 7ffe1e85ca00 8e43f3162100 
0004
[  729.618607]  9d7501597df8 c0e2c637 00401e85ca00 
9d7501597f18
[  729.618676]  9d7501597df8 c0e2dc7d 5403 


[  729.618747] Call Trace:
[  729.618826]  [] 
amdgpu_debugfs_sensor_read+0xf7/0x120 [amdgpu]
[  729.618938]  [] ? 
amdgpu_debugfs_regs_read+0x17d/0x220 [amdgpu]

[  729.619002]  [] full_proxy_read+0x54/0x90
[  729.619049]  [] __vfs_read+0x37/0x150
[  729.619095]  [] ? security_file_permission+0x9b/0xc0
[  729.621382]  [] vfs_read+0x96/0x130
[  729.622997]  [] SyS_read+0x55/0xc0
[  729.624540]  [] entry_SYSCALL_64_fastpath+0x1a/0xa9
[  729.626139] Code: 24 31 c0 41 c7 06 04 00 00 00 41 5c 41 5d 41 5e 41 
5f 5d c3 c1 e8 10 83 e0 1f 83 f8 07 77 ad 48 8d 14 c5 00 00 00 00 5b 48 
29 c2 <41> 8b 84 95 c4 00 00 00 0f c8 41 89 04 24 41 c7 06 04 00 00 00


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Re: [PATCH] drm/amdgpu: expose amdgpu_sensors on pre-powerplay chips

[Tom St Denis]

On 14/02/17 11:57 AM, Deucher, Alexander wrote:

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Samuel Pitoiset
Sent: Monday, February 13, 2017 7:23 PM
To: amd-gfx@lists.freedesktop.org
Cc: StDenis, Tom; Samuel Pitoiset
Subject: [PATCH] drm/amdgpu: expose amdgpu_sensors on pre-powerplay
chips

Totally untested but as long as read_sensor() has been recently
implemented for dpm based boards, amdgpu_sensors can now be
exposed.

Cc: Tom St Denis 
Signed-off-by: Samuel Pitoiset 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 6f021e70f15f..1a8e3b9a2268 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3202,10 +3202,7 @@ static ssize_t
amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
idx = *pos >> 2;

valuesize = sizeof(values);
-   if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs-

read_sensor)

-   r = adev->powerplay.pp_funcs->read_sensor(adev-

powerplay.pp_handle, idx, &values[0], &valuesize);

-   else
-   return -EINVAL;
+   r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);


amdgpu_dpm is handled by both powerplay and non-powerplay so I think if we 
check for that here, we should be fine.  E.g.,
if (amdgpu_dpm != 0)
r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);


And a similar fix in the DRM ioctl too I suppose.

Tom
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Re: [PATCH v2] drm/amdgpu: expose amdgpu_sensors on pre-powerplay chips

[Tom St Denis]

On 14/02/17 12:01 PM, Samuel Pitoiset wrote:



On 02/14/2017 05:41 PM, Tom St Denis wrote:

On 14/02/17 10:08 AM, Samuel Pitoiset wrote:

Totally untested but as long as read_sensor() has been recently
implemented for dpm based boards, amdgpu_sensors can now be
exposed.

v2: - make sure read_sensor is not NULL on dpm chips
- keep sanity check for powerplay chips

Cc: Tom St Denis 
Signed-off-by: Samuel Pitoiset 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 6f021e70f15f..80821b436aeb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3204,6 +3204,9 @@ static ssize_t amdgpu_debugfs_sensor_read(struct
file *f, char __user *buf,
 valuesize = sizeof(values);
 if (adev->powerplay.pp_funcs &&
adev->powerplay.pp_funcs->read_sensor)
 r =
adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx,
&values[0], &valuesize);
+else if (adev->pm.funcs && adev->pm.funcs->read_sensor)
+r = adev->pm.funcs->read_sensor(adev, idx, &values[0],
+&valuesize);
 else
 return -EINVAL;




Sorry NAK again, even with dpm=0 those function pointers are set and you
end up inside the dpm code trying to parse data structures that aren't
initialized.


No worries. I thought that check was enough. Anyway, writing code
without the hardware should be avoided. :)

Can you try the thing suggested by Alex? Because I will need to fix up
the DRM ioctl codepath as well.


Sure, I'm building a module with a amdgpu_dpm check near the top of the 
debugfs read function.


Tom

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Re: [PATCH v2] drm/amdgpu: expose amdgpu_sensors on pre-powerplay chips

[Tom St Denis]

On 14/02/17 12:16 PM, Tom St Denis wrote:

On 14/02/17 12:01 PM, Samuel Pitoiset wrote:

No worries. I thought that check was enough. Anyway, writing code
without the hardware should be avoided. :)

Can you try the thing suggested by Alex? Because I will need to fix up
the DRM ioctl codepath as well.


Sure, I'm building a module with a amdgpu_dpm check near the top of the
debugfs read function.


It seems returning an error code causes it to do "bad things" on read

[root@kaveri linux]# git diff
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

index 80821b4..d63c443 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3198,6 +3198,9 @@ static ssize_t amdgpu_debugfs_sensor_read(struct 
file *f, char __user *buf,

if (size & 3 || *pos & 0x3)
return -EINVAL;

+   if (amdgpu_dpm == 0)
+   return -EINVAL;
+
/* convert offset to sensor number */
idx = *pos >> 2;

That's what I applied on top of Samuel's three patches.

With DPM enabled it works fine obviously, with it disabled the entire 
system hangs.  I think probably because the VFS spins trying to read but 
never finishes...


Any ideas?

Tom
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Re: [PATCH v2] drm/amdgpu: expose amdgpu_sensors on pre-powerplay chips

[Tom St Denis]

On 14/02/17 12:52 PM, Tom St Denis wrote:

On 14/02/17 12:16 PM, Tom St Denis wrote:

On 14/02/17 12:01 PM, Samuel Pitoiset wrote:

No worries. I thought that check was enough. Anyway, writing code
without the hardware should be avoided. :)

Can you try the thing suggested by Alex? Because I will need to fix up
the DRM ioctl codepath as well.


Sure, I'm building a module with a amdgpu_dpm check near the top of the
debugfs read function.


It seems returning an error code causes it to do "bad things" on read

[root@kaveri linux]# git diff
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 80821b4..d63c443 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3198,6 +3198,9 @@ static ssize_t amdgpu_debugfs_sensor_read(struct
file *f, char __user *buf,
if (size & 3 || *pos & 0x3)
return -EINVAL;

+   if (amdgpu_dpm == 0)
+   return -EINVAL;
+
/* convert offset to sensor number */
idx = *pos >> 2;

That's what I applied on top of Samuel's three patches.

With DPM enabled it works fine obviously, with it disabled the entire
system hangs.  I think probably because the VFS spins trying to read but
never finishes...


Nevermind, the issue is umr reading UVD registers when dpm=0 on KV. 
Without sampling UVD the error works properly.


So add those three lines to your patch (and similar in the ioctl) you 
should be fine.


Cheers,
To
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