gEDA-user: installation
Hi, I'm having trouble with the installation, but I don't know if this should be posted hereI just downloaded the new version 20070221 of gEDA and I was wondering how I can install it as root. I can't find anywhere on the site where it limits the installation to just users, but when I try to install this as root, I get the following message: // Cut from Installation Log /// First check if I am running as root. whoami root == Error! == I have experienced a non-recoverable error while performing your installation and must die now. A string describing the error is shown below. Also, please review the log window for more clues about why I am dying, then click the OK button to close the install program, and try to fix the problem. Note that you can try to run the installer with the --log flag set. This will leave a file called Install.log in your run directory holding all compilation spew generated by the installer as it works. You can use this file help debug the install problem. You should not run this installer as root. Please log in as another user and try again. // End Cut /// My previous version (20060124) did not have this problem...i was able to run it from the CD-ROM simply be double-clicking the installer.exe icon (I'm running openSUSE 10.2). This seems like a trivial thing and I can't find any kind of information telling me to install it as a user other than root (in the docs or the geda-bugs message threads). I don't want to create a new user (I don't feel I should have to), but if i need to, I guess I'll have to. I'm just curious as to what changed between the two. I know it's been a year between the versions that I have, but the installer itself shouldn't change. BTW, I have had all of the main software packages installed...I was able to begin installing the material with the other version, so I believe I have all of the necessary system packages installed. If this isn't the place to post this, I'm sorry about that...please send an email to the entity I should post this too. I really would like to get these tools working...I think this suite is very good idea; I just can't get past all of the semantics (you know, the installation). Anyway, Thanks in advance - Expecting? Get great news right away with email Auto-Check. Try the Yahoo! Mail Beta. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog with Xilinx simprims...
Andy Peters wrote: Does iverilog support SDF backannotation? The SDF has the delay information. Here are some information about that and a link to a previous discussion: http://iverilog.wikia.com/wiki/Graffiti#SDF_support Cheers, Guenter ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: installation
On Sun, 18 Mar 2007, Jason Elder wrote: Hi, I'm having trouble with the installation, but I don't know if this should be posted hereI just downloaded the new version 20070221 of gEDA and I was wondering how I can install it as root. Do not install as root. If you install as root, and you need to install system-wide dependencies, the installer becomes confused when it tries to fire up an expect session as root. Old versions of the installer didn't check to see if the user was root. Then, users running as root would find that the installer failed when it tried to install system dependencies. Therefore, I implemented a check to verify that the user was *not* running as root. This change went in to the 20077221 installer (IIRC). In general, using your Linux box in root all the time is dangerous, and is considered bad form. You can make a mistake and harm your system running as root all the time. Run as a regular user. Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
I am a beginner, and I have a lot of exposure to Eagle, so please keep these limitations/biases in mind. I would really like to see the following additions: 1. In gschem, when selecting a footprint, I would like to see the footprint _and_ its description in a popup window. I should be able to browse the footprint library _visually_, basically. 2. In PCB, when I create a Convert buffer contents into an element, it should ask me for a description of the element. This should get embedded in the description field in the element header line. 3. There should be native support for elongated vias (they are called pads in Eagle) when defining an element. Since pin addition while creating a footprint in PCB is done by adding a via, maybe this elongated shape should be added as an option to the via itself, like you can flip between circular and octagonal. And then of course one would need the ability to rotate a via, so that the elongated shape could be aligned the way I want. The current method to define elongated pads (pins in PCB element terminology) is really roundabout, and error-prone, and needs manual editing of the element file in a text editor, if I understand correctly. You have to define (at least) two pads manually, one for the solder layer, one for the component layer, and make sure they both match the pin/via in diameter and centering, and then manually edit the element file to make the pad numbers match the pin number. I feel elongated pads is a sufficiently universally used feature to require native support in the software. I suspect that I am unaware of the heated arguments some of these issues must've seen in the period before I joined the list, in which case please excuse my raking them up again. :) BTW, I like the way PCB has unified the concepts of pads for element footprints, vias, and holes. Good engineering design, I thought. :) Tarun ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: installation
Do not install as root. If you install as root, and you need to
install system-wide dependencies, the installer becomes confused when
it tries to fire up an expect session as root.
Now I'm confused. In all these years of working on Unix, I've always
thought packages need to be installed as root. How else will you keep
the binaries in a place like /opt or /usr/local where all users of your
system can access them?
This is almost a religious issue. In creating the installer I chose
to follow the pre-existing gEDA practice, which is to install by
default somewhere underneath the user's ${HOME} directory.
However, I personally recommend users to install into a new directory,
/usr/local/geda, and then set their $PATH variables to point to it. I
think the installer will create this new directory, and ask for the
root password if needed. It's been a while since I looked.
Anyway, it's best to install into /usr/local/geda (or some similar
system-wide, but independent directory) because if you ever need to
remove your gEDA installation, you can just nuke the whole directory.
If you install into /usr/local, then you've got to rm each and every
gEDA file independently, which is quite a PITA.
More about uninstalling the gEDA Suite is here:
http://geda.seul.org/wiki/geda:gedasuite_installation#how_do_i_uninstall_the_geda_suite
Stuart
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: installation
This is almost a religious issue. Aren't most questions which have many correct answers? :) However, I personally recommend users to install into a new directory, /usr/local/geda, and then set their $PATH variables to point to it... Great. This is really I wanted to know. I wanted to know how a user would install in some system area which would be outside all home directories, and how he would set the ownership of the package files to be someone other than the human users of the system. If the installer does this, that's all that's needed, IMHO. Tarun -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
I assume that's the reason for PCB, too. No, pcb's plugins are very tightly coupled to the internal data structures. The reason I added pcb's plugins was to let people define their own actions without the cvs-build-merge issues, not as a generic way to allow for future expansion. You have the order backwards. Design the file format first, then the data structures. The file format should be designed as a language for expressing what you want to express. PCB has a second format it uses called a resource file. It's a semi-lisp-ish format that allows for arbitrarily nested data, without the complexities of XML (the whole parser is about a page of code). It could be used to hold pretty much anything, but it isn't designed for the data. * Finally, how should PCB behave with a hierarchical schematic? Right click on a symbol, select go inside, and another drawing opens up showing what's inside. gschem also should act this way. I think pcb blocks should be translucent. You should have some idea of the physical contents of a block even when you're not editing it. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
3. There should be native support for elongated vias (they are called pads in Eagle) when defining an element. The way to do this in pcb is to put a pin and a pad in the same place. The pin gives you the drill hole, and the pad defines the elongated copper shape. I suspect that I am unaware of the heated arguments some of these issues must've seen in the period before I joined the list, in which case please excuse my raking them up again. :) It's not heated, it's just nobody has had the time to do it right, yet. For example, a true multipin (my name) would need to know more about the physical layer stack than pcb currently knows. But I do envision a multipin having the ability to independently specify: * top, inner, and bottom shapes * copper shapes, including hole-to-edge distance and radius of each corner * pads defined by polygons * copper, paste, and mask each independently defined The current plan is to defer this until after the layer type flags project is done, as that project gives us proper mask, paste, etc layers. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus Verilog with Xilinx simprims...
On Mar 17, 2007, at 7:56 PM, CSB wrote: Wow, thanks for the quick responses ! Does iverilog support SDF backannotation? The SDF has the delay information. Ah ! Now you mention it, I remember removing a $sdf_annotate line from the generated verilog file. It was causing an error with vvp, so I just removed the offending line and quickly forgot about it... The error is: $sdf_annotate: This task is not defined by any modules. I just found a topic about iSDF in this mailing list; I will see what I can do with that. Ah! Now that you mention it, I remember running into $sdf_annotate issues with ModelSim, too, and the problem was how the Xilinx tools generated the Verilog timing sim source. The trick was to delete the $sdf_annotate line in the Verilog source, and then tell ModelSim to use the correct SDF through the GUI (there's also a command-line switch for it). Then it all worked. The Xilinx WebCase I opened about this was handled in the usual Xilinx manner (we'll fix it in a later revision of the tools). Now that I'm back on the VHDL side of the fence, I haven't paid attention to this. Any specific reason why you're running a post-fit simulation? The RTL simulation tells you if your logic is functionally correct, and the static timing analyzer (using your timing constraints) tells you if you've met timing. If both are good, there's no need to run a post-fit simulation. Well, that's where I'm most confused. I followed some instructions that explained how to use TestBencher (part of ISE). Is that what you are referring to? What I saw of it didn't impress me much... For my design, I didn't specify any timing constraints since I'm not concerned so much about speed as correct operation. Also, the amount of specify-able stuff was overwhelming, so I decided to skip that part 8~) The simplest timing constraint is simply clock frequency. That covers 99% of most designs. The other basic constraints deal with input and output delays through the I/O pins; basically, you specify what you need the input set-up and hold to be so you can correctly capture incoming synchronous signals, and you can specify what you'd like the maximum clock-to-out time based on an external synchronous device's requirements. Look for OFFSET IN and OFFSET OUT. If you're doing an asynchronous design, then you're on your own! Current CPLD and FPGA methodologies don't lend themselves well to async design. My reasoning was that I would run a post-fit simulation, and see if there were any glitches, or unusual operation. Mostly, I was thinking about timing hazards. But your comment makes me ask: does the fitted design guarantee a glitch-free operation ? (the only remaining issue would be speed, hence the timing constraints) I should also add that I'm fairly new to digital design, so I might be missing the point entirely. Certainly the fitted design will have glitches, as delays through various paths will be different. The point of synchronous design is that you can ignore those glitches; all you care about is if the inputs to all of your registers are settled by the setup time before the clock edge. And for each clock, that is what the static timing analyzer tells you -- the length of all paths through all registers. As long as the prop delay from register A through logic to the D input of register B is less than the clock period, you win. The timing analyzer accounts for register clock-to-out delay and register input setup and hold. If your design is purely combinatorial, then of course you will have glitches, and remember that a post-fit timing simulation will show you these glitches for the particular routing the tools just used, which may change for each place-and-route run as you tweak the design. The delays are worst-case (high temperature, low supply voltage, wrong phase of the moon), which means that your design will probably be better (path delays not as long). How much Better is not defined, and anyways you should never rely on datasheet typical values. One final comment: Rather than staring at a screen full of logic traces looking for set-up and hold failures, read up about Verilog's $setup and $hold and other timing-check functions that you can use in your test bench. Computers are good at this sort of tedious checking! -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: File corrupted after segmentation fault in pcb
On Sat, Mar 17, 2007 14:01, DJ Delorie wrote: If you edit the .pcb file and remove all the Rats[] entries (they're all at the end) it will at least load. However, all the layer information is missing, so you'll have to re-add all the layers and redefine the layer groups. Well, I guess the old saying Men don't take backup, they cry is up for it now... If I take a look at the bright side, this incident did convinced me to finish my backup script which takes an hourly snapshot. Backup is not so bad after all. Do you have a save file in /tmp, or in the same directory as the original file but with '-' appended? I saw that there was some backup files placed in /tmp, but not the ones I needed :-(. But thanks for the suggestion. Thanks for the help! Cheers, Mikael ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: File corrupted after segmentation fault in pcb
go look in your /tmp directory for unintentional back ups Mikael W. Bertelsen wrote: On Sat, Mar 17, 2007 14:01, DJ Delorie wrote: If you edit the .pcb file and remove all the Rats[] entries (they're all at the end) it will at least load. However, all the layer information is missing, so you'll have to re-add all the layers and redefine the layer groups. Well, I guess the old saying Men don't take backup, they cry is up for it now... If I take a look at the bright side, this incident did convinced me to finish my backup script which takes an hourly snapshot. Backup is not so bad after all. Do you have a save file in /tmp, or in the same directory as the original file but with '-' appended? I saw that there was some backup files placed in /tmp, but not the ones I needed :-(. But thanks for the suggestion. Thanks for the help! Cheers, Mikael ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Tool to calculate Nyquist-plot or impedance?
Wen wrote: Hi list, I am going to do Equivalent circuit fitting for a university project with impedance spectroscopy. I am looking for a tool that first allows to define (via a graphic interface would be best) an electric circuit made of resistors, conductors, inductors and maybe constant phase and warburg elements. What i need is a Nyquist-plot of that circuit- a plot that shows the imaginary (vert. axis) and the real (horiz. axis) part of the impedance of the defined circuit for a wide range of frequencies. So I am either looking for an application that outputs that Nyquist-plot directly or that calculates the impedance analytically with the frequency as a parameter, so that I can use it for a matlab/octave-script. Is there a geda-tool thats able to do one of those two things? I did not see something like that in the tutorial-part nor find it in the gschem-interface? If not, does somebody know other applications that are able to handle this? Thanks in advance, Wen gnucap. gnucap is a circuit simulator and it is very easy to describe your circuit and do an ac analysis of it to directly measure the impedance. You can take that data and feed it back to matlab or octave. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Tool to calculate Nyquist-plot or impedance?
On Sunday 18 March 2007 17:42, Wen wrote: Hi list, I am going to do Equivalent circuit fitting for a university project with impedance spectroscopy. I am looking for a tool that first allows to define (via a graphic interface would be best) an electric circuit made of resistors, conductors, inductors and maybe constant phase and warburg elements. I had to look up warburg elements. Gnucap has constant phase elements. Just specify a complex value for a resistor or dependent source. It looks like it would be easy to make a plugin for the warburg elements. It will be even easier when I get the Verilog-AMS compiler working. For now, you can make a bm function plugin, using the ones provided as a basis. Then a resistor or whatever could have a value that follows the warburg function. Or, you could use the model compiler to make a new element, as a plugin. gnucap plugins allow you to add or replace almost anything at run time using the attach command. You write in C++, compile to a .so and attach it. To get this functionality you need the latest development snapshot. What i need is a Nyquist-plot of that circuit- a plot that shows the imaginary (vert. axis) and the real (horiz. axis) part of the impedance of the defined circuit for a wide range of frequencies. Gnucap has impedance probes, so it will give you that directly. You can ask for magphase, or realimaginary. Just .print ac zreal(outnode) zimag(outnode) or something like that. You can plot it with octave, gnuplot, R, tcl-tk, or many other tools. gwave doesn't do this kind of plot. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
3. There should be native support for elongated vias (they are called pads in Eagle) when defining an element. The way to do this in pcb is to put a pin and a pad in the same place. The pin gives you the drill hole, and the pad defines the elongated copper shape. Yes, I've tried this with my footprints. The problem is that you need two pads (for a traditional double-layer footprint) and you need to edit the text file of the element to set the numbering of the pads. (Can I set the pad number through the GUI of PCB the way I can for the pin number by pressing 'n'?) This approach is error-prone, I felt. When I open up the text file of the element, I see a list of pads but I don't know which two pads are associated with pin 1, and so on. It's not heated, it's just nobody has had the time to do it right, yet. For example, a true multipin (my name) would need to know more about the physical layer stack than pcb currently knows. But I do envision a multipin having the ability to independently specify: * top, inner, and bottom shapes * copper shapes, including hole-to-edge distance and radius of each corner * pads defined by polygons * copper, paste, and mask each independently defined The current plan is to defer this until after the layer type flags project is done, as that project gives us proper mask, paste, etc layers. Yes, I've been reading some of the discussions about the multipin and the layer-type projects, and I got the sense that these would make a lot of the work easier for elongated pads. I think it's a good idea to do it in the sequence you intend. Will make the implementation a whole lot cleaner and more powerful internally. Tarun -- ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
You may want to try one of the many footprint scripts that are around. Making the footprints in a batch using a script is a lot less error prone than one by one in the GUI. If you are looking for DIPs or SIP headers with rounded pads over pins you could try my website. Actually I've seen some of those scripts and they are lovely for the kind of things they do. But I need to build much simpler footprints like TO220 devices, but with elongated pads. These are best done by hand, I guess. I even like TO92 to have elongated pads. I suspect I'm just unsure of my soldering skills and like larger pads, that's all. :) One area where I'll be developing scripts is for simple capacitors. I want pretty-looking non-polar and cylindrical electrolytic caps of various sizes. (No elongated pads needed.) Resistors I've already done by hand. Tarun ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: File corrupted after segmentation fault in pcb
On Sun, 18 Mar 2007, Mikael W. Bertelsen wrote: If I take a look at the bright side, this incident did convinced me to finish my backup script which takes an hourly snapshot. Backup is not so bad after all. Why don't you use some sort of version control instead? :) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
On 3/18/07, C P Tarun [EMAIL PROTECTED] wrote:
You may want to try one of the many footprint scripts that are around.
Making the footprints in a batch using a script is a lot less error prone
than one by one in the GUI.
If you are looking for DIPs or SIP headers with rounded pads over pins
you could try my website.
Actually I've seen some of those scripts and they are lovely for the kind
of things they do. But I need to build much simpler footprints like TO220
devices, but with elongated pads. These are best done by hand, I guess.
I even like TO92 to have elongated pads. I suspect I'm just unsure of my
soldering skills and like larger pads, that's all. :)
A script to place TO220 pads can be pretty simple (see below). The
poorly named routine element_add_pin_oval overlays a pin, a rounded pad
on the component side and a rounded pad on the solder side.
Adding a simple silkscreen would be one or two more lines of code.
(* jcl *)
use strict;
use warnings;
use Pcb_8;
my $Pcb = Pcb_8 - new(debug = 1);
$Pcb - element_begin(description = 'TH',
output_file =
tmp/ . 'TO220',
dim = 'mils');
my $pin_num = 1;
my @pos = (-100, 0, 0, 0, 100, 0);
while (@pos) {
my ($x, $y) = splice @pos, 0, 2;
$Pcb - element_add_pin_oval(x = $x,
y = $y,
width = 80,
length = 66,
name = '',
pin_number = $pin_num++,
clearance = 10,
drill_hole = 46,
mask = 10);
}
$Pcb - element_output();
--
http://www.luciani.org
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
A script to place TO220 pads can be pretty simple (see below). The poorly named routine element_add_pin_oval overlays a pin, a rounded pad on the component side and a rounded pad on the solder side. Very interesting. What's Pcb_8? Where do I find it? I'm looking through your Website to see if there's some Perl module there. Tarun ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
Very interesting. What's Pcb_8? Where do I find it? I'm looking through your Website to see if there's some Perl module there. Found Pcb_8 in your Perl library documentation. Thanks. Tarun ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: File corrupted after segmentation fault in pcb
On Mar 18, 2007, at 8:06 PM, Igor2 wrote: On Sun, 18 Mar 2007, Mikael W. Bertelsen wrote: If I take a look at the bright side, this incident did convinced me to finish my backup script which takes an hourly snapshot. Backup is not so bad after all. Why don't you use some sort of version control instead? :) What if the crash occurred before he was ready to commit a change? -a ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: File corrupted after segmentation fault in pcb
On Sun, 18 Mar 2007, Andy Peters wrote: On Mar 18, 2007, at 8:06 PM, Igor2 wrote: On Sun, 18 Mar 2007, Mikael W. Bertelsen wrote: If I take a look at the bright side, this incident did convinced me to finish my backup script which takes an hourly snapshot. Backup is not so bad after all. Why don't you use some sort of version control instead? :) What if the crash occurred before he was ready to commit a change? He was talking about hourly snapshots; normally with a version control, you prefer to commit changes in small sets, and I assume creating such a small changeset takes less time than an hour :) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Design Flow Roadmap starting point
A script to place TO220 pads can be pretty simple (see below). The poorly named routine element_add_pin_oval overlays a pin, a rounded pad on the component side and a rounded pad on the solder side. I have been reading your (excellently-formatted reference-class) documentation on your library. The documentation does not mention that add_pin_oval adds two pads on two layers... it seems to say that this is a hybrid object consisting of a pad and a pin with the same centre point. Is the document out of sync with the library? Tarun ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
