Re: gEDA-user: little slivers from pours
On Sun, Jan 10, 2010 at 6:04 PM, Ben Jackson b...@ben.com wrote: On Sat, Jan 09, 2010 at 05:41:05PM -0800, Ben Jackson wrote: I meant automatic solutions which would enforce the normal DRC rules on the slivers, eliminating any smaller than the minimum trace width. (replying to myself) Actually, I think I just figured out how to fix it AND do it live. I'll look into it. If I don't post back to the list in a few days someone pester me. ;-) Did you ever get time figure this out? Jared ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter update?
On Tue, 23 Feb 2010 11:16:45 +1300, Anthony Blake wrote: I don't get a lot of time atm.. please jump in =) Ok, then. Can you compile a list of tasks that need to be accomplished before the topo router is ready for general use? The smaler the individual tasks, the more likely they can be tackled by low time hackers like me... ---(kaimartin)--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Is it possible to do square holes in PCB?
Hello all, I did an oval shape hole once by using three overlapping round drill holes, worked fine. maybe you can do the same with 6 small round holes: ooo ooo ooo Cheers, Robert -Original Message- From: Dave N6NZ n...@arrl.net Reply-to: gEDA user mailing list geda-user@moria.seul.org To: gEDA user mailing list geda-user@moria.seul.org Subject: Re: gEDA-user: Is it possible to do square holes in PCB? Date: Sun, 21 Feb 2010 15:08:15 -0800 Mailer: Apple Mail (2.1077) On Feb 21, 2010, at 2:01 PM, Mark Rages wrote: On Sun, Feb 21, 2010 at 1:55 PM, Anthony Shanks yamazak...@gmail.com wrote: Some parts have mounting brackets that are square, not round. Yes I know I can make a equivalent circlular hole that would fit but it wastes a lot of space doing that and it interferes with routing. Have you talked to your board house about this? I wonder what happens if you specify a reuleaux drill in the fab drawing... How large is the square that you need? At some point, this is just another routed cut-out. You end up with a corner radius the size of the router bit in use, or else you can route a little past the corner to clear the corner of your square bracket. You would have to talk to your PCB house, but I'd be thinking along the lines of agreeing on what router bit is going to be used, and then adding a layer where the tracks represent the centerline of the routing operations. Wacky board shapes done by a CNC router are nothing new, routed cut-outs fall into that category. I'm sure your PCB house has a preferred way of getting the information. They will no doubt charge you the full freight, though, I don't know of any prototype service that does non-rectangular boards, although they might exist. -dave ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Eagle to gEDA conversion path??
On Mon, 22 Feb 2010 21:53:46 -0800, Dave N6NZ wrote: Really? Is there a use for gEDA-Eagle? There is at my place. I represent an island of geda in an eagle using environment. Eagle is pretty popular in German academia. If I want to share my work with them, a conversion path to eagle would help a lot. I never would have cared about Eagle, except that the RepRap PCB's are done with Eagle. Same here. Sometimes I have to reuse eagle projects made by others. ---(kaimartin)--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: offering a new release of vbpp
Hello Jimen, Are you still at this address? I have a new version of vbpp to offer. Can you please grant me access to http://svn.seul.org/viewcvs/viewvc.cgi/eda/vbpp/?root=SEUL You can find my version of vbpp here: http://www.verilog.net/vbpp-1.2.0.tar.gz Thanks, Martin On Tue, 9 Feb 2010, Martin d Anjou wrote: Hello Jimen, Are you still at this address? I have worked on vbpp and posted a new release at http://www.verilog.net/vbpp-1.2.0.tar.gz How do I upload it here: http://svn.seul.org/viewcvs/viewvc.cgi/eda/vbpp/?root=SEUL Regards, Martin d'Anjou ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: analog/code co-simulation and schematics and netlists for silicon
al davis wrote: I proposed a translator system, using an intermediate language, to translate both ways between schematic, layout, and simulation. It needs to happen. I've got a phone call to Reid Wenders of Triad scheduled this PM. Anyone have any ideas you'd like mentioned to him? Questions I should ask? I'm just planning on telling him the status of verilog-ams backend of gnetlist and that it can run some simulations from a netlist -- the way it needs to be for many chip design/verification work flows. Just in case there's any development money or new developers available. Reference: http://www.edn.com/article/CA6670945.html “We have been working with Keil to simulate mixed-signal peripherals. But, eventually, we are going to need a full analog/mixed-signal simulator on the desktop—something that can pull together Verilog, Spice, and software simulations on the desktop for a low price,” he says. “We are still searching.” Reid Wenders EDN, 7/23/2009 John Griessen Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gschem text line spacing in postscript
Hi, I noticed a small issue with the line spacing in the postscript output of gschem. It appears to be that the text line spacing is not consistent with the font scaling when output to postscript. Here is a screenshot to show the difference between the gschem scaling and the output postscript scaling, see http://www.engineersimplicity.com/gEDA/text_line_spacing.png I'm running a custom compiled version with the cairo/pango font scaling set to 1.0 and suspect that the spacing issue is linked to this. Is there another factor which influences line spacing? Thanks, Duncan -- Turn ideas into products - http://www.engineersimplicity.com The Art of Engineering - http://blog.engineersimplicity.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem text line spacing in postscript
On Tue, 2010-02-23 at 22:07 +0200, Duncan Drennan wrote: Hi, I noticed a small issue with the line spacing in the postscript output of gschem. It appears to be that the text line spacing is not consistent with the font scaling when output to postscript. Here is a screenshot to show the difference between the gschem scaling and the output postscript scaling, see http://www.engineersimplicity.com/gEDA/text_line_spacing.png I'm running a custom compiled version with the cairo/pango font scaling set to 1.0 and suspect that the spacing issue is linked to this. Is there another factor which influences line spacing? Thanks, Duncan Hmm... this will all be fixed when I get my backside into gear and finish up the cairo printing support... until then, I'm not sure.. It might be something we can fix in the existing printing code, but it could also just be a failing of the new cairo text rendering to match up with the old printing code. I attempted to match on-screen rendering before / after cairo, but never cross-checked how the printing output used to match up. Best regards, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem text line spacing in postscript
On Tue, 2010-02-23 at 22:01 +, Peter Clifton wrote: Hmm... this will all be fixed when I get my backside into gear and finish up the cairo printing support... until then, I'm not sure.. It might be something we can fix in the existing printing code, but it could also just be a failing of the new cairo text rendering to match up with the old printing code. I attempted to match on-screen rendering before / after cairo, but never cross-checked how the printing output used to match up. Yep.. the printed output uses a completely different way of calculating the line height. (Cairo + pango just do it for us in the renderer). There is some magic going on which is specific only to printing: libgeda/include/libgeda/defines.h:#define LINE_SPACING2.0 libgeda/src/o_text_basic.c static int o_text_height(const char *string, int size) which returns: 26*size/2*(1+LINE_SPACING*(line_count-1)) The printing code offsets by (char_height*LINE_SPACING) Where char_height is o_text_height(a, o_current-text-size); IE, 13 * o_current-text-size A better conversion to mils is probably 1000 (mils/inch) / 72 (pt/inch) = 13.89 mils/pt. BUT.. this should also be using the gEDA font size - points conversion. The 13 vs 13.89 discrepency is already incorporated in the 1.3 factor shipped by default. The short answer.. might be to change the 26*size/2 * ... to be 13.89 * (float)size * (float)(line_count - 1) And get rid of LINE_SPACING all together. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: analog/code co-simulation and schematics and netlists for silicon
I have daydreamed about the possibility of linking gEDA with qucs and simavr/gdb for example. To be able to create a circuit layout and perform harmonic ballance simulation combined with microcontroller code simulation... Oh, and while I daydream, an integrated tool for doing FEM analysis the pcb design to improve RF circuit layout. I am only new to gEDA so forgive me if I some of this is already possible.. From the little I have seen getting the circuit information out of gEDA must be fairly straight forward - it is getting the other tools to play nicely that would be tricky. This is something that I certainly would like to look into. Geoff Australia On Wed, Feb 24, 2010 at 4:49 AM, John Griessen j...@ecosensory.com wrote: al davis wrote: I proposed a translator system, using an intermediate language, to translate both ways between schematic, layout, and simulation. It needs to happen. I've got a phone call to Reid Wenders of Triad scheduled this PM. Anyone have any ideas you'd like mentioned to him? Questions I should ask? I'm just planning on telling him the status of verilog-ams backend of gnetlist and that it can run some simulations from a netlist -- the way it needs to be for many chip design/verification work flows. Just in case there's any development money or new developers available. Reference: http://www.edn.com/article/CA6670945.html “We have been working with Keil to simulate mixed-signal peripherals. But, eventually, we are going to need a full analog/mixed-signal simulator on the desktop—something that can pull together Verilog, Spice, and software simulations on the desktop for a low price,” he says. “We are still searching.” Reid Wenders EDN, 7/23/2009 John Griessen Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem text line spacing in postscript
The attached patch should make things a little closer between on-screen
and print-out.
Apparently this isn't the whole story though, on my box at least, Pango
seems to be using a little inter-line spacing. The calculations with
this patch assume that a 12 point font has 12/72 inches between each
baseline.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
diff --git a/libgeda/include/libgeda/defines.h b/libgeda/include/libgeda/defines.h
index d1f0422..cf7432a 100644
--- a/libgeda/include/libgeda/defines.h
+++ b/libgeda/include/libgeda/defines.h
@@ -121,9 +121,6 @@
/* Warning: it MUST be a string. */
#define TAB_CHAR_MODEL b
-/* multi text line spacing (multipled times character height) */
-#define LINE_SPACING2.0
-
/* The conn modes for type */
#define CONN_NULL 0
#define CONN_ENDPOINT 1
diff --git a/libgeda/src/o_text_basic.c b/libgeda/src/o_text_basic.c
index cd6bac8..e7f79b8 100644
--- a/libgeda/src/o_text_basic.c
+++ b/libgeda/src/o_text_basic.c
@@ -610,35 +610,6 @@ void o_text_print_text_string(FILE *fp, char *string, int unicode_count,
}
-/*! \brief calculates the height of a text string
- * \par Function Description
- * This function calculates the height of a \a string depending
- * on it's text \a size. The number of lines and the spacing
- * between the lines are taken into account.
- *
- * \param [in] string the text string
- * \param [in] sizethe text size of the character
- * \return the total height of the text string
- */
-static int o_text_height(const char *string, int size)
-{
- int line_count = 0;
-
- if (string == NULL) {
-return 0;
- }
-
- /* Get the number of lines in the string */
- line_count = o_text_num_lines(string);
-
- /* 26 is the height of a single char (in mils) */
- /* which represents a character which is 2 pts high */
- /* So size has to be divided in half */
- /* and it's added the LINE_SPACING*character_height of each line */
- return(26*size/2*(1+LINE_SPACING*(line_count-1)));
-}
-
-
/*! \brief print a text object into a postscript file
* \par Function Description
* This function writes the postscript representation of the text object
@@ -766,8 +737,9 @@ void o_text_print(TOPLEVEL *toplevel, FILE *fp, OBJECT *o_current,
break;
}
- char_height = o_text_height(a, o_current-text-size);
- fprintf(fp,%s %f [,centering_control,(float)(char_height*LINE_SPACING));
+ font_size = o_text_get_font_size_in_points (toplevel, o_current)
+/ 72.0 * 1000.0;
+ fprintf(fp,%s %f [,centering_control, font_size);
/* split the line at each newline and print them */
p = output_string; /* Current point */
@@ -790,8 +762,6 @@ void o_text_print(TOPLEVEL *toplevel, FILE *fp, OBJECT *o_current,
/* Collect pertinent info about the text location */
x = o_current-text-x;
y = o_current-text-y;
- font_size = o_text_get_font_size_in_points (toplevel, o_current)
-/ 72.0 * 1000.0;
fprintf(fp,] %d %d %d %f text\n,angle,x,y,font_size);
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Re: gEDA-user: analog/code co-simulation and schematics and netlists for silicon
On Wed, 2010-02-24 at 09:46 +1100, Geoff Swan wrote: I have daydreamed about the possibility of linking gEDA with qucs and simavr/gdb for example. To be able to create a circuit layout and perform harmonic ballance simulation combined with microcontroller code simulation... Oh, and while I daydream, an integrated tool for doing FEM analysis the pcb design to improve RF circuit layout. I am only new to gEDA so forgive me if I some of this is already possible.. From the little I have seen getting the circuit information out of gEDA must be fairly straight forward - it is getting the other tools to play nicely that would be tricky. This is something that I certainly would like to look into. Geoff Australia Doing marine renewables, I vote for integrated computational fluid dynamics + electrical simulation - although at this point in time, I'm looking at the gEDA tools and thinking building those (including gwave!!) is a piece of cake compared to building OpenFOAM. (OpenFOAM is a GPL'd FEA package with a NIH build-system). -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem text line spacing in postscript
On Tue, 2010-02-23 at 23:02 +, Peter Clifton wrote:
The attached patch should make things a little closer between on-screen
and print-out.
Apparently this isn't the whole story though, on my box at least, Pango
seems to be using a little inter-line spacing. The calculations with
this patch assume that a 12 point font has 12/72 inches between each
baseline.
This one adds a 12% leading to the text spacing for print, causing it to
pretty well match my on-screen leading. YMMV depending on what fonts
your system chooses.
Best regards,
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
diff --git a/libgeda/include/libgeda/defines.h b/libgeda/include/libgeda/defines.h
index d1f0422..cf7432a 100644
--- a/libgeda/include/libgeda/defines.h
+++ b/libgeda/include/libgeda/defines.h
@@ -121,9 +121,6 @@
/* Warning: it MUST be a string. */
#define TAB_CHAR_MODEL b
-/* multi text line spacing (multipled times character height) */
-#define LINE_SPACING2.0
-
/* The conn modes for type */
#define CONN_NULL 0
#define CONN_ENDPOINT 1
diff --git a/libgeda/src/o_text_basic.c b/libgeda/src/o_text_basic.c
index cd6bac8..6830674 100644
--- a/libgeda/src/o_text_basic.c
+++ b/libgeda/src/o_text_basic.c
@@ -89,6 +89,14 @@
*/
#define GEDA_FONT_FACTOR 1.3
+/*! \brief Scale factor font height and line-spacing (for print only)
+ *
+ * \par Description
+ * Specifies the scale factor between the nominal font size and the inter-
+ * line spacing used to render it when printing.
+ */
+#define PRINT_LINE_SPACING 1.12
+
/*! Default setting for text draw function. */
void (*text_draw_func)() = NULL;
@@ -610,35 +618,6 @@ void o_text_print_text_string(FILE *fp, char *string, int unicode_count,
}
-/*! \brief calculates the height of a text string
- * \par Function Description
- * This function calculates the height of a \a string depending
- * on it's text \a size. The number of lines and the spacing
- * between the lines are taken into account.
- *
- * \param [in] string the text string
- * \param [in] sizethe text size of the character
- * \return the total height of the text string
- */
-static int o_text_height(const char *string, int size)
-{
- int line_count = 0;
-
- if (string == NULL) {
-return 0;
- }
-
- /* Get the number of lines in the string */
- line_count = o_text_num_lines(string);
-
- /* 26 is the height of a single char (in mils) */
- /* which represents a character which is 2 pts high */
- /* So size has to be divided in half */
- /* and it's added the LINE_SPACING*character_height of each line */
- return(26*size/2*(1+LINE_SPACING*(line_count-1)));
-}
-
-
/*! \brief print a text object into a postscript file
* \par Function Description
* This function writes the postscript representation of the text object
@@ -661,7 +640,7 @@ void o_text_print(TOPLEVEL *toplevel, FILE *fp, OBJECT *o_current,
char *output_string = NULL;
char *name = NULL;
char *value = NULL;
- int x, y, angle, len, char_height;
+ int x, y, angle, len;
float font_size;
@@ -766,8 +745,9 @@ void o_text_print(TOPLEVEL *toplevel, FILE *fp, OBJECT *o_current,
break;
}
- char_height = o_text_height(a, o_current-text-size);
- fprintf(fp,%s %f [,centering_control,(float)(char_height*LINE_SPACING));
+ font_size = o_text_get_font_size_in_points (toplevel, o_current)
+/ 72.0 * 1000.0;
+ fprintf(fp,%s %f [,centering_control, font_size * PRINT_LINE_SPACING);
/* split the line at each newline and print them */
p = output_string; /* Current point */
@@ -790,8 +770,6 @@ void o_text_print(TOPLEVEL *toplevel, FILE *fp, OBJECT *o_current,
/* Collect pertinent info about the text location */
x = o_current-text-x;
y = o_current-text-y;
- font_size = o_text_get_font_size_in_points (toplevel, o_current)
-/ 72.0 * 1000.0;
fprintf(fp,] %d %d %d %f text\n,angle,x,y,font_size);
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Re: gEDA-user: Toporouter update?
Kai-Martin Knaak wrote: On Tue, 23 Feb 2010 11:16:45 +1300, Anthony Blake wrote: I don't get a lot of time atm.. please jump in =) Ok, then. Can you compile a list of tasks that need to be accomplished before the topo router is ready for general use? The smaler the individual tasks, the more likely they can be tackled by low time hackers like me... For sure. It would require some careful consideration though.. I'll get back to you within a week. Cheers, Anthony ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: analog/code co-simulation and schematics and netlists for silicon
On Tuesday 23 February 2010, John Griessen wrote: Anyone have any ideas you'd like mentioned to him? Questions I should ask? I'm just planning on telling him the status of verilog-ams backend of gnetlist and that it can run some simulations from a netlist -- the way it needs to be for many chip design/verification work flows. Just in case there's any development money or new developers available. It really doesn't work .. sorry. Gnucap (the development version) will take netlists in Spice, Spectre, or Verilog formats. The gnetlist backend only supports a small subset of what could be done. For years, I have accepted the fact that the generated netlist has some flaws and requires manual editing. I can deal with it, unhappily, but most beginners can't, and most people who might think of migrating won't even if they could. We really need a more general translator, that isn't based on the gschem format or any other tool specific format. I have a start, but need help. Reference: http://www.edn.com/article/CA6670945.html “We have been working with Keil to simulate mixed-signal peripherals. But, eventually, we are going to need a full analog/mixed-signal simulator on the desktop—something that can pull together Verilog, Spice, and software simulations on the desktop for a low price,” he says. “We are still searching.” Reid Wenders EDN, 7/23/2009 If I can get some help with Gnucap, this will happen. Actually, I do have some help now, but need more, especially people to work on user oriented issues, what most people think of as the easy part. Gnucap was designed for mixed signal from the beginning, long before there was such a thing as Verilog-AMS. What is lacking is a fully working model compiler. There is work in progress with Icarus to make this happen. The main missing piece now is a back-end for Icarus that matches the gnucap interface. That is really the only critical missing piece. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Message and Library windows
On Mon, 2010-02-22 at 20:02 -0800, Jared Casper wrote: On Mon, Feb 22, 2010 at 3:42 PM, Peter Clifton pc...@cam.ac.uk wrote: I'm tempted to pay someone a bounty to kill those with fire ;) (or certainly fix the message window's focus-stealing, attention grabbing - behaviour. The same is true of the netlist window when you press F on a net.) Patch attached. Here's the commit message (comments welcome): Committed (removing a few minor trailing white-space issues). Thank you for the patch! We'll see how everyone (using git HEAD) finds the new behaviours, and see if we need to adjust it at all. I can't help but feel that some log messages are important enough to bother the user about - and others are not.. we'll have to see what people actually using it think, I'm not doing any PCB design work at the moment myself. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Schematic import (was why separate xgsch2pcb?)
On Sun, 2010-02-21 at 11:26 +, Peter Clifton wrote: Looks like a mistake.. PCB has defgnetlist hard-coded rather than gnetlist. Try with this environment variable set as a work-around for now: PCB_GNETLIST=gnetlist This is no longer necessary.. I fixed the hard-coded default to be gnetlist rather than defgnetlist. Peter C. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: analog/code co-simulation and schematics and netlists for silicon
Peter Clifton wrote: On Wed, 2010-02-24 at 09:46 +1100, Geoff Swan wrote: I have daydreamed about the possibility of linking gEDA with qucs and simavr/gdb for example. My phone conversation today with Mr Wender of Triad was about verilog-ams and the possibilities it offers mostly. One way to get a model of a microprocessor running with gnucap doing analog and gates might be to use CMOS logic gate primitives that compute quickly and the usual models for analog elements and just let it all run on a server farm for a few hours. I'm not sure of the speed gnucap will simulate flip flops and nand gates at when you put enough together to make a working micro -- that's a lot of gates to sim. I'll try to spend some more time on testing the gnetlist verilog-ams back end with gnucap further, but first comes business survival. It could be months. Triad doesn't have a dedicate CAD guy to work on this kind of integration. Their sister company Viasic, (Bill Cox and gnetman), does. They're going to keep in touch about gnetlist/gnucap integration -- no promises. One thing to think about is what the NRE charges for a small chip containing a 8051 micro and custom analog peripherals would be with an open tool chain for simulation. As things are today Triad charges $200K NRE for a chip done by their staff using Cadence licenses. A DIY chip designed with gschem and verilog-ams and simulated with gnucap would have NRE charges of only $30K per chip. If a group of designs made with open tools was ready at the same time they could syndicate a wafer run and get the NRE charges down to $5K per batch per customer, (the shared slice of the cost of a single metal mask). al davis wrote: The gnetlist backend only supports a small subset of what could be done. . . We really need a more general translator, that isn't based on the gschem format or any other tool specific format. I have a start, but need help. . . What is lacking is a fully working model compiler. There is work in progress with Icarus to make this happen. The main missing piece now is a back-end for Icarus that matches the gnucap interface. Al, are you saying that Icarus verilog would run along side of gnucap once that interface is ready? Will Steve's model compiler aim at doing user definable verilog-ams models? Would you still use gschem/gnetlist to schematically connect verilog modules? That depends on having a good translator first, right? Could you just use a top level schematic as a guide for connecting code modules to simulate with no netlist generated from gschem? John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: how to push/commit a new vbpp to geda?
[snip] So let me ask again, how do I upload it here: http://svn.seul.org/viewcvs/viewvc.cgi/eda/vbpp/?root=SEUL You really to get permission from the author of the vbpp to get write access to his repository. I did see some of the e-mails that you sent, but until you get a response, there is very little I am going to do or even willing to do with regard to repository write access. If you cannot get explicit permission (as Jimen might have disappear from the net) then you have two choice (IMHO): 1) Rename, fork, host, and maintain the vbpp derived project going forward. You will need follow the license which is described in the COPYING file. For vbpp this seems to be some sort of GPL derived like/hacked up thing (VPP GENERAL PUBLIC LICENSE). 2) Fork, host, and maintain the vbpp project going forward (still following the appropriate license). Do this (with no project rename) at your own peril though, even though you made an honest effort to contact the author. You never know what will happen if the original author(s) comes along (suddenly wakes up from a coma etc...) and isn't happy that you hijacked his project. Good luck, Ales ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: analog/code co-simulation and schematics and netlists for silicon
On Tuesday 23 February 2010, John Griessen wrote: Al, are you saying that Icarus verilog would run along side of gnucap once that interface is ready? Icarus has two key parts .. A compiler, and a virtual machine. In its normal use, the compiler generates code for the virtual machine, then you run the virtual machine on that code. The icarus compiler has a provision for alternate target back ends. There are several available. -- fpga, pal, vvp, . The plan is to make a new target back end that will generate a gnucap model plugin. For gnucap, the Icarus virtual machine will not be used. In gnucap (development version, not 0.35) .. device models are not built-in, but can be loaded and unloaded at run time. This makes it possible to have a lot more models without the bloat of all of the models you are not using. (I'm not talking about the spice .model statement here .. This is the real code that implements the model.) These model plugins are standard shared-object files native to whatever system you are running on. As it stands now, some are hand coded in C++, some use the old gnucap-modelgen, and some are spice models. Gnucap can use unmodified Spice C model code as plugins, with a simple interface wrapper. The work in progress is along two lines .. One is an Icarus backend to generate a plugin. The other is to use another model compiler ADMS to generate gnucap code. You can use ADMS now to generate NGspice code, which gnucap can use as a plugin, but this is not as efficient as it should be, because of the ancient Spice interface overhead and mapping overhead. As another approach, it is possible to run the Icarus virtual machine along side of gnucap, but efficiency is not good, and you need to hack some code. It has been done. Would you still use gschem/gnetlist to schematically connect verilog modules? That depends on having a good translator first, right? Anything that generates a netlist. Gnucap uses language plugins to read whatever input format. Maybe someone could make a language plugin to read and write the gschem format directly. Once this is done, it will also give us a stand-alone translator, both ways, between any of the supported formats. Could you just use a top level schematic as a guide for connecting code modules to simulate with no netlist generated from gschem? Sure, but do you want to? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: how to push/commit a new vbpp to geda?
[snip] You really to get permission from the author of the vbpp to ^ \- need get write access to his repository. I did see some of the e-mails that [snip] ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Toporouter update?
On 02/23/2010 06:46 PM, Anthony Blake wrote: Ok, then. Can you compile a list of tasks that need to be accomplished before the topo router is ready for general use? The smaler the individual tasks, the more likely they can be tackled by low time hackers like me... For sure. It would require some careful consideration though.. I'll get back to you within a week. Keep me in the loop, too. -Ethan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: any last minute advice prior to sending out for PCB fab
After a very long time, I am just about ready to send out 3 different boards for fab. I would appreciate any advice to improve my chances of success. So far here's what has been done: 1. Run DRC on all PCBs with no issues.. 2. Checked schematics. 3. Checked schematic matches layout. 4. In process of checking all the components, especially the transistor pinouts (all SOT23 devices) 5. Checked the board dimensions. These boards plug into one another, so have to be sure they match up. It looks good physically and the pin numbers look correct from board-to-board. 6. Checked the soldermask. I found a bunch with very minimal dam spacing so fixed them. 7. fixed cosmetic trace runs that looked ugly. 8. double checked for unused traces left behind from component moves. The cash layout for PCB fab is going to be large enough that I am nervous about not getting it right. Still, I have a CPU card and SMPS to do which can wait a bit while this gets put together. what else? Any suggestions? thanks gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
Print out your surface copper layers and put the parts on the printout to make sure they match. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
DJ Delorie wrote: Print out your surface copper layers and put the parts on the printout to make sure they match. that's a really good idea, thanks! It'll delay things some, but yeah, sounds like the conservative way to go. I'll have to order up a bunch of parts to make it happen but that's ok. Printing out 1:1 should be close enough on a laser printer, I think. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
Check the gerbers and drill files using gerbv. I use a script that zips and renames all the files for the fab house. I take the zip file that is created, unzip it and check those files with gerbv. For a system of boards that plug into each I might panelize them so that they all align. You would quickly see misalignment. You would also save some money on the fabrication. (* jcl *) On Tue, Feb 23, 2010 at 10:01 PM, gene glick [1]carzr...@optonline.net wrote: After a very long time, I am just about ready to send out 3 different boards for fab. I would appreciate any advice to improve my chances of success. So far here's what has been done: 1. Run DRC on all PCBs with no issues.. 2. Checked schematics. 3. Checked schematic matches layout. 4. In process of checking all the components, especially the transistor pinouts (all SOT23 devices) 5. Checked the board dimensions. These boards plug into one another, so have to be sure they match up. It looks good physically and the pin numbers look correct from board-to-board. 6. Checked the soldermask. I found a bunch with very minimal dam spacing so fixed them. 7. fixed cosmetic trace runs that looked ugly. 8. double checked for unused traces left behind from component moves. The cash layout for PCB fab is going to be large enough that I am nervous about not getting it right. Still, I have a CPU card and SMPS to do which can wait a bit while this gets put together. what else? Any suggestions? thanks gene ___ geda-user mailing list [2]geda-u...@moria.seul.org [3]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user -- You can't create open hardware with closed EDA tools. twitter: [4]http://twitter.com/jluciani blog:[5]http://www.luciani.org References 1. mailto:carzr...@optonline.net 2. mailto:geda-user@moria.seul.org 3. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 4. http://twitter.com/jluciani 5. http://www.luciani.org/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
John Luciani wrote: Check the gerbers and drill files using gerbv. I use a script that zips and renames all the files for the fab house. I take the zip file that is created, unzip it and check those files with gerbv. For a system of boards that plug into each I might panelize them so that they all align. You would quickly see misalignment. You would also save some money on the fabrication. (* jcl *) I completely forgot to mention that I generated the Ben-mode prints to check it all out - that is really helpful. And yes, like you, run a script to generate and rename the gerber files. Gerbv is a great tool, I like it a bunch. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
On Tue, Feb 23, 2010 at 8:01 PM, gene glick carzr...@optonline.net wrote: After a very long time, I am just about ready to send out 3 different boards for fab. I would appreciate any advice to improve my chances of success. So far here's what has been done: 1. Run DRC on all PCBs with no issues.. 2. Checked schematics. 3. Checked schematic matches layout. 4. In process of checking all the components, especially the transistor pinouts (all SOT23 devices) 5. Checked the board dimensions. These boards plug into one another, so have to be sure they match up. It looks good physically and the pin numbers look correct from board-to-board. 6. Checked the soldermask. I found a bunch with very minimal dam spacing so fixed them. 7. fixed cosmetic trace runs that looked ugly. 8. double checked for unused traces left behind from component moves. Make a rendering with --photo-mode and check that it looks like what you are expecting. Errors become more obvious to my eyes with a realistic-looking rendering than the false color of gerbv or pcb. If the design isn't secret, post the rendering online (eg., imgur.com) and we'll all take a look. You can use Advanced Circuit's freedfm.com and see what it says. Regards, Mark markra...@gmail -- Mark Rages, Engineer Midwest Telecine LLC markra...@midwesttelecine.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: desktop-i18n in gEDA
[cc'ing geda-user since it looks like my subscription is all sorted out]
On Feb 19, 2010, at 9:54 AM, Peter TB Brett wrote:
Charles Lepple wrote:
Peter,
sorry to email you directly, but I am having some issues
subscribing to geda-user. (I'll email Ales later today.)
I am trying to package up geda-gaf 1.6.1 for Fink, and it is
trying to install some files outside the build root.
The whole log is here:
http://www.ghz.cc/charles/tmp/fink-build-log-geda-2010-02-17.txt.gz
The lines I am concerned with are here:
make prefix=../../.desktop-i18n install cp ./
LINGUAS ../../.desktop-i18n/geda-gschem.LINGUAS|| rm stamp-i18n
/sw/bin/gmkdir -p /sw/src/fink.build/root-geda-
gaf-1.6.1-0../../.desktop-i18n/share
/sw/bin/gmkdir: cannot create directory `/sw/src/fink.build/root-
geda-gaf-1.6.1-0..': Permission denied
make[4]: *** [install-data-yes] Error 1
Can you please help me understand what the desktop-i18n code is
trying to do here?
desktop-i18n needs to use gettext to translate the gEDA .desktop and
mimeinfo files. Unfortunately, gettext only works if it's pointed at
a a validly-structured locale directory containing compiled
translation databases. In order to provide this, desktop-i18n adds
rules to the po directory makefiles to 'install' the translation
databases into ${builddir}/.desktop-i18n. It appears that setting
DESTDIR is somehow interfering with this.
Though they use a very similar package build methodology, the Fedora
and Debian packagers don't seem to have experienced this issue; I'd
expect to have have heard from them by now! Perhaps there's
something they're doing differently?
I think the Fedora build is silently accepting the other directory
under BUILDROOT:
Making install in po
make[3]: Entering directory `/builddir/build/BUILD/geda-gaf-1.6.0/
libgeda/po'
/usr/bin/make prefix=../../.desktop-i18n install cp ./
LINGUAS ../../.desktop-i18n/libgeda38.LINGUAS || rm stamp-i18n
make[4]: Entering directory `/builddir/build/BUILD/geda-gaf-1.6.0/
libgeda/po'
/bin/mkdir -p /builddir/build/BUILDROOT/geda-gaf-1.6.0-3.fc13.i386/usr/
share
installing nl.gmo as /builddir/build/BUILDROOT/geda-
gaf-1.6.0-3.fc13.i386../../.desktop-i18n/share/locale/nl/LC_MESSAGES/
libgeda38.mo
...
That was from the build log here:
http://kojipkgs.fedoraproject.org/packages/geda-gaf/1.6.0/3.fc13/data/logs/i686/build.log
Apparently that web site requires the exact package name, so here's a
direct link to the geda-gaf status page: http://koji.fedoraproject.org/koji/packageinfo?packageID=9271
The Debian logs that I checked did not seem to show that level of
detail.
[ One possibility to investigate is that of running 'make all'
without DESTDIR and then 'make install' with DESTDIR. ]
The Fink build process is currently running make all without DESTDIR.
I could add a slash to the path being passed into DESTDIR, but that
wouldn't work either (the build process can't write to /sw/src, just
its allocated (/sw/src/fink.build/root-name_of_package-ver-rev).
--
Charles Lepple
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Re: gEDA-user: any last minute advice prior to sending out for PCB fab
On Tue, 23 Feb 2010 22:18:02 -0500 gene glick carzr...@optonline.net wrote: DJ Delorie wrote: Print out your surface copper layers and put the parts on the printout to make sure they match. that's a really good idea, thanks! It'll delay things some, but yeah, sounds like the conservative way to go. I'll have to order up a bunch of parts to make it happen but that's ok. Printing out 1:1 should be close enough on a laser printer, I think. Watch out, I stumbled on that one not too long ago. My particular laser printer (an ooddd Konica KL-3015) needs a ratio of 1:1.07, otherwise everything comes out too small. I assume this is from the paper shrinking ever so slightly as goes through the fusor rollers. Otherwise, it's an excellent idea. -- There are some things in life worth obsessing over. Most things aren't, and when you learn that, life improves. http://starbase.globalpc.net/~ezekowitz Vanessa Ezekowitz vanessaezekow...@gmail.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Message and Library windows
On Tue, Feb 23, 2010 at 3:53 PM, Peter Clifton pc...@cam.ac.uk wrote: I can't help but feel that some log messages are important enough to bother the user about - and others are not.. we'll have to see what people actually using it think, I'm not doing any PCB design work at the moment myself. Maybe add a Warn function along side Message (or something along those lines), and add a flag to HID.log that says whether or not to bring the log window to the foreground? Or go all out and add an enum for severity. It'd be easy to add the plumbing, the hard part would be to go through and decide what Message()s should be Warn()s, etc. I'm sure different severities could be displayed differently in the log quite easily as well... The functionality I saw someplace (was it in your repo?) to attach/embed the log window to the main window will help out with this problem as well I think. Jared ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem text line spacing in postscript
This one adds a 12% leading to the text spacing for print, causing it to pretty well match my on-screen leading. YMMV depending on what fonts your system chooses. Thanks Peter, I'll try it out and give you some feedback. Regards, Duncan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
