[gem5-dev] Cron /z/m5/regression/do-regression quick
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: FAILED! * build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: FAILED! * build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: FAILED! * build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory: FAILED! * build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: FAILED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple: CHANGED! * build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing: CHANGED! *
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: Create system file for RISCV FS
Hello Alec Roelke, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19828 to look at the new patch set (#2). Change subject: arch-riscv: Create system file for RISCV FS .. arch-riscv: Create system file for RISCV FS This patch is part of the implementation of the RISC-V Full system mode. The function of this patch is initialize the full system: device tree blob, bootloader, kernel, uart, etc. For reference, the full implemation can be found at: https://github.com/john-liu2039/Gem5-RISCV-FullSystem Change-Id: Iad2934016807408c25577ae45b2a7920a9e47004 --- M src/arch/riscv/RiscvSystem.py M src/arch/riscv/SConscript A src/arch/riscv/linux/system.cc A src/arch/riscv/linux/system.hh 4 files changed, 247 insertions(+), 4 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19828 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Iad2934016807408c25577ae45b2a7920a9e47004 Gerrit-Change-Number: 19828 Gerrit-PatchSet: 2 Gerrit-Owner: LIU YIFEI Gerrit-Reviewer: Alec Roelke Gerrit-CC: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] gently generalizing derived clock domains
Although something here still needs to be virtual... Gabe On Wed, Aug 7, 2019 at 6:49 PM Gabe Black wrote: > Oh, never mind! I'd misunderstood the difference between members and > children in the clock code. I think things are fine as is! I guess I'm > still not all the way back from my trip :-). > > Gabe > > On Wed, Aug 7, 2019 at 6:33 PM Gabe Black wrote: > >> You know, after writing that all out, I think maybe it would be better to >> have a generic ClockWatcher interface where something (anything) could >> watch a clock source and be notified of period updates. The >> DerivedClockDomain would implement that interface, but then so could my >> CPU. That would avoid having an awkward sort ClockDomain but not really >> class which would be just to hijack the clock watching ability of the >> DerivedClockDomain. >> >> I think that would also avoid having to rename anything, since even >> though the DerivedClockDomain makes some overly simplifying assumptions >> (clocks only go slower and in integer ratios), it wouldn't make any less >> sense if the update mechanism was changed. I'll go ahead and do things that >> way. >> >> Gabe >> >> On Wed, Aug 7, 2019 at 6:26 PM Gabe Black wrote: >> >>> Hi folks. I'm working on making a CPU model out of a black box CPU >>> implementation which doesn't explicitly schedule each of its clock ticks (I >>> assume it does that internally), but does respect a clock which I can >>> adjust. >>> >>> The existing clock domain mechanism lets a client call into it to see >>> when the next clock edge is, for instance, but doesn't actively tell other >>> entities when its clock rate has changed. In situations where the clock >>> rate isn't polled (ie the one I'm working on), the clock rate could change >>> without the CPU noticing. >>> >>> I see a mechanism in the clock domain classes which sort of already does >>> this, where there can be a source clock and then derived clocks which are >>> notified of input clock changes and can regenerate their output clock rate. >>> Unfortunately, the DerivedClockDomain class assumes that all derived clocks >>> are based on scaling with a simple divider/multiplier (probably mostly >>> true), and doesn't give any way to hook into the clock update >>> propagation mechanism otherwise. >>> >>> What I would like to do is to make the updateClockPeriod function in >>> DerivedClockDomain virtual, and then move the dividing logic into a new, >>> derived (in the C++ sense) class called, perhaps, ScaledClockDomain. Then I >>> could create my own clock domain class who's only purpose would be to let >>> my opaque CPU model know when the clock changes. >>> >>> Since this would change the names of the type of objects in configs, I >>> figured I'd throw out an email letting people know before attempting this >>> change. This would also make a normal method virtual which would add a >>> slight performance penalty when calling it, but since updating >>> frequency/clocking domains probably doesn't happen that often relatively >>> speaking and the overhead would be very small, that seems like a reasonable >>> trade off. >>> >>> Gabe >>> >> ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] gently generalizing derived clock domains
Oh, never mind! I'd misunderstood the difference between members and children in the clock code. I think things are fine as is! I guess I'm still not all the way back from my trip :-). Gabe On Wed, Aug 7, 2019 at 6:33 PM Gabe Black wrote: > You know, after writing that all out, I think maybe it would be better to > have a generic ClockWatcher interface where something (anything) could > watch a clock source and be notified of period updates. The > DerivedClockDomain would implement that interface, but then so could my > CPU. That would avoid having an awkward sort ClockDomain but not really > class which would be just to hijack the clock watching ability of the > DerivedClockDomain. > > I think that would also avoid having to rename anything, since even though > the DerivedClockDomain makes some overly simplifying assumptions (clocks > only go slower and in integer ratios), it wouldn't make any less sense if > the update mechanism was changed. I'll go ahead and do things that way. > > Gabe > > On Wed, Aug 7, 2019 at 6:26 PM Gabe Black wrote: > >> Hi folks. I'm working on making a CPU model out of a black box CPU >> implementation which doesn't explicitly schedule each of its clock ticks (I >> assume it does that internally), but does respect a clock which I can >> adjust. >> >> The existing clock domain mechanism lets a client call into it to see >> when the next clock edge is, for instance, but doesn't actively tell other >> entities when its clock rate has changed. In situations where the clock >> rate isn't polled (ie the one I'm working on), the clock rate could change >> without the CPU noticing. >> >> I see a mechanism in the clock domain classes which sort of already does >> this, where there can be a source clock and then derived clocks which are >> notified of input clock changes and can regenerate their output clock rate. >> Unfortunately, the DerivedClockDomain class assumes that all derived clocks >> are based on scaling with a simple divider/multiplier (probably mostly >> true), and doesn't give any way to hook into the clock update >> propagation mechanism otherwise. >> >> What I would like to do is to make the updateClockPeriod function in >> DerivedClockDomain virtual, and then move the dividing logic into a new, >> derived (in the C++ sense) class called, perhaps, ScaledClockDomain. Then I >> could create my own clock domain class who's only purpose would be to let >> my opaque CPU model know when the clock changes. >> >> Since this would change the names of the type of objects in configs, I >> figured I'd throw out an email letting people know before attempting this >> change. This would also make a normal method virtual which would add a >> slight performance penalty when calling it, but since updating >> frequency/clocking domains probably doesn't happen that often relatively >> speaking and the overhead would be very small, that seems like a reasonable >> trade off. >> >> Gabe >> > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] gently generalizing derived clock domains
You know, after writing that all out, I think maybe it would be better to have a generic ClockWatcher interface where something (anything) could watch a clock source and be notified of period updates. The DerivedClockDomain would implement that interface, but then so could my CPU. That would avoid having an awkward sort ClockDomain but not really class which would be just to hijack the clock watching ability of the DerivedClockDomain. I think that would also avoid having to rename anything, since even though the DerivedClockDomain makes some overly simplifying assumptions (clocks only go slower and in integer ratios), it wouldn't make any less sense if the update mechanism was changed. I'll go ahead and do things that way. Gabe On Wed, Aug 7, 2019 at 6:26 PM Gabe Black wrote: > Hi folks. I'm working on making a CPU model out of a black box CPU > implementation which doesn't explicitly schedule each of its clock ticks (I > assume it does that internally), but does respect a clock which I can > adjust. > > The existing clock domain mechanism lets a client call into it to see when > the next clock edge is, for instance, but doesn't actively tell other > entities when its clock rate has changed. In situations where the clock > rate isn't polled (ie the one I'm working on), the clock rate could change > without the CPU noticing. > > I see a mechanism in the clock domain classes which sort of already does > this, where there can be a source clock and then derived clocks which are > notified of input clock changes and can regenerate their output clock rate. > Unfortunately, the DerivedClockDomain class assumes that all derived clocks > are based on scaling with a simple divider/multiplier (probably mostly > true), and doesn't give any way to hook into the clock update > propagation mechanism otherwise. > > What I would like to do is to make the updateClockPeriod function in > DerivedClockDomain virtual, and then move the dividing logic into a new, > derived (in the C++ sense) class called, perhaps, ScaledClockDomain. Then I > could create my own clock domain class who's only purpose would be to let > my opaque CPU model know when the clock changes. > > Since this would change the names of the type of objects in configs, I > figured I'd throw out an email letting people know before attempting this > change. This would also make a normal method virtual which would add a > slight performance penalty when calling it, but since updating > frequency/clocking domains probably doesn't happen that often relatively > speaking and the overhead would be very small, that seems like a reasonable > trade off. > > Gabe > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-x86: Updating fault condition for write to cr4
Pouya Fotouhi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19892 )
Change subject: arch-x86: Updating fault condition for write to cr4
..
arch-x86: Updating fault condition for write to cr4
A fault is generated if there is a bit set that's above bit 11.
However, there are lots of bits above 11 now.
In particular, our implementation of CPUID returns 0x04000209 for
RCX (family 0: Standard Functions, function 1: FamilyModelStepping)
which sets bit 26 (XSAVE) on RCX - which is bit 18 on cr4.
Change-Id: I17c1c341d85e51d532a0ddbd622b9139025a5276
---
M src/arch/x86/isa/microops/regop.isa
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/arch/x86/isa/microops/regop.isa
b/src/arch/x86/isa/microops/regop.isa
index 6f2901b..9dd9375 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -1414,7 +1414,7 @@
{
CR4 cr4 = newVal;
// PAE can't be disabled in long mode.
-if (bits(newVal, 63, 11) ||
+if (bits(newVal, 63, 22) ||
(machInst.mode.mode == LongMode
&& !cr4.pae))
fault = std::make_shared(0);
}
--
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[gem5-dev] gently generalizing derived clock domains
Hi folks. I'm working on making a CPU model out of a black box CPU implementation which doesn't explicitly schedule each of its clock ticks (I assume it does that internally), but does respect a clock which I can adjust. The existing clock domain mechanism lets a client call into it to see when the next clock edge is, for instance, but doesn't actively tell other entities when its clock rate has changed. In situations where the clock rate isn't polled (ie the one I'm working on), the clock rate could change without the CPU noticing. I see a mechanism in the clock domain classes which sort of already does this, where there can be a source clock and then derived clocks which are notified of input clock changes and can regenerate their output clock rate. Unfortunately, the DerivedClockDomain class assumes that all derived clocks are based on scaling with a simple divider/multiplier (probably mostly true), and doesn't give any way to hook into the clock update propagation mechanism otherwise. What I would like to do is to make the updateClockPeriod function in DerivedClockDomain virtual, and then move the dividing logic into a new, derived (in the C++ sense) class called, perhaps, ScaledClockDomain. Then I could create my own clock domain class who's only purpose would be to let my opaque CPU model know when the clock changes. Since this would change the names of the type of objects in configs, I figured I'd throw out an email letting people know before attempting this change. This would also make a normal method virtual which would add a slight performance penalty when calling it, but since updating frequency/clocking domains probably doesn't happen that often relatively speaking and the overhead would be very small, that seems like a reasonable trade off. Gabe ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Use check_on_cache_probe on MOESI hammer
Pouya Fotouhi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19891 )
Change subject: mem-ruby: Use check_on_cache_probe on MOESI hammer
..
mem-ruby: Use check_on_cache_probe on MOESI hammer
This change uses check_on_cache_probe statement to check if the cacheline
subject to eviction is locked in MOESI hammer.
Change-Id: I2c43f22aba5af3a57e54b1c435e5d3fbba86d1d5
---
M src/mem/protocol/MOESI_hammer-cache.sm
1 file changed, 4 insertions(+), 0 deletions(-)
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm
b/src/mem/protocol/MOESI_hammer-cache.sm
index 9cbd277..4086f42 100644
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -468,7 +468,9 @@
}
} else {
// No room in the L1, so we need to make room
+ // Check if the line we want to evict is not locked
Addr l1i_victim_addr :=
L1Icache.cacheProbe(in_msg.LineAddress);
+ check_on_cache_probe(mandatoryQueue_in, l1i_victim_addr);
if (L2cache.cacheAvail(l1i_victim_addr)) {
// The L2 has room, so we move the line from the L1 to the
L2
trigger(Event:L1_to_L2,
@@ -525,7 +527,9 @@
}
} else {
// No room in the L1, so we need to make room
+ // Check if the line we want to evict is not locked
Addr l1d_victim_addr :=
L1Dcache.cacheProbe(in_msg.LineAddress);
+ check_on_cache_probe(mandatoryQueue_in, l1i_victim_addr);
if (L2cache.cacheAvail(l1d_victim_addr)) {
// The L2 has room, so we move the line from the L1 to the
L2
trigger(Event:L1_to_L2,
--
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Gerrit-Change-Id: I2c43f22aba5af3a57e54b1c435e5d3fbba86d1d5
Gerrit-Change-Number: 19891
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Gerrit-Owner: Pouya Fotouhi
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Use check_on_cache_probe on MOESI CMP
Pouya Fotouhi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19908 )
Change subject: mem-ruby: Use check_on_cache_probe on MOESI CMP
..
mem-ruby: Use check_on_cache_probe on MOESI CMP
This change uses check_on_cache_probe statement to check if the cacheline
subject to eviction is locked in MOESI CMP.
Change-Id: I3a8879e10ebd94ef68194836475e656761fed62c
---
M src/mem/protocol/MOESI_CMP_directory-L1cache.sm
1 file changed, 6 insertions(+), 0 deletions(-)
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
index 1f57316..3c49023 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -412,6 +412,9 @@
TBEs[in_msg.LineAddress]);
} else {
// No room in the L1, so we need to make room in the L1
+ // Check if the line we want to evict is not locked
+ Addr addr := L1Icache.cacheProbe(in_msg.LineAddress);
+ check_on_cache_probe(mandatoryQueue_in, addr);
trigger(Event:L1_Replacement,
L1Icache.cacheProbe(in_msg.LineAddress),
getL1ICacheEntry(L1Icache.cacheProbe(in_msg.LineAddress)),
@@ -443,6 +446,9 @@
TBEs[in_msg.LineAddress]);
} else {
// No room in the L1, so we need to make room in the L1
+ // Check if the line we want to evict is not locked
+ Addr addr := L1Dcache.cacheProbe(in_msg.LineAddress);
+ check_on_cache_probe(mandatoryQueue_in, addr);
trigger(Event:L1_Replacement,
L1Dcache.cacheProbe(in_msg.LineAddress),
getL1DCacheEntry(L1Dcache.cacheProbe(in_msg.LineAddress)),
--
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Gerrit-Change-Id: I3a8879e10ebd94ef68194836475e656761fed62c
Gerrit-Change-Number: 19908
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Use check_on_cache_probe on MOESI
Pouya Fotouhi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19890 )
Change subject: mem-ruby: Use check_on_cache_probe on MOESI
..
mem-ruby: Use check_on_cache_probe on MOESI
This change uses check_on_cache_probe statement to check if the cacheline
subject to eviction is locked in MOESI.
Change-Id: Ie650ccdc15bb41b4088e534975b662408aaccf24
---
M src/mem/protocol/MOESI_AMD_Base-CorePair.sm
1 file changed, 6 insertions(+), 0 deletions(-)
diff --git a/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
b/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
index e1504de..140bbc4 100644
--- a/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
@@ -543,7 +543,9 @@
tbe);
}
} else {
+// Check if the line we want to evict is not locked
Addr victim := L1Icache.cacheProbe(in_msg.LineAddress);
+check_on_cache_probe(mandatoryQueue_in, victim);
trigger(Event:L1I_Repl, victim,
getCacheEntry(victim), TBEs.lookup(victim));
}
@@ -582,7 +584,9 @@
cache_entry, tbe);
}
} else {
+ // Check if the line we want to evict is not locked
Addr victim := L1D1cache.cacheProbe(in_msg.LineAddress);
+ check_on_cache_probe(mandatoryQueue_in, victim);
trigger(Event:L1D1_Repl, victim,
getCacheEntry(victim), TBEs.lookup(victim));
}
@@ -618,7 +622,9 @@
cache_entry, tbe);
}
} else {
+ // Check if the line we want to evict is not locked
Addr victim := L1D0cache.cacheProbe(in_msg.LineAddress);
+ check_on_cache_probe(mandatoryQueue_in, victim);
trigger(Event:L1D0_Repl, victim, getCacheEntry(victim),
TBEs.lookup(victim));
}
--
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Gerrit-Change-Number: 19890
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Gerrit-Owner: Pouya Fotouhi
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: cpu: Pull more arch specialization to the top of BaseCPU.py.
Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/19889 ) Change subject: cpu: Pull more arch specialization to the top of BaseCPU.py. .. cpu: Pull more arch specialization to the top of BaseCPU.py. This simplifies the logic of the CPU python class, and brings us ever so slightly closer to factoring hardcoded ISA behavior out of non-ISA specific components. Change-Id: I7e4511dd4e6076f5c214be5af2a0e33af0142563 --- M src/cpu/BaseCPU.py 1 file changed, 38 insertions(+), 77 deletions(-) diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 6dd460c..a63f650 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -64,40 +64,47 @@ if buildEnv['TARGET_ISA'] == 'alpha': from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB -from m5.objects.AlphaInterrupts import AlphaInterrupts -from m5.objects.AlphaISA import AlphaISA -default_isa_class = AlphaISA +from m5.objects.AlphaInterrupts import AlphaInterrupts as ArchInterrupts +from m5.objects.AlphaISA import AlphaISA as ArchISA +ArchInterruptsParam = VectorParam.AlphaInterrupts +ArchISAsParam = VectorParam.AlphaISA elif buildEnv['TARGET_ISA'] == 'sparc': from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB -from m5.objects.SparcInterrupts import SparcInterrupts -from m5.objects.SparcISA import SparcISA -default_isa_class = SparcISA +from m5.objects.SparcInterrupts import SparcInterrupts as ArchInterrupts +from m5.objects.SparcISA import SparcISA as ArchISA +ArchInterruptsParam = VectorParam.SparcInterrupts +ArchISAsParam = VectorParam.SparcISA elif buildEnv['TARGET_ISA'] == 'x86': from m5.objects.X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB -from m5.objects.X86LocalApic import X86LocalApic -from m5.objects.X86ISA import X86ISA -default_isa_class = X86ISA +from m5.objects.X86LocalApic import X86LocalApic as ArchInterrupts +from m5.objects.X86ISA import X86ISA as ArchISA +ArchInterruptsParam = VectorParam.X86LocalApic +ArchISAsParam = VectorParam.X86ISA elif buildEnv['TARGET_ISA'] == 'mips': from m5.objects.MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB -from m5.objects.MipsInterrupts import MipsInterrupts -from m5.objects.MipsISA import MipsISA -default_isa_class = MipsISA +from m5.objects.MipsInterrupts import MipsInterrupts as ArchInterrupts +from m5.objects.MipsISA import MipsISA as ArchISA +ArchInterruptsParam = VectorParam.MipsInterrupts +ArchISAsParam = VectorParam.MipsISA elif buildEnv['TARGET_ISA'] == 'arm': from m5.objects.ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB from m5.objects.ArmTLB import ArmStage2IMMU, ArmStage2DMMU -from m5.objects.ArmInterrupts import ArmInterrupts -from m5.objects.ArmISA import ArmISA -default_isa_class = ArmISA +from m5.objects.ArmInterrupts import ArmInterrupts as ArchInterrupts +from m5.objects.ArmISA import ArmISA as ArchISA +ArchInterruptsParam = VectorParam.ArmInterrupts +ArchISAsParam = VectorParam.ArmISA elif buildEnv['TARGET_ISA'] == 'power': from m5.objects.PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB -from m5.objects.PowerInterrupts import PowerInterrupts -from m5.objects.PowerISA import PowerISA -default_isa_class = PowerISA +from m5.objects.PowerInterrupts import PowerInterrupts as ArchInterrupts +from m5.objects.PowerISA import PowerISA as ArchISA +ArchInterruptsParam = VectorParam.PowerInterrupts +ArchISAsParam = VectorParam.PowerISA elif buildEnv['TARGET_ISA'] == 'riscv': from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB -from m5.objects.RiscvInterrupts import RiscvInterrupts -from m5.objects.RiscvISA import RiscvISA -default_isa_class = RiscvISA +from m5.objects.RiscvInterrupts import RiscvInterrupts as ArchInterrupts +from m5.objects.RiscvISA import RiscvISA as ArchISA +ArchInterruptsParam = VectorParam.RiscvInterrupts +ArchISAsParam = VectorParam.RiscvISA class BaseCPU(ClockedObject): type = 'BaseCPU' @@ -171,40 +178,13 @@ dtb = Param.BaseTLB(ArchDTB(), "Data TLB") itb = Param.BaseTLB(ArchITB(), "Instruction TLB") -if buildEnv['TARGET_ISA'] == 'sparc': -interrupts = VectorParam.SparcInterrupts( -[], "Interrupt Controller") -isa = VectorParam.SparcISA([], "ISA instance") -elif buildEnv['TARGET_ISA'] == 'alpha': -interrupts = VectorParam.AlphaInterrupts( -[], "Interrupt Controller") -isa = VectorParam.AlphaISA([], "ISA instance") -elif buildEnv['TARGET_ISA'] == 'x86': -interrupts = VectorParam.X86LocalApic([], "Interrupt Controller") -isa = VectorParam.X86ISA([], "ISA instance") -elif buildEnv['TARGET_ISA'] ==
[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Use check_on_cache_probe on MI
Pouya Fotouhi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19888 )
Change subject: mem-ruby: Use check_on_cache_probe on MI
..
mem-ruby: Use check_on_cache_probe on MI
This change uses check_on_cache_probe statement to check if the cacheline
subject to eviction is locked in MI.
Change-Id: I276822e987e52f7682ff30f55880f295b6af023d
---
M src/mem/protocol/MI_example-cache.sm
1 file changed, 3 insertions(+), 0 deletions(-)
diff --git a/src/mem/protocol/MI_example-cache.sm
b/src/mem/protocol/MI_example-cache.sm
index b8036c1..dcfa148 100644
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -254,6 +254,9 @@
if (is_invalid(cache_entry) &&
cacheMemory.cacheAvail(in_msg.LineAddress) == false ) {
// make room for the block
+ // Check if the line we want to evict is not locked
+ Addr addr := cacheMemory.cacheProbe(in_msg.LineAddress);
+ check_on_cache_probe(mandatoryQueue_in, addr);
trigger(Event:Replacement,
cacheMemory.cacheProbe(in_msg.LineAddress),
getCacheEntry(cacheMemory.cacheProbe(in_msg.LineAddress)),
TBEs[cacheMemory.cacheProbe(in_msg.LineAddress)]);
--
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Gerrit-Change-Id: I276822e987e52f7682ff30f55880f295b6af023d
Gerrit-Change-Number: 19888
Gerrit-PatchSet: 1
Gerrit-Owner: Pouya Fotouhi
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Use check_on_cache_probe to protect locked lines from eviction
Pouya Fotouhi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19868 )
Change subject: mem-ruby: Use check_on_cache_probe to protect locked lines
from eviction
..
mem-ruby: Use check_on_cache_probe to protect locked lines from eviction
This change uses check_on_cache_probe statement to check if the cacheline
subject to eviction is locked in MESI Three Level.
Change-Id: Ib0de54aa067c7603db1f7321cc4825b123b641ac
---
M src/mem/protocol/MESI_Three_Level-L0cache.sm
1 file changed, 6 insertions(+), 0 deletions(-)
diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm
b/src/mem/protocol/MESI_Three_Level-L0cache.sm
index a87a3d9..399ca34 100644
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm
@@ -324,6 +324,9 @@
Icache_entry, TBEs[in_msg.LineAddress]);
} else {
// No room in the L0, so we need to make room in the L0
+ // Check if the line we want to evict is not locked
+ Addr addr := Icache.cacheProbe(in_msg.LineAddress);
+ check_on_cache_probe(mandatoryQueue_in, addr);
trigger(Event:L0_Replacement,
Icache.cacheProbe(in_msg.LineAddress),
getICacheEntry(Icache.cacheProbe(in_msg.LineAddress)),
TBEs[Icache.cacheProbe(in_msg.LineAddress)]);
@@ -354,6 +357,9 @@
Dcache_entry, TBEs[in_msg.LineAddress]);
} else {
// No room in the L1, so we need to make room in the L0
+ // Check if the line we want to evict is not locked
+ Addr addr := Dcache.cacheProbe(in_msg.LineAddress);
+ check_on_cache_probe(mandatoryQueue_in, addr);
trigger(Event:L0_Replacement,
Dcache.cacheProbe(in_msg.LineAddress),
getDCacheEntry(Dcache.cacheProbe(in_msg.LineAddress)),
TBEs[Dcache.cacheProbe(in_msg.LineAddress)]);
--
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Gerrit-Change-Number: 19868
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[gem5-dev] Change in gem5/gem5[master]: sim-se, tests: add a new sim-se test
Brandon Potter has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/17112 ) Change subject: sim-se, tests: add a new sim-se test .. sim-se, tests: add a new sim-se test This changeset adds a test to check the redirection features added in faux-filesystem changeset. The test contains a "chdir" system call to "/proc" which should be redirected to "$(gem5-dir)/m5out/fs/proc" (as specified by the config files). After "chdir", the test subsequently outputs the "/proc/cpuinfo" file which should output a configuration of a fake cpu with values set by a Python configuration file. Note, the test will call "clone" once. To avoid a runtime error, make sure that you run this test with "-n2" supplied to the "config/example/se.py" script. Change-Id: I505b046b7a4feddfa93a6ef0f0773ac43078cc94 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17112 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- A tests/test-progs/chdir-print/Makefile A tests/test-progs/chdir-print/README.txt A tests/test-progs/chdir-print/chdir-print.c 3 files changed, 167 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/tests/test-progs/chdir-print/Makefile b/tests/test-progs/chdir-print/Makefile new file mode 100644 index 000..6a357d5 --- /dev/null +++ b/tests/test-progs/chdir-print/Makefile @@ -0,0 +1,20 @@ + +CPP := g++ + +TEST_OBJS := chdir-print.o +TEST_PROGS := $(TEST_OBJS:.o=) + +# Rules == + +.PHONY: default clean + +default: $(TEST_PROGS) + +clean: + $(RM) $(TEST_OBJS) $(TEST_PROGS) + +$(TEST_PROGS): $(TEST_OBJS) + $(CPP) -static -o $@ $@.o + +%.o: %.c Makefile + $(CPP) -c -o $@ $*.c -msse3 diff --git a/tests/test-progs/chdir-print/README.txt b/tests/test-progs/chdir-print/README.txt new file mode 100644 index 000..b1e9213 --- /dev/null +++ b/tests/test-progs/chdir-print/README.txt @@ -0,0 +1,67 @@ +# example test compile and run parameters +# Note: the absolute path to the chdir-print binary should be specified +# in the run command even if running from the same folder. This is needed +# because chdir is executed before triggering a clone for the file read, +# and the cloned process won't be able to find the executable if a relative +# path is provided. + +# compile examples +scons --default=X86 ./build/X86/gem5.opt PROTOCOL=MOESI_hammer +scons --default=X86 ./build/X86/gem5.opt PROTOCOL=MESI_Three_Level + +# run parameters +/build/X86/gem5.opt /configs/example/se.py -c /tests/test-progs/chdir-print/chdir-print -n2 --ruby + + +# example successful output for MESI_Three_Level: + +<...> + + REAL SIMULATION +info: Entering event queue @ 0. Starting simulation... +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! +cwd: /proj/research_simu/users/jalsop/gem5-mem_dif_debug/tests/test-progs/chdir-print/ +cwd: /proc + +<...> + +processor : 0 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping: 0 +cpu MHz : 2000 +cache size: : 2048K +physical id : 0 +siblings: 2 +core id : 0 +cpu cores : 2 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + +processor : 1 +vendor_id : Generic +cpu family : 0 +model : 0 +model name : Generic +stepping: 0 +cpu MHz : 2000 +cache size: : 2048K +physical id : 0 +siblings: 2 +core id : 1 +cpu cores : 2 +fpu : yes +fpu exception : yes +cpuid level : 1 +wp : yes +flags : fpu +cache alignment : 64 + +SUCCESS +Exiting @ tick 2694923000 because exiting with last active thread context diff --git a/tests/test-progs/chdir-print/chdir-print.c b/tests/test-progs/chdir-print/chdir-print.c new file mode 100644 index 000..9fe42cd --- /dev/null +++ b/tests/test-progs/chdir-print/chdir-print.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2011-2015 Advanced Micro Devices, Inc. + * All rights reserved. + * + * For use for simulation and test purposes only + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the
[gem5-dev] Change in gem5/gem5[master]: tests: Refactor the Gem5Fixture to derive from UniqueFixture
Hello kokoro, Ciro Santilli, Giacomo Travaglini, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19251 to look at the new patch set (#10). Change subject: tests: Refactor the Gem5Fixture to derive from UniqueFixture .. tests: Refactor the Gem5Fixture to derive from UniqueFixture Gem5Fixture is used to define a fixture for building the gem5 binary. Most tests are expected to define their own Gem5Fixture, however, as some might depend on the same binary (e.g., ./build/ARM/gem5.opt), they will try to re-define a fixture for the same target. This patchset changes Gem5Fixture to derive from UniqueFixture. In addition, this patchset changes the way global fixtures are discovered to work with the new Gem5Fixture class. Instead of enumerating them when test definitions are loaded, we do so after the tests have been filtered according to specified tags (e.g., include opt variant, exclude fast, debug variants). Change-Id: Ie868a7e18ef6c3271f3c8a658229657cd43997cb --- M ext/testlib/fixture.py M ext/testlib/loader.py M ext/testlib/main.py M ext/testlib/wrappers.py M tests/gem5/fixture.py 5 files changed, 51 insertions(+), 121 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19251 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie868a7e18ef6c3271f3c8a658229657cd43997cb Gerrit-Change-Number: 19251 Gerrit-PatchSet: 10 Gerrit-Owner: Nikos Nikoleris Gerrit-Assignee: Jason Lowe-Power Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu-o3: fix atomic instructions non-speculative
Jordi Vaquero has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/19815 ) Change subject: cpu-o3: fix atomic instructions non-speculative .. cpu-o3: fix atomic instructions non-speculative Fix problem with O3 and AMO instructions. At initial stages amo instruction is considered a type of non-speculative store. After the instruction has been commited and during the squash step, acquire_release version of the AMO operation is considered speculative, that differents results in an assert fault. This fix ensures that AMO instructions are always considered non-speculative, during early stages and during squas/removal of the instruction. Change-Id: Ia0c5fbb9dc44a9991337b57eb759b1ed08e4149e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19815 Maintainer: Jason Lowe-Power Reviewed-by: Jason Lowe-Power Tested-by: kokoro --- M src/cpu/o3/inst_queue_impl.hh 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index c3e3fdf..f3362f2 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -1262,7 +1262,6 @@ bool is_acq_rel = squashed_inst->isMemBarrier() && (squashed_inst->isLoad() || - squashed_inst->isAtomic() || (squashed_inst->isStore() && !squashed_inst->isStoreConditional())); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19815 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ia0c5fbb9dc44a9991337b57eb759b1ed08e4149e Gerrit-Change-Number: 19815 Gerrit-PatchSet: 11 Gerrit-Owner: Jordi Vaquero Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jordi Vaquero Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Tuan Ta Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu-o3: added _amo_op parameter in o3 LSQ
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19814 )
Change subject: cpu-o3: added _amo_op parameter in o3 LSQ
..
cpu-o3: added _amo_op parameter in o3 LSQ
Fix bug with AMO (or RMW) instructions where the amo_op variable
is not being propagated to the LSQ request.
Change-Id: I60c59641d9b497051376f638e27f3c4cc361f615
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19814
Maintainer: Andreas Sandberg
Maintainer: Anthony Gutierrez
Tested-by: kokoro
Reviewed-by: Andreas Sandberg
Reviewed-by: Anthony Gutierrez
---
M src/cpu/o3/lsq.hh
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 4701a8c..29c76f7 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -366,7 +366,7 @@
isAnyActiveElement(byteEnable.begin(), byteEnable.end())) {
auto request = std::make_shared(_inst->getASID(),
addr, size, _flags, _inst->masterId(),
-_inst->instAddr(), _inst->contextId());
+_inst->instAddr(), _inst->contextId(), _amo_op);
if (!byteEnable.empty()) {
request->setByteEnable(byteEnable);
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I60c59641d9b497051376f638e27f3c4cc361f615
Gerrit-Change-Number: 19814
Gerrit-PatchSet: 11
Gerrit-Owner: Jordi Vaquero
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jordi Vaquero
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add TypeAtomicOp class to be used by new atomic instructions
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19810 )
Change subject: arch-arm: Add TypeAtomicOp class to be used by new atomic
instructions
..
arch-arm: Add TypeAtomicOp class to be used by new atomic instructions
Creating a new object TypeAtomicOp that will be used by the atomic
instructions following gem5 AMO feature.
Change-Id: If082b596fb37d7a1cb569a4320c23505591df6a5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19810
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/insts/mem64.hh
1 file changed, 46 insertions(+), 0 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/insts/mem64.hh b/src/arch/arm/insts/mem64.hh
index 8e21bb3..34eb43f 100644
--- a/src/arch/arm/insts/mem64.hh
+++ b/src/arch/arm/insts/mem64.hh
@@ -260,6 +260,52 @@
std::string generateDisassembly(
Addr pc, const SymbolTable *symtab) const override;
};
+
+/**
+ * A generic atomic op class
+ */
+
+template
+class AtomicGeneric2Op : public TypedAtomicOpFunctor
+{
+ public:
+AtomicGeneric2Op(T _a, std::function _op)
+: a(_a), op(_op)
+{}
+AtomicOpFunctor* clone() override
+{
+return new AtomicGeneric2Op(*this);
+}
+void execute(T *b) override
+{
+op(b, a);
+}
+ private:
+T a;
+std::function op;
+ };
+
+template
+class AtomicGeneric3Op : public TypedAtomicOpFunctor
+{
+ public:
+AtomicGeneric3Op(T _a, T _c, std::function _op)
+: a(_a), c(_c), op(_op)
+{}
+AtomicOpFunctor* clone() override
+{
+return new AtomicGeneric3Op(*this);
+}
+void execute(T *b) override
+{
+op(b, a, c);
+}
+ private:
+T a;
+T c;
+std::function op;
+};
+
}
#endif //__ARCH_ARM_INSTS_MEM_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: If082b596fb37d7a1cb569a4320c23505591df6a5
Gerrit-Change-Number: 19810
Gerrit-PatchSet: 5
Gerrit-Owner: Jordi Vaquero
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jordi Vaquero
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Cron /z/m5/regression/do-regression quick
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: FAILED! * build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: FAILED! * build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: FAILED! * build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory: FAILED! * build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp: CHANGED! * build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby: CHANGED! * build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic: CHANGED! * build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: CHANGED! * build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing: CHANGED! * build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic: CHANGED! * build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic: CHANGED! * build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing: CHANGED! * build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level: CHANGED! * build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple: CHANGED! * build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker: CHANGED! * build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing: CHANGED! * build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic: CHANGED! *
[gem5-dev] Change in gem5/gem5[master]: tests: Refactor the Gem5Fixture to derive from UniqueFixture
Hello kokoro, Ciro Santilli, Giacomo Travaglini, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19251 to look at the new patch set (#9). Change subject: tests: Refactor the Gem5Fixture to derive from UniqueFixture .. tests: Refactor the Gem5Fixture to derive from UniqueFixture Change-Id: Ie868a7e18ef6c3271f3c8a658229657cd43997cb --- M ext/testlib/fixture.py M ext/testlib/loader.py M ext/testlib/main.py M ext/testlib/wrappers.py M tests/gem5/fixture.py 5 files changed, 51 insertions(+), 121 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19251 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie868a7e18ef6c3271f3c8a658229657cd43997cb Gerrit-Change-Number: 19251 Gerrit-PatchSet: 9 Gerrit-Owner: Nikos Nikoleris Gerrit-Assignee: Jason Lowe-Power Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: adding register control flags enabling LSE implementation
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19809 )
Change subject: arch-arm: adding register control flags enabling LSE
implementation
..
arch-arm: adding register control flags enabling LSE implementation
Added changes on arch-arm architecture to accept Atomic instructions
following ARM v8.1 documentation. That includes enabling atomic bit
in ID registers and add have_lse variable into arm system.
Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19809
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
5 files changed, 20 insertions(+), 0 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index daf94a9..a92ae4f 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -86,6 +86,8 @@
"True if SVE is implemented (ARMv8)")
sve_vl = Param.SveVectorLength(1,
"SVE vector length in quadwords (128-bit)")
+have_lse = Param.Bool(True,
+"True if LSE is implemented (ARMv8.1)")
have_pan = Param.Bool(True,
"True if Priviledge Access Never is implemented (ARMv8.1)")
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 23738c6..299698d 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -93,6 +93,7 @@
haveSVE = system->haveSVE();
havePAN = system->havePAN();
sveVL = system->sveVL();
+haveLSE = system->haveLSE();
} else {
highestELIs64 = true; // ArmSystem::highestELIs64 does the same
haveSecurity = haveLPAE = haveVirtualization = false;
@@ -102,6 +103,7 @@
haveSVE = true;
havePAN = false;
sveVL = p->sve_vl_se;
+haveLSE = true;
}
// Initial rename mode depends on highestEL
@@ -393,6 +395,10 @@
miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
haveCrypto ? 0x1112 : 0x0);
+// LSE
+miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
+miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
+haveLSE ? 0x2 : 0x0);
// PAN
miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 63051cd..5e337c2 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -95,6 +95,7 @@
bool haveGICv3CPUInterface;
uint8_t physAddrRange;
bool haveSVE;
+bool haveLSE;
bool havePAN;
/** SVE vector length in quadwords */
@@ -687,6 +688,7 @@
SERIALIZE_SCALAR(physAddrRange);
SERIALIZE_SCALAR(haveSVE);
SERIALIZE_SCALAR(sveVL);
+SERIALIZE_SCALAR(haveLSE);
SERIALIZE_SCALAR(havePAN);
}
void unserialize(CheckpointIn )
@@ -704,6 +706,7 @@
UNSERIALIZE_SCALAR(physAddrRange);
UNSERIALIZE_SCALAR(haveSVE);
UNSERIALIZE_SCALAR(sveVL);
+UNSERIALIZE_SCALAR(haveLSE);
UNSERIALIZE_SCALAR(havePAN);
}
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 874e3b0..4ea0d1a 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -73,6 +73,7 @@
_haveLargeAsid64(p->have_large_asid_64),
_haveSVE(p->have_sve),
_sveVL(p->sve_vl),
+ _haveLSE(p->have_lse),
_havePAN(p->have_pan),
_m5opRange(p->m5ops_base ?
RangeSize(p->m5ops_base, 0x1) :
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index e09f477..46c58e8 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -130,6 +130,11 @@
/** SVE vector length at reset, in quadwords */
const unsigned _sveVL;
+/**
+ * True if LSE is implemented (ARMv8.1)
+ */
+const bool _haveLSE;
+
/** True if Priviledge Access Never is implemented */
const unsigned _havePAN;
@@ -244,6 +249,9 @@
/** Returns the SVE vector length at reset, in quadwords */
unsigned sveVL() const { return _sveVL; }
+/** Returns true if LSE is implemented (ARMv8.1) */
+bool haveLSE() const { return _haveLSE; }
+
/** Returns true if Priviledge Access Never is implemented */
bool havePAN() const { return _havePAN; }
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19809
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de
Gerrit-Change-Number:
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add TypeAtomicOp class to be used by new atomic instructions
Hello Andreas Sandberg, kokoro, Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19810 to look at the new patch set (#4). Change subject: arch-arm: Add TypeAtomicOp class to be used by new atomic instructions .. arch-arm: Add TypeAtomicOp class to be used by new atomic instructions Creating a new object TypeAtomicOp that will be used by the atomic instructions following gem5 AMO feature. Change-Id: If082b596fb37d7a1cb569a4320c23505591df6a5 --- M src/arch/arm/insts/mem64.hh 1 file changed, 46 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19810 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: If082b596fb37d7a1cb569a4320c23505591df6a5 Gerrit-Change-Number: 19810 Gerrit-PatchSet: 4 Gerrit-Owner: Jordi Vaquero Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jordi Vaquero Gerrit-Reviewer: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func
Hello Andreas Sandberg, Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19811 to look at the new patch set (#6). Change subject: arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func .. arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func CAS/CASP atomic instruction implementation This change includes: + Instructions decode + new amo64.isa file where CAS/CASP main functional code is implemented + mem64.isa include Execute/complete/initiatie skeletons, contructor and declarator + Added TypedAtomic function for pair register CASP instruction Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf --- M src/arch/arm/insts/mem64.hh M src/arch/arm/isa/formats/aarch64.isa A src/arch/arm/isa/insts/amo64.isa M src/arch/arm/isa/insts/insts.isa M src/arch/arm/isa/templates/mem64.isa 5 files changed, 696 insertions(+), 7 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19811 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf Gerrit-Change-Number: 19811 Gerrit-PatchSet: 6 Gerrit-Owner: Jordi Vaquero Gerrit-Assignee: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jordi Vaquero Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add TypeAtomicOp class to be used by new atomic instructions
Hello Andreas Sandberg, kokoro, Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19810 to look at the new patch set (#3). Change subject: arch-arm: Add TypeAtomicOp class to be used by new atomic instructions .. arch-arm: Add TypeAtomicOp class to be used by new atomic instructions Creating a new object TypeAtomicOp that will be used by the atomic instructions following gem5 AMO feature. Change-Id: If082b596fb37d7a1cb569a4320c23505591df6a5 --- M src/arch/arm/insts/mem64.hh 1 file changed, 46 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19810 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: If082b596fb37d7a1cb569a4320c23505591df6a5 Gerrit-Change-Number: 19810 Gerrit-PatchSet: 3 Gerrit-Owner: Jordi Vaquero Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Added LD/ST atomic instruction family and SWP instrs
Hello Andreas Sandberg, Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19812 to look at the new patch set (#5). Change subject: arch-arm: Added LD/ST atomic instruction family and SWP instrs .. arch-arm: Added LD/ST atomic instruction family and SWP instrs Adding LD/ST/SWP family of instructions, LD/ST include a set of operations like ADD/CLR/EOR/SET/UMAX/UMIN/SMAX/SMIN This commit includes: + Instruction decode + Instruction functional code + New set of skeletons for Ex/Com/Ini/Constructor and declaration. Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116 --- M src/arch/arm/isa/formats/aarch64.isa M src/arch/arm/isa/insts/amo64.isa M src/arch/arm/isa/templates/mem64.isa 3 files changed, 1,039 insertions(+), 27 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19812 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116 Gerrit-Change-Number: 19812 Gerrit-PatchSet: 5 Gerrit-Owner: Jordi Vaquero Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: cpu-o3: added _amo_op parameter in o3 LSQ
Hello Andreas Sandberg, kokoro, Giacomo Travaglini, Anthony Gutierrez, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19814 to look at the new patch set (#7). Change subject: cpu-o3: added _amo_op parameter in o3 LSQ .. cpu-o3: added _amo_op parameter in o3 LSQ Fix bug with AMO (or RMW) instructions where the amo_op variable is not being propagated to the LSQ request. Change-Id: I60c59641d9b497051376f638e27f3c4cc361f615 --- M src/cpu/o3/lsq.hh 1 file changed, 1 insertion(+), 1 deletion(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19814 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I60c59641d9b497051376f638e27f3c4cc361f615 Gerrit-Change-Number: 19814 Gerrit-PatchSet: 7 Gerrit-Owner: Jordi Vaquero Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: adding register control flags enabling LSE implementation
Hello Andreas Sandberg, kokoro, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19809 to look at the new patch set (#3). Change subject: arch-arm: adding register control flags enabling LSE implementation .. arch-arm: adding register control flags enabling LSE implementation Added changes on arch-arm architecture to accept Atomic instructions following ARM v8.1 documentation. That includes enabling atomic bit in ID registers and add have_lse variable into arm system. Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de --- M src/arch/arm/ArmSystem.py M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/system.cc M src/arch/arm/system.hh 5 files changed, 20 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19809 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de Gerrit-Change-Number: 19809 Gerrit-PatchSet: 3 Gerrit-Owner: Jordi Vaquero Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: kokoro Gerrit-CC: Giacomo Travaglini Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add TypeAtomicOp class to be used by new atomic instructions
Jordi Vaquero has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/c/public/gem5/+/19849 ) Change subject: arch-arm: Add TypeAtomicOp class to be used by new atomic instructions .. arch-arm: Add TypeAtomicOp class to be used by new atomic instructions Creating a new object TypeAtomicOp that will be used by the atomic instructions following gem5 AMO feature. Change-Id: I8b6d9d3738bec5cfaf7449fd787551be2db8cd81 --- M src/arch/arm/insts/mem64.hh 1 file changed, 46 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19849 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I8b6d9d3738bec5cfaf7449fd787551be2db8cd81 Gerrit-Change-Number: 19849 Gerrit-PatchSet: 2 Gerrit-Owner: Jordi Vaquero Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Added LD/ST atomic instruction family and SWP instrs
Hello Andreas Sandberg, Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19812 to look at the new patch set (#4). Change subject: arch-arm: Added LD/ST atomic instruction family and SWP instrs .. arch-arm: Added LD/ST atomic instruction family and SWP instrs Adding LD/ST/SWP family of instructions, LD/ST include a set of operations like ADD/CLR/EOR/SET/UMAX/UMIN/SMAX/SMIN This commit includes: + Instruction decode + Instruction functional code + New set of skeletons for Ex/Com/Ini/Constructor and declaration. Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116 --- M src/arch/arm/isa/formats/aarch64.isa M src/arch/arm/isa/insts/amo64.isa M src/arch/arm/isa/templates/mem64.isa 3 files changed, 1,039 insertions(+), 27 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19812 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116 Gerrit-Change-Number: 19812 Gerrit-PatchSet: 4 Gerrit-Owner: Jordi Vaquero Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func
Hello Andreas Sandberg, Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19811 to look at the new patch set (#4). Change subject: arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func .. arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func CAS/CASP atomic instruction implementation This change includes: + Instructions decode + new amo64.isa file where CAS/CASP main functional code is implemented + mem64.isa include Execute/complete/initiatie skeletons, contructor and declarator + Added TypedAtomic function for pair register CASP instruction Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf --- M src/arch/arm/insts/mem64.hh M src/arch/arm/isa/formats/aarch64.isa A src/arch/arm/isa/insts/amo64.isa M src/arch/arm/isa/insts/insts.isa M src/arch/arm/isa/templates/mem64.isa 5 files changed, 695 insertions(+), 7 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19811 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf Gerrit-Change-Number: 19811 Gerrit-PatchSet: 4 Gerrit-Owner: Jordi Vaquero Gerrit-Assignee: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: adding register control flags enabling LSE implementation
Jordi Vaquero has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/c/public/gem5/+/19848 ) Change subject: arch-arm: adding register control flags enabling LSE implementation .. arch-arm: adding register control flags enabling LSE implementation Added changes on arch-arm architecture to accept Atomic instructions following ARM v8.1 documentation. That includes enabling atomic bit in ID registers and add have_lse variable into arm system. Change-Id: I79c65170f9a4dbc317041f987897444c025fb536 --- M src/arch/arm/ArmSystem.py M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/system.cc M src/arch/arm/system.hh 5 files changed, 20 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19848 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I79c65170f9a4dbc317041f987897444c025fb536 Gerrit-Change-Number: 19848 Gerrit-PatchSet: 2 Gerrit-Owner: Jordi Vaquero Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: adding register control flags enabling LSE implementation
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19848 )
Change subject: arch-arm: adding register control flags enabling LSE
implementation
..
arch-arm: adding register control flags enabling LSE implementation
Added changes on arch-arm architecture to accept Atomic instructions
following ARM v8.1 documentation. That includes enabling atomic bit
in control registers and add have_lse variable into arm system.
Change-Id: I79c65170f9a4dbc317041f987897444c025fb536
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
5 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index daf94a9..a92ae4f 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -86,6 +86,8 @@
"True if SVE is implemented (ARMv8)")
sve_vl = Param.SveVectorLength(1,
"SVE vector length in quadwords (128-bit)")
+have_lse = Param.Bool(True,
+"True if LSE is implemented (ARMv8.1)")
have_pan = Param.Bool(True,
"True if Priviledge Access Never is implemented (ARMv8.1)")
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 23738c6..299698d 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -93,6 +93,7 @@
haveSVE = system->haveSVE();
havePAN = system->havePAN();
sveVL = system->sveVL();
+haveLSE = system->haveLSE();
} else {
highestELIs64 = true; // ArmSystem::highestELIs64 does the same
haveSecurity = haveLPAE = haveVirtualization = false;
@@ -102,6 +103,7 @@
haveSVE = true;
havePAN = false;
sveVL = p->sve_vl_se;
+haveLSE = true;
}
// Initial rename mode depends on highestEL
@@ -393,6 +395,10 @@
miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
haveCrypto ? 0x1112 : 0x0);
+// LSE
+miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
+miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
+haveLSE ? 0x2 : 0x0);
// PAN
miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 63051cd..5e337c2 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -95,6 +95,7 @@
bool haveGICv3CPUInterface;
uint8_t physAddrRange;
bool haveSVE;
+bool haveLSE;
bool havePAN;
/** SVE vector length in quadwords */
@@ -687,6 +688,7 @@
SERIALIZE_SCALAR(physAddrRange);
SERIALIZE_SCALAR(haveSVE);
SERIALIZE_SCALAR(sveVL);
+SERIALIZE_SCALAR(haveLSE);
SERIALIZE_SCALAR(havePAN);
}
void unserialize(CheckpointIn )
@@ -704,6 +706,7 @@
UNSERIALIZE_SCALAR(physAddrRange);
UNSERIALIZE_SCALAR(haveSVE);
UNSERIALIZE_SCALAR(sveVL);
+UNSERIALIZE_SCALAR(haveLSE);
UNSERIALIZE_SCALAR(havePAN);
}
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 874e3b0..4ea0d1a 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -73,6 +73,7 @@
_haveLargeAsid64(p->have_large_asid_64),
_haveSVE(p->have_sve),
_sveVL(p->sve_vl),
+ _haveLSE(p->have_lse),
_havePAN(p->have_pan),
_m5opRange(p->m5ops_base ?
RangeSize(p->m5ops_base, 0x1) :
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index e09f477..46c58e8 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -130,6 +130,11 @@
/** SVE vector length at reset, in quadwords */
const unsigned _sveVL;
+/**
+ * True if LSE is implemented (ARMv8.1)
+ */
+const bool _haveLSE;
+
/** True if Priviledge Access Never is implemented */
const unsigned _havePAN;
@@ -244,6 +249,9 @@
/** Returns the SVE vector length at reset, in quadwords */
unsigned sveVL() const { return _sveVL; }
+/** Returns true if LSE is implemented (ARMv8.1) */
+bool haveLSE() const { return _haveLSE; }
+
/** Returns true if Priviledge Access Never is implemented */
bool havePAN() const { return _havePAN; }
--
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Gerrit-Branch: master
Gerrit-Change-Id: I79c65170f9a4dbc317041f987897444c025fb536
Gerrit-Change-Number: 19848
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: cpu-o3: fix atomic instructions non-speculative
Jordi Vaquero has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/19850 ) Change subject: cpu-o3: fix atomic instructions non-speculative .. cpu-o3: fix atomic instructions non-speculative Fix problem with O3 and AMO instructions. At initial stages amo instruction is considered a type of non-speculative store. After the instruction has been commited and during the squash step, acquire_release version of the AMO operation is considered speculative, that differents results in an assert fault. This fix ensures that AMO instructions are always considered non-speculative, during early stages and during squas/removal of the instruction. Change-Id: Iccd981bc6d271b8259399ae668b3c1851562fb84 --- M src/cpu/o3/inst_queue_impl.hh 1 file changed, 0 insertions(+), 1 deletion(-) diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index c3e3fdf..f3362f2 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -1262,7 +1262,6 @@ bool is_acq_rel = squashed_inst->isMemBarrier() && (squashed_inst->isLoad() || - squashed_inst->isAtomic() || (squashed_inst->isStore() && !squashed_inst->isStoreConditional())); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19850 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Iccd981bc6d271b8259399ae668b3c1851562fb84 Gerrit-Change-Number: 19850 Gerrit-PatchSet: 1 Gerrit-Owner: Jordi Vaquero Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add TypeAtomicOp class to be used by new atomic instructions
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19849 )
Change subject: arch-arm: Add TypeAtomicOp class to be used by new atomic
instructions
..
arch-arm: Add TypeAtomicOp class to be used by new atomic instructions
Creating a new object TypeAtomicOp that will be used by the atomic
instructions following gem5 AMO feature.
Change-Id: I8b6d9d3738bec5cfaf7449fd787551be2db8cd81
---
M src/arch/arm/insts/mem64.hh
1 file changed, 46 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/insts/mem64.hh b/src/arch/arm/insts/mem64.hh
index 8e21bb3..57328a7 100644
--- a/src/arch/arm/insts/mem64.hh
+++ b/src/arch/arm/insts/mem64.hh
@@ -260,6 +260,52 @@
std::string generateDisassembly(
Addr pc, const SymbolTable *symtab) const override;
};
+
+/**
+ * A generic atomic op class
+ */
+
+template
+class AtomicGenericOp : public TypedAtomicOpFunctor
+{
+ public:
+AtomicGenericOp(T _a, std::function _op)
+: a(_a), op(_op)
+{}
+AtomicOpFunctor* clone()
+{
+ return new AtomicGenericOp(*this);
+}
+void execute(T *b)
+{
+ op(b, a);
+}
+ private:
+T a;
+std::function op;
+ };
+
+template
+class AtomicGenericOp3Param : public TypedAtomicOpFunctor
+{
+ public:
+AtomicGenericOp3Param(T _a, T _c, std::function _op)
+ : a(_a), c(_c), op(_op)
+{}
+AtomicOpFunctor* clone()
+{
+ return new AtomicGenericOp3Param(*this);
+}
+void execute(T *b)
+{
+ op(b, a, c);
+}
+ private:
+T a;
+T c;
+std::function op;
+};
+
}
#endif //__ARCH_ARM_INSTS_MEM_HH__
--
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Gerrit-Change-Number: 19849
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Gerrit-Owner: Jordi Vaquero
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Added LD/ST atomic instruction family and SWP instrs
Hello Andreas Sandberg, Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19812 to look at the new patch set (#3). Change subject: arch-arm: Added LD/ST atomic instruction family and SWP instrs .. arch-arm: Added LD/ST atomic instruction family and SWP instrs Adding LD/ST/SWP family of instructions, LD/ST include a set of operations like ADD/CLR/EOR/SET/UMAX/UMIN/SMAX/SMIN This commit includes: + Instruction decode + Instruction functional code + New set of skeletons for Ex/Com/Ini/Constructor and declaration. Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116 --- M src/arch/arm/isa/formats/aarch64.isa M src/arch/arm/isa/insts/amo64.isa M src/arch/arm/isa/templates/mem64.isa 3 files changed, 1,039 insertions(+), 27 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19812 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116 Gerrit-Change-Number: 19812 Gerrit-PatchSet: 3 Gerrit-Owner: Jordi Vaquero Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: tests: Add base class for fixtures that generate a target file
Hello kokoro, Ciro Santilli, Giacomo Travaglini, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19250 to look at the new patch set (#8). Change subject: tests: Add base class for fixtures that generate a target file .. tests: Add base class for fixtures that generate a target file The new TargetFixture can be used as a base class for fixtures that generate/download a file. These fixtures are guarrantied to be unique and their setup function is only executed once. Change-Id: I6a8737b06c4e74f3e29736ec363f61251d85da8c Signed-off-by: Nikos Nikoleris --- M tests/gem5/fixture.py 1 file changed, 52 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19250 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I6a8737b06c4e74f3e29736ec363f61251d85da8c Gerrit-Change-Number: 19250 Gerrit-PatchSet: 8 Gerrit-Owner: Nikos Nikoleris Gerrit-Assignee: Jason Lowe-Power Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: tests: Refactor the Gem5Fixture to derive from UniqueFixture
Hello kokoro, Ciro Santilli, Giacomo Travaglini, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19251 to look at the new patch set (#8). Change subject: tests: Refactor the Gem5Fixture to derive from UniqueFixture .. tests: Refactor the Gem5Fixture to derive from UniqueFixture Change-Id: Ie868a7e18ef6c3271f3c8a658229657cd43997cb --- M ext/testlib/fixture.py M ext/testlib/loader.py M ext/testlib/main.py M ext/testlib/wrappers.py M tests/gem5/fixture.py 5 files changed, 50 insertions(+), 119 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19251 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie868a7e18ef6c3271f3c8a658229657cd43997cb Gerrit-Change-Number: 19251 Gerrit-PatchSet: 8 Gerrit-Owner: Nikos Nikoleris Gerrit-Assignee: Jason Lowe-Power Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: tests: Add Arm full system regressions to the new framework
Hello Andreas Sandberg, Rahul Thakur, kokoro, Giacomo Travaglini, Jason Lowe-Power, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/18989 to look at the new patch set (#13). Change subject: tests: Add Arm full system regressions to the new framework .. tests: Add Arm full system regressions to the new framework Change-Id: I7e0499c8c3d63798d44f936580eecd40dc650694 Signed-off-by: Nikos Nikoleris --- A tests/gem5/fs/linux/arm/run.py A tests/gem5/fs/linux/arm/test.py 2 files changed, 196 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18989 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I7e0499c8c3d63798d44f936580eecd40dc650694 Gerrit-Change-Number: 18989 Gerrit-PatchSet: 13 Gerrit-Owner: Nikos Nikoleris Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Rahul Thakur Gerrit-Reviewer: kokoro Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: dev-arm: Perform SMMUv3 CFG Invalidation at device interface
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19813 )
Change subject: dev-arm: Perform SMMUv3 CFG Invalidation at device interface
..
dev-arm: Perform SMMUv3 CFG Invalidation at device interface
In the current SMMUv3 model, multiple micro/mainTLB are present at the
device interface (SMMUv3SlaveInterface), caching translations specific
to a device.
Those distributed TLBs are checked for a translation before checking for
centralized TLBs (shared by devices), like the configuration cache, walk
cache etc. This means that if a hit in these TLBs occurs, there won't
be a need to enter configuration stage (which is where the STE and CD
are retrieved). So if we invalidate a cached configuration (in
ConfigCache), we need to invalidate those interface TLB entries as well,
otherwise in theory we will keep the same translation even after a
change in configuration tables.
Change-Id: I4aa36ba8392a530267517bef7562318b282bee25
Signed-off-by: Giacomo Travaglini
Reviewed-by: Michiel van Tol
Reviewed-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19813
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/dev/arm/smmu_v3.cc
M src/dev/arm/smmu_v3_caches.cc
M src/dev/arm/smmu_v3_caches.hh
3 files changed, 66 insertions(+), 1 deletion(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/smmu_v3.cc b/src/dev/arm/smmu_v3.cc
index 2853929..f17ef95 100644
--- a/src/dev/arm/smmu_v3.cc
+++ b/src/dev/arm/smmu_v3.cc
@@ -395,6 +395,11 @@
case CMD_CFGI_STE: {
DPRINTF(SMMUv3, "CMD_CFGI_STE sid=%#x\n", cmd.dw0.sid);
configCache.invalidateSID(cmd.dw0.sid);
+
+for (auto slave_interface : slaveInterfaces) {
+slave_interface->microTLB->invalidateSID(cmd.dw0.sid);
+slave_interface->mainTLB->invalidateSID(cmd.dw0.sid);
+}
break;
}
@@ -405,12 +410,23 @@
// range = 31
DPRINTF(SMMUv3, "CMD_CFGI_ALL\n");
configCache.invalidateAll();
+
+for (auto slave_interface : slaveInterfaces) {
+slave_interface->microTLB->invalidateAll();
+slave_interface->mainTLB->invalidateAll();
+}
} else {
DPRINTF(SMMUv3, "CMD_CFGI_STE_RANGE\n");
const auto start_sid = cmd.dw0.sid & ~((1 << (range + 1))
- 1);
const auto end_sid = start_sid + (1 << (range + 1)) - 1;
-for (auto sid = start_sid; sid <= end_sid; sid++)
+for (auto sid = start_sid; sid <= end_sid; sid++) {
configCache.invalidateSID(sid);
+
+for (auto slave_interface : slaveInterfaces) {
+slave_interface->microTLB->invalidateSID(sid);
+slave_interface->mainTLB->invalidateSID(sid);
+}
+}
}
break;
}
@@ -419,12 +435,24 @@
DPRINTF(SMMUv3, "CMD_CFGI_CD sid=%#x ssid=%#x\n",
cmd.dw0.sid, cmd.dw0.ssid);
configCache.invalidateSSID(cmd.dw0.sid, cmd.dw0.ssid);
+
+for (auto slave_interface : slaveInterfaces) {
+slave_interface->microTLB->invalidateSSID(
+cmd.dw0.sid, cmd.dw0.ssid);
+slave_interface->mainTLB->invalidateSSID(
+cmd.dw0.sid, cmd.dw0.ssid);
+}
break;
}
case CMD_CFGI_CD_ALL: {
DPRINTF(SMMUv3, "CMD_CFGI_CD_ALL sid=%#x\n", cmd.dw0.sid);
configCache.invalidateSID(cmd.dw0.sid);
+
+for (auto slave_interface : slaveInterfaces) {
+slave_interface->microTLB->invalidateSID(cmd.dw0.sid);
+slave_interface->mainTLB->invalidateSID(cmd.dw0.sid);
+}
break;
}
diff --git a/src/dev/arm/smmu_v3_caches.cc b/src/dev/arm/smmu_v3_caches.cc
index 6dcaec6..63f0b05 100644
--- a/src/dev/arm/smmu_v3_caches.cc
+++ b/src/dev/arm/smmu_v3_caches.cc
@@ -258,6 +258,34 @@
}
void
+SMMUTLB::invalidateSSID(uint32_t sid, uint32_t ssid)
+{
+Set = sets[pickSetIdx(sid, ssid)];
+
+for (size_t i = 0; i < set.size(); i++) {
+Entry = set[i];
+
+if (e.sid == sid && e.ssid == ssid)
+e.valid = false;
+}
+}
+
+void
+SMMUTLB::invalidateSID(uint32_t sid)
+{
+for (size_t s = 0; s < sets.size(); s++) {
+Set = sets[s];
+
+for (size_t i = 0; i < set.size(); i++) {
+Entry = set[i];
+
+if (e.sid == sid)
+e.valid = false;
+}
+}
+}
+
+void
SMMUTLB::invalidateVA(Addr va, uint16_t asid, uint16_t vmid)
{
Set =
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Fix non-virtual base destructor of Repl Entry
Daniel Carvalho has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/19808 ) Change subject: mem-cache: Fix non-virtual base destructor of Repl Entry .. mem-cache: Fix non-virtual base destructor of Repl Entry ReplaceableEntry contains a virtual method, yet its destructor was not virtual, causing errors in some compilers. Change-Id: I13deec843f4007d9deb924882a8d98ff6a89c84f Signed-off-by: Daniel R. Carvalho Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19808 Reviewed-by: Nikos Nikoleris Maintainer: Nikos Nikoleris Tested-by: kokoro --- M src/mem/cache/replacement_policies/replaceable_entry.hh 1 file changed, 9 insertions(+), 6 deletions(-) Approvals: Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/mem/cache/replacement_policies/replaceable_entry.hh b/src/mem/cache/replacement_policies/replaceable_entry.hh index dffa4cf..c558bee 100644 --- a/src/mem/cache/replacement_policies/replaceable_entry.hh +++ b/src/mem/cache/replacement_policies/replaceable_entry.hh @@ -63,12 +63,15 @@ */ uint32_t _way; - public: - /** - * Replacement data associated to this entry. - * It must be instantiated by the replacement policy before being used. - */ - std::shared_ptr replacementData; + public: +ReplaceableEntry() = default; +virtual ~ReplaceableEntry() = default; + +/** + * Replacement data associated to this entry. + * It must be instantiated by the replacement policy before being used. + */ +std::shared_ptr replacementData; /** * Set both the set and way. Should be called only once. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19808 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I13deec843f4007d9deb924882a8d98ff6a89c84f Gerrit-Change-Number: 19808 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Carvalho Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Cron /z/m5/regression/do-regression quick
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: FAILED! * build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: FAILED! * build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: FAILED! * build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory: FAILED! * build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level: CHANGED! * build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: CHANGED! * build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level: CHANGED! *
