[gem5-users] Doubts in packet and request

[Riddhi Thakker]

Hello all,

I have observed that when I run benchmarks, the size of the packet is
always 64 bytes. Where as if I run small SE programs the sizes turns out to
be different. If I call an instruction of 'int' size, it will not call the
packet of size 64 bytes, it should be lesser.
Following are my questions:
1) Why every time the packet size is 64 when I run a benchmark ?
2) The packet which is created refer to only one instruction (i.e. one
request) or multiple ?
3)  If packet refers to only one instruction or request then how come for
all the kind of instructions is the packet size same ?
4) If a packet refers to different instructions or requests then how do I
infer how much data bytes do each instruction wants?
5) When I am trying to explicitly use the getReqInstSeqNum() function, then
why it gives me assertion failed error for VALID_INST_SEQ_NUM ?

I really want to get answers for these questions. It will be a great help
to me if anyone can get through this.

Thanks in advance.

Regards,
Riddhi Thakker
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[gem5-users] How to modify the Cache Timing Model ?

[梁政]

Hi




I am reading the latest code of gem5 and try to make the cache model more 
flexible (e.g., allowing non-constant access latency). So I will change the 
timing behavior of the Cache class.




Currently, I am reading the code in /mem/cache. I found that two major classes 
have their timing model: the Cache/NoncoherentCache/BaseCache family and the 
Tag family.




So what I need to do is to change related codes with a device timing model, 
right? Or there may be other points I missed? Thanks for your advice.




BTW, what are the FALRU tags for? It seems all configurations use SetAssoc 
Tags. I found a paper from UC.Berkeley. It is related to Sector Cache. Maybe 
someone will use that model in the future. But why should Fully-associative LRU 
cache be considered separately?  





Regards

Zheng Liang

EECS, Peking University___
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