[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp
Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.67 -> 1.68
---
Log message:
Match MachineFunction::UsedPhysRegs changes.
---
Diffs of the changes: (+1 -2)
X86FloatingPoint.cpp |3 +--
1 files changed, 1 insertion(+), 2 deletions(-)
Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.67
llvm/lib/Target/X86/X86FloatingPoint.cpp:1.68
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.67 Tue Dec 19 16:59:26 2006
+++ llvm/lib/Target/X86/X86FloatingPoint.cppWed Apr 25 17:13:27 2007
@@ -161,12 +161,11 @@
bool FPS::runOnMachineFunction(MachineFunction &MF) {
// We only need to run this pass if there are any FP registers used in this
// function. If it is all integer, there is nothing for us to do!
- const bool *PhysRegsUsed = MF.getUsedPhysregs();
bool FPIsUsed = false;
assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
for (unsigned i = 0; i <= 6; ++i)
-if (PhysRegsUsed[X86::FP0+i]) {
+if (MF.isPhysRegUsed(X86::FP0+i)) {
FPIsUsed = true;
break;
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp
Changes in directory llvm/lib/Target/X86: X86FloatingPoint.cpp updated: 1.65 -> 1.66 --- Log message: Fix a bug introduced by the streams patch. DEBUG code was made unconditional. --- Diffs of the changes: (+1 -1) X86FloatingPoint.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86FloatingPoint.cpp diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.65 llvm/lib/Target/X86/X86FloatingPoint.cpp:1.66 --- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.65 Thu Dec 7 16:21:48 2006 +++ llvm/lib/Target/X86/X86FloatingPoint.cppThu Dec 7 23:41:26 2006 @@ -210,7 +210,7 @@ PrevMI = prior(I); ++NumFP; // Keep track of # of pseudo instrs -DOUT << "\nFPInst:\t"; MI->print(*cerr.stream(), &(MF.getTarget())); +DOUT << "\nFPInst:\t" << *MI; // Get dead variables list now because the MI pointer may be deleted as part // of processing! ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp X86ISelDAGToDAG.cpp X86RegisterInfo.cpp X86Subtarget.cpp
Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.64 -> 1.65
X86ISelDAGToDAG.cpp updated: 1.137 -> 1.138
X86RegisterInfo.cpp updated: 1.183 -> 1.184
X86Subtarget.cpp updated: 1.42 -> 1.43
---
Log message:
What should be the last unnecessary s in the library.
---
Diffs of the changes: (+15 -20)
X86FloatingPoint.cpp | 17 -
X86ISelDAGToDAG.cpp |1 -
X86RegisterInfo.cpp | 10 --
X86Subtarget.cpp |7 +++
4 files changed, 15 insertions(+), 20 deletions(-)
Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.64
llvm/lib/Target/X86/X86FloatingPoint.cpp:1.65
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.64 Wed Dec 6 11:46:32 2006
+++ llvm/lib/Target/X86/X86FloatingPoint.cppThu Dec 7 16:21:48 2006
@@ -44,7 +44,6 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include
-#include
#include
using namespace llvm;
@@ -70,12 +69,12 @@
unsigned StackTop; // The current top of the FP stack.
void dumpStack() const {
- std::cerr << "Stack contents:";
+ cerr << "Stack contents:";
for (unsigned i = 0; i != StackTop; ++i) {
-std::cerr << " FP" << Stack[i];
+cerr << " FP" << Stack[i];
assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
}
- std::cerr << "\n";
+ cerr << "\n";
}
private:
// getSlot - Return the stack slot number a particular register number is
@@ -211,7 +210,7 @@
PrevMI = prior(I);
++NumFP; // Keep track of # of pseudo instrs
-DEBUG(std::cerr << "\nFPInst:\t"; MI->print(std::cerr, &(MF.getTarget(;
+DOUT << "\nFPInst:\t"; MI->print(*cerr.stream(), &(MF.getTarget()));
// Get dead variables list now because the MI pointer may be deleted as
part
// of processing!
@@ -238,7 +237,7 @@
for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
unsigned Reg = DeadRegs[i];
if (Reg >= X86::FP0 && Reg <= X86::FP6) {
-DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
+DOUT << "Register FP#" << Reg-X86::FP0 << " is dead!\n";
freeStackSlotAfter(I, Reg-X86::FP0);
}
}
@@ -247,13 +246,13 @@
DEBUG(
MachineBasicBlock::iterator PrevI(PrevMI);
if (I == PrevI) {
-std::cerr << "Just deleted pseudo instruction\n";
+cerr << "Just deleted pseudo instruction\n";
} else {
MachineBasicBlock::iterator Start = I;
// Rewind to first instruction newly inserted.
while (Start != BB.begin() && prior(Start) != PrevI) --Start;
-std::cerr << "Inserted instructions:\n\t";
-Start->print(std::cerr, &MF.getTarget());
+cerr << "Inserted instructions:\n\t";
+Start->print(*cerr.stream(), &MF.getTarget());
while (++Start != next(I));
}
dumpStack();
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.137
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.138
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.137 Wed Dec 6 11:46:32 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Dec 7 16:21:48 2006
@@ -34,7 +34,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/ADT/Statistic.h"
-#include
#include
#include
using namespace llvm;
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.183
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.184
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.183 Wed Dec 6 19:21:59 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Dec 7 16:21:48 2006
@@ -32,8 +32,6 @@
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/ADT/STLExtras.h"
-#include
-
using namespace llvm;
namespace {
@@ -244,8 +242,8 @@
static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
for (unsigned i = 1; i != NumEntries; ++i)
if (!(Table[i-1] < Table[i])) {
- std::cerr << "Entries out of order " << Table[i-1].from
-<< " " << Table[i].from << "\n";
+ cerr << "Entries out of order " << Table[i-1].from
+ << " " << Table[i].from << "\n";
return false;
}
return true;
@@ -845,8 +843,8 @@
// No fusion
if (PrintFailedFusing)
-std::cerr << "We failed to fuse ("
- << ((i == 1) ? "r" : "s") << "): " << *MI;
+cerr << "We failed to fuse ("
+ << ((i == 1) ? "r" : "s") << "): " << *MI;
return NULL;
}
Index: llvm/lib/Target/X86/X86Subtarget.cpp
diff -u llvm/lib/Target/X86/X86Subtarget.cpp:1.42
llvm/lib/Target/X86/X86Subtarget.cpp:1.43
--- llvm/lib/Target/X86/X86Subtarget.cpp:1.42 Thu Nov 30 16:42:55 2006
+++ llvm/lib/Target/X86/X86Subtarget.cppThu Dec 7 16:21:48 2006
@@ -15,7 +15,6 @@
#include "X86GenSubtarget.inc"
#include "llvm/Module.h"
#inc
[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp
Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.62 -> 1.63
---
Log message:
Fix 2005-05-08-FPStackifierPHI.ll failure.
---
Diffs of the changes: (+7 -26)
X86FloatingPoint.cpp | 33 +++--
1 files changed, 7 insertions(+), 26 deletions(-)
Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.62
llvm/lib/Target/X86/X86FloatingPoint.cpp:1.63
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.62 Thu Nov 30 01:12:03 2006
+++ llvm/lib/Target/X86/X86FloatingPoint.cppFri Dec 1 04:11:51 2006
@@ -62,11 +62,12 @@
MachineFunctionPass::getAnalysisUsage(AU);
}
private:
-LiveVariables *LV;// Live variable info for current function...
-MachineBasicBlock *MBB; // Current basic block
-unsigned Stack[8];// FP Registers in each stack slot...
-unsigned RegMap[8]; // Track which stack slot contains each register
-unsigned StackTop;// The current top of the FP stack.
+const TargetInstrInfo *TII; // Machine instruction info.
+LiveVariables *LV; // Live variable info for current function...
+MachineBasicBlock *MBB; // Current basic block
+unsigned Stack[8]; // FP Registers in each stack slot...
+unsigned RegMap[8]; // Track which stack slot contains each
register
+unsigned StackTop; // The current top of the FP stack.
void dumpStack() const {
std::cerr << "Stack contents:";
@@ -107,9 +108,6 @@
bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
if (!isAtTop(RegNo)) {
-MachineFunction *MF = I->getParent()->getParent();
-const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
-
unsigned STReg = getSTReg(RegNo);
unsigned RegOnTop = getStackEntry(0);
@@ -127,8 +125,6 @@
}
void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
- MachineFunction *MF = I->getParent()->getParent();
- const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
unsigned STReg = getSTReg(RegNo);
pushReg(AsReg); // New register on top of stack
@@ -179,6 +175,7 @@
// Early exit.
if (!FPIsUsed) return false;
+ TII = MF.getTarget().getInstrInfo();
LV = &getAnalysis();
StackTop = 0;
@@ -431,8 +428,6 @@
assert(StackTop > 0 && "Cannot pop empty stack!");
RegMap[Stack[--StackTop]] = ~0; // Update state
- MachineFunction *MF = I->getParent()->getParent();
- const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
// Check to see if there is a popping version of this instruction...
int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode());
if (Opcode != -1) {
@@ -464,8 +459,6 @@
RegMap[TopReg]= OldSlot;
RegMap[FPRegNo] = ~0;
Stack[--StackTop] = ~0;
- MachineFunction *MF = I->getParent()->getParent();
- const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
I = BuildMI(*MBB, ++I, TII->get(X86::FSTPrr)).addReg(STReg);
}
@@ -486,8 +479,6 @@
///
void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
- MachineFunction *MF = MI->getParent()->getParent();
- const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
unsigned DestReg = getFPReg(MI->getOperand(0));
// Change from the pseudo instruction to the concrete instruction.
@@ -528,8 +519,6 @@
// Convert from the pseudo instruction to the concrete instruction.
MI->RemoveOperand(NumOps-1);// Remove explicit ST(0) operand
- MachineFunction *MF = MI->getParent()->getParent();
- const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode(;
if (MI->getOpcode() == X86::FISTP64m ||
@@ -575,8 +564,6 @@
}
// Change from the pseudo instruction to the concrete instruction.
- MachineFunction *MF = I->getParent()->getParent();
- const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
MI->RemoveOperand(1); // Drop the source operand.
MI->RemoveOperand(0); // Drop the destination operand.
MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode(;
@@ -704,8 +691,6 @@
// Replace the old instruction with a new instruction
MBB->remove(I++);
- MachineFunction *MF = MI->getParent()->getParent();
- const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
I = BuildMI(*MBB, I, TII->get(Opcode)).addReg(getSTReg(NotTOS));
// If both operands are killed, pop one off of the stack in addition to
@@ -743,8 +728,6 @@
// anywhere.
moveToTop(Op0, I);
- MachineFunction *MF = I->getParent()->getParent();
- const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
// Change from the pseudo instruction to the concrete instruction.
MI->getOperand(0).setReg(getSTReg(Op1));
MI->RemoveOperand(1);
@@
[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp
Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.61 -> 1.62
---
Log message:
MachineInstr::setOpcode -> MachineInstr::setInstrDescriptor
---
Diffs of the changes: (+33 -31)
X86FloatingPoint.cpp | 64 ++-
1 files changed, 33 insertions(+), 31 deletions(-)
Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.61
llvm/lib/Target/X86/X86FloatingPoint.cpp:1.62
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.61 Mon Nov 27 17:37:22 2006
+++ llvm/lib/Target/X86/X86FloatingPoint.cppThu Nov 30 01:12:03 2006
@@ -108,7 +108,7 @@
void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
if (!isAtTop(RegNo)) {
MachineFunction *MF = I->getParent()->getParent();
-const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
+const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
unsigned STReg = getSTReg(RegNo);
unsigned RegOnTop = getStackEntry(0);
@@ -121,18 +121,18 @@
std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
// Emit an fxch to update the runtime processors version of the state
-BuildMI(*MBB, I, TII.get(X86::FXCH)).addReg(STReg);
+BuildMI(*MBB, I, TII->get(X86::FXCH)).addReg(STReg);
NumFXCH++;
}
}
void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
MachineFunction *MF = I->getParent()->getParent();
- const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
+ const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
unsigned STReg = getSTReg(RegNo);
pushReg(AsReg); // New register on top of stack
- BuildMI(*MBB, I, TII.get(X86::FLDrr)).addReg(STReg);
+ BuildMI(*MBB, I, TII->get(X86::FLDrr)).addReg(STReg);
}
// popStackAfter - Pop the current value off of the top of the FP stack
@@ -200,13 +200,12 @@
/// transforming FP instructions into their stack form.
///
bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
- const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
bool Changed = false;
MBB = &BB;
for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
MachineInstr *MI = I;
-unsigned Flags = TII.get(MI->getOpcode()).TSFlags;
+unsigned Flags = MI->getInstrDescriptor()->TSFlags;
if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
continue; // Efficiently ignore non-fp insts!
@@ -432,17 +431,16 @@
assert(StackTop > 0 && "Cannot pop empty stack!");
RegMap[Stack[--StackTop]] = ~0; // Update state
+ MachineFunction *MF = I->getParent()->getParent();
+ const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
// Check to see if there is a popping version of this instruction...
int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode());
if (Opcode != -1) {
-I->setOpcode(Opcode);
+I->setInstrDescriptor(TII->get(Opcode));
if (Opcode == X86::FUCOMPPr)
I->RemoveOperand(0);
-
} else {// Insert an explicit pop
-MachineFunction *MF = I->getParent()->getParent();
-const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
-I = BuildMI(*MBB, ++I, TII.get(X86::FSTPrr)).addReg(X86::ST0);
+I = BuildMI(*MBB, ++I, TII->get(X86::FSTPrr)).addReg(X86::ST0);
}
}
@@ -467,8 +465,8 @@
RegMap[FPRegNo] = ~0;
Stack[--StackTop] = ~0;
MachineFunction *MF = I->getParent()->getParent();
- const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
- I = BuildMI(*MBB, ++I, TII.get(X86::FSTPrr)).addReg(STReg);
+ const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
+ I = BuildMI(*MBB, ++I, TII->get(X86::FSTPrr)).addReg(STReg);
}
@@ -488,11 +486,13 @@
///
void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
+ MachineFunction *MF = MI->getParent()->getParent();
+ const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
unsigned DestReg = getFPReg(MI->getOperand(0));
// Change from the pseudo instruction to the concrete instruction.
MI->RemoveOperand(0); // Remove the explicit ST(0) operand
- MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
+ MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode(;
// Result gets pushed on the stack.
pushReg(DestReg);
@@ -502,9 +502,7 @@
///
void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
- MachineFunction *MF = MI->getParent()->getParent();
- const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
- unsigned NumOps = TII.getNumOperands(MI->getOpcode());
+ unsigned NumOps = MI->getInstrDescriptor()->numOperands;
assert((NumOps == 5 || NumOps == 1) &&
"Can only handle fst* & ftst instructions!");
@@ -530,7 +528,9 @@
// Convert from the pseudo instruction to the concrete instruction.
MI->RemoveOperand(NumOps-1);/
[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86InstrInfo.cpp X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.60 -> 1.61
X86ISelDAGToDAG.cpp updated: 1.129 -> 1.130
X86ISelLowering.cpp updated: 1.294 -> 1.295
X86InstrInfo.cpp updated: 1.74 -> 1.75
X86RegisterInfo.cpp updated: 1.180 -> 1.181
---
Log message:
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.
---
Diffs of the changes: (+75 -61)
X86FloatingPoint.cpp | 19 ++-
X86ISelDAGToDAG.cpp | 19 ++-
X86ISelLowering.cpp | 22 +-
X86InstrInfo.cpp | 30 +++---
X86RegisterInfo.cpp | 46 +++---
5 files changed, 75 insertions(+), 61 deletions(-)
Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.60
llvm/lib/Target/X86/X86FloatingPoint.cpp:1.61
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.60 Wed Nov 15 14:56:39 2006
+++ llvm/lib/Target/X86/X86FloatingPoint.cppMon Nov 27 17:37:22 2006
@@ -107,6 +107,9 @@
bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
if (!isAtTop(RegNo)) {
+MachineFunction *MF = I->getParent()->getParent();
+const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
+
unsigned STReg = getSTReg(RegNo);
unsigned RegOnTop = getStackEntry(0);
@@ -118,16 +121,18 @@
std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
// Emit an fxch to update the runtime processors version of the state
-BuildMI(*MBB, I, X86::FXCH, 1).addReg(STReg);
+BuildMI(*MBB, I, TII.get(X86::FXCH)).addReg(STReg);
NumFXCH++;
}
}
void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
+ MachineFunction *MF = I->getParent()->getParent();
+ const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
unsigned STReg = getSTReg(RegNo);
pushReg(AsReg); // New register on top of stack
- BuildMI(*MBB, I, X86::FLDrr, 1).addReg(STReg);
+ BuildMI(*MBB, I, TII.get(X86::FLDrr)).addReg(STReg);
}
// popStackAfter - Pop the current value off of the top of the FP stack
@@ -435,7 +440,9 @@
I->RemoveOperand(0);
} else {// Insert an explicit pop
-I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(X86::ST0);
+MachineFunction *MF = I->getParent()->getParent();
+const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
+I = BuildMI(*MBB, ++I, TII.get(X86::FSTPrr)).addReg(X86::ST0);
}
}
@@ -459,7 +466,9 @@
RegMap[TopReg]= OldSlot;
RegMap[FPRegNo] = ~0;
Stack[--StackTop] = ~0;
- I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(STReg);
+ MachineFunction *MF = I->getParent()->getParent();
+ const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
+ I = BuildMI(*MBB, ++I, TII.get(X86::FSTPrr)).addReg(STReg);
}
@@ -697,7 +706,7 @@
// Replace the old instruction with a new instruction
MBB->remove(I++);
- I = BuildMI(*MBB, I, Opcode, 1).addReg(getSTReg(NotTOS));
+ I = BuildMI(*MBB, I, TII.get(Opcode)).addReg(getSTReg(NotTOS));
// If both operands are killed, pop one off of the stack in addition to
// overwriting the other one.
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.129
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.130
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.129 Fri Nov 17 16:10:14 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Nov 27 17:37:22 2006
@@ -525,7 +525,8 @@
// Finally, if we found any FP code, emit the FP_REG_KILL instruction.
if (ContainsFPCode) {
- BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
+ BuildMI(*BB, BB->getFirstTerminator(),
+ TM.getInstrInfo()->get(X86::FP_REG_KILL));
++NumFPKill;
}
}
@@ -535,19 +536,20 @@
/// the main function.
void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
MachineFrameInfo *MFI) {
+ const TargetInstrInfo *TII = TM.getInstrInfo();
if (Subtarget->isTargetCygwin())
-BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("__main");
+BuildMI(BB, TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
// Switch the FPU to 64-bit precision mode for better compatibility and
speed.
int CWFrameIdx = MFI->CreateStackObject(2, 2);
- addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
+ addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
// Set the high part to be 64-bit precision.
- addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
+ addFrameReference(BuildMI(BB, TII->get(X86::MOV8mi)),
CWFrameIdx, 1).addImm(2);
// Reload the modified control word now.
- addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp
Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.59 -> 1.60
---
Log message:
Kill / dead info has been moved to MI's.
---
Diffs of the changes: (+11 -18)
X86FloatingPoint.cpp | 29 +++--
1 files changed, 11 insertions(+), 18 deletions(-)
Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.59
llvm/lib/Target/X86/X86FloatingPoint.cpp:1.60
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.59 Tue Nov 14 13:20:33 2006
+++ llvm/lib/Target/X86/X86FloatingPoint.cppWed Nov 15 14:56:39 2006
@@ -40,6 +40,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/Compiler.h"
#include "llvm/ADT/DepthFirstIterator.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include
@@ -213,20 +214,12 @@
// Get dead variables list now because the MI pointer may be deleted as
part
// of processing!
-LiveVariables::killed_iterator IB, IE;
-tie(IB, IE) = LV->dead_range(MI);
-
-DEBUG(
- const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo();
- LiveVariables::killed_iterator I = LV->killed_begin(MI);
- LiveVariables::killed_iterator E = LV->killed_end(MI);
- if (I != E) {
-std::cerr << "Killed Operands:";
-for (; I != E; ++I)
- std::cerr << " %" << MRI->getName(*I);
-std::cerr << "\n";
- }
-);
+SmallVector DeadRegs;
+for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg() && MO.isDead())
+DeadRegs.push_back(MO.getReg());
+}
switch (Flags & X86II::FPTypeMask) {
case X86II::ZeroArgFP: handleZeroArgFP(I); break;
@@ -241,8 +234,8 @@
// Check to see if any of the values defined by this instruction are dead
// after definition. If so, pop them.
-for (; IB != IE; ++IB) {
- unsigned Reg = *IB;
+for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
+ unsigned Reg = DeadRegs[i];
if (Reg >= X86::FP0 && Reg <= X86::FP6) {
DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
freeStackSlotAfter(I, Reg-X86::FP0);
@@ -762,6 +755,7 @@
unsigned Op0 = getFPReg(MI->getOperand(0));
unsigned Op1 = getFPReg(MI->getOperand(2));
+ bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
// The first operand *must* be on the top of the stack.
moveToTop(Op0, I);
@@ -773,9 +767,8 @@
MI->getOperand(0).setReg(getSTReg(Op1));
MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
-
// If we kill the second operand, make sure to pop it from the stack.
- if (Op0 != Op1 && LV->KillsRegister(MI, X86::FP0+Op1)) {
+ if (Op0 != Op1 && KillsOp1) {
// Get this value off of the register stack.
freeStackSlotAfter(I, Op1);
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp
Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.58 -> 1.59
---
Log message:
Revert. This wasn't meant to be checked in.
---
Diffs of the changes: (+18 -11)
X86FloatingPoint.cpp | 29 ++---
1 files changed, 18 insertions(+), 11 deletions(-)
Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.58
llvm/lib/Target/X86/X86FloatingPoint.cpp:1.59
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.58 Mon Nov 13 17:36:35 2006
+++ llvm/lib/Target/X86/X86FloatingPoint.cppTue Nov 14 13:20:33 2006
@@ -40,7 +40,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/Compiler.h"
#include "llvm/ADT/DepthFirstIterator.h"
-#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include
@@ -214,12 +213,20 @@
// Get dead variables list now because the MI pointer may be deleted as
part
// of processing!
-SmallVector DeadRegs;
-for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDead())
-DeadRegs.push_back(MO.getReg());
-}
+LiveVariables::killed_iterator IB, IE;
+tie(IB, IE) = LV->dead_range(MI);
+
+DEBUG(
+ const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo();
+ LiveVariables::killed_iterator I = LV->killed_begin(MI);
+ LiveVariables::killed_iterator E = LV->killed_end(MI);
+ if (I != E) {
+std::cerr << "Killed Operands:";
+for (; I != E; ++I)
+ std::cerr << " %" << MRI->getName(*I);
+std::cerr << "\n";
+ }
+);
switch (Flags & X86II::FPTypeMask) {
case X86II::ZeroArgFP: handleZeroArgFP(I); break;
@@ -234,8 +241,8 @@
// Check to see if any of the values defined by this instruction are dead
// after definition. If so, pop them.
-for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
- unsigned Reg = DeadRegs[i];
+for (; IB != IE; ++IB) {
+ unsigned Reg = *IB;
if (Reg >= X86::FP0 && Reg <= X86::FP6) {
DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
freeStackSlotAfter(I, Reg-X86::FP0);
@@ -755,7 +762,6 @@
unsigned Op0 = getFPReg(MI->getOperand(0));
unsigned Op1 = getFPReg(MI->getOperand(2));
- bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
// The first operand *must* be on the top of the stack.
moveToTop(Op0, I);
@@ -767,8 +773,9 @@
MI->getOperand(0).setReg(getSTReg(Op1));
MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
+
// If we kill the second operand, make sure to pop it from the stack.
- if (Op0 != Op1 && KillsOp1) {
+ if (Op0 != Op1 && LV->KillsRegister(MI, X86::FP0+Op1)) {
// Get this value off of the register stack.
freeStackSlotAfter(I, Op1);
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86InstrInfo.cpp X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.57 -> 1.58
X86ISelDAGToDAG.cpp updated: 1.126 -> 1.127
X86ISelLowering.cpp updated: 1.291 -> 1.292
X86InstrInfo.cpp updated: 1.71 -> 1.72
X86RegisterInfo.cpp updated: 1.176 -> 1.177
---
Log message:
Matches MachineInstr changes.
---
Diffs of the changes: (+47 -56)
X86FloatingPoint.cpp | 29 +++--
X86ISelDAGToDAG.cpp |9 +++--
X86ISelLowering.cpp |2 +-
X86InstrInfo.cpp | 22 +++---
X86RegisterInfo.cpp | 41 +
5 files changed, 47 insertions(+), 56 deletions(-)
Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.57
llvm/lib/Target/X86/X86FloatingPoint.cpp:1.58
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.57 Sat Nov 11 04:21:44 2006
+++ llvm/lib/Target/X86/X86FloatingPoint.cppMon Nov 13 17:36:35 2006
@@ -40,6 +40,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/Compiler.h"
#include "llvm/ADT/DepthFirstIterator.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include
@@ -213,20 +214,12 @@
// Get dead variables list now because the MI pointer may be deleted as
part
// of processing!
-LiveVariables::killed_iterator IB, IE;
-tie(IB, IE) = LV->dead_range(MI);
-
-DEBUG(
- const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo();
- LiveVariables::killed_iterator I = LV->killed_begin(MI);
- LiveVariables::killed_iterator E = LV->killed_end(MI);
- if (I != E) {
-std::cerr << "Killed Operands:";
-for (; I != E; ++I)
- std::cerr << " %" << MRI->getName(*I);
-std::cerr << "\n";
- }
-);
+SmallVector DeadRegs;
+for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg() && MO.isDead())
+DeadRegs.push_back(MO.getReg());
+}
switch (Flags & X86II::FPTypeMask) {
case X86II::ZeroArgFP: handleZeroArgFP(I); break;
@@ -241,8 +234,8 @@
// Check to see if any of the values defined by this instruction are dead
// after definition. If so, pop them.
-for (; IB != IE; ++IB) {
- unsigned Reg = *IB;
+for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
+ unsigned Reg = DeadRegs[i];
if (Reg >= X86::FP0 && Reg <= X86::FP6) {
DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
freeStackSlotAfter(I, Reg-X86::FP0);
@@ -762,6 +755,7 @@
unsigned Op0 = getFPReg(MI->getOperand(0));
unsigned Op1 = getFPReg(MI->getOperand(2));
+ bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
// The first operand *must* be on the top of the stack.
moveToTop(Op0, I);
@@ -773,9 +767,8 @@
MI->getOperand(0).setReg(getSTReg(Op1));
MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
-
// If we kill the second operand, make sure to pop it from the stack.
- if (Op0 != Op1 && LV->KillsRegister(MI, X86::FP0+Op1)) {
+ if (Op0 != Op1 && KillsOp1) {
// Get this value off of the register stack.
freeStackSlotAfter(I, Op1);
}
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.126
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.127
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.126 Sat Nov 11 04:21:44 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Nov 13 17:36:35 2006
@@ -525,8 +525,7 @@
// Finally, if we found any FP code, emit the FP_REG_KILL instruction.
if (ContainsFPCode) {
- BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0).
-addImplicitDefsUses();
+ BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
++NumFPKill;
}
}
@@ -537,8 +536,7 @@
void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
MachineFrameInfo *MFI) {
if (Subtarget->isTargetCygwin())
-BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("__main").
- addImplicitDefsUses();
+BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("__main");
// Switch the FPU to 64-bit precision mode for better compatibility and
speed.
int CWFrameIdx = MFI->CreateStackObject(2, 2);
@@ -949,8 +947,7 @@
// type of register here.
GlobalBaseReg = RegMap->createVirtualRegister(X86::GR32RegisterClass);
BuildMI(FirstMBB, MBBI, X86::MovePCtoStack, 0);
-BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg).
- addImplicitDefsUses();
+BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg);
}
return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).Val;
}
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.291
llvm/lib/Target/X86/X86ISelLowering.cpp:1.292
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.291 Sat Nov 11 04
[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp X86ISelDAGToDAG.cpp X86ISelLowering.cpp
Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.56 -> 1.57
X86ISelDAGToDAG.cpp updated: 1.125 -> 1.126
X86ISelLowering.cpp updated: 1.290 -> 1.291
---
Log message:
Add implicit use / def operands to created MI's.
---
Diffs of the changes: (+8 -10)
X86FloatingPoint.cpp |2 +-
X86ISelDAGToDAG.cpp | 14 ++
X86ISelLowering.cpp |2 +-
3 files changed, 8 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.56
llvm/lib/Target/X86/X86FloatingPoint.cpp:1.57
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.56 Thu Nov 9 19:28:43 2006
+++ llvm/lib/Target/X86/X86FloatingPoint.cppSat Nov 11 04:21:44 2006
@@ -232,7 +232,7 @@
case X86II::ZeroArgFP: handleZeroArgFP(I); break;
case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
-case X86II::TwoArgFP: handleTwoArgFP(I); break;
+case X86II::TwoArgFP: handleTwoArgFP(I); break;
case X86II::CompareFP: handleCompareFP(I); break;
case X86II::CondMovFP: handleCondMovFP(I); break;
case X86II::SpecialFP: handleSpecialFP(I); break;
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.125
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.126
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.125 Sat Nov 11 01:19:36 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Sat Nov 11 04:21:44 2006
@@ -525,12 +525,8 @@
// Finally, if we found any FP code, emit the FP_REG_KILL instruction.
if (ContainsFPCode) {
- const TargetInstrDescriptor &II=
TM.getInstrInfo()->get(X86::FP_REG_KILL);
- MachineInstrBuilder MIB =
-BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
- for (const unsigned *ImplicitDefs = II.ImplicitDefs;
- *ImplicitDefs; ++ImplicitDefs)
-MIB = MIB.addReg(*ImplicitDefs, true, true);
+ BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0).
+addImplicitDefsUses();
++NumFPKill;
}
}
@@ -541,7 +537,8 @@
void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
MachineFrameInfo *MFI) {
if (Subtarget->isTargetCygwin())
-BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("__main");
+BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("__main").
+ addImplicitDefsUses();
// Switch the FPU to 64-bit precision mode for better compatibility and
speed.
int CWFrameIdx = MFI->CreateStackObject(2, 2);
@@ -952,7 +949,8 @@
// type of register here.
GlobalBaseReg = RegMap->createVirtualRegister(X86::GR32RegisterClass);
BuildMI(FirstMBB, MBBI, X86::MovePCtoStack, 0);
-BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg);
+BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg).
+ addImplicitDefsUses();
}
return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).Val;
}
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.290
llvm/lib/Target/X86/X86ISelLowering.cpp:1.291
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.290 Fri Nov 10 15:43:37 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Sat Nov 11 04:21:44 2006
@@ -5076,7 +5076,7 @@
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
unsigned Opc =
X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
-BuildMI(BB, Opc, 1).addMBB(sinkMBB);
+BuildMI(BB, Opc, 1).addMBB(sinkMBB).addImplicitDefsUses();
MachineFunction *F = BB->getParent();
F->getBasicBlockList().insert(It, copy0MBB);
F->getBasicBlockList().insert(It, sinkMBB);
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp X86ISelLowering.cpp X86IntelAsmPrinter.cpp
Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.54 -> 1.55
X86ISelLowering.cpp updated: 1.286 -> 1.287
X86IntelAsmPrinter.cpp updated: 1.63 -> 1.64
---
Log message:
For PR786: http://llvm.org/PR786 :
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.
---
Diffs of the changes: (+3 -9)
X86FloatingPoint.cpp |1 -
X86ISelLowering.cpp| 10 +++---
X86IntelAsmPrinter.cpp |1 -
3 files changed, 3 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.54
llvm/lib/Target/X86/X86FloatingPoint.cpp:1.55
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.54 Tue Sep 5 15:27:32 2006
+++ llvm/lib/Target/X86/X86FloatingPoint.cppThu Nov 2 14:25:49 2006
@@ -106,7 +106,6 @@
bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
if (!isAtTop(RegNo)) {
-unsigned Slot = getSlot(RegNo);
unsigned STReg = getSTReg(RegNo);
unsigned RegOnTop = getStackEntry(0);
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.286
llvm/lib/Target/X86/X86ISelLowering.cpp:1.287
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.286 Tue Oct 31 14:13:11 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Nov 2 14:25:49 2006
@@ -532,7 +532,6 @@
SDOperand X86TargetLowering::LowerallTo(SDOperand Op, SelectionDAG &DAG) {
SDOperand Chain = Op.getOperand(0);
unsigned CallingConv= cast(Op.getOperand(1))->getValue();
- bool isVarArg = cast(Op.getOperand(2))->getValue() !=
0;
bool isTailCall = cast(Op.getOperand(3))->getValue() !=
0;
SDOperand Callee= Op.getOperand(4);
MVT::ValueType RetVT= Op.Val->getValueType(0);
@@ -1031,7 +1030,6 @@
SDOperand
X86TargetLowering::LowerX86_64allTo(SDOperand Op, SelectionDAG &DAG) {
SDOperand Chain = Op.getOperand(0);
- unsigned CallingConv= cast(Op.getOperand(1))->getValue();
bool isVarArg = cast(Op.getOperand(2))->getValue() !=
0;
bool isTailCall = cast(Op.getOperand(3))->getValue() !=
0;
SDOperand Callee= Op.getOperand(4);
@@ -1528,8 +1526,6 @@
SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
bool isFastCall) {
SDOperand Chain = Op.getOperand(0);
- unsigned CallingConv= cast(Op.getOperand(1))->getValue();
- bool isVarArg = cast(Op.getOperand(2))->getValue() !=
0;
bool isTailCall = cast(Op.getOperand(3))->getValue() !=
0;
SDOperand Callee= Op.getOperand(4);
MVT::ValueType RetVT= Op.Val->getValueType(0);
@@ -1549,11 +1545,13 @@
{ X86::AX, X86::DX },
{ X86::EAX, X86::EDX }
};
+#if 0
static const unsigned FastCallGPRArgRegs[][2] = {
{ X86::CL, X86::DL },
{ X86::CX, X86::DX },
{ X86::ECX, X86::EDX }
};
+#endif
static const unsigned XMMArgRegs[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
};
@@ -1906,7 +1904,6 @@
SDOperand X86TargetLowering::LowerStdCallCCCallTo(SDOperand Op,
SelectionDAG &DAG) {
SDOperand Chain = Op.getOperand(0);
- unsigned CallingConv= cast(Op.getOperand(1))->getValue();
bool isVarArg = cast(Op.getOperand(2))->getValue() !=
0;
bool isTailCall = cast(Op.getOperand(3))->getValue() !=
0;
SDOperand Callee= Op.getOperand(4);
@@ -2841,7 +2838,7 @@
unsigned i = 0;
for (; i != NumElems; ++i) {
SDOperand Elt = N->getOperand(i);
-if (ConstantSDNode *EltV = dyn_cast(Elt)) {
+if (isa(Elt)) {
ElementBase = Elt;
break;
}
@@ -5431,7 +5428,6 @@
SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
- TargetMachine &TM = getTargetMachine();
SelectionDAG &DAG = DCI.DAG;
switch (N->getOpcode()) {
default: break;
Index: llvm/lib/Target/X86/X86IntelAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.63
llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.64
--- llvm/lib/Target/X86/X86IntelAsmPrinter.cpp:1.63 Tue Oct 31 02:31:24 2006
+++ llvm/lib/Target/X86/X86IntelAsmPrinter.cpp Thu Nov 2 14:25:49 2006
@@ -386,7 +386,6 @@
std::string name = Mang->getValueName(I);
Constant *C = I->getInitializer();
-unsigned Size = TD->getTypeSize(C->getType());
unsigned Align = TD->getPreferredAlignmentLog(I);
bool bCustomSegment = false;
___
llvm-commits mailing list
llvm
[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp
Changes in directory llvm/lib/Target/X86: X86FloatingPoint.cpp updated: 1.53 -> 1.54 --- Log message: Bugfix to work with the two-addr changes that have been made in the tree recently --- Diffs of the changes: (+2 -1) X86FloatingPoint.cpp |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/Target/X86/X86FloatingPoint.cpp diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.53 llvm/lib/Target/X86/X86FloatingPoint.cpp:1.54 --- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.53 Sun Aug 27 07:54:01 2006 +++ llvm/lib/Target/X86/X86FloatingPoint.cppTue Sep 5 15:27:32 2006 @@ -752,7 +752,7 @@ MachineInstr *MI = I; unsigned Op0 = getFPReg(MI->getOperand(0)); - unsigned Op1 = getFPReg(MI->getOperand(1)); + unsigned Op1 = getFPReg(MI->getOperand(2)); // The first operand *must* be on the top of the stack. moveToTop(Op0, I); @@ -760,6 +760,7 @@ // Change the second operand to the stack register that the operand is in. // Change from the pseudo instruction to the concrete instruction. MI->RemoveOperand(0); + MI->RemoveOperand(1); MI->getOperand(0).setReg(getSTReg(Op1)); MI->setOpcode(getConcreteOpcode(MI->getOpcode())); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp
Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.51 -> 1.52
---
Log message:
Do once flag never set to true.
---
Diffs of the changes: (+3 -1)
X86FloatingPoint.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.51
llvm/lib/Target/X86/X86FloatingPoint.cpp:1.52
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.51 Wed Jun 28 18:27:49 2006
+++ llvm/lib/Target/X86/X86FloatingPoint.cppWed Jul 19 14:33:08 2006
@@ -312,9 +312,11 @@
#else
#define ASSERT_SORTED(TABLE) \
{ static bool TABLE##Checked = false; \
-if (!TABLE##Checked) \
+if (!TABLE##Checked) {\
assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \
"All lookup tables must be sorted for efficient access!"); \
+ TABLE##Checked = true; \
+} \
}
#endif
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.49 -> 1.50
X86InstrInfo.td updated: 1.238 -> 1.239
---
Log message:
Added fisttp for fp to int conversion.
---
Diffs of the changes: (+29 -3)
X86FloatingPoint.cpp | 17 ++---
X86InstrInfo.td | 15 +++
2 files changed, 29 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.49
llvm/lib/Target/X86/X86FloatingPoint.cpp:1.50
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.49 Thu Jan 26 14:41:32 2006
+++ llvm/lib/Target/X86/X86FloatingPoint.cppFri Feb 17 20:36:28 2006
@@ -357,6 +357,9 @@
{ X86::FpIST16m , X86::FIST16m },
{ X86::FpIST32m , X86::FIST32m },
{ X86::FpIST64m , X86::FISTP64m },
+ { X86::FpISTT16m , X86::FISTTP16m},
+ { X86::FpISTT32m , X86::FISTTP32m},
+ { X86::FpISTT64m , X86::FISTTP64m},
{ X86::FpISUB16m , X86::FISUB16m },
{ X86::FpISUB32m , X86::FISUB32m },
{ X86::FpISUBR16m, X86::FISUBR16m},
@@ -502,12 +505,17 @@
unsigned Reg = getFPReg(MI->getOperand(MI->getNumOperands()-1));
bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg);
- // FISTP64r is strange because there isn't a non-popping versions.
+ // FISTP64m is strange because there isn't a non-popping versions.
// If we have one _and_ we don't want to pop the operand, duplicate the value
// on the stack instead of moving it. This ensure that popping the value is
// always ok.
+ // Ditto FISTTP16m, FISTTP32m, FISTTP64m.
//
- if (MI->getOpcode() == X86::FpIST64m && !KillsSrc) {
+ if (!KillsSrc &&
+ (MI->getOpcode() == X86::FpIST64m ||
+ MI->getOpcode() == X86::FpISTT16m ||
+ MI->getOpcode() == X86::FpISTT32m ||
+ MI->getOpcode() == X86::FpISTT64m)) {
duplicateToTop(Reg, 7 /*temp register*/, I);
} else {
moveToTop(Reg, I);// Move to the top of the stack...
@@ -517,7 +525,10 @@
MI->RemoveOperand(MI->getNumOperands()-1);// Remove explicit ST(0)
operand
MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
- if (MI->getOpcode() == X86::FISTP64m) {
+ if (MI->getOpcode() == X86::FISTP64m ||
+ MI->getOpcode() == X86::FISTTP16m ||
+ MI->getOpcode() == X86::FISTTP32m ||
+ MI->getOpcode() == X86::FISTTP64m) {
assert(StackTop > 0 && "Stack empty??");
--StackTop;
} else if (KillsSrc) { // Last use of operand?
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.238
llvm/lib/Target/X86/X86InstrInfo.td:1.239
--- llvm/lib/Target/X86/X86InstrInfo.td:1.238 Fri Feb 17 18:15:05 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Fri Feb 17 20:36:28 2006
@@ -2957,6 +2957,21 @@
def FISTP32m : FPI<0xDB, MRM3m, (ops i32mem:$dst), "fistp{l} $dst">;
def FISTP64m : FPI<0xDF, MRM7m, (ops i64mem:$dst), "fistp{ll} $dst">;
+// FISTTP requires SSE3 even though it's a FPStack op.
+def FpISTT16m : FpI_<(ops i16mem:$op, RFP:$src), OneArgFP,
+[(X86fp_to_i16mem RFP:$src, addr:$op)]>,
+Requires<[HasSSE3]>;
+def FpISTT32m : FpI_<(ops i32mem:$op, RFP:$src), OneArgFP,
+[(X86fp_to_i32mem RFP:$src, addr:$op)]>,
+Requires<[HasSSE3]>;
+def FpISTT64m : FpI_<(ops i64mem:$op, RFP:$src), OneArgFP,
+[(X86fp_to_i64mem RFP:$src, addr:$op)]>,
+Requires<[HasSSE3]>;
+
+def FISTTP16m : FPI<0xDF, MRM1m, (ops i16mem:$dst), "fisttp{s} $dst">;
+def FISTTP32m : FPI<0xDB, MRM1m, (ops i32mem:$dst), "fisttp{l} $dst">;
+def FISTTP64m : FPI<0xDD, MRM1m, (ops i64mem:$dst), "fisttp{ll} $dst">;
+
// FP Stack manipulation instructions.
def FLDrr : FPI<0xC0, AddRegFrm, (ops RST:$op), "fld $op">, D9;
def FSTrr : FPI<0xD0, AddRegFrm, (ops RST:$op), "fst $op">, DD;
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp
Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.48 -> 1.49
---
Log message:
Improve compatibility with VC2005, patch by Morten Ofstad!
---
Diffs of the changes: (+6 -1)
X86FloatingPoint.cpp |7 ++-
1 files changed, 6 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.48
llvm/lib/Target/X86/X86FloatingPoint.cpp:1.49
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.48 Sun Jan 22 17:37:17 2006
+++ llvm/lib/Target/X86/X86FloatingPoint.cppThu Jan 26 14:41:32 2006
@@ -281,7 +281,12 @@
unsigned from;
unsigned to;
bool operator<(const TableEntry &TE) const { return from < TE.from; }
-bool operator<(unsigned V) const { return from < V; }
+friend bool operator<(const TableEntry &TE, unsigned V) {
+ return TE.from < V;
+}
+friend bool operator<(unsigned V, const TableEntry &TE) {
+ return V < TE.from;
+}
};
}
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp X86ISelPattern.cpp X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.46 -> 1.47
X86ISelPattern.cpp updated: 1.198 -> 1.199
X86InstrInfo.td updated: 1.215 -> 1.216
---
Log message:
Rename fcmovae to fcmovnb and fcmova to fcmovnbe (following Intel manual).
Some assemblers can't recognize the aliases.
---
Diffs of the changes: (+9 -9)
X86FloatingPoint.cpp |4 ++--
X86ISelPattern.cpp |2 +-
X86InstrInfo.td | 12 ++--
3 files changed, 9 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.46
llvm/lib/Target/X86/X86FloatingPoint.cpp:1.47
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.46 Tue Jan 10 16:22:02 2006
+++ llvm/lib/Target/X86/X86FloatingPoint.cppFri Jan 20 20:55:41 2006
@@ -324,11 +324,11 @@
{ X86::FpADD32m , X86::FADD32m },
{ X86::FpADD64m , X86::FADD64m },
{ X86::FpCHS , X86::FCHS },
- { X86::FpCMOVA , X86::FCMOVA },
- { X86::FpCMOVAE , X86::FCMOVAE },
{ X86::FpCMOVB , X86::FCMOVB },
{ X86::FpCMOVBE , X86::FCMOVBE },
{ X86::FpCMOVE , X86::FCMOVE },
+ { X86::FpCMOVNB , X86::FCMOVNB },
+ { X86::FpCMOVNBE , X86::FCMOVNBE },
{ X86::FpCMOVNE , X86::FCMOVNE },
{ X86::FpCMOVNP , X86::FCMOVNP },
{ X86::FpCMOVP , X86::FCMOVP },
Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.198
llvm/lib/Target/X86/X86ISelPattern.cpp:1.199
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.198Sun Jan 15 03:00:21 2006
+++ llvm/lib/Target/X86/X86ISelPattern.cpp Fri Jan 20 20:55:41 2006
@@ -758,7 +758,7 @@
static const unsigned CMOVTABFP[] = {
X86::FpCMOVE, X86::FpCMOVNE, /*missing*/0, /*missing*/0,
/*missing*/0, /*missing*/ 0, X86::FpCMOVB, X86::FpCMOVBE,
-X86::FpCMOVA, X86::FpCMOVAE, X86::FpCMOVP, X86::FpCMOVNP
+X86::FpCMOVNBE,X86::FpCMOVNB, X86::FpCMOVP, X86::FpCMOVNP
};
static const int SSE_CMOVTAB[] = {
/*CMPEQ*/ 0, /*CMPNEQ*/ 4, /*missing*/ 0, /*missing*/ 0,
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.215
llvm/lib/Target/X86/X86InstrInfo.td:1.216
--- llvm/lib/Target/X86/X86InstrInfo.td:1.215 Thu Jan 19 19:13:30 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Fri Jan 20 20:55:41 2006
@@ -2862,10 +2862,10 @@
def FpCMOVP : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
[(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
X86_COND_P, STATUS))]>;
- def FpCMOVAE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
+ def FpCMOVNB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
[(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
X86_COND_AE, STATUS))]>;
- def FpCMOVA : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
+ def FpCMOVNBE: FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
[(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
X86_COND_A, STATUS))]>;
def FpCMOVNE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
@@ -2884,10 +2884,10 @@
"fcmove {$op, %ST(0)|%ST(0), $op}">, DA;
def FCMOVP : FPI<0xD8, AddRegFrm, (ops RST:$op),
"fcmovu {$op, %ST(0)|%ST(0), $op}">, DA;
-def FCMOVAE : FPI<0xC0, AddRegFrm, (ops RST:$op),
- "fcmovae {$op, %ST(0)|%ST(0), $op}">, DB;
-def FCMOVA : FPI<0xD0, AddRegFrm, (ops RST:$op),
- "fcmova {$op, %ST(0)|%ST(0), $op}">, DB;
+def FCMOVNB : FPI<0xC0, AddRegFrm, (ops RST:$op),
+ "fcmovnb {$op, %ST(0)|%ST(0), $op}">, DB;
+def FCMOVNBE : FPI<0xD0, AddRegFrm, (ops RST:$op),
+ "fcmovnbe {$op, %ST(0)|%ST(0), $op}">, DB;
def FCMOVNE : FPI<0xC8, AddRegFrm, (ops RST:$op),
"fcmovne {$op, %ST(0)|%ST(0), $op}">, DB;
def FCMOVNP : FPI<0xD8, AddRegFrm, (ops RST:$op),
___
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp X86InstrInfo.td
Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.45 -> 1.46
X86InstrInfo.td updated: 1.193 -> 1.194
---
Log message:
* fp to sint patterns.
* fiadd, fisub, etc.
---
Diffs of the changes: (+119 -56)
X86FloatingPoint.cpp | 92 ---
X86InstrInfo.td | 83 +-
2 files changed, 119 insertions(+), 56 deletions(-)
Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.45
llvm/lib/Target/X86/X86FloatingPoint.cpp:1.46
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.45 Wed Dec 21 01:47:04 2005
+++ llvm/lib/Target/X86/X86FloatingPoint.cppTue Jan 10 16:22:02 2006
@@ -320,46 +320,58 @@
// concrete X86 instruction which uses the register stack.
//
static const TableEntry OpcodeTable[] = {
- { X86::FpABS, X86::FABS },
- { X86::FpADD32m , X86::FADD32m },
- { X86::FpADD64m , X86::FADD64m },
- { X86::FpCHS, X86::FCHS },
- { X86::FpCMOVA , X86::FCMOVA },
- { X86::FpCMOVAE , X86::FCMOVAE },
- { X86::FpCMOVB , X86::FCMOVB },
- { X86::FpCMOVBE , X86::FCMOVBE },
- { X86::FpCMOVE , X86::FCMOVE },
- { X86::FpCMOVNE , X86::FCMOVNE },
- { X86::FpCMOVNP , X86::FCMOVNP },
- { X86::FpCMOVP , X86::FCMOVP },
- { X86::FpCOS, X86::FCOS },
- { X86::FpDIV32m , X86::FDIV32m },
- { X86::FpDIV64m , X86::FDIV64m },
- { X86::FpDIVR32m, X86::FDIVR32m },
- { X86::FpDIVR64m, X86::FDIVR64m },
- { X86::FpILD16m , X86::FILD16m },
- { X86::FpILD32m , X86::FILD32m },
- { X86::FpILD64m , X86::FILD64m },
- { X86::FpIST16m , X86::FIST16m },
- { X86::FpIST32m , X86::FIST32m },
- { X86::FpIST64m , X86::FISTP64m },
- { X86::FpLD0, X86::FLD0 },
- { X86::FpLD1, X86::FLD1 },
- { X86::FpLD32m , X86::FLD32m },
- { X86::FpLD64m , X86::FLD64m },
- { X86::FpMUL32m , X86::FMUL32m },
- { X86::FpMUL64m , X86::FMUL64m },
- { X86::FpSIN, X86::FSIN },
- { X86::FpSQRT , X86::FSQRT},
- { X86::FpST32m , X86::FST32m },
- { X86::FpST64m , X86::FST64m },
- { X86::FpSUB32m , X86::FSUB32m },
- { X86::FpSUB64m , X86::FSUB64m },
- { X86::FpSUBR32m, X86::FSUBR32m },
- { X86::FpSUBR64m, X86::FSUBR64m },
- { X86::FpTST, X86::FTST },
- { X86::FpUCOMIr , X86::FUCOMIr },
- { X86::FpUCOMr , X86::FUCOMr },
+ { X86::FpABS , X86::FABS },
+ { X86::FpADD32m , X86::FADD32m },
+ { X86::FpADD64m , X86::FADD64m },
+ { X86::FpCHS , X86::FCHS },
+ { X86::FpCMOVA , X86::FCMOVA },
+ { X86::FpCMOVAE , X86::FCMOVAE },
+ { X86::FpCMOVB , X86::FCMOVB },
+ { X86::FpCMOVBE , X86::FCMOVBE },
+ { X86::FpCMOVE , X86::FCMOVE },
+ { X86::FpCMOVNE , X86::FCMOVNE },
+ { X86::FpCMOVNP , X86::FCMOVNP },
+ { X86::FpCMOVP , X86::FCMOVP },
+ { X86::FpCOS , X86::FCOS },
+ { X86::FpDIV32m , X86::FDIV32m },
+ { X86::FpDIV64m , X86::FDIV64m },
+ { X86::FpDIVR32m , X86::FDIVR32m },
+ { X86::FpDIVR64m , X86::FDIVR64m },
+ { X86::FpIADD16m , X86::FIADD16m },
+ { X86::FpIADD32m , X86::FIADD32m },
+ { X86::FpIDIV16m , X86::FIDIV16m },
+ { X86::FpIDIV32m , X86::FIDIV32m },
+ { X86::FpIDIVR16m, X86::FIDIVR16m},
+ { X86::FpIDIVR32m, X86::FIDIVR32m},
+ { X86::FpILD16m , X86::FILD16m },
+ { X86::FpILD32m , X86::FILD32m },
+ { X86::FpILD64m , X86::FILD64m },
+ { X86::FpIMUL16m , X86::FIMUL16m },
+ { X86::FpIMUL32m , X86::FIMUL32m },
+ { X86::FpIST16m , X86::FIST16m },
+ { X86::FpIST32m , X86::FIST32m },
+ { X86::FpIST64m , X86::FISTP64m },
+ { X86::FpISUB16m , X86::FISUB16m },
+ { X86::FpISUB32m , X86::FISUB32m },
+ { X86::FpISUBR16m, X86::FISUBR16m},
+ { X86::FpISUBR32m, X86::FISUBR32m},
+ { X86::FpLD0 , X86::FLD0 },
+ { X86::FpLD1 , X86::FLD1 },
+ { X86::FpLD32m , X86::FLD32m },
+ { X86::FpLD64m , X86::FLD64m },
+ { X86::FpMUL32m , X86::FMUL32m },
+ { X86::FpMUL64m , X86::FMUL64m },
+ { X86::FpSIN , X86::FSIN },
+ { X86::FpSQRT, X86::FSQRT},
+ { X86::FpST32m , X86::FST32m },
+ { X86::FpST64m , X86::FST64m },
+ { X86::FpSUB32m , X86::FSUB32m },
+ { X86::FpSUB64m , X86::FSUB64m },
+ { X86::FpSUBR32m , X86::FSUBR32m },
+ { X86::FpSUBR64m , X86::FSUBR64m },
+ { X86::FpTST , X86::FTST },
+ { X86::FpUCOMIr , X86::FUCOMIr },
+ { X86::FpUCOMr , X86::FUCOMr },
};
static unsigned getConcreteOpcode(unsigned Opcode) {
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.193
llvm/lib/Target/X86/X86InstrInfo.td:1.194
--- llvm/lib/Target/X86/X86InstrInfo.td:1.193 Tue Jan 10 14:26:56 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Tue Jan 10 16:22:02 2006
@@ -50,6 +50,7 @@
SDTCisPtrTy<1>, SDTCisVT<2,
OtherVT>]>;
def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
SDTCisPtrTy<1>, SDTCisVT<2,
OtherVT>]>;
+
[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp X86ISelPattern.cpp X86InstrInfo.td X86RegisterInfo.cpp
Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.44 -> 1.45
X86ISelPattern.cpp updated: 1.189 -> 1.190
X86InstrInfo.td updated: 1.177 -> 1.178
X86RegisterInfo.cpp updated: 1.112 -> 1.113
---
Log message:
Rewrite FP stackifier support in the X86InstrInfo.td file, splitting patterns
that were overloaded to work before and after the stackifier runs. With the
new clean world, it is possible to write patterns for these instructions: woo!
This also adds a few simple patterns here and there, though there are a lot
still missing. These should be easy to add though. :)
See the comments under "Floating Point Stack Support" for more details on
the new world order.
This patch as absolutely no effect on the generated code, woo!
---
Diffs of the changes: (+354 -364)
X86FloatingPoint.cpp | 83 +++
X86ISelPattern.cpp | 76 +++
X86InstrInfo.td | 552 +--
X86RegisterInfo.cpp |7
4 files changed, 354 insertions(+), 364 deletions(-)
Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.44
llvm/lib/Target/X86/X86FloatingPoint.cpp:1.45
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.44 Tue Aug 23 18:41:14 2005
+++ llvm/lib/Target/X86/X86FloatingPoint.cppWed Dec 21 01:47:04 2005
@@ -311,6 +311,63 @@
}
#endif
+//===--===//
+// Register File -> Register Stack Mapping Methods
+//===--===//
+
+// OpcodeTable - Sorted map of register instructions to their stack version.
+// The first element is an register file pseudo instruction, the second is the
+// concrete X86 instruction which uses the register stack.
+//
+static const TableEntry OpcodeTable[] = {
+ { X86::FpABS, X86::FABS },
+ { X86::FpADD32m , X86::FADD32m },
+ { X86::FpADD64m , X86::FADD64m },
+ { X86::FpCHS, X86::FCHS },
+ { X86::FpCMOVA , X86::FCMOVA },
+ { X86::FpCMOVAE , X86::FCMOVAE },
+ { X86::FpCMOVB , X86::FCMOVB },
+ { X86::FpCMOVBE , X86::FCMOVBE },
+ { X86::FpCMOVE , X86::FCMOVE },
+ { X86::FpCMOVNE , X86::FCMOVNE },
+ { X86::FpCMOVNP , X86::FCMOVNP },
+ { X86::FpCMOVP , X86::FCMOVP },
+ { X86::FpCOS, X86::FCOS },
+ { X86::FpDIV32m , X86::FDIV32m },
+ { X86::FpDIV64m , X86::FDIV64m },
+ { X86::FpDIVR32m, X86::FDIVR32m },
+ { X86::FpDIVR64m, X86::FDIVR64m },
+ { X86::FpILD16m , X86::FILD16m },
+ { X86::FpILD32m , X86::FILD32m },
+ { X86::FpILD64m , X86::FILD64m },
+ { X86::FpIST16m , X86::FIST16m },
+ { X86::FpIST32m , X86::FIST32m },
+ { X86::FpIST64m , X86::FISTP64m },
+ { X86::FpLD0, X86::FLD0 },
+ { X86::FpLD1, X86::FLD1 },
+ { X86::FpLD32m , X86::FLD32m },
+ { X86::FpLD64m , X86::FLD64m },
+ { X86::FpMUL32m , X86::FMUL32m },
+ { X86::FpMUL64m , X86::FMUL64m },
+ { X86::FpSIN, X86::FSIN },
+ { X86::FpSQRT , X86::FSQRT},
+ { X86::FpST32m , X86::FST32m },
+ { X86::FpST64m , X86::FST64m },
+ { X86::FpSUB32m , X86::FSUB32m },
+ { X86::FpSUB64m , X86::FSUB64m },
+ { X86::FpSUBR32m, X86::FSUBR32m },
+ { X86::FpSUBR64m, X86::FSUBR64m },
+ { X86::FpTST, X86::FTST },
+ { X86::FpUCOMIr , X86::FUCOMIr },
+ { X86::FpUCOMr , X86::FUCOMr },
+};
+
+static unsigned getConcreteOpcode(unsigned Opcode) {
+ ASSERT_SORTED(OpcodeTable);
+ int Opc = Lookup(OpcodeTable, ARRAY_SIZE(OpcodeTable), Opcode);
+ assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
+ return Opc;
+}
//===--===//
// Helper Methods
@@ -407,9 +464,12 @@
void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
unsigned DestReg = getFPReg(MI->getOperand(0));
- MI->RemoveOperand(0); // Remove the explicit ST(0) operand
- // Result gets pushed on the stack...
+ // Change from the pseudo instruction to the concrete instruction.
+ MI->RemoveOperand(0); // Remove the explicit ST(0) operand
+ MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
+
+ // Result gets pushed on the stack.
pushReg(DestReg);
}
@@ -424,20 +484,22 @@
unsigned Reg = getFPReg(MI->getOperand(MI->getNumOperands()-1));
bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg);
- // FSTP80r and FISTP64r are strange because there are no non-popping
versions.
+ // FISTP64r is strange because there isn't a non-popping versions.
// If we have one _and_ we don't want to pop the operand, duplicate the value
// on the stack instead of moving it. This ensure that popping the value is
// always ok.
//
- if ((MI->getOpcode() == X86::FSTP80m ||
- MI->getOpcode() == X86::FISTP64m) && !KillsSrc) {
+ if (MI->getOpcode() == X86::FpIST64m && !KillsSrc) {
duplicateToTop(Reg, 7 /*temp register*/, I);
} else {
moveToTop(Reg, I);// Mov
