[U-Boot] [PATCH v2] MIPS: initialize board_init_f() argument to zero.

2016-01-21 Thread Purna Chandra Mandal
Argument boot_flags of board_init_f() should be set to 0 as
$a0 may be utilized in lowlevel_init() or mips_cache_reset()
or previous stage boot-loader.

Signed-off-by: Purna Chandra Mandal 

---

Changes in v2:
- add comment in same line as of the asm instruction
- add commit message

 arch/mips/cpu/start.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index e95cdca..2aa2dcb 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -185,7 +185,7 @@ reset:
PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset
sw  sp, 0(t0)
 #endif
-
+   movea0, zero# a0 <-- boot_flags = 0
PTR_LA  t9, board_init_f
jr  t9
 move   ra, zero
-- 
1.8.3.1

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Re: [U-Boot] [PATCH v2 14/14] dm: video: test: Test that bitmap display works correctly

2016-01-21 Thread Simon Glass
On 18 January 2016 at 19:52, Simon Glass  wrote:
> Add a test for the 'bmp' command. Test both the uncompressed and compressed
> versions of the file, since they use different code paths.
>
> Signed-off-by: Simon Glass 
> Acked-by: Anatolij Gustschin 
> ---
>
> Changes in v2: None
>
>  include/configs/sandbox.h |   2 ++
>  test/dm/video.c   |  54 
> ++
>  tools/logos/denx-comp.bmp | Bin 0 -> 4148 bytes
>  3 files changed, 56 insertions(+)
>  create mode 100644 tools/logos/denx-comp.bmp

Applied to u-boot-dm
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Re: [U-Boot] [PATCH v2 13/14] dm: video: test: Add tests for rotated consoles

2016-01-21 Thread Simon Glass
On 18 January 2016 at 19:52, Simon Glass  wrote:
> Test that text is displayed correctly when the console is rotated.
>
> Signed-off-by: Simon Glass 
> Acked-by: Anatolij Gustschin 
> ---
>
> Changes in v2: None
>
>  configs/sandbox_defconfig |  1 +
>  test/dm/video.c   | 27 +++
>  2 files changed, 28 insertions(+)

Applied to u-boot-dm
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Re: [U-Boot] Please pull from u-boot-i2c

2016-01-21 Thread Tom Rini
On Thu, Jan 21, 2016 at 07:39:07AM +0100, Heiko Schocher wrote:

> Hello Tom,
> 
> please pull from u-boot-i2c.git
> 
> The following changes since commit 57e5ecaf755d5301cd33683788e4b8432938bbbe:
> 
>   iocon / bamboo: Drop CONFIG_SYS_LONGHELP (2016-01-20 15:25:00 -0500)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-i2c.git master
> 
> for you to fetch changes up to 9d0826879e13e8139a7b169c2365225e848ff57e:
> 
>   sunxi: Add support for the I2C controller which is part of the PRCM 
> (2016-01-21 07:30:01 +0100)
> 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [PATCH 01/19] video: Add stb TrueType font renderer

2016-01-21 Thread Måns Rullgård
Tom Rini  writes:

>> > style does not comply with U-Boot but I think it is best to leave alone to
>> > permit the source to be synced later if needed.
>> >
>> > The only change is to fix a reference to fabs() which should route through
>> > a macro to allow U-Boot to provide its own version.
>> 
>> This seems to be using floating-point quite a bit.  Unless I missed a
>> recent change, that's not allowed in u-boot.
>
> You are generally speaking, correct.  I am wondering if we don't need to
> make exceptions, from time to time.  For example, when we can easily
> correct general math problems by using something from 
> that's one thing and should be done.
>
> On the other hand, we have this, which is adding a nice looking font for
> the cases where our console is not a serial port but a screen and in
> some cases a rather nice high DPI one too.  So under the assumption that
> no, we can't find a font we can borrow that doesn't also use floating
> point, maybe we allow this, BUT with some caveats needing to be added
> such as noting that hey, what happens if you 'go' some benchmark that
> does FP stuff?  Well, it better be save/restoring, yes?

On some CPUs you also need to explicitly enable the FPU, and some rely
on software completion of certain operations (usually involving
subnormals).  Of course we shouldn't let that prevent other systems
having nice features.  We just need to be a bit careful about when we
enable them.

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Re: [U-Boot] FPGA detection failure on Cyclone V soc development kit

2016-01-21 Thread Tom Rini
On Wed, Jan 20, 2016 at 08:31:30PM +, Måns Rullgård wrote:

> I'm having a problem with u-boot 2016.01 failing to detect the FPGA on
> my Altera Cyclone V SoC Development Kit.  On startup, it simply prints
> "FPGA: Not Altera chip ID" (the ID having been read as all-zero).  No
> amount of messing with jumpers or switches makes a difference.  The
> software on the SD card included in the box appears to work, so on a
> whim I took the SPL pre-loader from this card and combined it with the
> main 2016.01 u-boot.  This makes the detection succeed, despite Marek
> baulking at this idea.  The "good" SPL identifies as "U-Boot SPL
> 2013.01.01 (Dec 04 2014 - 08:59:41)" which is a different build date
> than the main u-boot on the same SD card, so which source code version
> it was built from is anyone's guess.
> 
> What's interesting is that Marek's board works with u-boot 2016.01 while
> mine fails even with the very same binary.  The boards are different
> revisions (his 100-0321003-C1, mine -E1), and the main Cyclone V chips
> are also different (his 5CSXFC6D6F31C8NES, mine 5CSXFC6D6F31C6N).
> 
> Any suggestions for what to try next?

v2016.01 release or to of tree?  If top of tree, try
http://patchwork.ozlabs.org/patch/570009/

-- 
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Re: [U-Boot] FPGA detection failure on Cyclone V soc development kit

2016-01-21 Thread Marek Vasut
On Thursday, January 21, 2016 at 05:20:33 PM, Måns Rullgård wrote:
> Tom Rini  writes:
> > On Wed, Jan 20, 2016 at 08:31:30PM +, Måns Rullgård wrote:
> >> I'm having a problem with u-boot 2016.01 failing to detect the FPGA on
> >> my Altera Cyclone V SoC Development Kit.  On startup, it simply prints
> >> "FPGA: Not Altera chip ID" (the ID having been read as all-zero).  No
> >> amount of messing with jumpers or switches makes a difference.  The
> >> software on the SD card included in the box appears to work, so on a
> >> whim I took the SPL pre-loader from this card and combined it with the
> >> main 2016.01 u-boot.  This makes the detection succeed, despite Marek
> >> baulking at this idea.  The "good" SPL identifies as "U-Boot SPL
> >> 2013.01.01 (Dec 04 2014 - 08:59:41)" which is a different build date
> >> than the main u-boot on the same SD card, so which source code version
> >> it was built from is anyone's guess.
> >> 
> >> What's interesting is that Marek's board works with u-boot 2016.01 while
> >> mine fails even with the very same binary.  The boards are different
> >> revisions (his 100-0321003-C1, mine -E1), and the main Cyclone V chips
> >> are also different (his 5CSXFC6D6F31C8NES, mine 5CSXFC6D6F31C6N).
> >> 
> >> Any suggestions for what to try next?
> > 
> > v2016.01 release or to of tree?  If top of tree, try
> > http://patchwork.ozlabs.org/patch/570009/
> 
> Tried release, top of tree, and top of tree with that patch.  Nothing
> works.

btw. you dropped Dinh from the CC .

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 06/14] efi_loader: Add runtime services

2016-01-21 Thread Leif Lindholm
On Fri, Jan 15, 2016 at 06:06:12AM +0100, Alexander Graf wrote:
> After booting has finished, EFI allows firmware to still interact with the OS
> using the "runtime services". These callbacks live in a separate address 
> space,
> since they are available long after U-Boot has been overwritten by the OS.
> 
> This patch adds enough framework for arbitrary code inside of U-Boot to become
> a runtime service with the right section attributes set. For now, we don't 
> make
> use of it yet though.
> 
> We could maybe in the future map U-boot environment variables to EFI variables
> here.
> 
> Signed-off-by: Alexander Graf 

Just a couple of return value issues:

> ---
> 
> v1 -> v2:
> 
>   - Fix runtime service sections
>   - Add runtime detach
>   - Enable runtime relocations
>   - Add get_time
>   - Fix relocation
>   - Fix 32bit
>   - Add am335x support
>   - Move section definition to header
>   - Add systab to runtime section
>   - Add self-relocation hook table
>   - Fix self-relocation
>   - Relocate efi_runtime section early during bootup
>   - Fix return values for a number of callbacks to be more UEFI compliant
>   - Move to GPLv2+
> ---
>  arch/arm/config.mk|   4 +
>  arch/arm/cpu/armv8/u-boot.lds |  16 +++
>  arch/arm/cpu/u-boot.lds   |  30 +
>  arch/arm/lib/sections.c   |   4 +
>  board/ti/am335x/u-boot.lds|  30 +
>  common/board_r.c  |   4 +
>  include/efi_loader.h  |  10 ++
>  lib/efi_loader/efi_boottime.c |   6 +-
>  lib/efi_loader/efi_runtime.c  | 300 
> ++
>  9 files changed, 401 insertions(+), 3 deletions(-)
>  create mode 100644 lib/efi_loader/efi_runtime.c
> 

...

> diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
> new file mode 100644
> index 000..b7aa1e9
> --- /dev/null
> +++ b/lib/efi_loader/efi_runtime.c
> @@ -0,0 +1,300 @@
> +/*
> + *  EFI application runtime services
> + *
> + *  Copyright (c) 2016 Alexander Graf
> + *
> + *  SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/* For manual relocation support */
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static efi_status_t EFI_RUNTIME_TEXT efi_unimplemented(void);
> +static efi_status_t EFI_RUNTIME_TEXT efi_device_error(void);
> +static efi_status_t EFI_RUNTIME_TEXT efi_invalid_parameter(void);
> +
> +#if defined(CONFIG_ARM64)
> +#define R_RELATIVE   1027
> +#define R_MASK   0xULL
> +#define IS_RELA  1
> +#elif defined(CONFIG_ARM)
> +#define R_RELATIVE   23
> +#define R_MASK   0xffULL
> +#else
> +#error Need to add relocation awareness
> +#endif
> +
> +struct elf_rel {
> + ulong *offset;
> + ulong info;
> +};
> +
> +struct elf_rela {
> + ulong *offset;
> + ulong info;
> + long addend;
> +};
> +
> +/*
> + * EFI Runtime code lives in 2 stages. In the first stage, U-Boot and an EFI
> + * payload are running concurrently at the same time. In this mode, we can
> + * handle a good number of runtime callbacks
> + */
> +
> +static void efi_reset_system(enum efi_reset_type reset_type,
> + efi_status_t reset_status, unsigned long data_size,
> + void *reset_data)
> +{
> + EFI_ENTRY("%d %lx %lx %p", reset_type, reset_status, data_size, 
> reset_data);
> +
> + switch (reset_type) {
> + case EFI_RESET_COLD:
> + case EFI_RESET_WARM:
> + do_reset(NULL, 0, 0, NULL);
> + break;
> + case EFI_RESET_SHUTDOWN:
> + /* We don't have anything to map this to */
> + break;
> + }
> +
> + EFI_EXIT(EFI_SUCCESS);
> +}
> +
> +static efi_status_t efi_get_time(struct efi_time *time,
> +   struct efi_time_cap *capabilities)
> +{
> +#ifdef CONFIG_CMD_DATE
> +
> + struct rtc_time tm;
> + int r;
> +#ifdef CONFIG_DM_RTC
> + struct udevice *dev;
> +#endif
> +
> + EFI_ENTRY("%p %p", time, capabilities);
> +
> +#ifdef CONFIG_DM_RTC
> + r = uclass_get_device(UCLASS_RTC, 0, );
> + if (r)
> + return EFI_EXIT(EFI_UNSUPPORTED);

EFI_DEVICE_ERROR?

> +#endif
> +
> +#ifdef CONFIG_DM_RTC
> + r = dm_rtc_get(dev, );
> +#else
> + r = rtc_get();
> +#endif
> + if (r)
> + return EFI_EXIT(EFI_UNSUPPORTED);

EFI_DEVICE_ERROR?

> +
> + memset(time, 0, sizeof(*time));
> + time->year = tm.tm_year;
> + time->month = tm.tm_mon;
> + time->day = tm.tm_mday;
> + time->hour = tm.tm_hour;
> + time->minute = tm.tm_min;
> + time->daylight = tm.tm_isdst;
> +
> + return EFI_EXIT(EFI_SUCCESS);
> +
> +#else /* CONFIG_CMD_DATE */
> +
> + return EFI_DEVICE_ERROR;
> +
> +#endif /* CONFIG_CMD_DATE */
> +}


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Re: [U-Boot] [PATCH 01/19] video: Add stb TrueType font renderer

2016-01-21 Thread Tom Rini
> > style does not comply with U-Boot but I think it is best to leave alone to
> > permit the source to be synced later if needed.
> >
> > The only change is to fix a reference to fabs() which should route through
> > a macro to allow U-Boot to provide its own version.
> 
> This seems to be using floating-point quite a bit.  Unless I missed a
> recent change, that's not allowed in u-boot.

You are generally speaking, correct.  I am wondering if we don't need to
make exceptions, from time to time.  For example, when we can easily
correct general math problems by using something from 
that's one thing and should be done.

On the other hand, we have this, which is adding a nice looking font for
the cases where our console is not a serial port but a screen and in
some cases a rather nice high DPI one too.  So under the assumption that
no, we can't find a font we can borrow that doesn't also use floating
point, maybe we allow this, BUT with some caveats needing to be added
such as noting that hey, what happens if you 'go' some benchmark that
does FP stuff?  Well, it better be save/restoring, yes?

-- 
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Re: [U-Boot] FPGA detection failure on Cyclone V soc development kit

2016-01-21 Thread Måns Rullgård
Tom Rini  writes:

> On Wed, Jan 20, 2016 at 08:31:30PM +, Måns Rullgård wrote:
>
>> I'm having a problem with u-boot 2016.01 failing to detect the FPGA on
>> my Altera Cyclone V SoC Development Kit.  On startup, it simply prints
>> "FPGA: Not Altera chip ID" (the ID having been read as all-zero).  No
>> amount of messing with jumpers or switches makes a difference.  The
>> software on the SD card included in the box appears to work, so on a
>> whim I took the SPL pre-loader from this card and combined it with the
>> main 2016.01 u-boot.  This makes the detection succeed, despite Marek
>> baulking at this idea.  The "good" SPL identifies as "U-Boot SPL
>> 2013.01.01 (Dec 04 2014 - 08:59:41)" which is a different build date
>> than the main u-boot on the same SD card, so which source code version
>> it was built from is anyone's guess.
>> 
>> What's interesting is that Marek's board works with u-boot 2016.01 while
>> mine fails even with the very same binary.  The boards are different
>> revisions (his 100-0321003-C1, mine -E1), and the main Cyclone V chips
>> are also different (his 5CSXFC6D6F31C8NES, mine 5CSXFC6D6F31C6N).
>> 
>> Any suggestions for what to try next?
>
> v2016.01 release or to of tree?  If top of tree, try
> http://patchwork.ozlabs.org/patch/570009/

Tried release, top of tree, and top of tree with that patch.  Nothing
works.

-- 
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Re: [U-Boot] [PATCH] ARMv8:ls2-2080a: Implement core ERRATA 829520, 833471

2016-01-21 Thread york sun
On 01/21/2016 07:44 AM, Ashish Kumar wrote:



>> a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
>> index a503934..9ab5d97 100644
>> --- a/include/configs/ls2080a_common.h
>> +++ b/include/configs/ls2080a_common.h
>> @@ -18,6 +18,8 @@
>>  /* Errata fixes */
>>  #define CONFIG_ARM_ERRATA_828024
>>  #define CONFIG_ARM_ERRATA_826974
>> +#define CONFIG_ARM_ERRATA_833471
>> +#define CONFIG_ARM_ERRATA_829520
>>  
> 
> This seems to be a wrong location. This file is for board (common part for 
> multiple boards).
> 
> [Ashish]Could you please elaborate more? Errata is valid for both 
> ls2080/ls2085, in fact it is errata/bug in arm-v8 core
> 
Ashish,

You are enabling an SoC erratum, not a board erratum. It should be done in SoC
file. You may argue why there are ARM errata macros in this file already. I
think that was a mistake and should be moved out.

Since we don't have a config file for armv8, the closest one is
arch/arm/include/asm/arch-fsl-layerscape/config.h.

York

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Re: [U-Boot] [PATCH v2] board/t4240rdb: VID support

2016-01-21 Thread york sun
On 01/20/2016 11:31 PM, ying.zh...@freescale.com wrote:
> From: Ying Zhang 
> 
> The fuse status register provides the values from on-chip
> voltage ID efuses programmed at the factory.
> These values define the voltage requirements for
> the chip. u-boot reads FUSESR and translates the values
> into the appropriate commands to set the voltage output
> value of an external voltage regulator.
> 
> Signed-off-by: Ying Zhang 
> ---
> Changed from v1:
> - Not support IR chip is used in AMD mode
> ---
>  board/freescale/common/vid.c | 19 +--
>  board/freescale/common/vid.h |  4 
>  board/freescale/t4rdb/t4240rdb.c |  7 +++
>  include/configs/T4240RDB.h   | 10 ++
>  4 files changed, 38 insertions(+), 2 deletions(-)
> 
> diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
> index f1bed51..1bd65a8 100644
> --- a/board/freescale/common/vid.c
> +++ b/board/freescale/common/vid.c
> @@ -42,7 +42,7 @@ int __weak board_vdd_drop_compensation(void)
>   * The IR chip can show up under the following addresses:
>   * 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA)
>   * 0x09 (Verified on T1040RDB-PA)
> - * 0x38 (Verified on T2080QDS, T2081QDS)
> + * 0x38 (Verified on T2080QDS, T2081QDS, T4240RDB)
>   */
>  static int find_ir_chip_on_i2c(void)
>  {
> @@ -292,7 +292,7 @@ int adjust_vdd(ulong vdd_override)
>   (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
>  #endif
>   u32 fusesr;
> - u8 vid;
> + u8 vid, buf;
>   int vdd_target, vdd_current, vdd_last;
>   int ret, i2caddress;
>   unsigned long vdd_string_override;
> @@ -346,6 +346,21 @@ int adjust_vdd(ulong vdd_override)
>   debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
>   }
>  
> + /* check IR chip work on Intel mode*/
> + ret = i2c_read(i2caddress,
> +IR36021_INTEL_MODE_OOFSET,
> +1, (void *), 1);
> + if (ret) {
> + printf("VID: failed to read IR chip mode.\n");
> + ret = -1;
> + goto exit;
> + }
> + if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
> + printf("VID: IR Chip is not used in Intel mode.\n");
> + ret = -1;
> + goto exit;
> + }
> +
>   /* get the voltage ID from fuse status register */
>   fusesr = in_be32(>dcfg_fusesr);
>   /*

This change is not specifically for T4240RDB. Please separate IR change to
another patch.

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Re: [U-Boot] Uboot send pull request

2016-01-21 Thread Tom Rini
On Thu, Jan 21, 2016 at 02:48:11PM +0800, ub...@andestech.com wrote:

>  Hi Tom,
> 
>  Please pull the following patch from u-boot-nds32 into your tree.
>  Thanks!
> 
> The following changes since commit 077678eb0c226e52a1f90edabd3369ab26065b32:
> 
>   Merge git://git.denx.de/u-boot-dm (2016-01-12 18:12:42 -0500)
> 
> are available in the git repository at:
> 
> 
>   git://git.denx.de/u-boot-nds32.git master
> 
> for you to fetch changes up to b19cc6bf2160e09607e141fe0fc571701070d1d6:
> 
>   nds32: Fix compile error. (2016-01-21 10:41:43 +0800)
> 

Applied to u-boot/master, thanks!


-- 
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Re: [U-Boot] [RFC PATCH 6/6] clk: add fixed rate clock driver

2016-01-21 Thread Masahiro Yamada
2016-01-20 13:35 GMT+09:00 Simon Glass :
> Hi Masahiro,
>
> On 18 January 2016 at 22:15, Masahiro Yamada
>  wrote:
>> 2015-12-28 23:20 GMT+09:00 Simon Glass :
>>> Hi Masahiro,
>>>
>>> On 18 December 2015 at 04:15, Masahiro Yamada
>>>  wrote:
 This commit intends to implement "fixed-clock" as in Linux.
 (drivers/clk/clk-fixed-rate.c in Linux)

 If you need a very simple clock to just provide fixed clock rate
 like a crystal oscillator, you do not have to write a new driver.
 This driver can support it.

 Note:
 As you see in dts/ directories, fixed clocks are often collected in
 one container node like this:

   clocks {
   refclk_a: refclk_a {
   #clock-cells = <0>;
   compatible = "fixed-clock";
   clock-frequency = <1000>;
   };

   refclk_b: refclk_b {
   #clock-cells = <0>;
   compatible = "fixed-clock";
   clock-frequency = <2000>;
   };
   };

 This does not work in the current DM of U-Boot, unfortunately.
 The "clocks" node must have 'compatible = "simple-bus";' or something
 to bind children.
>>>
>>> I suppose we could explicitly probe the children of the 'clocks' node
>>> somewhere. What do you suggest?
>>>

 Most of developers would be unhappy about adding such a compatible
 string only in U-Boot because we generally want to use the same set
 of device trees beyond projects.
>>>
>>> I'm not sure we need to change it, but if we did, we could try to
>>> upstream the change.
>>>

 Signed-off-by: Masahiro Yamada 
 ---

 I do not understand why we need both .get_rate and .get_periph_rate.

 I set both in this driver, but I am not sure if I am doing right.
>>>
>>> This is to avoid needing a new clock device for every single clock
>>> divider in the SoC. For example, it is common to have a PLL be used by
>>> 20-30 devices. In U-Boot we can encode the device number as a
>>> peripheral ID, Then we can adjust those dividers by settings the
>>> clock's rate on a per-peripheral basis. Thus we need only one clock
>>> device instead of 20-30.
>>>
>>> In the case of your clock I think you could return -ENOSYS for
>>> get_periph_rate().
>>
>> I've just posted v2.
>>
>> I am still keeping both .get_rate() and .get_periph_rate().
>>
>> If I follow your suggestion, each clock consumer must know the
>> detail of its clock providers to choose the correct one,
>> either .get_rate() or .get_periph_rate().
>>
>> Or do you want drivers to do like this?
>>
>>
>>
>> clock_cells = clk_get_nr_cells(...);
>>
>> if (clock_cells == 0)
>>   rate = clk_get_rate(...);
>> else
>>   rate = clk_get_periph_rate(...);
>>
>>
>>
>> For the proper use of these two, the details of clocks must be
>> hard-coded in drivers.
>> They, of course should be describe in device tree and clock providers.
>
> In general drivers don't use PLLs directly. So I doubt this case will
> arise. Do you have an example?
>

No, I don't.

You commented "In the case of your clock I think you could return -ENOSYS for
get_periph_rate().", so I just imagined there is a case where drivers
call clk_get_rate(), not clk_get_periph_rate().



-- 
Best Regards
Masahiro Yamada
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Re: [U-Boot] [PATCH v2] MIPS: initialize board_init_f() argument to zero.

2016-01-21 Thread Daniel Schwierzeck


Am 21.01.2016 um 15:32 schrieb Purna Chandra Mandal:
> Argument boot_flags of board_init_f() should be set to 0 as
> $a0 may be utilized in lowlevel_init() or mips_cache_reset()
> or previous stage boot-loader.
> 
> Signed-off-by: Purna Chandra Mandal 
> 
> ---
> 
> Changes in v2:
> - add comment in same line as of the asm instruction
> - add commit message
> 
>  arch/mips/cpu/start.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

applied to u-boot-mips/next, thanks!
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[U-Boot] [PATCH] MIPS: start.S: fix and optimize instructions

2016-01-21 Thread Daniel Schwierzeck
Fix 32 vs 64 bit load/store instructions. Access CP0_WATCHHI as
32 Bit register. Use 64 Bit register access for clearing gd_data
and copying U-Boot.

Signed-off-by: Daniel Schwierzeck 
---
 arch/mips/cpu/start.S | 22 +++---
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index 2aa2dcb..d2c31ae 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -115,7 +115,7 @@ reset:
 
/* Clear watch registers */
MTC0zero, CP0_WATCHLO
-   MTC0zero, CP0_WATCHHI
+   mtc0zero, CP0_WATCHHI
 
/* WP(Watch Pending), SW0/1 should be cleared */
mtc0zero, CP0_CAUSE
@@ -161,14 +161,14 @@ reset:
 #endif
 
/* Set up temporary stack */
-   PTR_LI  t0, -16
+   li  t0, -16
PTR_LI  t1, CONFIG_SYS_INIT_SP_ADDR
and sp, t1, t0  # force 16 byte alignment
PTR_SUB sp, sp, GD_SIZE # reserve space for gd
and sp, sp, t0  # force 16 byte alignment
movek0, sp  # save gd pointer
 #ifdef CONFIG_SYS_MALLOC_F_LEN
-   PTR_LI  t2, CONFIG_SYS_MALLOC_F_LEN
+   li  t2, CONFIG_SYS_MALLOC_F_LEN
PTR_SUB sp, sp, t2  # reserve space for early malloc
and sp, sp, t0  # force 16 byte alignment
 #endif
@@ -177,14 +177,14 @@ reset:
/* Clear gd */
movet0, k0
 1:
-   sw  zero, 0(t0)
+   PTR_S   zero, 0(t0)
blt t0, t1, 1b
-PTR_ADDI t0, 4
+PTR_ADDI t0, PTRSIZE
 
 #ifdef CONFIG_SYS_MALLOC_F_LEN
-   PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset
-   sw  sp, 0(t0)
+   PTR_S   sp, GD_MALLOC_BASE(k0)  # gd->malloc_base offset
 #endif
+
movea0, zero# a0 <-- boot_flags = 0
PTR_LA  t9, board_init_f
jr  t9
@@ -224,11 +224,11 @@ ENTRY(relocate_code)
 * t2 = source end address
 */
 1:
-   lw  t3, 0(t0)
-   sw  t3, 0(t1)
-   PTR_ADDU t0, 4
+   PTR_L   t3, 0(t0)
+   PTR_S   t3, 0(t1)
+   PTR_ADDU t0, PTRSIZE
blt t0, t2, 1b
-PTR_ADDU t1, 4
+PTR_ADDU t1, PTRSIZE
 
/* If caches were enabled, we would have to flush them here. */
PTR_SUB a1, t1, s2  # a1 <-- size
-- 
2.5.0

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Re: [U-Boot] [PATCH v2 0/4] Add LPDDR3 support for A83T

2016-01-21 Thread Hans de Goede

Hi,

On 01/11/2016 06:20 PM, Vishnu Patekar wrote:

This adds LPDDR3 support for A83T and support for Banana Pi M3 which has LPDDR3.
These patches are based on u-boot-sunxi next branch.

These patches tesed on Banana-pi M3. DCDC5 voltage is kept as 1.2V

changes from v1 -> v2
1. introduce CONFIG_DRAM_TYPE for A83T default 3(DDR3),
 removed DRAM_TYPE from Obsolete SYS_EXTRA_OPTIONS.
2. Cleanup in seperate patch.
3. set rank 2, in mctl_sys_init.


Thanks! I've merged this with the rename Chen-Yu suggested
for the defconfig/dts applied.

Regards,

Hans
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Re: [U-Boot] [PATCH 8/8] test/py: add DFU test

2016-01-21 Thread Stephen Warren

On 01/21/2016 03:50 AM, Lukasz Majewski wrote:

Hi Stephen,


From: Stephen Warren 

Add a test of DFU functionality to the Python test suite. The test
starts DFU in U-Boot, waits for USB device enumeration on the host,
executes dfu-util multiple times to test various transfer sizes, many
of which trigger USB driver edge cases, and finally aborts the DFU
command in U-Boot.

This test mirrors the functionality previously available via the shell
scripts in test/dfu, and hence those are removed too.

...

Acked-by: Lukasz Majewski 

Great work Stephen, Thanks !


Thanks for the review. I'm glad you're OK with the patch, given it 
deletes your previous script.


I'll hold off on posting v2 (for the comment fix) for a few days in case 
there are other comments.

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Re: [U-Boot] [PATCH 1/4] sunxi: Support Secure Memory Touch Arbiter (SMTA) in sun8i H3

2016-01-21 Thread Hans de Goede

Hi,

On 01/06/2016 08:13 AM, Chen-Yu Tsai wrote:

Secure Memory Touch Arbiter is the same thing as the TrustZone
Protection Controller found on A31/A31s.

Access to many peripherals on the H3 can be controlled by the SMTA,
and the settings default to secure access only.

This patch supports the new settings, and sets them to allow non-secure
access.


Except that you've forgotten to update arch/arm/cpu/armv7/sunxi/board.c
to actually call tzpc_init on the H3, I've added this chunk to fix this:

@@ -127,8 +127,8 @@ void s_init(void)
"orr r0, r0, #1 << 6\n"
"mcr p15, 0, r0, c1, c0, 1\n");
 #endif
-#if defined CONFIG_MACH_SUN6I
-   /* Enable non-secure access to the RTC */
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
+   /* Enable non-secure access to some peripherals */
tzpc_init();
 #endif

Regards,

Hans





Signed-off-by: Chen-Yu Tsai 
---
  arch/arm/cpu/armv7/sunxi/Makefile  |  1 +
  arch/arm/cpu/armv7/sunxi/tzpc.c| 11 ++-
  arch/arm/include/asm/arch-sunxi/tzpc.h | 13 -
  3 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
b/arch/arm/cpu/armv7/sunxi/Makefile
index dfb0a3e..7a6a3cc 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_MACH_SUN8I)  += clock_sun6i.o
  endif
  obj-$(CONFIG_MACH_SUN9I)  += clock_sun9i.o
  obj-$(CONFIG_MACH_SUN6I)  += tzpc.o
+obj-$(CONFIG_MACH_SUN8I)   += tzpc.o

  obj-$(CONFIG_AXP152_POWER)+= pmic_bus.o
  obj-$(CONFIG_AXP209_POWER)+= pmic_bus.o
diff --git a/arch/arm/cpu/armv7/sunxi/tzpc.c b/arch/arm/cpu/armv7/sunxi/tzpc.c
index 5c9c69b..6c8a0fd 100644
--- a/arch/arm/cpu/armv7/sunxi/tzpc.c
+++ b/arch/arm/cpu/armv7/sunxi/tzpc.c
@@ -13,6 +13,15 @@ void tzpc_init(void)
  {
struct sunxi_tzpc *tzpc = (struct sunxi_tzpc *)SUNXI_TZPC_BASE;

+#ifdef CONFIG_MACH_SUN6I
/* Enable non-secure access to the RTC */
-   writel(SUNXI_TZPC_DECPORT0_RTC, >decport0_set);
+   writel(SUN6I_TZPC_DECPORT0_RTC, >decport0_set);
+#endif
+
+#ifdef CONFIG_MACH_SUN8I_H3
+   /* Enable non-secure access to all peripherals */
+   writel(SUN8I_H3_TZPC_DECPORT0_ALL, >decport0_set);
+   writel(SUN8I_H3_TZPC_DECPORT1_ALL, >decport1_set);
+   writel(SUN8I_H3_TZPC_DECPORT2_ALL, >decport2_set);
+#endif
  }
diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h 
b/arch/arm/include/asm/arch-sunxi/tzpc.h
index ba4d43b..95c55cd 100644
--- a/arch/arm/include/asm/arch-sunxi/tzpc.h
+++ b/arch/arm/include/asm/arch-sunxi/tzpc.h
@@ -13,10 +13,21 @@ struct sunxi_tzpc {
u32 decport0_status;/* 0x04 Status of decode protection port 0 */
u32 decport0_set;   /* 0x08 Set decode protection port 0 */
u32 decport0_clear; /* 0x0c Clear decode protection port 0 */
+   /* For A80 and later SoCs */
+   u32 decport1_status;/* 0x10 Status of decode protection port 1 */
+   u32 decport1_set;   /* 0x14 Set decode protection port 1 */
+   u32 decport1_clear; /* 0x18 Clear decode protection port 1 */
+   u32 decport2_status;/* 0x1c Status of decode protection port 2 */
+   u32 decport2_set;   /* 0x20 Set decode protection port 2 */
+   u32 decport2_clear; /* 0x24 Clear decode protection port 2 */
  };
  #endif

-#define SUNXI_TZPC_DECPORT0_RTC(1 << 1)
+#define SUN6I_TZPC_DECPORT0_RTC(1 << 1)
+
+#define SUN8I_H3_TZPC_DECPORT0_ALL  0xbe
+#define SUN8I_H3_TZPC_DECPORT1_ALL  0xff
+#define SUN8I_H3_TZPC_DECPORT2_ALL  0x7f

  void tzpc_init(void);



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Re: [U-Boot] [PATCH 0/4] sunxi: PSCI support for H3

2016-01-21 Thread Hans de Goede

Hi,

On 01/06/2016 08:13 AM, Chen-Yu Tsai wrote:

Hi everyone,

This series enables PSCI support for the H3. Like other Allwinner SoCs,
the implementation only supports PSCI 0.1, specifically only secondary
CPU boot/hotplug.

Patch 1 supports the SMTA (previously called TZPC) TrustZone hardware
on H3. This controls non-secure access to some important hardware blocks.

Patch 2 supports the security switch in H3's CCU. This is H3 only. No
other SoCs have this feature.

Patch 3 supports H3 using sun6i PSCI implementation. H3 uses the same
power sequence as sun6i, including the power clamps. This is shown in
Allwinner's SDK, and confirmed / tested by Siarhei.

Patch 4 enables PSCI support for the H3 in Kconfig.


I've only tested booting HYP/SMP on my Orange Pi PC. Hotplugging was not
tested, but should work.


Many thanks for this patch-set, I've applied this to my tree, and it will
be part of the pull-req I plan to send out this weekend.

Regards,

Hans
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Re: [U-Boot] [PATCH] igep00x0: enable CONFIG_CMD_SETEXPR

2016-01-21 Thread Ladislav Michl
On Thu, Jan 21, 2016 at 02:11:13PM -0500, Tom Rini wrote:
> On Thu, Jan 21, 2016 at 11:35:01AM +0100, Ladislav Michl wrote:
> 
> > Enable CONFIG_CMD_SETEXPR, useful when passing initramfs end address:
> > $ fatload mmc 0:1 $rdaddr root.cpio.gz
> > $ setexpr rdendaddr $rdaddr + $filesize
> > $ fdt chosen $rdaddr $rdendaddr
> > $ bootz $loadaddr - $fdtaddr
> 
> OK, but why do that instead of 'bootz $loadaddr $rdaddr $fdtaddr' ?

=> bootz $loadaddr $rdaddr $fdtaddr
Wrong Ramdisk Image Format
Ramdisk image is corrupt or invalid

Well, perhaps that could be done with CONFIG_SUPPORT_RAW_INITRD, which
expects size of initrd, not an end address. I'll give it a try and possibly
enable that instead.

ladis
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Re: [U-Boot] [PATCH] igep00x0: enable CONFIG_CMD_SETEXPR

2016-01-21 Thread Ladislav Michl
On Thu, Jan 21, 2016 at 08:56:15PM +0100, Ladislav Michl wrote:
> On Thu, Jan 21, 2016 at 02:11:13PM -0500, Tom Rini wrote:
[...]
> > OK, but why do that instead of 'bootz $loadaddr $rdaddr $fdtaddr' ?
> 
> => bootz $loadaddr $rdaddr $fdtaddr
> Wrong Ramdisk Image Format
> Ramdisk image is corrupt or invalid
> 
> Well, perhaps that could be done with CONFIG_SUPPORT_RAW_INITRD, which
> expects size of initrd, not an end address. I'll give it a try and possibly
> enable that instead.

Ok, works and is even already defined in ti_armv7_common.h and
'bootz $loadaddr $rdaddr:$filesize $fdtaddr' is even simpler. Thank you :)

ladis
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Re: [U-Boot] [PATCH] ARMv8:ls2-2080a: Implement core ERRATA 829520, 833471

2016-01-21 Thread Ashish Kumar
Please see inline

Regards
Ashish

-Original Message-
From: york sun [mailto:york@nxp.com] 
Sent: Tuesday, January 19, 2016 10:34 PM
To: Ashish Kumar ; u-boot@lists.denx.de
Subject: Re: [PATCH] ARMv8:ls2-2080a: Implement core ERRATA 829520, 833471

On 01/17/2016 11:15 PM, Ashish Kumar wrote:
>  * 829520: Code bounded by indirect conditional branch might corrupt 
> instruction stream,
> Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect 
> Predictor
> 
>  * 833471: VMSR FPSCR functional failure or deadlock
> Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush
> 
> Signed-off-by: Ashish Kumar 
> ---
>  arch/arm/cpu/armv8/start.S   |   20 
>  include/configs/ls2080a_common.h |2 ++
>  2 files changed, 22 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S 
> index da45d98..dd583c9 100644
> --- a/arch/arm/cpu/armv8/start.S
> +++ b/arch/arm/cpu/armv8/start.S
> @@ -132,6 +132,26 @@ apply_a57_core_errata:
>   msr S3_1_c15_c2_0, x0   /* cpuactlr_el1 */
>  #endif
>  
> +#ifdef CONFIG_ARM_ERRATA_833471
> + mrs x0, S3_1_c15_c2_0   /* cpuactlr_el1 */
> + /* FPSCR write flush.
> +  * Note that in some cases where a flush is unnecessary this
> + could impact performance. */
> + orr x0, x0, #1 << 38
> + msr S3_1_c15_c2_0, x0   /* cpuactlr_el1 */
> +#endif
> +
> +#ifdef CONFIG_ARM_ERRATA_829520
> + mrs x0, S3_1_c15_c2_0   /* cpuactlr_el1 */
> + /* Disable Indirect Predictor bit will prevent this erratum
> + from occurring
> +  * Note that in some cases where a flush is unnecessary this
> + could impact performance. */
> + orr x0, x0, #1 << 4
> + msr S3_1_c15_c2_0, x0   /* cpuactlr_el1 */
> +#endif
> +
> +
>  #ifdef CONFIG_ARM_ERRATA_833069
>   mrs x0, S3_1_c15_c2_0   /* cpuactlr_el1 */
>   /* Disable Enable Invalidates of BTB bit */ diff --git 
> a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
> index a503934..9ab5d97 100644
> --- a/include/configs/ls2080a_common.h
> +++ b/include/configs/ls2080a_common.h
> @@ -18,6 +18,8 @@
>  /* Errata fixes */
>  #define CONFIG_ARM_ERRATA_828024
>  #define CONFIG_ARM_ERRATA_826974
> +#define CONFIG_ARM_ERRATA_833471
> +#define CONFIG_ARM_ERRATA_829520
>  

This seems to be a wrong location. This file is for board (common part for 
multiple boards).

[Ashish]Could you please elaborate more? Errata is valid for both 
ls2080/ls2085, in fact it is errata/bug in arm-v8 core

York

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Re: [U-Boot] [PATCH v5 2/2] usb: eth: add Realtek RTL8152B/RTL8153 DRIVER

2016-01-21 Thread Anand Moon
Hi Marek,

On 21 January 2016 at 02:04, Marek Vasut  wrote:
> On Wednesday, January 20, 2016 at 09:10:07 PM, Anand Moon wrote:
>> Hi Ted / Marek / Stephen,
>>
>> On 20 January 2016 at 22:22, Stephen Warren  wrote:
>> > On 01/19/2016 11:24 PM, Ted Chen wrote:
>> >> This patch adds driver support for the Realtek RTL8152B/RTL8153 USB
>> >> network adapters.
>> >
>> > This looks fine to me, although I didn't take a detailed enough look to
>> > actually give and an ack/reviewed-by.
>>
>> What about the other patch: usb xhci Fix vendor command error if the
>> request.patch
>
> Please repost it , make sure to CC everyone . If there is agreement that
> it fixes real issue, I'll pick it.
>
>> After setting the usbether mac address my odroid xu4 board shop booting.
>> even after reset of environment it dose not boot.
>> ---
>> -- U-Boot 2016.01-00406-g048c61d-dirty (Jan 21
>> 2016 - 06:27:09 +1030) for ODROID-XU3
>>
>> CPU:   Exynos5422 @ 800 MHz
>> Model: Odroid XU3 based on EXYNOS5422
>> Board: Odroid XU3 based on EXYNOS5422
>> Type:  xu4
>> DRAM:  2 GiB
>> MMC:   EXYNOS DWMMC: 0, EXYNOS DWMMC: 1
>> *** Warning - bad CRC, using default environment
>>
>> In:serial
>> Out:   serial
>> Err:   serial
>> Net:   No ethernet found.
>> Hit any key to stop autoboot:  0
>> ODROID-XU3 #
>> ODROID-XU3 #
>> ODROID-XU3 #
>> ODROID-XU3 # setenv usbethaddr 00:1e:06:31:06:b3
>> ODROID-XU3 # saveenv
>
> You ran saveenv, so usbethaddr is now in permanent storage. That's why
> 'reset' won't help you.
>

But I need to set common mac address so that I will get single IP.
I don't need random mac address.

Any way thanks for your input.

>> Saving Environment to MMC...
>> Writing to MMC(0)... done
>> ODROID-XU3 # usb info
>> USB is stopped. Please issue 'usb start' first.
>> ODROID-XU3 # usb start
>> starting USB...
>> USB0:   USB EHCI 1.00
>> USB1:   Register 2000140 NbrPorts 2
>> Starting the controller
>> USB XHCI 1.00
>> USB2:   Register 2000140 NbrPorts 2
>> Starting the controller
>> USB XHCI 1.00
>> scanning bus 0 for devices... 1 USB Device(s) found
>> scanning bus 1 for devices... Device not responding to set address.
>>
>>   USB device not accepting new address (error=8000)
>
> This error looks suspicious.

I had another wireless mouse and USB to Ethernet adapter connected to the board
may be it's not getting recognized at that moment.

Any way thanks for you input.

>
>> 2 USB Device(s) found
>> scanning bus 2 for devices... 2 USB Device(s) found
>>scanning usb for ethernet devices... 1 Ethernet Device(s) found
> [...]

Well I have tested the TFTP booting functionality of the board and it
was success.
Fell free to add my tested by for this version.

Tested-by: Anand Moon 

Best Regards.
-Anand Moon
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[U-Boot] [PATCH v4 3/3] armv8/ls1043aqds: Add lpuart support

2016-01-21 Thread Wenbin Song
Add lpuart support using the driver model.

Signed-off-by: Wenbin Song 
---
Changes in v4:
- No change
---
 arch/arm/dts/Makefile   |  1 +
 arch/arm/dts/fsl-ls1043a-qds-lpuart.dts | 16 ++
 arch/arm/dts/fsl-ls1043a-qds.dtsi   |  4 +++
 arch/arm/dts/fsl-ls1043a.dtsi   | 54 +
 configs/ls1043aqds_lpuart_defconfig | 10 ++
 include/configs/ls1043aqds.h|  5 +++
 6 files changed, 90 insertions(+)
 create mode 100644 arch/arm/dts/fsl-ls1043a-qds-lpuart.dts
 create mode 100644 configs/ls1043aqds_lpuart_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 302456c..a51275c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -97,6 +97,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
+   fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb
 
 dtb-$(CONFIG_MACH_SUN4I) += \
diff --git a/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts 
b/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts
new file mode 100644
index 000..18adb97
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1043a-qds.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi 
b/arch/arm/dts/fsl-ls1043a-qds.dtsi
index 6fa16b8..b9dad72 100644
--- a/arch/arm/dts/fsl-ls1043a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi
@@ -121,3 +121,7 @@
  {
status = "okay";
 };
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 85ea81e..12ea0ab 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -182,5 +182,59 @@
interrupts = <0 55 0x4>;
clocks = < 4 0>;
};
+
+   lpuart0: serial@295 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x295 0x0 0x1000>;
+   interrupts = <0 48 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart1: serial@296 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x296 0x0 0x1000>;
+   interrupts = <0 49 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart2: serial@297 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x297 0x0 0x1000>;
+   interrupts = <0 50 0x4>;
+   clock-names = "ipg";
+   clocks = <>;
+   status = "disabled";
+   };
+
+   lpuart3: serial@298 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x298 0x0 0x1000>;
+   interrupts = <0 51 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart4: serial@299 {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x299 0x0 0x1000>;
+   interrupts = <0 52 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
+
+   lpuart5: serial@29a {
+   compatible = "fsl,ls1021a-lpuart";
+   reg = <0x0 0x29a 0x0 0x1000>;
+   interrupts = <0 53 0x4>;
+   clocks = <>;
+   clock-names = "ipg";
+   status = "disabled";
+   };
};
 };
diff --git a/configs/ls1043aqds_lpuart_defconfig 
b/configs/ls1043aqds_lpuart_defconfig
new file mode 100644
index 000..21d6407
--- /dev/null
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -0,0 +1,10 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_FSL_LPUART=y
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 398f1c3..b55ed58 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -88,6 +88,11 @@ unsigned long get_board_ddr_clk(void);
 #define 

Re: [U-Boot] [v2] mmc: fsl_esdhc: fix mmc read/write error on T4080

2016-01-21 Thread Yangbo Lu
> -Original Message-
> From: Tom Rini [mailto:tr...@konsulko.com]
> Sent: Tuesday, January 19, 2016 11:59 PM
> To: Yangbo Lu
> Cc: york sun; Andy Fleming; U-Boot list
> Subject: Re: [U-Boot] [v2] mmc: fsl_esdhc: fix mmc read/write error on
> T4080
> 
> On Mon, Jan 18, 2016 at 07:18:59AM +, Yangbo Lu wrote:
> > > -Original Message-
> > > From: Tom Rini [mailto:tr...@konsulko.com]
> > > Sent: Friday, January 15, 2016 2:09 AM
> > > To: york sun
> > > Cc: Andy Fleming; Yangbo Lu; U-Boot list
> > > Subject: Re: [U-Boot] [v2] mmc: fsl_esdhc: fix mmc read/write error
> > > on
> > > T4080
> > >
> > > On Thu, Jan 14, 2016 at 05:51:32PM +, york sun wrote:
> > > > On 01/08/2016 04:23 PM, Andy Fleming wrote:
> > > > > On Thu, Jan 7, 2016 at 2:50 AM, Yangbo Lu 
> wrote:
> > > > >> Fill the right command type when using CMD12 to stop data
> transfer.
> > > > >>
> > > > >> Signed-off-by: Yangbo Lu 
> > > > >> ---
> > > > >> Changes for v2:
> > > > >> - Removed fix for T4160 because other patch had done
> > > > >> that
> > > > >> ---
> > > > >>  drivers/mmc/fsl_esdhc.c | 2 +-
> > > > >>  1 file changed, 1 insertion(+), 1 deletion(-)
> > > > >>
> > > > >> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> > > > >> index c5054d6..16fb01a 100644
> > > > >> --- a/drivers/mmc/fsl_esdhc.c
> > > > >> +++ b/drivers/mmc/fsl_esdhc.c
> > > > >> @@ -107,7 +107,7 @@ static uint esdhc_xfertyp(struct mmc_cmd
> > > > >> *cmd, struct mmc_data *data)
> > > > >>
> > > > >>  #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
> > > > >> defined(CONFIG_LS102XA) ||
> > > > >> defined(CONFIG_FSL_LAYERSCAPE) ||
> > > \
> > > > >> -   defined(CONFIG_PPC_T4160)
> > > > >> +   defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
> > > > >> if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
> > > > >> xfertyp |= XFERTYP_CMDTYP_ABORT;  #endif
> > > > >
> > > > >
> > > > > These sorts of chip-specific #ifdefs are very hard to maintain.
> > > > > It would be far better if there were a single define, like:
> > > > >
> > > > > #ifdef CONFIG_FSL_ESDHC_USES_ABORT_TO_STOP
> > > > >
> > > > > And then define that on any system that needs this code. With
> > > > > the current version, I have no idea why this code is needed. I
> > > > > have guesses, but in order to be sure, I'd have to check several
> > > > > reference manuals. With my suggestion, it is obvious to everyone
> > > > > why this code is here, and it gives a hint to those who are
> > > > > adding support to new chips.
> > > > >
> > > > > Now, I'm not saying you should use my suggestion precisely.
> > > > > Perhaps every version of the esdhc after some point uses this
> > > > > mechanism. Then you could use that information. And perhaps my
> > > > > naming doesn't reflect what is happening. My point is, you're
> > > > > going to have to do this again when you release LS232XB, and that
> seems like a poor use of your time.
> > > > > :)
> > > >
> > > > Yangbo,
> > > >
> > > > I agree with Andy on this. Please make the suggested change.
> > >
> > > ... as some sort of Kconfig entry that's ideally selected rather
> > > than prmopted for when applicable.  Like it would be done in the
> > > kernel :)
> > >
> > > --
> > > Tom
> > [Lu Yangbo-B47093] Hi Tom, I want to reconfirm whether your suggestion
> is same with Andy and York's.
> > Could I define it in include/configs/.h? Or use Kconfig?
> 
> I'm agreeing with what Andy/York say and noting that the right way to fix
> this is not to add something to include/configs/ but to use Kconfig and
> have the platforms select the symbol (rather than prompt for it), similar
> to how flags like this would work in the Linux kernel.
> 
> --
> Tom

[Lu Yangbo-B47093] Thank you. But I just find I need to remove all the #ifdef 
rather than add one.
Because the MMC_CMD_STOP_TRANSMISSION command must be set a 
XFERTYP_CMDTYP_ABORT command type according to SD spec.

A new version patch would be sent later.

Best regards,
Yangbo Lu
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[U-Boot] [PATCH v4 2/3] armv8/ls1043aqds: Spilt off board device tree

2016-01-21 Thread Wenbin Song
Move new /chosen node out of the board device tree.

Signed-off-by: Wenbin Song 
---
Changes in v4:
- No change
---
 arch/arm/dts/Makefile|  2 +-
 arch/arm/dts/fsl-ls1043a-qds-duart.dts   | 16 
 .../dts/{fsl-ls1043a-qds.dts => fsl-ls1043a-qds.dtsi}|  1 -
 configs/ls1043aqds_defconfig |  2 +-
 4 files changed, 18 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/dts/fsl-ls1043a-qds-duart.dts
 rename arch/arm/dts/{fsl-ls1043a-qds.dts => fsl-ls1043a-qds.dtsi} (99%)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7706b41..302456c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -96,7 +96,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb
-dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds.dtb \
+dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-rdb.dtb
 
 dtb-$(CONFIG_MACH_SUN4I) += \
diff --git a/arch/arm/dts/fsl-ls1043a-qds-duart.dts 
b/arch/arm/dts/fsl-ls1043a-qds-duart.dts
new file mode 100644
index 000..2124e38
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1043a-qds-duart.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1043a-qds.dtsi"
+
+/ {
+   chosen {
+   stdout-path = 
+   };
+};
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dts 
b/arch/arm/dts/fsl-ls1043a-qds.dtsi
similarity index 99%
rename from arch/arm/dts/fsl-ls1043a-qds.dts
rename to arch/arm/dts/fsl-ls1043a-qds.dtsi
index 7435222..6fa16b8 100644
--- a/arch/arm/dts/fsl-ls1043a-qds.dts
+++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi
@@ -10,7 +10,6 @@
  * warranty of any kind, whether express or implied.
  */
 
-/dts-v1/;
 /include/ "fsl-ls1043a.dtsi"
 
 / {
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index 60fb0ad..1fd530d 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -2,5 +2,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043AQDS=y
 CONFIG_SYS_NS16550=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_OF_CONTROL=y
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v4 1/3] armv8/ls1043aqds: Select lpuart pins of various muxes

2016-01-21 Thread Wenbin Song
From: Shaohui Xie 

Set Board Configuration Register to select the lpuart pins of various
muxes.

Signed-off-by: Shaohui Xie 
Signed-off-by: Mingkai Hu 
---
Changes in v4:
- remove the blank line and ending period
- modify the suffix of lpuart to 0 on the comment 
---
 board/freescale/ls1043aqds/ls1043aqds.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c 
b/board/freescale/ls1043aqds/ls1043aqds.c
index d6696ca..080d5b5 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -40,6 +40,9 @@ enum {
 #define CFG_SD_MUX3_MUX4   0x1 /* MUX4 */
 #define CFG_SD_MUX4_SLOT3  0x0 /* SLOT3 TX/RX1 */
 #define CFG_SD_MUX4_SLOT1  0x1 /* SLOT1 TX/RX3 */
+#define CFG_UART_MUX_MASK  0x6
+#define CFG_UART_MUX_SHIFT 1
+#define CFG_LPUART_EN  0x1
 
 int checkboard(void)
 {
@@ -218,7 +221,17 @@ void board_retimer_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_LPUART
+   u8 uart;
+#endif
fsl_lsch2_early_init_f();
+#ifdef CONFIG_LPUART
+   /* We use lpuart0 as system console */
+   uart = QIXIS_READ(brdcfg[14]);
+   uart &= ~CFG_UART_MUX_MASK;
+   uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
+   QIXIS_WRITE(brdcfg[14], uart);
+#endif
 
return 0;
 }
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCHv2 3/3] ARMv8/ls1043ardb: Integrate FSL PPA

2016-01-21 Thread Zhiqiang Hou
From: Hou Zhiqiang 

Signed-off-by: Hou Zhiqiang 
---
V2
 - No change.
 board/freescale/ls1043ardb/ls1043ardb.c | 11 +++
 include/configs/ls1043ardb.h|  9 +
 2 files changed, 20 insertions(+)

diff --git a/board/freescale/ls1043ardb/ls1043ardb.c 
b/board/freescale/ls1043ardb/ls1043ardb.c
index c8f723a..eff09aa 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -94,6 +95,9 @@ int board_early_init_f(void)
 int board_init(void)
 {
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+#ifdef CONFIG_FSL_LS_PPA
+   u64 ppa_entry;
+#endif
 
/*
 * Set CCI-400 control override register to enable barrier
@@ -113,6 +117,13 @@ int board_init(void)
enable_layerscape_ns_access();
 #endif
 
+#ifdef CONFIG_FSL_LS_PPA
+   ppa_init_pre(_entry);
+
+   if (ppa_entry)
+   ppa_init_entry((void *)ppa_entry);
+#endif
+
return 0;
 }
 
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 585114f..fd28814 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -9,6 +9,15 @@
 
 #include "ls1043a_common.h"
 
+#if defined(CONFIG_FSL_LS_PPA)
+#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE  (1UL * 1024 * 1024)
+
+#define CONFIG_SYS_LS_PPA_FW_IN_NOR
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
+#defineCONFIG_SYS_LS_PPA_FW_ADDR   0x6050
+#endif
+#endif
+
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCHv2 2/3] ARMv8/layerscape: Add FSL PPA support

2016-01-21 Thread Zhiqiang Hou
From: Hou Zhiqiang 

The FSL Primary Protected Application (PPA) is a software component
loaded during boot which runs in TrustZone and remains resident
after boot.

Signed-off-by: Hou Zhiqiang 
---
Tested on LS1043A RDB board

V2:
 - Added arguments of boot location pointer to ppa_init.

 arch/arm/cpu/armv8/fsl-layerscape/Makefile |   1 +
 arch/arm/cpu/armv8/fsl-layerscape/ppa.c| 212 +
 arch/arm/cpu/armv8/fsl-layerscape/ppa_entry.S  |  42 +
 arch/arm/include/asm/arch-fsl-layerscape/ppa.h |  15 ++
 4 files changed, 270 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ppa.c
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ppa_entry.S
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/ppa.h

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile 
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index cce7405..27bfeb1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -10,6 +10,7 @@ obj-y += soc.o
 obj-$(CONFIG_MP) += mp.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 obj-$(CONFIG_SPL) += spl.o
+obj-$(CONFIG_FSL_LS_PPA) += ppa.o ppa_entry.o
 
 ifneq ($(CONFIG_FSL_LSCH3),)
 obj-y += fsl_lsch3_speed.o
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c 
b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
new file mode 100644
index 000..db767f9
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#ifdef CONFIG_FSL_LSCH3
+#include 
+#elif defined(CONFIG_FSL_LSCH2)
+#include 
+#endif
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void c_runtime_cpu_setup(void);
+
+#define LS_PPA_FIT_FIRMWARE_IMAGE  "firmware"
+#define LS_PPA_FIT_CNF_NAME"config@1"
+#define PPA_MEM_SIZE_ENV_VAR   "ppamemsize"
+
+/*
+ * Return the actual size of the PPA private DRAM block.
+ */
+unsigned long ppa_get_dram_block_size(void)
+{
+   unsigned long dram_block_size = CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE;
+
+   char *dram_block_size_env_var = getenv(PPA_MEM_SIZE_ENV_VAR);
+
+   if (dram_block_size_env_var) {
+   dram_block_size = simple_strtoul(dram_block_size_env_var, NULL,
+10);
+
+   if (dram_block_size < CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE) {
+   printf("fsl-ppa: WARNING: Invalid value for \'"
+  PPA_MEM_SIZE_ENV_VAR
+  "\' environment variable: %lu\n",
+  dram_block_size);
+
+   dram_block_size = CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE;
+   }
+   }
+
+   return dram_block_size;
+}
+
+/*
+ * PPA firmware FIT image parser checks if the image is in FIT
+ * format, verifies integrity of the image and calculates raw
+ * image address and size values.
+ *
+ * Returns 0 on success and a negative errno on error task fail.
+ */
+static int parse_ppa_firmware_fit_image(const void **raw_image_addr,
+   size_t *raw_image_size)
+{
+   const void *ppa_data;
+   size_t ppa_size;
+   void *fit_hdr;
+   int conf_node_off, fw_node_off;
+   char *conf_node_name = NULL;
+
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
+   fit_hdr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
+#else
+#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
+#endif
+
+   conf_node_name = LS_PPA_FIT_CNF_NAME;
+
+   if (fdt_check_header(fit_hdr)) {
+   printf("fsl-ppa: Bad firmware image (not a FIT image)\n");
+   return -EINVAL;
+   }
+
+   if (!fit_check_format(fit_hdr)) {
+   printf("fsl-ppa: Bad firmware image (bad FIT header)\n");
+   return -EINVAL;
+   }
+
+   conf_node_off = fit_conf_get_node(fit_hdr, conf_node_name);
+   if (conf_node_off < 0) {
+   printf("fsl-ppa: %s: no such config\n", conf_node_name);
+   return -ENOENT;
+   }
+
+   fw_node_off = fit_conf_get_prop_node(fit_hdr, conf_node_off,
+   LS_PPA_FIT_FIRMWARE_IMAGE);
+   if (fw_node_off < 0) {
+   printf("fsl-ppa: No '%s' in config\n",
+   LS_PPA_FIT_FIRMWARE_IMAGE);
+   return -ENOLINK;
+   }
+
+   /* Verify PPA firmware image */
+   if (!(fit_image_verify(fit_hdr, fw_node_off))) {
+   printf("fsl-ppa: Bad firmware image (bad CRC)\n");
+   return -EINVAL;
+   }
+
+   if (fit_image_get_data(fit_hdr, fw_node_off, _data, _size)) {
+   printf("fsl-ppa: Can't get %s subimage data/size",
+   LS_PPA_FIT_FIRMWARE_IMAGE);
+   return -ENOENT;
+   }
+
+   debug("fsl-ppa: 

[U-Boot] [PATCHv2 1/3] armv8: fsl-layerscape: add i/d-cache enable function to enable_caches

2016-01-21 Thread Zhiqiang Hou
From: Hou Zhiqiang 

This function assume that the d-cache and MMU has been enabled earlier,
so it just created MMU table in main memory. But the assumption is not
always correct, for example, the early setup is done in EL3, while
enable_caches() is called when the PE has turned into another EL.

Define the function mmu_setup() for fsl-layerscape to cover the weak
one.

Signed-off-by: Hou Zhiqiang 
---
Tested on LS1043A RDB board

V2:
 - Replace patch [PATCH 1/3] ARMv8/layerscape: Add mmu_init API

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 6ea28ed..3147870 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -393,15 +393,21 @@ int arch_cpu_init(void)
return 0;
 }
 
+void mmu_setup(void)
+{
+   final_mmu_setup();
+}
+
 /*
- * This function is called from lib/board.c.
- * It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
- * There is no need to disable d-cache for this operation.
+ * This function is called from common/board_r.c.
+ * It recreates MMU table in main memory.
  */
 void enable_caches(void)
 {
-   final_mmu_setup();
+   mmu_setup();
__asm_invalidate_tlb_all();
+   icache_enable();
+   dcache_enable();
 }
 #endif
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCHv2 1/3] armv8: fsl-layerscape: add i/d-cache enable function to enable_caches

2016-01-21 Thread Zhiqiang Hou
From: Hou Zhiqiang 

This function assume that the d-cache and MMU has been enabled earlier,
so it just created MMU table in main memory. But the assumption is not
always correct, for example, the early setup is done in EL3, while
enable_caches() is called when the PE has turned into another EL.

Define the function mmu_setup() for fsl-layerscape to cover the weak
one.

Signed-off-by: Hou Zhiqiang 
---
Tested on LS1043A RDB board

V2:
 - Replace patch [PATCH 1/3] ARMv8/layerscape: Add mmu_init API

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 6ea28ed..3147870 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -393,15 +393,21 @@ int arch_cpu_init(void)
return 0;
 }
 
+void mmu_setup(void)
+{
+   final_mmu_setup();
+}
+
 /*
- * This function is called from lib/board.c.
- * It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
- * There is no need to disable d-cache for this operation.
+ * This function is called from common/board_r.c.
+ * It recreates MMU table in main memory.
  */
 void enable_caches(void)
 {
-   final_mmu_setup();
+   mmu_setup();
__asm_invalidate_tlb_all();
+   icache_enable();
+   dcache_enable();
 }
 #endif
 
-- 
2.1.0.27.g96db324

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[U-Boot] [v3] mmc: fsl_esdhc: set Abort command type for CMD12

2016-01-21 Thread Yangbo Lu
According to SD spec, CMD12, CMD52 for writing I/O abort in CCCR need
to be set an Abort command type when they are sent. So, we remove all
chip-specific #ifdefs and make it available for all platforms.

Signed-off-by: Yangbo Lu 
---
Changes for v2:
- Removed fix for T4160 because other patch had done that
Changes for v3:
- Removed all #ifdefs
---
 drivers/mmc/fsl_esdhc.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index c5054d6..f78dcc2 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -105,12 +105,9 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct 
mmc_data *data)
else if (cmd->resp_type & MMC_RSP_PRESENT)
xfertyp |= XFERTYP_RSPTYP_48;
 
-#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
-   defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LAYERSCAPE) || \
-   defined(CONFIG_PPC_T4160)
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
-#endif
+
return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 }
 
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH v2 5/7] enable chain of trust for ARM platforms

2016-01-21 Thread york sun
On 01/17/2016 01:42 AM, Aneesh Bansal wrote:
> Chain of Trust is enabled for ARM platforms (LS1021 and LS1043).
> In board_late_init(), fsl_setenv_chain_of_trust() is called which
> will perform the following:
> - If boot mode is non-secure, return (No Change)
> - If boot mode is secure, set the following environmet variables:
>bootdelay = 0 (To disable Boot Prompt)
>bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
> 
> Signed-off-by: Aneesh Bansal 
> ---
> Changes in v2:
> Defconfigs for Secure Boot Target are not removed
> 
>  arch/arm/cpu/armv8/fsl-layerscape/soc.c |  4 
>  board/freescale/common/Makefile |  1 +
>  board/freescale/common/fsl_chain_of_trust.c | 17 +
>  board/freescale/ls1021aqds/ls1021aqds.c |  4 
>  board/freescale/ls1021atwr/ls1021atwr.c |  4 
>  include/fsl_validate.h  |  2 ++
>  6 files changed, 32 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> index 23d6b73..2f92b55 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -12,6 +12,7 @@
>  #include 
>  #include 
>  #include 
> +#include 

Does this patch depend on other patches? It causes compiling error for fsl_sec.h
on ls2 boards.

error: #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined

York

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Re: [U-Boot] [Patch V5 2/4] spi: fsl_qspi: Fix qspi_op_rdid memcpy issue

2016-01-21 Thread Scott Wood
On 01/20/2016 09:43 PM, Gong Qianyu wrote:
> From: Gong Qianyu 
> 
> In current driver everytime we memcpy 4 bytes to the dest memory
> regardless of the remaining length.
> This patch adds checking the remaining length before memcpy.
> If the length is shorter than 4 bytes, memcpy the actual length of data
> to the dest memory.
> 
> Signed-off-by: Gong Qianyu 
> ---
> V2-V5:
>  - No change.
>  
>  drivers/spi/fsl_qspi.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
> index 38e5900..f178857 100644
> --- a/drivers/spi/fsl_qspi.c
> +++ b/drivers/spi/fsl_qspi.c
> @@ -500,7 +500,10 @@ static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 
> *rxbuf, u32 len)
>   if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
>   data = qspi_read32(priv->flags, >rbdr[i]);
>   data = qspi_endian_xchg(data);
> - memcpy(rxbuf, , 4);
> + if (size < 4)
> + memcpy(rxbuf, , size);
> + else
> + memcpy(rxbuf, , 4);

memcpy(rxbuf, , min(size, 4));

>   rxbuf++;
>   size -= 4;
>   i++;

size -= 4 even if size was < 4?

-Scott

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[U-Boot] [PATCH] fix lcd testpattern in 16bit mode

2016-01-21 Thread Andreas Neubacher
The testpattern of the lcd was only working in 8bit mode(2x3 tiles in
different colors). With this patch now 8bit and 16bit is supported.
In 16bit mode there are 2x4 tiles in different colors.
The number of LCD-colors is defined in the include/configs/.h


br,
Andy
From 925cfe21b270c9e36627d5c69634a6873111f442 Mon Sep 17 00:00:00 2001
From: Andreas Neubacher 
Date: Thu, 21 Jan 2016 13:06:32 +0100
Subject: [PATCH] fix the color testpattern in 16bit mode

Signed-off-by: Andreas Neubacher 
---
 common/lcd.c  | 17 -
 include/lcd.h | 11 +--
 2 files changed, 25 insertions(+), 3 deletions(-)

diff --git a/common/lcd.c b/common/lcd.c
index d29308a..09c8b5f 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -100,13 +100,24 @@ static void lcd_stub_puts(struct stdio_dev *dev, const char *s)
 /* Small utility to check that you got the colours right */
 #ifdef LCD_TEST_PATTERN
 
+#if LCD_BPP == LCD_COLOR8 
 #define	N_BLK_VERT	2
 #define	N_BLK_HOR	3
 
 static int test_colors[N_BLK_HOR * N_BLK_VERT] = {
 	CONSOLE_COLOR_RED,	CONSOLE_COLOR_GREEN,	CONSOLE_COLOR_YELLOW,
 	CONSOLE_COLOR_BLUE,	CONSOLE_COLOR_MAGENTA,	CONSOLE_COLOR_CYAN,
+}; /*LCD_BPP == LCD_COLOR8 */
+
+#elif LCD_BPP == LCD_COLOR16
+#define	N_BLK_VERT	2
+#define	N_BLK_HOR	4
+
+static int test_colors[N_BLK_HOR * N_BLK_VERT] = {
+	CONSOLE_COLOR_RED,	CONSOLE_COLOR_GREEN,	CONSOLE_COLOR_YELLOW,	CONSOLE_COLOR_BLUE,
+	CONSOLE_COLOR_MAGENTA,	CONSOLE_COLOR_CYAN,	CONSOLE_COLOR_GREY,	CONSOLE_COLOR_WHITE,
 };
+#endif /*LCD_BPP == LCD_COLOR16 */
 
 static void test_pattern(void)
 {
@@ -115,12 +126,15 @@ static void test_pattern(void)
 	ushort v_step = (v_max + N_BLK_VERT - 1) / N_BLK_VERT;
 	ushort h_step = (h_max + N_BLK_HOR  - 1) / N_BLK_HOR;
 	ushort v, h;
+#if LCD_BPP == LCD_COLOR8 
 	uchar *pix = (uchar *)lcd_base;
+#elif LCD_BPP == LCD_COLOR16
+	ushort *pix = (ushort *)lcd_base;
+#endif
 
 	printf("[LCD] Test Pattern: %d x %d [%d x %d]\n",
 		h_max, v_max, h_step, v_step);
 
-	/* WARNING: Code silently assumes 8bit/pixel */
 	for (v = 0; v < v_max; ++v) {
 		uchar iy = v / v_step;
 		for (h = 0; h < h_max; ++h) {
@@ -131,6 +145,7 @@ static void test_pattern(void)
 }
 #endif /* LCD_TEST_PATTERN */
 
+
 /*
  * With most lcd drivers the line length is set up
  * by calculating it from panel_info parameters. Some
diff --git a/include/lcd.h b/include/lcd.h
index 59202b7..b813fd0 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -193,8 +193,15 @@ void lcd_sync(void);
 #define CONSOLE_COLOR_WHITE	0x00ff	/* Must remain last / highest */
 #define NBYTES(bit_code)	(NBITS(bit_code) >> 3)
 #else /* 16bpp color definitions */
-#define CONSOLE_COLOR_BLACK	0x
-#define CONSOLE_COLOR_WHITE	0x		/* Must remain last / highest */
+# define CONSOLE_COLOR_BLACK	0x
+# define CONSOLE_COLOR_RED	0xF800
+# define CONSOLE_COLOR_GREEN	0x07E0
+# define CONSOLE_COLOR_YELLOW	0xFFE0
+# define CONSOLE_COLOR_BLUE	0x001F
+# define CONSOLE_COLOR_MAGENTA	0xF81F
+# define CONSOLE_COLOR_CYAN	0x07FF
+# define CONSOLE_COLOR_GREY	0xC618
+# define CONSOLE_COLOR_WHITE	0x		/* Must remain last / highest */
 #endif /* color definitions */
 
 #if LCD_BPP == LCD_COLOR16
-- 
1.9.1

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Re: [U-Boot] [Patch V5 1/4] spi: fsl_qspi: fix compile warning for 64-bit platform

2016-01-21 Thread Scott Wood
On 01/20/2016 09:42 PM, Gong Qianyu wrote:
> From: Gong Qianyu 
> 
> This patch fixes the following compile warning:
> drivers/spi/fsl_qspi.c: In function 'fsl_qspi_probe':
> drivers/spi/fsl_qspi.c:937:15:
>   warning: cast to pointer from integer of different size
>[-Wint-to-pointer-cast]
>   priv->regs = (struct fsl_qspi_regs *)plat->reg_base;
>^
> Just make the cast explicit.
> 
> Signed-off-by: Gong Qianyu 
> ---
> V5:
>  - Use uintptr_t instead of unsigned long.
> V4:
>  - Revise the commit message.
> V2-V3:
>  - No change.
> 
>  drivers/spi/fsl_qspi.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
> index 542b6cf..38e5900 100644
> --- a/drivers/spi/fsl_qspi.c
> +++ b/drivers/spi/fsl_qspi.c
> @@ -936,7 +936,7 @@ static int fsl_qspi_probe(struct udevice *bus)
>  
>   dm_spi_bus->max_hz = plat->speed_hz;
>  
> - priv->regs = (struct fsl_qspi_regs *)plat->reg_base;
> + priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
>   priv->flags = plat->flags;
>  
>   priv->speed_hz = plat->speed_hz;
> 

Use phys_to_virt().

-Scott

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[U-Boot] [PATCH 1/2] test/py: move find_ram_base() into u_boot_utils

2016-01-21 Thread Stephen Warren
From: Stephen Warren 

find_ram_base() is a shared utility function, not a core part of the
U-Boot console interaction.

Signed-off-by: Stephen Warren 
---
These two patches depend on my previous series starting with:
test/py: fix timeout to be absolute
and ending with:
test/py: add DFU test
---
 test/py/tests/test_md.py   |  5 +++--
 test/py/u_boot_console_base.py | 37 -
 test/py/u_boot_utils.py| 38 ++
 3 files changed, 41 insertions(+), 39 deletions(-)

diff --git a/test/py/tests/test_md.py b/test/py/tests/test_md.py
index 94603c7df609..32cce4f15c53 100644
--- a/test/py/tests/test_md.py
+++ b/test/py/tests/test_md.py
@@ -4,13 +4,14 @@
 # SPDX-License-Identifier: GPL-2.0
 
 import pytest
+import u_boot_utils
 
 @pytest.mark.buildconfigspec('cmd_memory')
 def test_md(u_boot_console):
 '''Test that md reads memory as expected, and that memory can be modified
 using the mw command.'''
 
-ram_base = u_boot_console.find_ram_base()
+ram_base = u_boot_utils.find_ram_base(u_boot_console)
 addr = '%08x' % ram_base
 val = 'a5f09876'
 expected_response = addr + ': ' + val
@@ -26,7 +27,7 @@ def test_md_repeat(u_boot_console):
 '''Test command repeat (via executing an empty command) operates correctly
 for "md"; the command must repeat and dump an incrementing address.'''
 
-ram_base = u_boot_console.find_ram_base()
+ram_base = u_boot_utils.find_ram_base(u_boot_console)
 addr_base = '%08x' % ram_base
 words = 0x10
 addr_repeat = '%08x' % (ram_base + (words * 4))
diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py
index 06f61f987180..51163bc0db68 100644
--- a/test/py/u_boot_console_base.py
+++ b/test/py/u_boot_console_base.py
@@ -86,7 +86,6 @@ class ConsoleBase(object):
 
 self.at_prompt = False
 self.at_prompt_logevt = None
-self.ram_base = None
 
 def close(self):
 '''Terminate the connection to the U-Boot console.
@@ -378,39 +377,3 @@ class ConsoleBase(object):
 '''
 
 return ConsoleDisableCheck(self, check_type)
-
-def find_ram_base(self):
-'''Find the running U-Boot's RAM location.
-
-Probe the running U-Boot to determine the address of the first bank
-of RAM. This is useful for tests that test reading/writing RAM, or
-load/save files that aren't associated with some standard address
-typically represented in an environment variable such as
-${kernel_addr_r}. The value is cached so that it only needs to be
-actively read once.
-
-Args:
-None.
-
-Returns:
-The address of U-Boot's first RAM bank, as an integer.
-'''
-
-if self.config.buildconfig.get('config_cmd_bdi', 'n') != 'y':
-pytest.skip('bdinfo command not supported')
-if self.ram_base == -1:
-pytest.skip('Previously failed to find RAM bank start')
-if self.ram_base is not None:
-return self.ram_base
-
-with self.log.section('find_ram_base'):
-response = self.run_command('bdinfo')
-for l in response.split('\n'):
-if '-> start' in l:
-self.ram_base = int(l.split('=')[1].strip(), 16)
-break
-if self.ram_base is None:
-self.ram_base = -1
-raise Exception('Failed to find RAM bank start in `bdinfo`')
-
-return self.ram_base
diff --git a/test/py/u_boot_utils.py b/test/py/u_boot_utils.py
index 539af618dbf2..522390a207ef 100644
--- a/test/py/u_boot_utils.py
+++ b/test/py/u_boot_utils.py
@@ -169,3 +169,41 @@ def run_and_log(u_boot_console, cmd, ignore_errors=False):
 runner = u_boot_console.log.get_runner(cmd[0], sys.stdout)
 runner.run(cmd, ignore_errors=ignore_errors)
 runner.close()
+
+ram_base = None
+def find_ram_base(u_boot_console):
+'''Find the running U-Boot's RAM location.
+
+Probe the running U-Boot to determine the address of the first bank
+of RAM. This is useful for tests that test reading/writing RAM, or
+load/save files that aren't associated with some standard address
+typically represented in an environment variable such as
+${kernel_addr_r}. The value is cached so that it only needs to be
+actively read once.
+
+Args:
+u_boot_console: A console connection to U-Boot.
+
+Returns:
+The address of U-Boot's first RAM bank, as an integer.
+'''
+
+global ram_base
+if u_boot_console.config.buildconfig.get('config_cmd_bdi', 'n') != 'y':
+pytest.skip('bdinfo command not supported')
+if ram_base == -1:
+pytest.skip('Previously failed to find RAM bank start')
+if ram_base is not None:
+return ram_base
+
+with u_boot_console.log.section('find_ram_base'):
+response = 

[U-Boot] [PATCH 2/2] test/py: add a networking test

2016-01-21 Thread Stephen Warren
From: Stephen Warren 

This tests:
- dhcp (if indicated by boardenv file).
- Static IP network setup (if provided by boardenv file).
- Ping.
- TFTP get.

Signed-off-by: Stephen Warren 
---
 test/py/tests/test_net.py | 153 ++
 1 file changed, 153 insertions(+)
 create mode 100644 test/py/tests/test_net.py

diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py
new file mode 100644
index ..c73854ea74e0
--- /dev/null
+++ b/test/py/tests/test_net.py
@@ -0,0 +1,153 @@
+# Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+# Test various network-related functionality, such as the dhcp, ping, and
+# tftpboot commands.
+
+import pytest
+import u_boot_utils
+
+'''
+Note: This test relies on boardenv_* containing configuration values to define
+which the network environment available for testing. Without this, this test
+will be automatically skipped.
+
+For example:
+
+# Any commands that need to be executed prior to testing,
+# to get the network hardware into an operational state.
+#
+# If no commands are required, this variable may be omitted, or set to an
+# empty list.
+env__net_pre_commands = [
+"usb start",
+]
+
+# True if a DHCP server is attached to the network, and should be tested.
+# If DHCP testing is not possible or desired, this variable may be omitted or
+# set to False.
+env__net_dhcp_server = True
+
+# A list of environment variables that should be set in order to configure a
+# static IP. If solely relying on DHCP, this variable may be omitted or set to
+# an empty list.
+env__net_static_env_vars = [
+("ipaddr", "10.0.0.100"),
+("netmask", "255.255.255.0"),
+("serverip", "10.0.0.1"),
+]
+
+# Details regarding a file that may be read from a TFTP server. This variable
+# may be omitted or set to None if TFTP testing is not possible or desired.
+env__net_tftp_readable_file = {
+"fn": "ubtest-readable.bin",
+"size": 5058624,
+"crc32": "c2244b26",
+}
+'''
+
+net_set_up = False
+
+def test_net_pre_commands(u_boot_console):
+'''Execute any commands required to enable network hardware.
+
+These commands are provided by the boardenv_* file; see the comment at the
+beginning of this file.
+'''
+
+cmds = u_boot_console.config.env.get('env__net_pre_commands', None)
+if not cmds:
+pytest.skip('No network pre-commands defined')
+
+for cmd in cmds:
+u_boot_console.run_command(cmd)
+
+@pytest.mark.buildconfigspec('cmd_dhcp')
+def test_net_dhcp(u_boot_console):
+'''Test the dhcp command.
+
+The boardenv_* file may be used to enable/disable this test; see the
+comment at the beginning of this file.
+'''
+
+test_dhcp = u_boot_console.config.env.get('env__net_dhcp_server', False)
+if not test_dhcp:
+pytest.skip('No DHCP server available')
+
+u_boot_console.run_command('setenv autoload no')
+output = u_boot_console.run_command('dhcp')
+assert 'DHCP client bound to address ' in output
+
+global net_set_up
+net_set_up = True
+
+@pytest.mark.buildconfigspec('net')
+def test_net_setup_static(u_boot_console):
+'''Set up a static IP configuration.
+
+The configuration is provided by the boardenv_* file; see the comment at
+the beginning of this file.
+'''
+
+env_vars = u_boot_console.config.env.get('env__net_static_env_vars', None)
+if not env_vars:
+pytest.skip('No static network configuration is defined')
+
+for (var, val) in env_vars:
+u_boot_console.run_command('setenv %s %s' % (var, val))
+
+global net_set_up
+net_set_up = True
+
+@pytest.mark.buildconfigspec('cmd_ping')
+def test_net_ping(u_boot_console):
+'''Test the ping command.
+
+The $serverip (as set up by either test_net_dhcp or test_net_setup_static)
+is pinged. The test validates that the host is alive, as reported by the
+ping command's output.
+'''
+
+if not net_set_up:
+pytest.skip("Network not initialized")
+
+output = u_boot_console.run_command('ping $serverip')
+assert 'is alive' in output
+
+@pytest.mark.buildconfigspec('cmd_net')
+def test_net_tftpboot(u_boot_console):
+'''Test the tftpboot command.
+
+A file is downloaded from the TFTP server, its size and optionally its
+CRC32 are validated.
+
+The details of the file to download are provided by the boardenv_* file;
+see the comment at the beginning of this file.
+'''
+
+if not net_set_up:
+pytest.skip("Network not initialized")
+
+f = u_boot_console.config.env.get('env__net_tftp_readable_file', None)
+if not f:
+pytest.skip('No TFTP readable file to read')
+
+addr = u_boot_utils.find_ram_base(u_boot_console)
+fn = f['fn']
+output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
+expected_text = 'Bytes transferred = '
+sz = f.get('size', None)
+

Re: [U-Boot] Please pull u-boot-dm

2016-01-21 Thread Tom Rini
On Thu, Jan 21, 2016 at 08:30:36AM -0700, Simon Glass wrote:

> Hi Tom,
> 
> This includes the lpuart and TI driver-model model conversion, clock
> improvements, the new Python-based test infrastructure and a
> video/console uclass initially implemented for sandbox.
> 
> 
> The following changes since commit 57e5ecaf755d5301cd33683788e4b8432938bbbe:
> 
>   iocon / bamboo: Drop CONFIG_SYS_LONGHELP (2016-01-20 15:25:00 -0500)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-dm.git
> 
> for you to fetch changes up to 747440d0fa95f2205a8fcef49b6c7845700b6246:
> 
>   dm: video: test: Test that bitmap display works correctly
> (2016-01-20 19:10:16 -0700)
> 

Applied to u-boot/master, thanks!

I've also tossed -S into my buildman summary of everything build
testing.  Some high/low-lights (and I'm only singling out -dm since I
added it just now):
   aarch64: (for 30/30 boards)  all -56.1  bss +1.6  rodata -9.1  text -48.7 
...
   sandbox: (for 1/1 boards)  all +16120.0  bss -128.0  data +5264.0  rodata 
-5648.0  text +16632.0 
...
   arm: (for 486/491 boards)  all +74.3  bss -1.4  data +8.1  rodata +8.3  
spl/u-boot-spl:all -0.3  spl/u-boot-spl:bss +0.0  spl/u-boot-spl:data +0.0  
spl/u-boot-spl:rodata -1.1  spl/u-boot-spl:text +0.7  text +59.3 
ls1021atwr_nor :  all +12350  bss -100  data +624  rodata +2986  
text +8840 
ls1021atwr_nor_lpuart:  all +12300  bss +60  data +572  rodata 
+2780  text + 
orangepi_pc:  all +8310  bss +36  data +1340  rodata +398  
spl/u-boot-spl:all +144  spl/u-boot-spl:data +8  spl/u-boot-spl:text +136  text 
+6536 


Everything else was either noise in growth or reduction.  PowerPC lost
100 bytes nearly everywhere.

-- 
Tom


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[U-Boot] [PATCH] pci: restore initialization for DM_PCI

2016-01-21 Thread Stephen Warren
From: Stephen Warren 

PCI controllers should be enumerated at startup so that PCI devices
such as Ethernet controllers are available at startup. Fix board_init_r()
not to skip calling pci_init() when CONFIG_DM_PCI is defined, and provide
an implementation of pci_init() for the DM case.

Fixes: 96350f729c42 ("dm: tegra: net: Convert tegra boards to driver model
for Ethernet")
Signed-off-by: Stephen Warren 
---
I'm not sure if relying on the side-effects of calling
uclass_{first,ext}_device is the correct approach; is there a more explicit
way to probe all PCI controllers?

Arguably, perhaps we should introduce a "pci start" command instead of
this change to be consistent with e.g. USB. However, that would be a
regression relative to earlier versions of U-Boot.
---
 common/board_r.c |  2 --
 drivers/pci/pci-uclass.c | 15 +++
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/common/board_r.c b/common/board_r.c
index 75ee43e2d76e..e5029aff1e96 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -249,9 +249,7 @@ static int initr_unlock_ram_in_cache(void)
 #ifdef CONFIG_PCI
 static int initr_pci(void)
 {
-#ifndef CONFIG_DM_PCI
pci_init();
-#endif
 
return 0;
 }
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 685df9d274e4..f51f08289d66 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1247,3 +1247,18 @@ U_BOOT_DRIVER(pci_generic_drv) = {
.id = UCLASS_PCI_GENERIC,
.of_match   = pci_generic_ids,
 };
+
+void pci_init(void)
+{
+   struct udevice *bus;
+
+   /*
+* Enumerate all known controller devices. Enumeration has the side-
+* effect of probing them, so PCIe devices will be enumerated too.
+*/
+   for (uclass_first_device(UCLASS_PCI, );
+bus;
+uclass_next_device()) {
+   ;
+   }
+}
-- 
2.7.0

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[U-Boot] [PATCH v2 2/3] tpm: st33zp24: Add tpm st33zp24 support with i2c

2016-01-21 Thread Christophe Ricard
Add support for TPM ST33ZP24 family with i2c.

For i2c we are relying only on DM_I2C.

Reviewed-by: Simon Glass 
Signed-off-by: Christophe Ricard 
---

Changes in v2:
- Adding Reviewed-by: Simon Glass 

 README |   7 +
 drivers/tpm/Kconfig|   9 +
 drivers/tpm/Makefile   |   1 +
 drivers/tpm/tpm_tis_st33zp24_i2c.c | 543 +
 4 files changed, 560 insertions(+)
 create mode 100644 drivers/tpm/tpm_tis_st33zp24_i2c.c

diff --git a/README b/README
index 9423c34..e7c41c3 100644
--- a/README
+++ b/README
@@ -1432,6 +1432,13 @@ The following options need to be configured:
CONFIG_TPM_TIS_I2C_BURST_LIMITATION
Define the burst count bytes upper limit
 
+   CONFIG_TPM_ST33ZP24
+   Support for STMicroelectronics TPM devices. Requires DM_TPM 
support.
+
+   CONFIG_TPM_ST33ZP24_I2C
+   Support for STMicroelectronics ST33ZP24 I2C devices.
+   Requires TPM_ST33ZP24 and I2C.
+
CONFIG_TPM_ATMEL_TWI
Support for Atmel TWI TPM device. Requires I2C support.
 
diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig
index 5a75f85..9432160 100644
--- a/drivers/tpm/Kconfig
+++ b/drivers/tpm/Kconfig
@@ -64,4 +64,13 @@ config TPM_AUTH_SESSIONS
  TPM_LoadKey2 and TPM_GetPubKey are provided. Both features are
  available using the 'tpm' command, too.
 
+config TPM_ST33ZP24_I2C
+   bool "STMicroelectronics ST33ZP24 I2C TPM"
+   depends on TPM && DM_I2C
+   ---help---
+ This driver supports STMicroelectronics TPM devices connected on the 
I2C bus.
+ The usual tpm operations and the 'tpm' command can be used to talk
+ to the device using the standard TPM Interface Specification (TIS)
+ protocol
+
 endmenu
diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile
index 1d49e95..cb066d7 100644
--- a/drivers/tpm/Makefile
+++ b/drivers/tpm/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_TPM_ATMEL_TWI) += tpm_atmel_twi.o
 obj-$(CONFIG_TPM_TIS_INFINEON) += tpm_tis_infineon.o
 obj-$(CONFIG_TPM_TIS_LPC) += tpm_tis_lpc.o
 obj-$(CONFIG_TPM_TIS_SANDBOX) += tpm_tis_sandbox.o
+obj-$(CONFIG_TPM_ST33ZP24_I2C) += tpm_tis_st33zp24_i2c.o
diff --git a/drivers/tpm/tpm_tis_st33zp24_i2c.c 
b/drivers/tpm/tpm_tis_st33zp24_i2c.c
new file mode 100644
index 000..9e4829f
--- /dev/null
+++ b/drivers/tpm/tpm_tis_st33zp24_i2c.c
@@ -0,0 +1,543 @@
+/*
+ * STMicroelectronics TPM ST33ZP24 I2C UBOOT driver
+ *
+ * Copyright (C) 2016 STMicroelectronics
+ *
+ * Description: Device driver for ST33ZP24 I2C TPM TCG.
+ *
+ * This device driver implements the TPM interface as defined in
+ * the TCG TPM Interface Spec version 1.21, revision 1.0 and the
+ * STMicroelectronics Protocol Stack Specification version 1.2.0.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "tpm_tis.h"
+#include "tpm_internal.h"
+
+#define TPM_ACCESS 0x0
+#define TPM_STS0x18
+#define TPM_DATA_FIFO  0x24
+
+#define LOCALITY0  0
+
+#define TPM_DUMMY_BYTE 0xAA
+#define TPM_ST33ZP24_I2C_SLAVE_ADDR0x13
+
+#define TPM_WRITE_DIRECTION 0x80
+
+/*
+ * st33zp24_i2c_write8_reg
+ * Send byte to the TIS register according to the ST33ZP24 I2C protocol.
+ * @param: tpm_register, the tpm tis register where the data should be written
+ * @param: tpm_data, the tpm_data to write inside the tpm_register
+ * @param: tpm_size, The length of the data
+ * @return: Number of byte written successfully else an error code.
+ */
+static int st33zp24_i2c_write8_reg(struct udevice *dev, u8 tpm_register,
+  const u8 *tpm_data, size_t tpm_size)
+{
+   struct tpm_chip_priv *chip_priv = dev_get_uclass_priv(dev);
+
+   chip_priv->buf[0] = tpm_register;
+   memcpy(chip_priv->buf + 1, tpm_data, tpm_size);
+
+   return dm_i2c_write(dev, 0, chip_priv->buf, tpm_size + 1);
+}
+
+/*
+* st33zp24_i2c_read8_reg
+* Recv byte from the TIS register according to the ST33ZP24 I2C protocol.
+* @param: tpm_register, the tpm tis register where the data should be read
+* @param: tpm_data, the TPM response
+* @param: tpm_size, tpm TPM response size to read.
+* @return: Number of byte read successfully else an error code.
+*/
+static int st33zp24_i2c_read8_reg(struct udevice *dev, u8 tpm_register,
+ u8 *tpm_data, size_t tpm_size)
+{
+   int status;
+   u8 data;
+
+   data = TPM_DUMMY_BYTE;
+   status = st33zp24_i2c_write8_reg(dev, tpm_register, , 1);
+   if (status < 0)
+   return status;
+
+   return dm_i2c_read(dev, 0, tpm_data, tpm_size);
+}
+
+/*
+ * st33zp24_i2c_write
+ * Send 

[U-Boot] [PATCH v2 1/3] tpm: Rename tpm_tis_infineon.h to tpm_tis.h and move infineon specific stuff in tpm_infineon.c

2016-01-21 Thread Christophe Ricard
I2C protocol is not standardize for TPM 1.2.
TIS prococol is define by the Trusted Computing Group and potentially
available on several TPMs.

tpm_tis_infineon.h header is not generic enough.

Rename tpm_tis_infineon.h to tpm_tis.h and move infineon specific
defines/variables to tpm_tis_infineon.c

Reviewed-by: Simon Glass 
Signed-off-by: Christophe Ricard 
---

Changes in v2:
- Adding Reviewed-by: Simon Glass 

 drivers/tpm/{tpm_tis_infineon.h => tpm_tis.h} | 17 +
 drivers/tpm/tpm_tis_infineon.c| 17 -
 2 files changed, 17 insertions(+), 17 deletions(-)
 rename drivers/tpm/{tpm_tis_infineon.h => tpm_tis.h} (86%)

diff --git a/drivers/tpm/tpm_tis_infineon.h b/drivers/tpm/tpm_tis.h
similarity index 86%
rename from drivers/tpm/tpm_tis_infineon.h
rename to drivers/tpm/tpm_tis.h
index 3b510d1..25b152b 100644
--- a/drivers/tpm/tpm_tis_infineon.h
+++ b/drivers/tpm/tpm_tis.h
@@ -37,18 +37,12 @@ enum tpm_timeout {
 #define TPM_RSP_SIZE_BYTE  2
 #define TPM_RSP_RC_BYTE6
 
-enum i2c_chip_type {
-   SLB9635,
-   SLB9645,
-   UNKNOWN,
-};
-
 struct tpm_chip {
int is_open;
int locality;
u32 vend_dev;
unsigned long timeout_a, timeout_b, timeout_c, timeout_d;  /* msec */
-   enum i2c_chip_type chip_type;
+   ulong chip_type;
 };
 
 struct tpm_input_header {
@@ -134,13 +128,4 @@ enum tis_status {
TPM_STS_DATA_EXPECT = 0x08,
 };
 
-/* expected value for DIDVID register */
-#define TPM_TIS_I2C_DID_VID_9635 0x000b15d1L
-#define TPM_TIS_I2C_DID_VID_9645 0x001a15d1L
-
-#defineTPM_ACCESS(l)   (0x | ((l) << 4))
-#defineTPM_STS(l)  (0x0001 | ((l) << 4))
-#defineTPM_DATA_FIFO(l)(0x0005 | ((l) << 4))
-#defineTPM_DID_VID(l)  (0x0006 | ((l) << 4))
-
 #endif
diff --git a/drivers/tpm/tpm_tis_infineon.c b/drivers/tpm/tpm_tis_infineon.c
index f57c328..a4b6741 100644
--- a/drivers/tpm/tpm_tis_infineon.c
+++ b/drivers/tpm/tpm_tis_infineon.c
@@ -30,17 +30,32 @@
 #include 
 #include 
 
-#include "tpm_tis_infineon.h"
+#include "tpm_tis.h"
 #include "tpm_internal.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+enum i2c_chip_type {
+   SLB9635,
+   SLB9645,
+   UNKNOWN,
+};
+
+/* expected value for DIDVID register */
+#define TPM_TIS_I2C_DID_VID_9635 0x000b15d1L
+#define TPM_TIS_I2C_DID_VID_9645 0x001a15d1L
+
 static const char * const chip_name[] = {
[SLB9635] = "slb9635tt",
[SLB9645] = "slb9645tt",
[UNKNOWN] = "unknown/fallback to slb9635",
 };
 
+#defineTPM_ACCESS(l)   (0x | ((l) << 4))
+#defineTPM_STS(l)  (0x0001 | ((l) << 4))
+#defineTPM_DATA_FIFO(l)(0x0005 | ((l) << 4))
+#defineTPM_DID_VID(l)  (0x0006 | ((l) << 4))
+
 /*
  * tpm_tis_i2c_read() - read from TPM register
  * @addr: register address to read from
-- 
2.5.0

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[U-Boot] [PATCH v2 0/3] Add support for st33zp24 i2c and spi TPMs

2016-01-21 Thread Christophe Ricard

Hi Simon,

After a first tentative in August 2015:
http://lists.denx.de/pipermail/u-boot/2015-August/222596.html

I finally found some spare time for a new round to send a new version patch
version bringing support for ST33ZP24 TPM 1.2 with i2c and spi support.

I have been able to follow all your guidance from my previous tentative
and got able to convert omap24xx_i2c and omap3_spi drivers to DM.
I will send them in a separate patchset for your review.

Best Regards
Christophe


Changes in v2:
- Adding Reviewed-by: Simon Glass 

Christophe Ricard (3):
  tpm: Rename tpm_tis_infineon.h to tpm_tis.h and move infineon specific
stuff in tpm_infineon.c
  tpm: st33zp24: Add tpm st33zp24 support with i2c
  tpm: st33zp24: Add tpm st33zp24 spi support

 README|  11 +
 drivers/tpm/Kconfig   |  18 +
 drivers/tpm/Makefile  |   2 +
 drivers/tpm/{tpm_tis_infineon.h => tpm_tis.h} |  17 +-
 drivers/tpm/tpm_tis_infineon.c|  17 +-
 drivers/tpm/tpm_tis_st33zp24_i2c.c| 543 +
 drivers/tpm/tpm_tis_st33zp24_spi.c| 672 ++
 7 files changed, 1263 insertions(+), 17 deletions(-)
 rename drivers/tpm/{tpm_tis_infineon.h => tpm_tis.h} (86%)
 create mode 100644 drivers/tpm/tpm_tis_st33zp24_i2c.c
 create mode 100644 drivers/tpm/tpm_tis_st33zp24_spi.c

-- 
2.5.0

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[U-Boot] [PATCH v2 2/2] tpm: tpm_tis_lpc: fix typo

2016-01-21 Thread Christophe Ricard
TPM_TIS_LPC is connected to the LPC bus, not I2C.

Reviewed-by: Simon Glass 
Signed-off-by: Christophe Ricard 
---

Changes in v2:
- Adding Reviewed-by: Simon Glass 

 drivers/tpm/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig
index 31b35f7..5a75f85 100644
--- a/drivers/tpm/Kconfig
+++ b/drivers/tpm/Kconfig
@@ -50,7 +50,7 @@ config TPM_TIS_LPC
bool "Enable support for Infineon SLB9635/45 TPMs on LPC"
depends on TPM && X86
help
- This driver supports Infineon TPM devices connected on the I2C bus.
+ This driver supports Infineon TPM devices connected on the LPC bus.
  The usual tpm operations and the 'tpm' command can be used to talk
  to the device using the standard TPM Interface Specification (TIS)
  protocol
-- 
2.5.0

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[U-Boot] [PATCH v2 0/2] TPM minor fixes

2016-01-21 Thread Christophe Ricard

Hi Simon,

Please find in this serie one bug fix and a typo cleanup.
This series is only adding mention to your review


Best Regards
Christophe


Changes in v2:
- Adding Reviewed-by: Simon Glass 

Christophe Ricard (2):
  tpm: Fix fault in case CONFIG_DM_TPM is set without any TPM
  tpm: tpm_tis_lpc: fix typo

 common/cmd_tpm.c| 2 +-
 drivers/tpm/Kconfig | 2 +-
 lib/tpm.c   | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

-- 
2.5.0

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[U-Boot] [PATCH v2 1/2] tpm: Fix fault in case CONFIG_DM_TPM is set without any TPM

2016-01-21 Thread Christophe Ricard
In case CONFIG_DM_TPM was set without any TPM chipset configured a fault
was generated (NULL pointer access).

Reviewed-by: Simon Glass 
Signed-off-by: Christophe Ricard 
---

Changes in v2:
- Adding Reviewed-by: Simon Glass 

 common/cmd_tpm.c | 2 +-
 lib/tpm.c| 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/common/cmd_tpm.c b/common/cmd_tpm.c
index add6bfb..6edf3e9 100644
--- a/common/cmd_tpm.c
+++ b/common/cmd_tpm.c
@@ -448,7 +448,7 @@ static int get_tpm(struct udevice **devp)
int rc;
 
rc = uclass_first_device(UCLASS_TPM, devp);
-   if (rc) {
+   if (rc || !*devp) {
printf("Could not find TPM (ret=%d)\n", rc);
return CMD_RET_FAILURE;
}
diff --git a/lib/tpm.c b/lib/tpm.c
index 8a62216..f428d45 100644
--- a/lib/tpm.c
+++ b/lib/tpm.c
@@ -262,7 +262,7 @@ int tpm_init(void)
struct udevice *dev;
 
err = uclass_first_device(UCLASS_TPM, );
-   if (err)
+   if (err || !dev)
return err;
return tpm_open(dev);
 }
-- 
2.5.0

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[U-Boot] [PATCH v2 3/3] tpm: st33zp24: Add tpm st33zp24 spi support

2016-01-21 Thread Christophe Ricard
Add support for TPM ST33ZP24 spi.

The ST33ZP24 does have a spi interface.
The transport protocol is proprietary.

For spi we are relying only on DM_SPI.

Reviewed-by: Simon Glass 
Signed-off-by: Christophe Ricard 
---

Changes in v2:
- Adding Reviewed-by: Simon Glass 

 README |   4 +
 drivers/tpm/Kconfig|   9 +
 drivers/tpm/Makefile   |   1 +
 drivers/tpm/tpm_tis_st33zp24_spi.c | 672 +
 4 files changed, 686 insertions(+)
 create mode 100644 drivers/tpm/tpm_tis_st33zp24_spi.c

diff --git a/README b/README
index e7c41c3..dc2917c 100644
--- a/README
+++ b/README
@@ -1439,6 +1439,10 @@ The following options need to be configured:
Support for STMicroelectronics ST33ZP24 I2C devices.
Requires TPM_ST33ZP24 and I2C.
 
+   CONFIG_TPM_ST33ZP24_SPI
+   Support for STMicroelectronics ST33ZP24 SPI devices.
+   Requires TPM_ST33ZP24 and SPI.
+
CONFIG_TPM_ATMEL_TWI
Support for Atmel TWI TPM device. Requires I2C support.
 
diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig
index 9432160..9a7b7f5 100644
--- a/drivers/tpm/Kconfig
+++ b/drivers/tpm/Kconfig
@@ -73,4 +73,13 @@ config TPM_ST33ZP24_I2C
  to the device using the standard TPM Interface Specification (TIS)
  protocol
 
+config TPM_ST33ZP24_SPI
+   bool "STMicroelectronics ST33ZP24 SPI TPM"
+   depends on TPM && DM_SPI
+   ---help---
+ This driver supports STMicroelectronics TPM devices connected on the 
SPI bus.
+ The usual tpm operations and the 'tpm' command can be used to talk
+ to the device using the standard TPM Interface Specification (TIS)
+ protocol
+
 endmenu
diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile
index cb066d7..c42a93f 100644
--- a/drivers/tpm/Makefile
+++ b/drivers/tpm/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_TPM_TIS_INFINEON) += tpm_tis_infineon.o
 obj-$(CONFIG_TPM_TIS_LPC) += tpm_tis_lpc.o
 obj-$(CONFIG_TPM_TIS_SANDBOX) += tpm_tis_sandbox.o
 obj-$(CONFIG_TPM_ST33ZP24_I2C) += tpm_tis_st33zp24_i2c.o
+obj-$(CONFIG_TPM_ST33ZP24_SPI) += tpm_tis_st33zp24_spi.o
diff --git a/drivers/tpm/tpm_tis_st33zp24_spi.c 
b/drivers/tpm/tpm_tis_st33zp24_spi.c
new file mode 100644
index 000..417bbf1
--- /dev/null
+++ b/drivers/tpm/tpm_tis_st33zp24_spi.c
@@ -0,0 +1,672 @@
+/*
+ * STMicroelectronics TPM ST33ZP24 SPI UBOOT driver
+ *
+ * Copyright (C) 2016 STMicroelectronics
+ *
+ * Description: Device driver for ST33ZP24 SPI TPM TCG.
+ *
+ * This device driver implements the TPM interface as defined in
+ * the TCG TPM Interface Spec version 1.21, revision 1.0 and the
+ * STMicroelectronics Protocol Stack Specification version 1.2.0.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "tpm_tis.h"
+#include "tpm_internal.h"
+
+#define TPM_ACCESS 0x0
+#define TPM_STS0x18
+#define TPM_DATA_FIFO  0x24
+
+#define LOCALITY0  0
+
+#define TPM_DATA_FIFO  0x24
+#define TPM_INTF_CAPABILITY0x14
+
+#define TPM_DUMMY_BYTE 0x00
+#define TPM_WRITE_DIRECTION0x80
+
+#define MAX_SPI_LATENCY15
+#define LOCALITY0  0
+
+#define ST33ZP24_OK0x5A
+#define ST33ZP24_UNDEFINED_ERR 0x80
+#define ST33ZP24_BADLOCALITY   0x81
+#define ST33ZP24_TISREGISTER_UKNOWN0x82
+#define ST33ZP24_LOCALITY_NOT_ACTIVATED0x83
+#define ST33ZP24_HASH_END_BEFORE_HASH_START0x84
+#define ST33ZP24_BAD_COMMAND_ORDER 0x85
+#define ST33ZP24_INCORECT_RECEIVED_LENGTH  0x86
+#define ST33ZP24_TPM_FIFO_OVERFLOW 0x89
+#define ST33ZP24_UNEXPECTED_READ_FIFO  0x8A
+#define ST33ZP24_UNEXPECTED_WRITE_FIFO 0x8B
+#define ST33ZP24_CMDRDY_SET_WHEN_PROCESSING_HASH_END   0x90
+#define ST33ZP24_DUMMY_BYTES   0x00
+
+/*
+ * TPM command can be up to 2048 byte, A TPM response can be up to
+ * 1024 byte.
+ * Between command and response, there are latency byte (up to 15
+ * usually on st33zp24 2 are enough).
+ *
+ * Overall when sending a command and expecting an answer we need if
+ * worst case:
+ * 2048 (for the TPM command) + 1024 (for the TPM answer).  We need
+ * some latency byte before the answer is available (max 15).
+ * We have 2048 + 1024 + 15.
+ */
+#define ST33ZP24_SPI_BUFFER_SIZE (TPM_BUFSIZE + (TPM_BUFSIZE / 2) +\
+ MAX_SPI_LATENCY)
+
+struct st33zp24_spi_phy {
+ 

Re: [U-Boot] [PATCH 8/9] ARM: ARMv7: PSCI: ls102xa: add psci functions implemention

2016-01-21 Thread Scott Wood
On Tue, 2016-01-19 at 06:28 +, Dongsheng Wang wrote:
> Hi Scott,
> 
> > On Mon, 2016-01-18 at 12:27 +0800, Dongsheng Wang wrote:
> > > From: Wang Dongsheng 
> > > 
> > > Based on PSCI v1.0, implement interface for ls102xa SoC:
> > > psci_version,
> > > psci_features,
> > > psci_cpu_suspend,
> > > psci_affinity_info,
> > > psci_system_reset,
> > > psci_system_off.
> > > 
> > > Tested on LS1021aQDS, LS1021aTWR.
> > > 
> > > Signed-off-by: Wang Dongsheng 
> > > ---
> > >  arch/arm/cpu/armv7/ls102xa/psci.S  | 110
> > > +++--
> > >  arch/arm/include/asm/arch-ls102xa/config.h |   1 +
> > >  board/freescale/ls1021aqds/Makefile|   1 +
> > >  board/freescale/ls1021aqds/psci.S  |  36 ++
> > >  board/freescale/ls1021atwr/Makefile|   1 +
> > >  board/freescale/ls1021atwr/psci.S  |  28 
> > >  include/configs/ls1021aqds.h   |   3 +
> > >  include/configs/ls1021atwr.h   |   1 +
> > >  8 files changed, 177 insertions(+), 4 deletions(-)  create mode
> > > 100644 board/freescale/ls1021aqds/psci.S  create mode 100644
> > > board/freescale/ls1021atwr/psci.S
> > > 
> > > diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S
> > > b/arch/arm/cpu/armv7/ls102xa/psci.S
> > > index 3091362..bfc908e 100644
> > > --- a/arch/arm/cpu/armv7/ls102xa/psci.S
> > > +++ b/arch/arm/cpu/armv7/ls102xa/psci.S
> > > @@ -12,19 +12,72 @@
> > >  #include   #include 
> > > 
> > > +#define RCPM_TWAITSR 0x04C
> > > +
> > >  #define SCFG_CORE0_SFT_RST  0x130
> > >  #define SCFG_CORESRENCR 0x204
> > > 
> > > -#define DCFG_CCSR_BRR   0x0E4
> > > -#define DCFG_CCSR_SCRATCHRW10x200
> > > +#define DCFG_CCSR_RSTCR  0x0B0
> > > +#define DCFG_CCSR_RSTCR_RESET_REQ0x2
> > > +#define DCFG_CCSR_BRR0x0E4
> > > +#define DCFG_CCSR_SCRATCHRW1 0x200
> > > +
> > > +#define PSCI_FN_PSCI_VERSION_FEATURE_MASK0x0
> > > +#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK 0x0
> > > +#define PSCI_FN_CPU_OFF_FEATURE_MASK 0x0
> > > +#define PSCI_FN_CPU_ON_FEATURE_MASK  0x0
> > > +#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK   0x0
> > > +#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK  0x0
> > > +#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK0x0
> > > 
> > >   .pushsection ._secure.text, "ax"
> > > 
> > >   .arch_extension sec
> > > 
> > > + .align  5
> > > +
> > >  #define  ONE_MS  (GENERIC_TIMER_CLK / 1000)
> > >  #define  RESET_WAIT  (30 * ONE_MS)
> > > 
> > > +.globl   psci_version
> > > +psci_version:
> > > + movwr0, #0
> > > + movtr0, #1
> > > +
> > > + bx  lr
> > > +
> > > +_ls102x_psci_supported_table:
> > > + .word   PSCI_FN_PSCI_VERSION
> > > + .word   PSCI_FN_PSCI_VERSION_FEATURE_MASK
> > > + .word   PSCI_FN_CPU_SUSPEND
> > > + .word   PSCI_FN_CPU_SUSPEND_FEATURE_MASK
> > > + .word   PSCI_FN_CPU_OFF
> > > + .word   PSCI_FN_CPU_OFF_FEATURE_MASK
> > > + .word   PSCI_FN_CPU_ON
> > > + .word   PSCI_FN_CPU_ON_FEATURE_MASK
> > > + .word   PSCI_FN_AFFINITY_INFO
> > > + .word   PSCI_FN_AFFINITY_INFO_FEATURE_MASK
> > > + .word   PSCI_FN_SYSTEM_OFF
> > > + .word   PSCI_FN_SYSTEM_OFF_FEATURE_MASK
> > > + .word   PSCI_FN_SYSTEM_RESET
> > > + .word   PSCI_FN_SYSTEM_RESET_FEATURE_MASK
> > > + .word   0
> > > + .word   PSCI_RET_NOT_SUPPORTED
> > 
> > Can you use the main _psci_table instead of duplicating it?
> > 
> 
> The main table does not apply here. Because this table shows what is
> supported in our platform.

How does that set differ from what's in the main table?

> And this table also contains the sub-feature mask of PSCI functions.

...which is always zero.  As of PSCI 1.0 there's only one function that
supports subfeatures, and you could put an explicit check in for that if it
ever needs a non-zero value.

> > > +
> > > +.globl   psci_features
> > > +psci_features:
> > > + adr r2, _ls102x_psci_supported_table
> > > +1:   ldr r3, [r2]
> > > + cmp r3, #0
> > > + beq out_psci_features
> > > + cmp r1, r3
> > > + addne   r2, r2, #8
> > > + bne 1b
> > 
> > Why are you adding 8 here?
> > 
> 
> +4 is the sub-feature mask of the PSCI function. So we need to +8 to jump to
> next PSCI function.
> .word PSCI_FN_PSCI_VERSION
> .word PSCI_FN_PSCI_VERSION_FEATURE_MASK
>
> > > +
> > > +out_psci_features:
> > > + ldr r0, [r2, #4]
> > > + bx  lr
> > 
> > If you find a match, you're supposed to return zero, not the next function
> > id in
> > the table.
> > How did you test this?  There should really be a test suite for runtime
> > services
> > such as this, especially when trying to comply with a standard.
> 
> I think maybe you missed something about this code. The return value is
> PSCI_FN_PSCI_XX_FEATURE_MASK,
> not return next function ID.

Yes, I misread the table and missed the masks.  But see above about them being
unnecessary.

In any case, a test suite 

Re: [U-Boot] [PATCH 2/2] armv8/fsl-layerscape: fdt: add fixup for fman

2016-01-21 Thread Scott Wood
On 01/21/2016 01:09 AM, Gong Qianyu wrote:
> 1.Add fixup for fman clock.
> 2.Add fdt_fixup_fman_firmware() to insert the Fman ucode firmware into
> the device tree.
> 
> Signed-off-by: Gong Qianyu 
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 121 
> 
>  1 file changed, 121 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
> b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> index 2a3e621..c93aa18 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
> @@ -19,6 +19,7 @@
>  #ifdef CONFIG_MP
>  #include 
>  #endif
> +#include "../../../../../drivers/qe/qe.h" /* For struct qe_firmware 
> */

Move the header to include/ if it's not private to drivers/qe.

Better yet, don't duplicate these fixups.  Move the existing code out of
arch/powerpc.

-Scott

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Re: [U-Boot] [Patch V3 3/3] armv8/ls1043aqds: add QSPI boot support

2016-01-21 Thread Scott Wood
On Thu, 2016-01-14 at 04:26 +, Qianyu Gong wrote:
> > -Original Message-
> > From: Scott Wood [mailto:o...@buserror.net]
> > Sent: Thursday, January 14, 2016 8:21 AM
> > To: Qianyu Gong ; u-boot@lists.denx.de
> > Cc: b07...@freescale.com; b48...@freescale.com;
> > wenbin.s...@freescale.com; Mingkai Hu 
> > Subject: Re: [U-Boot] [Patch V3 3/3] armv8/ls1043aqds: add QSPI boot
> > support
> > 
> > On Tue, 2016-01-12 at 03:14 +, Qianyu Gong wrote:
> > > > -Original Message-
> > > > From: Scott Wood [mailto:o...@buserror.net]
> > > > Sent: Tuesday, January 12, 2016 1:47 AM
> > > > To: Qianyu Gong ; u-boot@lists.denx.de
> > > > Cc: b07...@freescale.com; b48...@freescale.com;
> > > > wenbin.s...@freescale.com; Mingkai Hu 
> > > > Subject: Re: [U-Boot] [Patch V3 3/3] armv8/ls1043aqds: add QSPI boot
> > > > support
> > > > 
> > > > On Mon, 2016-01-11 at 10:17 +0800, Gong Qianyu wrote:
> > > > > diff --git a/board/freescale/ls1043aqds/ls1043aqds.c
> > > > > b/board/freescale/ls1043aqds/ls1043aqds.c
> > > > > index d6696ca..770b79f 100644
> > > > > --- a/board/freescale/ls1043aqds/ls1043aqds.c
> > > > > +++ b/board/freescale/ls1043aqds/ls1043aqds.c
> > > > > @@ -43,15 +43,19 @@ enum {
> > > > > 
> > > > >  int checkboard(void)
> > > > >  {
> > > > > +#ifndef CONFIG_QSPI_BOOT
> > > > >   char buf[64];
> > > > >  #ifndef CONFIG_SD_BOOT
> > > > >   u8 sw;
> > > > >  #endif
> > > > > +#endif
> > > > > 
> > > > >   puts("Board: LS1043AQDS, boot from ");
> > > > > 
> > > > >  #ifdef CONFIG_SD_BOOT
> > > > >   puts("SD\n");
> > > > > +#elif defined(CONFIG_QSPI_BOOT)
> > > > > + puts("QSPI\n");
> > > > >  #else
> > > > >   sw = QIXIS_READ(brdcfg[0]);
> > > > >   sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; @@ 
> > > > > -68,12
> > > > +72,15
> > > > > @@ int checkboard(void)
> > > > >   printf("invalid setting of SW%u\n",
> > > > > QIXIS_LBMAP_SWITCH);
> > > > #endif
> > > > > 
> > > > > +#ifndef CONFIG_QSPI_BOOT
> > > > > + /* For QSPI boot, here I2C is not ready yet. */
> > > > >   printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
> > > > >  QIXIS_READ(id), QIXIS_READ(arch));
> > > > > 
> > > > >   printf("FPGA:  v%d (%s), build %d\n",
> > > > >  (int)QIXIS_READ(scver), qixis_read_tag(buf),
> > > > >  (int)qixis_read_minor());
> > > > > +#endif
> > > > 
> > > > Why isn't i2c ready?  How is DDR inited without it?
> > > > 
> > > > -Scott
> > > 
> > > Hi Scott,
> > > 
> > > The calling sequence in U-Boot is :
> > > checkboard() -> init_func_i2c() -> dram_init()
> > > 
> > > So I2C is not ready in checkboard() but is ready for DDR initialization.
> > 
> > Can you move the prints later in the boot sequence?
> > 
> > In any case, the relevant variable is whether qixis uses i2c, not whether
> > you're
> > booting from qspi (even if they are correlated).
> > 
> > -Scott
> 
> Yes. Only with QSPI it needs I2C to access QIXIS. 
> But if defining CONFIG_DISPLAY_BOARDINFO_LATE, the print layout will look
> really uncomfortable.. So we just comment out the FPGA prints for QSPI boot.

Can this info be dumped from a command instead of just removed?

-Scott

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Re: [U-Boot] [PATCH] board: ls2085aqds: Update kernel_size env variable

2016-01-21 Thread Scott Wood
On Thu, 2016-01-14 at 18:06 +, york sun wrote:
> On 01/05/2016 09:00 PM, Prabhakar Kushwaha wrote:
> > kernel_size env variable is defined as 0x2800, it is beyond NOR
> > flash.
> > 
> > Update kernel_size with 40MB kernel size.
> > 
> > Signed-off-by: Prabhakar Kushwaha 
> > ---
> >  include/configs/ls2080aqds.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
> > index ba84248..a402c06 100644
> > --- a/include/configs/ls2080aqds.h
> > +++ b/include/configs/ls2080aqds.h
> > @@ -346,7 +346,7 @@ unsigned long get_board_ddr_clk(void);
> > "initrd_high=0x\0"  \
> > "kernel_start=0x58110\0"\
> > "kernel_load=0xa000\0"  \
> > -   "kernel_size=0x2800\0"
> > +   "kernel_size=0x280\0"
> >  
> >  #ifdef CONFIG_FSL_MC_ENET
> >  #define CONFIG_FSL_MEMAC
> > 
> Prabhakar,
> 
> I am tired of these changes. Can you go over all the default settings and
> verify
> they all make sense? A short while ago Scott found fdt_high was not correct.

That was ls1021a.

-Scott

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[U-Boot] [PATCH v9 03/49] dm: pmic: Add 'reg status' to show all regulators

2016-01-21 Thread Simon Glass
It is convenient to be able to see the status of all regulators in a list.
Add this feature to the 'reg status' command.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 common/cmd_regulator.c | 66 ++
 1 file changed, 56 insertions(+), 10 deletions(-)

diff --git a/common/cmd_regulator.c b/common/cmd_regulator.c
index 793f08e..bfea6e0 100644
--- a/common/cmd_regulator.c
+++ b/common/cmd_regulator.c
@@ -180,18 +180,13 @@ static int do_info(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
return CMD_RET_SUCCESS;
 }
 
-static int do_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static void do_status_detail(struct udevice *dev,
+struct dm_regulator_uclass_platdata *uc_pdata)
 {
-   struct dm_regulator_uclass_platdata *uc_pdata;
-   int current, value, mode, ret;
-   const char *mode_name = NULL;
-   struct udevice *dev;
+   int current, value, mode;
+   const char *mode_name;
bool enabled;
 
-   ret = curr_dev_and_platdata(, _pdata, true);
-   if (ret)
-   return ret;
-
printf("Regulator %s status:\n", uc_pdata->name);
 
enabled = regulator_get_enable(dev);
@@ -206,6 +201,57 @@ static int do_status(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
mode = regulator_get_mode(dev);
mode_name = get_mode_name(uc_pdata->mode, uc_pdata->mode_count, mode);
constraint(" * mode id:", mode, mode_name);
+}
+
+static void do_status_line(struct udevice *dev)
+{
+   struct dm_regulator_uclass_platdata *pdata;
+   int current, value, mode;
+   const char *mode_name;
+   bool enabled;
+
+   pdata = dev_get_uclass_platdata(dev);
+   enabled = regulator_get_enable(dev);
+   value = regulator_get_value(dev);
+   current = regulator_get_current(dev);
+   mode = regulator_get_mode(dev);
+   mode_name = get_mode_name(pdata->mode, pdata->mode_count, mode);
+   printf("%-20s %-10s ", pdata->name, enabled ? "enabled" : "disabled");
+   if (value >= 0)
+   printf("%10d ", value);
+   else
+   printf("%10s ", "-");
+   if (current >= 0)
+   printf("%10d ", current);
+   else
+   printf("%10s ", "-");
+   if (mode >= 0)
+   printf("%-10s", mode_name);
+   else
+   printf("%-10s", "-");
+   printf("\n");
+}
+
+static int do_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+   struct dm_regulator_uclass_platdata *uc_pdata;
+   struct udevice *dev;
+   int ret;
+
+   if (currdev && (argc < 2 || strcmp(argv[1], "-a"))) {
+   ret = curr_dev_and_platdata(, _pdata, true);
+   if (ret)
+   return CMD_RET_FAILURE;
+   do_status_detail(dev, uc_pdata);
+   return 0;
+   }
+
+   /* Show all of them in a list, probing them as needed */
+   printf("%-20s %-10s %10s %10s %-10s\n", "Name", "Enabled", "uV", "mA",
+  "Mode");
+   for (ret = uclass_first_device(UCLASS_REGULATOR, ); dev;
+ret = uclass_next_device())
+   do_status_line(dev);
 
return CMD_RET_SUCCESS;
 }
@@ -400,7 +446,7 @@ U_BOOT_CMD(regulator, CONFIG_SYS_MAXARGS, 1, do_regulator,
"list - list UCLASS regulator devices\n"
"regulator dev [regulator-name] - show/[set] operating regulator 
device\n"
"regulator info - print constraints info\n"
-   "regulator status   - print operating status\n"
+   "regulator status [-a]  - print operating status [for all]\n"
"regulator value [val] [-f] - print/[set] voltage value [uV] 
(force)\n"
"regulator current [val]- print/[set] current value [uA]\n"
"regulator mode [id]- print/[set] operating mode id\n"
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 02/49] dm: pinctrl: Add a function to parse PIN_CONFIG flags

2016-01-21 Thread Simon Glass
Add a function which produces a flags word from a few common PIN_CONFIG
settings. This is useful for simple pinctrl drivers that don't need to worry
about drive strength, etc.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/pinctrl/pinctrl-uclass.c | 12 
 include/dm/pinctrl.h | 13 +
 2 files changed, 25 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c
index c42b312..1acbfaf 100644
--- a/drivers/pinctrl/pinctrl-uclass.c
+++ b/drivers/pinctrl/pinctrl-uclass.c
@@ -15,6 +15,18 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int pinctrl_decode_pin_config(const void *blob, int node)
+{
+   int flags = 0;
+
+   if (fdtdec_get_bool(blob, node, "bias-pull-up"))
+   flags |= 1 << PIN_CONFIG_BIAS_PULL_UP;
+   else if (fdtdec_get_bool(blob, node, "bias-pull-down"))
+   flags |= 1 << PIN_CONFIG_BIAS_PULL_DOWN;
+
+   return flags;
+}
+
 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
 /**
  * pinctrl_config_one() - apply pinctrl settings for a single node
diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h
index f6025f6..5cd4503 100644
--- a/include/dm/pinctrl.h
+++ b/include/dm/pinctrl.h
@@ -284,4 +284,17 @@ int pinctrl_request_noflags(struct udevice *dev, int func);
  */
 int pinctrl_get_periph_id(struct udevice *dev, struct udevice *periph);
 
+/**
+ * pinctrl_decode_pin_config() - decode pin configuration flags
+ *
+ * This decodes some of the PIN_CONFIG values into flags, with each value
+ * being (1 << pin_cfg). This does not support things with values like the
+ * slew rate.
+ *
+ * @blob:  Device tree blob
+ * @node:  Node containing the PIN_CONFIG values
+ * @return decoded flag value, or -ve on error
+ */
+int pinctrl_decode_pin_config(const void *blob, int node);
+
 #endif /* __PINCTRL_H */
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 01/49] dm: core: Don't set pinctrl for pinctrl devices

2016-01-21 Thread Simon Glass
There is sort-of race condition when a pinctrl device is probed. The pinctrl
function is called which may end up using the same device as is being
probed. This results in operations being used before the device is actually
probed.

For now, disallow pinctrl operations on pinctrl devices while probing. An
alternative solution would be to move the operation to later in the
device_probe() function (for pinctrl devices only) but this needs more
thought.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/core/device.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/core/device.c b/drivers/core/device.c
index 1e5584a..f5def35 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -299,9 +299,11 @@ int device_probe_child(struct udevice *dev, void 
*parent_priv)
 
/*
 * Process pinctrl for everything except the root device, and
-* continue regardless of the result of pinctrl.
+* continue regardless of the result of pinctrl. Don't process pinctrl
+* settings for pinctrl devices since the device may not yet be
+* probed.
 */
-   if (dev->parent)
+   if (dev->parent && device_get_uclass_id(dev) != UCLASS_PINCTRL)
pinctrl_select_state(dev, "default");
 
ret = uclass_pre_probe_device(dev);
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 18/49] rockchip: i2c: Update the driver to use the new clock ID

2016-01-21 Thread Simon Glass
We can use the new clk_get_by_index() function to get the correct clock.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2:
- Update call to clk_get_by_index()

 drivers/i2c/rk_i2c.c | 38 ++
 1 file changed, 22 insertions(+), 16 deletions(-)

diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c
index ebdba35..3fceade 100644
--- a/drivers/i2c/rk_i2c.c
+++ b/drivers/i2c/rk_i2c.c
@@ -30,10 +30,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 struct rk_i2c {
struct udevice *clk;
-   struct udevice *pinctrl;
struct i2c_regs *regs;
unsigned int speed;
-   enum periph_id id;
+   int clk_id;
 };
 
 static inline void rk_i2c_get_div(int div, int *divh, int *divl)
@@ -56,7 +55,7 @@ static void rk_i2c_set_clk(struct rk_i2c *i2c, uint32_t 
scl_rate)
int div, divl, divh;
 
/* First get i2c rate from pclk */
-   i2c_rate = clk_get_periph_rate(i2c->clk, i2c->id);
+   i2c_rate = clk_get_periph_rate(i2c->clk, i2c->clk_id);
 
div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
divh = 0;
@@ -352,23 +351,29 @@ int rockchip_i2c_set_bus_speed(struct udevice *bus, 
unsigned int speed)
return 0;
 }
 
-static int rockchip_i2c_probe(struct udevice *bus)
+static int rockchip_i2c_ofdata_to_platdata(struct udevice *bus)
 {
-   struct rk_i2c *i2c = dev_get_priv(bus);
+   struct rk_i2c *priv = dev_get_priv(bus);
int ret;
 
-   ret = uclass_get_device(UCLASS_PINCTRL, 0, >pinctrl);
-   if (ret)
-   return ret;
-   ret = uclass_get_device(UCLASS_CLK, 0, >clk);
-   if (ret)
-   return ret;
-   ret = pinctrl_get_periph_id(i2c->pinctrl, bus);
-   if (ret < 0)
+   ret = clk_get_by_index(bus, 0, >clk);
+   if (ret < 0) {
+   debug("%s: Could not get clock for %s: %d\n", __func__,
+ bus->name, ret);
return ret;
-   i2c->id = ret;
-   i2c->regs = (void *)dev_get_addr(bus);
-   return pinctrl_request(i2c->pinctrl, i2c->id, 0);
+   }
+   priv->clk_id = ret;
+
+   return 0;
+}
+
+static int rockchip_i2c_probe(struct udevice *bus)
+{
+   struct rk_i2c *priv = dev_get_priv(bus);
+
+   priv->regs = (void *)dev_get_addr(bus);
+
+   return 0;
 }
 
 static const struct dm_i2c_ops rockchip_i2c_ops = {
@@ -385,6 +390,7 @@ U_BOOT_DRIVER(i2c_rockchip) = {
.name   = "i2c_rockchip",
.id = UCLASS_I2C,
.of_match = rockchip_i2c_ids,
+   .ofdata_to_platdata = rockchip_i2c_ofdata_to_platdata,
.probe  = rockchip_i2c_probe,
.priv_auto_alloc_size = sizeof(struct rk_i2c),
.ops= _i2c_ops,
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 13/49] rockchip: jerry: Disable pmic-int-1 setup to avoid a hang

2016-01-21 Thread Simon Glass
This hangs when activated (by probing the PMIC). Disable it for now until we
understand the root cause.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 arch/arm/dts/rk3288-veyron.dtsi | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index 12404ff..a31e00e 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -715,7 +715,10 @@
 
pmic {
pmic_int_l: pmic-int-l {
-   rockchip,pins = ;
+   /*
+* Causes jerry to hang when probing bus 0
+* rockchip,pins = ;
+*/
};
};
 
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 17/37] rockchip: video: Add a video-output driver

2016-01-21 Thread Simon Glass
Some rockchip SoCs include video output (VOP). Add a driver to support this.
It can output via a display driver (UCLASS_DISPLAY) and currently HDMI and
eDP are supported.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/arm/include/asm/arch-rockchip/vop_rk3288.h | 349 
 drivers/video/rockchip/Makefile |   2 +-
 drivers/video/rockchip/rk_vop.c | 346 +++
 3 files changed, 696 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/include/asm/arch-rockchip/vop_rk3288.h
 create mode 100644 drivers/video/rockchip/rk_vop.c

diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h 
b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
new file mode 100644
index 000..0104ba3
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
@@ -0,0 +1,349 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_VOP_RK3288_H
+#define _ASM_ARCH_VOP_RK3288_H
+
+struct rk3288_vop {
+   u32 reg_cfg_done;
+   u32 version_info;
+   u32 sys_ctrl;
+   u32 sys_ctrl1;
+   u32 dsp_ctrl0;
+   u32 dsp_ctrl1;
+   u32 dsp_bg;
+   u32 mcu_ctrl;
+   u32 intr_ctrl0;
+   u32 intr_ctrl1;
+   u32 intr_reserved0;
+   u32 intr_reserved1;
+
+   u32 win0_ctrl0;
+   u32 win0_ctrl1;
+   u32 win0_color_key;
+   u32 win0_vir;
+   u32 win0_yrgb_mst;
+   u32 win0_cbr_mst;
+   u32 win0_act_info;
+   u32 win0_dsp_info;
+   u32 win0_dsp_st;
+   u32 win0_scl_factor_yrgb;
+   u32 win0_scl_factor_cbr;
+   u32 win0_scl_offset;
+   u32 win0_src_alpha_ctrl;
+   u32 win0_dst_alpha_ctrl;
+   u32 win0_fading_ctrl;
+   u32 win0_reserved0;
+
+   u32 win1_ctrl0;
+   u32 win1_ctrl1;
+   u32 win1_color_key;
+   u32 win1_vir;
+   u32 win1_yrgb_mst;
+   u32 win1_cbr_mst;
+   u32 win1_act_info;
+   u32 win1_dsp_info;
+   u32 win1_dsp_st;
+   u32 win1_scl_factor_yrgb;
+   u32 win1_scl_factor_cbr;
+   u32 win1_scl_offset;
+   u32 win1_src_alpha_ctrl;
+   u32 win1_dst_alpha_ctrl;
+   u32 win1_fading_ctrl;
+   u32 win1_reservd0;
+   u32 reserved2[48];
+   u32 post_dsp_hact_info;
+   u32 post_dsp_vact_info;
+   u32 post_scl_factor_yrgb;
+   u32 post_reserved;
+   u32 post_scl_ctrl;
+   u32 post_dsp_vact_info_f1;
+   u32 dsp_htotal_hs_end;
+   u32 dsp_hact_st_end;
+   u32 dsp_vtotal_vs_end;
+   u32 dsp_vact_st_end;
+   u32 dsp_vs_st_end_f1;
+   u32 dsp_vact_st_end_f1;
+};
+check_member(rk3288_vop, dsp_vact_st_end_f1, 0x19c);
+
+enum rockchip_fb_data_format_t {
+   ARGB = 0,
+   RGB888 = 1,
+   RGB565 = 2,
+};
+
+enum {
+   LB_YUV_3840X5 = 0x0,
+   LB_YUV_2560X8 = 0x1,
+   LB_RGB_3840X2 = 0x2,
+   LB_RGB_2560X4 = 0x3,
+   LB_RGB_1920X5 = 0x4,
+   LB_RGB_1280X8 = 0x5
+};
+
+enum vop_modes {
+   VOP_MODE_EDP = 0,
+   VOP_MODE_HDMI,
+   VOP_MODE_NONE,
+   VOP_MODE_AUTO_DETECT,
+   VOP_MODE_UNKNOWN,
+};
+
+/* VOP_VERSION_INFO */
+#define M_FPGA_VERSION (0x << 16)
+#define M_RTL_VERSION  (0x)
+
+/* VOP_SYS_CTRL */
+#define M_AUTO_GATING_EN (1 << 23)
+#define M_STANDBY_EN (1 << 22)
+#define M_DMA_STOP   (1 << 21)
+#define M_MMU_EN (1 << 20)
+#define M_DAM_BURST_LENGTH (0x3 << 18)
+#define M_MIPI_OUT_EN (1 << 15)
+#define M_EDP_OUT_EN   (1 << 14)
+#define M_HDMI_OUT_EN  (1 << 13)
+#define M_RGB_OUT_EN   (1 << 12)
+#define M_ALL_OUT_EN   \
+   (M_MIPI_OUT_EN | M_EDP_OUT_EN | M_HDMI_OUT_EN | M_RGB_OUT_EN)
+#define M_EDPI_WMS_FS  (1 << 10)
+#define M_EDPI_WMS_MODE(1 << 9)
+#define M_EDPI_HALT_EN (1 << 8)
+#define M_DOUB_CH_OVERLAP_NUM (0xf << 4)
+#define M_DOUB_CHANNEL_EN (1 << 3)
+#define M_DIRECT_PATH_LAYER_SEL (0x3 << 1)
+#define M_DIRECT_PATH_EN   (1)
+
+#define V_AUTO_GATING_EN(x) (((x) & 1) << 23)
+#define V_STANDBY_EN(x) (((x) & 1) << 22)
+#define V_DMA_STOP(x)   (((x) & 1) << 21)
+#define V_MMU_EN(x) (((x) & 1) << 20)
+#define V_DMA_BURST_LENGTH(x) (((x) & 3) << 18)
+#define V_MIPI_OUT_EN(x)  (((x) & 1) << 15)
+#define V_EDP_OUT_EN(x)   (((x) & 1) << 14)
+#define V_HDMI_OUT_EN(x)  (((x) & 1) << 13)
+#define V_RGB_OUT_EN(x)   (((x) & 1) << 12)
+#define V_EDPI_WMS_FS(x)  (((x) & 1) << 10)
+#define V_EDPI_WMS_MODE(x)(((x) & 1) << 9)
+#define V_EDPI_HALT_EN(x) (((x)&1)<<8)
+#define V_DOUB_CH_OVERLAP_NUM(x) (((x) & 0xf) << 4)
+#define V_DOUB_CHANNEL_EN(x) (((x) & 1) << 3)
+#define V_DIRECT_PATH_LAYER_SEL(x) (((x) & 3) << 1)
+#define V_DIRECT_PATH_EN(x)   ((x) & 1)
+
+/* VOP_SYS_CTRL1 */
+#define M_AXI_OUTSTANDING_MAX_NUM (0x1f << 13)
+#define M_AXI_MAX_OUTSTANDING_EN  (1 << 12)
+#define M_NOC_WIN_QOS (3 << 10)
+#define M_NOC_QOS_EN  (1 << 9)

[U-Boot] [PATCH v2 18/37] rockchip: Don't skip low-level init

2016-01-21 Thread Simon Glass
At present the low-level init is skipped on rockchip. Among other things
this means that the instruction cache is left disabled. Fix this.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/arm/mach-rockchip/board.c| 4 
 arch/arm/mach-rockchip/rk3288-board-spl.c | 4 
 include/configs/rk3288_common.h   | 1 -
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index f026abf..380aa91 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -45,3 +45,7 @@ void enable_caches(void)
dcache_enable();
 }
 #endif
+
+void lowlevel_init(void)
+{
+}
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c 
b/arch/arm/mach-rockchip/rk3288-board-spl.c
index b2c5729..f61eeab 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -270,3 +270,7 @@ err:
/* No way to report error here */
hang();
 }
+
+void lowlevel_init(void)
+{
+}
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index ebddfb0..b9ff5a5 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -16,7 +16,6 @@
 #define CONFIG_BAUDRATE115200
 #define CONFIG_SYS_MALLOC_LEN  (32 << 20)
 #define CONFIG_SYS_CBSIZE  1024
-#define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_THUMB_BUILD
 #define CONFIG_OF_LIBFDT
 #define CONFIG_DISPLAY_BOARDINFO
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 13/37] rockchip: Rename the CRU_MODE_CON fields

2016-01-21 Thread Simon Glass
These should match the datasheet naming. Adjust them.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 58 -
 drivers/clk/clk_rk3288.c| 39 -
 2 files changed, 38 insertions(+), 59 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h 
b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
index 7ebcc40..b0dea70 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -131,35 +131,35 @@ enum {
 
 /* CRU_MODE_CON */
 enum {
-   NPLL_WORK_SHIFT = 0xe,
-   NPLL_WORK_MASK  = 3,
-   NPLL_WORK_SLOW  = 0,
-   NPLL_WORK_NORMAL,
-   NPLL_WORK_DEEP,
-
-   GPLL_WORK_SHIFT = 0xc,
-   GPLL_WORK_MASK  = 3,
-   GPLL_WORK_SLOW  = 0,
-   GPLL_WORK_NORMAL,
-   GPLL_WORK_DEEP,
-
-   CPLL_WORK_SHIFT = 8,
-   CPLL_WORK_MASK  = 3,
-   CPLL_WORK_SLOW  = 0,
-   CPLL_WORK_NORMAL,
-   CPLL_WORK_DEEP,
-
-   DPLL_WORK_SHIFT = 4,
-   DPLL_WORK_MASK  = 3,
-   DPLL_WORK_SLOW  = 0,
-   DPLL_WORK_NORMAL,
-   DPLL_WORK_DEEP,
-
-   APLL_WORK_SHIFT = 0,
-   APLL_WORK_MASK  = 3,
-   APLL_WORK_SLOW  = 0,
-   APLL_WORK_NORMAL,
-   APLL_WORK_DEEP,
+   NPLL_MODE_SHIFT = 0xe,
+   NPLL_MODE_MASK  = 3,
+   NPLL_MODE_SLOW  = 0,
+   NPLL_MODE_NORMAL,
+   NPLL_MODE_DEEP,
+
+   GPLL_MODE_SHIFT = 0xc,
+   GPLL_MODE_MASK  = 3,
+   GPLL_MODE_SLOW  = 0,
+   GPLL_MODE_NORMAL,
+   GPLL_MODE_DEEP,
+
+   CPLL_MODE_SHIFT = 8,
+   CPLL_MODE_MASK  = 3,
+   CPLL_MODE_SLOW  = 0,
+   CPLL_MODE_NORMAL,
+   CPLL_MODE_DEEP,
+
+   DPLL_MODE_SHIFT = 4,
+   DPLL_MODE_MASK  = 3,
+   DPLL_MODE_SLOW  = 0,
+   DPLL_MODE_NORMAL,
+   DPLL_MODE_DEEP,
+
+   APLL_MODE_SHIFT = 0,
+   APLL_MODE_MASK  = 3,
+   APLL_MODE_SLOW  = 0,
+   APLL_MODE_NORMAL,
+   APLL_MODE_DEEP,
 };
 
 /* CRU_APLL_CON0 */
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index 5a8f175..ed39b93 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -97,27 +97,6 @@ enum {
PERI_ACLK_DIV_SHIFT = 0,
PERI_ACLK_DIV_MASK  = 0x1f,
 
-   /* CLKSEL37 */
-   DPLL_MODE_MASK  = 0x3,
-   DPLL_MODE_SHIFT = 4,
-   DPLL_MODE_SLOW  = 0,
-   DPLL_MODE_NORM,
-
-   CPLL_MODE_MASK  = 3,
-   CPLL_MODE_SHIFT = 8,
-   CPLL_MODE_SLOW  = 0,
-   CPLL_MODE_NORM,
-
-   GPLL_MODE_MASK  = 3,
-   GPLL_MODE_SHIFT = 12,
-   GPLL_MODE_SLOW  = 0,
-   GPLL_MODE_NORM,
-
-   NPLL_MODE_MASK  = 3,
-   NPLL_MODE_SHIFT = 14,
-   NPLL_MODE_SLOW  = 0,
-   NPLL_MODE_NORM,
-
SOCSTS_DPLL_LOCK= 1 << 5,
SOCSTS_APLL_LOCK= 1 << 6,
SOCSTS_CPLL_LOCK= 1 << 7,
@@ -251,7 +230,7 @@ static int rkclk_configure_ddr(struct rk3288_cru *cru, 
struct rk3288_grf *grf,
 
/* PLL enter normal-mode */
rk_clrsetreg(>cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
-DPLL_MODE_NORM << DPLL_MODE_SHIFT);
+DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
 
return 0;
 }
@@ -331,8 +310,8 @@ static void rkclk_init(struct rk3288_cru *cru, struct 
rk3288_grf *grf)
rk_clrsetreg(>cru_mode_con,
 GPLL_MODE_MASK << GPLL_MODE_SHIFT |
 CPLL_MODE_MASK << CPLL_MODE_SHIFT,
-GPLL_MODE_NORM << GPLL_MODE_SHIFT |
-GPLL_MODE_NORM << CPLL_MODE_SHIFT);
+GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
+CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
 }
 #endif
 
@@ -345,17 +324,17 @@ static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
int pll_id = rk_pll_id(clk_id);
struct rk3288_pll *pll = >pll[pll_id];
static u8 clk_shift[CLK_COUNT] = {
-   0xff, APLL_WORK_SHIFT, DPLL_WORK_SHIFT, CPLL_WORK_SHIFT,
-   GPLL_WORK_SHIFT, NPLL_WORK_SHIFT
+   0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
+   GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
};
uint shift;
 
con = readl(>cru_mode_con);
shift = clk_shift[clk_id];
-   switch ((con >> shift) & APLL_WORK_MASK) {
-   case APLL_WORK_SLOW:
+   switch ((con >> shift) & APLL_MODE_MASK) {
+   case APLL_MODE_SLOW:
return OSC_HZ;
-   case APLL_WORK_NORMAL:
+   case APLL_MODE_NORMAL:
/* normal mode */
con = readl(>con0);

[U-Boot] [PATCH v2 22/37] rockchip: sdram: Tidy up a few comments

2016-01-21 Thread Simon Glass
Fix spaces in two comments in this file.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c 
b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index 5da04b9..2a43574 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -405,7 +405,7 @@ static void set_bandwidth_ratio(const struct chan_info 
*chan, u32 channel,
/* Data Byte disable*/
clrbits_le32(>datx8[2].dxgcr, 1);
clrbits_le32(>datx8[3].dxgcr, 1);
-   /*disable DLL */
+   /* disable DLL */
setbits_le32(>datx8[2].dxdllcr, DXDLLCR_DLLDIS);
setbits_le32(>datx8[3].dxdllcr, DXDLLCR_DLLDIS);
} else {
@@ -416,7 +416,7 @@ static void set_bandwidth_ratio(const struct chan_info 
*chan, u32 channel,
setbits_le32(>datx8[2].dxgcr, 1);
setbits_le32(>datx8[3].dxgcr, 1);
 
-   /*enable DLL */
+   /* enable DLL */
clrbits_le32(>datx8[2].dxdllcr, DXDLLCR_DLLDIS);
clrbits_le32(>datx8[3].dxdllcr, DXDLLCR_DLLDIS);
/* reset DLL */
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 49/49] rockchip: jerry: Enable the Chrome OS EC

2016-01-21 Thread Simon Glass
Turn on the EC and enable the keyboard.

Signed-off-by: Simon Glass 
---

Changes in v9:
- Rebase to upstream/master

Changes in v2: None

 arch/arm/dts/rk3288-veyron-chromebook.dtsi | 4 
 configs/chromebook_jerry_defconfig | 8 
 include/configs/chromebook_jerry.h | 7 +++
 include/configs/firefly-rk3288.h   | 2 ++
 include/configs/rk3288_common.h| 7 +++
 5 files changed, 28 insertions(+)

diff --git a/arch/arm/dts/rk3288-veyron-chromebook.dtsi 
b/arch/arm/dts/rk3288-veyron-chromebook.dtsi
index 6d619c9..bbbc2f4 100644
--- a/arch/arm/dts/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/dts/rk3288-veyron-chromebook.dtsi
@@ -91,12 +91,16 @@
 
  {
status = "okay";
+   spi-activate-delay = <100>;
+   spi-max-frequency = <300>;
+   spi-deactivate-delay = <200>;
 
cros_ec: ec@0 {
compatible = "google,cros-ec-spi";
spi-max-frequency = <300>;
interrupt-parent = <>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+   ec-interrupt = < 7 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <_int>;
reg = <0>;
diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index ceec6f5..b2672b8 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ROCKCHIP_RK3288=y
 CONFIG_TARGET_CHROMEBOOK_JERRY=y
 CONFIG_SPL_STACK_R_ADDR=0x8
+CONFIG_DM_KEYBOARD=y
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-jerry"
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
@@ -21,7 +22,13 @@ CONFIG_SPL_SYSCON=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_I2C_MUX=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_CMD_CROS_EC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
 CONFIG_RESET=y
 CONFIG_DM_MMC=y
@@ -31,6 +38,7 @@ CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_FULL is not set
 CONFIG_ROCKCHIP_PINCTRL=y
 CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_RK808=y
 CONFIG_DM_REGULATOR=y
 CONFIG_REGULATOR_RK808=y
diff --git a/include/configs/chromebook_jerry.h 
b/include/configs/chromebook_jerry.h
index 78c06af..6e32f2c 100644
--- a/include/configs/chromebook_jerry.h
+++ b/include/configs/chromebook_jerry.h
@@ -7,6 +7,11 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define ROCKCHIP_DEVICE_SETTINGS \
+   "stdin=serial,cros-ec-keyb\0" \
+   "stdout=serial\0" \
+   "stderr=serial\0"
+
 #include 
 
 #define CONFIG_ENV_IS_NOWHERE
@@ -17,4 +22,6 @@
 
 #undef CONFIG_SPL_GPIO_SUPPORT
 
+#define CONFIG_KEYBOARD
+
 #endif
diff --git a/include/configs/firefly-rk3288.h b/include/configs/firefly-rk3288.h
index 4c5c4dd..8ac6521 100644
--- a/include/configs/firefly-rk3288.h
+++ b/include/configs/firefly-rk3288.h
@@ -7,6 +7,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define ROCKCHIP_DEVICE_SETTINGS
+
 #include 
 
 #define CONFIG_SPL_MMC_SUPPORT
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index f47573b..ebddfb0 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -42,6 +42,12 @@
 #define CONFIG_ROCKCHIP_COMMON
 #define CONFIG_SPL_ROCKCHIP_COMMON
 
+#define CONFIG_SILENT_CONSOLE
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_SYS_CONSOLE_IS_IN_ENV
+# define CONFIG_CONSOLE_MUX
+#endif
+
 /* MMC/SD IP block */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
@@ -110,6 +116,7 @@
"fdt_high=0x1fff\0" \
"initrd_high=0x1fff\0" \
ENV_MEM_LAYOUT_SETTINGS \
+   ROCKCHIP_DEVICE_SETTINGS \
BOOTENV
 #endif
 
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 12/37] dm: video: Repurpose the 'displayport' uclass to 'display'

2016-01-21 Thread Simon Glass
The current DisplayPort uclass is too specific. The operations it provides
are shared with other types of output devices, such as HDMI and LVDS LCD
displays.

Generalise the uclass so that it can be used with these devices as well.
Adjust the uclass to handle the EDID reading and conversion to
display_timing internally.

Also update nyan-big which is affected by this.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 configs/nyan-big_defconfig   |  2 +-
 drivers/video/Kconfig| 13 +
 drivers/video/Makefile   |  2 +-
 drivers/video/display-uclass.c   | 52 
 drivers/video/dp-uclass.c| 34 ---
 drivers/video/tegra124/display.c | 18 -
 drivers/video/tegra124/dp.c  |  9 ---
 include/{displayport.h => display.h} | 33 ++-
 include/dm/uclass-id.h   |  2 +-
 include/edid.h   |  1 +
 10 files changed, 95 insertions(+), 71 deletions(-)
 create mode 100644 drivers/video/display-uclass.c
 delete mode 100644 drivers/video/dp-uclass.c
 rename include/{displayport.h => display.h} (59%)

diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 7fc1bde..03348a6 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -25,7 +25,7 @@ CONFIG_TEGRA114_SPI=y
 CONFIG_TPM_TIS_INFINEON=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-CONFIG_DISPLAY_PORT=y
+CONFIG_DISPLAY=y
 CONFIG_VIDEO_TEGRA124=y
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_TPM=y
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index ae122da..9ecfeae 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -293,12 +293,15 @@ config VIDEO_LCD_SPI_MISO
option takes a string in the format understood by 'name_to_gpio'
function, e.g. PH1 for pin 1 of port H.
 
-config DISPLAY_PORT
-   bool "Enable DisplayPort support"
+config DISPLAY
+   bool "Enable Display support"
+   depends on DM
+   default y
help
-  eDP (Embedded DisplayPort) is a standard widely used in laptops
-  to drive LCD panels. This framework provides support for enabling
-  these displays where supported by the video hardware.
+  This supports drivers that provide a display, such as eDP (Embedded
+  DisplayPort) and HDMI (High Definition Multimedia Interface).
+  The devices provide a simple interface to start up the display,
+  read display information and enable it.
 
 config VIDEO_SANDBOX_SDL
bool "Enable sandbox video console using SDL"
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 6658e96..c135e22 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -6,7 +6,7 @@
 #
 
 ifdef CONFIG_DM
-obj-$(CONFIG_DISPLAY_PORT) += dp-uclass.o
+obj-$(CONFIG_DISPLAY) += display-uclass.o
 obj-$(CONFIG_DM_VIDEO) += backlight-uclass.o
 obj-$(CONFIG_DM_VIDEO) += panel-uclass.o simple_panel.o
 obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o console_normal.o
diff --git a/drivers/video/display-uclass.c b/drivers/video/display-uclass.c
new file mode 100644
index 000..31522ea
--- /dev/null
+++ b/drivers/video/display-uclass.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2014 Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+int display_read_edid(struct udevice *dev, u8 *buf, int buf_size)
+{
+   struct dm_display_ops *ops = display_get_ops(dev);
+
+   if (!ops || !ops->read_edid)
+   return -ENOSYS;
+   return ops->read_edid(dev, buf, buf_size);
+}
+
+int display_enable(struct udevice *dev, int panel_bpp,
+   const struct display_timing *timing)
+{
+   struct dm_display_ops *ops = display_get_ops(dev);
+
+   if (!ops || !ops->enable)
+   return -ENOSYS;
+   return ops->enable(dev, panel_bpp, timing);
+}
+
+int display_read_timing(struct udevice *dev, struct display_timing *timing)
+{
+   struct dm_display_ops *ops = display_get_ops(dev);
+   int panel_bits_per_colour;
+   u8 buf[EDID_EXT_SIZE];
+   int ret;
+
+   if (!ops || !ops->read_edid)
+   return -ENOSYS;
+   ret = ops->read_edid(dev, buf, sizeof(buf));
+   if (ret < 0)
+   return ret;
+
+   return edid_get_timing(buf, ret, timing, _bits_per_colour);
+}
+
+UCLASS_DRIVER(display) = {
+   .id = UCLASS_DISPLAY,
+   .name   = "display",
+   .per_device_platdata_auto_alloc_size= sizeof(struct display_plat),
+};
diff --git a/drivers/video/dp-uclass.c b/drivers/video/dp-uclass.c
deleted file mode 100644
index 17f5de9..000
--- a/drivers/video/dp-uclass.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2014 Google Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include 
-#include 
-#include 
-#include 
-
-int display_port_read_edid(struct 

[U-Boot] [PATCH v9 22/49] rockchip: pinctrl: Add a full pinctrl driver

2016-01-21 Thread Simon Glass
We can make use of the device tree to configure pinctrl settings. Add this
support for the driver so we can use it in U-Boot proper.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/pinctrl/rockchip/pinctrl_rk3288.c | 230 +-
 1 file changed, 229 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c 
b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
index ec3c4fe..0e7721e 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
@@ -24,8 +24,103 @@ DECLARE_GLOBAL_DATA_PTR;
 struct rk3288_pinctrl_priv {
struct rk3288_grf *grf;
struct rk3288_pmu *pmu;
+   int num_banks;
 };
 
+/**
+ * Encode variants of iomux registers into a type variable
+ */
+#define IOMUX_GPIO_ONLYBIT(0)
+#define IOMUX_WIDTH_4BIT   BIT(1)
+#define IOMUX_SOURCE_PMU   BIT(2)
+#define IOMUX_UNROUTED BIT(3)
+
+/**
+ * @type: iomux variant using IOMUX_* constants
+ * @offset: if initialized to -1 it will be autocalculated, by specifying
+ * an initial offset value the relevant source offset can be reset
+ * to a new value for autocalculating the following iomux registers.
+ */
+struct rockchip_iomux {
+   u8 type;
+   s16 offset;
+};
+
+/**
+ * @reg: register offset of the gpio bank
+ * @nr_pins: number of pins in this bank
+ * @bank_num: number of the bank, to account for holes
+ * @name: name of the bank
+ * @iomux: array describing the 4 iomux sources of the bank
+ */
+struct rockchip_pin_bank {
+   u16 reg;
+   u8 nr_pins;
+   u8 bank_num;
+   char *name;
+   struct rockchip_iomux iomux[4];
+};
+
+#define PIN_BANK(id, pins, label)  \
+   {   \
+   .bank_num   = id,   \
+   .nr_pins= pins, \
+   .name   = label,\
+   .iomux  = { \
+   { .offset = -1 },   \
+   { .offset = -1 },   \
+   { .offset = -1 },   \
+   { .offset = -1 },   \
+   },  \
+   }
+
+#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)  \
+   {   \
+   .bank_num   = id,   \
+   .nr_pins= pins, \
+   .name   = label,\
+   .iomux  = { \
+   { .type = iom0, .offset = -1 }, \
+   { .type = iom1, .offset = -1 }, \
+   { .type = iom2, .offset = -1 }, \
+   { .type = iom3, .offset = -1 }, \
+   },  \
+   }
+
+#ifndef CONFIG_SPL_BUILD
+static struct rockchip_pin_bank rk3288_pin_banks[] = {
+   PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
+IOMUX_SOURCE_PMU,
+IOMUX_SOURCE_PMU,
+IOMUX_UNROUTED
+   ),
+   PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
+IOMUX_UNROUTED,
+IOMUX_UNROUTED,
+0
+   ),
+   PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
+   PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
+   PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
+IOMUX_WIDTH_4BIT,
+0,
+0
+   ),
+   PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
+0,
+0,
+IOMUX_UNROUTED
+   ),
+   PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
+   PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
+0,
+IOMUX_WIDTH_4BIT,
+IOMUX_UNROUTED
+   ),
+   PIN_BANK(8, 16, "gpio8"),
+};
+#endif
+
 static void pinctrl_rk3288_pwm_config(struct rk3288_grf *grf, int pwm_id)
 {
switch (pwm_id) {
@@ -410,7 +505,106 @@ static int 

[U-Boot] [PATCH v2 23/37] rockchip: sdram: Use syscon_get_first_range() where possible

2016-01-21 Thread Simon Glass
This is a shortcut to obtaining a register address. Use it where possible, to
simplify the code.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 17 +++--
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c 
b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index 2a43574..074cf518 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -808,20 +808,9 @@ static int rk3288_dmc_probe(struct udevice *dev)
priv->chan[1].msch = (struct rk3288_msch *)
(regmap_get_range(map, 0) + 0x80);
 
-   map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_GRF);
-   if (IS_ERR(map))
-   return PTR_ERR(map);
-   priv->grf = regmap_get_range(map, 0);
-
-   map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_SGRF);
-   if (IS_ERR(map))
-   return PTR_ERR(map);
-   priv->sgrf = regmap_get_range(map, 0);
-
-   map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_PMU);
-   if (IS_ERR(map))
-   return PTR_ERR(map);
-   priv->pmu = regmap_get_range(map, 0);
+   priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+   priv->sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
+   priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 
ret = regmap_init_mem(dev, );
if (ret)
-- 
2.7.0.rc3.207.g0ac5344

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Re: [U-Boot] [PATCH v4 5/6] rockchip: kylin: Enable boot with android boot image

2016-01-21 Thread Simon Glass
Hi,

On 15 January 2016 at 18:18, Simon Glass  wrote:
> Hi,
>
> On 15 January 2016 at 08:42, Daniel Schwierzeck
>  wrote:
>> Am Freitag, den 15.01.2016, 09:42 -0500 schrieb Tom Rini:
>>> On Fri, Jan 15, 2016 at 10:20:43AM +0800, Jeffy Chen wrote:
>>> > Hi Tom,
>>> >
>>> > On 2016-1-15 8:59, Tom Rini wrote:
>>> > > On Fri, Jan 15, 2016 at 08:53:06AM +0800, Jeffy Chen wrote:
>>> > > > Hi Tom,
>>> > > >
>>> > > > On 2016-1-15 0:22, Tom Rini wrote:
>>> > > > > On Thu, Jan 14, 2016 at 10:31:34AM +0800, Jeffy Chen wrote:
>>> > > > > > Hi Tom,
>>> > > > > >
>>> > > > > > On 2016-1-13 23:28, Tom Rini wrote:
>>> > > > > > > On Wed, Jan 13, 2016 at 04:53:19PM +0800, Jeffy Chen
>>> > > > > > > wrote:
>>> > > > > > >
>>> > > > > > > > The android kernel is using appended dtb by default,
>>> > > > > > > > and store
>>> > > > > > > > ramdisk right after kernel & dtb.
>>> > > > > > > > So we needs to relocate ramdisk, and use atags to pass
>>> > > > > > > > params.
>>> > > > > > > >
>>> > > > > > > > Signed-off-by: Jeffy Chen 
>>> > > > > > > > Acked-by: Simon Glass 
>>> > > > > > > > ---
>>> > > > > > > >
>>> > > > > > > > Changes in v4: None
>>> > > > > > > > Changes in v3: None
>>> > > > > > > > Changes in v2: None
>>> > > > > > > >
>>> > > > > > > >  include/configs/kylin_rk3036.h | 23
>>> > > > > > > > +++
>>> > > > > > > >  1 file changed, 23 insertions(+)
>>> > > > > > > >
>>> > > > > > > > diff --git a/include/configs/kylin_rk3036.h
>>> > > > > > > > b/include/configs/kylin_rk3036.h
>>> > > > > > > > index b750b26..49997ec 100644
>>> > > > > > > > --- a/include/configs/kylin_rk3036.h
>>> > > > > > > > +++ b/include/configs/kylin_rk3036.h
>>> > > > > > > > @@ -35,6 +35,29 @@
>>> > > > > > > >  #undef CONFIG_EXTRA_ENV_SETTINGS
>>> > > > > > > >  #define CONFIG_EXTRA_ENV_SETTINGS \
>>> > > > > > > > "partitions=" PARTS_DEFAULT \
>>> > > > > > > > +   "mmcdev=0\0" \
>>> > > > > > > > +   "mmcpart=5\0" \
>>> > > > > > > > +   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR)
>>> > > > > > > > "\0" \
>>> > > > > > > > +
>>> > > > > > > > +#define CONFIG_ANDROID_BOOT_IMAGE
>>> > > > > > > > +#define CONFIG_SYS_BOOT_RAMDISK_HIGH
>>> > > > > > > This should already be set.
>>> > > > > > Right, i'll remove it...
>>> > > > > > > > +#define CONFIG_SYS_HUSH_PARSER
>>> > > > > > > > +
>>> > > > > > > > +#undef CONFIG_BOOTCOMMAND
>>> > > > > > > > +#define CONFIG_BOOTCOMMAND \
>>> > > > > > > > +   "mmc dev ${mmcdev}; if mmc rescan; then " \
>>> > > > > > > > +   "part start mmc ${mmcdev} ${mmcpart}
>>> > > > > > > > boot_start;" \
>>> > > > > > > > +   "part size mmc ${mmcdev} ${mmcpart}
>>> > > > > > > > boot_size;" \
>>> > > > > > > > +   "mmc read ${loadaddr} ${boot_start}
>>> > > > > > > > ${boot_size};" \
>>> > > > > > > > +   "bootm start ${loadaddr}; bootm
>>> > > > > > > > ramdisk;" \
>>> > > > > > > > +   "bootm prep; bootm go;" \
>>> > > > > > > > +   "fi;" \
>>> > > > > > > > +
>>> > > > > > > > +/* Enable atags */
>>> > > > > > > > +#define CONFIG_SYS_BOOTPARAMS_LEN  (64*1024)
>>> > > > > > > > +#define CONFIG_INITRD_TAG
>>> > > > > > > > +#define CONFIG_SETUP_MEMORY_TAGS
>>> > > > > > > > +#define CONFIG_CMDLINE_TAG
>>> > > > > > > But I'm confused as to what exactly is going on here.
>>> > > > > > >  Appended dtb is
>>> > > > > > > not the same as ATAGS.  And you shouldn't need to split
>>> > > > > > > up bootm like
>>> > > > > > > that.  Can you please explain a bit more?  Thanks!
>>> > > > > > The u-boot will pass atags to kernel, and kernel will merge
>>> > > > > > those
>>> > > > > > atags into the appended dtb(fdt).
>>> > > > > >
>>> > > > > > The default bootm flow would not pass ramdisk state, but we
>>> > > > > > need it,
>>> > > > > > so we should add this state into default flow, or just use
>>> > > > > > split
>>> > > > > > bootm cmds :)
>>> > > > > That seems very strange.  Is the ramdisk concatenated with
>>> > > > > the kernel
>>> > > > > and dtb as well (and that's why bootm ramdisk somehow finds
>>> > > > > it but
>>> > > > > normal bootm doesn't as you aren't passing in a ramdisk
>>> > > > > address) ?
>>> > > > Yes, the ramdisk concatenated with the kernel and dtb as
>>> > > > well(u-boot/include/android_image.h: struct andr_img_hdr).
>>> > > >
>>> > > > And the normal bootm cmd would find it by parsing andr_img_hdr
>>> > > > struct.
>>> > > > But we still need bootm ramdisk state, because it will call
>>> > > > boot_ramdisk_high to relocate ramdisk area :)
>>> > > >
>>> > > > I found if not relocate it to somewhere else, it would be
>>> > > > corrupted
>>> > > > after kernel's decompressing(during update fdt area).
>>> > > So 'bootm $loadaddr' of an Android image sees, but does not
>>> > > relocate the
>>> > > ramdisk that is included in the image, but bootm ramdisk does?
>>> > >  That
>>> > > 

Re: [U-Boot] [PATCH v5 3/6] rockchip: kylin: Add default gpt partition table

2016-01-21 Thread Simon Glass
On 13 January 2016 at 19:19, Jeffy Chen  wrote:
> Add default android gpt partition table for kylin board.
>
> Use "gpt write mmc 0 $partitions" to apply.
>
> Signed-off-by: Jeffy Chen 
> Acked-by: Simon Glass 
> Reviewed-by: Tom Rini 
> ---
>
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
>  include/configs/kylin_rk3036.h | 29 +
>  1 file changed, 29 insertions(+)

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [PATCH v5 5/6] rockchip: kylin: Check fastboot request

2016-01-21 Thread Simon Glass
On 14 January 2016 at 10:17, Simon Glass  wrote:
> On 13 January 2016 at 19:19, Jeffy Chen  wrote:
>> We will save boot mode flag in grf's os_reg[4], if fastboot
>> requested or fastboot key pressed, try to enter fastboot mode
>> at preboot stage.
>>
>> Signed-off-by: Jeffy Chen 
>>
>> ---
>>
>> Changes in v5:
>> Change "grf" to local var.
>>
>> Changes in v4:
>> Remove unused reboot mode definitions.
>>
>> Changes in v3:
>> Use rockchip's legacy reboot mode definitions.
>>
>> Changes in v2: None
>>
>>  board/kylin/kylin_rk3036/kylin_rk3036.c | 32 
>> 
>>  include/configs/kylin_rk3036.h  |  3 +++
>>  2 files changed, 35 insertions(+)
>
> Acked-by: Simon Glass 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [PATCH v5 2/6] rockchip: rk3036: Bind GPIO banks

2016-01-21 Thread Simon Glass
On 13 January 2016 at 19:19, Jeffy Chen  wrote:
> Call dm_scan_fdt_node() in rk3036 pinctrl uclass binding.
>
> Signed-off-by: Jeffy Chen 
> Acked-by: Simon Glass 
> Reviewed-by: Tom Rini 
> ---
>
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
>  drivers/pinctrl/rockchip/pinctrl_rk3036.c | 8 
>  1 file changed, 8 insertions(+)

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [PATCH 0/8] Convert lpuart serial driver to driver model

2016-01-21 Thread Simon Glass
Hi,

On 12 January 2016 at 02:30, Bhuvanchandra DV
 wrote:
> Hi Bin,
>
>
> On 01/12/2016 12:21 PM, Bin Meng wrote:
>>
>> Hi Bhuvanchandra,
>>
>> On Tue, Jan 12, 2016 at 2:43 PM, Bhuvanchandra DV
>>  wrote:
>>>
>>> Hi Bin,
>>>
>>>
>>> On 01/12/2016 11:05 AM, Bin Meng wrote:


 Hi Bhuvanchandra,

 On Tue, Jan 12, 2016 at 12:28 PM, Bhuvanchandra DV
  wrote:
>
>
> - Convert lpuart driver to driver model and remove the legacy code.
> - Update Toradex Colibri VF50/VF61 serial support with driver model.
> - Update Freescale vf610twr serial support with driver model.
> - Update Freescale ls1021atwr serial support with driver model.
> - Update Phytec pcm052 serial support with driver model.
> - Tested the driver on Toradex Colibri VF50/VF61 hardware.
> - Compile checked board files for vf610twr, ls1021atwr and pcm052
> since I don't have access to such hardware at my end. Reviewers
> and testers welcome!
>
> Bhuvanchandra DV (8):
> dm: lpuart: Add driver model support for the serial driver
> colibri_vf: Update enabling lpuart support with driver model
> arm: vf610twr: Add driver model support
> vf610twr: Update enabling lpuart with driver model
> arm: ls102xa: Add driver model support
> ls1021x: Update enabling lpuart with driver model
> arm: pcm052: Enable driver model support
> pcm052: Update enabling lpuart support with driver model
>
>arch/arm/include/asm/arch-ls102xa/serial.h |  16 
>arch/arm/include/asm/arch-vf610/serial.h   |  16 
>board/freescale/ls1021atwr/ls1021atwr.c|  15 ++-
>board/freescale/vf610twr/vf610twr.c|  13 +++
>board/phytec/pcm052/pcm052.c   |  13 +++
>board/toradex/colibri_vf/colibri_vf.c  |  13 +++
>configs/ls1021atwr_nor_lpuart_defconfig|   1 +
>configs/pcm052_defconfig   |   1 +
>configs/vf610twr_defconfig |   1 +
>configs/vf610twr_nand_defconfig|   1 +
>drivers/serial/Kconfig |   6 ++
>drivers/serial/serial_lpuart.c | 148
> +++--
>include/configs/colibri_vf.h   |   6 +-
>include/configs/ls1021atwr.h   |   1 +
>include/configs/pcm052.h   |   6 +-
>include/configs/vf610twr.h |   6 +-
>16 files changed, 180 insertions(+), 83 deletions(-)
>create mode 100644 arch/arm/include/asm/arch-ls102xa/serial.h
>create mode 100644 arch/arm/include/asm/arch-vf610/serial.h
>
> --



 Please see existing patch series @
 http://patchwork.ozlabs.org/patch/561855/. You can drop the ls102xa
 changes and rebase your patch series on top of that. Thanks!
>>>
>>>
>>>
>>> We are not aware of this patch set, sorry! about that. You want me to
>>> drop
>>> only the ls102xa changes? How about the changes/updates to the lpuart
>>> driver? should i update them with your device tree support stuff and
>>> rebase
>>> the remaining patch set along with your Signed-off-by tag ?
>>> Any suggestions ?
>>>
>>
>> I believe you can:
>> - Drop the LPUART DM conversion patch in your series, which was already
>> done
>
>
> I believe that the patch set[1] is now _only_ supporting device tree enabled
> boards, there are boards using lpuart which are not yet having device trees,
> boards like vf610twr and Phytec pcm052. Even with driver model enabled i
> guess these boards canont use lpuart via platform data with this patch set.
> I think it would be nice to have the support for both platform data and
> device tree so that we can use it with platform data via board files and
> device tree too.
>
> Since only few boards are using lpuart driver we can update the driver
> completly to driver model, drop the legacy code and update the boards.
>
> Seems the legacy code in lpuart driver is broken:
> drivers/serial/serial_lpuart.c:148:9: error: too few arguments to function
> '_lpuart_serial_tstc'
>
> I will test the patch set[1] atleast on Toradex Colibri VF50/VF61 h/w and
> will provide a detailed report of my observations.
>
>
> [1] http://patchwork.ozlabs.org/patch/561855/
>
>> - Drop the ls1021atwr changes, which was already done
>> - Do the similar changes to all other boards in your series, by
>> following ls1021atwr changes in my series
>> - There is no need to add my SOB tag in your series as I was actually
>> not doing anything :)

Please go ahead and post any new patches that are required here now
that Bin's series has landed.

Regards,
Simon
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Re: [U-Boot] [PATCH v5 6/6] rockchip: kylin: Store env in emmc

2016-01-21 Thread Simon Glass
On 14 January 2016 at 10:17, Simon Glass  wrote:
> On 13 January 2016 at 19:19, Jeffy Chen  wrote:
>> There's a 64K reserved area at the end of the first 4M.
>> Store env there, so we can use fastboot to flash it.
>>
>> Signed-off-by: Jeffy Chen 
>>
>> ---
>>
>> Changes in v5:
>> New patch.
>>
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2: None
>>
>>  include/configs/kylin_rk3036.h | 12 
>>  1 file changed, 12 insertions(+)
>
> Acked-by: Simon Glass 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [PATCH 1/8] test/py: fix timeout to be absolute

2016-01-21 Thread Simon Glass
On 20 January 2016 at 15:15, Stephen Warren  wrote:
> From: Stephen Warren 
>
> Currently, Spawn.expect() imposes its timeout solely upon receipt of new
> data, not on its overall operation. In theory, this could cause the
> timeout not to fire if U-Boot continually generated output that did not
> match the expected patterns.
>
> Fix the code to additionally impose a timeout on overall operation, which
> is the intended mode of operation.
>
> Signed-off-by: Stephen Warren 
> ---
>  test/py/u_boot_spawn.py | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH 7/8] test/py: ums: add filesystem-based testing

2016-01-21 Thread Simon Glass
On 21 January 2016 at 04:26, Lukasz Majewski  wrote:
> Hi Stephen,
>
>> From: Stephen Warren 
>>
>> Enhance the UMS test to optionally mount a partition and read/write a
>> file to it, validating that the content written and read back are
>> identical.
>>
>> This enhancement is backwards-compatible; old boardenv contents that
>> don't define the new configuration data will cause the test code to
>> perform as before.
>>
>> test/ums/ is deleted since the Python test now performs the same
>> testing that it did.
>>
>> The code is also re-written to make use of the recently added utility
>> module, and split it up into nested functions so the overall logic of
>> the test process can be followed more easily without the details
>> cluttering the code.
>>
>> Cc: Lukasz Majewski 
>> Signed-off-by: Stephen Warren 
>> ---
>>  test/py/tests/test_ums.py   | 212
>> +++-
>> test/ums/README |  30 --- test/ums/ums_gadget_test.sh
>> | 183 -- 3 files changed, 169
>> insertions(+), 256 deletions(-) delete mode 100644 test/ums/README
>>  delete mode 100755 test/ums/ums_gadget_test.sh
>>

Acked-by: Simon Glass 
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Re: [U-Boot] [PATCH] pci: restore initialization for DM_PCI

2016-01-21 Thread Simon Glass
Hi,

On 21 January 2016 at 18:39, Bin Meng  wrote:
> Hi Stephen,
>
> On Fri, Jan 22, 2016 at 7:35 AM, Stephen Warren  wrote:
>> From: Stephen Warren 
>>
>> PCI controllers should be enumerated at startup so that PCI devices
>> such as Ethernet controllers are available at startup. Fix board_init_r()
>> not to skip calling pci_init() when CONFIG_DM_PCI is defined, and provide
>> an implementation of pci_init() for the DM case.
>>
>
> What exact issue are you trying to fix? I posted the same question on
> Simon's patch [1] before. Does your patch and Simon's fix the same
> issue?
>
> Note I submitted a similar patch [2] last year for x86 only, to
> explicitly trigger the PCI enueration. But it was not accepted.
>
>> Fixes: 96350f729c42 ("dm: tegra: net: Convert tegra boards to driver model
>> for Ethernet")
>> Signed-off-by: Stephen Warren 
>> ---
>> I'm not sure if relying on the side-effects of calling
>> uclass_{first,ext}_device is the correct approach; is there a more explicit
>> way to probe all PCI controllers?
>>
>> Arguably, perhaps we should introduce a "pci start" command instead of
>> this change to be consistent with e.g. USB. However, that would be a
>> regression relative to earlier versions of U-Boot.
>> ---
>
> [1] http://patchwork.ozlabs.org/patch/569323/
> [2] http://patchwork.ozlabs.org/patch/500246/
>
> Regards,
> Bin

This does go against the driver-model philosophy of lazy init. I
wonder if we should add this patch with a Kconfig option to enable it?
Then it can be enabled only for boards that need it.

Regards
Simon
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Re: [U-Boot] [PATCH 6/8] test/py: add various utility code

2016-01-21 Thread Simon Glass
Hi Stephen,

On 20 January 2016 at 15:15, Stephen Warren  wrote:
> From: Stephen Warren 
>
> Add various common utility functions. These will be used by a forthcoming
> re-written UMS test, and a brand-new DFU test.
>
> Signed-off-by: Stephen Warren 
> ---
>  test/py/u_boot_console_base.py |  19 +
>  test/py/u_boot_utils.py| 171 
> +
>  2 files changed, 190 insertions(+)
>  create mode 100644 test/py/u_boot_utils.py

Acked-by: Simon Glass 

>
> diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py
> index 433bec6e9fdd..06f61f987180 100644
> --- a/test/py/u_boot_console_base.py
> +++ b/test/py/u_boot_console_base.py
> @@ -215,6 +215,25 @@ class ConsoleBase(object):
>  self.log.action('Sending Ctrl-C')
>  self.run_command(chr(3), wait_for_echo=False, send_nl=False)
>
> +def wait_for(self, text):
> +'''Wait for a pattern to be emitted by U-Boot.

I meant to say we should use """ for function comments to keep it
consistent with the rest of U-Boot. Maybe could adjust this in a
follow-on patch?

> +
> +This is useful when a long-running command such as "dfu" is 
> executing,
> +and it periodically emits some text that should show up at a specific
> +location in the log file.
> +
> +Args:
> +text: The text to wait for; either a string (containing raw text,
> +not a regular expression) or an re object.
> +
> +Returns:
> +Nothing.
> +'''
> +
> +if type(text) == type(''):
> +text = re.escape(text)
> +self.p.expect([text])

Does this potentially wait forever?

> +
>  def drain_console(self):
>  '''Read from and log the U-Boot console for a short time.
>
> diff --git a/test/py/u_boot_utils.py b/test/py/u_boot_utils.py
> new file mode 100644
> index ..539af618dbf2
> --- /dev/null
> +++ b/test/py/u_boot_utils.py
> @@ -0,0 +1,171 @@
> +# Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
> +#
> +# SPDX-License-Identifier: GPL-2.0
> +
> +# Utility code shared across multiple tests.
> +
> +import hashlib
> +import os
> +import os.path
> +import sys
> +import time
> +
> +def md5sum_data(data):
> +'''Calculate the MD5 hash of some data.
> +
> +Args:
> +data: The data to hash.
> +
> +Returns:
> +The hash of the data, as a binary string.
> +'''
> +
> +h = hashlib.md5()
> +h.update(data)
> +return h.digest()

Or just:

   return hashlib.md5().update(data).digest()

Regards,
Simon
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Re: [U-Boot] [PATCH] pci: restore initialization for DM_PCI

2016-01-21 Thread Simon Glass
Hi Bin,

On 21 January 2016 at 21:06, Bin Meng  wrote:
> Hi Simon,
>
> On Fri, Jan 22, 2016 at 12:03 PM, Simon Glass  wrote:
>> Hi Bin,
>>
>> On 21 January 2016 at 20:53, Bin Meng  wrote:
>>> On Fri, Jan 22, 2016 at 11:36 AM, Simon Glass  wrote:
 Hi,

 On 21 January 2016 at 18:39, Bin Meng  wrote:
> Hi Stephen,
>
> On Fri, Jan 22, 2016 at 7:35 AM, Stephen Warren  
> wrote:
>> From: Stephen Warren 
>>
>> PCI controllers should be enumerated at startup so that PCI devices
>> such as Ethernet controllers are available at startup. Fix board_init_r()
>> not to skip calling pci_init() when CONFIG_DM_PCI is defined, and provide
>> an implementation of pci_init() for the DM case.
>>
>
> What exact issue are you trying to fix? I posted the same question on
> Simon's patch [1] before. Does your patch and Simon's fix the same
> issue?
>
> Note I submitted a similar patch [2] last year for x86 only, to
> explicitly trigger the PCI enueration. But it was not accepted.
>
>> Fixes: 96350f729c42 ("dm: tegra: net: Convert tegra boards to driver 
>> model
>> for Ethernet")
>> Signed-off-by: Stephen Warren 
>> ---
>> I'm not sure if relying on the side-effects of calling
>> uclass_{first,ext}_device is the correct approach; is there a more 
>> explicit
>> way to probe all PCI controllers?
>>
>> Arguably, perhaps we should introduce a "pci start" command instead of
>> this change to be consistent with e.g. USB. However, that would be a
>> regression relative to earlier versions of U-Boot.
>> ---
>
> [1] http://patchwork.ozlabs.org/patch/569323/
> [2] http://patchwork.ozlabs.org/patch/500246/
>
> Regards,
> Bin

 This does go against the driver-model philosophy of lazy init. I
 wonder if we should add this patch with a Kconfig option to enable it?
 Then it can be enabled only for boards that need it.

>>>
>>> I suspect the issue is somewhere else. On Intel Galileo with a PCI
>>> ethernet, it works fine without such explicit pci init. Which PCI
>>> ethernet driver does not work on Tegra?
>>
>> It could be because that board probes PCI to get its serial to work.
>
> Even if it does not have a PCI serial, the PCI ethernet driver should
> still have a chance to get PCI bus probe by calling one of these DM
> PCI APIs. See an example in eth_designware.c. That's why I'd like to
> know which PCI ethernet driver is this?

Well beaver uses RTL8169. But unless the driver is bound, it won't be
visible to the Ethernet stack.

>
>>
>> This could be fixed on Tegra by adding an Ethernet node to the device
>> tree to cause it to be probed. But I don't think that should be a
>> requirement.
>>
>
> Regards,
> Bin
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Re: [U-Boot] [PATCH] pci: restore initialization for DM_PCI

2016-01-21 Thread Tom Rini
On Thu, Jan 21, 2016 at 04:35:33PM -0700, Stephen Warren wrote:

> From: Stephen Warren 
> 
> PCI controllers should be enumerated at startup so that PCI devices
> such as Ethernet controllers are available at startup. Fix board_init_r()
> not to skip calling pci_init() when CONFIG_DM_PCI is defined, and provide
> an implementation of pci_init() for the DM case.
> 
> Fixes: 96350f729c42 ("dm: tegra: net: Convert tegra boards to driver model
> for Ethernet")
> Signed-off-by: Stephen Warren 
> ---
> I'm not sure if relying on the side-effects of calling
> uclass_{first,ext}_device is the correct approach; is there a more explicit
> way to probe all PCI controllers?
> 
> Arguably, perhaps we should introduce a "pci start" command instead of
> this change to be consistent with e.g. USB. However, that would be a
> regression relative to earlier versions of U-Boot.

So it's a good discussion to have.  In the U-Boot world, can we have
cases where we need PCI up before we could reasonably make use of
CONFIG_PREBOOT to ensure the board is in a good enough state to use for
most use cases?

-- 
Tom


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[U-Boot] [PATCH v9 14/49] rockchip: Use a separate clock ID for clocks

2016-01-21 Thread Simon Glass
At present we use the same peripheral ID for clocks and pinctrl. While this
works it is probably better to use the device tree clock binding ID for
clocks. We can use the clk_get_by_index() function to find this.

Update the clock drivers and the code that uses them.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2:
- Update call to clk_get_by_index()

 configs/chromebook_jerry_defconfig |  1 +
 configs/firefly-rk3288_defconfig   |  1 +
 drivers/clk/clk_rk3036.c   | 16 +-
 drivers/clk/clk_rk3288.c   | 63 +-
 drivers/mmc/rockchip_dw_mmc.c  | 13 +++-
 5 files changed, 50 insertions(+), 44 deletions(-)

diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index 456b6ea..5535105 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -12,6 +12,7 @@ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent"
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index f41c241..5b26a3d 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -12,6 +12,7 @@ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent"
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
diff --git a/drivers/clk/clk_rk3036.c b/drivers/clk/clk_rk3036.c
index f650810..dfecc24 100644
--- a/drivers/clk/clk_rk3036.c
+++ b/drivers/clk/clk_rk3036.c
@@ -13,8 +13,8 @@
 #include 
 #include 
 #include 
-#include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -233,19 +233,19 @@ static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru,
 }
 
 static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint 
clk_general_rate,
- enum periph_id periph)
+ int periph)
 {
uint src_rate;
uint div, mux;
u32 con;
 
switch (periph) {
-   case PERIPH_ID_EMMC:
+   case HCLK_EMMC:
con = readl(>cru_clksel_con[12]);
mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
break;
-   case PERIPH_ID_SDCARD:
+   case HCLK_SDIO:
con = readl(>cru_clksel_con[12]);
mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
@@ -259,7 +259,7 @@ static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, 
uint clk_general_rate,
 }
 
 static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint 
clk_general_rate,
- enum periph_id periph, uint freq)
+ int periph, uint freq)
 {
int src_clk_div;
int mux;
@@ -277,14 +277,14 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, 
uint clk_general_rate,
}
 
switch (periph) {
-   case PERIPH_ID_EMMC:
+   case HCLK_EMMC:
rk_clrsetreg(>cru_clksel_con[12],
 EMMC_PLL_MASK << EMMC_PLL_SHIFT |
 EMMC_DIV_MASK << EMMC_DIV_SHIFT,
 mux << EMMC_PLL_SHIFT |
 (src_clk_div - 1) << EMMC_DIV_SHIFT);
break;
-   case PERIPH_ID_SDCARD:
+   case HCLK_SDIO:
rk_clrsetreg(>cru_clksel_con[11],
 MMC0_PLL_MASK << MMC0_PLL_SHIFT |
 MMC0_DIV_MASK << MMC0_DIV_SHIFT,
@@ -320,7 +320,7 @@ static ulong rk3036_set_periph_rate(struct udevice *dev, 
int periph, ulong rate)
ulong new_rate;
 
switch (periph) {
-   case PERIPH_ID_EMMC:
+   case HCLK_EMMC:
new_rate = rockchip_mmc_set_clk(priv->cru, clk_get_rate(dev),
periph, rate);
break;
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index 0172ad1..e410e7d1 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -14,7 +14,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -364,24 +364,24 @@ static ulong rk3288_clk_set_rate(struct udevice *dev, 
ulong rate)
 }
 
 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint 
clk_general_rate,
- enum periph_id periph)
+ int periph)
 {
uint src_rate;
uint div, mux;
u32 con;
 
switch (periph) {
-   case PERIPH_ID_EMMC:
+   case HCLK_EMMC:
con = readl(>cru_clksel_con[12]);

[U-Boot] [PATCH v9 43/49] rockchip: pinctrl: Implement the get_gpio_mux() method

2016-01-21 Thread Simon Glass
Implement this so that the GPIO command will be able to report whether a
GPIO is used for input or output.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/pinctrl/rockchip/pinctrl_rk3288.c | 68 +++
 1 file changed, 52 insertions(+), 16 deletions(-)

diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c 
b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
index 53b8cf2..8356786 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
@@ -520,18 +520,16 @@ static int rk3288_pinctrl_set_state_simple(struct udevice 
*dev,
 }
 
 #ifndef CONFIG_SPL_BUILD
-static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
-  int muxval, int flags)
+int rk3288_pinctrl_get_pin_info(struct rk3288_pinctrl_priv *priv,
+   int banknum, int ind, u32 **addrp, uint *shiftp,
+   uint *maskp)
 {
-   struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
struct rockchip_pin_bank *bank = _pin_banks[banknum];
-   uint shift, muxnum, ind = index;
+   uint muxnum;
u32 *addr;
 
-   debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
for (muxnum = 0; muxnum < 4; muxnum++) {
struct rockchip_iomux *mux = >iomux[muxnum];
-   uint mask;
 
if (ind >= 8) {
ind -= 8;
@@ -543,24 +541,61 @@ static int rk3288_pinctrl_set_pins(struct udevice *dev, 
int banknum, int index,
else
addr = (u32 *)priv->grf - 4;
addr += mux->offset;
-   shift = ind & 7;
+   *shiftp = ind & 7;
if (mux->type & IOMUX_WIDTH_4BIT) {
-   mask = 0xf;
-   shift *= 4;
-   if (shift >= 16) {
-   shift -= 16;
+   *maskp = 0xf;
+   *shiftp *= 4;
+   if (*shiftp >= 16) {
+   *shiftp -= 16;
addr++;
}
} else {
-   mask = 3;
-   shift *= 2;
+   *maskp = 3;
+   *shiftp *= 2;
}
 
debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr,
- mask, shift);
-   rk_clrsetreg(addr, mask << shift, muxval << shift);
-   break;
+ *maskp, *shiftp);
+   *addrp = addr;
+   return 0;
}
+
+   return -EINVAL;
+}
+
+static int rk3288_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
+  int index)
+{
+   struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
+   uint shift;
+   uint mask;
+   u32 *addr;
+   int ret;
+
+   ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, , ,
+ );
+   if (ret)
+   return ret;
+   return (readl(addr) & mask) >> shift;
+}
+
+static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
+  int muxval, int flags)
+{
+   struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
+   uint shift, ind = index;
+   uint mask;
+   u32 *addr;
+   int ret;
+
+   debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
+   ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, , ,
+ );
+   if (ret)
+   return ret;
+   rk_clrsetreg(addr, mask << shift, muxval << shift);
+
+   /* Handle pullup/pulldown */
if (flags) {
uint val = 0;
 
@@ -618,6 +653,7 @@ static int rk3288_pinctrl_set_state(struct udevice *dev, 
struct udevice *config)
 static struct pinctrl_ops rk3288_pinctrl_ops = {
 #ifndef CONFIG_SPL_BUILD
.set_state  = rk3288_pinctrl_set_state,
+   .get_gpio_mux   = rk3288_pinctrl_get_gpio_mux,
 #endif
.set_state_simple   = rk3288_pinctrl_set_state_simple,
.request= rk3288_pinctrl_request,
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 26/49] rockchip: jerry: Drop unused options

2016-01-21 Thread Simon Glass
To reduce the SPL image size, drop the LED features. Jerry does not have
an LED and we can leave out GPIO support also.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 configs/chromebook_jerry_defconfig | 5 -
 include/configs/chromebook_jerry.h | 2 ++
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index 99f6161..ceec6f5 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -22,9 +22,6 @@ CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_LED=y
-CONFIG_SPL_LED=y
-CONFIG_LED_GPIO=y
 CONFIG_PWRSEQ=y
 CONFIG_RESET=y
 CONFIG_DM_MMC=y
@@ -34,10 +31,8 @@ CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_FULL is not set
 CONFIG_ROCKCHIP_PINCTRL=y
 CONFIG_DM_PMIC=y
-CONFIG_PMIC_ACT8846=y
 CONFIG_PMIC_RK808=y
 CONFIG_DM_REGULATOR=y
-CONFIG_REGULATOR_ACT8846=y
 CONFIG_REGULATOR_RK808=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
diff --git a/include/configs/chromebook_jerry.h 
b/include/configs/chromebook_jerry.h
index e29d776..78c06af 100644
--- a/include/configs/chromebook_jerry.h
+++ b/include/configs/chromebook_jerry.h
@@ -15,4 +15,6 @@
 #define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SPI_FLASH_GIGADEVICE
 
+#undef CONFIG_SPL_GPIO_SUPPORT
+
 #endif
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 05/37] video: bridge: Allow GPIOs to be optional

2016-01-21 Thread Simon Glass
Some video bridges will not have GPIOs to control reset, etc. Allow these
to be optional.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 drivers/video/bridge/video-bridge-uclass.c | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/video/bridge/video-bridge-uclass.c 
b/drivers/video/bridge/video-bridge-uclass.c
index 6c5990f..07270ba 100644
--- a/drivers/video/bridge/video-bridge-uclass.c
+++ b/drivers/video/bridge/video-bridge-uclass.c
@@ -55,7 +55,8 @@ static int video_bridge_pre_probe(struct udevice *dev)
   _priv->sleep, GPIOD_IS_OUT);
if (ret) {
debug("%s: Could not decode sleep-gpios (%d)\n", __func__, ret);
-   return ret;
+   if (ret != -ENOENT)
+   return ret;
}
/*
 * Drop this for now as we do not have driver model pinctrl support
@@ -70,7 +71,8 @@ static int video_bridge_pre_probe(struct udevice *dev)
   GPIOD_IS_OUT);
if (ret) {
debug("%s: Could not decode reset-gpios (%d)\n", __func__, ret);
-   return ret;
+   if (ret != -ENOENT)
+   return ret;
}
/*
 * Drop this for now as we do not have driver model pinctrl support
@@ -83,9 +85,10 @@ static int video_bridge_pre_probe(struct udevice *dev)
 */
ret = gpio_request_by_name(dev, "hotplug-gpios", 0, _priv->hotplug,
   GPIOD_IS_IN);
-   if (ret && ret != -ENOENT) {
+   if (ret) {
debug("%s: Could not decode hotplug (%d)\n", __func__, ret);
-   return ret;
+   if (ret != -ENOENT)
+   return ret;
}
 
return 0;
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 32/37] rockchip: firefly-rk3288: Enable HDMI output

2016-01-21 Thread Simon Glass
Enable HDMI output and a console on firefly.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 configs/firefly-rk3288_defconfig | 7 +++
 include/configs/firefly-rk3288.h | 9 -
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index d8db532..15eb4d8 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -32,9 +32,13 @@ CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_FULL is not set
 CONFIG_ROCKCHIP_PINCTRL=y
 CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_ACT8846=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_REGULATOR_ACT8846=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_DEBUG_UART=y
@@ -42,6 +46,9 @@ CONFIG_DEBUG_UART_BASE=0xff69
 CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_ROTATION=y
+CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
diff --git a/include/configs/firefly-rk3288.h b/include/configs/firefly-rk3288.h
index 8ac6521..d6423e7 100644
--- a/include/configs/firefly-rk3288.h
+++ b/include/configs/firefly-rk3288.h
@@ -7,7 +7,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define ROCKCHIP_DEVICE_SETTINGS
+#define ROCKCHIP_DEVICE_SETTINGS \
+   "stdin=serial,cros-ec-keyb\0" \
+   "stdout=serial,vidconsole\0" \
+   "stderr=serial,vidconsole\0"
 
 #include 
 
@@ -21,4 +24,8 @@
  */
 #define CONFIG_ENV_OFFSET (96 * 1024)
 
+#define CONFIG_I2C_EDID
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES10
+
 #endif
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 08/37] dm: backlight: Add a backlight uclass

2016-01-21 Thread Simon Glass
LCD panels normally have a backlight which can be controlled to illuminate
the LCD contents. Add a uclass to support this. Initially it only has a
method to enable the backlight.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 drivers/video/Makefile   |  1 +
 drivers/video/backlight-uclass.c | 25 +
 include/backlight.h  | 31 +++
 include/dm/uclass-id.h   |  1 +
 4 files changed, 58 insertions(+)
 create mode 100644 drivers/video/backlight-uclass.c
 create mode 100644 include/backlight.h

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index ee04629..fa90721 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -7,6 +7,7 @@
 
 ifdef CONFIG_DM
 obj-$(CONFIG_DISPLAY_PORT) += dp-uclass.o
+obj-$(CONFIG_DM_VIDEO) += backlight-uclass.o
 obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o console_normal.o
 obj-$(CONFIG_DM_VIDEO) += video_bmp.o
 obj-$(CONFIG_VIDEO_ROTATION) += console_rotate.o
diff --git a/drivers/video/backlight-uclass.c b/drivers/video/backlight-uclass.c
new file mode 100644
index 000..0238289
--- /dev/null
+++ b/drivers/video/backlight-uclass.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+int backlight_enable(struct udevice *dev)
+{
+   const struct backlight_ops *ops = backlight_get_ops(dev);
+
+   if (!ops->enable)
+   return -ENOSYS;
+
+   return ops->enable(dev);
+}
+
+UCLASS_DRIVER(backlight) = {
+   .id = UCLASS_PANEL_BACKLIGHT,
+   .name   = "backlight",
+};
diff --git a/include/backlight.h b/include/backlight.h
new file mode 100644
index 000..90e1d98
--- /dev/null
+++ b/include/backlight.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ * Written by Simon Glass 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _BACKLIGHT_H
+#define _BACKLIGHT_H
+
+struct backlight_ops {
+   /**
+* enable() - Enable a backlight
+*
+* @dev:Backlight device to enable
+* @return 0 if OK, -ve on error
+*/
+   int (*enable)(struct udevice *dev);
+};
+
+#define backlight_get_ops(dev) ((struct backlight_ops *)(dev)->driver->ops)
+
+/**
+ * backlight_enable() - Enable a backlight
+ *
+ * @dev:   Backlight device to enable
+ * @return 0 if OK, -ve on error
+ */
+int backlight_enable(struct udevice *dev);
+
+#endif
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 8f0381d..5421981 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -45,6 +45,7 @@ enum uclass_id {
UCLASS_MMC, /* SD / MMC card or chip */
UCLASS_MOD_EXP, /* RSA Mod Exp device */
UCLASS_MTD, /* Memory Technology Device (MTD) device */
+   UCLASS_PANEL_BACKLIGHT, /* Backlight controller for panel */
UCLASS_PCH, /* x86 platform controller hub */
UCLASS_PCI, /* PCI bus */
UCLASS_PCI_GENERIC, /* Generic PCI bus device */
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 21/37] rockchip: config: Enable the 'gpio' command

2016-01-21 Thread Simon Glass
Now that we have a pretty good GPIO driver, enable the 'gpio' command on all
rockchip boards.

Signed-off-by: Simon Glass 
---

Changes in v2: None

 include/configs/rk3288_common.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index b9ff5a5..ebf1ab0 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -79,6 +79,7 @@
 
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_TIME
+#define CONFIG_CMD_GPIO
 
 #define CONFIG_SYS_SDRAM_BASE  0
 #define CONFIG_NR_DRAM_BANKS   1
-- 
2.7.0.rc3.207.g0ac5344

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Re: [U-Boot] [PATCH v2] clk: add fixed rate clock driver

2016-01-21 Thread Simon Glass
On 19 January 2016 at 21:35, Simon Glass  wrote:
> On 18 January 2016 at 21:55, Masahiro Yamada
>  wrote:
>> This commit intends to implement "fixed-clock" as in Linux.
>> (drivers/clk/clk-fixed-rate.c in Linux)
>>
>> If you need a very simple clock to just provide fixed clock rate
>> like a crystal oscillator, you do not have to write a new driver.
>> This driver can support it.
>>
>> Signed-off-by: Masahiro Yamada 
>> ---
>>
>> Changes in v2:
>>   - Change file name from clk-fixed-rate.c to clk_fixed-rate.c
>>   - Use .ofdata_to_platdata method instead of .probe
>>   - Change driver name "Fixed Rate Clock" to "fixed_rate_clock"
>>
>>  drivers/clk/Makefile |  2 +-
>>  drivers/clk/clk_fixed_rate.c | 57 
>> 
>>  2 files changed, 58 insertions(+), 1 deletion(-)
>>  create mode 100644 drivers/clk/clk_fixed_rate.c
>
> Acked-by: Simon Glass 

Applied to u-boot-rockchip, thanks!
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Re: [U-Boot] [PATCH v2 3/3] tpm: st33zp24: Add tpm st33zp24 spi support

2016-01-21 Thread Simon Glass
On 21 January 2016 at 15:27, Christophe Ricard
 wrote:
> Add support for TPM ST33ZP24 spi.
>
> The ST33ZP24 does have a spi interface.
> The transport protocol is proprietary.
>
> For spi we are relying only on DM_SPI.
>
> Reviewed-by: Simon Glass 
> Signed-off-by: Christophe Ricard 
> ---
>
> Changes in v2:
> - Adding Reviewed-by: Simon Glass 
>
>  README |   4 +
>  drivers/tpm/Kconfig|   9 +
>  drivers/tpm/Makefile   |   1 +
>  drivers/tpm/tpm_tis_st33zp24_spi.c | 672 
> +
>  4 files changed, 686 insertions(+)
>  create mode 100644 drivers/tpm/tpm_tis_st33zp24_spi.c

Applied to u-boot-dm, thanks!

(please enable this for your board in a subsequent patch, as this is
dead code at present)
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Re: [U-Boot] [PATCH v2 2/2] tpm: tpm_tis_lpc: fix typo

2016-01-21 Thread Simon Glass
On 21 January 2016 at 15:19, Christophe Ricard
 wrote:
> TPM_TIS_LPC is connected to the LPC bus, not I2C.
>
> Reviewed-by: Simon Glass 
> Signed-off-by: Christophe Ricard 
> ---
>
> Changes in v2:
> - Adding Reviewed-by: Simon Glass 
>
>  drivers/tpm/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Applied to u-boot-dm, thanks!
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Re: [U-Boot] [PATCH v2 2/3] tpm: st33zp24: Add tpm st33zp24 support with i2c

2016-01-21 Thread Simon Glass
On 21 January 2016 at 15:27, Christophe Ricard
 wrote:
> Add support for TPM ST33ZP24 family with i2c.
>
> For i2c we are relying only on DM_I2C.
>
> Reviewed-by: Simon Glass 
> Signed-off-by: Christophe Ricard 
> ---
>
> Changes in v2:
> - Adding Reviewed-by: Simon Glass 
>
>  README |   7 +
>  drivers/tpm/Kconfig|   9 +
>  drivers/tpm/Makefile   |   1 +
>  drivers/tpm/tpm_tis_st33zp24_i2c.c | 543 
> +
>  4 files changed, 560 insertions(+)
>  create mode 100644 drivers/tpm/tpm_tis_st33zp24_i2c.c

Applied to u-boot-dm, thanks!

(please enable this for your board in a subsequent patch, as this is
dead code at present)
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Re: [U-Boot] [Patch V5 2/4] spi: fsl_qspi: Fix qspi_op_rdid memcpy issue

2016-01-21 Thread Qianyu Gong

> -Original Message-
> From: Scott Wood
> Sent: Friday, January 22, 2016 3:30 AM
> To: Qianyu Gong ; u-boot@lists.denx.de;
> r58...@freescale.com
> Cc: mingkai...@freescale.com; jt...@openedev.com; b48...@freescale.com;
> shaohui@freescale.com; wenbin.s...@freescale.com; Scott Wood
> ; Gong Qianyu 
> Subject: Re: [Patch V5 2/4] spi: fsl_qspi: Fix qspi_op_rdid memcpy issue
> 
> On 01/20/2016 09:43 PM, Gong Qianyu wrote:
> > From: Gong Qianyu 
> >
> > In current driver everytime we memcpy 4 bytes to the dest memory
> > regardless of the remaining length.
> > This patch adds checking the remaining length before memcpy.
> > If the length is shorter than 4 bytes, memcpy the actual length of
> > data to the dest memory.
> >
> > Signed-off-by: Gong Qianyu 
> > ---
> > V2-V5:
> >  - No change.
> >
> >  drivers/spi/fsl_qspi.c | 5 -
> >  1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index
> > 38e5900..f178857 100644
> > --- a/drivers/spi/fsl_qspi.c
> > +++ b/drivers/spi/fsl_qspi.c
> > @@ -500,7 +500,10 @@ static void qspi_op_rdid(struct fsl_qspi_priv *priv, 
> > u32
> *rxbuf, u32 len)
> > if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
> > data = qspi_read32(priv->flags, >rbdr[i]);
> > data = qspi_endian_xchg(data);
> > -   memcpy(rxbuf, , 4);
> > +   if (size < 4)
> > +   memcpy(rxbuf, , size);
> > +   else
> > +   memcpy(rxbuf, , 4);
> 
> memcpy(rxbuf, , min(size, 4));
> 
> > rxbuf++;
> > size -= 4;
> > i++;
> 
> size -= 4 even if size was < 4?
> 
> -Scott

Yes.. The following is complete code:

i = 0;
size = len;
while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
rbsr_reg = qspi_read32(priv->flags, >rbsr);
if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
data = qspi_read32(priv->flags, >rbdr[i]);
data = qspi_endian_xchg(data);
memcpy(rxbuf, , min(size, 4));
rxbuf++;
size -= 4;
i++;
}
}


Regards,
Qianyu
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[U-Boot] [PATCH 7/7] usb: dwc2: Do not mix data toggle for IN and OUT endpoints, check bounds

2016-01-21 Thread Stefan Brüns
USB protocol allows for 16 IN and 16 OUT endpoints (USB 2.0 Spec,
8.3.2.2 Endpoint Field). A function may have an EP 1 for both IN and OUT,
so these two should be kept separate. As EPs are either BULK or INTERRUPT
(or ISO), it is fine to have one array per direction for all transfer
types (also see e236519b7365ef75c5da6a5623f0b03d9c00cfae).

USB device address is 7 bits, so a bus may have more than 16 devices.
Check the device number, as the DWC2 driver only supports BULK/ISO for
the first 16 devices.

Signed-off-by: Stefan Brüns 
---
 drivers/usb/host/dwc2.c | 29 +++--
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 291e4a5..7c107bc 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -34,7 +34,8 @@ struct dwc2_priv {
uint8_t *aligned_buffer;
uint8_t *status_buffer;
 #endif
-   int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
+   uint8_t in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
+   uint8_t out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
struct dwc2_core_regs *regs;
int root_hub_devnum;
 };
@@ -739,7 +740,7 @@ static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, 
struct usb_device *dev,
return stat;
 }
 
-int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, int *toggle)
+int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, uint8_t 
*toggle)
 {
int ret;
uint32_t hcint, hctsiz;
@@ -775,7 +776,7 @@ static int dwc2_eptype[] = {
 };
 
 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
- int *pid, int in, void *buffer, int num_packets,
+ uint8_t *pid, int in, void *buffer, int num_packets,
  int xfer_len, int *actual_len, int odd_frame)
 {
int ret = 0;
@@ -829,7 +830,7 @@ static int transfer_chunk(struct dwc2_hc_regs *hc_regs, 
void *aligned_buffer,
 }
 
 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
- unsigned long pipe, int *pid, int in, void *buffer, int len)
+ unsigned long pipe, uint8_t *pid, int in, void *buffer, int len)
 {
struct dwc2_core_regs *regs = priv->regs;
struct dwc2_hc_regs *hc_regs = >hc_regs[DWC2_HC_CHANNEL];
@@ -960,14 +961,19 @@ int _submit_bulk_msg(struct dwc2_priv *priv, struct 
usb_device *dev,
 {
int devnum = usb_pipedevice(pipe);
int ep = usb_pipeendpoint(pipe);
+   uint8_t* pid;
 
-   if (devnum == priv->root_hub_devnum) {
+   if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
dev->status = 0;
return -EINVAL;
}
 
-   return chunk_msg(priv, dev, pipe, >bulk_data_toggle[devnum][ep],
-usb_pipein(pipe), buffer, len);
+   if (usb_pipein(pipe))
+   pid = >in_data_toggle[devnum][ep];
+   else
+   pid = >out_data_toggle[devnum][ep];
+
+   return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
 }
 
 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
@@ -975,7 +981,8 @@ static int _submit_control_msg(struct dwc2_priv *priv, 
struct usb_device *dev,
   struct devrequest *setup)
 {
int devnum = usb_pipedevice(pipe);
-   int pid, ret, act_len;
+   int ret, act_len;
+   uint8_t pid;
/* For CONTROL endpoint pid should start with DATA1 */
int status_direction;
 
@@ -1075,8 +1082,10 @@ static int dwc2_init_common(struct dwc2_priv *priv)
 DWC2_HPRT0_PRTRST);
 
for (i = 0; i < MAX_DEVICE; i++) {
-   for (j = 0; j < MAX_ENDPOINT; j++)
-   priv->bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
+   for (j = 0; j < MAX_ENDPOINT; j++) {
+   priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
+   priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
+   }
}
 
return 0;
-- 
2.1.4

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[U-Boot] [PATCH v9 12/49] rockchip: Use pwrseq for MMC start-up on jerry

2016-01-21 Thread Simon Glass
This is defined in the device tree in Linux. Copy over the settings so that
this can be used instead of hard-coding the reset line.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 arch/arm/dts/rk3288-veyron.dtsi| 15 +++
 configs/chromebook_jerry_defconfig |  1 +
 include/configs/rk3288_common.h|  1 +
 3 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi
index 7e37158..12404ff 100644
--- a/arch/arm/dts/rk3288-veyron.dtsi
+++ b/arch/arm/dts/rk3288-veyron.dtsi
@@ -106,6 +106,13 @@
priority = /bits/ 8 <200>;
};
 
+   emmc_pwrseq: emmc-pwrseq {
+   compatible = "mmc-pwrseq-emmc";
+   pinctrl-0 = <_reset>;
+   pinctrl-names = "default";
+   reset-gpios = < 9 GPIO_ACTIVE_HIGH>;
+   };
+
sound {
compatible = "rockchip,rockchip-audio-max98090";
rockchip,model = "ROCKCHIP-I2S";
@@ -259,11 +266,12 @@
bus-width = <8>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
+   mmc-pwrseq = <_pwrseq>;
disable-wp;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
-   pinctrl-0 = <_clk _cmd _bus8 _deassert_reset>;
+   pinctrl-0 = <_clk _cmd _bus8 _pwr>;
status = "okay";
 };
 
@@ -671,9 +679,8 @@
};
 
emmc {
-   /* Make sure eMMC is not in reset */
-   emmc_deassert_reset: emmc-deassert-reset {
-   rockchip,pins = <7 12 RK_FUNC_GPIO _pull_up>;
+   emmc_reset: emmc-reset {
+   rockchip,pins = <2 9 RK_FUNC_GPIO _pull_none>;
};
 
/*
diff --git a/configs/chromebook_jerry_defconfig 
b/configs/chromebook_jerry_defconfig
index 39cd9d6..456b6ea 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -23,6 +23,7 @@ CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_LED=y
 CONFIG_SPL_LED=y
 CONFIG_LED_GPIO=y
+CONFIG_PWRSEQ=y
 CONFIG_RESET=y
 CONFIG_DM_MMC=y
 CONFIG_ROCKCHIP_DWMMC=y
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 238711a..f47573b 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -26,6 +26,7 @@
 #define CONFIG_SYS_TIMER_COUNTER   (CONFIG_SYS_TIMER_BASE + 8)
 
 #define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 07/49] dm: Add a power sequencing uclass

2016-01-21 Thread Simon Glass
Some devices need special sequences to be used when starting up. Add a
uclass for this. Drivers can be added to provide specific features as
needed.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/misc/Kconfig | 18 ++
 drivers/misc/Makefile|  1 +
 drivers/misc/pwrseq-uclass.c | 24 
 include/dm/uclass-id.h   |  1 +
 include/pwrseq.h | 18 ++
 5 files changed, 62 insertions(+)
 create mode 100644 drivers/misc/pwrseq-uclass.c
 create mode 100644 include/pwrseq.h

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index b92da4e..cba2363 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -90,6 +90,24 @@ config MXC_OCOTP
  Programmable memory pages that are stored on the some
  Freescale i.MX processors.
 
+config PWRSEQ
+   bool "Enable power-sequencing drivers"
+   depends on DM
+   help
+ Power-sequencing drivers provide support for controlling power for
+ devices. They are typically referenced by a phandle from another
+ device. When the device is started up, its power sequence can be
+ initiated.
+
+config SPL_PWRSEQ
+   bool "Enable power-sequencing drivers for SPL"
+   depends on PWRSEQ
+   help
+ Power-sequencing drivers provide support for controlling power for
+ devices. They are typically referenced by a phandle from another
+ device. When the device is started up, its power sequence can be
+ initiated.
+
 config PCA9551_LED
bool "Enable PCA9551 LED driver"
help
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index aa137f5..fc8eb6f 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
 obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
 obj-$(CONFIG_NS87308) += ns87308.o
 obj-$(CONFIG_PDSP188x) += pdsp188x.o
+obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
 obj-$(CONFIG_SANDBOX) += reset_sandbox.o
 ifdef CONFIG_DM_I2C
 obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
diff --git a/drivers/misc/pwrseq-uclass.c b/drivers/misc/pwrseq-uclass.c
new file mode 100644
index 000..8ed2ad4
--- /dev/null
+++ b/drivers/misc/pwrseq-uclass.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+int pwrseq_set_power(struct udevice *dev, bool enable)
+{
+   struct pwrseq_ops *ops = pwrseq_get_ops(dev);
+
+   if (!ops->set_power)
+   return -ENOSYS;
+
+   return ops->set_power(dev, enable);
+}
+
+UCLASS_DRIVER(pwrseq) = {
+   .id = UCLASS_PWRSEQ,
+   .name   = "pwrseq",
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index a0a3a79..b5f43ae 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -51,6 +51,7 @@ enum uclass_id {
UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */
UCLASS_PINCONFIG,   /* Pin configuration node device */
UCLASS_PMIC,/* PMIC I/O device */
+   UCLASS_PWRSEQ,  /* Power sequence device */
UCLASS_REGULATOR,   /* Regulator device */
UCLASS_RESET,   /* Reset device */
UCLASS_REMOTEPROC,  /* Remote Processor device */
diff --git a/include/pwrseq.h b/include/pwrseq.h
new file mode 100644
index 000..b934f29
--- /dev/null
+++ b/include/pwrseq.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __pwrseq_h
+#define __pwrseq_h
+
+struct pwrseq_ops {
+   int (*set_power)(struct udevice *dev, bool enable);
+};
+
+#define pwrseq_get_ops(dev)((struct pwrseq_ops *)(dev)->driver->ops)
+
+int pwrseq_set_power(struct udevice *dev, bool enable);
+
+#endif
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 34/49] dm: power: Tidy up debugging output and return values

2016-01-21 Thread Simon Glass
The currect PMIC debugging is a little confusing. Adjust it so that it is
clear whether the operation succeeded or failed. Also, avoid creating a new
error return value when a perfectly good one is already available.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/power/pmic/pmic-uclass.c   | 11 ---
 drivers/power/pmic/rk808.c | 14 ++
 drivers/power/regulator/regulator-uclass.c |  2 +-
 3 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/drivers/power/pmic/pmic-uclass.c b/drivers/power/pmic/pmic-uclass.c
index 8b19998..7211026 100644
--- a/drivers/power/pmic/pmic-uclass.c
+++ b/drivers/power/pmic/pmic-uclass.c
@@ -133,8 +133,9 @@ int pmic_reg_read(struct udevice *dev, uint reg)
u8 byte;
int ret;
 
+   debug("%s: reg=%x", __func__, reg);
ret = pmic_read(dev, reg, , 1);
-   debug("%s: reg=%x, value=%x\n", __func__, reg, byte);
+   debug(", value=%x, ret=%d\n", byte, ret);
 
return ret ? ret : byte;
 }
@@ -142,9 +143,13 @@ int pmic_reg_read(struct udevice *dev, uint reg)
 int pmic_reg_write(struct udevice *dev, uint reg, uint value)
 {
u8 byte = value;
+   int ret;
+
+   debug("%s: reg=%x, value=%x", __func__, reg, value);
+   ret = pmic_write(dev, reg, , 1);
+   debug(", ret=%d\n", ret);
 
-   debug("%s: reg=%x, value=%x\n", __func__, reg, value);
-   return pmic_write(dev, reg, , 1);
+   return ret;
 }
 
 int pmic_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set)
diff --git a/drivers/power/pmic/rk808.c b/drivers/power/pmic/rk808.c
index 11d5f07..770f471 100644
--- a/drivers/power/pmic/rk808.c
+++ b/drivers/power/pmic/rk808.c
@@ -30,9 +30,12 @@ static int rk808_reg_count(struct udevice *dev)
 static int rk808_write(struct udevice *dev, uint reg, const uint8_t *buff,
  int len)
 {
-   if (dm_i2c_write(dev, reg, buff, len)) {
+   int ret;
+
+   ret = dm_i2c_write(dev, reg, buff, len);
+   if (ret) {
debug("write error to device: %p register: %#x!", dev, reg);
-   return -EIO;
+   return ret;
}
 
return 0;
@@ -40,9 +43,12 @@ static int rk808_write(struct udevice *dev, uint reg, const 
uint8_t *buff,
 
 static int rk808_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
 {
-   if (dm_i2c_read(dev, reg, buff, len)) {
+   int ret;
+
+   ret = dm_i2c_read(dev, reg, buff, len);
+   if (ret) {
debug("read error from device: %p register: %#x!", dev, reg);
-   return -EIO;
+   return ret;
}
 
return 0;
diff --git a/drivers/power/regulator/regulator-uclass.c 
b/drivers/power/regulator/regulator-uclass.c
index 4241a4c..fec2886 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -178,7 +178,7 @@ static void regulator_show(struct udevice *dev, int ret)
printf("; set %d uA", uc_pdata->min_uA);
printf("; enabling");
if (ret)
-   printf(" (ret: %d)\n", ret);
+   printf(" (ret: %d)", ret);
printf("\n");
 }
 
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 31/49] dm: power: Allow regulators to be omitted from SPL

2016-01-21 Thread Simon Glass
For some boards the pmic interface is useful but the regulator interface
(which comes with it) is too large. Allow them to be separated such that
SPL can decide which it needs.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/power/pmic/Kconfig   | 21 +
 drivers/power/pmic/pmic-uclass.c |  2 ++
 drivers/power/regulator/Kconfig  |  9 +
 drivers/power/regulator/Makefile |  4 ++--
 4 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 8be3c07..7f69ae1 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -10,6 +10,27 @@ config DM_PMIC
- 'drivers/power/pmic/pmic-uclass.c'
- 'include/power/pmic.h'
 
+config PMIC_CHILDREN
+   bool "Allow child devices for PMICs"
+   depends on DM_PMIC
+   default y
+   ---help---
+   This allows PMICs to support child devices (such as regulators) in
+   SPL. This adds quite a bit of code so if you are not using this
+   feature you can turn it off. Most likely you should turn it on for
+   U-Boot proper.
+
+config SPL_PMIC_CHILDREN
+   bool "Allow child devices for PMICs in SPL"
+   depends on DM_PMIC
+   default y
+   ---help---
+   This allows PMICs to support child devices (such as regulators) in
+   SPL. This adds quite a bit of code so if you are not using this
+   feature you can turn it off. In this case you may need a 'back door'
+   to call your regulator code (e.g. see rk808.c for direct functions
+   for use in SPL).
+
 config PMIC_ACT8846
bool "Enable support for the active-semi 8846 PMIC"
depends on DM_PMIC && DM_I2C
diff --git a/drivers/power/pmic/pmic-uclass.c b/drivers/power/pmic/pmic-uclass.c
index 49709f3..8b19998 100644
--- a/drivers/power/pmic/pmic-uclass.c
+++ b/drivers/power/pmic/pmic-uclass.c
@@ -18,6 +18,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
 int pmic_bind_children(struct udevice *pmic, int offset,
   const struct pmic_child_info *child_info)
 {
@@ -84,6 +85,7 @@ int pmic_bind_children(struct udevice *pmic, int offset,
debug("Bound: %d childs for PMIC: '%s'\n", bind_count, pmic->name);
return bind_count;
 }
+#endif
 
 int pmic_get(const char *name, struct udevice **devp)
 {
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index 8f638a9..465ff3f 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -16,6 +16,15 @@ config DM_REGULATOR
for this purpose if PMIC I/O driver is implemented or dm_scan_fdt_node()
otherwise. Detailed information can be found in the header file.
 
+config SPL_DM_REGULATOR
+   bool "Enable regulators for SPL"
+   depends on DM_REGULATOR
+   ---help---
+   Regulators are seldom needed in SPL. Even if they are accessed, some
+   code space can be saved by accessing the PMIC registers directly.
+   Enable this option if you need regulators in SPL and can cope with
+   the extra code size.
+
 config REGULATOR_ACT8846
bool "Enable driver for ACT8846 regulator"
depends on DM_REGULATOR && PMIC_ACT8846
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 0d18c2b..1590d85 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -5,11 +5,11 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-$(CONFIG_DM_REGULATOR) += regulator-uclass.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
 obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
 obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
 obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o
-obj-$(CONFIG_DM_REGULATOR_FIXED) += fixed.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
 obj-$(CONFIG_REGULATOR_RK808) += rk808.o
 obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
 obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 08/49] rockchip: Avoid using MMC code when not booting from MMC

2016-01-21 Thread Simon Glass
This saves some code space in SPL which is useful on jerry.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 arch/arm/mach-rockchip/rk3288-board-spl.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c 
b/arch/arm/mach-rockchip/rk3288-board-spl.c
index 8199cad..b2c5729 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -113,6 +113,7 @@ static void configure_l2ctlr(void)
 
 static int configure_emmc(struct udevice *pinctrl)
 {
+#ifdef CONFIG_SPL_MMC_SUPPORT
struct gpio_desc desc;
int ret;
 
@@ -142,6 +143,7 @@ static int configure_emmc(struct udevice *pinctrl)
debug("gpio value ret=%d\n", ret);
return ret;
}
+#endif
 
return 0;
 }
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 06/49] power: Add support for RK808 regulators

2016-01-21 Thread Simon Glass
Add regulator support for the RK808 PMIC. It integrated 4 BUCKs and 8 LDOs
all of which are supported by this driver.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/power/regulator/Kconfig  |   9 ++
 drivers/power/regulator/Makefile |   1 +
 drivers/power/regulator/rk808.c  | 301 +++
 3 files changed, 311 insertions(+)
 create mode 100644 drivers/power/regulator/rk808.c

diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index 434dd02..8f638a9 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -49,6 +49,15 @@ config DM_REGULATOR_FIXED
features for fixed value regulators. The driver implements get/set api
for enable and get only for voltage value.
 
+config REGULATOR_RK808
+   bool "Enable driver for RK808 regulators"
+   depends on DM_REGULATOR && PMIC_RK808
+   ---help---
+   Enable support for the regulator functions of the RK808 PMIC. The
+   driver implements get/set api for the various BUCKS and LDOs supported
+   by the PMIC device. This driver is controlled by a device tree node
+   which includes voltage limits.
+
 config REGULATOR_S5M8767
bool "Enable support for S5M8767 regulator"
depends on DM_REGULATOR && PMIC_S5M8767
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index c85978e..0d18c2b 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
 obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
 obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o
 obj-$(CONFIG_DM_REGULATOR_FIXED) += fixed.o
+obj-$(CONFIG_REGULATOR_RK808) += rk808.o
 obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
 obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o
 obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o
diff --git a/drivers/power/regulator/rk808.c b/drivers/power/regulator/rk808.c
new file mode 100644
index 000..adef8f5
--- /dev/null
+++ b/drivers/power/regulator/rk808.c
@@ -0,0 +1,301 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass 
+ *
+ * Based on Rockchip's drivers/power/pmic/pmic_rk808.c:
+ * Copyright (C) 2012 rockchips
+ * zyw 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifndef CONFIG_SPL_BUILD
+#define ENABLE_DRIVER
+#endif
+
+struct rk808_reg_info {
+   uint min_uv;
+   uint step_uv;
+   s8 vsel_reg;
+   u8 vsel_bits;
+};
+
+static const struct rk808_reg_info rk808_buck[] = {
+   { 712500, 12500, REG_BUCK1_ON_VSEL, 6, },
+   { 712500, 12500, REG_BUCK2_ON_VSEL, 6, },
+   { 712500, 12500, -1, 6, },
+   { 180, 10, REG_BUCK4_ON_VSEL, 4, },
+};
+
+static const struct rk808_reg_info rk808_ldo[] = {
+   { 180, 10, LDO1_ON_VSEL, 5, },
+   { 180, 10, LDO2_ON_VSEL, 5, },
+   { 80, 10, LDO3_ON_VSEL, 4, },
+   { 180, 10, LDO4_ON_VSEL, 5, },
+   { 180, 10, LDO5_ON_VSEL, 5, },
+   { 80, 10, LDO6_ON_VSEL, 5, },
+   { 80, 10, LDO7_ON_VSEL, 5, },
+   { 180, 10, LDO8_ON_VSEL, 5, },
+};
+
+
+static int _buck_set_value(struct udevice *pmic, int buck, int uvolt)
+{
+   const struct rk808_reg_info *info = _buck[buck - 1];
+   int mask = (1 << info->vsel_bits) - 1;
+   int val;
+
+   if (info->vsel_reg == -1)
+   return -ENOSYS;
+   val = (uvolt - info->min_uv) / info->step_uv;
+   debug("%s: reg=%x, mask=%x, val=%x\n", __func__, info->vsel_reg, mask,
+ val);
+
+   return pmic_clrsetbits(pmic, info->vsel_reg, mask, val);
+}
+
+static int _buck_set_enable(struct udevice *pmic, int buck, bool enable)
+{
+   uint mask;
+   int ret;
+
+   buck--;
+   mask = 1 << buck;
+   if (enable) {
+   ret = pmic_clrsetbits(pmic, DCDC_ILMAX, 0, 3 << (buck * 2));
+   if (ret)
+   return ret;
+   ret = pmic_clrsetbits(pmic, REG_DCDC_UV_ACT, 1 << buck, 0);
+   if (ret)
+   return ret;
+   }
+
+   return pmic_clrsetbits(pmic, REG_DCDC_EN, mask, enable ? mask : 0);
+}
+
+#ifdef ENABLE_DRIVER
+static int buck_get_value(struct udevice *dev)
+{
+   int buck = dev->driver_data - 1;
+   const struct rk808_reg_info *info = _buck[buck];
+   int mask = (1 << info->vsel_bits) - 1;
+   int ret, val;
+
+   if (info->vsel_reg == -1)
+   return -ENOSYS;
+   ret = pmic_reg_read(dev->parent, info->vsel_reg);
+   if (ret < 0)
+   return ret;
+   val = ret & mask;
+
+   return info->min_uv + val * info->step_uv;
+}
+
+static int buck_set_value(struct udevice *dev, int uvolt)
+{
+   int buck = dev->driver_data;
+
+   return 

[U-Boot] [PATCH v9 48/49] rockchip: spi: Remove the explicit pinctrl setting

2016-01-21 Thread Simon Glass
The correct pinctrl is handled automatically so we don't need to do it in
the driver. The exception is when we want to use a different chip select
(other than 0). But this isn't used at present.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/spi/rk_spi.c | 28 ++--
 1 file changed, 2 insertions(+), 26 deletions(-)

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 412fa8b..9eff423 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -27,8 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DEBUG_RK_SPI   0
 
 struct rockchip_spi_platdata {
-   int periph_id;
-   struct udevice *pinctrl;
s32 frequency;  /* Default clock frequency, -1 for none */
fdt_addr_t base;
uint deactivate_delay_us;   /* Delay to wait after deactivate */
@@ -139,17 +137,7 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice 
*bus)
int ret;
 
plat->base = dev_get_addr(bus);
-   ret = uclass_get_device(UCLASS_PINCTRL, 0, >pinctrl);
-   if (ret)
-   return ret;
-   ret = pinctrl_get_periph_id(plat->pinctrl, bus);
 
-   if (ret < 0) {
-   debug("%s: Could not get peripheral ID for %s: %d\n", __func__,
- bus->name, ret);
-   return ret;
-   }
-   plat->periph_id = ret;
ret = clk_get_by_index(bus, 0, >clk);
if (ret < 0) {
debug("%s: Could not get clock for %s: %d\n", __func__,
@@ -164,8 +152,8 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice 
*bus)
"spi-deactivate-delay", 0);
plat->activate_delay_us = fdtdec_get_int(blob, node,
 "spi-activate-delay", 0);
-   debug("%s: base=%x, periph_id=%d, max-frequency=%d, 
deactivate_delay=%d\n",
- __func__, (uint)plat->base, plat->periph_id, plat->frequency,
+   debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
+ __func__, (uint)plat->base, plat->frequency,
  plat->deactivate_delay_us);
 
return 0;
@@ -207,11 +195,6 @@ static int rockchip_spi_claim_bus(struct udevice *dev)
struct rockchip_spi *regs = priv->regs;
u8 spi_dfs, spi_tf;
uint ctrlr0;
-#if !CONFIG_IS_ENABLED(PINCTRL_FULL)
-   struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
-   struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
-   int ret;
-#endif
 
/* Disable the SPI hardware */
rkspi_enable_chip(regs, 0);
@@ -273,13 +256,6 @@ static int rockchip_spi_claim_bus(struct udevice *dev)
ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
 
writel(ctrlr0, >ctrlr0);
-#if !CONFIG_IS_ENABLED(PINCTRL_FULL)
-   ret = pinctrl_request(plat->pinctrl, plat->periph_id, slave_plat->cs);
-   if (ret) {
-   debug("%s: Cannot request pinctrl: %d\n", __func__, ret);
-   return ret;
-   }
-#endif
 
return 0;
 }
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v2 15/37] rockchip: video: Add a display driver for rockchip HDMI

2016-01-21 Thread Simon Glass
Some Rockchip SoCs support HDMI output. Add a display driver for this so
that these displays can be used on supported boards.

Unfortunately this driver is not fully functional. It cannot reliably read
EDID information over HDMI. This seems to be due to the clocks being
incorrect - the I2C bus speed appears to be up to 100x slower than the
clock settings indicate. The root cause may be in the clock logic.

Signed-off-by: Simon Glass 
---

Changes in v2:
- Update for new clk_get_by_index() API

 arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h | 456 +++
 drivers/video/Kconfig|  10 +
 drivers/video/Makefile   |   1 +
 drivers/video/rockchip/Makefile  |   8 +
 drivers/video/rockchip/rk_hdmi.c | 933 +++
 5 files changed, 1408 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
 create mode 100644 drivers/video/rockchip/Makefile
 create mode 100644 drivers/video/rockchip/rk_hdmi.c

diff --git a/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h 
b/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
new file mode 100644
index 000..0b51d40
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
@@ -0,0 +1,456 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_HDMI_H
+#define _ASM_ARCH_HDMI_H
+
+
+#define HDMI_EDID_BLOCK_SIZE128
+
+struct rk3288_hdmi {
+   u32 reserved0[0x100];
+   u32 ih_fc_stat0;
+   u32 ih_fc_stat1;
+   u32 ih_fc_stat2;
+   u32 ih_as_stat0;
+   u32 ih_phy_stat0;
+   u32 ih_i2cm_stat0;
+   u32 ih_cec_stat0;
+   u32 ih_vp_stat0;
+   u32 ih_i2cmphy_stat0;
+   u32 ih_ahbdmaaud_stat0;
+   u32 reserved1[0x17f-0x109];
+   u32 ih_mute_fc_stat0;
+   u32 ih_mute_fc_stat1;
+   u32 ih_mute_fc_stat2;
+   u32 ih_mute_as_stat0;
+   u32 ih_mute_phy_stat0;
+   u32 ih_mute_i2cm_stat0;
+   u32 ih_mute_cec_stat0;
+   u32 ih_mute_vp_stat0;
+   u32 ih_mute_i2cmphy_stat0;
+   u32 ih_mute_ahbdmaaud_stat0;
+   u32 reserved2[0x1fe - 0x189];
+   u32 ih_mute;
+   u32 tx_invid0;
+   u32 tx_instuffing;
+   u32 tx_gydata0;
+   u32 tx_gydata1;
+   u32 tx_rcrdata0;
+   u32 tx_rcrdata1;
+   u32 tx_bcbdata0;
+   u32 tx_bcbdata1;
+   u32 reserved3[0x7ff-0x207];
+   u32 vp_status;
+   u32 vp_pr_cd;
+   u32 vp_stuff;
+   u32 vp_remap;
+   u32 vp_conf;
+   u32 vp_stat;
+   u32 vp_int;
+   u32 vp_mask;
+   u32 vp_pol;
+   u32 reserved4[0xfff-0x808];
+   u32 fc_invidconf;
+   u32 fc_inhactv0;
+   u32 fc_inhactv1;
+   u32 fc_inhblank0;
+   u32 fc_inhblank1;
+   u32 fc_invactv0;
+   u32 fc_invactv1;
+   u32 fc_invblank;
+   u32 fc_hsyncindelay0;
+   u32 fc_hsyncindelay1;
+   u32 fc_hsyncinwidth0;
+   u32 fc_hsyncinwidth1;
+   u32 fc_vsyncindelay;
+   u32 fc_vsyncinwidth;
+   u32 fc_infreq0;
+   u32 fc_infreq1;
+   u32 fc_infreq2;
+   u32 fc_ctrldur;
+   u32 fc_exctrldur;
+   u32 fc_exctrlspac;
+   u32 fc_ch0pream;
+   u32 fc_ch1pream;
+   u32 fc_ch2pream;
+   u32 fc_aviconf3;
+   u32 fc_gcp;
+   u32 fc_aviconf0;
+   u32 fc_aviconf1;
+   u32 fc_aviconf2;
+   u32 fc_avivid;
+   u32 fc_avietb0;
+   u32 fc_avietb1;
+   u32 fc_avisbb0;
+   u32 fc_avisbb1;
+   u32 fc_avielb0;
+   u32 fc_avielb1;
+   u32 fc_avisrb0;
+   u32 fc_avisrb1;
+   u32 fc_audiconf0;
+   u32 fc_audiconf1;
+   u32 fc_audiconf2;
+   u32 fc_audiconf3;
+   u32 fc_vsdieeeid0;
+   u32 fc_vsdsize;
+   u32 reserved7[0x2fff-0x102a];
+   u32 phy_conf0;
+   u32 phy_tst0;
+   u32 phy_tst1;
+   u32 phy_tst2;
+   u32 phy_stat0;
+   u32 phy_int0;
+   u32 phy_mask0;
+   u32 phy_pol0;
+   u32 reserved8[0x301f-0x3007];
+   u32 phy_i2cm_slave_addr;
+   u32 phy_i2cm_address_addr;
+   u32 phy_i2cm_datao_1_addr;
+   u32 phy_i2cm_datao_0_addr;
+   u32 phy_i2cm_datai_1_addr;
+   u32 phy_i2cm_datai_0_addr;
+   u32 phy_i2cm_operation_addr;
+   u32 phy_i2cm_int_addr;
+   u32 phy_i2cm_ctlint_addr;
+   u32 phy_i2cm_div_addr;
+   u32 phy_i2cm_softrstz_addr;
+   u32 phy_i2cm_ss_scl_hcnt_1_addr;
+   u32 phy_i2cm_ss_scl_hcnt_0_addr;
+   u32 phy_i2cm_ss_scl_lcnt_1_addr;
+   u32 phy_i2cm_ss_scl_lcnt_0_addr;
+   u32 phy_i2cm_fs_scl_hcnt_1_addr;
+   u32 phy_i2cm_fs_scl_hcnt_0_addr;
+   u32 phy_i2cm_fs_scl_lcnt_1_addr;
+   u32 phy_i2cm_fs_scl_lcnt_0_addr;
+   u32 reserved9[0x30ff-0x3032];
+   u32 aud_conf0;
+   u32 aud_conf1;
+   u32 aud_int;
+   u32 aud_conf2;
+   u32 aud_int1;
+   u32 

[U-Boot] [PATCH v9 35/49] dm: power: Allow regulators to not implement all operations

2016-01-21 Thread Simon Glass
Some regulators will not implement any operations (e.g. fixed regulators).
This is not an error, so allow the autoset process to continue when one
of these regulators is found.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/power/regulator/regulator-uclass.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/power/regulator/regulator-uclass.c 
b/drivers/power/regulator/regulator-uclass.c
index fec2886..9fe07f2 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -334,6 +334,8 @@ int regulators_enable_boot_on(bool verbose)
}
if (verbose)
regulator_show(dev, ret);
+   if (ret == -ENOSYS)
+   ret = 0;
}
 
return ret;
-- 
2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH v9 44/49] rockchip: gpio: Read the GPIO value correctly

2016-01-21 Thread Simon Glass
This function should return 0 or 1, not a mask. Fix it.

Signed-off-by: Simon Glass 
---

Changes in v9: None
Changes in v2: None

 drivers/gpio/rk_gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index fbdf9f3..a22e219 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -53,7 +53,7 @@ static int rockchip_gpio_get_value(struct udevice *dev, 
unsigned offset)
struct rockchip_gpio_priv *priv = dev_get_priv(dev);
struct rockchip_gpio_regs *regs = priv->regs;
 
-   return readl(>ext_port) & OFFSET_TO_BIT(offset);
+   return readl(>ext_port) & OFFSET_TO_BIT(offset) ? 1 : 0;
 }
 
 static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
-- 
2.7.0.rc3.207.g0ac5344

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