and the software seems
to be too much. You should try post-mortem debugging with core dumps
instead.
regards,
matthias
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* Matthias Welwarsky
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(), but this is only
allocating sized 2^n blocks of memory. So dma_alloc_coherent() allocates
the next bigger 2^n block and then free's the excess pages one by one.
That isn't really helping with keeping the memory pool in shape.
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* Matthias Welwarsky
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if everyone is disciplined enough, my inbox
will fill with mails I already received from the list.
regards,
matthias
ps.
If you intend to reply to this email, please make sure that it goes to
the list and not to my address. I like my inbox nice and tidy.
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Anthony P. Lannutti wrote:
So, I have:
RegisterValue
--- -
RSZ_CNT.HRSZ (hrsz) 256
RSZ_CNT.VRSZ (vrsz) 256
That should be:
RSZ_CNT.HRSZ = 256-1
RSZ_CNT.VRSZ = 256-1
I think you need to subtract 1 from the computed resize factors.
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* Matthias
of bytes I
intend to write out?
Yes. The page size doesn't have an influence on this anyway. It's an MMU
thing, not a cache thing.
Thanks.
Regards,
Andy
- Original Message
From: Matthias Welwarsky [EMAIL PROTECTED]
To: Andy Ngo [EMAIL PROTECTED]
Cc: davinci-linux-open-source
Andy,
opening /dev/mem O_RDWR|O_SYNC should be enough to map the region
uncached and with the write buffer disabled. In that case, every read
and write into the memory mapped region directly translates into a CPU
access to the respective physical address. No need to call msync before
or after.
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;
return 0;
}
have a look at the function uncached_access in the same file. You'll
see that it returns 1 for O_SYNC, so it should work as is suggested.
regards,
matthias
Matthias Welwarsky wrote:
Andy Ngo wrote:
Thanks, but how do I set the range uncacheable? I don't see such an
option
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