Hi,
I need to hook up a DVB (8 bit) tuner to the EMIF. Current thinking
is to write a module to trigger DMA transfer using a GPIO interrupt on
the 'Packet Ready' output of the tuner. Anyone have anything they can
point me at that might be similar to save some time?
Also I fi
Hi, nicholas,
> I need to hook up a DVB (8 bit) tuner to the EMIF. Current thinking
> is to write a module to trigger DMA transfer using a GPIO interrupt on
> the 'Packet Ready' output of the tuner. Anyone have anything they can
> point me at that might be similar to s
s Fearnley
Sent: 24 June 2008 12:14
To: davinci-linux-open-source@linux.davincidsp.com
Subject: EMIF
Hi,
I need to hook up a DVB (8 bit) tuner to the EMIF. Current thinking
is to write a module to trigger DMA transfer using a GPIO interrupt on
the 'Packet Ready' output of the tuner.
scheme for attaching a DVB tuner directly (no
glue logic) to the CCD interface.
Howard
-Original Message-
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED]
] On Behalf Of Nicholas Fearnley
Sent: 24 June 2008 12:14
To: davinci-linux-open-source@linux.davincidsp.com
Subject: EMIF
Hi,
When interfacing FPGA to the DM6446 EVM EMIF do I need a bus switch on
CS3 for my device or is this handled already by the CPLD (Altera MaxII)?
Am I right in thinking simply accessing an address in the CS3 space
will automatically assert the CS3 signal?
I plan on only having 8 bits exposed
Title: Configuration of EMIF
Hello All,
I need an access to external hardware such as FPGA over EMIF.
Has anybody an idea how and where should be EMIF configured?
Thanks
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hello everyone
in dm6446 we want to expand the seven uart devices by the emif
bus.but i can not find the emif bus driver in the Linux,if i want to write/read
data to the uart which expanded by the emif bus how can do it? now i have no
idea.who can give me a guideline
uot;unable to handle kernel paging request at
virtual address 0100".
Do you have any hint about accessing emif? I suspect this is not the
way I should use emif...
Thanks.
This message was sent using IMP, the Int
Hi,
I try to access EMIF interface from Linux. I know about Section
3.6.6.4 of TMS320DM6446 Datasheet: I clear ATAEN: PINMUX0 &= ~ (1 <<
17);
This doesnt' help.
For a test case I would like to access kernel image at flash from
Linux, as I can access from u-boot:
DaVinci EVM
Title: Configuration of EMIF
Johannes,
I presume the EMIF you are
referring to is the Asynchronous EMIF of the DM6446. Please refer to document
number SPRUE20.pdf (I believe Rev A is the latest, dated June 2006) found at http://focus.ti.com/lit/ug/sprue20a/sprue20a.pdf
Title: Configuration of EMIF
Hi,
We are doing the exact same thing and this
was a fun “detour” for several hours
Basically, we modified the VPFE driver to
allow an IOCTL to access our FPGA.
Look in the include/asm/arch folder –
you will find IO.h (remember this comes from the
the usual way to expand uart is using 16c550 compatible chipsets connected
on the bus.
the davinci driver for internal uart can manage also external chipsets.
I don't know doing that with emif i/f.
2010/4/24 liuyue18301
>
>hello everyone
>in dm6446 we want to ex
Il 24/04/10 04.10, liuyue18301 ha scritto:
>
>hello everyone
>in dm6446 we want to expand the seven uart devices by the emif
> bus.but i can not find the emif bus driver in the Linux,if i want to
> write/read data to the uart which expanded by the emif bus how
tavio Campana
> Il 24/04/10 04.10, liuyue18301 ha scritto:
> >
> >hello everyone
> >in dm6446 we want to expand the seven uart devices by the emif
> bus.but i can not find the emif bus driver in the Linux,if i want to
> write/read data to the uart which exp
Hi everyone!
I'm currently working on the DM355 EVM and analyzing the ASYNC EMIF-Bus.
I don't understand where at the boot up process the AEMIF control
registers are finally set? Especially the registers A1CR and A2CR for
timing stuff. I know that they are responsible for NAND an
Title: Using both ATA and EMIF
Hello All,
It is possible to use both ATA and EMIF at the same time?
Has anybody implemented this issue?
Thanks
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http
Hello Johannes,
EMIFA and ATA are multiplexed modules. You cannot access both
simultaneously. This is clearly documented in the EMIFA and ATA/CF pin
terminal function tables. Please refer to Section 3.6.6.4 of
TMS320DM6446 Datasheet.
Regards,
Satheesh S
**
hi,everyone
I have tried to use both ata and emif, they can be used at the same time.I try
to send some control commands via EMIF, while copy some data to ATA hard disk.
you can just to use they as follows:
1)change PINMUX0 to enable ATA after kernel boot time
2)when you want to use emif bus to
Karlheinz Woschee schrieb:
Hi everyone!
I'm currently working on the DM355 EVM and analyzing the ASYNC EMIF-Bus.
I don't understand where at the boot up process the AEMIF control
registers are finally set? Especially the registers A1CR and A2CR for
timing stuff. I know that they are respo
Johannes Schell wrote:
Hello All,
It is possible to use both ATA and EMIF at the same time?
IIUC, they are pin-multiplexed on the DVEVM, so cannot be used together.
Kevin
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Davinci-linux-open-source
-
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On Behalf Of
chendh
Sent: Wednesday, November 15, 2006 3:32 AM
To: davinci-linux-open-source@linux.davincidsp.com
Subject: Using both ATA and EMIF
hi,everyone
I have tried to use both ata and emif, they can be used at the same time.I
try to send
Hi
Found a few minor issues when stressing the ATA + EMIF together
So here is what I did to work around the problems
1. Using the hdparm utility (hdparm -d 0 -r 0 -p 0 /dev/had) --> to put
the hdd into a non-dma, slow mode
2. use this sequence shown below to swap between
hi,all
I have tried to use lock_kernel and unlock_kernel rather than spinlocks.
Unfortunately, when copy some data to hard disk while changing PINMUX0 to enabe
EMIF, this will cause write error. Both in DMA and PIO mode will fail. The
error information is as follows:
hdb: status timeout
: chendh [mailto:[EMAIL PROTECTED]
Sent: Friday, November 17, 2006 4:01 AM
To: Steve Spano
Cc: [EMAIL PROTECTED]; davinci-linux-open-source@linux.davincidsp.com
Subject: Re: Using both ATA and EMIF
hi,all
I have tried to use lock_kernel and unlock_kernel rather than spinlocks.
Unfortunately
we must to use the DMA mode, how to do it?
thanks.
chendh
- Original Message -
From: Steve Spano
To: 'chendh'
Cc: [EMAIL PROTECTED] ; davinci-linux-open-source@linux.davincidsp.com
Sent: Friday, November 17, 2006 5:43 PM
Subject: RE: Using both ATA and EMIF
S
Hmmm
I think you would have to have some kind of small logic device outside of
the davinci, like a CPLD.
You could use the CPLD to generate a DMA-BUSY flag when DMA transfers were
in process. You would have to check this flag to see if you could access the
EMIF only when a DMA transfer is
hello Guys:
this is second time to turn to help on the same problem.
i want to know is there EMIF driver in the linux? and if i want to
send/recv data to the uarts which are expanded by FPGA ,how can i do it? which
driver should i create or modify EMIF driver or UART driver?i want to
Whenever we enables ATA interface, /EM_WE, /EM_OE
signal does not assert correctly.
Anybody know how to solve this problem?
Junho
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http://linux.davinc
Hi
I have tried according to CODE REFERENCE, the result is as follows:
The test case is:
0)power on board
1)start one process to copy large datas to hard disk
2)start another process to change PINMUX0 to enable EMIF, and then return to ATA
3)do 2) about 40 times
4)test over, power down.
a)in PIO
2010/4/25 liuyue18301 :
>
> hello Guys:
> this is second time to turn to help on the same problem.
> i want to know is there EMIF driver in the linux? and if i want to
There is no EMIF driver.
> send/recv data to the uarts which are expanded by FPGA ,how can i do it?
Th
On Mon, Apr 26, 2010 at 5:05 AM, Steve Chen wrote:
> 2010/4/25 liuyue18301 :
>>
>> hello Guys:
>> this is second time to turn to help on the same problem.
>> i want to know is there EMIF driver in the linux? and if i want to
>
> There is no EMIF driver.
Hi Steve,
On Mon, Apr 26, 2010 at 15:35:37, Steve Chen wrote:
> 2010/4/25 liuyue18301 :
> >
> > hello Guys:
> > this is second time to turn to help on the same problem.
> > i want to know is there EMIF driver in the linux? and if i want to
>
> There i
On Mon, Apr 26, 2010 at 5:19 AM, Nori, Sekhar wrote:
> Hi Steve,
>
> On Mon, Apr 26, 2010 at 15:35:37, Steve Chen wrote:
>> 2010/4/25 liuyue18301 :
>> >
>> > hello Guys:
>> > this is second time to turn to help on the same problem.
>> >
I would recommend that you look at the 8250 driver and modify it
(duplicate) to change the memory addresses that it uses. The memory
addresses should be changed to correspond to your EMIF. If your EMIF,
which maps to an FPGA, has the standard UART register set, then it may
be a matter of simply
Would someone please clear up the following for me?
The documentation for the the EMIF (srue20b) and the source code for
DVFlasher both say :
To talk to NAND-Flashes:
Tie A[2] to CLE and A[1] to ALE. Apparently A[0] and BA[1:0] are not
connected.
to set CLE low and ALE low
Hi All,
I am new to the DM355 & Davinci-linux development.
We have a custom DM355 based board which is similar to DM355EVM board.
The board have DM9000 ethernet chip on EMIF .
I want to implment DMA for DM9000's transmit/receive oparation,
DM355 has EDMA provisions fo
Junho,
EMIFA and ATA are multiplexed modules. You cannot access both
simultaneously. This is clearly documented in the EMIFA and ATA/CF pin
terminal function tables. Please refer to Section 3.6.6.4 of
TMS320DM6446 Datasheet.
Regards,
Satheesh S
**
James T Long wrote:
> Would someone please clear up the following for me?
>
> The documentation for the the EMIF (srue20b) and the source code for
> DVFlasher both say :
>
> To talk to NAND-Flashes:
>
> Tie A[2] to CLE and A[1] to ALE. Apparently
There are two pieces to this issue:
1) The transfer between memory and the DM9000. This should be no problem
as the DM9000 will show up in the EMIF address space.
2) The initiation of the transfer. You either need to manually invoke
the transfer (through the ESR) or an event can
Hi,
You do not have a dedicated EDMA channel for DM9000-EMIF. But you can always
use an unallocated DMA channel for Transmit and Receive.
EDMA will be used to transfer the data to/from DDR from/to DM9000 FIFO.
We had tried to change the current DM9000 driver to use EDMA on the transmit
path
&tcc, EVENTQ_0);
where
#define DAVINCI_DMA_CHANNEL_ANY -1 ---> edma.h
Best Regards!!
U.C. Lee
On Thu, Dec 11, 2008 at 6:46 AM, Narnakaje, Snehaprabha <[EMAIL PROTECTED]
> wrote:
> Hi,
>
>
>
> You do not have a dedicated EDMA channel fo
Hi
Well, what I found is this
You can access the ATA and EMIF by switching the PINMIX0 register.
I do this within a new IOCTL in the VPFE driver that I added to access my
FPGA which lets me configure a progressive scan imager.
Normally, the IDE starts in a DMA based mode.
I had to do the
Steve,
Here are a few thoughts (as I don't have your hardware I won't ever be able to
try it out):
1) To access ATA and EMIF at the same time you need drivers that "sync" with
each other. IN THEORY it is possible to run with DMA IF and ONLY IF while
that DMA is occuring th
Title: Samsung Enterprise Portal mySingle
Question about Nor Flash Memory Size based on EMIF
Hi all.
I am using DM6446 DVEVM,
I have a question about the NOR flash memory size of DVEVM and the source
code of uboot and git kernel tree.
In Uboot Code,
AM29LV256 NOR Flash Memory is
Hi All,
I am new to the DM355 & Davinci-linux development.
We have a custom DM355 based board which is similar to DM355EVM board.
The board have DM9000 ethernet chip on EMIF .
I want to implment DMA for DM9000's transmit/receive oparation,
DM355 has EDMA provisions fo
(3):
arm:davinci: prepare to move aemif driver to drivers/mfd
arm:davinci: Move emif driver to drivers/mfd from mach-davinci folder
arm:davinci: move NAND and NOR devices as aemif MFD slaves
arch/arm/Kconfig |1 +
arch/arm/mach-davinci/Makefile
(3):
arm:davinci: prepare to move aemif driver to drivers/mfd
arm:davinci: move emif driver to drivers/mfd from mach-davinci folder
arm:davinci: move NAND and NOR devices as aemif MFD slaves
arch/arm/Kconfig |1 +
arch/arm/mach-davinci/Makefile
The da850_emif25_pins pinmux array is not used. Remove it.
Signed-off-by: Michael Williamson
---
arch/arm/mach-davinci/da850.c | 16
arch/arm/mach-davinci/include/mach/da8xx.h |1 -
2 files changed, 0 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach
From: Felipe Balbi <[EMAIL PROTECTED]>
Later patch will come to use it in davinci_nand.c and get
rid of a define there. In DM355, the base is different, so
better to apply this patch before adding support for DM355
nand chip.
Signed-off-by: Felipe Balbi <[EMAIL PROTECTED]>
---
arch/arm/mach-davi
> http://davinci-linux-open-source.1494791.n2.nabble.com/PATCH-arm-davinci-configure-davinci-aemif-chipselects-through-OF-tt7059739.html#none
>
> Manjunathappa, Prakash (3):
> arm:davinci: prepare to move aemif driver to drivers/mfd
> arm:davinci: move emif driver to drivers/mfd fro
Hi Prakash,
On Tue, Feb 21, 2012 at 11:54:56, Manjunathappa, Prakash wrote:
> Hi,
>
> I do not see any comments on this series. Can it be applied?
I have not yet gotten to reviewing the davinci parts of this series.
I have a backlog and am clearing it oldest first. Hope to get to this
by this we
Move emif handling code from platform folder to multi functional
devices frame work. emif MFD driver adds "davinci_nand" and
"physmap-flash" as slave devices.
Signed-off-by: Manjunathappa, Prakash
---
Since v4:
Fix updating NAND/NOR platfrom data.
Since v3:
No change. Resen
The da850_emif25_pins pinmux array is not used. Remove it.
Signed-off-by: Michael Williamson
---
arch/arm/mach-davinci/da850.c | 16
arch/arm/mach-davinci/include/mach/da8xx.h |1 -
2 files changed, 0 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach
From: Felipe Balbi <[EMAIL PROTECTED]>
Later patch will come to use it in davinci_nand.c and get
rid of a define there. In DM355, the base is different, so
better to apply this patch before adding support for DM355
nand chip.
Signed-off-by: Felipe Balbi <[EMAIL PROTECTED]>
---
arch/arm/mach-davi
From: Felipe Balbi
Later patch will come to use it in davinci_nand.c and get
rid of a define there. In DM355, the base is different, so
better to apply this patch before adding support for DM355
nand chip.
Signed-off-by: Felipe Balbi
---
arch/arm/mach-davinci/board-dm644x-evm.c | 19
Hi Prakash,
On Thu, Feb 23, 2012 at 07:28:23PM +0530, Manjunathappa, Prakash wrote:
> +static int __init davinci_aemif_probe(struct platform_device *pdev)
> +{
> + struct davinci_aemif_devices *davinci_aemif_devices =
> + pdev->dev.platform_data;
> + struct platform_device *dev
Hi Samuel,
On Mon, Feb 27, 2012 at 19:56:38, Samuel Ortiz wrote:
[snip]
> So it seems you're passing a platform devices array through your mfd aemif
> platform data pointer. And from what I can see, it's mostly a 1 entry array
> (for the NAND case) or a 2 entries array (for the NAND and NOR case).
Hi Samuel,
On Tue, Feb 28, 2012 at 11:14:39, Manjunathappa, Prakash wrote:
> Hi Samuel,
>
> On Mon, Feb 27, 2012 at 19:56:38, Samuel Ortiz wrote:
> [snip]
> > So it seems you're passing a platform devices array through your mfd aemif
> > platform data pointer. And from what I can see, it's mostly
Hi Prakash,
On Tue, Feb 28, 2012 at 05:44:39AM +, Manjunathappa, Prakash wrote:
> Hi Samuel,
>
> On Mon, Feb 27, 2012 at 19:56:38, Samuel Ortiz wrote:
> [snip]
> > So it seems you're passing a platform devices array through your mfd aemif
> > platform data pointer. And from what I can see, it
Hi Samuel,
May be I did not do a good job giving complete information on this earlier.
So I have replied on top of my mail with below information (seems you missed it)
More information on AEMIF:
DaVinci AEMIF is an async memory interface, driver for which was implemented
in arch/arm/mach-davinci/
Hi Prakash,
On Tue, Mar 06, 2012 at 01:12:25PM +, Manjunathappa, Prakash wrote:
> Hi Samuel,
>
> May be I did not do a good job giving complete information on this earlier.
> So I have replied on top of my mail with below information (seems you missed
> it)
>
I did get it, sorry for not bei
rt of the quote:
>
> "...code a driver that scans the connected memories in order to register
> its child devices for each of the subsystems."
>
emif is not discoverable interface, does not support scanning for connected
devices.
Could you please let me kno
On Monday 08 December 2008, Felipe Balbi wrote:
> From: Felipe Balbi <[EMAIL PROTECTED]>
>
> Later patch will come to use it in davinci_nand.c and get
> rid of a define there. In DM355, the base is different, so
> better to apply this patch before adding support for DM355
> nand chip.
>
> Signed-
On Tue, Dec 09, 2008 at 01:23:23PM -0800, David Brownell wrote:
> Looks plausible and safe ... though I'd be tempted to
> combine this with the part of the NAND driver patch
> which uses this, and removes the FIXME comment.
>
> That would make your patch #2 much less busy, and
> make it more appar
008 22:03:32 +0200
Subject: [PATCH 01/14] arch: davinci: pass emif control base via resource
Later patch will come to use it in davinci_nand.c and get
rid of a define there. In DM355, the base is different, so
better to apply this patch before adding support for DM355
nand chip.
Signed-off-by:
Much better ... but I hope someone will clean
up the duplicate #defines below, at some point.
Maybe just make them DM6466_ASYNC_EMIF_* symbols
or whatever, which live in a common header
The different ARM-equipped flavors of DaVinci
chips aren't in full agreement about these
addresses. And they ne
, Prakash (3):
arm:davinci: prepare to move aemif driver to drivers/mfd
arm:davinci: move emif driver to mfd framework
arm:davinci: move NAND and NOR devices as emif MFD slaves
arch/arm/Kconfig |1 +
arch/arm/mach-davinci/Makefile |2
devices = davinci_aemif_devices->devices;
+ cells = davinci_emifs;
+
+ /* DaVinci NAND device client */
+ for (i = 0; i < davinci_aemif_devices->num_devices; i++) {
+ if (!strcmp(devices[i].name,
+ cells[DAVINCI_NAND_DEVICE_C
NAND and NOR device are made as aemif device slaves, hence all DaVinci
board NAND/NOR device registration is achieved via emif MFD driver.
Signed-off-by: Manjunathappa, Prakash
---
Since v4:
No change.
Since v3:
Changed NAND device id to 1 for board-mityomapl138.
Since v2:
Make changes for all
ct mfd_cell *cells;
+ int i, ret;
+
+ devices = davinci_aemif_devices->devices;
+ cells = davinci_emifs;
+
+ /* DaVinci NAND device client */
+ for (i = 0; i < davinci_aemif_devices->num_devices; i++) {
+ if (!strcmp(devices[i].name,
+
Move aemif kernel module from arch/arm/mach-davinci/ to multi functional
devices frame work. "davinci_aemif" MFD driver adds "davinci_nand" and
"physmap-flash" slave devices.
Signed-off-by: Manjunathappa, Prakash
---
Since v2:
Modified emif MFD driver to load
Move aemif kernel module from arch/arm/mach-davinci/ to multi functional
devices frame work. "davinci_aemif" MFD driver adds "davinci_nand" and
"physmap-flash" slave devices.
Signed-off-by: Manjunathappa, Prakash
---
Since v3:
No change. Resending as 3/3 in patch ch
;
> Signed-off-by: Manjunathappa, Prakash
> ---
> Since v3:
> No change. Resending as 3/3 in patch changed.
> Since v2:
> Modified emif MFD driver to load multiple instance of NAND/NOR devices.
> Since v1:
> Patch generated using -M option.
>
> arch/arm/Kconfig
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