https://bugs.freedesktop.org/show_bug.cgi?id=80531
Martin Peres changed:
What|Removed |Added
Resolution|--- |MOVED
Status|NEW
https://bugs.freedesktop.org/show_bug.cgi?id=75992
Martin Peres changed:
What|Removed |Added
Resolution|--- |MOVED
Status|NEW
https://bugs.freedesktop.org/show_bug.cgi?id=107296
Martin Peres changed:
What|Removed |Added
Status|REOPENED|RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=108521
Martin Peres changed:
What|Removed |Added
Resolution|--- |MOVED
Status|REOPENED
https://bugs.freedesktop.org/show_bug.cgi?id=109955
Martin Peres changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=108934
Martin Peres changed:
What|Removed |Added
Resolution|--- |MOVED
Status|NEW
On Tue, 19 Nov 2019, Fabio Estevam wrote:
Hi Adrian,
Hi Fabio,
On Mon, Nov 18, 2019 at 12:25 PM Adrian Ratiu
wrote:
Some nitpicks:
+ +config DRM_IMX_MIPI_DSI + tristate "Freescale i.MX DRM
MIPI DSI"
This text seems too generic as there are i.MX SoCs that use
different MIPI
https://bugs.freedesktop.org/show_bug.cgi?id=107465
Martin Peres changed:
What|Removed |Added
Resolution|--- |MOVED
Status|NEW
https://bugs.freedesktop.org/show_bug.cgi?id=107456
Martin Peres changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=107376
Martin Peres changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=107278
Bug 107278 depends on bug 107376, which changed state.
Bug 107376 Summary: Raven: `flush_delayed_work()` takes 500 ms
https://bugs.freedesktop.org/show_bug.cgi?id=107376
What|Removed |Added
https://bugs.freedesktop.org/show_bug.cgi?id=105433
Martin Peres changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
crtc_crc_poll() is defined as returning 'unsigned int' but the
.poll method is declared as returning '__poll_t', a bitwise type.
Fix this by using the proper return type and using the EPOLL
constants instead of the POLL ones, as required for __poll_t.
CC: Maarten Lankhorst
CC: Maxime Ripard
CC:
fb_deferred_io_work() can access the vmbus ringbuffer by calling
fbdefio->deferred_io() -> synthvid_deferred_io() -> synthvid_update().
Because the vmbus ringbuffer is inaccessible between hvfb_suspend()
and hvfb_resume(), we must cancel info->deferred_work before calling
vmbus_close() and then re
* Tomi Valkeinen [191119 15:56]:
> Afaik, Weston and X both handle page flips and/or dirtying the fb, so they
> should work. Are there applications that do not work, and cannot be made to
> work, except the few SGX test apps?
I'm not sure sure yet what all it affects, I'll do some more tests on i
On 11/19/19 3:37 AM, Jan Kara wrote:
> On Tue 19-11-19 00:16:36, John Hubbard wrote:
>> @@ -2025,6 +2149,20 @@ static int __record_subpages(struct page *page,
>> unsigned long addr,
>> return nr;
>> }
>>
>> +static bool __pin_compound_head(struct page *head, int refs, unsigned int
>> flag
On 11/19/19 8:10 AM, Jens Axboe wrote:
> On 11/19/19 1:16 AM, John Hubbard wrote:
>> Convert fs/io_uring to use the new pin_user_pages() call, which sets
>> FOLL_PIN. Setting FOLL_PIN is now required for code that requires
>> tracking of pinned pages, and therefore for any code that calls
>> put_us
On Mon, Nov 18, 2019 at 11:45 PM Thierry Reding
wrote:
>
> On Sat, Nov 02, 2019 at 06:56:28PM +0100, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > Hi Ben,
> >
> > here's a revised subset of the patches I had sent out a couple of weeks
> > ago. I've reworked the BAR2 accesses in the way t
On 2019/11/19 下午10:14, Jason Gunthorpe wrote:
On Tue, Nov 19, 2019 at 10:02:08PM +0800, Jason Wang wrote:
On 2019/11/19 下午8:38, Jason Gunthorpe wrote:
On Tue, Nov 19, 2019 at 10:41:31AM +0800, Jason Wang wrote:
On 2019/11/19 上午4:28, Jason Gunthorpe wrote:
On Mon, Nov 18, 2019 at 03:27:13PM -
On Tue, Nov 19, 2019 at 1:08 PM Daniel Vetter wrote:
>
> For locking semantics it really doesn't matter when we grab the
> ticket. But for lockdep validation it does: the acquire ctx is a fake
> lockdep. Since other drivers might want to do a full multi-lock dance
> in their fault-handler, not jus
On Wed, 20 Nov 2019 at 01:02, Rob Herring wrote:
>
> On Tue, Nov 19, 2019 at 8:43 AM Krzysztof Kozlowski wrote:
> >
> > With split of power domain controller bindings to power-domain.yaml, the
> > consumer part was renamed to power-domain.txt. Update the references in
> > other bindings.
> >
> >
https://bugzilla.kernel.org/show_bug.cgi?id=205585
Bug ID: 205585
Summary: [Regression] [amdgpu] AMD Vega 64 GPU invalid access
and EEH under load
Product: Drivers
Version: 2.5
Kernel Version: 5.4-rc7
Hardware: PPC-64
Hi,
On Tue, Nov 19, 2019 at 07:46:28PM +0100, Andreas Kemnade wrote:
> On Tue, 19 Nov 2019 17:55:57 +0200
> Tomi Valkeinen wrote:
>
> > On 19/11/2019 17:06, Tony Lindgren wrote:
> >
> > >> The userspace apps need to do this. If they're using single-buffering,
> > >> then
> > >> using the dirty
Hi Sebastian,
> Am 18.11.2019 um 15:51 schrieb H. Nikolaus Schaller :
>
>> Ok, I tried not to break video mode support, but I do not have any
>> hardware. Make sure to set the MIPI_DSI_MODE_VIDEO flag in the panel
>> driver.
>
> Indeed, this may be missing (can't look into the code at the moment
These structures look like a bunch of data tables that aren't going to
change after boot. Let's move them to the const RO section of memory so
that they can't be modified at runtime on modern machines.
Signed-off-by: Stephen Boyd
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 30 +--
Hi Tony,
On Mon, Nov 18, 2019 at 02:52:09PM -0800, Tony Lindgren wrote:
> * Sebastian Reichel [191118 15:03]:
> > On Mon, Nov 18, 2019 at 03:37:12PM +0100, H. Nikolaus Schaller wrote:
> > > > Am 18.11.2019 um 15:33 schrieb Sebastian Reichel
> > > > :
> > > > On Mon, Nov 18, 2019 at 03:05:07PM +0
On 11/19/19 12:46 AM, Stephen Rothwell wrote:
> Hi all,
>
> Changes since 20191118:
on x86_64:
ERROR: "pm_suspend_target_state" [drivers/gpu/drm/i915/i915.ko] undefined!
# CONFIG_SUSPEND is not set
--
~Randy
Reported-by: Randy Dunlap
___
dri-devel
19.11.2019 09:21, Thierry Reding пишет:
> On Mon, Nov 18, 2019 at 11:02:20PM +0300, Dmitry Osipenko wrote:
>> External memory controller is interconnected with memory controller and
>> with external memory. Document new interconnect property which designates
>> external memory controller as interco
When compiling with W=1 few warnings about unused variables show up.
This patch removes all the involved variables.
Signed-off-by: Benjamin Gaignard
---
drivers/gpu/drm/drm_modes.c | 22 +++---
1 file changed, 3 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/drm_mod
Current code assumes that all the irqs registers offsets can be
accessed in all the hw revisions; this is not the case for some
targets that should not access some of the irq registers.
This change adds the support to selectively remove the irqs that
are not supported in some of the hw revisions.
Hi Laurent,
Thank you for your feedback!
> From: Laurent Pinchart
> Sent: 19 November 2019 00:08
> Subject: Re: [PATCH v4 08/13] dt-bindings: display: bridge: Repurpose
> lvds-encoder
>
> Hi Fabrizio,
>
> Thank you for the patch.
>
> On Wed, Nov 13, 2019 at 03:51:27PM +, Fabrizio Castro
Instead of obtaining the width/height of the framebuffer from the CRTC
state, obtain it from the current plane state.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm
19.11.2019 09:31, Thierry Reding пишет:
> On Mon, Nov 18, 2019 at 11:02:30PM +0300, Dmitry Osipenko wrote:
> [...]
>> diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h
>> index 1238e35653d1..593954324259 100644
>> --- a/include/soc/tegra/mc.h
>> +++ b/include/soc/tegra/mc.h
>> @@ -141,6
Add a compatible string for the LCD controller found in the JZ4770 SoC.
Signed-off-by: Paul Cercueil
---
Documentation/devicetree/bindings/display/ingenic,lcd.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/ingenic,lcd.txt
b/Documentation/device
On 11/19/19 7:53 PM, Souza, Jose wrote:
> On Tue, 2019-11-19 at 13:58 +0100, Benjamin Gaignard wrote:
>> Include drm_crtc_helper_internal.h to provide
>> drm_connector_get_single_encoder
>> prototype.
>>
>> Fixes: a92462d6bf493 ("drm/connector: Share with non-atomic drivers
>> the function to get
Clamping a value between INT_MIN and INT_MAX always return the value itself
and generate warnings when compiling with W=1.
Signed-off-by: Benjamin Gaignard
---
drivers/gpu/drm/drm_rect.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_rect.c b/driv
18.11.2019 23:02, Dmitry Osipenko пишет:
> EMC now provides MC with memory bandwidth using interconnect API.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/memory/tegra/tegra124-emc.c | 24
> 1 file changed, 24 insertions(+)
>
> diff --git a/drivers/memory/tegra/teg
While the LCD controller can effectively only support a maximum
resolution of 800x600, the framebuffer's height can be much higher,
since we can change the Y start offset.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Hi Laurent,
Thank you for your feedback!
> From: Laurent Pinchart
> Sent: 19 November 2019 00:16
> Subject: Re: [PATCH v4 12/13] [HACK] drm/bridge: lvds-codec: Enforce device
> specific compatible strings
>
> Hi Fabrizio,
>
> Thank you for the patch.
>
> On Wed, Nov 13, 2019 at 03:51:31PM +0
Check that the requested display size isn't above the limits supported
by the CRTC.
- JZ4750 and older support up to 800x600;
- JZ4755 supports up to 1024x576;
- JZ4760 and JZ4770 support up to 720p;
- JZ4780 supports up to 2k.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-dr
* Tomi Valkeinen [191119 05:42]:
> On 19/11/2019 01:05, Tony Lindgren wrote:
> > * Sebastian Reichel [191117 07:11]:
> > > We can simply use the atomic helper for
> > > handling the dirtyfb callback.
> > ...
> > > --- a/drivers/gpu/drm/omapdrm/omap_crtc.c
> > > +++ b/drivers/gpu/drm/omapdrm/omap_
It is possible that there is no drm_framebuffer associated with a given
plane state.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c
b/drivers/gpu/drm
The LCD controller in the JZ4770 supports up to 720p. While there has
been many new features added since the old JZ4740, which are not yet
handled here, this driver still works fine.
Signed-off-by: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm.c | 7 +++
1 file changed, 7 insertions(
On Tue, Nov 19, 2019 at 04:18:15PM +0100, Hans de Goede wrote:
> Hi All,
>
> This series needs to be merged through a single tree, to keep things
> bisectable. I have even considered just squashing all 3 patches into 1,
> but having separate commits seems better, but that does lead to an
> interme
* Tomi Valkeinen [191119 14:54]:
> On 19/11/2019 16:32, Tony Lindgren wrote:
>
> > > We haven't had omap_gem_op_finish() in the kernel for some years now...
> > >
> > > Shouldn't a normal page flip, or if doing single-buffering, using the
> > > dirtyfb ioctl, do the job?
> >
> > It does not see
Include drm_crtc_helper_internal.h to provide drm_connector_get_single_encoder
prototype.
Fixes: a92462d6bf493 ("drm/connector: Share with non-atomic drivers the
function to get the single encoder")
Cc: José Roberto de Souza
Signed-off-by: Benjamin Gaignard
---
drivers/gpu/drm/drm_crtc_helpe
Hi Nikolaus,
On Tue, Nov 19, 2019 at 10:42:55AM +0100, H. Nikolaus Schaller wrote:
> > Am 18.11.2019 um 15:51 schrieb H. Nikolaus Schaller :
> >
> >> Ok, I tried not to break video mode support, but I do not have any
> >> hardware. Make sure to set the MIPI_DSI_MODE_VIDEO flag in the panel
> >> d
Exported functions prototypes are missing in drm_fb_cma_helper.c
Include drm_fb_cma_helper to fix that issue.
Signed-off-by: Benjamin Gaignard
---
drivers/gpu/drm/drm_fb_cma_helper.c | 1 +
include/drm/drm_fb_cma_helper.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm
19.11.2019 09:25, Thierry Reding пишет:
> On Mon, Nov 18, 2019 at 11:02:26PM +0300, Dmitry Osipenko wrote:
>> Define interconnect IDs for memory controller (MC), external memory
>> controller (EMC), external memory (EMEM) and memory clients of display
>> controllers (DC).
>>
>> Signed-off-by: Dmitr
On Tue, 19 Nov 2019 17:55:57 +0200
Tomi Valkeinen wrote:
> On 19/11/2019 17:06, Tony Lindgren wrote:
>
> >> The userspace apps need to do this. If they're using single-buffering, then
> >> using the dirtyfb ioctl should do the trick, after the SGX has finished
> >> drawing.
> >
> > Sounds lik
On 2019-11-14 22:59, Stephen Boyd wrote:
Quoting Shubhashree Dhar (2019-11-13 21:56:16)
Current code assumes that all the irqs registers offsets can be
accessed in all the hw revisions; this is not the case for some
targets that should not access some of the irq registers.
What happens if we r
19.11.2019 09:30, Thierry Reding пишет:
> On Mon, Nov 18, 2019 at 11:02:30PM +0300, Dmitry Osipenko wrote:
>> All NVIDIA Tegra SoCs have identical topology in regards to memory
>> interconnection between memory clients and memory controllers.
>> The memory controller (MC) and external memory contro
[+cc Daniel, Vidya, Thierry; thread starts at
https://lore.kernel.org/r/20191017121901.13699-1-kher...@redhat.com]
On Tue, Nov 19, 2019 at 11:26:45PM +0100, Karol Herbst wrote:
> On Tue, Nov 19, 2019 at 10:50 PM Bjorn Helgaas wrote:
> > On Thu, Oct 17, 2019 at 02:19:01PM +0200, Karol Herbst wrote
On Tue, Nov 19, 2019 at 10:50 PM Bjorn Helgaas wrote:
>
> [+cc Dave]
>
> On Thu, Oct 17, 2019 at 02:19:01PM +0200, Karol Herbst wrote:
> > Fixes state transitions of Nvidia Pascal GPUs from D3cold into higher device
> > states.
> >
> > v2: convert to pci_dev quirk
> > put a proper technical ex
Hi Fabrizio,
On Tue, Nov 19, 2019 at 11:17:34AM +, Fabrizio Castro wrote:
> On 19 November 2019 00:16 Laurent Pinchart wrote:
> > On Wed, Nov 13, 2019 at 03:51:31PM +, Fabrizio Castro wrote:
> > > The lvds-codec driver is a generic stub for transparent LVDS
> > > encoders and decoders.
> >
[+cc Dave]
On Thu, Oct 17, 2019 at 02:19:01PM +0200, Karol Herbst wrote:
> Fixes state transitions of Nvidia Pascal GPUs from D3cold into higher device
> states.
>
> v2: convert to pci_dev quirk
> put a proper technical explanation of the issue as a in-code comment
> v3: disable it only for c
It is possible to set a flag in the struct mipi_dsi_device
so the panel is handled in low power (LP) mode. Some displays
only support this mode and it is also good for testing.
Cc: Stephan Gerhold
Signed-off-by: Linus Walleij
---
drivers/gpu/drm/mcde/mcde_dsi.c | 10 ++
1 file changed,
On Fri, Nov 15, 2019 at 10:33:24AM +, Oleksandr Andrushchenko wrote:
> On 11/15/19 11:21 AM, Daniel Vetter wrote:
> > The current code is a pretty good wtf moment, since we drop the
> > reference before we use it. It's not a big deal, because a) we only
> > use the pointer, so doesn't blow up a
On Fri, Nov 15, 2019 at 03:21:20PM +0200, Jyri Sarha wrote:
> On 15/11/2019 11:21, Daniel Vetter wrote:
> > Doesn't do anything.
> >
> > Signed-off-by: Daniel Vetter
> > Cc: Jyri Sarha
> > Cc: Tomi Valkeinen
>
> Acked-by: Jyri Sarha
Thanks for taking a look, pushed to drm-misc-next.
-Daniel
On Fri, Nov 15, 2019 at 10:33:24AM +0100, Boris Brezillon wrote:
> On Fri, 15 Nov 2019 10:21:14 +0100
> Daniel Vetter wrote:
>
> > Spotted while looking through them all.
> >
> > Signed-off-by: Daniel Vetter
> > Cc: Sam Ravnborg
> > Cc: Boris Brezillon
>
> Acked-by: Boris Brezillon
Merged,
On 19/11/2019 16:09, Mikita Lipski wrote:
On 19/11/2019 12:11, Ville Syrjälä wrote:
On Tue, Nov 19, 2019 at 04:59:40PM +, Cornij, Nikola wrote:
If you're going to make all of them the same, then u64, please.
This is because I'm not sure if calculations require 64-bit at some
stage.
Hi all,
While looking at (dynamic) dma-buf issues and ideas I've spotted a bit
more room for locking down the cross-driver dma_resv rules.
Only functional fallout is a tiny patch for msm, assuming I didn't botch
anything in the auditing of all relevant code.
Comments, review and testing very muc
On 19/11/2019 12:11, Ville Syrjälä wrote:
On Tue, Nov 19, 2019 at 04:59:40PM +, Cornij, Nikola wrote:
If you're going to make all of them the same, then u64, please.
This is because I'm not sure if calculations require 64-bit at some stage.
If it does then it's already broken. Someone s
Semnatically it really doesn't matter where we grab the ticket. But
since the ticket is a fake lockdep lock, it matters for lockdep
validation purposes.
This means stuff like grabbing a ticket and then doing
copy_from/to_user isn't allowed anymore. This is a changed compared to
the current ttm fau
For locking semantics it really doesn't matter when we grab the
ticket. But for lockdep validation it does: the acquire ctx is a fake
lockdep. Since other drivers might want to do a full multi-lock dance
in their fault-handler, not just lock a single dma_resv. Therefore we
must init the acquire_ctx
It's kinda really hard to get this wrong on a driver with both display
and dma_resv locking. But who ever knows, so better to make sure that
really all drivers nest these the same way.
For actual lock semantics the acquire context nesting doesn't matter.
But to teach lockdep what's going on with w
On Tue, Nov 19, 2019 at 3:11 PM Paul Kocialkowski
wrote:
>
> Hi,
>
> On Wed 13 Nov 19, 11:04, Patrik Jakobsson wrote:
> > On Tue, Nov 12, 2019 at 4:50 PM Paul Kocialkowski
> > wrote:
> > >
> > > Hi,
> > >
> > > On Tue 12 Nov 19, 16:11, Paul Kocialkowski wrote:
> > > > Hi,
> > > >
> > > > On Tue 1
On Mon, Oct 21, 2019 at 06:02:06PM +0200, Krzysztof Kozlowski wrote:
> Convert generic PWM controller bindings to DT schema format using
> json-schema. The consumer bindings are provided by dt-schema.
>
> Signed-off-by: Krzysztof Kozlowski
> Acked-by: Stephen Boyd
> Acked-by: Paul Walmsley
Lo
On Thu, 17 Oct 2019 at 22:19, Karol Herbst wrote:
>
> Fixes state transitions of Nvidia Pascal GPUs from D3cold into higher device
> states.
Can we get this acked/committed? At this stage I think we've done all
we can unless Intel actually escalate this internally and work out how
the hw is brok
https://bugzilla.kernel.org/show_bug.cgi?id=205049
Pierre-Eric Pelloux-Prayer (pierre-eric.pelloux-pra...@amd.com) changed:
What|Removed |Added
CC|
I test v3 and it works fine.
Regards,
Philip
On 2019-11-12 3:22 p.m., Jason Gunthorpe wrote:
From: Jason Gunthorpe
Convert the collision-retry lock around hmm_range_fault to use the one now
provided by the mmu_interval notifier.
Although this driver does not seem to use the collision retry l
On Tue, 2019-11-19 at 13:58 +0100, Benjamin Gaignard wrote:
> Include drm_crtc_helper_internal.h to provide
> drm_connector_get_single_encoder
> prototype.
>
> Fixes: a92462d6bf493 ("drm/connector: Share with non-atomic drivers
> the function to get the single encoder")
drm_connector_get_single_e
Hi Adrian,
On Mon, Nov 18, 2019 at 12:25 PM Adrian Ratiu
wrote:
Some nitpicks:
> +
> +config DRM_IMX_MIPI_DSI
> + tristate "Freescale i.MX DRM MIPI DSI"
This text seems too generic as there are i.MX SoCs that use different
MIPI DSI IP.
Maybe "Freescale i.MX6 DRM MIPI DSI" instead?
> +m
https://bugzilla.kernel.org/show_bug.cgi?id=205049
--- Comment #13 from Alex Deucher (alexdeuc...@gmail.com) ---
I'm not able to reproduce this on my raven systems. Could be a mesa issue.
Does setting the R600_DEBUG=nodcc environment variable help?
--
You are receiving this mail because:
You a
https://bugzilla.kernel.org/show_bug.cgi?id=205049
--- Comment #12 from le...@onet.pl ---
Is anyone actually working on this problem?
I just upgraded from Fedora 30 to 31, hoping that the upgrade might include
other miscellaneous changes that fix the problem, but the problem is EXACTLY
THE SAME.
Quoting Kalyan Thota (2019-11-18 02:47:43)
> Add display hw catalog changes for SC7180 target.
>
> Changes in v1:
>
> 1) Configure register offsets and capabilities for the
> display hw blocks.
>
> This patch has dependency on the below series
>
> https://patchwork.kernel.org/patch/11243111/
>
On Tue, Nov 19, 2019 at 04:59:40PM +, Cornij, Nikola wrote:
> If you're going to make all of them the same, then u64, please.
>
> This is because I'm not sure if calculations require 64-bit at some stage.
If it does then it's already broken. Someone should probably figure out
what's actally n
On Tue, Nov 19, 2019 at 8:43 AM Krzysztof Kozlowski wrote:
>
> With split of power domain controller bindings to power-domain.yaml, the
> consumer part was renamed to power-domain.txt. Update the references in
> other bindings.
>
> Reported-by: Geert Uytterhoeven
> Fixes: abb4805e343a ("dt-bindi
If you're going to make all of them the same, then u64, please.
This is because I'm not sure if calculations require 64-bit at some stage.
-Original Message-
From: Lipski, Mikita
Sent: November 19, 2019 10:08 AM
To: Ville Syrjälä ; Lipski, Mikita
Cc: amd-...@lists.freedesktop.org; dri
Hi,
On 19-11-2019 16:47, Ville Syrjälä wrote:
On Tue, Nov 19, 2019 at 04:18:18PM +0100, Hans de Goede wrote:
At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
different PWM controllers for controlling the LCD's backlight brightness.
Either the one integrated into the PMIC o
Hi Krzysztof,
On Tue, Nov 19, 2019 at 3:43 PM Krzysztof Kozlowski wrote:
> With split of power domain controller bindings to power-domain.yaml, the
> consumer part was renamed to power-domain.txt. Update the references in
> other bindings.
>
> Reported-by: Geert Uytterhoeven
> Fixes: abb4805e34
On 19/11/2019 17:06, Tony Lindgren wrote:
The userspace apps need to do this. If they're using single-buffering, then
using the dirtyfb ioctl should do the trick, after the SGX has finished
drawing.
Sounds like that's not happening.
But why would the userspace app need to know this might be n
On Tue, Nov 19, 2019 at 04:18:18PM +0100, Hans de Goede wrote:
> At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
> different PWM controllers for controlling the LCD's backlight brightness.
> Either the one integrated into the PMIC or the one integrated into the
> SoC (the 1st
On Tue, 19 Nov 2019, Hans de Goede wrote:
> Hi All,
>
> This series needs to be merged through a single tree, to keep things
> bisectable. I have even considered just squashing all 3 patches into 1,
> but having separate commits seems better, but that does lead to an
> intermediate state where the
At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
different PWM controllers for controlling the LCD's backlight brightness.
Either the one integrated into the PMIC or the one integrated into the
SoC (the 1st LPSS PWM controller).
So far in the LPSS code on BYT we have skipped
At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
different PWM controllers for controlling the LCD's backlight brightness.
Either the one integrated into the PMIC or the one integrated into the
SoC (the 1st LPSS PWM controller).
So far in the LPSS code on BYT we have skipped
At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
different PWM controllers for controlling the LCD's backlight brightness.
Either the one integrated into the PMIC or the one integrated into the
SoC (the 1st LPSS PWM controller).
So far in the LPSS code on BYT we have skipped
Hi All,
This series needs to be merged through a single tree, to keep things
bisectable. I have even considered just squashing all 3 patches into 1,
but having separate commits seems better, but that does lead to an
intermediate state where the backlight sysfs interface will be broken
(and fixed 2
On 19/11/2019 09:56, Ville Syrjälä wrote:
On Tue, Nov 19, 2019 at 09:45:26AM -0500, mikita.lip...@amd.com wrote:
From: Mikita Lipski
We shouldn't compare int with unsigned long to find the max value
and since we are not expecting negative value returned from
compute_offset we should make thi
Does gitlab not generate email when a comment is added to a ticket ?
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On Tue, Nov 19, 2019 at 09:45:26AM -0500, mikita.lip...@amd.com wrote:
> From: Mikita Lipski
>
> We shouldn't compare int with unsigned long to find the max value
> and since we are not expecting negative value returned from
> compute_offset we should make this function return unsigned long
> so
On 19/11/2019 16:32, Tony Lindgren wrote:
We haven't had omap_gem_op_finish() in the kernel for some years now...
Shouldn't a normal page flip, or if doing single-buffering, using the
dirtyfb ioctl, do the job?
It does not seem to happen with the old pvr-omap4 related patches
and whatever gle
Current implementation don't switch to RGB565 format if BGR888 was
previously used. Fix that.
Signed-off-by: Eugeniy Paltsev
---
drivers/gpu/drm/arc/arcpgu_crtc.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/arc/arcpgu_crtc.c
b/drivers/gpu/drm
Eugeniy Paltsev (4):
DRM: ARC: PGU: fix framebuffer format switching
DRM: ARC: PGU: cleanup supported format list code
DRM: ARC: PGU: replace unsupported by HW RGB888 format by XRGB888
DRM: ARC: PGU: add ARGB format to supported format list
drivers/gpu/drm/arc/arcpgu_crtc.c | 36 +
Get rid of 'simplefb_format' structure usage as we only use its
'fourcc' field.
Signed-off-by: Eugeniy Paltsev
---
drivers/gpu/drm/arc/arcpgu_crtc.c | 25 +++--
1 file changed, 11 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/arc/arcpgu_crtc.c
b/drivers/gpu/dr
ARC PGU doesn't support RGB888 (24 bit) format but supports
XRGB888 (32 bit) format. Fix incorrect format list in a driver.
Signed-off-by: Eugeniy Paltsev
---
drivers/gpu/drm/arc/arcpgu_crtc.c | 6 +++---
drivers/gpu/drm/arc/arcpgu_regs.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
As we ignore first 8 bit of 32 bit pixel value we can add ARGB
format as alias of XRGB.
Signed-off-by: Eugeniy Paltsev
---
drivers/gpu/drm/arc/arcpgu_crtc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/arc/arcpgu_crtc.c
b/drivers/gpu/drm/arc/arcpgu_crtc.c
index 98
From: Mikita Lipski
We shouldn't compare int with unsigned long to find the max value
and since we are not expecting negative value returned from
compute_offset we should make this function return unsigned long
so we can compare the values when computing rc parameters.
Cc: Nikola Cornij
Cc: Har
With split of power domain controller bindings to power-domain.yaml, the
consumer part was renamed to power-domain.txt. Update the references in
other bindings.
Reported-by: Geert Uytterhoeven
Fixes: abb4805e343a ("dt-bindings: power: Convert Samsung Exynos Power Domain
bindings to json-schema"
Hi,
On Wed 13 Nov 19, 11:04, Patrik Jakobsson wrote:
> On Tue, Nov 12, 2019 at 4:50 PM Paul Kocialkowski
> wrote:
> >
> > Hi,
> >
> > On Tue 12 Nov 19, 16:11, Paul Kocialkowski wrote:
> > > Hi,
> > >
> > > On Tue 12 Nov 19, 11:20, Patrik Jakobsson wrote:
> > > > On Thu, Nov 7, 2019 at 4:30 PM Pau
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