On Tue, Nov 24, 2015 at 5:56 PM, Richard Earnshaw
wrote:
> On 24/11/15 02:51, Bin.Cheng wrote:
>>>> The aarch64's problem is we don't define addptr3 pattern, and we don't
>>>> >> have direct insn pattern describing the "x + y << z"
On Sat, Nov 21, 2015 at 1:39 AM, Richard Earnshaw
wrote:
> On 20/11/15 08:31, Bin.Cheng wrote:
>> On Thu, Nov 19, 2015 at 10:32 AM, Bin.Cheng wrote:
>>> On Tue, Nov 17, 2015 at 6:08 PM, James Greenhalgh
>>> wrote:
>>>> On Tue, Nov 17, 2015 at 05:2
On Wed, Nov 18, 2015 at 11:50 PM, Bernd Schmidt wrote:
> On 11/10/2015 11:19 AM, Bin.Cheng wrote:
>>
>> On Tue, Nov 10, 2015 at 6:06 PM, Bernd Schmidt
>> wrote:
>>>
>>>
>>> Multi-line expressions should be wrapped in parentheses so that
>>
On Thu, Nov 19, 2015 at 10:32 AM, Bin.Cheng wrote:
> On Tue, Nov 17, 2015 at 6:08 PM, James Greenhalgh
> wrote:
>> On Tue, Nov 17, 2015 at 05:21:01PM +0800, Bin Cheng wrote:
>>> Hi,
>>> GIMPLE IVO needs to call backend interface to calculate costs for a
On Tue, Nov 17, 2015 at 6:08 PM, James Greenhalgh
wrote:
> On Tue, Nov 17, 2015 at 05:21:01PM +0800, Bin Cheng wrote:
>> Hi,
>> GIMPLE IVO needs to call backend interface to calculate costs for addr
>> expressions like below:
>>FORM1: "r73 + r74 + 16380"
>>FORM2: "r73 << 2 + r74 + 16380"
>
On Tue, Nov 17, 2015 at 1:56 AM, Ajit Kumar Agarwal
wrote:
>
> Sorry I missed out some of the points in earlier mail which is given below.
>
> -Original Message-
> From: Ajit Kumar Agarwal
> Sent: Monday, November 16, 2015 11:07 PM
> To: 'Jeff Law'; GCC Patches
> Cc: Vinod Kathail; Shail A
On Fri, Nov 13, 2015 at 2:13 PM, Jeff Law wrote:
> On 10/07/2015 10:32 PM, Ajit Kumar Agarwal wrote:
>
>>
>> 0001-RFC-Patch-Optimized-changes-in-the-register-used-ins.patch
>>
>>
>> From f164fd80953f3cffd96a492c8424c83290cd43cc Mon Sep 17 00:00:00 2001
>> From: Ajit Kumar Agarwal
>> Date: Wed, 7
On Tue, Nov 10, 2015 at 6:06 PM, Bernd Schmidt wrote:
> On 11/10/2015 09:25 AM, Bin.Cheng wrote:
>>>
>>> Thanks for reviewing. I haven't committed it yet, could you please
>>> point out which quoted piece is so that I can update patch?
>
>
On Tue, Nov 10, 2015 at 9:26 AM, Bin.Cheng wrote:
> On Mon, Nov 9, 2015 at 11:24 PM, Bernd Schmidt wrote:
>> On 11/08/2015 10:11 AM, Richard Biener wrote:
>>>
>>> On November 8, 2015 3:58:57 AM GMT+01:00, "Bin.Cheng"
>>> wrote:
>>>>>
On Mon, Nov 9, 2015 at 11:24 PM, Bernd Schmidt wrote:
> On 11/08/2015 10:11 AM, Richard Biener wrote:
>>
>> On November 8, 2015 3:58:57 AM GMT+01:00, "Bin.Cheng"
>> wrote:
>>>>
>>>> +inline bool
>>&
On Fri, Nov 6, 2015 at 9:24 PM, Richard Biener
wrote:
> On Wed, Nov 4, 2015 at 11:18 AM, Bin Cheng wrote:
>> Hi,
>> PR52272 reported a performance regression in spec2006/410.bwaves once GCC is
>> prevented from representing address of one memory object using address of
>> another memory object.
On Wed, Oct 21, 2015 at 11:55 AM, Bin.Cheng wrote:
> On Fri, Oct 9, 2015 at 8:04 PM, Bernd Schmidt wrote:
>> On 10/09/2015 02:00 PM, Bin.Cheng wrote:
>>>
>>> I further bootstrap and test attached patch on aarch64. Also three
>>> cases in spec2k6/fp are impro
On Wed, Oct 21, 2015 at 5:15 PM, Richard Biener
wrote:
> On Wed, Oct 21, 2015 at 6:46 AM, Bin Cheng wrote:
>> Hi,
>> As analyzed in PR67921, I think the issue is caused by fold_binary_loc which
>> folds:
>> 4 - (sizetype) &c - (sizetype) ((int *) p1_8(D) + ((sizetype) a_23 * 24 +
>> 4))
>> into
On Fri, Oct 9, 2015 at 8:04 PM, Bernd Schmidt wrote:
> On 10/09/2015 02:00 PM, Bin.Cheng wrote:
>>
>> I further bootstrap and test attached patch on aarch64. Also three
>> cases in spec2k6/fp are improved by 3~6%, two cases in spec2k6/fp are
>> regressed by ~2%. O
On Wed, Sep 30, 2015 at 12:00 AM, Pat Haugen
wrote:
> On 09/25/2015 11:51 PM, Ajit Kumar Agarwal wrote:
>>
>> I have made the following changes in the estimate_reg_pressure_cost
>> function used
>> by the loop invariant and IVOPTS.
>>
>> Earlier the estimate_reg_pressure cost uses the cost of n_ne
On Wed, Sep 30, 2015 at 11:33 AM, Bin.Cheng wrote:
> On Tue, Sep 29, 2015 at 1:21 AM, Jeff Law wrote:
>> On 09/28/2015 05:28 AM, Bernd Schmidt wrote:
>>>
>>> On 09/28/2015 11:43 AM, Bin Cheng wrote:
>>>>
>>>> Bootstrap and test on x86_64
On Thu, Oct 8, 2015 at 1:53 PM, Ajit Kumar Agarwal
wrote:
>
>
> -Original Message-
> From: Bin.Cheng [mailto:amker.ch...@gmail.com]
> Sent: Thursday, October 08, 2015 10:29 AM
> To: Ajit Kumar Agarwal
> Cc: GCC Patches; Vinod Kathail; Shail Aditya Gupta; Vidhumouli H
On Thu, Oct 8, 2015 at 5:55 PM, Bernd Schmidt wrote:
> On 10/08/2015 07:17 AM, Bin.Cheng wrote:
>>
>> On Thu, Oct 8, 2015 at 12:59 PM, Richard Henderson wrote:
>>>
>>> This is the patch that richi includes in the PR. There will need to
>>> be an ad
On Thu, Oct 8, 2015 at 12:59 PM, Richard Henderson wrote:
> This is the patch that richi includes in the PR. There will need to
> be an additional patch to solve an ICE for the AVR backend, as noted
> in the PR, but this is good enough to solve the bad-code generation
> problem for the i386 backe
On Thu, Oct 8, 2015 at 12:32 PM, Ajit Kumar Agarwal
wrote:
> Following Proposed:
>
> Changes are done in the Loop Invariant(LICM) at RTL level and also the
> Induction variable optimization based on SSA representation.
> The current logic used in LICM for register used inside the loops is changed
On Tue, Sep 29, 2015 at 1:21 AM, Jeff Law wrote:
> On 09/28/2015 05:28 AM, Bernd Schmidt wrote:
>>
>> On 09/28/2015 11:43 AM, Bin Cheng wrote:
>>>
>>> Bootstrap and test on x86_64 and x86_32. Will test it on aarch64. So
>>> any
>>> comments?
>>>
>>> Thanks,
>>> bin
>>>
>>> 2015-09-28 Bin Cheng
On Tue, Sep 29, 2015 at 2:25 AM, Aaron Sawdey
wrote:
> On Sat, 2015-09-26 at 04:51 +, Ajit Kumar Agarwal wrote:
>> I have made the following changes in the estimate_reg_pressure_cost function
>> used
>> by the loop invariant and IVOPTS.
>>
>> Earlier the estimate_reg_pressure cost uses the co
On Sun, Sep 27, 2015 at 11:13 PM, Ajit Kumar Agarwal
wrote:
>
>
> -Original Message-
> From: Segher Boessenkool [mailto:seg...@kernel.crashing.org]
> Sent: Sunday, September 27, 2015 7:49 PM
> To: Ajit Kumar Agarwal
> Cc: GCC Patches; Vinod Kathail; Shail Aditya Gupta; Vidhumouli Hunsigida
On Sat, Sep 26, 2015 at 12:51 PM, Ajit Kumar Agarwal
wrote:
> I have made the following changes in the estimate_reg_pressure_cost function
> used
> by the loop invariant and IVOPTS.
>
> Earlier the estimate_reg_pressure cost uses the cost of n_new variables that
> are generated by the Loop Invar
Ping.
On Thu, Aug 27, 2015 at 5:41 PM, Bin Cheng wrote:
> Hi,
> This is a rework for
> https://gcc.gnu.org/ml/gcc-patches/2015-07/msg02335.html, with review
> comments addressed. For now, SCEV may compute iv base in the form of
> "(signed T)((unsigned T)base + step))". This complicates other
>
Just realized that I missed the updated patch before. Here it is...
Thanks,
bin
On Tue, Sep 8, 2015 at 6:07 PM, Bin.Cheng wrote:
> On Tue, Sep 8, 2015 at 6:06 PM, Bin.Cheng wrote:
>> On Wed, Sep 2, 2015 at 10:12 PM, Richard Biener
>> wrote:
>>> On Wed, Sep 2, 20
On Wed, Sep 2, 2015 at 8:32 PM, Richard Biener
wrote:
> On Wed, Sep 2, 2015 at 5:50 AM, Bin Cheng wrote:
>> Hi,
>> When calling get_shiftadd_cost, the mult_op is stripped at caller places.
>> We should look into unnecessary conversion in op1 before checking equality,
>> otherwise it computes wron
On Tue, Sep 8, 2015 at 6:06 PM, Bin.Cheng wrote:
> On Wed, Sep 2, 2015 at 10:12 PM, Richard Biener
> wrote:
>> On Wed, Sep 2, 2015 at 5:26 AM, Bin Cheng wrote:
>>> Hi,
>>> This patch is a new approach to fix PR66388. IVO today computes iv_use with
>>&g
On Wed, Sep 2, 2015 at 10:12 PM, Richard Biener
wrote:
> On Wed, Sep 2, 2015 at 5:26 AM, Bin Cheng wrote:
>> Hi,
>> This patch is a new approach to fix PR66388. IVO today computes iv_use with
>> iv_cand which has at least same type precision as the use. On 64bit
>> platforms like AArch64, this
On Thu, Aug 27, 2015 at 6:54 PM, Ajit Kumar Agarwal
wrote:
>
>
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On
> Behalf Of Bin Cheng
> Sent: Thursday, August 27, 2015 3:12 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH GCC][rework]I
On Wed, Aug 26, 2015 at 3:29 PM, Richard Biener wrote:
> On Wed, 26 Aug 2015, Bin.Cheng wrote:
>
>> On Wed, Aug 26, 2015 at 3:50 AM, Jeff Law wrote:
>> > On 08/25/2015 05:06 AM, Alan Lawrence wrote:
>> >>
>> >> When SRA completely scalarizes an
On Wed, Aug 26, 2015 at 3:50 AM, Jeff Law wrote:
> On 08/25/2015 05:06 AM, Alan Lawrence wrote:
>>
>> When SRA completely scalarizes an array, this patch changes the
>> generated accesses from e.g.
>>
>> MEM[(int[8] *)&a + 4B] = 1;
>>
>> to
>>
>> a[1] = 1;
>>
>> This overcomes a limitation in dom2
On Fri, Aug 14, 2015 at 4:28 PM, Richard Biener
wrote:
> On Tue, Jul 28, 2015 at 11:38 AM, Bin Cheng wrote:
>> Hi,
>> For now, SCEV may compute iv base in the form of "(signed T)((unsigned
>> T)base + step))". This complicates other optimizations/analysis depending
>> on SCEV because it's hard t
On Wed, Aug 19, 2015 at 5:19 AM, Segher Boessenkool
wrote:
> Hi,
>
> I've used this patch in the past for another port, and now again for
> rs6000, and I think it is generally useful. It prints very verbose
> information to the dump file about how ivopts comes up with its costs
> for various form
On Wed, Aug 19, 2015 at 2:14 AM, Jeff Law wrote:
> On 08/17/2015 04:01 AM, Bin.Cheng wrote:
>>>
>>>
>>> + c0 = fold_convert (type, c0);
>>> + c1 = fold_convert (type, c1);
>>> +
>>> + if (operand_equal_p (var, c0, 0))
&g
On Tue, Aug 18, 2015 at 4:02 PM, Ajit Kumar Agarwal
wrote:
>
>
> -Original Message-
> From: Bin.Cheng [mailto:amker.ch...@gmail.com]
> Sent: Tuesday, August 18, 2015 1:08 PM
> To: Ajit Kumar Agarwal
> Cc: Richard Biener; Bin Cheng; GCC Patches; Vinod Kathail;
de is collecting some comparison
basic block of loop?
Thanks,
bin
>
> Thanks & Regards
> Ajit
>
>
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On
> Behalf Of Bin.Cheng
> Sent: Monday, August 17, 2015 3:32 PM
> To: Richa
Thanks for all your reviews.
On Fri, Aug 14, 2015 at 4:17 PM, Richard Biener
wrote:
> On Tue, Jul 28, 2015 at 11:36 AM, Bin Cheng wrote:
>> Hi,
>> Loop niter computes inaccurate bound information for different loops. This
>> patch is to improve it by using loop initial condition in
>> determine
On Fri, Aug 14, 2015 at 6:10 AM, Jeff Law wrote:
> On 07/28/2015 03:38 AM, Bin Cheng wrote:
>>
>> Hi,
>> For now, SCEV may compute iv base in the form of "(signed T)((unsigned
>> T)base + step))". This complicates other optimizations/analysis depending
>> on SCEV because it's hard to dive into ty
On Fri, Aug 14, 2015 at 6:08 AM, Jeff Law wrote:
> On 07/28/2015 03:36 AM, Bin Cheng wrote:
>>
>> Hi,
>> Loop niter computes inaccurate bound information for different loops.
>> This
>> patch is to improve it by using loop initial condition in
>> determine_value_range. Generally, loop niter is co
Ping.
Thanks,
bin
On Tue, Jul 28, 2015 at 5:38 PM, Bin Cheng wrote:
> Hi,
> For now, SCEV may compute iv base in the form of "(signed T)((unsigned
> T)base + step))". This complicates other optimizations/analysis depending
> on SCEV because it's hard to dive into type conversions. For many cas
Ping.
Thanks,
bin
On Tue, Jul 28, 2015 at 5:36 PM, Bin Cheng wrote:
> Hi,
> Loop niter computes inaccurate bound information for different loops. This
> patch is to improve it by using loop initial condition in
> determine_value_range. Generally, loop niter is computed by subtracting
> start v
On Mon, Jul 27, 2015 at 12:23 PM, Bin.Cheng wrote:
> On Mon, Jul 27, 2015 at 11:41 AM, Michael Collison
> wrote:
>> This patch is designed to optimize end of loop conditions involving of the
>> form
>> i < x && i < y into i < min (x, y). Loop conditi
On Mon, Jul 27, 2015 at 11:41 AM, Michael Collison
wrote:
> This patch is designed to optimize end of loop conditions involving of the
> form
> i < x && i < y into i < min (x, y). Loop condition involving '>' are
> handled similarly using max(x,y).
> As an example:
>
> #define N 1024
>
> int a[N
On Fri, Jul 24, 2015 at 7:23 PM, Richard Biener
wrote:
> On Fri, Jul 24, 2015 at 1:09 PM, Bin.Cheng wrote:
>> On Thu, Jul 23, 2015 at 10:06 PM, Richard Biener
>> wrote:
>>> On Fri, Jul 17, 2015 at 8:27 AM, Bin Cheng wrote:
>>>> Hi,
>>>> This
On Thu, Jul 23, 2015 at 10:06 PM, Richard Biener
wrote:
> On Fri, Jul 17, 2015 at 8:27 AM, Bin Cheng wrote:
>> Hi,
>> This patch is to fix PR66388. It's an old issue but recently became worse
>> after my scev overflow change. IVOPT now can only compute iv use with
>> candidate which has at leas
Ping^2
On Thu, Jul 9, 2015 at 5:42 PM, Bin.Cheng wrote:
> Ping.
>
> On Fri, Jun 26, 2015 at 4:47 PM, Bin Cheng wrote:
>> Hi,
>> The canonical form of subtract of immediate is (add op0 minus_imm), which is
>> supported with addsi3_aarch64 pattern on aarch64. Unf
On Thu, Jul 9, 2015 at 5:49 PM, Richard Biener
wrote:
> On Thu, Jul 9, 2015 at 11:37 AM, Bin Cheng wrote:
>> Hi,
>> When I going through the code, I spot this minor issue. When
>> start_cand/orig_cand/third_cand have overall cost in order like "start_cand
>> < third_cand < orig_cand", GCC choose
Ping.
On Fri, Jun 26, 2015 at 4:47 PM, Bin Cheng wrote:
> Hi,
> The canonical form of subtract of immediate is (add op0 minus_imm), which is
> supported with addsi3_aarch64 pattern on aarch64. Unfortunately wrong cost
> (8 rather than 4) is computed by aarch64_rtx_cost because it doesn't honor
>
On Sat, Jun 27, 2015 at 5:13 AM, Jeff Law wrote:
> On 06/26/2015 03:02 AM, Bin Cheng wrote:
>>
>> Hi,
>> GCC avoids multi-pointers/dangling-pointers of struct iv by allocating
>> multiple copies of the structure. This patch is an obvious fix to the
>> issue
>> by managing iv structures in obstack
Hi,
I applied this obvious patch to trunk. It was approved in last Stage 4.
Thanks,
bin
2015-06-03 Bin Cheng
* tree-ssa-loop-ivopts.c (dump_iv): New parameter.
(dump_use, dump_cand, find_induction_variables): Pass new argument
to dump_iv.
(record_use): Preserve the ssa name i
On Tue, Jun 2, 2015 at 11:40 PM, Bernhard Reutner-Fischer
wrote:
> On June 2, 2015 5:56:13 AM GMT+02:00, Bin Cheng wrote:
>>Hi,
>>On some arm processors, the offset supported in addressing modes is
>>very
>>small. As a result, the dozens of address induction variables will be
>>grouped into seve
On Tue, Jun 2, 2015 at 11:37 AM, Bin.Cheng wrote:
> On Tue, May 26, 2015 at 5:04 PM, Richard Biener
> wrote:
>> On Sun, May 24, 2015 at 8:47 AM, Bin.Cheng wrote:
>>> On Fri, May 22, 2015 at 7:45 PM, Richard Biener
>>> wrote:
>>>> On Wed, May 20, 20
On Tue, Jun 2, 2015 at 4:40 PM, Richard Biener
wrote:
> On Tue, Jun 2, 2015 at 4:55 AM, Bin.Cheng wrote:
>> On Mon, Jun 1, 2015 at 6:45 PM, Richard Biener
>> wrote:
>>> On Tue, May 26, 2015 at 1:04 PM, Bin Cheng wrote:
>>>> Hi,
>>>> My first par
On Tue, May 26, 2015 at 5:04 PM, Richard Biener
wrote:
> On Sun, May 24, 2015 at 8:47 AM, Bin.Cheng wrote:
>> On Fri, May 22, 2015 at 7:45 PM, Richard Biener
>> wrote:
>>> On Wed, May 20, 2015 at 11:41 AM, Bin Cheng wrote:
>>>> Hi,
>>>> A
On Mon, Jun 1, 2015 at 6:45 PM, Richard Biener
wrote:
> On Tue, May 26, 2015 at 1:04 PM, Bin Cheng wrote:
>> Hi,
>> My first part patch improving how we handle overflow in scev is posted at
>> https://gcc.gnu.org/ml/gcc-patches/2015-05/msg01795.html . Here comes the
>> second part patch.
>>
>> T
On Mon, Jun 1, 2015 at 6:41 PM, Richard Biener
wrote:
> On Tue, May 26, 2015 at 1:13 PM, Bin.Cheng wrote:
>> Hi,
>> The first part patch improving how we handle overflow in scev is
>> posted at https://gcc.gnu.org/ml/gcc-patches/2015-05/msg01795.html .
>> Here
On Mon, Jun 1, 2015 at 4:00 PM, Richard Biener
wrote:
> On Sat, May 30, 2015 at 7:47 AM, Jeff Law wrote:
>> On 05/19/2015 10:12 AM, Aditya K wrote:
>>>
>>> w.r.t. the PR48052, here is the patch which finds out if scev would wrap
>>> or not.
>>> The patch symbolically evaluates if valid_niter>= lo
On Wed, May 27, 2015 at 11:44 PM, Kyrill Tkachov wrote:
> Hi Bin,
>
>
> On 08/05/15 11:47, Bin Cheng wrote:
>>
>> Hi,
>> GCC's IVO currently handles every IV use independently, which is not right
>> by learning from cases reported in PR65447.
>>
>> The rationale is:
>> 1) Lots of address type IVs
On Wed, May 27, 2015 at 4:39 PM, Andrew Pinski wrote:
> On Wed, May 27, 2015 at 4:38 PM, Kyrill Tkachov
> wrote:
>> Ping.
>> https://gcc.gnu.org/ml/gcc-patches/2015-05/msg00054.html
>
> This and the one in AARCH64 is too noisy. Can we have an option to
> turn this on and default to turning them
Hi,
The first part patch improving how we handle overflow in scev is
posted at https://gcc.gnu.org/ml/gcc-patches/2015-05/msg01795.html .
Here comes the second part patch.
This patch does below improvements:
1) Computes and records control iv for each loop's exit edge. This
provides a way to co
On Fri, May 22, 2015 at 7:45 PM, Richard Biener
wrote:
> On Wed, May 20, 2015 at 11:41 AM, Bin Cheng wrote:
>> Hi,
>> As we know, GCC is too conservative when checking overflow behavior in SCEV
>> and loop related optimizers. Result is some variable can't be recognized as
>> scalar evolution and
On Fri, May 22, 2015 at 4:58 PM, Kyrill Tkachov
wrote:
> Hi Venkat,
>
>
> On 22/05/15 09:50, Kumar, Venkataramanan wrote:
>>
>> Hi Kyrill,
>>
>> Sorry for little delay in responding.
>>
>>> -Original Message-
>>> From: Kyrill Tkachov [mailto:kyrylo.tkac...@foss.arm.com]
>>> Sent: Tuesday,
On Wed, May 6, 2015 at 7:02 PM, Richard Biener
wrote:
> On Mon, May 4, 2015 at 9:47 PM, Abderrazek Zaafrani
> wrote:
>> This is an old thread and we are still running into similar issues:
>> Code is not being vectorized on 64-bit target due to scev not being
>> able to optimally analyze overflow
On Wed, May 13, 2015 at 7:38 PM, Richard Biener
wrote:
> On Fri, May 8, 2015 at 12:47 PM, Bin Cheng wrote:
>> Hi,
>> GCC's IVO currently handles every IV use independently, which is not right
>> by learning from cases reported in PR65447.
>>
>> The rationale is:
>> 1) Lots of address type IVs ref
On Mon, Apr 27, 2015 at 9:26 PM, Bill Schmidt
wrote:
> On Mon, 2015-04-27 at 14:23 +0800, Bin.Cheng wrote:
>> On Mon, Mar 30, 2015 at 1:42 AM, Bill Schmidt
>> wrote:
>
>>
>> > Index: gc
On Mon, Apr 27, 2015 at 8:01 PM, Uros Bizjak wrote:
> On Wed, Feb 4, 2015 at 2:21 PM, Christian Bruel
> wrote:
>> While trying to reduce the PR64835 case for ARM and x86, I noticed that the
>> alignment flags are cleared for x86 when attribute optimized is used.
>>
>> With the attached testcases
On Fri, Apr 24, 2015 at 12:52 PM, Thomas Preud'homme
wrote:
>> From: Jeff Law [mailto:l...@redhat.com]
>> Sent: Friday, April 24, 2015 11:15 AM
>>
>> So revised review is "ok for the trunk" :-)
>
> Committed.
Hi Thomas,
The newly introduced test failed on
arm-none-linux-gnueabi&arm-none-linux-gnue
On Thu, Apr 23, 2015 at 10:51 PM, Ramana Radhakrishnan
wrote:
> On Mon, Mar 30, 2015 at 9:25 PM, Kwok Cheung Yeung
> wrote:
>> This is a simple patch that ensures that a .size directive is emitted when
>> space is allocated for a static variable in the BSS on bare-metal ARM
>> targets. This allo
On Mon, Apr 27, 2015 at 6:20 PM, Richard Sandiford
wrote:
> I think it's been the case for a while that parallel builds of GCC tend
> to serialise around the compilation of insn-recog.c, especially with
> higher --enable-checking settings. This patch tries to speed that
> up by replacing most of
On Mon, Mar 30, 2015 at 1:42 AM, Bill Schmidt
wrote:
> Hi,
>
> This is a follow-up to
> https://gcc.gnu.org/ml/gcc-patches/2015-03/msg00103.html, which adds
> support for faster unaligned vector memory accesses on POWER8. As
> pointed out in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65456, the
On Tue, Apr 21, 2015 at 3:10 PM, Tom de Vries wrote:
> Hi,
>
> this patch fixes PR65802.
>
> diff --git a/gcc/testsuite/g++.dg/
pr65802.C b/gcc/testsuite/g++.dg/pr65802.C
> new file mode 100644
> index 000..26e5317
> --- /dev/null
> +++ b/gcc/testsuite/g++.dg/pr65802.C
> @@ -0,0 +1,29 @@
> +//
On Thu, Apr 23, 2015 at 4:19 PM, Kyrill Tkachov wrote:
>
> On 22/04/15 09:42, Bin Cheng wrote:
>>
>> Hi,
>> Case pr42172-1.c failed on pre-armv7 processors because GCC actually
>> generates better code without ldr instruction. This patch just refines
>> test
>> case by checking str instead of ldr
On Thu, Apr 16, 2015 at 4:55 PM, Richard Biener wrote:
> On Thu, 16 Apr 2015, Tom de Vries wrote:
>
>> [stage1 ping^2]
>> On 10-03-15 16:30, Tom de Vries wrote:
>> > [stage1 ping]
>> > On 22-02-15 14:13, Tom de Vries wrote:
>> > > On 19-02-15 14:03, Richard Biener wrote:
>> > > > On Thu, 19 Feb 20
On Wed, Mar 18, 2015 at 5:06 PM, Kyrill Tkachov wrote:
>
> On 17/03/15 19:11, Jeff Law wrote:
>>
>> On 03/16/2015 04:12 AM, Kyrill Tkachov wrote:
>>>
>>> Hi all,
>>>
>>> Eyeballing the mult_by_coeff_cost function I think it has a typo/bug.
>>> It's supposed to return the cost of multiplying by a c
On Fri, Mar 13, 2015 at 7:56 PM, Ramana Radhakrishnan
wrote:
> On Fri, Mar 6, 2015 at 7:46 AM, Bin Cheng wrote:
>> Hi,
>> This patch is the second part fixing memset-inline-{4,5,6,8,9}.c failures on
>> cortex-a9. It adds a function checking CPU tuning information in dejagnu,
>> it also uses that
Ping.
Thanks,
bin
On Fri, Mar 6, 2015 at 3:46 PM, Bin Cheng wrote:
> Hi,
> This patch is the second part fixing memset-inline-{4,5,6,8,9}.c failures on
> cortex-a9. It adds a function checking CPU tuning information in dejagnu,
> it also uses that function to skip related testcase when we are c
Ping.
This is for case failures and it doesn't affect normal compilation, so
I suppose it's fine for this stage?
Thanks,
bin
On Fri, Mar 6, 2015 at 3:42 PM, Bin Cheng wrote:
> Hi,
> This patch is the first part fixing memset-inline-{4,5,6,8,9}.c failures on
> cortex-a9. GCC/arm doesn't generate
On Wed, Feb 11, 2015 at 7:24 PM, Richard Biener
wrote:
> On Wed, Feb 11, 2015 at 9:23 AM, Bin.Cheng wrote:
>> On Tue, Feb 10, 2015 at 12:24 AM, Richard Biener
>> wrote:
>>
>> Previously, the computation of _1174 can be replaced by _629 in bb8 in
>> DOM2 pa
On Wed, Feb 11, 2015 at 4:55 AM, Jeff Law wrote:
>
> This PR was originally minor issue where we regressed on this kind of
> sequence:
>
> typedef struct toto_s *toto_t;
> toto_t add (toto_t a, toto_t b) {
> int64_t tmp = (int64_t)(intptr_t)a + ((int64_t)(intptr_t)b&~1L);
> return (toto_t)(int
On Tue, Feb 10, 2015 at 12:24 AM, Richard Biener
wrote:
> On February 9, 2015 11:09:49 AM CET, Bin Cheng wrote:
>
> Did you extract a testcase for it? Note that the IV step itself may be
> expanded
> Too much.
>
> I
>>looked into the regression and thought it was because of passes after
>>IVO
On Tue, Feb 10, 2015 at 6:18 PM, Bin.Cheng wrote:
> On Tue, Feb 10, 2015 at 6:02 PM, Richard Biener
> wrote:
>> On Mon, Feb 9, 2015 at 11:33 AM, Bin Cheng wrote:
>>> The second time I missed patch in one day, I hate myself.
>>> Here it is.
>>
>> I thin
On Tue, Feb 10, 2015 at 6:02 PM, Richard Biener
wrote:
> On Mon, Feb 9, 2015 at 11:33 AM, Bin Cheng wrote:
>> The second time I missed patch in one day, I hate myself.
>> Here it is.
>
> I think the patch is reasonable but I would have used a default = NULL
> arg for 'stop' to make the patch smal
On Wed, Feb 4, 2015 at 12:28 AM, Jeff Law wrote:
> On 02/03/15 01:29, Bin.Cheng wrote:
>>
>>
>> Hmm, if I understand correctly, it's a code size regression, so I
>> don't think it's appropriate to adapt the test case. Either the patch
>> or somet
On Tue, Feb 3, 2015 at 3:24 PM, Jeff Law wrote:
> On 02/02/15 08:59, Alex Velenko wrote:
>>
>> On 11/10/14 13:44, Felix Yang wrote:
>>>
>>> Hello Jeff,
>>>
>>> I see that you have improved the RTL typesafety issue for ira.c,
>>> so I rebased this patch
>>> on the latest trunk and change
On Fri, Jan 16, 2015 at 5:04 AM, Jeff Law wrote:
>
> Stage3 is closing rapidly. I've drained my queue of patches I was tracking
> for gcc-5.However, note that I don't track everything. If it's a patch
> for a backend, language other than C or seemingly has another maintainer
> that's engaged
On Fri, Jan 9, 2015 at 6:03 AM, Jeff Law wrote:
> On 01/08/15 08:58, Kito Cheng wrote:
>>
>> Hi Jeff:
>>
>> After discussion with Bin, he prefer just use
>> gcc.c-torture/execute/scal-to-vec1.c
>> instead of introduce new one, do you have any further comment on this
>> patch?
>
> Ah, if there's an
nce it introduces conflict option failures when testing against
specific processor, e.g. testing against Cortex-M profile processors.
Thanks,
bin
>
> On Wed, Jan 7, 2015 at 4:50 PM, Bin.Cheng wrote:
>> On Wed, Jan 7, 2015 at 4:03 PM, Kito Cheng wrote:
>>> Hi Jeff:
>>
On Wed, Jan 7, 2015 at 4:03 PM, Kito Cheng wrote:
> Hi Jeff:
>
> It's updated patch,bootstrapped and run regression tested on arm-eabi,
> arm-none-linux-uclibcgnueabi, x86_64-unknown-linux-gnu and nds32le-elf
> without introducing regression.
>
> Thanks for your review :)
>
> 2015-01-07 Kito Chen
On Tue, Jan 6, 2015 at 7:36 AM, Vladimir Makarov wrote:
>
> On 2015-01-05 12:31 PM, Jeff Law wrote:
>>
>> On 01/05/15 00:44, Kito Cheng wrote:
>>>
>>> Hi Vladimir:
>>>This patch has a discusses with you in May 2014, this patch is about
>>> the caller-save register store and restore instruction
On Mon, Jan 5, 2015 at 3:44 PM, Kito Cheng wrote:
> Hi Vladimir:
> This patch has a discusses with you in May 2014, this patch is about
> the caller-save register store and restore instruction generation, the
> current LRA implementation will miss caller-save store/restore
> instruction if need
On Tue, Dec 16, 2014 at 6:37 PM, Bin.Cheng wrote:
> On Thu, Nov 13, 2014 at 1:54 PM, Bin Cheng wrote:
>> Hi,
>> As commented at https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00684.html,
>> this is a simple patch enabling neon memset inlining on
>> cortex-a53
On Sun, Jan 4, 2015 at 6:55 AM, Andrew Pinski wrote:
> On Mon, Nov 24, 2014 at 1:32 PM, Jeff Law wrote:
>> On 11/22/14 21:20, Andrew Pinski wrote:
>>>
>>> Hi,
>>>The problem here is here is that OBJCOPY is not being set to the
>>> newly built objcopy when compiling libgo. This patch adds
>>>
On Wed, Dec 24, 2014 at 4:35 PM, zhangjian wrote:
> Hi, guys
>
> I encounter a gcc failure when I build mysql on opensuse[1]
> 5.6.17/storage/perfschema/pfs_account.cc:320:1: error: could not split insn
> [ 1245s] }
> [ 1245s] ^
> [ 1245s] (insn 482 1770 1461 (parallel [
> [ 1245s] (
On Mon, Dec 22, 2014 at 3:54 PM, Bin.Cheng wrote:
> On Sat, Dec 20, 2014 at 8:18 PM, Eric Botcazou wrote:
>>> As described both in the PR and patch comments, this patch fixes PR62151 by
>>> setting right value to ELIM_I0/ELIM_I1 when distributing REG_DEAD notes from
>&g
On Sat, Dec 20, 2014 at 8:18 PM, Eric Botcazou wrote:
>> As described both in the PR and patch comments, this patch fixes PR62151 by
>> setting right value to ELIM_I0/ELIM_I1 when distributing REG_DEAD notes from
>> i0/i1. It is said that distribute_notes had caused many bugs in the past.
>> I th
On Fri, Dec 19, 2014 at 6:09 AM, Segher Boessenkool
wrote:
> On Thu, Dec 18, 2014 at 05:00:01PM +, Jiong Wang wrote:
>> On 17/12/14 15:54, Richard Biener wrote:
>> >ick. I realize we don't have SSA form on RTL but doesn't DF provide
>> >at least some help in looking up definition statements f
On Tue, Dec 16, 2014 at 4:42 PM, Bin.Cheng wrote:
> On Thu, Dec 11, 2014 at 8:08 PM, Richard Biener
> wrote:
>> On Thu, Dec 11, 2014 at 10:56 AM, Bin.Cheng wrote:
>>> On Wed, Dec 10, 2014 at 9:47 PM, Richard Biener
>>> wrote:
>>>> On Fri, Dec 5, 2
Please ignore this one, I will further refine it. Sorry for disturbing!
Thanks,
bin
On Tue, Dec 16, 2014 at 4:42 PM, Bin.Cheng wrote:
> On Thu, Dec 11, 2014 at 8:08 PM, Richard Biener
> wrote:
>> On Thu, Dec 11, 2014 at 10:56 AM, Bin.Cheng wrote:
>>> On Wed, Dec 10, 201
On Thu, Nov 13, 2014 at 1:54 PM, Bin Cheng wrote:
> Hi,
> As commented at https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00684.html,
> this is a simple patch enabling neon memset inlining on
> cortex-a53/cortex-a57 in AArch32 mode.
>
> Test on
> arm-none-linux-gnueabihf/--with-cpu=cortex-a57/--with
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