/target-supports.exp: Add testing infrastructure to require the A
extension or add it to an existing -march.
Signed-off-by: Patrick O'Neill
---
This patch relies on the previous one in the series. If applied seperately,
amo-table-a-6-store-compat-3.c and amo-table-a-6-load-3.c mu
.
* config/riscv/sync-ztso.md (atomic_load_ztso): Ditto.
(atomic_store_ztso): Ditto.
* config/riscv/sync.md (atomic_load): Ditto.
(atomic_store): Ditto.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/sync-rvwmo.md | 4 ++--
gcc/config/riscv/sync-ztso.md
the
Ztso extension or add it to an existing -march.
Signed-off-by: Patrick O'Neill
---
.../riscv/amo-table-ztso-amo-add-1.c | 3 ++-
.../riscv/amo-table-ztso-amo-add-2.c | 3 ++-
.../riscv/amo-table-ztso-amo-add-3.c | 3 ++-
.../riscv/amo-table-ztso-amo-ad
On 10/30/23 09:55, Jeff Law wrote:
On 10/30/23 10:37, Patrick O'Neill wrote:
GCC recently changed its register allocator which causes this
testcase to fail.
This patch updates the regex to be more robust to change by accepting
any s register in the range of 1-9 for cm.push and cm.p
/issues/499#issuecomment-1784446631
The patch was applied to this baseline:
https://github.com/gcc-mirror/gcc/commit/c6929b085580cf00cbc52b0f5b0afe2b9caa2a22
and no new failures or resolved failures were found when running the
testsuite.
Tested-by: Patrick O'Neill
Thanks!
Patrick
gcc/Ch
register in the
range of 1-9 for cm.push and cm.popret insns.
Signed-off-by: Patrick O'Neill
---
Tested using glibc rv64gc on r14-4980-g2672c60917d.
---
gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
On 10/27/23 11:02, Jeff Law wrote:
On 10/27/23 11:56, Patrick O'Neill wrote:
GCC recently changed to emit __riscv_restore_5 which causes this
testcase to fail.
This patch updates the regex to be more robust to change by accepting
any number after __riscv_save_ and __riscv_restore_.
number
after __riscv_save_ and __riscv_restore_.
Signed-off-by: Patrick O'Neill
---
Tested using glibc rv64gc on r14-4980-g2672c60917d.
---
gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.t
On 8/25/23 15:36, Jeff Law wrote:
Spurred by Jivan's patch and a desire for cleaner testresults, I went
ahead and make the stack_save_restore tests independent of the precise
stack size by using a regexp.
Pushed to the trunk.
Jeff
Hi Jeff, A recent change that I'm still bisecting [1] cause
On 10/26/23 11:15, Robin Dapp wrote:
rv32gcv:
FAIL: gfortran.dg/intrinsic_pack_6.f90 -O2 execution test
FAIL: gfortran.dg/intrinsic_pack_6.f90 -O3 -g execution test
FAIL: gfortran.dg/matmul_3.f90 -O2 execution test
FAIL: gfortran.fortran-torture/execute/intrinsic_matmul.f90 execution,
inter -finline-functions
FAIL: gfortran.fortran-torture/execute/intrinsic_matmul.f90 execution,
-O3 -g
rv64gcv:
FAIL: gfortran.dg/matmul_6.f90 -O2 execution test
Tested-by: Patrick O'Neill
Patrick
On 10/26/23 01:13, Juzhe-Zhong wrote:
This patch addresses the redundant AVL/VL toggl
On 10/26/23 06:30, Jeff Law wrote:
On 10/25/23 18:13, Patrick O'Neill wrote:
On rv32gcv testcases like g++.target/riscv/rvv/base/bug-22.C fail with:
FAIL: g++.target/riscv/rvv/base/bug-22.C (test for excess errors)
Excess errors:
cc1plus: error: ABI requires '-march=rv32'
g++.target/riscv/rvv/rvv.exp: Add -mabi argument to CFLAGS.
Signed-off-by: Patrick O'Neill
---
Resolved failures:
FAIL: g++.target/riscv/rvv/base/bug-18.C (test for excess errors)
FAIL: g++.target/riscv/rvv/base/bug-19.C (test for excess errors)
FAIL: g++.target/riscv/rvv/base/bug-20.C (
The CI just picked it up:
https://github.com/ewlu/gcc-precommit-ci/issues/449#issue-1958483272
Since it doesn't apply to the CI's baseline hash it's only performing a
build.
I'll re-run it in the morning once the baseline has been updated.
In the meantime I started a full build+test run on my l
_TARGET=-Os -mcmodel=medany'
'CXXFLAGS_FOR_TARGET=-Os -mcmodel=medany'
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20231023 (experimental) (g70b66ac9bcb-dirty)
--------
juzh
del=medlow' 'CXXFLAGS_FOR_TARGET=-O2
-mcmodel=medlow'
On 10/23/23 15:50, 钟居哲 wrote:
I didn't reproduce it. How to enable RTL checking ?
juzhe.zh...@rivai.ai
*From:* Patrick O'Neill <mailto:patr...@rivo
.zh...@rivai.ai
*From:* Patrick O'Neill <mailto:patr...@rivosinc.com>
*Date:* 2023-10-24 02:30
*To:* Lehua Ding <mailto:lehua.d...@rivai.ai>
*CC:* kito.cheng <mailto:kito.ch...@gmail.com>; rdapp.gcc
<mailto:rdapp@gmail.com>; palmer <mailto:pal.
execution test
FAIL: gfortran.dg/host_assoc_function_7.f90 -O3
-fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer
-finline-functions execution test
FAIL: gfortran.dg/host_assoc_function_7.f90 -O3 -g execution test
Thanks for the quick revision Lehua!
Tested-by: Patrick O'Neill
FAIL: gfortran.dg/host_assoc_function_7.f90 -O3 -fomit-frame-pointer
-funroll-loops -fpeel-loops -ftracer -finline-functions execution test
FAIL: gfortran.dg/host_assoc_function_7.f90 -O3 -g execution test
Thanks for the quick revision Lehua!
Tested-by: Patrick O'Neill
Patrick
On 10/19/2
_run-1.exe
PASS: gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c
(test for excess errors)
spawn riscv64-unknown-elf-run ./cond_convert_float2int_run-1.exe
bbl loader
On 2023/10/18 4:25, Patrick O'Neill wrote:
Hi Lehua!
I ran the gcc testsuite on qemu before/after applying your
Hi Lehua!
I ran the gcc testsuite on qemu before/after applying your patches to
305034e3 rv32/64gcv [1].
Baseline
= Summary of gcc testsuite =
| # of unexpected case / # of unique
unexpected case
|
On 10/4/23 08:53, Jeff Law wrote:
On 10/3/23 16:26, Patrick O'Neill wrote:
I vaugely recall some discussion about backporting the Ztso mappings
along with the RVWMO mappings. Now that the RVWMO mappings have been
backported for 13.3, is there interest in also backporting the Ztso
map
Committed, thanks!
Patrick
On 10/5/23 17:51, Kito Cheng wrote:
LGTM
Patrick O'Neill 於 2023年10月6日 週五 07:46 寫道：
stdint.h can be replaced with stdint-gcc.h to resolve some missing
system headers in non-multilib installations.
Tested using glibc rv32gcv and rv64gcv on r14
.
* gcc.target/riscv/rvv/vsetvl/pr111255.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c: Ditto.
Signed-off-by: Patrick O'Neill
---
Changes from v1:
- Avoid changing riscv_vector.h
Failures looked like this:
In file included from
/riscv-gnu-toolchain/build/sysroot/usr/in
On 10/5/23 15:14, Jeff Law wrote:
On 10/4/23 16:55, Patrick O'Neill wrote:
Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to
perform a memcpy. We no longer expect memcpy for riscv_v targets.
gcc/testsuite/ChangeLog:
* gcc.dg/pr90263.c: Skip riscv_v ta
On 10/4/23 15:29, Jeff Law wrote:
On 10/4/23 16:21, Patrick O'Neill wrote:
On 10/4/23 15:14, Jeff Law wrote:
On 10/4/23 15:57, Patrick O'Neill wrote:
Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to
perform a memcpy. We no longer expect memcpy for riscv
Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to
perform a memcpy. We no longer expect memcpy for riscv_v targets.
gcc/testsuite/ChangeLog:
* gcc.dg/pr90263.c: Skip riscv_v targets.
* gcc.target/riscv/rvv/base/pr90263.c: New test.
Signed-off-by: Patrick
On 10/4/23 15:14, Jeff Law wrote:
On 10/4/23 15:57, Patrick O'Neill wrote:
Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to
perform a memcpy. We no longer expect memcpy for riscv_v targets.
gcc/testsuite/ChangeLog:
* gcc.dg/pr90263.c: xfail riscv_v target
Since r14-4358-g9464e72bcc9 riscv_v targets use vector instructions to
perform a memcpy. We no longer expect memcpy for riscv_v targets.
gcc/testsuite/ChangeLog:
* gcc.dg/pr90263.c: xfail riscv_v targets.
Signed-off-by: Patrick O'Neill
Co-authored-by: Joern Rennecke
---
gcc/test
On 10/4/23 12:19, Joern Rennecke wrote:
On Wed, 4 Oct 2023 at 18:38, Patrick O'Neill wrote:
Hi Joern,
I'm seeing new failures introduced by this patch
(9464e72bcc9123b619215af8cfef491772a3ebd9).
On rv64gcv:
FAIL: gcc.dg/pr90263.c scan-assembler memcpy
My testing didn't flag
Hi Joern,
I'm seeing new failures introduced by this patch
(9464e72bcc9123b619215af8cfef491772a3ebd9).
On rv64gcv:
FAIL: gcc.dg/pr90263.c scan-assembler memcpy
FAIL: gfortran.fortran-torture/execute/intrinsic_count.f90 execution,
-O2 -fomit-frame-pointer -finline-functions -funroll-loops
D
-psabi-doc/pull/391
2023-08-08 Patrick O'Neill
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as
dependent on 'a' extension.
* config/riscv/riscv-opts.h (MASK_ZTSO): New mask.
(TARGET_ZTSO): New target.
* config
On rv32 targets, this patch fixes ztso testcases errors like this:
cc1: error: ABI requires '-march=rv32'
2023-08-11 Patrick O'Neill
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add -mabi=lp64d
to dg-options.
* gcc.target/riscv
could have easily missed it.
Regardless, fixing the extraneous newline is easy :-)
gcc/
* config/riscv/sync-ztso.md (atomic_load_ztso): Avoid extraenous
newline.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/sync-ztso.md | 4 ++--
1 file changed, 2 insertions(+), 2 del
][committed] Remove spurious newline in ztso sequence
Patrick O'Neill (2):
RISC-V: Add Ztso atomic mappings
RISC-V: Specify -mabi for ztso testcases
gcc/common/config/riscv/riscv-common.cc | 6 +
gcc/config/riscv/riscv-opts.h | 4 +
gcc/config/riscv/ris
On 10/3/23 14:55, Jeff Law wrote:
On 10/3/23 14:19, Patrick O'Neill wrote:
Some characters are escaped which causes the testcase to fail. This
patch restores the original characters.
Tested for regressions using multilib rv32gcv-ilp32d, rv64gcv-lp64d.
gcc/testsuite/Chan
On 10/2/23 06:57, Kito Cheng wrote:
On Tue, Sep 26, 2023 at 10:59 AM Patrick O'Neill wrote:
stdint.h can be replaced with stdint-gcc.h to resolve some missing
system headers in non-multilib installations.
Tested using glibc rv32gcv and rv64gcv on r14-4258-gc9837443075.
gcc/Chan
.
Signed-off-by: Patrick O'Neill
---
gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90 | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
index 265e91
Committed. Thanks Juzhe!
I had to adjust the changelog's PR formatting to get the pre-commit
hooks to accept it.
Here's the committed patch:
From f446cf5d58568e406cc81f434a63b3045942e9a9 Mon Sep 17 00:00:00 2001
From: Patrick O'Neill
Date: Sat, 30 Sep 2023 15:50:11 -0700
Resolves a riscv*-*-* bootstrap failure due to a newly-turned-on assert.
2023-09-30 Jakub Jelinek
PR target/111649
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc
(vector_infos_manager::vector_infos_manager):
Replace safe_grow with safe_grow_cleared.
---
https://gcc.gnu.org/bu
Hi Jakub,
A follow-up commit of yours (9d249b7e31e) is causing bootstrap failures
for riscv*-*-* targets.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111649
Patrick
On 9/29/23 03:42, Jakub Jelinek wrote:
Hi!
As reported by Jonathan on IRC, my vec.h patch broke build with GCC 4.8.x
or 4.9.x
On 9/29/23 14:59, Jeff Law wrote:
On 9/29/23 15:37, Patrick O'Neill wrote:
Resolves this error on rv32gcv:
cc1: error: ABI requires '-march=rv32'
compiler exited with status 1
FAIL: gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c -O0 (test for
excess errors)
Tested for re
/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c: Specify -mabi=lp64d.
Signed-off-by: Patrick O'Neill
---
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wre
On 9/29/23 12:05, Jeff Law wrote:
On 9/12/23 12:54, Patrick O'Neill wrote:
This testcase causes lots of false-positives for machine description
files.
contrib/ChangeLog:
* check_GNU_style_lib.py: Skip machine description file bracket
linting.
OK. We probably need a compl
On 9/26/23 11:13, Andrew Pinski wrote:
On Tue, Sep 26, 2023 at 10:59 AM Patrick O'Neill wrote:
stdint.h can be replaced with stdint-gcc.h to resolve some missing
system headers in non-multilib installations.
Tested using glibc rv32gcv and rv64gcv on r14-4258-gc9837443075.
gcc/Chan
.
* gcc.target/riscv/rvv/vsetvl/pr111255.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c: Ditto.
Signed-off-by: Patrick O'Neill
---
Failures looked like this:
In file included from
/riscv-gnu-toolchain/build/sysroot/usr/include/features.h:515,
from
/riscv-gnu-tool
Hi Juzhe,
I'm seeing a few new regressions from this patch on glibc rv32gcv.
I filed a bugzilla for the ICE:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111546
Patrick
On 9/19/23 19:24, Juzhe-Zhong wrote:
This patch extends 'VWEXT' iterator so that we will support
integer extension/integer
On 9/21/23 09:14, Patrick O'Neill wrote:
On 9/21/23 03:20, Palmer Dabbelt wrote:
On Wed, 20 Sep 2023 10:47:23 PDT (-0700), Patrick O'Neill wrote:
...
[1]:
Executing on host:
/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
rinsic API test in your test CI?
Currently, we don't include all API test in the GCC testsuite since
it's too big.
juzhe.zh...@rivai.ai
*From:* Patrick O'Neill <mailto:patr...@rivosinc.com>
*
On 9/21/23 03:20, Palmer Dabbelt wrote:
On Wed, 20 Sep 2023 10:47:23 PDT (-0700), Patrick O'Neill wrote:
...
[1]:
Executing on host:
/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
-B/github/ewlu-runner-2/_work/riscv-gnu-tool
Committed. Thanks!
On 9/20/23 10:19, Kito Cheng wrote:
LGTM
Patrick O'Neill 於 2023年9月20日 週三 18:07 寫道：
Resolves some of the missing stubs failures:
fatal error: gnu/stubs-lp64d.h: No such file or directory
compilation terminated.
2023-09-20 Juzhe Zhong
gcc/test
ar failures for
testcases like
gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c that
#include .
On 9/19/23 18:12, Patrick O'Neill wrote:
I'll let it run overnight and see if this helps. Even before this patch,
I was seeing 233 stubs related failures for rv32gcv and 7 fo
Resolves some of the missing stubs failures:
fatal error: gnu/stubs-lp64d.h: No such file or directory
compilation terminated.
2023-09-20 Juzhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h: Remove unneeded math.h
import.
Tested-by: Patrick O'
ito Cheng <mailto:kito.ch...@gmail.com>
*Date:* 2023-09-20 08:52
*To:* 钟居哲 <mailto:juzhe.zh...@rivai.ai>
*CC:* Patrick O'Neill <mailto:patr...@rivosinc.com>; Robin Dapp
<mailto:rdapp@gmail.com>; gcc-patches
<mailto:gcc-patches@gcc.gnu.org>
Hi,
This patch highlights an issue Edwin and I have been having with the
testsuite where rv64 testcases are run when testing rv32gcv.
There's a large number of new failures in the rv32gcv testsuite from
this seemingly innocuous patch.
https://github.com/ewlu/riscv-gnu-toolchain/issues/166
(The
Committed, thanks!
The pre-commit hook didn't like the Authored-by format so I changed it
into:
2023-09-19 Juzhe Zhong
Patrick
From 0b9c51dc2fb58911b91889895d00437673d9f4cf Mon Sep 17 00:00:00 2001
From: Patrick O'Neill
Date: Tue, 19 Sep 2023 10:03:35 -0700
Subject: [PATCH] R
176
79 | ip = __mon_yday[__isleap(y)];
Tested on rv32gc glibc with --enable-checking=rtl.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_const_move): Eliminate
src_op_0 var to avoid rtl check error.
Authored-by: Juzhe Zhong
Tested-by: Patrick O'Neill
---
gcc/
Hi,
After this patch, there is now an ICE when bootstrapping with
--enable-checking=rtl on rv32gc.
More details:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111461
Thanks,
Patrick
On 8/29/23 07:40, Li, Pan2 via Gcc-patches wrote:
Committed, thanks Kito.
Pan
-Original Message-
From:
Committed - Thanks!
Patrick
On 9/15/23 13:06, Palmer Dabbelt wrote:
On Fri, 15 Sep 2023 09:37:48 PDT (-0700), Patrick O'Neill wrote:
On 9/15/23 01:49, Kito Cheng via Gcc-patches wrote:
I guess another solution is using reg_or_subregno instead of REGNO, but
that should not catch more
On 9/15/23 01:49, Kito Cheng via Gcc-patches wrote:
I guess another solution is using reg_or_subregno instead of REGNO, but
that should not catch more cases, and just more run-time check, so this
version is LGTM.
I tested an equivalent patch (without the comment changes).
This patch resolves th
This testcase causes lots of false-positives for machine description files.
contrib/ChangeLog:
* check_GNU_style_lib.py: Skip machine description file bracket linting.
Signed-off-by: Patrick O'Neill
---
contrib/check_GNU_style_lib.py | 3 +++
1 file changed, 3 insertions(+)
On 8/24/23 11:28, Palmer Dabbelt wrote:
Reviewed-by: Palmer Dabbelt
I think Joern is still looking into fixing up all these explicit ISA
strings in the tests, but I don't see any reason to block fixing
failing tests on that.
Thanks!
Committed
Patrick
-abi-7.c: ...here.
* gcc.target/riscv/vector-abi-8.c: Moved to...
* gcc.target/riscv/rvv/base/vector-abi-8.c: ...here.
* gcc.target/riscv/vector-abi-9.c: Moved to...
* gcc.target/riscv/rvv/base/vector-abi-9.c: ...here.
Signed-off-by: Patrick O'Neill
---
On 8/16/23 21:36, Jeff Law wrote:
On 8/16/23 19:17, Patrick O'Neill wrote:
This adds new regression tests to ensure half-register rotations are
correctly optimized into rori instructions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbb-rol-ror-08.c: New test.
* gcc.target/risc
: Patrick O'Neill
---
Trunk optimized these added testcases correctly.
GCC 13.2 and earlier do not optimize these cases correctly.
Expands on testcases added in:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;f=gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c;h=0ccf520d349a82dafca0deb3d307a1080e8
case.
Co-authored-by: Charlie Jenkins
Signed-off-by: Patrick O'Neill
---
Trunk optimized these added testcases correctly.
GCC 13.2 and earlier do not optimize these cases correctly.
Expands on testcases added in:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;f=gcc/testsuite/gcc.t
On 8/11/23 13:44, Jeff Law wrote:
On 8/11/23 13:15, Patrick O'Neill wrote:
On rv32 targets, this patch fixes ztso testcases errors like this:
cc1: error: ABI requires '-march=rv32'
2023-08-11 Patrick O'Neill
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo-table-z
On rv32 targets, this patch fixes ztso testcases errors like this:
cc1: error: ABI requires '-march=rv32'
2023-08-11 Patrick O'Neill
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add -mabi=lp64d
to dg-options.
* gcc.target/riscv
Committed - thanks!
On 8/8/23 14:54, Palmer Dabbelt wrote:
On Tue, 08 Aug 2023 14:52:14 PDT (-0700), Patrick O'Neill wrote:
The RISC-V Ztso extension currently has no effect on generated code.
With the additional ordering constraints guarenteed by Ztso, we can emit
more optimized a
On 7/31/23 22:04, Jeff Law wrote:
On 7/17/23 15:28, Patrick O'Neill wrote:
The RISC-V Ztso extension currently has no effect on generated code.
With the additional ordering constraints guarenteed by Ztso, we can emit
more optimized atomic mappings than the RVWMO mappings.
This PR defi
-psabi-doc/pull/391
2023-08-08 Patrick O'Neill
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as
dependent on 'a' extension.
* config/riscv/riscv-opts.h (MASK_ZTSO): New mask.
(TARGET_ZTSO): New target.
* config
GCC 13.2 released[2] so I merged the series now that the branch is unfrozen.
Thanks,
Patrick
[2] https://inbox.sourceware.org/gcc/ZMJeq%2FY5SN+7i8a+@tucnak/T/#u
On 7/25/23 11:01, Patrick O'Neill wrote:
Discussed during the weekly RISC-V GCC meeting[1] and pre-approved by
Jeff Law.
If
No worries! I'm glad it was an easy fix ;)
On 7/27/23 19:55, Demin Han wrote:
Sorry for not consider rv32 config.
The fix is OK. If convenient, please commit it.
On 2023/7/28 4:46, Patrick O'Neill wrote:
The newly added testcase fails on rv32 targets with this message:
FAIL: gcc.ta
Thanks!
Here's the comitted patch:
https://inbox.sourceware.org/gcc-patches/20230728163758.377962-1-patr...@rivosinc.com/T/#u
On 7/27/23 15:11, juzhe.zhong wrote:
LGTM.Thanks. You can go ahead commit it.
Replied Message
FromPatrick O'Neill <mailto:patr...@rivosinc.co
dg-options.
Signed-off-by: Patrick O'Neill
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
in
The newly added testcase fails on rv32 targets with this message:
FAIL: gcc.target/riscv/rvv/autovec/madd-split2-1.c -O3 -ftree-vectorize (test
for excess errors)
verbose log:
compiler exited with status 1
output is:
cc1: error: ABI requires '-march=rv32'
Something like this appears to fix the
This final patch fixes an error introduced by patch 9/12 in this series.
I'll backport alongside the other patches once the 13 branch is unfrozen :)
On 7/25/23 18:22, Kito Cheng wrote:
OK for backport :)
On Wed, Jul 26, 2023 at 2:11 AM Patrick O'Neill wrote:
From: Martin Liska
From: Martin Liska
Fixes:
gcc/config/riscv/sync.md:66:1: error: control reaches end of non-void function
[-Werror=return-type]
66 | [(set (attr "length") (const_int 4))])
| ^
PR target/109713
gcc/ChangeLog:
* config/riscv/sync.md: Add gcc_unreachable to a switch.
---
gcc
This change brings atomic loads in line with table A.6 of the ISA
manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md (atomic_load): Implement atomic
load mapping.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/sy
These tests cover basic cases to ensure the atomic mappings follow the
strengthened Table A.6 mappings that are compatible with Table A.7.
2023-04-27 Patrick O'Neill
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo-table-a-6-amo-add-1.c: New test.
* gcc.target/riscv/amo-ta
Atomic operations with the appropriate bits set already enfore release
semantics. Remove unnecessary release fences from atomic ops.
This change brings AMO ops in line with table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/ris
This patch sets the relevant .rl bits on amo operations.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand): Change behavior
of %A to include release bits.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/riscv.cc | 7 +
ordering of both given models.
This change brings LR/SC ops in line with table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_union_memmodels): Expose
riscv_union_memmodels function to sync.md.
* config/riscv/ris
This change brings atomic fences in line with table A.6 of the ISA
manual.
Relax mem_thread_fence according to the memmodel given.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md (mem_thread_fence_1): Change fence
depending on the given memory model.
S
This change makes atomic stores strictly stronger than table A.6 of the
ISA manual. This mapping makes the overall patchset compatible with
table A.7 as well.
2023-04-27 Patrick O'Neill
PR target/89835
gcc/ChangeLog:
* config/riscv/sync.md (atomic_store): Use simple
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
libgcc/ChangeLog:
* config/riscv/atomic.c: Change LR.aq/SC.rl pairs into
sequentially consistent LR.aqrl/SC.rl pairs.
Signed-off-by: Pa
This patch enforces SEQ_CST for atomic compare_exchange ops.
Replace Fence/LR.aq/SC.aq pairs with SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md (atomic_cas_value_strong): Change
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md: Change LR.aq/SC.rl pairs into
sequentially consistent LR.aqrl/SC.rl pairs.
Signed-off-by: Pa
Remove references to MEMMODEL_SYNC_* models by converting via
memmodel_base().
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/riscv.cc: Remove MEMMODEL_SYNC_* cases and
sanitize memmodel input with memmodel_base.
Signed-off-by: Patrick O'Neill
---
gcc/co
riscv: fix error: control reaches end of non-void function
Patrick O'Neill (11):
RISC-V: Eliminate SYNC memory models
RISC-V: Enforce Libatomic LR/SC SEQ_CST
RISC-V: Enforce subword atomic LR/SC SEQ_CST
RISC-V: Enforce atomic compare_exchange SEQ_CST
RISC-V: Add AMO releas
mappings.rst
[2] https://inbox.sourceware.org/gcc-patches/ZFV8pNAstwrF2qBb@andrea/T/#t
[3] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/391
gcc/ChangeLog:
2023-07-17 Patrick O'Neill
* common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as
depend
On 5/16/23 19:47, Palmer Dabbelt wrote:
On Tue, 16 May 2023 19:46:28 PDT (-0700), Vineet Gupta wrote:
On 5/16/23 19:21, Kito Cheng wrote:
Palmer:
For short-term, this should help your internal test:
https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1233
That only helps if using blee
On 5/15/23 21:32, Jeff Law wrote:
On 5/9/23 10:01, Patrick O'Neill wrote:
Ping.
OK for backporting. Sorry for the delay.
jeff
Committed.
Thanks,
Patrick
Ping.
On 5/3/23 10:19, Patrick O'Neill wrote:
RISC-V has no support for subword atomic operations; code currently
generates libatomic library calls.
This patch changes the default behavior to inline subword atomic calls
(using the same logic as the existing library call).
Behavior c
quot;).
https://github.com/preames/public-notes/blob/master/riscv-tso-mappings.rst
LLVM has implemented this same mapping (Ztso is still behind a
experimental flag in LLVM, so there is *not* a defined ABI for this yet).
https://reviews.llvm.org/D143076
2023-05-04 Patrick O'Neill
gcc/ChangeLo
-atomics command line flags.
gcc/libgcc/config/riscv/atomic.c has the same logic implemented in asm.
This will need to stay for backwards compatibility and the
-mno-inline-atomics flag.
2023-05-03 Patrick O'Neill
gcc/ChangeLog:
PR target/104338
* config/riscv/riscv-protos.h
:
On 5/2/23 14:34, Patrick O'Neill wrote:
> Is this OK for a backport to GCC-13 as well?
Let me sync with Richi & Jakub. They're the release managers and
this
doesn't fall under the usual rules for things that can be backported.
I would guess that most distros have th
Is this OK for a backport to GCC-13 as well?
(with the whitespace fixes/changelog revision squashed into it)
Patrick
On 4/26/23 10:01, Patrick O'Neill wrote:
Committed - I had to reformat the changelog so it would push and resolve a
trivial merge conflict in riscv.opt.
---
RISC-V h
heck-function-bodies was pre-approved by Jeff Law.
Committed.
Patrick
---
These tests cover basic cases to ensure the atomic mappings follow the
strengthened Table A.6 mappings that are compatible with Table A.7.
2023-04-27 Patrick O'Neill
gcc/testsuite/ChangeLog:
* gcc.target/
On 4/28/23 11:04, Jeff Law wrote:
On 4/27/23 10:23, Patrick O'Neill wrote:
This change brings atomic loads in line with table A.6 of the ISA
manual.
2023-04-27 Patrick O'Neill
gcc/ChangeLog:
* config/riscv/sync.md (atomic_load): Implement atomic
load mapping.
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