Hi Manasi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v5.1-rc3 next-20190403]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com
Hi Manasi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v5.1-rc3 next-20190403]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com
On Thu, Apr 04, 2019 at 08:32:06AM +0800, Zhenyu Wang wrote:
> On 2019.04.03 17:12:37 -0700, Rodrigo Vivi wrote:
> > On Tue, Apr 02, 2019 at 05:40:37PM +0800, Zhenyu Wang wrote:
> > >
> > > Hi,
> > >
> > > Here's gvt-fixes for 5.1-rc4 which includes misc fixes for
> > > vGPU display plane size
== Series Details ==
Series: drm/i915/dp: On link train failure on eDP, retry with max params first
URL : https://patchwork.freedesktop.org/series/58975/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK
On Wed, Apr 03, 2019 at 05:39:40PM -0700, Runyan, Arthur J wrote:
> I update the Bspec as general programming. SRD_CTL TP2 TP3 Select - "This
> bit impacts PSR2. Clear it before enabling PSR2 and do not set it while PSR2
> is enabled."
> I haven't seen the hardware bug report come through yet
On 2019.04.03 17:12:37 -0700, Rodrigo Vivi wrote:
> On Tue, Apr 02, 2019 at 05:40:37PM +0800, Zhenyu Wang wrote:
> >
> > Hi,
> >
> > Here's gvt-fixes for 5.1-rc4 which includes misc fixes for
> > vGPU display plane size calculation, shadow mm pin count,
> > error recovery path for workload
On 2019.04.03 17:12:37 -0700, Rodrigo Vivi wrote:
> On Tue, Apr 02, 2019 at 05:40:37PM +0800, Zhenyu Wang wrote:
> >
> > Hi,
> >
> > Here's gvt-fixes for 5.1-rc4 which includes misc fixes for
> > vGPU display plane size calculation, shadow mm pin count,
> > error recovery path for workload
I update the Bspec as general programming. SRD_CTL TP2 TP3 Select - "This bit
impacts PSR2. Clear it before enabling PSR2 and do not set it while PSR2 is
enabled."
I haven't seen the hardware bug report come through yet to establish the wa
number.
> -Original Message-
> From: Vivi,
Certain eDP panels fail to link train with optimized settings for
link rate and lane count and need the max link parameters to be used
for link training to pass.
So in on link training failure for eDP, retry the link training
with max link parameters first since this tends to fix link
failures on
On Wed, Apr 03, 2019 at 04:35:38PM -0700, José Roberto de Souza wrote:
> PSR is only supported in eDP transcoder and there is only one
> instance of it, so lets drop all of this code.
Is this sentence true? I mean, in the way it is written it
seems like HW doesn't actually support it...
Or should
On Wed, Apr 03, 2019 at 04:35:36PM -0700, José Roberto de Souza wrote:
> This interlaced restriction applies to all gens, not only to Haswell.
I believe this came from VLV times and I doubt we would be
impacted by it ever, but better to protect just in case:
Reviewed-by: Rodrigo Vivi
>
>
On Wed, Apr 03, 2019 at 04:35:35PM -0700, José Roberto de Souza wrote:
> Even when driver is reloaded and hits this scenario the PSR mutex
> should be initialized, otherwise reading PSR debugfs status will
> execute mutex_lock() over a mutex that was not initialized.
>
> Cc: Dhinakaran Pandiyan
On Wed, Apr 03, 2019 at 04:35:34PM -0700, José Roberto de Souza wrote:
> PSR support for VLV and CHV was dropped in commit ce3508fd2a77
> ("drm/i915/psr: Nuke PSR support for VLV and CHV") so no need to keep
> this registers around.
o.O
Reviewed-by: Rodrigo Vivi
>
> Cc: Dhinakaran Pandiyan
On Wed, Apr 03, 2019 at 04:35:33PM -0700, José Roberto de Souza wrote:
> Turn out it is not a DMC bug it is actually a HW one, so this
> workaround will be needed for current gens, lets update the comment
> and remove the FIXME.
Do we have a Wa #number for this? p[art of workaround page
or just
On Tue, Apr 02, 2019 at 05:40:37PM +0800, Zhenyu Wang wrote:
>
> Hi,
>
> Here's gvt-fixes for 5.1-rc4 which includes misc fixes for
> vGPU display plane size calculation, shadow mm pin count,
> error recovery path for workload create and one kerneldoc
> fix which I missed to include before.
== Series Details ==
Series: series starting with [1/7] drm/i915/psr: Update PSR2 SU corruption
workaround comment
URL : https://patchwork.freedesktop.org/series/58974/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5867 -> Patchwork_12677
== Series Details ==
Series: series starting with [1/7] drm/i915/psr: Update PSR2 SU corruption
workaround comment
URL : https://patchwork.freedesktop.org/series/58974/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/psr: Update PSR2 SU
== Series Details ==
Series: series starting with [1/7] drm/i915/psr: Update PSR2 SU corruption
workaround comment
URL : https://patchwork.freedesktop.org/series/58974/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a823afc06f70 drm/i915/psr: Update PSR2 SU corruption
This interlaced restriction applies to all gens, not only to Haswell.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c
PSR registers are a mess, some have the full address while others just
have the additional offset from psr_mmio_base.
psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET + 0x800 and
using it makes more difficult for people with an PSR register address
from BSpec to search the register name
Even when driver is reloaded and hits this scenario the PSR mutex
should be initialized, otherwise reading PSR debugfs status will
execute mutex_lock() over a mutex that was not initialized.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
Just moving it to reduce the tabs and avoid break code lines.
No behavior changes intended here.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_irq.c | 63 +++--
1 file changed, 36 insertions(+), 27 deletions(-)
diff --git
PSR support for VLV and CHV was dropped in commit ce3508fd2a77
("drm/i915/psr: Nuke PSR support for VLV and CHV") so no need to keep
this registers around.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 36
Turn out it is not a DMC bug it is actually a HW one, so this
workaround will be needed for current gens, lets update the comment
and remove the FIXME.
BSpec: 7723
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 6 ++
1
PSR is only supported in eDP transcoder and there is only one
instance of it, so lets drop all of this code.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 17 +---
drivers/gpu/drm/i915/intel_psr.c | 147
== Series Details ==
Series: drm/i915: Use lockdep_pin_lock() over the construction of the request
URL : https://patchwork.freedesktop.org/series/58932/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5860_full -> Patchwork_12672_full
The function __kms_addfb() and drmModeAddFB2WithModifiers() have a
similar code. Due to this similarity, this commit replace part of the
code inside __kms_addfb() by using drmModeAddFB2WithModifiers().
Signed-off-by: Rodrigo Siqueira
---
lib/ioctl_wrappers.c | 27 ++-
1
== Series Details ==
Series: drm/i915: Fix uninitialized mask in intel_device_info_subplatform_init
URL : https://patchwork.freedesktop.org/series/58921/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5860_full -> Patchwork_12670_full
== Series Details ==
Series: drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color
(rev3)
URL : https://patchwork.freedesktop.org/series/58912/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5860_full -> Patchwork_12669_full
On Wed, Apr 03, 2019 at 10:22:16PM +0300, Ville Syrjälä wrote:
> On Wed, Apr 03, 2019 at 12:07:35PM -0700, Manasi Navare wrote:
> > On Wed, Apr 03, 2019 at 09:55:56PM +0300, Ville Syrjälä wrote:
> > > On Wed, Apr 03, 2019 at 11:37:21AM -0700, Manasi Navare wrote:
> > > > On Wed, Apr 03, 2019 at
On Wed, Apr 03, 2019 at 10:25:33AM +0100, Tvrtko Ursulin wrote:
On 03/04/2019 09:15, Lucas De Marchi wrote:
On Tue, Apr 2, 2019 at 11:58 PM Tvrtko Ursulin
wrote:
On 03/04/2019 02:46, Lucas De Marchi wrote:
No reason to stick to u32 for platform mask if we can just use more bits
on 64 bit
On Wed, Apr 03, 2019 at 01:57:00PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
> >Sent: Tuesday, April 2, 2019 1:32 AM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Shankar, Uma ; Roper, Matthew D
> >
> >Subject:
On Wed, Apr 03, 2019 at 12:07:35PM -0700, Manasi Navare wrote:
> On Wed, Apr 03, 2019 at 09:55:56PM +0300, Ville Syrjälä wrote:
> > On Wed, Apr 03, 2019 at 11:37:21AM -0700, Manasi Navare wrote:
> > > On Wed, Apr 03, 2019 at 03:14:51PM +0300, Ville Syrjälä wrote:
> > > > On Tue, Apr 02, 2019 at
On Wed, Apr 03, 2019 at 09:55:56PM +0300, Ville Syrjälä wrote:
> On Wed, Apr 03, 2019 at 11:37:21AM -0700, Manasi Navare wrote:
> > On Wed, Apr 03, 2019 at 03:14:51PM +0300, Ville Syrjälä wrote:
> > > On Tue, Apr 02, 2019 at 02:52:34PM -0700, Manasi Navare wrote:
> > > > For certain eDP 1.4
== Series Details ==
Series: series starting with [1/2] drm/i915: add Makefile magic for testing
headers are self-contained
URL : https://patchwork.freedesktop.org/series/58963/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5865 -> Patchwork_12676
On Wed, Apr 03, 2019 at 11:37:21AM -0700, Manasi Navare wrote:
> On Wed, Apr 03, 2019 at 03:14:51PM +0300, Ville Syrjälä wrote:
> > On Tue, Apr 02, 2019 at 02:52:34PM -0700, Manasi Navare wrote:
> > > For certain eDP 1.4 panels, we need to use max lane count for the
> > > link training to succeed.
On Wed, Apr 03, 2019 at 03:14:51PM +0300, Ville Syrjälä wrote:
> On Tue, Apr 02, 2019 at 02:52:34PM -0700, Manasi Navare wrote:
> > For certain eDP 1.4 panels, we need to use max lane count for the
> > link training to succeed.
> >
> > This patch adds a EDID quirk for such eDP panels using
> >
== Series Details ==
Series: series starting with [1/2] drm/i915: add Makefile magic for testing
headers are self-contained
URL : https://patchwork.freedesktop.org/series/58963/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: add Makefile
== Series Details ==
Series: series starting with [1/2] drm/i915: add Makefile magic for testing
headers are self-contained
URL : https://patchwork.freedesktop.org/series/58963/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5f24918578ab drm/i915: add Makefile magic for
== Series Details ==
Series: drm/i915: add immutable zpos plane properties (rev2)
URL : https://patchwork.freedesktop.org/series/58761/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5865 -> Patchwork_12675
Summary
---
From: Jani Nikula
The below commits added dummy files to test that certain headers are
self-contained, i.e. compilable as standalone units:
39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
header")
3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
Start partitioning off the code that talks to the hardware (GT) from the
uapi layers and move the device facing code under gt/
One casualty is s/intel_ringbuffer.h/intel_engine.h/ with the plan to
subdivide that header and body further (and split out the submission
code from the ringbuffer and
On Wed, 2019-04-03 at 10:00 +0530, kiran.s.ku...@intel.com wrote:
> From: Kiran Kumar S
>
> As per the display workaround #1200, FBC needs wait for vblank before
> enabling and before disabling FBC.
>
> In some cases, depending on whether FBC was compressing in that
> frame,
> several control
== Series Details ==
Series: drm/i915: use unsigned long for platform_mask (rev2)
URL : https://patchwork.freedesktop.org/series/58895/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5858_full -> Patchwork_12663_full
== Series Details ==
Series: drm/i915: add Makefile magic for testing headers are self-contained
(rev4)
URL : https://patchwork.freedesktop.org/series/58938/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5863 -> Patchwork_12674
From: Ville Syrjälä
This adds basic immutable support for the zpos property. The zpos increases
from bottom to top: primary, sprites, cursor.
Signed-off-by: Ville Syrjälä
[cont...@emersion.fr: adapted for latest drm-tip]
Signed-off-by: Simon Ser
---
Changes in v2: set correct author and
On Thu, Mar 21, 2019 at 05:56:39PM +0200, Imre Deak wrote:
> On Thu, Mar 21, 2019 at 12:32:47AM +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: series starting with [CI,1/4] drm/i915: Force 2*96 MHz cdclk on
> > glk/cnl when audio power is enabled
> > URL :
== Series Details ==
Series: drm/i915: add Makefile magic for testing headers are self-contained
(rev4)
URL : https://patchwork.freedesktop.org/series/58938/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: add Makefile magic for testing
== Series Details ==
Series: drm/i915: add Makefile magic for testing headers are self-contained
(rev4)
URL : https://patchwork.freedesktop.org/series/58938/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5f226a4e31cd drm/i915: add Makefile magic for testing headers are
Hi Aditya,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20190403]
[cannot apply to v5.1-rc3]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url
>-Original Message-
>From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
>Sent: Tuesday, April 2, 2019 1:32 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma ; Roper, Matthew D
>
>Subject: [PATCH v2 0/7] drm/i915: Finish the GAMMA_LUT stuff
>
>From: Ville Syrjälä
>
>-Original Message-
>From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
>Sent: Tuesday, April 2, 2019 1:33 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma ; Roper, Matthew D
>
>Subject: [PATCH v2 7/7] drm/i915: Expose full 1024 LUT entries on ivb+
>
>From: Ville Syrjälä
On Wed, 03 Apr 2019, Chris Wilson wrote:
> Quoting Jani Nikula (2019-04-03 14:32:36)
>> The below commits added dummy files to test that certain headers are
>> self-contained, i.e. compilable as standalone units:
>>
>> 39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
>>
The below commits added dummy files to test that certain headers are
self-contained, i.e. compilable as standalone units:
39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
header")
3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
i915_request_types.h")
Quoting Jani Nikula (2019-04-03 14:32:36)
> The below commits added dummy files to test that certain headers are
> self-contained, i.e. compilable as standalone units:
>
> 39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
> header")
> 3a891a626794 ("drm/i915: Move
The below commits added dummy files to test that certain headers are
self-contained, i.e. compilable as standalone units:
39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
header")
3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
i915_request_types.h")
On Wed, Apr 03, 2019 at 03:14:51PM +0300, Ville Syrjälä wrote:
> On Tue, Apr 02, 2019 at 02:52:34PM -0700, Manasi Navare wrote:
> > For certain eDP 1.4 panels, we need to use max lane count for the
> > link training to succeed.
> >
> > This patch adds a EDID quirk for such eDP panels using
> >
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Wednesday, April 3, 2019 6:10 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Roper, Matthew D
>
>Subject: Re: [PATCH v2 2/7] drm/i915: Don't use split gamma when we don't have
>to
>
>On
On 03/04/2019 14:00, Chris Wilson wrote:
Quoting Chris Wilson (2019-03-29 15:49:12)
Use the engine->flags to store whether we want to kick the submission
tasklet on receipt of a breadcrumb interrupt, so that this decision can
be made by the submission backend and not dependent on a limited
Quoting Chris Wilson (2019-03-29 15:49:12)
> Use the engine->flags to store whether we want to kick the submission
> tasklet on receipt of a breadcrumb interrupt, so that this decision can
> be made by the submission backend and not dependent on a limited feature
> test within the interrupt
On Wed, Apr 03, 2019 at 12:23:06PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
> >Sent: Tuesday, April 2, 2019 1:32 AM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Shankar, Uma ; Roper, Matthew D
> >
> >Subject:
>-Original Message-
>From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
>Sent: Tuesday, April 2, 2019 1:32 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma ; Roper, Matthew D
>
>Subject: [PATCH v2 2/7] drm/i915: Don't use split gamma when we don't have to
>
>From: Ville
On Tue, Apr 02, 2019 at 02:52:34PM -0700, Manasi Navare wrote:
> For certain eDP 1.4 panels, we need to use max lane count for the
> link training to succeed.
>
> This patch adds a EDID quirk for such eDP panels using
> their vendor ID and product ID to force using max lane count in the driver.
== Series Details ==
Series: drm/i915: add Makefile magic for testing headers are self-contained
(rev2)
URL : https://patchwork.freedesktop.org/series/58938/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5862 -> Patchwork_12673
== Series Details ==
Series: series starting with [1/2] drm/edid: Add a EDID edp panel quirk for
forcing max lane count
URL : https://patchwork.freedesktop.org/series/58893/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5857_full -> Patchwork_12661_full
On Wed, 03 Apr 2019, Chris Wilson wrote:
> From: Jani Nikula
>
> The below commits added dummy files to test that certain headers are
> self-contained, i.e. compilable as standalone units:
>
> 39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
> header")
> 3a891a626794
== Series Details ==
Series: drm/i915: add Makefile magic for testing headers are self-contained
(rev2)
URL : https://patchwork.freedesktop.org/series/58938/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fc28b7a305b3 drm/i915: add Makefile magic for testing headers are
== Series Details ==
Series: drm/i915: add Makefile magic for testing headers are self-contained
(rev2)
URL : https://patchwork.freedesktop.org/series/58938/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: add Makefile magic for testing
On Tue, Apr 02, 2019 at 10:17:25PM -0700, Aditya Swarup wrote:
> From: Clinton Taylor
>
> v2: Fix commit msg to reflect why issue occurs(Jani)
> Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color.
>
> Changing settings from 10/12 bit deep color to 8 bit(& vice versa)
> doesn't work
Quoting Jani Nikula (2019-04-03 11:06:36)
> The below commits added dummy files to test that certain headers are
> self-contained, i.e. compilable as standalone units:
>
> 39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
> header")
> 3a891a626794 ("drm/i915: Move
From: Jani Nikula
The below commits added dummy files to test that certain headers are
self-contained, i.e. compilable as standalone units:
39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
header")
3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
Quoting Jani Nikula (2019-04-03 11:06:36)
> The below commits added dummy files to test that certain headers are
> self-contained, i.e. compilable as standalone units:
>
> 39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
> header")
> 3a891a626794 ("drm/i915: Move
Quoting Chris Wilson (2019-04-03 11:10:31)
> Quoting Jani Nikula (2019-04-03 11:06:36)
> > The below commits added dummy files to test that certain headers are
> > self-contained, i.e. compilable as standalone units:
> >
> > 39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its
Quoting Jani Nikula (2019-04-03 11:06:36)
> The below commits added dummy files to test that certain headers are
> self-contained, i.e. compilable as standalone units:
>
> 39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
> header")
> 3a891a626794 ("drm/i915: Move
The below commits added dummy files to test that certain headers are
self-contained, i.e. compilable as standalone units:
39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
header")
3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by
i915_request_types.h")
== Series Details ==
Series: drm/i915: Use lockdep_pin_lock() over the construction of the request
URL : https://patchwork.freedesktop.org/series/58932/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5860 -> Patchwork_12672
On 03/04/2019 09:15, Lucas De Marchi wrote:
On Tue, Apr 2, 2019 at 11:58 PM Tvrtko Ursulin
wrote:
On 03/04/2019 02:46, Lucas De Marchi wrote:
No reason to stick to u32 for platform mask if we can just use more bits
on 64 bit platforms.
$ size drivers/gpu/drm/i915/i915.ko*
text
Den 26.03.2019 19.23, skrev Daniel Vetter:
> On Tue, Mar 26, 2019 at 06:55:31PM +0100, Noralf Trønnes wrote:
>> The gamma_size variable has not been used since
>> commit 4abe35204af8 ("drm/kms/fb: use slow work mechanism for normal hotplug
>> also.")
>>
>> While in the area move a comment back
Den 27.03.2019 17.36, skrev Eric Anholt:
> Noralf Trønnes writes:
>
>> drm_dev_register() initializes internal clients like bootsplash as the
>> last thing it does, so all setup needs to be done at this point.
>>
>> Fix by calling vc4_kms_load() before registering.
>> Also check the error code
Quoting Patchwork (2019-04-03 09:49:14)
> == Series Details ==
>
> Series: series starting with [CI,1/2] drm/i915: add intel_uncore_init_early
> URL : https://patchwork.freedesktop.org/series/58891/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5856_full ->
On Wed, Apr 03, 2019 at 09:13:59AM +0100, Tvrtko Ursulin wrote:
> P.S. Also the assert about no junk in high bits did not fire in CI which
> would suggest stack slot was either zero or no more than three low bits
> sets. Strange luck.
GCC happens to initialize it to zero. It's also why GCC
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: add intel_uncore_init_early
URL : https://patchwork.freedesktop.org/series/58891/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5856_full -> Patchwork_12660_full
Quoting Simon Ser (2019-04-02 17:36:33)
> On Tuesday, April 2, 2019 3:35 PM, Joonas Lahtinen
> wrote:
> > Quoting Simon Ser (2019-03-30 00:19:25)
> >
> > > From: emersion cont...@emersion.fr
> >
> > Please fix your From: field.
>
> Gah.
>
> > > This adds basic immutable support for the zpos
== Series Details ==
Series: drm/i915: FBC needs vblank before enable / disable. (rev6)
URL : https://patchwork.freedesktop.org/series/58843/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5860 -> Patchwork_12671
Summary
During request construction, we take the timeline->mutex to ensure
exclusive access to the ringbuffer (for command emission) and the
timeline itself (for command ordering). The timeline->mutex should not
be dropped by callers until we release it in i915_request_add().
lockdep provides a pin/unpin
On Tue, Apr 2, 2019 at 11:58 PM Tvrtko Ursulin
wrote:
>
>
> On 03/04/2019 02:46, Lucas De Marchi wrote:
> > No reason to stick to u32 for platform mask if we can just use more bits
> > on 64 bit platforms.
> >
> > $ size drivers/gpu/drm/i915/i915.ko*
> > text data bss dec
On 03/04/2019 08:13, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-04-03 07:44:07)
From: Tvrtko Ursulin
Mask need to be initialized to zero since device id checks may not match.
Signed-off-by: Tvrtko Ursulin
Reported-by: Dan Carpenter
Fixes: 805446c8347c ("drm/i915: Introduce concept
== Series Details ==
Series: drm/i915: FBC needs vblank before enable / disable. (rev6)
URL : https://patchwork.freedesktop.org/series/58843/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7ee6b083d8fa drm/i915: FBC needs vblank before enable / disable.
-:53:
== Series Details ==
Series: drm/i915: Fix uninitialized mask in intel_device_info_subplatform_init
URL : https://patchwork.freedesktop.org/series/58921/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5860 -> Patchwork_12670
Quoting Chris Wilson (2019-04-03 08:54:41)
> Quoting Tvrtko Ursulin (2019-04-02 14:17:30)
> >
> > On 25/03/2019 09:03, Chris Wilson wrote:
> > > @@ -727,17 +695,19 @@ i915_request_alloc(struct intel_engine_cs *engine,
> > > struct i915_gem_context *ctx)
> > > if (ret)
> > >
Quoting Tvrtko Ursulin (2019-04-02 14:17:30)
>
> On 25/03/2019 09:03, Chris Wilson wrote:
> > @@ -727,17 +695,19 @@ i915_request_alloc(struct intel_engine_cs *engine,
> > struct i915_gem_context *ctx)
> > if (ret)
> > goto err_unwind;
> >
> > - ret =
== Series Details ==
Series: drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color
(rev3)
URL : https://patchwork.freedesktop.org/series/58912/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5860 -> Patchwork_12669
== Series Details ==
Series: linux-next: build failure after merge of the drm-misc tree (rev2)
URL : https://patchwork.freedesktop.org/series/58857/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5856_full -> Patchwork_12658_full
On 02/04/2019 09:35, Petri Latvala wrote:
> On Mon, Apr 01, 2019 at 04:39:24PM +0200, Guillaume Tucker wrote:
>> The MIPS architecture doesn't provide the hardware atomics that are
>> required for the "create-clear" sub-test such as
>> __sync_add_and_fetch(). As a simple and pragmatic solution,
From: Kiran Kumar S
As per the display workaround #1200, FBC needs wait for vblank before
enabling and before disabling FBC.
In some cases, depending on whether FBC was compressing in that frame,
several control signals in the compression engine also will fail to
properly recognize the final
Quoting Tvrtko Ursulin (2019-04-03 07:44:07)
> From: Tvrtko Ursulin
>
> Mask need to be initialized to zero since device id checks may not match.
>
> Signed-off-by: Tvrtko Ursulin
> Reported-by: Dan Carpenter
> Fixes: 805446c8347c ("drm/i915: Introduce concept of a sub-platform")
> Cc: Tvrtko
From: Kiran Kumar S
As per the display workaround #1200, FBC needs wait for vblank before
enabling and before disabling FBC.
In some cases, depending on whether FBC was compressing in that frame,
several control signals in the compression engine also will fail to
properly recognize the final
== Series Details ==
Series: drm/i915: FBC needs vblank before enable / disable. (rev4)
URL : https://patchwork.freedesktop.org/series/58843/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5860 -> Patchwork_12668
Summary
== Series Details ==
Series: drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color
(rev3)
URL : https://patchwork.freedesktop.org/series/58912/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
464216adb294 drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit
Hello Tvrtko Ursulin,
The patch 805446c8347c: "drm/i915: Introduce concept of a
sub-platform" from Mar 27, 2019, leads to the following static
checker warning:
drivers/gpu/drm/i915/intel_device_info.c:807
intel_device_info_subplatform_init()
error: uninitialized symbol 'mask'.
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