On 2017-07-10 19:40, Sricharan R wrote:
Hi,
On 7/4/2017 12:19 PM, Archit Taneja wrote:
On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
The BAM has multiple flags to control the transfer. This patch
adds flags parameter in register and data transfer functions and
modifies all these function call
On Sun 16-07-17 15:28:27, Zhaoyang Huang wrote:
> It is no need to find the very beginning of the area within
> alloc_vmap_area, which can be done by judging each node during the process
Please describe _why_ the patch is needed. I suspect this is an
optimization but for which workloads it matters
Hi Vitaly,
[auto build test ERROR on linus/master]
[also build test ERROR on v4.13-rc1 next-20170717]
[cannot apply to tip/x86/core]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Vitaly
On 17 July 2017 at 08:01, Tony Lindgren wrote:
> * Faiz Abbas [170714 05:48]:
>> This patch series removes some code in omap_hsmmc.c
>> and hsmmc.c and members from hsmmc.h and
>> hsmmc-omap.h which are not used anymore post
>> conversion to device-tree.
>
> Hey that's nice! That gets us a bit cl
Hi all,
As usual, the executive friendly graph is at
http://neuling.org/linux-next-size.html :-)
(No merge commits counted, next-20170704 was the first linux-next after
the merge window opened.)
Commits in v4.13-rc1 (relative to v4.12): 11258
Commits in next-20170704:
On 2017-07-04 12:24, Archit Taneja wrote:
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
1. NAND_READ_LOCATION: provides the offset in page for
reading in BAM DMA mode
2. NAND_ERASED_CW_DETECT_CFG: contains the status for erased
code words
3. NAND_BUFFER_STATUS: contains the status for E
Keep supporting proprietary "xlnx,phy-type" attribute and add support for
MII connectivity to the PHY.
Reviewed-by: Andrew Lunn
Signed-off-by: Alvaro Gamez Machado
---
Changes from v2:
* Replaced u32 phy_mode -> phy_interface_t phy_mode
* Fix bug we introduced PHY_INTERFACE_MODE_RGMII ->
P
On Mon, 17 Jul 2017, Liang, Kan wrote:
> There are three proposed patches so far.
> Patch 1: The patch as above which speed up the hrtimer.
> Patch 2: Thomas's first proposal.
> https://patchwork.kernel.org/patch/9803033/
> https://patchwork.kernel.org/patch/9805903/
> Patch 3: my original proposal
Hi Arvind,
[auto build test ERROR on staging/staging-testing]
[also build test ERROR on v4.13-rc1 next-20170717]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Arvind-Yadav/constify-lustre
On 2017-07-04 15:10, Archit Taneja wrote:
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
1. The BAM mode requires few registers configuration before each
NAND page read and codeword read which is different from ADM
so add the helper functions which will be called in BAM mode
only.
2.
* Ulf Hansson [170717 00:09]:
> On 17 July 2017 at 08:01, Tony Lindgren wrote:
> > * Faiz Abbas [170714 05:48]:
> >> This patch series removes some code in omap_hsmmc.c
> >> and hsmmc.c and members from hsmmc.h and
> >> hsmmc-omap.h which are not used anymore post
> >> conversion to device-tree.
On Mon, 17 Jul 2017 11:41:01 +0530
Abhishek Sahu wrote:
> >> > +
> >> > +nand@79b {
> >
> > nand-controller@ {
> >
> > BTW, glad to see another driver moving to the new DT representation
> > :-).
> >
> >> > +compatible = "qcom,qpic-nandc-v1.4.0";
> >> > +reg = <0x7
On 2017-07-04 15:14, Archit Taneja wrote:
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
1. Add the function for command descriptor preparation which
will be used only by BAM DMA and it will form the DMA descriptors
containing command elements.
2. Add the data descriptor preparation funct
From: Zhaoyang Huang
It is no need to find the very beginning of the area within
alloc_vmap_area, which can be done by judging each node during the process
For current approach, the worst case is that the starting node which be found
for searching the 'vmap_area_list' is close to the 'vstart', w
Hi Krzysztof,
On Mon, Jul 17, 2017 at 7:49 AM, Krzysztof Kozlowski wrote:
> Remove options which do not exist anymore:
> - DRM_RCAR_HDMI was merged to generic DRM bridge and is obsolete since
>commit 5c602531feb3 ("drm: rcar-du: Replace manual bridge
>implementation with DRM bridge");
Hi Krzysztof,
On Mon, Jul 17, 2017 at 7:49 AM, Krzysztof Kozlowski wrote:
> Remove options which do not exist anymore:
> - DRM_RCAR_HDMI was merged to generic DRM bridge and is obsolete since
>commit 5c602531feb3 ("drm: rcar-du: Replace manual bridge
>implementation with DRM bridge");
>
On 2017-07-04 15:25, Archit Taneja wrote:
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
The current driver defines the register offset with preprocessor
macro which is defined crossponding to NAND controller version
1.4.0. This patch changes these macro with enumeration. It also
adds mapping arra
Hi Stephen,
On 07/14/2017 08:52 PM, kbuild test robot wrote:
> Hi Gabriel,
>
> [auto build test ERROR on clk/clk-next]
> [also build test ERROR on v4.12 next-20170714]
> [if your patch is applied to the wrong git tree, please drop us a note to
> help improve the system]
>
> url:
> https://gi
On 2017-07-04 15:27, Archit Taneja wrote:
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
The current QCOM NAND driver only supports version 1.4.0
QCOM QPIC NAND controller. This patch adds the support for
version 1.5.0 which contains some of the registers at
different offsets. The driver data cont
On 17-07-17, 14:16, Sean Wang wrote:
> Hi, Viresh
>
> I missed to add Acks from Rob for patch 2 and 3 since we sent out almost
> at the same time. Do I need to resend again for this or the series is
> okay for you?
Looks like you missed including Rafael for this series (He is the one
who applies
On 2017-07-10 19:48, Sricharan R wrote:
On 6/29/2017 12:46 PM, Abhishek Sahu wrote:
1. Add the function for command descriptor preparation which
will be used only by BAM DMA and it will form the DMA descriptors
containing command elements.
2. Add the data descriptor preparation function w
From: Benson Leung
This is the driver for the USB Type C cable detection mechanism
built into the ChromeOS Embedded Controller on systems that
have USB Type-C ports.
At present, this allows for the presence of display out, but in
future, it may also be used to notify host and device type cables
From: Benson Leung
This patch add documentation for binding of USB Type C cable detection
mechanism is using EXTCON subsystem. The device can detect the presence
of display out but it may also detect other external accessories when
external accessories is attached or detached.
Signed-off-by: Ben
On Fri, Jul 14, 2017 at 10:22:49AM -0700, Andi Kleen wrote:
> Jiri Olsa writes:
> >
> > Setting the reset field to 0 for freq events.
>
> Looks good to me.
>
> Reviewed-by: Andi Kleen
>
> BTW I suspect there's a related bug that
>
> perf record -e '{cycles:pp,branches}:S' ..
>
> would enable
On Fri, 2017-07-14 at 18:54 +0200, Alexander Potapenko wrote:
> KMSAN reported use of uninitialized memory in skb_set_hash_from_sk(),
> which originated from the TCP request socket created in
> cookie_v6_check():
> ==
>
> Signed-off
Sorry for noise. Please ignore this. This change should not be separate.
~arvind
On Monday 17 July 2017 11:19 AM, Arvind Yadav wrote:
attribute_groups are not supposed to change at runtime. All functions
working with attribute_groups provided by work
with const attribute_group. So mark the non
Sorry for noise. Please ignore this.
~arvind
On Monday 17 July 2017 11:18 AM, Arvind Yadav wrote:
attribute_groups are not supposed to change at runtime. All functions
working with attribute_groups provided by work
with const attribute_group. So mark the non-const structs as const.
Signed-of
Sorry for noise. Please ignore this.
~arvind
On Monday 17 July 2017 11:18 AM, Arvind Yadav wrote:
attribute_groups are not supposed to change at runtime. All functions
working with attribute_groups provided by work
with const attribute_group. So mark the non-const structs as const.
Signed-of
Sorry for noise. Please ignore this.
~arvind
On Monday 17 July 2017 11:18 AM, Arvind Yadav wrote:
attribute_groups are not supposed to change at runtime. All functions
working with attribute_groups provided by work
with const attribute_group. So mark the non-const structs as const.
Signed-of
Sorry for noise. Please ignore this. It's having build error. Again, I
will push all changes.
~arvind
On Monday 17 July 2017 11:18 AM, Arvind Yadav wrote:
attribute_groups are not supposed to change at runtime. All functions
working with attribute_groups provided by work
with const attribute
Sorry for noise. Please ignore this. I will fix this error and push again.
~arvind
On Monday 17 July 2017 12:45 PM, kbuild test robot wrote:
Hi Arvind,
[auto build test ERROR on staging/staging-testing]
[also build test ERROR on v4.13-rc1 next-20170717]
[if your patch is applied to the wrong
On Thu, 13 Jul 2017, Moritz Fischer wrote:
> From: Moritz Fischer
>
> Add support for the Maxim/Dallas DS1374 RTC/WDT with trickle charger.
> The device can either be configured as simple RTC, as simple RTC with
> Alarm (IRQ) as well as simple RTC with watchdog timer.
>
> Break up the old monol
On Mon, 2017-07-17 at 00:39 -0700, Eric Dumazet wrote:
> On Fri, 2017-07-14 at 18:54 +0200, Alexander Potapenko wrote:
> > KMSAN reported use of uninitialized memory in skb_set_hash_from_sk(),
> > which originated from the TCP request socket created in
> > cookie_v6_check():
>
> > ===
On Thu, 13 Jul 2017, Michal Simek wrote:
> MTF_CORE should be enabled when driver is enabled.
"MFD_CORE"
You also need more information here. Why is it required? What
happens if it's not specified? Etc.
> Signed-off-by: Michal Simek
> ---
>
> drivers/mfd/Kconfig | 1 +
> 1 file changed, 1
On 17.7.2017 09:59, Lee Jones wrote:
> On Thu, 13 Jul 2017, Michal Simek wrote:
>
>> MTF_CORE should be enabled when driver is enabled.
>
> "MFD_CORE"
>
> You also need more information here. Why is it required? What
> happens if it's not specified? Etc.
There is compilation warning. Fair en
On 10/07/17 10:01, Neil Armstrong wrote:
> The Amlogic SoC embeds a standalone CEC controller, this patch adds a driver
> for such controller.
> The controller does not need HPD to be active, and could support up to max
> 5 logical addresses, but only 1 is handled since the Suspend firmware can
> m
On Fri, Jul 14, 2017 at 03:35:46PM +0200, Linus Walleij wrote:
> On Wed, Jul 12, 2017 at 5:55 PM, Johan Hovold wrote:
>
> > This reverts commit 99b04f4c4051 ("ASoC: add Component level
> > pcm_new/pcm_free"), which started calling the pcm_new callback for every
> > component in a *card* when crea
On 16-07-17, 01:04, Joel Fernandes wrote:
> Currently the iowait_boost feature in schedutil makes the frequency go to max
> on iowait wakeups. This feature was added to handle a case that Peter
> described where the throughput of operations involving continuous I/O requests
> [1] is reduced due to
On Thu, 13 Jul 2017 11:54:38 +0800, Eddie Huang wrote:
> On Thu, 2017-07-13 at 08:46 +0530, Viresh Kumar wrote:
> > I am fine with both. Maybe don't resend for just that, mediatek
> > doesn't sound any bad.
>
> I am also fine with both. I think most people won't confuse about mtk
> and mediatek.
On Fri, Jul 14, 2017 at 03:36:57PM +0200, Linus Walleij wrote:
> On Wed, Jul 12, 2017 at 5:55 PM, Johan Hovold wrote:
>
> > This reverts commit f1013cdeeeb9 ("ASoC: ux500: drop platform DAI
> > assignments"), which seems to have been based on a misunderstanding and
> > prevents the platform drive
On Mon, Jul 17, 2017 at 08:06:40AM +0200, Michal Hocko wrote:
> On Fri 14-07-17 15:18:23, Mel Gorman wrote:
> > Fairly sure that's not what you meant.
> >
> >
> > > pg_data_t *node = NODE_DATA(node_order[i]);
> > >
> > > - zoneref_idx = build_zonelists_node(node, zonelist, zon
On Mon, 10 Jul 2017 22:23:08 +0800, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> MT2701/MT7623 is a 32-bit ARMv7 based quad-core (4 * Cortex-A7) with
> single cluster and this hardware is also compatible with the existing
> driver through enabling CPU frequency feature with operating-point
On Mon, Jul 17, 2017 at 07:06:38PM +0800, Jin Yao wrote:
SNIP
> +#define X86_BR_TYPE_MAP_MAX 16
> +
> +static int
> +common_branch_type(int type)
> +{
> + int i;
> + const int branch_map[X86_BR_TYPE_MAP_MAX] = {
> + PERF_BR_CALL, /* X86_BR_CALL */
> + PE
This series patches supported the mail in devicetree and used the
thermal IPA by default.
Verified with kernel is based on Linus's master branch and Heiko's
v4.14-armsoc-tmp/dts64 branch. ( The Linux version 4.12.0 for now).
The most rockchip SoCs will be supported with IPA mode for thermal
in la
This patch adds the MALI's power-model to set the IPA model to be used
for power management.
Signed-off-by: Caesar Wang
---
Changes in v2: None
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 12
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/
As RK3399 had used the Power allocator thermal governor by default,
enabled this to manage thermals by dynamically allocating and limiting
power to devices.
Also, this patch supported the dynamic-power-coefficient/sustainable_power
and GPU's power model for needed parameters with thermal IPA.
The
This patch enables the gpu and adds the mali-supply power for RK3399-GRU
devices.
Signed-off-by: Caesar Wang
---
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
b/arch/arm64/
> Am 17.07.2017 um 00:08 schrieb Mauro Carvalho Chehab
> :
>
> [1] There's an unrelated bug with the Kernel's sphinx extension
> kimage: when parsing GraphViz graphs, it uses "-Tpdf" argument,
> in order to generate a PDF image. That doesn't work on some
> distros, as GraphViz doesn't support PD
Add Mali GPU device tree node for the RK3399 SoCs, with devfreq
opp table.
RK3399 and RK3399-OP1 SoCs have a different recommendation table with
gpu opp. Also, the ARM's mali driver found on
https://developer.arm.com/products/software/mali-drivers/midgard-kernel.
Signed-off-by: Caesar Wang
---
On Fri, Jul 14, 2017 at 05:59:06AM -0500, Eric W. Biederman wrote:
> in which cases the oddities will happen let alone test them. Plus at
> least for ia64 and alpha those architectures don't appear to be
> receiving updates for new syscalls, and no new hardware is being built
> so I don't know how
RK3399's GPU uses the quad-core Mali-T860, which is the new generation of
high-end graphics processors from ARM.
This patch added "rockchip,rk3399-mali" for dt-bindings, in order to
support IPA of gpu thermal in later.
Signed-off-by: Caesar Wang
---
Changes in v2: None
Documentation/devicetre
On Mon 17-07-17 09:07:23, Mel Gorman wrote:
> On Mon, Jul 17, 2017 at 08:06:40AM +0200, Michal Hocko wrote:
> > On Fri 14-07-17 15:18:23, Mel Gorman wrote:
> > > Fairly sure that's not what you meant.
> > >
> > >
> > > > pg_data_t *node = NODE_DATA(node_order[i]);
> > > >
> > >
On Mon, Jul 17, 2017 at 07:06:36PM +0800, Jin Yao wrote:
> v9:
> ---
>It only changes the patch "perf/x86/intel: Record branch type".
>Peter suggests to use __ffs() to find first bit.
>Yes, with this change, the code is simpler and clearer.
>
>No other functional changes.
I think
Generally looks like I imagined, but there are a few nits and some
things that I'd like to do differently. Comments inline. Thanks!
On 2017-07-14 23:40, Stephen Boyd wrote:
> Sometimes drivers only use muxes under certain scenarios. For
> example, the chipidea usb controller may be connected to a
On Mon, Jul 03, 2017 at 04:09:33PM +0530, Arvind Yadav wrote:
> attribute_groups are not supposed to change at runtime. All functions
> working with attribute_groups provided by work with const
> attribute_group. So mark the non-const structs as const.
>
> File size before:
>text dat
>From b798b9b631e237d285aa8699da00bfb8ced33bea Mon Sep 17 00:00:00 2001
From: Akira Yokosawa
Date: Mon, 17 Jul 2017 16:25:33 +0900
Subject: [PATCH] documentation: Fix two-CPU control-dependency example
In commit 5646f7acc95f ("memory-barriers: Fix control-ordering
no-transitivity example"), the o
This patch series add hardware CRC32 ("Ethernet") calculation support
for STMicroelectronics STM32F429.
Polynomial and key setting are not supported, key is fixed as 0x4C11DB7
and poly is 0x.
Module is tested on STM32F429-disco board with crypto testmgr using
cases within the key 0xFF
Add device tree binding for STM32F4.
Signed-off-by: Cosar Dindar
---
Documentation/devicetree/bindings/crypto/st,stm32-crc.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
b/Documentation/devicetree/bindings/cry
This patch adds CRC (CRC32 Crypto) support for STM32F4 series.
As an hardware limitation polynomial and key setting are not supported.
They are fixed as 0x4C11DB7 (poly) and 0x (key).
CRC32C Castagnoli algorithm is not used.
Signed-off-by: Cosar Dindar
Reviewed-by: Fabien Dessenne
---
On 7/17/2017 4:11 PM, Jiri Olsa wrote:
On Mon, Jul 17, 2017 at 07:06:38PM +0800, Jin Yao wrote:
SNIP
+#define X86_BR_TYPE_MAP_MAX16
+
+static int
+common_branch_type(int type)
+{
+ int i;
+ const int branch_map[X86_BR_TYPE_MAP_MAX] = {
+ PERF_BR_CALL,
On Mon 17-07-17 15:27:31, Zhaoyang Huang wrote:
> From: Zhaoyang Huang
>
> It is no need to find the very beginning of the area within
> alloc_vmap_area, which can be done by judging each node during the process
>
> For current approach, the worst case is that the starting node which be found
>
On Tue, Jul 04, 2017 at 04:44:40PM -0500, Gustavo A. R. Silva wrote:
> Remove unnecessary static on local variable _type_.
> Such variable is initialized before being used,
> on every execution path throughout the function.
> The static has no benefit and, removing it reduces
> the code size.
>
>
On 15-07-17, 21:40, Julia Lawall wrote:
> for_each_compatible_node performs an of_node_get on each iteration, so a
> return from the loop requires an of_node_put.
>
> The semantic patch that fixes this problem is as follows
> (http://coccinelle.lip6.fr):
>
> //
> @@
> local idexpression n;
> exp
On Fri, Jul 14, 2017 at 11:09:07AM +0800, Chen-Yu Tsai wrote:
> On Thu, Jul 13, 2017 at 10:12 PM, Maxime Ripard
> wrote:
> > The depends on relationship is obvious, and using an if statement will
> > propagate it to every option without the need for each and every one of
> > them to define it.
> >
On 07/17/2017 04:07 PM, Zhaoyang Huang wrote:
> It is no need to find the very beginning of the area within
> alloc_vmap_area, which can be done by judging each node during the process
>
> For current approach, the worst case is that the starting node which be found
> for searching the 'vmap_area_
On Fri, Jul 14, 2017 at 11:15:18AM +0800, Chen-Yu Tsai wrote:
> On Thu, Jul 13, 2017 at 10:12 PM, Maxime Ripard
> wrote:
> > The atomic_check callback is optional, and we don't implement anything in
> > some parts of our drivers. Let's remove it.
> >
> > Signed-off-by: Maxime Ripard
>
> Reviewed
On 2017-07-17 12:52, Boris Brezillon wrote:
On Mon, 17 Jul 2017 11:41:01 +0530
Abhishek Sahu wrote:
>> > +
>> > +nand@79b {
>
> nand-controller@ {
>
> BTW, glad to see another driver moving to the new DT representation
> :-).
>
>> > + compatible = "qcom,qpic-nandc-v1.4.0";
>> > + reg =
On Fri, Jul 14, 2017 at 05:49:23PM +0300, Priit Laes wrote:
> SATA clock on sun4i/sun7i is of type (parent) / M / 6 where
> 6 is fixed post-divider.
>
> Signed-off-by: Priit Laes
> ---
> drivers/clk/sunxi-ng/ccu_div.c | 15 +--
> drivers/clk/sunxi-ng/ccu_div.h | 3 ++-
> 2 files cha
Hi Enric,
When I tried to apply this patch, error happened as following:
(based on v4.13-rc1)
Applying: extcon: cros-ec: Add extcon-cros-ec driver to support display out.
error: patch failed: include/linux/mfd/cros_ec_commands.h:285
error: include/linux/mfd/cros_ec_commands.h: patch does not appl
Hi,
On Fri, Jul 14, 2017 at 05:49:24PM +0300, Priit Laes wrote:
> Introduce a clock controller driver for sun4i A10 and sun7i A20
> series SoCs.
>
> Signed-off-by: Priit Laes
> ---
> drivers/clk/sunxi-ng/Kconfig | 13 +-
> drivers/clk/sunxi-ng/Makefile |1 +-
> dr
On Sun 16-07-17 19:59:51, Tetsuo Handa wrote:
> Since the whole memory reclaim path has never been designed to handle the
> scheduling priority inversions, those locations which are assuming that
> execution of some code path shall eventually complete without using
> synchronization mechanisms can
On Fri, Jul 07, 2017 at 11:50:14PM +0100, Lee Jones wrote:
> On Fri, 07 Jul 2017, Linus Torvalds wrote:
>
> > On Fri, Jul 7, 2017 at 2:50 AM, Lee Jones wrote:
> > >
> > > include/linux/mfd/madera/registers.h | 8832
> > >
> >
> > So I've pulled everything but
On Mon, Jul 17, 2017 at 10:19:42AM +0200, Michal Hocko wrote:
> On Mon 17-07-17 09:07:23, Mel Gorman wrote:
> > On Mon, Jul 17, 2017 at 08:06:40AM +0200, Michal Hocko wrote:
> > > On Fri 14-07-17 15:18:23, Mel Gorman wrote:
> > > > Fairly sure that's not what you meant.
> > > >
> > > >
> > > > >
From: Arnd Bergmann
Without PM support, gcc warns about two unused functions:
platform/qcom/venus/core.c:146:13: error: 'venus_clks_disable' defined but not
used [-Werror=unused-function]
platform/qcom/venus/core.c:126:12: error: 'venus_clks_enable' defined but not
used [-Werror=unused-functio
In venus_boot(), we pass a pointer to a phys_addr_t
into dmam_alloc_coherent, which the compiler warns about:
platform/qcom/venus/firmware.c: In function 'venus_boot':
platform/qcom/venus/firmware.c:63:49: error: passing argument 3 of
'dmam_alloc_coherent' from incompatible pointer type
[-Werror
The way how default DMA pool is exposed has changed and now we need to
use dedicated interface to work with it. This patch makes alloc/release
operations to use such interface. Since default DMA pool is not
handled by generic code anymore we have to implement our own mmap
operation.
Signed-off-by:
Christoph noticed [1] that default DMA pool in current form overload
the DMA coherent infrastructure. In reply, Robin suggested to split
the per-device vs. global pool interfaces, so allocation/release from
default DMA pool is driven by dma ops implementation.
This patch implements Robin's idea an
Hi,
This is follow-up for Christoph complain of overloading the current
dma coherent infrastructure with the global pool. To address that I
implemented Robin's idea of the new interface to the global pool and
wire up it with (only existent user) ARM NOMMU. Since I have not
heard from Vitaly and/o
From: Rob Clark
Not entirely sure what triggers it, but with venus build as kernel
module and in initrd, we hit this crash:
Unable to handle kernel paging request at virtual address 80003c039000
pgd = 0a14f000
[80003c039000] *pgd=bd9f7003, *pud=bd9f6003,
*p
From: Arnd Bergmann
If QCOM_MDT_LOADER is enabled, but ARCH_QCOM is not, we run into
a build error:
ERROR: "qcom_mdt_load" [drivers/media/platform/qcom/venus/venus-core.ko]
undefined!
ERROR: "qcom_mdt_get_size" [drivers/media/platform/qcom/venus/venus-core.ko]
undefined!
This changes the 'sel
Hi,
Here is a collection of fixes for the issues found so far. The
patches 1/4, 3/4 and 4/4 has been already sent to the linux-media.
2/4 is a reworked version of [1], which has been sent
from Arnd, but the change was not correct, so please review it.
Arnd Bergmann (2):
venus: mark PM functions
Hi Mark,
On Thu, Jul 13, 2017 at 05:01:42PM +0100, Mark Brown wrote:
> On Thu, Jul 13, 2017 at 04:12:56PM +0200, Maxime Ripard wrote:
>
> > This might be problematic if the clock to enable is stored in another node.
> > Let's add a function that allows to attach a clock that has already been
> >
Hi,
2017-07-17 10:54 GMT+02:00 Chanwoo Choi :
> Hi Enric,
>
> When I tried to apply this patch, error happened as following:
> (based on v4.13-rc1)
>
> Applying: extcon: cros-ec: Add extcon-cros-ec driver to support display out.
> error: patch failed: include/linux/mfd/cros_ec_commands.h:285
> err
Hi,
On 2017년 07월 17일 17:54, Chanwoo Choi wrote:
> Hi Enric,
>
> When I tried to apply this patch, error happened as following:
> (based on v4.13-rc1)
>
> Applying: extcon: cros-ec: Add extcon-cros-ec driver to support display out.
> error: patch failed: include/linux/mfd/cros_ec_commands.h:285
>
On Fri, Jul 14, 2017 at 12:40:19PM +0800, Chen-Yu Tsai wrote:
> On Thu, Jul 13, 2017 at 10:13 PM, Maxime Ripard
> wrote:
> > The Bananapi M2-Magic is a board with an A33, a USB host and USB OTG
> > connectors, and 8GB eMMC, an AP6212 WiFi/Bluetooth chip and connectors for
> > DSI, CSI and GPIOs.
>
On 07/17/2017 04:45 PM, zijun_hu wrote:
> On 07/17/2017 04:07 PM, Zhaoyang Huang wrote:
>> It is no need to find the very beginning of the area within
>> alloc_vmap_area, which can be done by judging each node during the process
>>
>> For current approach, the worst case is that the starting node w
On Fri 14-07-17 22:44:14, Joey Lee wrote:
> On Fri, Jul 14, 2017 at 10:37:13AM +0200, Michal Hocko wrote:
> > On Thu 13-07-17 20:45:21, Joey Lee wrote:
> > > On Thu, Jul 13, 2017 at 09:06:19AM +0200, Michal Hocko wrote:
> > > > On Thu 13-07-17 14:58:06, Joey Lee wrote:
> > [...]
> > > > > If BIOS e
On Fri, Jul 14, 2017 at 02:42:52PM +0800, Chen-Yu Tsai wrote:
> Now that the CCU device tree binding headers have been merged, we can
> use the properly named macros in the device tree, instead of raw
> numbers.
>
> Signed-off-by: Chen-Yu Tsai
> ---
>
> This patch is included as it is a pre-requ
On Fri, Jul 14, 2017 at 06:04:03PM -0700, Matthias Kaehlcke wrote:
> The current code uses two different enum types for PCH transcoders and
> performs implicit conversions between the two types. This is error prone
> and causes clang to raise warnings like this:
>
> drivers/gpu/drm/i915/intel_dp.c
From: Colin Ian King
Don't return plain integer 0, instead return NULL
Fixes sparse warning:
warning: Using plain integer as NULL pointer
Signed-off-by: Colin Ian King
---
drivers/net/ethernet/broadcom/genet/bcmgenet.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/driver
Hi,
On Fri, Jul 14, 2017 at 02:42:53PM +0800, Chen-Yu Tsai wrote:
> Starting with the A83T SoC, Allwinner introduced a new timing mode for
> its MMC clocks. The new mode changes how the MMC controller sample and
> output clocks are delayed to match chip and board specifics. There are
> two control
On Thu, 2017-07-13 at 17:15 -0400, Jérôme Glisse wrote:
> Existing user of ZONE_DEVICE in its DEVICE_PUBLIC variant are not tie
> to specific device and behave more like host memory. This patch rename
> DEVICE_PUBLIC to DEVICE_HOST and free the name DEVICE_PUBLIC to be use
> for cache coherent devi
On Thu, 2017-07-13 at 17:15 -0400, Jérôme Glisse wrote:
> HMM pages (private or public device pages) are ZONE_DEVICE page and
> thus you can not use page->lru fields of those pages. This patch
> re-arrange the uncharge to allow single page to be uncharge without
> modifying the lru field of the str
On 06/07/2017 at 11:35:24 +0300, Claudiu Beznea wrote:
> Hi all,
>
> This series adds support for sama5d2 SoM1 devices.
>
> The at91-sama5d27_som1.dtsi add specific bindings for SoM1 board.
> The at91-sama5d27_som1_ek.dts add specific bindings for SoM1 EK board.
>
> Thank you,
> Claudiu
>
> Cha
Hi,
On Fri, Jul 14, 2017 at 02:42:54PM +0800, Chen-Yu Tsai wrote:
> The MMC2 clock supports a new timing mode. When the new mode is active,
> the output clock rate is halved.
>
> This patch sets the feature flag for the new timing mode, and adds
> a pre-divider based on the mode bit.
>
> Signed-
On Fri, Jul 14, 2017 at 02:42:55PM +0800, Chen-Yu Tsai wrote:
> The register for the "new timing mode" also has bit fields for setting
> output and sample timing phases. According to comments in Allwinner's
> BSP kernel, the default values are good enough.
>
> Keep the default values already in th
On Mon 17-07-17 09:58:04, Mel Gorman wrote:
> On Mon, Jul 17, 2017 at 10:19:42AM +0200, Michal Hocko wrote:
> > On Mon 17-07-17 09:07:23, Mel Gorman wrote:
> > > On Mon, Jul 17, 2017 at 08:06:40AM +0200, Michal Hocko wrote:
> > > > On Fri 14-07-17 15:18:23, Mel Gorman wrote:
> > > > > Fairly sure t
On 10/07/2017 at 08:12:05 +0200, Ludovic Desroches wrote:
> Use pin macros instead of magic numbers to ease interpretation.
>
> Signed-off-by: Ludovic Desroches
> ---
>
> I have remove the unexpected brace removal from the first version of this
> patch.
>
> arch/arm/boot/dts/at91-sama5d2_xpla
On Thu, 2017-07-13 at 17:15 -0400, Jérôme Glisse wrote:
> HMM pages (private or public device pages) are ZONE_DEVICE page and
> thus need special handling when it comes to lru or refcount. This
> patch make sure that memcontrol properly handle those when it face
> them. Those pages are use like reg
ttribute_groups are not supposed to change at runtime. All functions
working with attribute_groups provided by work
with const attribute_group. So mark the non-const structs as const.
Arvind Yadav (3):
[PATCH v2 1/3] staging: lustre: constify attribute_group structures.
[PATCH v2 2/3] staging
1 - 100 of 1112 matches
Mail list logo
