On 11/09/2016 05:35 AM, Masahiro Yamada wrote:
> Such debug lines might be useful when debugging the driver first,
> but should be deleted from the upstream code.
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Marek Vasut
> ---
>
> drivers/mtd/nand/denali.c | 12 -
On 11/09/2016 05:35 AM, Masahiro Yamada wrote:
> Remove parentheses surrounding the whole right side of an assignment.
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Marek Vasut
> ---
>
> drivers/mtd/nand/denali.c | 14 +++---
> 1 file changed, 7 inser
tk"). Since then, this has been only initialized, but
> never referenced.
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Marek Vasut
> ---
>
> drivers/mtd/nand/denali.c | 2 --
> drivers/mtd/nand/denali.h | 1 -
> 2 files changed, 3 deletions(-)
>
> diff
On 11/09/2016 05:35 AM, Masahiro Yamada wrote:
> The denali->blksperchip is set, but not referenced any more. The
> denali->totalblks is used only for calculating denali->blksperchip.
> Both of them are unneeded.
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Marek Vas
s function is only for Intel platforms.
> I found drivers/staging/spectra used to exist, but it was deleted by
> commit be7f39c5ecf5 ("Staging: delete spectra driver") 5 years ago.
>
> So, I guess nobody would need this function any more.
>
> Signed-off-
On 11/09/2016 03:08 AM, Masahiro Yamada wrote:
> I hope this will make the code a little more readable.
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Marek Vasut
> ---
>
> drivers/mtd/mtdcore.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
&g
On 11/09/2016 05:35 AM, Masahiro Yamada wrote:
> The interrupt handler is setup in denali_init(), not in
> denali_drv_init(). This comment is false.
>
> Such a comment adds no value, so just delete it instead of move.
>
> Signed-off-by: Masahiro Yamada
Review
On 11/09/2016 03:08 AM, Masahiro Yamada wrote:
> There is no need to initialize oobregion and section since they will
> be filled by mtd_ooblayout_find_region().
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Marek Vasut
> ---
>
> drivers/mtd/mtdcore.c | 8
On 11/09/2016 05:35 AM, Masahiro Yamada wrote:
> The driver calls devm_kzalloc()/devm_kfree() to allocate/free memory.
> They are declared in , not in .
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Marek Vasut
> ---
>
> drivers/mtd/nand/denali.c | 1 -
> driv
printk("Failed to ioremap_nocache\n");
> + for (j = 0; j < i; j++) {
> + if (mymtd[j]) {
> + map_destroy(mymtd[j]);
> + iounm
vice briefly in order to read BAR 0 of the SPI host controller.
>
> Signed-off-by: Mika Westerberg
> Acked-by: Lee Jones
Acked-by: Marek Vasut
--
Best regards,
Marek Vasut
->type) {
> + case INTEL_SPI_BYT:
> + pci_read_config_dword(dev, SPIBASE_BYT, &spi_base);
> + if (spi_base & SPIBASE_BYT_EN) {
> + res->start = spi_base & ~(SPIBASE_BYT_SZ - 1);
> + res->end = res->start + SPIBASE_BYT_SZ - 1;
> + }
> + break;
> +
> + case INTEL_SPI_LPT:
> + pci_read_config_dword(dev, RCBABASE, &rcba);
> + if (rcba & 1) {
> + spi_base = rcba & ~(SPIBASE_LPT_SZ - 1);
Use the round_down() macro here ?
> + res->start = spi_base + SPIBASE_LPT;
> + res->end = res->start + SPIBASE_LPT_SZ - 1;
[...]
--
Best regards,
Marek Vasut
status = readl(ispi->base + HSFSTS_CTL);
> + if (status & HSFSTS_CTL_FCERR)
> + ret = -EIO;
> + else if (status & HSFSTS_CTL_AEL)
> + ret = -EACCES;
> +
> + if (ret < 0) {
> + dev_err(ispi->dev, "write error: %llx: %#x\n", to,
> + status);
> + return ret;
> + }
> +
> + len -= block_size;
> + to += block_size;
> + retlen += block_size;
> + write_buf += block_size;
> + }
> +
> + return retlen;
> +}
[...]
--
Best regards,
Marek Vasut
No SECT_4K support here ?
> { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
> { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
> { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
>
--
Best regards,
Marek Vasut
-by: Larry D. Pinney
It looks OK:
Acked-by: Marek Vasut
> ---
> Sorry, forgot to add this to the series I sent earlier
>
> drivers/mtd/spi-nor/spi-nor.c |2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
2539, 0, 64 * 1024, 512, 0) },
> { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
> { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ)
> },
> { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ)
> },
>
--
Best regards,
Marek Vasut
,
> { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
> { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ)
> },
> { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ)
> },
>
--
Best regards,
Marek Vasut
05d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
> + { "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64, SECT_4K) },
> { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
> { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
> { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
>
--
Best regards,
Marek Vasut
gt;> I took these values from the manufacturer SDK (Qualcomm). I could not detect
>> any problems with the setting.
>>
>> Kind regards,
>>
>> André
>>
>> Am 21.12.2016 um 08:33 schrieb Marek Vasut:
>>> On 12/21/2016 08:23 AM, John Crispin wrote:
>>>
On 10/24/2016 09:41 AM, Jagan Teki wrote:
> On Sun, Oct 23, 2016 at 2:03 AM, Marek Vasut wrote:
>> On 10/22/2016 01:00 PM, Jagan Teki wrote:
>>> On Wed, Oct 5, 2016 at 5:30 PM, Cyrille Pitchen
>>> wrote:
>>>> Hi all,
>>>>
>>>> This s
reate a maintainer team formed of the most active MTD contributors
>> to help Brian with this task, which will hopefully improve the
>> subsystem reactivity.
>>
>> Signed-off-by: Boris Brezillon
> Acked-by: Cyrille Pitchen
>
> thanks! :)
Acked-by: Marek Vasut
Thanks
--
Best regards,
Marek Vasut
s a correct
> fix for the problem and avoids the warning.
>
> Signed-off-by: Arnd Bergmann
Reviewed-by: Marek Vasut
> ---
> drivers/mtd/maps/ichxrom.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/maps/ichxrom.c b/drivers/mtd
n just up the debug level
or add his own printk .
> write_enable(nor);
>
> write_sr(nor, val | SR_QUAD_EN_MX);
>
--
Best regards,
Marek Vasut
/* 0x6b */
> + ENTRY_3TO4(SPINOR_OP_READ_1_2_2), /* 0xbb */
> + ENTRY_3TO4(SPINOR_OP_SE), /* 0xd8 */
> + ENTRY_3TO4(SPINOR_OP_READ_1_4_4), /* 0xeb */
> + };
> +#undef ENTRY_3TO4
> +
> + return spi_nor_convert_opcode(opcode, spi_nor_3to4_table,
> + ARRAY_SIZE(spi_nor_3to4_table));
> +}
> +
[...]
--
Best regards,
Marek Vasut
> + *code_nbits = SNOR_PROTO_CODE_FROM_PROTO(proto);
> + if (addr_nbits)
> + *addr_nbits = SNOR_PROTO_ADDR_FROM_PROTO(proto);
> + if (data_nbits)
> + *data_nbits = SNOR_PROTO_DATA_FROM_PROTO(proto);
> +
> + return 0;
> +}
> +
[...]
--
Best regards,
Marek Vasut
024, 2048, SPI_NOR_QUAD_READ)
> },
> { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ)
> },
>
> /* Micron */
>
This should be submitted separately as it could be applied right away.
--
Best regards,
Marek Vasut
/spi-nor.h
> @@ -80,6 +80,7 @@
> #define SPINOR_OP_BP 0x02/* Byte program */
> #define SPINOR_OP_WRDI 0x04/* Write disable */
> #define SPINOR_OP_AAI_WP 0xad/* Auto address increment word program
> */
> +#define SPINOR_OP_ULBPR 0x98/* Global Block Protection
> Unlock */
>
> /* Used for Macronix and Winbond flashes. */
> #define SPINOR_OP_EN4B 0xb7/* Enter 4-byte mode */
>
--
Best regards,
Marek Vasut
On 10/25/2016 11:39 AM, Cyrille Pitchen wrote:
> Hi Marek,
Hi,
> Le 25/10/2016 à 00:16, Marek Vasut a écrit :
>> On 10/24/2016 06:34 PM, Cyrille Pitchen wrote:
>>> This patch adds an entry in the spi_nor_ids[] table to add support
>>> to the Macronix mx66l1g45g.
On 10/25/2016 11:18 AM, Cyrille Pitchen wrote:
> Le 25/10/2016 à 00:10, Marek Vasut a écrit :
>> On 10/24/2016 06:34 PM, Cyrille Pitchen wrote:
>>> This patch provides an alternative mean to support memory above 16MiB
>>> (128Mib) by replacing 3byte address op code
On 10/25/2016 10:52 AM, Cyrille Pitchen wrote:
> Hi Marek,
>
> Le 25/10/2016 à 00:00, Marek Vasut a écrit :
>> On 10/24/2016 06:34 PM, Cyrille Pitchen wrote:
>>> The patch checks whether the Quad Enable bit is already set in the Status
>>> Register. If so, the
the commit message. I presume this happens if
buf[i].name[0] = 0xff for all $i, right ?
So please expand the explanation and add my Ack for V2:
Acked-by: Marek Vasut
Thanks
> ---
> drivers/mtd/redboot.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/mtd/redb
select FSL_IFC
> select MEMORY
> help
>
--
Best regards,
Marek Vasut
pport for Freescale IFC controller"
>>> - depends on FSL_SOC || ARCH_LAYERSCAPE
>>> + depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A
>>> select FSL_IFC
>>> select MEMORY
>>> help
>>>
>
> Best Regards,
> Alison Wang
>
--
Best regards,
Marek Vasut
x this.
>
> Signed-off-by: Geert Uytterhoeven
Reviewed-by: Marek Vasut
> ---
> drivers/clk/clk-conf.c | 15 +--
> 1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c
> index 674785d968a3e1c5..e0e0
> if (!(chip->options & NAND_SCAN_SILENT_NODEV))
> pr_warn("No NAND device found\n");
>
--
Best regards,
Marek Vasut
On 01/03/2017 02:01 PM, Boris Brezillon wrote:
> Now that struct nand_chip embeds an mtd_info object we can get rid of the
> mtd parameter and extract it from the chip parameter with the nand_to_mtd()
> helper.
>
> Signed-off-by: Boris Brezillon
Reviewed-by: Marek Vasut
>
On 01/04/2017 06:13 PM, Boris Brezillon wrote:
> On Wed, 4 Jan 2017 16:15:46 +0100
> Marek Vasut wrote:
>
>> On 01/03/2017 02:01 PM, Boris Brezillon wrote:
>>> Move Micron specific initialization logic into nand_micron.c. This is
>>> part of the "separate v
On 12/12/2016 08:54 AM, Lee Jones wrote:
> On Fri, 09 Dec 2016, Marek Vasut wrote:
>
>> On 12/09/2016 01:25 PM, Mika Westerberg wrote:
>>> On Fri, Dec 09, 2016 at 08:57:53AM +, Lee Jones wrote:
>>>> On Wed, 07 Dec 2016, Marek Vasut wrote:
>>>>
culation (default addressing mode).
>> - The spi nor commands used.
>>
>> Protocol is described on Xilinx User Guide UG333
>>
>> Reviewed-by: Cyrille Pitchen
>> Signed-off-by: Ricardo Ribalda Delgado
>> Cc: Boris Brezillon
>> Cc: Brian Norris
>> C
> Cc: Boris Brezillon
> Cc: Brian Norris
> Cc: Marek Vasut
[...]
> +static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor)
> +{
> + int ret;
> + u8 val;
> +
> + ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1);
> + if (ret
On 12/14/2016 12:56 AM, Stefan Agner wrote:
> On 2016-12-08 20:24, Marek Vasut wrote:
>> On 12/09/2016 04:44 AM, Stefan Agner wrote:
>>> On 2016-12-08 15:33, Marek Vasut wrote:
>>>> On 12/08/2016 11:52 PM, Stefan Agner wrote:
>>>>> The LCD bus width
On 12/14/2016 01:01 AM, Stefan Agner wrote:
> On 2016-12-08 15:38, Marek Vasut wrote:
>> On 12/08/2016 09:46 PM, Stefan Agner wrote:
>>> On 2016-12-07 18:37, Marek Vasut wrote:
>>>> On 12/08/2016 02:26 AM, Stefan Agner wrote:
>>>>> On 2016-12-07 16:59
t; 16)
> #define CTRL_SET_BUS_WIDTH(x) (((x) & 0x3) << 10)
> #define CTRL_GET_BUS_WIDTH(x)(((x) >> 10) & 0x3)
> +#define CTRL_BUS_WIDTH_MASK (0x3 << 10)
> #define CTRL_SET_WORD_LENGTH(x) (((x) & 0x3) << 8)
> #define CTRL_GET_WORD_LENGTH(x) (((x) >> 8) & 0x3)
> #define CTRL_MASTER (1 << 5)
>
--
Best regards,
Marek Vasut
On 12/14/2016 09:29 PM, Stefan Agner wrote:
> On 2016-12-14 00:04, Marek Vasut wrote:
>> On 12/14/2016 01:01 AM, Stefan Agner wrote:
>>> On 2016-12-08 15:38, Marek Vasut wrote:
>>>> On 12/08/2016 09:46 PM, Stefan Agner wrote:
>>>>> On 2016-12-07 18:37,
On 12/14/2016 09:51 PM, Stefan Agner wrote:
> On 2016-12-13 23:52, Marek Vasut wrote:
>> On 12/14/2016 02:02 AM, Stefan Agner wrote:
>>> The LCD bus width does not need to align with the pixel format. The
>>> LCDIF controller automatically converts between pixel f
>
> Signed-off-by: Stefan Agner
Acked-by: Marek Vasut
> ---
> Changes since v1:
> - Improved comments/fixed typo
>
> drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 11 +--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mxsfb/mxsfb
which allows to
> determine what bus_formats are supported by the display. Choose the
> first available or fallback to 24 bit if none are available.
>
> Signed-off-by: Stefan Agner
Acked-by: Marek Vasut
> ---
> Changes in v3:
> - Use read-modify-write to update the LCDC_CTRL fie
> drivers/mtd/nand/xway_nand.c:235:1: error:
> type defaults to 'int' in declaration of 'MODULE_DEVICE_TABLE'
> [-Werror=implicit-int]
>
> It missed to include the header file.
>
> Signed-off-by: Sudip Mukherjee
Acked-by: Marek V
case SPI_NOR_NORMAL:
> - nor->read_opcode = SPINOR_OP_READ_4B;
> - break;
> - }
> - nor->program_opcode = SPINOR_OP_PP_4B;
> - /* No small sector erase for 4-byt
;rb_first' in the mtdswap driver , you'll see you can also use the
MTDSWAP_ECNT_MIN macro in mtdswap_map_free_block() and in
mtdswap_pick_gc_blk() . Can you fix those too ?
Otherwise:
Acked-by: Marek Vasut
> ---
> drivers/mtd/mtdswap.c | 6 ++
> 1 file changed, 2 insertions(
On 12/24/2016 04:18 PM, Geliang Tang wrote:
> On Fri, Dec 23, 2016 at 07:51:56PM +0100, Marek Vasut wrote:
>> On 12/20/2016 02:54 PM, Geliang Tang wrote:
>>> Since macros MTDSWAP_ECNT_MIN() and MTDSWAP_ECNT_MAX() have been
>>> defined in mtdswap.c, use them instead of
On 11/29/2016 09:12 AM, Sandeep Jain wrote:
> Dear Maintainers,
>This patch is already reviewed twice with no issues.
> Requesting your attention for patch merge.
>
> Thanks & Regards,
> Sandeep Jain
>
> On Sat, Nov 05, 2016 at 08:22:31AM +0100, Marek Vasut wrot
er exposes a single read-only MTD device but with a module parameter
> "writeable=1" the MTD device can be made read-write which makes it possible
> to upgrade BIOS directly from Linux.
>
> Signed-off-by: Mika Westerberg
> Acked-by: Cyrille Pitchen
> ---
[...]
Revi
some ECC ?
> + nor->mtd.writebufsize = nor->page_size;
> + nor->mtd.size = 8 * nor->page_size * info->n_sectors;
> + nor->mtd.erasesize = 8 * nor->page_size;
> + } else {
> + nor->flags |= SNOR_F_S3AN_ADDR_DEFAULT;
> + }
> +
> + return 0;
> +}
[...]
--
Best regards,
Marek Vasut
vice has one.
>
> Signed-off-by: Mika Westerberg
> Acked-by: Lee Jones
Reviewed-by: Marek Vasut
--
Best regards,
Marek Vasut
On 12/01/2016 07:14 PM, Brian Norris wrote:
> On Thu, Dec 01, 2016 at 04:39:23PM +0100, Marek Vasut wrote:
>> On 11/29/2016 09:12 AM, Sandeep Jain wrote:
>>> On Sat, Nov 05, 2016 at 08:22:31AM +0100, Marek Vasut wrote:
>>>> On 11/03/2016 12:34 PM, Sandeep Jain wrote:
On 12/01/2016 06:52 PM, Ricardo Ribalda Delgado wrote:
> Hi Marek
Hi,
> Thanks for your review
>
> On Thu, Dec 1, 2016 at 5:05 PM, Marek Vasut wrote:
>>
>> On 11/24/2016 05:56 PM, Ricardo Ribalda Delgado wrote:
>
>>> +#define
On 12/02/2016 11:52 AM, Ricardo Ribalda Delgado wrote:
> Hi Marek
Hi,
> On Thu, Dec 1, 2016 at 7:11 PM, Marek Vasut wrote:
>> On 12/01/2016 06:52 PM, Ricardo Ribalda Delgado wrote:
>>> Hi Marek
>>
>> Hi,
>>
>>> Thanks for your review
>>&g
iphier-v5b-nand" (and v5a).
>> The fact that it is denali is part of the documentation.
>>
>
> Let me think about this.
>
> Socionext bought two version of Denali IP,
> and we are now re-using the newer one (v5b) for several SoCs.
> Socionext has some more product lines other than Uniphier SoC family,
> perhaps wider re-use might happen in the future.
>
> At first, I included "uniphier" in compatible, but I am still wondering
> if such a specific string is good or not.
>
> Also, comments from Altera engineers are appreciated.
Adding a few more on Cc
--
Best regards,
Marek Vasut
ot;);
> - return 0;
> + return -ENOMEM;
I wonder if you shouldn't also nuke the ubi_err() , because when you run
out of memory, printk() will likely also fail.
> }
>
> err = mtd_read(ubi->mtd, addr, len, &read, buf);
>
--
Best regards,
Marek Vasut
On 12/04/2016 09:33 PM, Joe Perches wrote:
> On Sun, 2016-12-04 at 13:48 +0100, Marek Vasut wrote:
>> On 12/04/2016 07:12 AM, Pan Bian wrote:
>>> From: Pan Bian
>>>
>>> When __vmalloc() returns a NULL pointer, the region is not checked, and
>>> we cann
On 12/05/2016 04:30 AM, Masahiro Yamada wrote:
> Hi Dinh,
>
>
> 2016-12-04 7:08 GMT+09:00 Dinh Nguyen :
>> Hi,
>>
>> On Fri, Dec 2, 2016 at 8:49 PM, Marek Vasut wrote:
>>> On 12/03/2016 03:41 AM, Masahiro Yamada wrote:
>>>> Hi Rob,
>>
On 12/05/2016 05:10 AM, Masahiro Yamada wrote:
> Hi Marek,
>
>
> 2016-12-05 12:44 GMT+09:00 Marek Vasut :
>> On 12/05/2016 04:30 AM, Masahiro Yamada wrote:
>>> Hi Dinh,
>>>
>>>
>>> 2016-12-04 7:08 GMT+09:00 Dinh Nguyen :
>>>>
clocks = <&misc_clk &misc_clk>;
> + interrupt-parent = <&gic>;
> + interrupts = <0 14 4>;
> + arasan,has-mdma;
> + #address-cells = <1>;
> + #size-cells = <0>
> +
> + nand@0 {
> + reg = <0>
> + partition@0 {
> + label = "filesystem";
> + reg = <0x0 0x0 0x100>;
> + };
> + (...)
> + };
> + };
>
--
Best regards,
Marek Vasut
+ chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
> + anfc_writefifo(nfc, PROG_SET_FEATURE, achip->spktsize,
> + subfeature_param);
> +
> + status = chip->waitfunc(mtd, chip);
> + if (status & NAND_STATUS_FAIL)
> + return -EIO;
> +
> + return 0;
> +}
> +
> +static int anfc_init_timing_mode(struct anfc *nfc,
> + struct anfc_nand_chip *achip)
> +{
> + int mode, err;
> + unsigned int feature[2];
> + u32 inftimeval;
> + struct nand_chip *chip = &achip->chip;
> + struct mtd_info *mtd = nand_to_mtd(chip);
> +
> + memset(feature, 0, NVDDR_MODE_PACKET_SIZE);
> + /* Get nvddr timing modes */
> + mode = onfi_get_sync_timing_mode(chip) & 0xff;
> + if (!mode) {
> + mode = fls(onfi_get_async_timing_mode(chip)) - 1;
> + inftimeval = mode;
> + } else {
> + mode = fls(mode) - 1;
> + inftimeval = NVDDR_MODE | (mode << NVDDR_TIMING_MODE_SHIFT);
> + mode |= ONFI_DATA_INTERFACE_NVDDR;
> + }
> +
> + feature[0] = mode;
> + chip->select_chip(mtd, achip->csnum);
> + err = chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_TIMING_MODE,
> + (uint8_t *)feature);
> + chip->select_chip(mtd, -1);
> + if (err)
> + return err;
> +
> + achip->inftimeval = inftimeval;
> +
> + if (mode & ONFI_DATA_INTERFACE_NVDDR)
> + achip->spktsize = NVDDR_MODE_PACKET_SIZE;
> +
> + return 0;
> +}
[...]
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Xilinx, Inc");
There should be a contact with email address here.
> +MODULE_DESCRIPTION("Arasan NAND Flash Controller Driver");
>
--
Best regards,
Marek Vasut
>> 1 file changed, 21 insertions(+)
>>>> create mode 100644
>>>> Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
>>>
>>> Acked-by: Rob Herring
>>>
>>
>> Acked-by: Alan Tull
> Acked-by: Moritz Fischer
Acked-by: Marek Vasut
--
Best regards,
Marek Vasut
ff-by: Luis Henriques
Reviewed-by: Marek Vasut
> ---
> drivers/mtd/maps/sc520cdp.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/mtd/maps/sc520cdp.c b/drivers/mtd/maps/sc520cdp.c
> index 093edd51bdc7..7a27ed345d0d 100644
> --- a/drivers/mtd/maps/sc52
On 11/21/2016 10:49 PM, Moritz Fischer wrote:
> Add myself as co-maintainer to fpga mgr framework.
>
> Signed-off-by: Moritz Fischer
> Cc: Alan Tull
> Cc: Greg Kroah-Hartman
> Cc: linux-kernel@vger.kernel.org
> Cc: linux-f...@vger.kernel.org
Acked-by: Marek Vasut
> -
(1 << (n))
This would turn into BIT(n) , no ?
> +#define LRADC_CTRL1_MX28_LRADC_IRQ_MASK 0x1fff
> +#define LRADC_CTRL1_MX23_LRADC_IRQ_MASK 0x01ff
> +#define LRADC_CTRL1_LRADC_IRQ_OFFSET 0
[...]
--
Best regards,
Marek Vasut
c-adc.c
> delete mode 100644 drivers/iio/adc/mxs-lradc.c
> create mode 100644 drivers/input/touchscreen/mxs-lradc-ts.c
> create mode 100644 drivers/mfd/mxs-lradc.c
> create mode 100644 include/linux/mfd/mxs-lradc.h
>
Except minor nit in 1/5, the whole series is:
Reviewed-by: Marek Vasut
--
Best regards,
Marek Vasut
On 12/08/2016 09:46 PM, Stefan Agner wrote:
> On 2016-12-07 18:37, Marek Vasut wrote:
>> On 12/08/2016 02:26 AM, Stefan Agner wrote:
>>> On 2016-12-07 16:59, Stefan Agner wrote:
>>>> On 2016-12-07 16:49, Marek Vasut wrote:
>>>>> On 12/08/2016 01:27 AM,
MEDIA_BUS_FMT_RGB888_1X24:
> + reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_24BIT);
> + break;
> + default:
> + dev_err(drm->dev, "Unknown media bus format %d\n", bus_format);
> + break;
> + }
> + writel(reg, mxsfb->base + LCDC_CTRL);
On MX6SX:
Tested-by: Marek Vasut
--
Best regards,
Marek Vasut
On 12/09/2016 04:44 AM, Stefan Agner wrote:
> On 2016-12-08 15:33, Marek Vasut wrote:
>> On 12/08/2016 11:52 PM, Stefan Agner wrote:
>>> The LCD bus width does not need to align with the pixel format. The
>>> LCDIF controller automatically converts between pixel f
A PMOD module may contain a device
> with which the kernel communicates, via the FPGA.
>
> Signed-off-by: Joel Holdsworth
Reviewed-by: Marek Vasut
--
Best regards,
Marek Vasut
On 12/09/2016 01:25 PM, Mika Westerberg wrote:
> On Fri, Dec 09, 2016 at 08:57:53AM +, Lee Jones wrote:
>> On Wed, 07 Dec 2016, Marek Vasut wrote:
>>
>>> On 12/07/2016 09:53 AM, Mika Westerberg wrote:
>>>> On Tue, Dec 06, 2016 at 09:45:25AM +, Lee Jon
if (!base)
> + return ret;
I think return -ENOMEM right away won't hurt here. Also, dev_err()
explaining the failure would be nice to add.
Thanks!
> cascade = devm_kzalloc(dev, sizeof(*cascade) * DOC_MAX_NBFLOORS,
> GFP_KERNEL);
> if (!cascade)
>
--
Best regards,
Marek Vasut
;
> + if (!base) {
> + dev_err(dev, "failed to map I/O memory\n");
> + return ret;
Um, return -ENOMEM right away ?
Otherwise,
Acked-by: Marek Vasut
> + }
> +
> cascade = devm_kzalloc(dev, sizeof(*cascade) * DOC_MAX_NBFLOORS,
> GFP_KERNEL);
> if (!cascade)
>
--
Best regards,
Marek Vasut
On 03/20/2017 12:26 PM, Artur Jedrysek wrote:
> Cadence Quad SPI driver successfully runs on Xtensa CPU, and Kconfig
> file is updated to indicate that.
>
> Signed-off-by: Artur Jedrysek
Acked-by: Marek Vasut
> ---
> Changelog:
> v2: This change is extracted from pre
+1206,7 @@ static int cqspi_probe(struct platform_device *pdev)
> mutex_init(&cqspi->bus_mutex);
> cqspi->pdev = pdev;
> platform_set_drvdata(pdev, cqspi);
> + cqspi->caps = 0;
The structure is zeroed-out on allocation, so this shouldn't be needed.
> /* Obtain configuration from OF. */
> ret = cqspi_of_get_pdata(pdev);
> @@ -1277,13 +1324,6 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
> #define CQSPI_DEV_PM_OPS NULL
> #endif
>
> -static struct of_device_id const cqspi_dt_ids[] = {
> - {.compatible = "cdns,qspi-nor",},
> - { /* end of table */ }
> -};
> -
> -MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
> -
> static struct platform_driver cqspi_platform_driver = {
> .probe = cqspi_probe,
> .remove = cqspi_remove,
>
--
Best regards,
Marek Vasut
; + read-only;
> +
> + nvmem-provider;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + eeprom@1000 {
> + label = "wmac-eeprom";
> + reg = <0x1000 0x1000>;
> + };
> + };
> + };
>
--
Best regards,
Marek Vasut
mp;cs);
> @@ -1123,7 +1183,7 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi,
> struct device_node *np)
> goto err;
> }
>
> - ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD);
> + ret = spi_nor_scan(nor, NULL, mode);
> if (ret)
> goto err;
>
> @@ -1277,13 +1337,6 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
> #define CQSPI_DEV_PM_OPS NULL
> #endif
>
> -static struct of_device_id const cqspi_dt_ids[] = {
> - {.compatible = "cdns,qspi-nor",},
> - { /* end of table */ }
> -};
> -
> -MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
> -
> static struct platform_driver cqspi_platform_driver = {
> .probe = cqspi_probe,
> .remove = cqspi_remove,
>
--
Best regards,
Marek Vasut
- reg : Contains two entries, each of which is a tuple consisting of a
> physical address and length. The first entry is the address and
> length of the controller register set. The second entry is the
>
--
Best regards,
Marek Vasut
On 03/10/2017 05:06 AM, Moritz Fischer wrote:
> On Thu, Mar 9, 2017 at 7:17 PM, Marek Vasut wrote:
>> On 03/07/2017 09:26 AM, Alban wrote:
>>> Config data for drivers, like MAC addresses, is often stored in MTD.
>>> Add a binding that define how such data storage can b
On 03/10/2017 07:38 AM, Maxime Ripard wrote:
> Hi Marek,
>
> On Fri, Mar 10, 2017 at 05:52:36AM +0100, Marek Vasut wrote:
>> On 03/10/2017 05:06 AM, Moritz Fischer wrote:
>>> On Thu, Mar 9, 2017 at 7:17 PM, Marek Vasut wrote:
>>>> On 03/07/2017 09:26 AM
On 03/10/2017 01:00 PM, Artur Jedrysek wrote:
>
> From: Marek Vasut [mailto:marek.va...@gmail.com]
> Sent: 10 March 2017 04:37
>> On 03/08/2017 09:02 AM, Artur Jedrysek wrote:
>>> Recent versions of Cadence QSPI controller support Octal SPI transfers
>>> as
On 03/10/2017 01:03 PM, Artur Jedrysek wrote:
>
>> From: Marek Vasut [mailto:marek.va...@gmail.com]
>> Sent: 10 March 2017 04:39
>> On 03/08/2017 09:05 AM, Artur Jedrysek wrote:
>>> This patch updates Cadence QSPI Device Tree documentation to include
>>> i
;>
>
> Quad-SPI controller can always support single, dual and quad. There was
> no option to configure max mode. Octal-SPI controller can be configured
> to support either octal or quad mode. No controller could be configured
> (during hardware compilation/synthesis) to support only single/dual
> SPI mode. To put it shortly: single, dual and quad is always supported.
So basically the whole check you need to perform here is
mode = quad;
if (controller->flags & CAN_DO_OCTAL) {
if (readl(ID_REGISTER) & IS_CONFIGURED_AS_OCTAL)
mode = octal;
}
--
Best regards,
Marek Vasut
W, seems it's just block size (512) at some other calling side.
>
> (Sorry for previous same content email, just found out it's html
> format and rejected by mail list)
>
> On Mon, Feb 27, 2017 at 1:31 AM, Marek Vasut wrote:
>> On 02/22/2017 03:15 AM, Lepton Wu wrot
o does" suggested by
> Documentation/CodingStyle.
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Marek Vasut
> ---
>
> drivers/mtd/nand/denali_pci.c | 14 +-
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mtd/nand/denali_p
>> nor->read_reg = m25p80_read_reg;
>> + nor->mtd._put_device = m25p80_put;
>> +nor->mtd._get_device = m25p80_get;
>>
>> nor->dev = &spi->dev;
>> spi_nor_set_flash_node(nor, spi->dev.of_node);
This makes me ponder how many other drivers suffer from this issue and
whether you shouldn't fix this in the core code instead. What do you think?
--
Best regards,
Marek Vasut
ghmem addresses.
>>>
>>> Fix this by allocating the BDI objects dynamically with kmalloc. The
>>> objects now fall in the logical address space so that BDI APIs will
>>> work in all cases (mtd builtin or module).
>>>
>>> Signed-off-by: Steve Longerbe
> Signed-off-by: Masahiro Yamada
Reviewed-by: Marek Vasut
> ---
>
> drivers/mtd/nand/denali_dt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/denali_dt.c b/drivers/mtd/nand/denali_dt.c
> index 0cb1e8d..f821dc1 100644
>
a few return -ENODEV).
>
> This series make those drivers return more precise error code.
>
Reviewed-by: Marek Vasut
Nice cleanup, thanks!
--
Best regards,
Marek Vasut
On 02/23/2017 12:30 PM, Colin King wrote:
> From: Colin Ian King
>
> trivial fix to spelling mistake in NS_ERR error message
>
> Signed-off-by: Colin Ian King
Acked-by: Marek Vasut
Thanks
> ---
> drivers/mtd/nand/nandsim.c | 2 +-
> 1 file changed, 1 insertion(+),
On 02/14/2017 10:57 AM, Mika Westerberg wrote:
> On Tue, Feb 14, 2017 at 05:52:48AM +0100, Marek Vasut wrote:
>> On 02/13/2017 09:13 AM, Nicholas Mc Guire wrote:
>>> writeable in struct intel_spi is a boolean and assignment should be to
>>> true/false not 1/0 as re
automatically driven during the
> memory access and it is not managed by a GPIO.
>
> Signed-off-by: Christophe Leroy
Reviewed-by: Marek Vasut
but please wait for the NAND experts ...
> ---
> drivers/mtd/nand/gpio.c | 18 --
> 1 file changed, 12 insertions(+),
base
>
> Patch was compile tested with: multi_v7_defconfig (implies
> CONFIG_MTD_SPI_NOR=y)
Was this driver even enabled with multi_v7 and MTD_SPI_NOR=y ?
Nonetheless, the patch is correct:
Acked-by: Marek Vasut
> Patch is against 4.10-rc7 (localversion-next is next-20170213)
>
> dr
;
> -
Drop this one new line.
> dev_dbg(dev,
> "mtd .name = %s, .size = 0x%llx (%lldMiB), "
> ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
>
--
Best regards,
Marek Vasut
gt;writeable = false;
>
> end = (limit << 12) + 4096;
> if (end > part->size)
>
Looks OK, also this is the only place in the driver where writeable is
assigned to an explicit true/false value.
Acked-by: Marek Vasut
btw the variable should be renamed from writeable to writable ;-)
--
Best regards,
Marek Vasut
On 02/17/2017 11:08 PM, Alexey Khoroshilov wrote:
> hisi_spi_nor_probe() ignores clk_prepare_enable() error code.
> The patch fixes that.
>
> Found by Linux Driver Verification project (linuxtesting.org).
>
> Signed-off-by: Alexey Khoroshilov
Acked-by: Marek Vasut
> -
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