On Jul 29, 2016, at 5:14 PM, Kevin Rosenberg wrote:
I had a question about your experience. You mentioned using a input
signal near the maximum of the USRP’s ADC to get the best SNR. I
reviewed the schematics and application notes. I found a maximum Vpp
mentioned of 3.3V. I was wondering what vol
Hi
There are a *lot* of papers out there on downsampling and ADEV. Just about any
/ every technique known
has been tried and evaluated. The only “correct” answer is to throw away the
samples (decimation). Anything
else you do will give you subtle (or not so subtle) issues. That said, there
ar
Hi
The simple answer is a filter at the highest sample rate (say 1 second) that
impacts the 1 second data.
You then decimate from there. If you want 1 second data that “looks right” you
start at something higher
(say 0.1 second) and filter there. The data set is filtered once (if at all)
and d
Hmm, I might have answered my own question: filter to the fast samples to the
equivalent noise bandwidth (ENBW) of the lower desired sampling rate and then
decimate.
> On Jul 29, 2016, at 9:44 PM, Kevin Rosenberg wrote:
>
> Hi Bob,
>
> You have a good point. That leads to the question is what
Hi Bob,
You have a good point. That leads to the question is what is the “best”
measurement technique when you are sampling at a more smaller interval than the
desired tau?
SDRs sample at high rates. The slowest the USRP N2x0 can sample is just under
200Ksps. For easy math, let’s assume we sam
HI
Keep in mind that if you apply pre-filtering, an ADEV plot is lying to you ….
Bob
> On Jul 29, 2016, at 6:58 PM, Kevin Rosenberg wrote:
>
> Jeff,
>
> Thanks for your very useful paper Oscillator Metrology with SDRs[1]. I
> created a C++ program and checked residuals using a 10 MHz clock sp
Jeff,
Thanks for your very useful paper Oscillator Metrology with SDRs[1]. I created
a C++ program and checked residuals using a 10 MHz clock split to the A and B
channels of a LFRX and BasicRX boards and sampled at 1 Mhz. Using boxcar
averaging of 1000 samples at 1 kHz, I was impressed by the
On Wed, 1 Jun 2016 16:00:39 +
"Sherman, Jeffrey A. (Fed)" wrote:
> I'm not sure exact which ~15dB you're contemplating, but I'll hazard
> a guess.
You measured an ADC noise floor of -140dBc/Hz. The TimePod has a spec'ed
noise floor of -170dBc/Hz(typ). That's a difference of ~30dB.
The diff
On 6/1/16 8:45 AM, Sherman, Jeffrey A. (Fed) wrote:
Jim Lux:
If you pick the right USRP models, you can lock the sampling clocks
together or distribute the clock. I don't know if that distribution is
sufficiently high quality for time-nuts kinds of applications.
A bit of extra detail related to
Jim Lux:
If you pick the right USRP models, you can lock the sampling clocks
together or distribute the clock. I don't know if that distribution is
sufficiently high quality for time-nuts kinds of applications.
A bit of extra detail related to this but not reported in print... The N210 has
two m
Atilla Kinali:
Yes, the spec'ed SNR of the ADS62P44 is 74dBFS (typ) while the LTC2216
is spec'ed with 81dBFS (typ). Additionally, the input amplitudes in
Sherman and Jördens experiments were kept around half scale, which is
another -6dB in SNR. There is another ~15dB in difference, but I currently
On Wed, 25 May 2016 16:01:51 +
"Sherman, Jeffrey A. (Fed)" wrote:
> We found that in the studied units the limiting non-stationary noise
> source was likely the aperture jitter of the ADC (the instability of the
> delay between an idealized sample trigger and actuation of the sample/hold
> ci
Bob Camp:
> In many DMTD (and single mixer) systems, a lowpass and high pass filter are
> applied to the signal coming out of the mixer.
> This is done to improve the zero crossing detection. It also effectively
> reduces the “pre detection” bandwidth. My understanding
> of the setup in your pap
No it has 4 x LTC2216 (single 16bit ADCs).
Bruce
On Sunday, 29 May 2016 4:06 AM, Bob Camp wrote:
HI
It’s been a while since I dug into a TimePod. Doesn’t it have two dual ADC’s in
it? You can select which
way you route the signals into the ADEV process.
Bob
> On May 28, 2016, at 11
HI
It’s been a while since I dug into a TimePod. Doesn’t it have two dual ADC’s in
it? You can select which
way you route the signals into the ADEV process.
Bob
> On May 28, 2016, at 11:04 AM, Bruce Griffiths
> wrote:
>
> One can just measure the TDEV performance.I can measure the TDEV per
One can just measure the TDEV performance.I can measure the TDEV performance at
10MHz later today if that's useful.It should be somewhat similar to the single
channel SDR instrument given there is no cancellation of most of the internal
ADC clock conditioning system noise.
Bruce
On Sunday
On Sat, 28 May 2016 08:47:45 + (UTC)
Bruce Griffiths wrote:
> This SDR setup appears to have a higher PN (at least 2 ADC's per signal
> are required to achieve lower PN ) than a Timepod, however it appears
> to be better at measuring ADEV than a Timepod.
Yes, the spec'ed SNR of the ADS62P44
On 5/27/16 6:58 PM, Hal Murray wrote:
bruce.griffi...@xtra.co.nz said:
All the filtering and down mixing is done in the digital domain.
Anitialiasing filters in front of the ADCs are also be required.
What sort of bandwidth is expected?
The usual trick with audio ADCs is to have a low cost a
On 5/27/16 5:17 PM, Bruce Griffiths wrote:
On Thursday, May 26, 2016 06:40:26 PM Bob Camp wrote:
Hi
Very interesting paper, thanks for sharing !!
One question:
In many DMTD (and single mixer) systems, a lowpass and high pass filter are
applied to the signal coming out of the mixer. This is do
On 5/27/16 6:15 PM, Bob Camp wrote:
Hi
On May 27, 2016, at 8:17 PM, Bruce Griffiths wrote:
On Thursday, May 26, 2016 06:40:26 PM Bob Camp wrote:
Hi
Very interesting paper, thanks for sharing !!
One question:
In many DMTD (and single mixer) systems, a lowpass and high pass filter are
appl
Hi
The Max V FPGA on the Bemicro card is pretty impressive. The gotcha is with the
Quartus
side of things. Altera is not willing to let you have the DSP stuff (NCO’s,
CIC’s, FIR’s) for free
the way Xilinx is.
Bob
> On May 28, 2016, at 4:47 AM, Bruce Griffiths
> wrote:
>
> A low pass filter
Hi
The normal process with a 10 Hz beat note in a DMTD is to have something like a
6 Hz two
pole high pass and a 15 Hz two pole lowpass after the mixer and before any zero
crossing stuff.
This is after down conversion, but before any demodulation. This of course is
based on the
fundamental a
A low pass filter will reduce the source broadband noise aliased into the ADC
output signal.
Using the LVDS ADC outputs rather than the CMOS outputs may help in reducing
noise generated on the board. NB the ADC performance is specified when the LVDS
outputs are used.
This SDR setup appears to
> As we are doing a similar desgin
> also using a Zynq 7010 I would appreciate if you could elaborate
> a bit what made the FPGA too small for your application.
It wasn't too small, I just had to think about just how much
filtering I was using. "It was a struggle" probably overstated the
situatio
On Sat, 28 May 2016 12:08:18 +1000
Michael Wouters wrote:
> I also have been looking at low-cost SDR hardware for T&F measurements
> and have made an RF phase meter based on the Red Pitaya. The
> performance of this was not as good as I was hoping for: the
> fractional frequency resolution of thi
On Fri, 27 May 2016 18:58:35 -0700
Hal Murray wrote:
> bruce.griffi...@xtra.co.nz said:
> > All the filtering and down mixing is done in the digital domain.
> > Anitialiasing filters in front of the ADCs are also be required.
>
> What sort of bandwidth is expected?
>
> The usual trick with aud
Bob
On Fri, 5/27/16, Bruce Griffiths wrote:
Subject: Re: [time-nuts] Commercial software defined radio for clock
metrology
To: "Discussion of precise time and frequency measurement"
Date: Friday, May 27, 2016, 10:08 PM
The Red Pitaya FPGA may
be a littl
For anyone thinking of rolling their own:
The results in the paper were achieved using an ADC pair with no input buffers.
The TI ADCs with sample rates much greater than 100MHz or so use input buffer
amps that drive sets of interleaved ADCs. The more complex clock conditioning
and distribution ci
The first version of the Red Pitaya apparently used an LTC2145 dual input 14
bit ADC with an SNR of around 72dB (11.6 bits) or so. Various claims of 10 bits
effective implies that poor layout, and/or a noisy sampling clock, and/or the
analog front end degrade the performance somewhat. For this
Hi
> On May 27, 2016, at 8:17 PM, Bruce Griffiths
> wrote:
>
> On Thursday, May 26, 2016 06:40:26 PM Bob Camp wrote:
>> Hi
>>
>> Very interesting paper, thanks for sharing !!
>>
>> One question:
>>
>> In many DMTD (and single mixer) systems, a lowpass and high pass filter are
>> applied to
The following may be of interest to those playing with low-cost SDR hardware:
I also have been looking at low-cost SDR hardware for T&F measurements
and have made an RF phase meter based on the Red Pitaya. The
performance of this was not as good as I was hoping for: the
fractional frequency resolu
The Red Pitaya FPGA may be a little too small.Its not clear if a single chip
ADC is used.If not, the performance will suffer.Dc coupled inputs will degrade
the performance somewhat compared to transformer coupled inputs.
Input bandwidth would be around 40MHz or so for the Nyquist band of
intere
This might be a good job for the Red Pitaya q.v.
Don
On 2016-05-27 18:17, Bruce Griffiths wrote:
On Thursday, May 26, 2016 06:40:26 PM Bob Camp wrote:
Hi
Very interesting paper, thanks for sharing !!
One question:
In many DMTD (and single mixer) systems, a lowpass and high pass
filter are
bruce.griffi...@xtra.co.nz said:
> All the filtering and down mixing is done in the digital domain.
> Anitialiasing filters in front of the ADCs are also be required.
What sort of bandwidth is expected?
The usual trick with audio ADCs is to have a low cost analog filter that
does't have a shar
On Thursday, May 26, 2016 06:40:26 PM Bob Camp wrote:
> Hi
>
> Very interesting paper, thanks for sharing !!
>
> One question:
>
> In many DMTD (and single mixer) systems, a lowpass and high pass filter are
> applied to the signal coming out of the mixer. This is done to improve the
> zero cross
Thx!!! André Esteves
2016-05-25 17:01 GMT+01:00 Sherman, Jeffrey A. (Fed)
:
> Hello,
>
> A recently published paper might be of interest to the time-nuts
> community. We studied how well an unmodified commercial software defined
> radio (SDR) device/firmware could serve in comparing high-perform
Hi
Very interesting paper, thanks for sharing !!
One question:
In many DMTD (and single mixer) systems, a lowpass and high pass filter are
applied to the signal coming out of the mixer.
This is done to improve the zero crossing detection. It also effectively
reduces the “pre detection” bandwi
Jeff thanks for sharing the document with time-nuts. Others with more
knowledge will comment I suspect over the next 24 hours. I did read through
the document with interest and there are some alternates to a $1K sdr as
you suggest.
However since I have had an opportunity several times to build a an
Hello,
A recently published paper might be of interest to the time-nuts community. We
studied how well an unmodified commercial software defined radio (SDR)
device/firmware could serve in comparing high-performance oscillators and
atomic clocks. Though we chose to study the USRP platform, the d
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