Re: [algogeeks] Where does OS scheduling run??
Hello, There exists differnet google groups for OS related queries. Could you please move out your discussion there. Thanks Pramod Negi On Thu, May 6, 2010 at 5:34 AM, Yalla Sridhar sridhar2...@gmail.com wrote: yea if your processor has multiple cores or is Hyper Threading support then it can execute more than 1 instruction concurrently. On Thu, May 6, 2010 at 12:10 AM, praba garan prabagara...@gmail.comwrote: Windows Task Manager Performance tab shows the presence of two processors. Will 2 instructions be executed concurrently?? With Regards, Prabagaran. On Wed, May 5, 2010 at 4:56 PM, Varun Nagpal varun.nagp...@gmail.comwrote: I guess with Virtual machines, instructions that simulate instructions of microprocessor are scheduled onto the real processor. But good question is how the scheduling of real microprocessor instructions done in a virtual machine. And the answer is again that its done on virtual processor, which essentially has all hardware components of real processor modeled in software. All sub-parts of this software representing essential hardware components, again run synchronously (in parallel) either at instruction accurate level or cycle accurate level. All new processor that are designed as of today, are first mostly are verified using simulators written in hardware description languages like VHDL/SystemVerilog/SystemC and then simulated either in software or hardware. For hardware simulation, in some cases its eventually possible to create them on FPGA's and verify before they are sent to fab lab. Its an arduous task. For example, you can get HDL code for free for SUN Open Sparc processor and can flash it on FPGA. So It doesn't really matter whether your processor is real or virtual, so you need to understand architecture principles and some digital electronics to understand at hardware(VLSI ) level Intel x86 and now x64 are the most popular architectures. Other popular architectures are ARM, MIPS, SPARC, PowerPC, etc. You should probably read the book: Computer Architecture, by hennrey Peterson On Tue, May 4, 2010 at 10:49 PM, praba garan prabagara...@gmail.com wrote: I think it is necessary to study the full architecture of INTEL MotherBoard to get a full picture. How does scheduling happen incase of Virtual Machines?? Then how does a packet coming to the Guest OS is sent to Guest OS. ie, either directly to Guest OS or through Host OS. With Regards, Prabagaran. On Mon, May 3, 2010 at 12:25 PM, Varun Nagpal varun.nagp...@gmail.com wrote: I think its a good question and fairly complicated to explain at hardware(RTL) level. Anyways, let me give it a try : You suggested that only 1 instruction is executed by one processor, which is not true(if you have read computer architecture). Briefly, lets assume the instruction pipeline(assuming only single hardware thread) is filled with instructions from the present thread(or process) of execution. Assume number of pipeline stages to be 20. In the pipeline, 20 instructions from the current instruction control flow are executing synchronously on every clock tick. Depending upon the design of pipeline, data from registers/memory is read in different pipeline stages. Also there may also be many execution stages(ALU) before the data is written to register/memory. The OS kernel keeps a track of all the threads/processes presently executing, active, waiting, suspended etc. in memory in the form of a data structure, which is to say that it always knows the next thread/process it needs to schedule on to the processor. I think it has a compare register that stores an arbitrary number(as decided by kernel) of clock ticks for a time slice expiry and keeps another counter register to keep track of time slice expiration for present thread. At every clock tick, it increments the counter register and compares it with compare register. This summing and comparison is done by inserting an instruction in the current instruction flow. The point is that a clock interrupt is generated whenever the values of the counter and the compare registers match. When this does occur, the next PC value,registers etc(i.e its context information) is pushed onto the stack and a jump is made to an area in memory storing an interrupt vector table. I also assume that when this jump is made, the OS kernel supplies some information to the jump instruction about the next thread to be executed. This information maybe stored in another dedicated register. Now by using this information and interrupt vector table, it can find out the memory address of next thread(ii.e next instruction) to be executed. The PC including other registers is then simply loaded with context information of the new thread. Important thing here is again that when all of this is happening, the pipeline may still be executing instructions from the previous
Re: [algogeeks] Where does OS scheduling run??
yea if your processor has multiple cores or is Hyper Threading support then it can execute more than 1 instruction concurrently. On Thu, May 6, 2010 at 12:10 AM, praba garan prabagara...@gmail.com wrote: Windows Task Manager Performance tab shows the presence of two processors. Will 2 instructions be executed concurrently?? With Regards, Prabagaran. On Wed, May 5, 2010 at 4:56 PM, Varun Nagpal varun.nagp...@gmail.comwrote: I guess with Virtual machines, instructions that simulate instructions of microprocessor are scheduled onto the real processor. But good question is how the scheduling of real microprocessor instructions done in a virtual machine. And the answer is again that its done on virtual processor, which essentially has all hardware components of real processor modeled in software. All sub-parts of this software representing essential hardware components, again run synchronously (in parallel) either at instruction accurate level or cycle accurate level. All new processor that are designed as of today, are first mostly are verified using simulators written in hardware description languages like VHDL/SystemVerilog/SystemC and then simulated either in software or hardware. For hardware simulation, in some cases its eventually possible to create them on FPGA's and verify before they are sent to fab lab. Its an arduous task. For example, you can get HDL code for free for SUN Open Sparc processor and can flash it on FPGA. So It doesn't really matter whether your processor is real or virtual, so you need to understand architecture principles and some digital electronics to understand at hardware(VLSI ) level Intel x86 and now x64 are the most popular architectures. Other popular architectures are ARM, MIPS, SPARC, PowerPC, etc. You should probably read the book: Computer Architecture, by hennrey Peterson On Tue, May 4, 2010 at 10:49 PM, praba garan prabagara...@gmail.com wrote: I think it is necessary to study the full architecture of INTEL MotherBoard to get a full picture. How does scheduling happen incase of Virtual Machines?? Then how does a packet coming to the Guest OS is sent to Guest OS. ie, either directly to Guest OS or through Host OS. With Regards, Prabagaran. On Mon, May 3, 2010 at 12:25 PM, Varun Nagpal varun.nagp...@gmail.com wrote: I think its a good question and fairly complicated to explain at hardware(RTL) level. Anyways, let me give it a try : You suggested that only 1 instruction is executed by one processor, which is not true(if you have read computer architecture). Briefly, lets assume the instruction pipeline(assuming only single hardware thread) is filled with instructions from the present thread(or process) of execution. Assume number of pipeline stages to be 20. In the pipeline, 20 instructions from the current instruction control flow are executing synchronously on every clock tick. Depending upon the design of pipeline, data from registers/memory is read in different pipeline stages. Also there may also be many execution stages(ALU) before the data is written to register/memory. The OS kernel keeps a track of all the threads/processes presently executing, active, waiting, suspended etc. in memory in the form of a data structure, which is to say that it always knows the next thread/process it needs to schedule on to the processor. I think it has a compare register that stores an arbitrary number(as decided by kernel) of clock ticks for a time slice expiry and keeps another counter register to keep track of time slice expiration for present thread. At every clock tick, it increments the counter register and compares it with compare register. This summing and comparison is done by inserting an instruction in the current instruction flow. The point is that a clock interrupt is generated whenever the values of the counter and the compare registers match. When this does occur, the next PC value,registers etc(i.e its context information) is pushed onto the stack and a jump is made to an area in memory storing an interrupt vector table. I also assume that when this jump is made, the OS kernel supplies some information to the jump instruction about the next thread to be executed. This information maybe stored in another dedicated register. Now by using this information and interrupt vector table, it can find out the memory address of next thread(ii.e next instruction) to be executed. The PC including other registers is then simply loaded with context information of the new thread. Important thing here is again that when all of this is happening, the pipeline may still be executing instructions from the previous thread. In addition it will contain interrupt instructions! Only when PC is updated(in some stage of pipeline) that the instruction fetch stage will start fetching instructions from instruction memory area of new thread. In
Re: [algogeeks] Where does OS scheduling run??
I guess with Virtual machines, instructions that simulate instructions of microprocessor are scheduled onto the real processor. But good question is how the scheduling of real microprocessor instructions done in a virtual machine. And the answer is again that its done on virtual processor, which essentially has all hardware components of real processor modeled in software. All sub-parts of this software representing essential hardware components, again run synchronously (in parallel) either at instruction accurate level or cycle accurate level. All new processor that are designed as of today, are first mostly are verified using simulators written in hardware description languages like VHDL/SystemVerilog/SystemC and then simulated either in software or hardware. For hardware simulation, in some cases its eventually possible to create them on FPGA's and verify before they are sent to fab lab. Its an arduous task. For example, you can get HDL code for free for SUN Open Sparc processor and can flash it on FPGA. So It doesn't really matter whether your processor is real or virtual, so you need to understand architecture principles and some digital electronics to understand at hardware(VLSI ) level Intel x86 and now x64 are the most popular architectures. Other popular architectures are ARM, MIPS, SPARC, PowerPC, etc. You should probably read the book: Computer Architecture, by hennrey Peterson On Tue, May 4, 2010 at 10:49 PM, praba garan prabagara...@gmail.com wrote: I think it is necessary to study the full architecture of INTEL MotherBoard to get a full picture. How does scheduling happen incase of Virtual Machines?? Then how does a packet coming to the Guest OS is sent to Guest OS. ie, either directly to Guest OS or through Host OS. With Regards, Prabagaran. On Mon, May 3, 2010 at 12:25 PM, Varun Nagpal varun.nagp...@gmail.com wrote: I think its a good question and fairly complicated to explain at hardware(RTL) level. Anyways, let me give it a try : You suggested that only 1 instruction is executed by one processor, which is not true(if you have read computer architecture). Briefly, lets assume the instruction pipeline(assuming only single hardware thread) is filled with instructions from the present thread(or process) of execution. Assume number of pipeline stages to be 20. In the pipeline, 20 instructions from the current instruction control flow are executing synchronously on every clock tick. Depending upon the design of pipeline, data from registers/memory is read in different pipeline stages. Also there may also be many execution stages(ALU) before the data is written to register/memory. The OS kernel keeps a track of all the threads/processes presently executing, active, waiting, suspended etc. in memory in the form of a data structure, which is to say that it always knows the next thread/process it needs to schedule on to the processor. I think it has a compare register that stores an arbitrary number(as decided by kernel) of clock ticks for a time slice expiry and keeps another counter register to keep track of time slice expiration for present thread. At every clock tick, it increments the counter register and compares it with compare register. This summing and comparison is done by inserting an instruction in the current instruction flow. The point is that a clock interrupt is generated whenever the values of the counter and the compare registers match. When this does occur, the next PC value,registers etc(i.e its context information) is pushed onto the stack and a jump is made to an area in memory storing an interrupt vector table. I also assume that when this jump is made, the OS kernel supplies some information to the jump instruction about the next thread to be executed. This information maybe stored in another dedicated register. Now by using this information and interrupt vector table, it can find out the memory address of next thread(ii.e next instruction) to be executed. The PC including other registers is then simply loaded with context information of the new thread. Important thing here is again that when all of this is happening, the pipeline may still be executing instructions from the previous thread. In addition it will contain interrupt instructions! Only when PC is updated(in some stage of pipeline) that the instruction fetch stage will start fetching instructions from instruction memory area of new thread. In a 20 stage pipeline, it is still highly likely that it may be the case that pipeline contains instructions from old thread, followed by interrupt instruction , followed by instructions from new thread. I hope this explanation should give you better clarity. On Sun, May 2, 2010 at 7:01 PM, harit agarwal agarwalha...@gmail.com wrote: although CPU is busy in exexcution...it check's its registers values for the pending interrupts .. if any interrupt is pending at the end of the current CPU cycle...it
Re: [algogeeks] Where does OS scheduling run??
Windows Task Manager Performance tab shows the presence of two processors. Will 2 instructions be executed concurrently?? With Regards, Prabagaran. On Wed, May 5, 2010 at 4:56 PM, Varun Nagpal varun.nagp...@gmail.comwrote: I guess with Virtual machines, instructions that simulate instructions of microprocessor are scheduled onto the real processor. But good question is how the scheduling of real microprocessor instructions done in a virtual machine. And the answer is again that its done on virtual processor, which essentially has all hardware components of real processor modeled in software. All sub-parts of this software representing essential hardware components, again run synchronously (in parallel) either at instruction accurate level or cycle accurate level. All new processor that are designed as of today, are first mostly are verified using simulators written in hardware description languages like VHDL/SystemVerilog/SystemC and then simulated either in software or hardware. For hardware simulation, in some cases its eventually possible to create them on FPGA's and verify before they are sent to fab lab. Its an arduous task. For example, you can get HDL code for free for SUN Open Sparc processor and can flash it on FPGA. So It doesn't really matter whether your processor is real or virtual, so you need to understand architecture principles and some digital electronics to understand at hardware(VLSI ) level Intel x86 and now x64 are the most popular architectures. Other popular architectures are ARM, MIPS, SPARC, PowerPC, etc. You should probably read the book: Computer Architecture, by hennrey Peterson On Tue, May 4, 2010 at 10:49 PM, praba garan prabagara...@gmail.com wrote: I think it is necessary to study the full architecture of INTEL MotherBoard to get a full picture. How does scheduling happen incase of Virtual Machines?? Then how does a packet coming to the Guest OS is sent to Guest OS. ie, either directly to Guest OS or through Host OS. With Regards, Prabagaran. On Mon, May 3, 2010 at 12:25 PM, Varun Nagpal varun.nagp...@gmail.com wrote: I think its a good question and fairly complicated to explain at hardware(RTL) level. Anyways, let me give it a try : You suggested that only 1 instruction is executed by one processor, which is not true(if you have read computer architecture). Briefly, lets assume the instruction pipeline(assuming only single hardware thread) is filled with instructions from the present thread(or process) of execution. Assume number of pipeline stages to be 20. In the pipeline, 20 instructions from the current instruction control flow are executing synchronously on every clock tick. Depending upon the design of pipeline, data from registers/memory is read in different pipeline stages. Also there may also be many execution stages(ALU) before the data is written to register/memory. The OS kernel keeps a track of all the threads/processes presently executing, active, waiting, suspended etc. in memory in the form of a data structure, which is to say that it always knows the next thread/process it needs to schedule on to the processor. I think it has a compare register that stores an arbitrary number(as decided by kernel) of clock ticks for a time slice expiry and keeps another counter register to keep track of time slice expiration for present thread. At every clock tick, it increments the counter register and compares it with compare register. This summing and comparison is done by inserting an instruction in the current instruction flow. The point is that a clock interrupt is generated whenever the values of the counter and the compare registers match. When this does occur, the next PC value,registers etc(i.e its context information) is pushed onto the stack and a jump is made to an area in memory storing an interrupt vector table. I also assume that when this jump is made, the OS kernel supplies some information to the jump instruction about the next thread to be executed. This information maybe stored in another dedicated register. Now by using this information and interrupt vector table, it can find out the memory address of next thread(ii.e next instruction) to be executed. The PC including other registers is then simply loaded with context information of the new thread. Important thing here is again that when all of this is happening, the pipeline may still be executing instructions from the previous thread. In addition it will contain interrupt instructions! Only when PC is updated(in some stage of pipeline) that the instruction fetch stage will start fetching instructions from instruction memory area of new thread. In a 20 stage pipeline, it is still highly likely that it may be the case that pipeline contains instructions from old thread, followed by interrupt instruction , followed by instructions from new thread.
Re: [algogeeks] Where does OS scheduling run??
I think it is necessary to study the full architecture of INTEL MotherBoard to get a full picture. How does scheduling happen incase of Virtual Machines?? Then how does a packet coming to the Guest OS is sent to Guest OS. ie, either directly to Guest OS or through Host OS. With Regards, Prabagaran. On Mon, May 3, 2010 at 12:25 PM, Varun Nagpal varun.nagp...@gmail.comwrote: I think its a good question and fairly complicated to explain at hardware(RTL) level. Anyways, let me give it a try : You suggested that only 1 instruction is executed by one processor, which is not true(if you have read computer architecture). Briefly, lets assume the instruction pipeline(assuming only single hardware thread) is filled with instructions from the present thread(or process) of execution. Assume number of pipeline stages to be 20. In the pipeline, 20 instructions from the current instruction control flow are executing synchronously on every clock tick. Depending upon the design of pipeline, data from registers/memory is read in different pipeline stages. Also there may also be many execution stages(ALU) before the data is written to register/memory. The OS kernel keeps a track of all the threads/processes presently executing, active, waiting, suspended etc. in memory in the form of a data structure, which is to say that it always knows the next thread/process it needs to schedule on to the processor. I think it has a compare register that stores an arbitrary number(as decided by kernel) of clock ticks for a time slice expiry and keeps another counter register to keep track of time slice expiration for present thread. At every clock tick, it increments the counter register and compares it with compare register. This summing and comparison is done by inserting an instruction in the current instruction flow. The point is that a clock interrupt is generated whenever the values of the counter and the compare registers match. When this does occur, the next PC value,registers etc(i.e its context information) is pushed onto the stack and a jump is made to an area in memory storing an interrupt vector table. I also assume that when this jump is made, the OS kernel supplies some information to the jump instruction about the next thread to be executed. This information maybe stored in another dedicated register. Now by using this information and interrupt vector table, it can find out the memory address of next thread(ii.e next instruction) to be executed. The PC including other registers is then simply loaded with context information of the new thread. Important thing here is again that when all of this is happening, the pipeline may still be executing instructions from the previous thread. In addition it will contain interrupt instructions! Only when PC is updated(in some stage of pipeline) that the instruction fetch stage will start fetching instructions from instruction memory area of new thread. In a 20 stage pipeline, it is still highly likely that it may be the case that pipeline contains instructions from old thread, followed by interrupt instruction , followed by instructions from new thread. I hope this explanation should give you better clarity. On Sun, May 2, 2010 at 7:01 PM, harit agarwal agarwalha...@gmail.com wrote: although CPU is busy in exexcution...it check's its registers values for the pending interrupts .. if any interrupt is pending at the end of the current CPU cycle...it shedules the interrupt handler to further execute the interrupt subroutine... -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.com. For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en.
Re: [algogeeks] Where does OS scheduling run??
I think its a good question and fairly complicated to explain at hardware(RTL) level. Anyways, let me give it a try : You suggested that only 1 instruction is executed by one processor, which is not true(if you have read computer architecture). Briefly, lets assume the instruction pipeline(assuming only single hardware thread) is filled with instructions from the present thread(or process) of execution. Assume number of pipeline stages to be 20. In the pipeline, 20 instructions from the current instruction control flow are executing synchronously on every clock tick. Depending upon the design of pipeline, data from registers/memory is read in different pipeline stages. Also there may also be many execution stages(ALU) before the data is written to register/memory. The OS kernel keeps a track of all the threads/processes presently executing, active, waiting, suspended etc. in memory in the form of a data structure, which is to say that it always knows the next thread/process it needs to schedule on to the processor. I think it has a compare register that stores an arbitrary number(as decided by kernel) of clock ticks for a time slice expiry and keeps another counter register to keep track of time slice expiration for present thread. At every clock tick, it increments the counter register and compares it with compare register. This summing and comparison is done by inserting an instruction in the current instruction flow. The point is that a clock interrupt is generated whenever the values of the counter and the compare registers match. When this does occur, the next PC value,registers etc(i.e its context information) is pushed onto the stack and a jump is made to an area in memory storing an interrupt vector table. I also assume that when this jump is made, the OS kernel supplies some information to the jump instruction about the next thread to be executed. This information maybe stored in another dedicated register. Now by using this information and interrupt vector table, it can find out the memory address of next thread(ii.e next instruction) to be executed. The PC including other registers is then simply loaded with context information of the new thread. Important thing here is again that when all of this is happening, the pipeline may still be executing instructions from the previous thread. In addition it will contain interrupt instructions! Only when PC is updated(in some stage of pipeline) that the instruction fetch stage will start fetching instructions from instruction memory area of new thread. In a 20 stage pipeline, it is still highly likely that it may be the case that pipeline contains instructions from old thread, followed by interrupt instruction , followed by instructions from new thread. I hope this explanation should give you better clarity. On Sun, May 2, 2010 at 7:01 PM, harit agarwal agarwalha...@gmail.com wrote: although CPU is busy in exexcution...it check's its registers values for the pending interrupts .. if any interrupt is pending at the end of the current CPU cycle...it shedules the interrupt handler to further execute the interrupt subroutine... -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.com. For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.com. For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en.
Re: [algogeeks] Where does OS scheduling run??
@ Pradeep *CPU stop its current processing and goes to the interrupt subroutine* you have mentioned that the CPU stops its current processing and goes to the interrupt subroutine.. My Question is how does the CPU stops its execution(any special hardware involved) because it is busy in executing the current instruction. With Regards, Prabagaran. On Sun, May 2, 2010 at 4:02 AM, pradeep verma ppradeep...@gmail.com wrote: lets suppose Processor executing a instruction(process1) and another process2 tries to take the control of CPU so inorder to inform CPU it has to interrupt the CPU right now we know that if interrupt comes CPU stop its current processing and goes to the interrupt subroutine...now CPU knows that its a pre-emption interrupt so CPU first run its short term scheduler(this will inform CPU that the interruting process priority is less or greater ..n if greater than CPU goes to previous process1 preempt it and start executing higher priority process2 ) I think its clear Regards Pradeep On Sun, May 2, 2010 at 3:06 AM, praba garan prabagara...@gmail.comwrote: @ Guillermo Garcia The link gives the overall abstract idea. I am talking in register level. When a user process executes 1. PC program counter will contain the address of the next instruction in user code. 2. Processor registers(accumulator ...) contain the current instruction data. Then where does the interrupt actually arrives?? And by that time the user process the control, then who does the preempting and how?? With Regards, Prabagaran. On Sun, May 2, 2010 at 2:35 AM, Guillermo Garcia gegarci...@gmail.comwrote: read here - http://en.wikipedia.org/wiki/Preemption_%28computing%29 Time slice The period of time for which a process is allowed to run in a preemptive multitasking system is generally called the *time slice*, or *quantum*. The scheduler is run once every time slice to choose the next process to run. If the time slice is too short then the scheduler will consume too much processing time. An interrupt http://en.wikipedia.org/wiki/Interrupt is scheduled to allow the operating systemhttp://en.wikipedia.org/wiki/Operating_system kernel http://en.wikipedia.org/wiki/Kernel_%28computer_science%29 to switch between processes when their time slices expire, effectively allowing the processor’s time to be shared between a number of tasks, giving the illusion that it is dealing with these tasks simultaneously, or concurrently. The operating system which controls such a design is called a multi-tasking system. On Sat, May 1, 2010 at 5:26 PM, praba garan prabagara...@gmail.comwrote: @ Guillermo Garcia Suppose a user program is executing and and clock interrupt arrives.. Then who receives the interrupt?? Can you xplain me the clock interrupt(like any hardwares involved) bit detailed?? With Regards, Prabagaran. On Sun, May 2, 2010 at 1:38 AM, Guillermo Garcia gegarci...@gmail.comwrote: The scheduler takes control with a clock interruption. Then it analyzes if it has to preempt or not the running task. On Sat, May 1, 2010 at 5:00 PM, praba garan prabagara...@gmail.comwrote: Hi all, I have a doubt in OS. The scheduler does the process of preemption. And one processor can run atmost 1 instruction at a time. Then how where does the scheduler run?? With Regards, Prabagaran. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message
Re: [algogeeks] Where does OS scheduling run??
@Prabagaran Execution of an instruction, by the CPU, is an ATOMIC operation. Interrupts, if any, will be processed after the execution of the current instruction. CPU has interrupt pins attached to it. Whenever an interrupt occurs, the CPU will be informed about the interrupt through these hardwired pins. That's how the CPU will get to know the occurrence of an interrupt. For now, please assume that somehow, these pins will be set to the corresponding values, if any interrupt occurs. Please refer to the Intel's Manual for further details on Interrupt Handling. Now, when a timer interrupt occurs, the kernel will get to know that the time quantum assigned to the current process has expired and then it loads the next waiting process to execute on the CPU. Hope this helps. -- CM Saikanth Varma On Sun, May 2, 2010 at 10:25 PM, praba garan prabagara...@gmail.com wrote: @ Pradeep *CPU stop its current processing and goes to the interrupt subroutine* you have mentioned that the CPU stops its current processing and goes to the interrupt subroutine.. My Question is how does the CPU stops its execution(any special hardware involved) because it is busy in executing the current instruction. With Regards, Prabagaran. On Sun, May 2, 2010 at 4:02 AM, pradeep verma ppradeep...@gmail.comwrote: lets suppose Processor executing a instruction(process1) and another process2 tries to take the control of CPU so inorder to inform CPU it has to interrupt the CPU right now we know that if interrupt comes CPU stop its current processing and goes to the interrupt subroutine...now CPU knows that its a pre-emption interrupt so CPU first run its short term scheduler(this will inform CPU that the interruting process priority is less or greater ..n if greater than CPU goes to previous process1 preempt it and start executing higher priority process2 ) I think its clear Regards Pradeep On Sun, May 2, 2010 at 3:06 AM, praba garan prabagara...@gmail.comwrote: @ Guillermo Garcia The link gives the overall abstract idea. I am talking in register level. When a user process executes 1. PC program counter will contain the address of the next instruction in user code. 2. Processor registers(accumulator ...) contain the current instruction data. Then where does the interrupt actually arrives?? And by that time the user process the control, then who does the preempting and how?? With Regards, Prabagaran. On Sun, May 2, 2010 at 2:35 AM, Guillermo Garcia gegarci...@gmail.comwrote: read here - http://en.wikipedia.org/wiki/Preemption_%28computing%29 Time slice The period of time for which a process is allowed to run in a preemptive multitasking system is generally called the *time slice*, or *quantum*. The scheduler is run once every time slice to choose the next process to run. If the time slice is too short then the scheduler will consume too much processing time. An interrupt http://en.wikipedia.org/wiki/Interrupt is scheduled to allow the operating systemhttp://en.wikipedia.org/wiki/Operating_system kernel http://en.wikipedia.org/wiki/Kernel_%28computer_science%29 to switch between processes when their time slices expire, effectively allowing the processor’s time to be shared between a number of tasks, giving the illusion that it is dealing with these tasks simultaneously, or concurrently. The operating system which controls such a design is called a multi-tasking system. On Sat, May 1, 2010 at 5:26 PM, praba garan prabagara...@gmail.comwrote: @ Guillermo Garcia Suppose a user program is executing and and clock interrupt arrives.. Then who receives the interrupt?? Can you xplain me the clock interrupt(like any hardwares involved) bit detailed?? With Regards, Prabagaran. On Sun, May 2, 2010 at 1:38 AM, Guillermo Garcia gegarci...@gmail.com wrote: The scheduler takes control with a clock interruption. Then it analyzes if it has to preempt or not the running task. On Sat, May 1, 2010 at 5:00 PM, praba garan prabagara...@gmail.comwrote: Hi all, I have a doubt in OS. The scheduler does the process of preemption. And one processor can run atmost 1 instruction at a time. Then how where does the scheduler run?? With Regards, Prabagaran. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For
Re: [algogeeks] Where does OS scheduling run??
we know that there are many pins available in microprocessor chips one of them is INTR(interrupt Req) When a CPU receives an Interrupt Request (IRQ), it first checks if it must react to the interrupt. So-called Maskable Interrupts allow a programmer to specify that the CPU does ignore it, while Non-Maskeable Interrupt requests must be serviced. now if a process wants a control of CPU it sends a positive signal on INTR pin this will interrupt CPU n this is how CPU is being interrupted. after that CPU stops its current processing I think now its clear Regards Pradeep On Sun, May 2, 2010 at 10:25 PM, praba garan prabagara...@gmail.com wrote: @ Pradeep *CPU stop its current processing and goes to the interrupt subroutine* you have mentioned that the CPU stops its current processing and goes to the interrupt subroutine.. My Question is how does the CPU stops its execution(any special hardware involved) because it is busy in executing the current instruction. With Regards, Prabagaran. On Sun, May 2, 2010 at 4:02 AM, pradeep verma ppradeep...@gmail.comwrote: lets suppose Processor executing a instruction(process1) and another process2 tries to take the control of CPU so inorder to inform CPU it has to interrupt the CPU right now we know that if interrupt comes CPU stop its current processing and goes to the interrupt subroutine...now CPU knows that its a pre-emption interrupt so CPU first run its short term scheduler(this will inform CPU that the interruting process priority is less or greater ..n if greater than CPU goes to previous process1 preempt it and start executing higher priority process2 ) I think its clear Regards Pradeep On Sun, May 2, 2010 at 3:06 AM, praba garan prabagara...@gmail.comwrote: @ Guillermo Garcia The link gives the overall abstract idea. I am talking in register level. When a user process executes 1. PC program counter will contain the address of the next instruction in user code. 2. Processor registers(accumulator ...) contain the current instruction data. Then where does the interrupt actually arrives?? And by that time the user process the control, then who does the preempting and how?? With Regards, Prabagaran. On Sun, May 2, 2010 at 2:35 AM, Guillermo Garcia gegarci...@gmail.comwrote: read here - http://en.wikipedia.org/wiki/Preemption_%28computing%29 Time slice The period of time for which a process is allowed to run in a preemptive multitasking system is generally called the *time slice*, or *quantum*. The scheduler is run once every time slice to choose the next process to run. If the time slice is too short then the scheduler will consume too much processing time. An interrupt http://en.wikipedia.org/wiki/Interrupt is scheduled to allow the operating systemhttp://en.wikipedia.org/wiki/Operating_system kernel http://en.wikipedia.org/wiki/Kernel_%28computer_science%29 to switch between processes when their time slices expire, effectively allowing the processor’s time to be shared between a number of tasks, giving the illusion that it is dealing with these tasks simultaneously, or concurrently. The operating system which controls such a design is called a multi-tasking system. On Sat, May 1, 2010 at 5:26 PM, praba garan prabagara...@gmail.comwrote: @ Guillermo Garcia Suppose a user program is executing and and clock interrupt arrives.. Then who receives the interrupt?? Can you xplain me the clock interrupt(like any hardwares involved) bit detailed?? With Regards, Prabagaran. On Sun, May 2, 2010 at 1:38 AM, Guillermo Garcia gegarci...@gmail.com wrote: The scheduler takes control with a clock interruption. Then it analyzes if it has to preempt or not the running task. On Sat, May 1, 2010 at 5:00 PM, praba garan prabagara...@gmail.comwrote: Hi all, I have a doubt in OS. The scheduler does the process of preemption. And one processor can run atmost 1 instruction at a time. Then how where does the scheduler run?? With Regards, Prabagaran. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send
Re: [algogeeks] Where does OS scheduling run??
although CPU is busy in exexcution...it check's its registers values for the pending interrupts .. if any interrupt is pending at the end of the current CPU cycle...it shedules the interrupt handler to further execute the interrupt subroutine... -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.com. For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en.
[algogeeks] Where does OS scheduling run??
Hi all, I have a doubt in OS. The scheduler does the process of preemption. And one processor can run atmost 1 instruction at a time. Then how where does the scheduler run?? With Regards, Prabagaran. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.com. For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en.
Re: [algogeeks] Where does OS scheduling run??
The scheduler takes control with a clock interruption. Then it analyzes if it has to preempt or not the running task. On Sat, May 1, 2010 at 5:00 PM, praba garan prabagara...@gmail.com wrote: Hi all, I have a doubt in OS. The scheduler does the process of preemption. And one processor can run atmost 1 instruction at a time. Then how where does the scheduler run?? With Regards, Prabagaran. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.com. For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en.
Re: [algogeeks] Where does OS scheduling run??
read here - http://en.wikipedia.org/wiki/Preemption_%28computing%29 Time slice The period of time for which a process is allowed to run in a preemptive multitasking system is generally called the *time slice*, or *quantum*. The scheduler is run once every time slice to choose the next process to run. If the time slice is too short then the scheduler will consume too much processing time. An interrupt http://en.wikipedia.org/wiki/Interrupt is scheduled to allow the operating system http://en.wikipedia.org/wiki/Operating_system kernelhttp://en.wikipedia.org/wiki/Kernel_%28computer_science%29to switch between processes when their time slices expire, effectively allowing the processor’s time to be shared between a number of tasks, giving the illusion that it is dealing with these tasks simultaneously, or concurrently. The operating system which controls such a design is called a multi-tasking system. On Sat, May 1, 2010 at 5:26 PM, praba garan prabagara...@gmail.com wrote: @ Guillermo Garcia Suppose a user program is executing and and clock interrupt arrives.. Then who receives the interrupt?? Can you xplain me the clock interrupt(like any hardwares involved) bit detailed?? With Regards, Prabagaran. On Sun, May 2, 2010 at 1:38 AM, Guillermo Garcia gegarci...@gmail.comwrote: The scheduler takes control with a clock interruption. Then it analyzes if it has to preempt or not the running task. On Sat, May 1, 2010 at 5:00 PM, praba garan prabagara...@gmail.comwrote: Hi all, I have a doubt in OS. The scheduler does the process of preemption. And one processor can run atmost 1 instruction at a time. Then how where does the scheduler run?? With Regards, Prabagaran. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.com. For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en.
Re: [algogeeks] Where does OS scheduling run??
@ Guillermo Garcia The link gives the overall abstract idea. I am talking in register level. When a user process executes 1. PC program counter will contain the address of the next instruction in user code. 2. Processor registers(accumulator ...) contain the current instruction data. Then where does the interrupt actually arrives?? And by that time the user process the control, then who does the preempting and how?? With Regards, Prabagaran. On Sun, May 2, 2010 at 2:35 AM, Guillermo Garcia gegarci...@gmail.comwrote: read here - http://en.wikipedia.org/wiki/Preemption_%28computing%29 Time slice The period of time for which a process is allowed to run in a preemptive multitasking system is generally called the *time slice*, or *quantum*. The scheduler is run once every time slice to choose the next process to run. If the time slice is too short then the scheduler will consume too much processing time. An interrupt http://en.wikipedia.org/wiki/Interrupt is scheduled to allow the operating system http://en.wikipedia.org/wiki/Operating_system kernel http://en.wikipedia.org/wiki/Kernel_%28computer_science%29 to switch between processes when their time slices expire, effectively allowing the processor’s time to be shared between a number of tasks, giving the illusion that it is dealing with these tasks simultaneously, or concurrently. The operating system which controls such a design is called a multi-tasking system. On Sat, May 1, 2010 at 5:26 PM, praba garan prabagara...@gmail.comwrote: @ Guillermo Garcia Suppose a user program is executing and and clock interrupt arrives.. Then who receives the interrupt?? Can you xplain me the clock interrupt(like any hardwares involved) bit detailed?? With Regards, Prabagaran. On Sun, May 2, 2010 at 1:38 AM, Guillermo Garcia gegarci...@gmail.comwrote: The scheduler takes control with a clock interruption. Then it analyzes if it has to preempt or not the running task. On Sat, May 1, 2010 at 5:00 PM, praba garan prabagara...@gmail.comwrote: Hi all, I have a doubt in OS. The scheduler does the process of preemption. And one processor can run atmost 1 instruction at a time. Then how where does the scheduler run?? With Regards, Prabagaran. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.com. For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en.
Re: [algogeeks] Where does OS scheduling run??
lets suppose Processor executing a instruction(process1) and another process2 tries to take the control of CPU so inorder to inform CPU it has to interrupt the CPU right now we know that if interrupt comes CPU stop its current processing and goes to the interrupt subroutine...now CPU knows that its a pre-emption interrupt so CPU first run its short term scheduler(this will inform CPU that the interruting process priority is less or greater ..n if greater than CPU goes to previous process1 preempt it and start executing higher priority process2 ) I think its clear Regards Pradeep On Sun, May 2, 2010 at 3:06 AM, praba garan prabagara...@gmail.com wrote: @ Guillermo Garcia The link gives the overall abstract idea. I am talking in register level. When a user process executes 1. PC program counter will contain the address of the next instruction in user code. 2. Processor registers(accumulator ...) contain the current instruction data. Then where does the interrupt actually arrives?? And by that time the user process the control, then who does the preempting and how?? With Regards, Prabagaran. On Sun, May 2, 2010 at 2:35 AM, Guillermo Garcia gegarci...@gmail.comwrote: read here - http://en.wikipedia.org/wiki/Preemption_%28computing%29 Time slice The period of time for which a process is allowed to run in a preemptive multitasking system is generally called the *time slice*, or *quantum*. The scheduler is run once every time slice to choose the next process to run. If the time slice is too short then the scheduler will consume too much processing time. An interrupt http://en.wikipedia.org/wiki/Interrupt is scheduled to allow the operating systemhttp://en.wikipedia.org/wiki/Operating_system kernel http://en.wikipedia.org/wiki/Kernel_%28computer_science%29 to switch between processes when their time slices expire, effectively allowing the processor’s time to be shared between a number of tasks, giving the illusion that it is dealing with these tasks simultaneously, or concurrently. The operating system which controls such a design is called a multi-tasking system. On Sat, May 1, 2010 at 5:26 PM, praba garan prabagara...@gmail.comwrote: @ Guillermo Garcia Suppose a user program is executing and and clock interrupt arrives.. Then who receives the interrupt?? Can you xplain me the clock interrupt(like any hardwares involved) bit detailed?? With Regards, Prabagaran. On Sun, May 2, 2010 at 1:38 AM, Guillermo Garcia gegarci...@gmail.comwrote: The scheduler takes control with a clock interruption. Then it analyzes if it has to preempt or not the running task. On Sat, May 1, 2010 at 5:00 PM, praba garan prabagara...@gmail.comwrote: Hi all, I have a doubt in OS. The scheduler does the process of preemption. And one processor can run atmost 1 instruction at a time. Then how where does the scheduler run?? With Regards, Prabagaran. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm
Re: [algogeeks] Where does OS scheduling run??
correct, and in each process switch, the process state (registers, etc. ) is stored so when the scheduler wants to go back to execute such process, it restores it to the state exactly before its execution was interrupted On Sat, May 1, 2010 at 7:32 PM, pradeep verma ppradeep...@gmail.com wrote: lets suppose Processor executing a instruction(process1) and another process2 tries to take the control of CPU so inorder to inform CPU it has to interrupt the CPU right now we know that if interrupt comes CPU stop its current processing and goes to the interrupt subroutine...now CPU knows that its a pre-emption interrupt so CPU first run its short term scheduler(this will inform CPU that the interruting process priority is less or greater ..n if greater than CPU goes to previous process1 preempt it and start executing higher priority process2 ) I think its clear Regards Pradeep On Sun, May 2, 2010 at 3:06 AM, praba garan prabagara...@gmail.comwrote: @ Guillermo Garcia The link gives the overall abstract idea. I am talking in register level. When a user process executes 1. PC program counter will contain the address of the next instruction in user code. 2. Processor registers(accumulator ...) contain the current instruction data. Then where does the interrupt actually arrives?? And by that time the user process the control, then who does the preempting and how?? With Regards, Prabagaran. On Sun, May 2, 2010 at 2:35 AM, Guillermo Garcia gegarci...@gmail.comwrote: read here - http://en.wikipedia.org/wiki/Preemption_%28computing%29 Time slice The period of time for which a process is allowed to run in a preemptive multitasking system is generally called the *time slice*, or *quantum*. The scheduler is run once every time slice to choose the next process to run. If the time slice is too short then the scheduler will consume too much processing time. An interrupt http://en.wikipedia.org/wiki/Interrupt is scheduled to allow the operating systemhttp://en.wikipedia.org/wiki/Operating_system kernel http://en.wikipedia.org/wiki/Kernel_%28computer_science%29 to switch between processes when their time slices expire, effectively allowing the processor’s time to be shared between a number of tasks, giving the illusion that it is dealing with these tasks simultaneously, or concurrently. The operating system which controls such a design is called a multi-tasking system. On Sat, May 1, 2010 at 5:26 PM, praba garan prabagara...@gmail.comwrote: @ Guillermo Garcia Suppose a user program is executing and and clock interrupt arrives.. Then who receives the interrupt?? Can you xplain me the clock interrupt(like any hardwares involved) bit detailed?? With Regards, Prabagaran. On Sun, May 2, 2010 at 1:38 AM, Guillermo Garcia gegarci...@gmail.comwrote: The scheduler takes control with a clock interruption. Then it analyzes if it has to preempt or not the running task. On Sat, May 1, 2010 at 5:00 PM, praba garan prabagara...@gmail.comwrote: Hi all, I have a doubt in OS. The scheduler does the process of preemption. And one processor can run atmost 1 instruction at a time. Then how where does the scheduler run?? With Regards, Prabagaran. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com. To unsubscribe from this group, send email to algogeeks+unsubscr...@googlegroups.comalgogeeks%2bunsubscr...@googlegroups.com . For more options, visit this group at http://groups.google.com/group/algogeeks?hl=en. -- You received this message because you are subscribed to the Google Groups Algorithm Geeks group. To post to this group, send email to algoge...@googlegroups.com.
