date:20170320

Re: [PATCH 000/100] Add Vega10 Support

2017-03-20 Thread Christian König

Am 21.03.2017 um 00:38 schrieb Tom St Denis:

On 03/20/2017 06:34 PM, Jan Ziak wrote:

On Mon, Mar 20, 2017 at 10:41 PM, Alex Deucher mailto:alexdeuc...@gmail.com>> wrote:

On Mon, Mar 20, 2017 at 5:36 PM, Jan Ziak <0xe2.0x9a.0...@gmail.com
> wrote:
> Hi
>
> 
https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2

>
> The file nbio_6_1_sh_mask.h is uncompressed. It consists from 
133884 lines.
> Only generated C/C++ code will be able to utilize the content 
of such a file
> efficiently. All hand-written codes combined will be able to 
utilize about

> 1% of the file.
>
> Is there a reason why nbio_6_1_sh_mask.h is huge?

That IP block contains a lot of registers.  The idea is to open 
source

as much IP as possible to facilitate debugging, new features, etc.

Alex

[This email contains long/wide lines and should be viewed on a
sufficiently wide screen]

For example if I open the file in vim and go to line 66952:

#define 
DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT

0x9

Then abstracting away some of the digits used in the defined identifier
and using egrep:

$ egrep
"\" 

nbio_6_1_sh_mask.h
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT 

   0x9

The egrep command produced 20 lines.

Instead of the many #define directives, it is a possibility to define
functions such as:

int
DWC_E12MP_PHY_Xa_NS_Xb_c_LANEd_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_e__DTB_SEL__SHIFT(int 

a, int b, int c, int d, int e) __attribute__((pure));

I suppose the file nbio_6_1_sh_mask.h is the output of a tool (it is a
generated file). It is an option to modify the tool to output C
functions with proper input guards instead of #define directives.

The registers are generated by the HW team and then filtered down to 
become what we release publicly.  It is machine generated very likely 
from the RTL that specifies the hardware itself.

Yes, exactly that. And it was actually quite some work to get to this point.

Generally speaking if a class of registers share masks/offsets the 
lowest (zero'th) is used in programming and offsets are used when 
selecting the correct MMIO address to use specific instances.

The problem is that the files we get from the HW team describe the 
register block already broken down to the memory mappings. E.g. when an 
RTL block is instantiated N t

[PATCH] drm/amdgpu: load mc firware in driver for Polaris.

2017-03-20 Thread Rex Zhu

load mc ucode in driver if VBIOS not loaded
a full version of MC ucode,

Change-Id: I2aea697155f6b3916dc304a6bf198c3f8417bda5
Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 84 +--
 1 file changed, 81 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 5fcb64e..c9a5c31 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -253,14 +253,14 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device 
*adev)
 }
 
 /**
- * gmc_v8_0_mc_load_microcode - load MC ucode into the hw
+ * gmc_v8_0_mc_load_microcode - load tong MC ucode into the hw
  *
  * @adev: amdgpu_device pointer
  *
  * Load the GDDR MC ucode into the hw (CIK).
  * Returns 0 on success, error on failure.
  */
-static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev)
+static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
 {
const struct mc_firmware_header_v1_0 *hdr;
const __le32 *fw_data = NULL;
@@ -329,6 +329,76 @@ static int gmc_v8_0_mc_load_microcode(struct amdgpu_device 
*adev)
return 0;
 }
 
+static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
+{
+   const struct mc_firmware_header_v1_0 *hdr;
+   const __le32 *fw_data = NULL;
+   const __le32 *io_mc_regs = NULL;
+   u32 data, vbios_version;
+   int i, ucode_size, regs_size;
+
+   if (!adev->mc.fw)
+   return -EINVAL;
+
+   /* Skip MC ucode loading on SR-IOV capable boards.
+* vbios does this for us in asic_init in that case.
+* Skip MC ucode loading on VF, because hypervisor will do that
+* for this adaptor.
+*/
+   if (amdgpu_sriov_bios(adev))
+   return 0;
+
+   WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
+   data = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
+   vbios_version = data & 0xf;
+
+   if (vbios_version == 0)
+   return 0;
+
+   hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
+   amdgpu_ucode_print_mc_hdr(&hdr->header);
+
+   adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
+   regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
+   io_mc_regs = (const __le32 *)
+   (adev->mc.fw->data + 
le32_to_cpu(hdr->io_debug_array_offset_bytes));
+   ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
+   fw_data = (const __le32 *)
+   (adev->mc.fw->data + 
le32_to_cpu(hdr->header.ucode_array_offset_bytes));
+
+   data = RREG32(mmMC_SEQ_MISC0);
+   data &= ~(0x40);
+   WREG32(mmMC_SEQ_MISC0, data);
+
+   /* load mc io regs */
+   for (i = 0; i < regs_size; i++) {
+   WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
+   WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
+   }
+
+   WREG32(mmMC_SEQ_SUP_CNTL, 0x0008);
+   WREG32(mmMC_SEQ_SUP_CNTL, 0x0010);
+
+   /* load the MC ucode */
+   for (i = 0; i < ucode_size; i++)
+   WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
+
+   /* put the engine back into the active state */
+   WREG32(mmMC_SEQ_SUP_CNTL, 0x0008);
+   WREG32(mmMC_SEQ_SUP_CNTL, 0x0004);
+   WREG32(mmMC_SEQ_SUP_CNTL, 0x0001);
+
+   /* wait for training to complete */
+   for (i = 0; i < adev->usec_timeout; i++) {
+   data = RREG32(mmMC_SEQ_MISC0);
+   if (data & 0x80)
+   break;
+   udelay(1);
+   }
+
+   return 0;
+}
+
 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
   struct amdgpu_mc *mc)
 {
@@ -1095,7 +1165,15 @@ static int gmc_v8_0_hw_init(void *handle)
gmc_v8_0_mc_program(adev);
 
if (adev->asic_type == CHIP_TONGA) {
-   r = gmc_v8_0_mc_load_microcode(adev);
+   r = gmc_v8_0_tonga_mc_load_microcode(adev);
+   if (r) {
+   DRM_ERROR("Failed to load MC firmware!\n");
+   return r;
+   }
+   } else if (adev->asic_type == CHIP_POLARIS11 ||
+   adev->asic_type == CHIP_POLARIS10 ||
+   adev->asic_type == CHIP_POLARIS12) {
+   r = gmc_v8_0_polaris_mc_load_microcode(adev);
if (r) {
DRM_ERROR("Failed to load MC firmware!\n");
return r;
-- 
1.9.1

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Re: [PATCH] drm/amdgpu: fix duplicated code

2017-03-20 Thread Christian König


Am 21.03.2017 um 03:34 schrieb Jerry Zhang:


On 03/21/2017 10:10 AM, Chunming Zhou wrote:

it could come from branch merge.

Change-Id: I16959aad6ca6d64cb8330f23ee6472eec4cf2a3e
Signed-off-by: Chunming Zhou 

Reviewed-by: Junwei Zhang 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 
  1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

index 81c3c75..dd7df45 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -990,10 +990,6 @@ static int amdgpu_vm_bo_update_mapping(struct 
amdgpu_device *adev,


  ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);

-memset(¶ms, 0, sizeof(params));
-params.adev = adev;
-params.src = src;
-
  /* sync to everything on unmapping */
  if (!(flags & AMDGPU_PTE_VALID))
  owner = AMDGPU_FENCE_OWNER_UNDEFINED;


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Re: [PATCH] drm/amdgpu: fix duplicated code

2017-03-20 Thread Jerry Zhang



On 03/21/2017 10:10 AM, Chunming Zhou wrote:

it could come from branch merge.

Change-Id: I16959aad6ca6d64cb8330f23ee6472eec4cf2a3e
Signed-off-by: Chunming Zhou 

Reviewed-by: Junwei Zhang 

---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 
  1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 81c3c75..dd7df45 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -990,10 +990,6 @@ static int amdgpu_vm_bo_update_mapping(struct 
amdgpu_device *adev,

ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);

-   memset(¶ms, 0, sizeof(params));
-   params.adev = adev;
-   params.src = src;
-
/* sync to everything on unmapping */
if (!(flags & AMDGPU_PTE_VALID))
owner = AMDGPU_FENCE_OWNER_UNDEFINED;


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[PATCH] drm/amdgpu: fix duplicated code

2017-03-20 Thread Chunming Zhou

it could come from branch merge.

Change-Id: I16959aad6ca6d64cb8330f23ee6472eec4cf2a3e
Signed-off-by: Chunming Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 81c3c75..dd7df45 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -990,10 +990,6 @@ static int amdgpu_vm_bo_update_mapping(struct 
amdgpu_device *adev,
 
ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
 
-   memset(¶ms, 0, sizeof(params));
-   params.adev = adev;
-   params.src = src;
-
/* sync to everything on unmapping */
if (!(flags & AMDGPU_PTE_VALID))
owner = AMDGPU_FENCE_OWNER_UNDEFINED;
-- 
1.9.1

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Re: [PATCH 000/100] Add Vega10 Support

2017-03-20 Thread Tom St Denis

On 03/20/2017 06:34 PM, Jan Ziak wrote:

On Mon, Mar 20, 2017 at 10:41 PM, Alex Deucher mailto:alexdeuc...@gmail.com>> wrote:

On Mon, Mar 20, 2017 at 5:36 PM, Jan Ziak <0xe2.0x9a.0...@gmail.com
> wrote:
> Hi
>
> 
https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2

>
> The file nbio_6_1_sh_mask.h is uncompressed. It consists from 133884 
lines.
> Only generated C/C++ code will be able to utilize the content of such a 
file
> efficiently. All hand-written codes combined will be able to utilize about
> 1% of the file.
>
> Is there a reason why nbio_6_1_sh_mask.h is huge?

That IP block contains a lot of registers.  The idea is to open source
as much IP as possible to facilitate debugging, new features, etc.

Alex

[This email contains long/wide lines and should be viewed on a
sufficiently wide screen]

For example if I open the file in vim and go to line 66952:

#define 
DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9

Then abstracting away some of the digits used in the defined identifier
and using egrep:

$ egrep
"\"
nbio_6_1_sh_mask.h
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9

The egrep command produced 20 lines.

Instead of the many #define directives, it is a possibility to define
functions such as:

int
DWC_E12MP_PHY_Xa_NS_Xb_c_LANEd_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_e__DTB_SEL__SHIFT(int
a, int b, int c, int d, int e) __attribute__((pure));

I suppose the file nbio_6_1_sh_mask.h is the output of a tool (it is a
generated file). It is an option to modify the tool to output C
functions with proper input guards instead of #define directives.

The registers are generated by the HW team and then filtered down to 
become what we release publicly.  It is machine generated very likely 
from the RTL that specifies the hardware itself.

Generally speaking if a class of registers share masks/offsets the 
lowest (zero'th) is used in programming and offsets are used when 
selecting the correct MMIO address to use specific instances.

Having these enumerated though is handy for tools like UMR which would 
decode to the correct instance of the register (you could even see that 
by watching the logscan via umr).  So we make use of them fairly 
efficiently.  UMR reads the headers to create the arrays of 
registers/bitfields which if they were computed at runtime (via helper 
functions) would

Re: [PATCH 000/100] Add Vega10 Support

2017-03-20 Thread Jan Ziak

On Mon, Mar 20, 2017 at 10:41 PM, Alex Deucher 
wrote:

> On Mon, Mar 20, 2017 at 5:36 PM, Jan Ziak <0xe2.0x9a.0...@gmail.com>
> wrote:
> > Hi
> >
> > https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/
> drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.
> h?h=amd-staging-4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2
> >
> > The file nbio_6_1_sh_mask.h is uncompressed. It consists from 133884
> lines.
> > Only generated C/C++ code will be able to utilize the content of such a
> file
> > efficiently. All hand-written codes combined will be able to utilize
> about
> > 1% of the file.
> >
> > Is there a reason why nbio_6_1_sh_mask.h is huge?
>
> That IP block contains a lot of registers.  The idea is to open source
> as much IP as possible to facilitate debugging, new features, etc.
>
> Alex
>

[This email contains long/wide lines and should be viewed on a sufficiently
wide screen]

For example if I open the file in vim and go to line 66952:

#define 
DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9

Then abstracting away some of the digits used in the defined identifier and
using egrep:

$ egrep
"\"
nbio_6_1_sh_mask.h
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
   0x9

The egrep command produced 20 lines.

Instead of the many #define directives, it is a possibility to define
functions such as:

int
DWC_E12MP_PHY_Xa_NS_Xb_c_LANEd_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_e__DTB_SEL__SHIFT(int
a, int b, int c, int d, int e) __attribute__((pure));

I suppose the file nbio_6_1_sh_mask.h is the output of a tool (it is a
generated file). It is an option to modify the tool to output C functions
with proper input guards instead of #define directives.

Jan
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Re: [PATCH 000/100] Add Vega10 Support

2017-03-20 Thread Alex Deucher

On Mon, Mar 20, 2017 at 5:36 PM, Jan Ziak <0xe2.0x9a.0...@gmail.com> wrote:
> Hi
>
> https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2
>
> The file nbio_6_1_sh_mask.h is uncompressed. It consists from 133884 lines.
> Only generated C/C++ code will be able to utilize the content of such a file
> efficiently. All hand-written codes combined will be able to utilize about
> 1% of the file.
>
> Is there a reason why nbio_6_1_sh_mask.h is huge?

That IP block contains a lot of registers.  The idea is to open source
as much IP as possible to facilitate debugging, new features, etc.

Alex
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Re: [PATCH 000/100] Add Vega10 Support

2017-03-20 Thread Jan Ziak

Hi

https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2

The file nbio_6_1_sh_mask.h is uncompressed. It consists from 133884 lines.
Only generated C/C++ code will be able to utilize the content of such a
file efficiently. All hand-written codes combined will be able to utilize
about 1% of the file.

Is there a reason why nbio_6_1_sh_mask.h is huge?

Jan
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[PATCH 058/100] drm/amd/powerplay: add global PowerPlay mutex.

2017-03-20 Thread Alex Deucher

From: Rex Zhu 

Signed-off-by: Rex Zhu 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c   | 192 
 drivers/gpu/drm/amd/powerplay/inc/pp_instance.h |   1 +
 2 files changed, 132 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 8132d46..985ed21 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -341,8 +341,9 @@ static int pp_dpm_force_performance_level(void *handle,
return 0;
}
 
+   mutex_lock(&pp_handle->pp_lock);
hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
-
+   mutex_unlock(&pp_handle->pp_lock);
return 0;
 }
 
@@ -352,6 +353,7 @@ static enum amd_dpm_forced_level 
pp_dpm_get_performance_level(
struct pp_hwmgr  *hwmgr;
struct pp_instance *pp_handle = (struct pp_instance *)handle;
int ret = 0;
+   enum amd_dpm_forced_level level;
 
ret = pp_check(pp_handle);
 
@@ -359,8 +361,10 @@ static enum amd_dpm_forced_level 
pp_dpm_get_performance_level(
return ret;
 
hwmgr = pp_handle->hwmgr;
-
-   return hwmgr->dpm_level;
+   mutex_lock(&pp_handle->pp_lock);
+   level = hwmgr->dpm_level;
+   mutex_unlock(&pp_handle->pp_lock);
+   return level;
 }
 
 static int pp_dpm_get_sclk(void *handle, bool low)
@@ -380,8 +384,10 @@ static int pp_dpm_get_sclk(void *handle, bool low)
pr_info("%s was not implemented.\n", __func__);
return 0;
}
-
-   return hwmgr->hwmgr_func->get_sclk(hwmgr, low);
+   mutex_lock(&pp_handle->pp_lock);
+   ret = hwmgr->hwmgr_func->get_sclk(hwmgr, low);
+   mutex_unlock(&pp_handle->pp_lock);
+   return ret;
 }
 
 static int pp_dpm_get_mclk(void *handle, bool low)
@@ -401,8 +407,10 @@ static int pp_dpm_get_mclk(void *handle, bool low)
pr_info("%s was not implemented.\n", __func__);
return 0;
}
-
-   return hwmgr->hwmgr_func->get_mclk(hwmgr, low);
+   mutex_lock(&pp_handle->pp_lock);
+   ret = hwmgr->hwmgr_func->get_mclk(hwmgr, low);
+   mutex_unlock(&pp_handle->pp_lock);
+   return ret;
 }
 
 static int pp_dpm_powergate_vce(void *handle, bool gate)
@@ -422,8 +430,10 @@ static int pp_dpm_powergate_vce(void *handle, bool gate)
pr_info("%s was not implemented.\n", __func__);
return 0;
}
-
-   return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
+   mutex_lock(&pp_handle->pp_lock);
+   ret = hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
+   mutex_unlock(&pp_handle->pp_lock);
+   return ret;
 }
 
 static int pp_dpm_powergate_uvd(void *handle, bool gate)
@@ -443,8 +453,10 @@ static int pp_dpm_powergate_uvd(void *handle, bool gate)
pr_info("%s was not implemented.\n", __func__);
return 0;
}
-
-   return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
+   mutex_lock(&pp_handle->pp_lock);
+   ret = hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
+   mutex_unlock(&pp_handle->pp_lock);
+   return ret;
 }
 
 static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type  state)
@@ -472,7 +484,7 @@ static int pp_dpm_dispatch_tasks(void *handle, enum 
amd_pp_event event_id,
 
if (ret != 0)
return ret;
-
+   mutex_lock(&pp_handle->pp_lock);
switch (event_id) {
case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE:
ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
@@ -498,6 +510,7 @@ static int pp_dpm_dispatch_tasks(void *handle, enum 
amd_pp_event event_id,
default:
break;
}
+   mutex_unlock(&pp_handle->pp_lock);
return ret;
 }
 
@@ -507,6 +520,7 @@ static enum amd_pm_state_type 
pp_dpm_get_current_power_state(void *handle)
struct pp_power_state *state;
struct pp_instance *pp_handle = (struct pp_instance *)handle;
int ret = 0;
+   enum amd_pm_state_type pm_type;
 
ret = pp_check(pp_handle);
 
@@ -518,21 +532,26 @@ static enum amd_pm_state_type 
pp_dpm_get_current_power_state(void *handle)
if (hwmgr->current_ps == NULL)
return -EINVAL;
 
+   mutex_lock(&pp_handle->pp_lock);
+
state = hwmgr->current_ps;
 
switch (state->classification.ui_label) {
case PP_StateUILabel_Battery:
-   return POWER_STATE_TYPE_BATTERY;
+   pm_type = POWER_STATE_TYPE_BATTERY;
case PP_StateUILabel_Balanced:
-   return POWER_STATE_TYPE_BALANCED;
+   pm_type = POWER_STATE_TYPE_BALANCED;
case PP_StateUILabel_Performance:
-   return POWER_STATE_TYPE_PERFORMANCE;
+   pm_type = POWER_STATE_TYPE_PERFORMANCE;
default:
if (state->classification.

[PATCH 075/100] drm/amdgpu: impl sriov detection for vega10

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

Read vega10 hw register to detect if sriov is enabled, and call
it before IP blocks setting.

Signed-off-by: Xiangliang Yu 
Reviewed-by: Alex Deucher 
Acked-by: Christian König 
Reviewed-by: Monk Liu 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 18 ++
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h |  1 +
 drivers/gpu/drm/amd/amdgpu/soc15.c |  2 ++
 3 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index f517e9a..9021872 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -231,3 +231,21 @@ int nbio_v6_1_init(struct amdgpu_device *adev)
 
return 0;
 }
+
+void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
+{
+   uint32_t reg;
+
+   reg = RREG32(SOC15_REG_OFFSET(NBIO, 0,
+ mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER));
+   if (reg & 1)
+   adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
+
+   if (reg & 0x8000)
+   adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
+
+   if (!reg) {
+   if (is_virtual_machine())   /* passthrough mode exclus 
sriov mod */
+   adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
+   }
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h 
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
index a778d1c..3e04093 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
@@ -48,5 +48,6 @@ void nbio_v6_1_ih_control(struct amdgpu_device *adev);
 u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev);
 void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, 
bool enable);
 void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, 
bool enable);
+void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev);
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 07e10f3..263f602 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -469,6 +469,8 @@ static const struct amdgpu_ip_block_version 
vega10_common_ip_block =
 
 int soc15_set_ip_blocks(struct amdgpu_device *adev)
 {
+   nbio_v6_1_detect_hw_virt(adev);
+
switch (adev->asic_type) {
case CHIP_VEGA10:
amdgpu_ip_block_add(adev, &vega10_common_ip_block);
-- 
2.5.5

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[PATCH 096/100] drm/amdgpu/vce4: alloc mm table for MM sriov

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

Allocate MM table for sriov device.

Signed-off-by: Xiangliang Yu 
Signed-off-by: Monk Liu 
Reviewed-by: Alex Deucher 
Reviewed-by: Monk Liu 
Reviewed-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 21a86d8..b1b887e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -294,6 +294,21 @@ static int vce_v4_0_sw_init(void *handle)
return r;
}
 
+   if (amdgpu_sriov_vf(adev)) {
+   r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
+   AMDGPU_GEM_DOMAIN_VRAM,
+   &adev->virt.mm_table.bo,
+   &adev->virt.mm_table.gpu_addr,
+   (void 
*)&adev->virt.mm_table.cpu_addr);
+   if (!r) {
+   memset((void *)adev->virt.mm_table.cpu_addr, 0, 
PAGE_SIZE);
+   printk("mm table gpu addr = 0x%llx, cpu addr = %p. \n",
+  adev->virt.mm_table.gpu_addr,
+  adev->virt.mm_table.cpu_addr);
+   }
+   return r;
+   }
+
return r;
 }
 
@@ -302,6 +317,12 @@ static int vce_v4_0_sw_fini(void *handle)
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+   /* free MM table */
+   if (amdgpu_sriov_vf(adev))
+   amdgpu_bo_free_kernel(&adev->virt.mm_table.bo,
+ &adev->virt.mm_table.gpu_addr,
+ (void *)&adev->virt.mm_table.cpu_addr);
+
r = amdgpu_vce_suspend(adev);
if (r)
return r;
-- 
2.5.5

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[PATCH 070/100] drm/amd/display: Less log spam

2017-03-20 Thread Alex Deucher

From: Jordan Lazare 

Signed-off-by: Jordan Lazare 
Acked-by: Harry Wentland 
Reviewed-by: Charlene Liu 
Acked-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/dc/bios/command_table2.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c 
b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
index 36d1582..e33e6bf 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
@@ -238,8 +238,8 @@ static enum bp_result transmitter_control_v1_6(
if (cntl->action == TRANSMITTER_CONTROL_ENABLE ||
cntl->action == TRANSMITTER_CONTROL_ACTIAVATE ||
cntl->action == TRANSMITTER_CONTROL_DEACTIVATE) {
-   dm_logger_write(bp->base.ctx->logger, LOG_HW_SET_MODE,\
-   "%s:ps.param.symclk_10khz = %d\n",\
+   dm_logger_write(bp->base.ctx->logger, LOG_BIOS,\
+   "%s:ps.param.symclk_10khz = %d\n",\
__func__, ps.param.symclk_10khz);
}
 
@@ -328,8 +328,8 @@ static enum bp_result set_pixel_clock_v7(
(uint8_t) bp->cmd_helper->
transmitter_color_depth_to_atom(
bp_params->color_depth);
-   dm_logger_write(bp->base.ctx->logger, LOG_HW_SET_MODE,\
-   "%s:program display 
clock = %d"\
+   dm_logger_write(bp->base.ctx->logger, LOG_BIOS,\
+   "%s:program display clock = %d"\
"colorDepth = %d\n", __func__,\
bp_params->target_pixel_clock, 
bp_params->color_depth);
 
@@ -760,8 +760,8 @@ static enum bp_result set_dce_clock_v2_1(
 */
params.param.dceclk_10khz = cpu_to_le32(
bp_params->target_clock_frequency / 10);
-   dm_logger_write(bp->base.ctx->logger, LOG_HW_SET_MODE,
-   "%s:target_clock_frequency = 
%d"\
+   dm_logger_write(bp->base.ctx->logger, LOG_BIOS,
+   "%s:target_clock_frequency = %d"\
"clock_type = %d \n", __func__,\
bp_params->target_clock_frequency,\
bp_params->clock_type);
-- 
2.5.5

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[PATCH 091/100] drm/amdgpu: Don't touch PG&CG for SRIOV MM

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

For SRIOV, MM don't need to care about PG & CG, skip it.

Signed-off-by: Xiangliang Yu 
Reviewed-by: Alex Deucher 
Reviewed-by: Monk Liu 
Reviewed-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 6 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 6 ++
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index b2e1d3b..e1a838e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -1138,6 +1138,9 @@ static void amdgpu_uvd_idle_work_handler(struct 
work_struct *work)
container_of(work, struct amdgpu_device, uvd.idle_work.work);
unsigned fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
 
+   if (amdgpu_sriov_vf(adev))
+   return;
+
if (fences == 0) {
if (adev->pm.dpm_enabled) {
amdgpu_dpm_enable_uvd(adev, false);
@@ -1159,6 +1162,9 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
struct amdgpu_device *adev = ring->adev;
bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
 
+   if (amdgpu_sriov_vf(adev))
+   return;
+
if (set_clocks) {
if (adev->pm.dpm_enabled) {
amdgpu_dpm_enable_uvd(adev, true);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 647944b..f9e45d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -320,6 +320,9 @@ static void amdgpu_vce_idle_work_handler(struct work_struct 
*work)
container_of(work, struct amdgpu_device, vce.idle_work.work);
unsigned i, count = 0;
 
+   if (amdgpu_sriov_vf(adev))
+   return;
+
for (i = 0; i < adev->vce.num_rings; i++)
count += amdgpu_fence_count_emitted(&adev->vce.ring[i]);
 
@@ -350,6 +353,9 @@ void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring)
struct amdgpu_device *adev = ring->adev;
bool set_clocks;
 
+   if (amdgpu_sriov_vf(adev))
+   return;
+
mutex_lock(&adev->vce.idle_mutex);
set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);
if (set_clocks) {
-- 
2.5.5

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[PATCH 097/100] drm/amdgpu/vce4: Ignore vce ring/ib test temporarily

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

In order to not break SRIOV gfx development, will revert
this patch after vce proved working.

Signed-off-by: Xiangliang Yu 
Reviewed-by: Alex Deucher 
Reviewed-by: Monk Liu 
Reviewed-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index f9e45d2..eccd70a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -957,6 +957,10 @@ int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
unsigned i;
int r;
 
+   /* TODO: remove it if VCE can work for sriov */
+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
r = amdgpu_ring_alloc(ring, 16);
if (r) {
DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
@@ -995,6 +999,10 @@ int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long 
timeout)
struct fence *fence = NULL;
long r;
 
+   /* TODO: remove it if VCE can work for sriov */
+   if (amdgpu_sriov_vf(ring->adev))
+   return 0;
+
/* skip vce ring1/2 ib test for now, since it's not reliable */
if (ring != &ring->adev->vce.ring[0])
return 0;
-- 
2.5.5

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[PATCH 098/100] drm/amdgpu: add mmsch structures

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

For MM SRIOV, need to prepare MM table send send it to MMSCH to
initial UVD & VCE engine. Create new header file for the structures.

Signed-off-by: Xiangliang Yu 
Signed-off-by: Monk Liu 
Reviewed-by: Alex Deucher 
Acked-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h | 87 +
 1 file changed, 87 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h

diff --git a/drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h 
b/drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h
new file mode 100644
index 000..5f0fc8b
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __MMSCH_V1_0_H__
+#define __MMSCH_V1_0_H__
+
+#define MMSCH_VERSION_MAJOR1
+#define MMSCH_VERSION_MINOR0
+#define MMSCH_VERSION  (MMSCH_VERSION_MAJOR << 16 | MMSCH_VERSION_MINOR)
+
+enum mmsch_v1_0_command_type {
+   MMSCH_COMMAND__DIRECT_REG_WRITE = 0,
+   MMSCH_COMMAND__DIRECT_REG_POLLING = 2,
+   MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE = 3,
+   MMSCH_COMMAND__INDIRECT_REG_WRITE = 8,
+   MMSCH_COMMAND__END = 0xf
+};
+
+struct mmsch_v1_0_init_header {
+   uint32_t version;
+   uint32_t header_size;
+   uint32_t vce_init_status;
+   uint32_t uvd_init_status;
+   uint32_t vce_table_offset;
+   uint32_t vce_table_size;
+   uint32_t uvd_table_offset;
+   uint32_t uvd_table_size;
+};
+
+struct mmsch_v1_0_cmd_direct_reg_header {
+   uint32_t reg_offset   : 28;
+   uint32_t command_type : 4;
+};
+
+struct mmsch_v1_0_cmd_indirect_reg_header {
+   uint32_t reg_offset: 20;
+   uint32_t reg_idx_space : 8;
+   uint32_t command_type  : 4;
+};
+
+struct mmsch_v1_0_cmd_direct_write {
+   struct mmsch_v1_0_cmd_direct_reg_header cmd_header;
+   uint32_t reg_value;
+};
+
+struct mmsch_v1_0_cmd_direct_read_modify_write {
+   struct mmsch_v1_0_cmd_direct_reg_header cmd_header;
+   uint32_t write_data;
+   uint32_t mask_value;
+};
+
+struct mmsch_v1_0_cmd_direct_polling {
+   struct mmsch_v1_0_cmd_direct_reg_header cmd_header;
+   uint32_t mask_value;
+   uint32_t wait_value;
+};
+
+struct mmsch_v1_0_cmd_end {
+   struct mmsch_v1_0_cmd_direct_reg_header cmd_header;
+};
+
+struct mmsch_v1_0_cmd_indirect_write {
+   struct mmsch_v1_0_cmd_indirect_reg_header cmd_header;
+   uint32_t reg_value;
+};
+
+#endif
-- 
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[PATCH 094/100] drm/amdgpu/soc15: bypass pp block for vf

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

Disable pp block if device is  vf.

Signed-off-by: Xiangliang Yu 
Reviewed-by: Alex Deucher 
Reviewed-by: Monk Liu 
Acked-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 54cb0b5..7e54d9dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -483,9 +483,10 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
-   if (!amdgpu_sriov_vf(adev))
+   if (!amdgpu_sriov_vf(adev)) {
amdgpu_ip_block_add(adev, &psp_v3_1_ip_block);
-   amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+   amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+   }
if (amdgpu_sriov_vf(adev))
amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
 #if defined(CONFIG_DRM_AMD_DC)
-- 
2.5.5

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[PATCH 067/100] drm/amd/display: Add DCE12 core support

2017-03-20 Thread Alex Deucher

From: Harry Wentland 

Signed-off-by: Harry Wentland 
Signed-off-by: Alex Deucher 
---
 .../amd/display/dc/dce120/dce120_hw_sequencer.c|  197 
 .../amd/display/dc/dce120/dce120_hw_sequencer.h|   36 +
 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c |   58 +
 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h |   62 ++
 .../drm/amd/display/dc/dce120/dce120_ipp_cursor.c  |  202 
 .../drm/amd/display/dc/dce120/dce120_ipp_gamma.c   |  167 +++
 .../drm/amd/display/dc/dce120/dce120_mem_input.c   |  340 ++
 .../drm/amd/display/dc/dce120/dce120_mem_input.h   |   37 +
 .../drm/amd/display/dc/dce120/dce120_resource.c| 1099 +++
 .../drm/amd/display/dc/dce120/dce120_resource.h|   39 +
 .../display/dc/dce120/dce120_timing_generator.c| 1109 
 .../display/dc/dce120/dce120_timing_generator.h|   41 +
 12 files changed, 3387 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_gamma.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h
 create mode 100644 
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
new file mode 100644
index 000..f5ffd8f6
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dc.h"
+#include "core_dc.h"
+#include "core_types.h"
+#include "dce120_hw_sequencer.h"
+
+#include "dce110/dce110_hw_sequencer.h"
+
+/* include DCE12.0 register header files */
+#include "vega10/DC/dce_12_0_offset.h"
+#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "vega10/soc15ip.h"
+#include "reg_helper.h"
+
+struct dce120_hw_seq_reg_offsets {
+   uint32_t crtc;
+};
+
+static const struct dce120_hw_seq_reg_offsets reg_offsets[] = {
+{
+   .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
+},
+{
+   .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
+},
+{
+   .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
+},
+{
+   .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
+},
+{
+   .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
+},
+{
+   .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
+}
+};
+
+#define HW_REG_CRTC(reg, id)\
+   (reg + reg_offsets[id].crtc)
+
+#define CNTL_ID(controller_id)\
+   controller_id
+/***
+ * Private definitions
+ 
**/
+#if 0
+static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)
+{
+   uint32_t addr;
+   uint32_t value = 0;
+   uint32_t chunk_int = 0;
+   uint32_t chunk_mul = 0;
+/*
+   addr = mmDCP0_DVMM_PTE_CONTROL + controller_id *
+   (mmDCP1_DVMM_PTE_CONTROL- mmDCP0_DVMM_PTE_CONTROL);
+
+   value = dm_read_reg(ctx, addr);
+
+   set_reg_field_value(
+

[PATCH 074/100] drm/amdgpu/gfx9: programing wptr_poll_addr register

2017-03-20 Thread Alex Deucher

From: Monk Liu 

Required for SR-IOV.

Signed-off-by: Monk Liu 
Signed-off-by: Xiangliang Yu 
Reviewed-by: Christian König 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index bb93b0a..4704524 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1501,7 +1501,7 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device 
*adev)
struct amdgpu_ring *ring;
u32 tmp;
u32 rb_bufsz;
-   u64 rb_addr, rptr_addr;
+   u64 rb_addr, rptr_addr, wptr_gpu_addr;
 
/* Set the write pointer delay */
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_DELAY), 0);
@@ -1529,6 +1529,10 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device 
*adev)
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR), 
lower_32_bits(rptr_addr));
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR_HI), 
upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
 
+   wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO), 
lower_32_bits(wptr_gpu_addr));
+   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI), 
upper_32_bits(wptr_gpu_addr));
+
mdelay(1);
WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL), tmp);
 
-- 
2.5.5

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[PATCH 045/100] drm/amdgpu: add NBIO 6.1 driver

2017-03-20 Thread Alex Deucher

From: Junwei Zhang 

This handles nbio 6.1 specific implementations which
are used by various other IPs.

Signed-off-by: Hawking Zhang 
Signed-off-by: Junwei Zhang 
Reviewed-by: Alex Deucher 
Signed-off-by: Tom St Denis 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/Makefile|   2 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 233 +
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h |  52 
 3 files changed, 286 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index fbf6474..69823e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -40,7 +40,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o 
kv_dpm.o \
 amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o 
dce_v6_0.o si_dpm.o si_smc.o
 
 amdgpu-y += \
-   vi.o mxgpu_vi.o
+   vi.o mxgpu_vi.o nbio_v6_1.o
 
 # add GMC block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
new file mode 100644
index 000..f517e9a
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -0,0 +1,233 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "amdgpu_atombios.h"
+#include "nbio_v6_1.h"
+
+#include "vega10/soc15ip.h"
+#include "vega10/NBIO/nbio_6_1_default.h"
+#include "vega10/NBIO/nbio_6_1_offset.h"
+#include "vega10/NBIO/nbio_6_1_sh_mask.h"
+#include "vega10/vega10_enum.h"
+
+#define smnCPM_CONTROL 
 0x11180460
+#define smnPCIE_CNTL2  
 0x11180070
+
+u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
+{
+u32 tmp = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0));
+
+   tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
+   tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
+
+   return tmp;
+}
+
+u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev,
+   uint32_t idx)
+{
+   return RREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0) + idx);
+}
+
+void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev,
+uint32_t idx, uint32_t val)
+{
+   WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0) + idx, val);
+}
+
+void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
+{
+   if (enable)
+   WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_FB_EN),
+   BIF_FB_EN__FB_READ_EN_MASK | 
BIF_FB_EN__FB_WRITE_EN_MASK);
+   else
+   WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_FB_EN), 0);
+}
+
+void nbio_v6_1_hdp_flush(struct amdgpu_device *adev)
+{
+   WREG32(SOC15_REG_OFFSET(NBIO, 0, 
mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL), 0);
+}
+
+u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
+{
+   return RREG32(SOC15_REG_OFFSET(NBIO, 0, 
mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE));
+}
+
+static const u32 nbio_sdma_doorbell_range_reg[] =
+{
+   SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE),
+   SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE)
+};
+
+void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
+ bool use_doorbell, int doorbell_index)
+{
+   u32 doorbell_range = RREG32(nbio_sdma_doorbell_range_reg[instance]);
+
+   if (use_doorbell) {
+   doorbell_range = REG_SET_FIELD(doorbell_range, 
BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
+   doorbell_range = REG_SET_FIELD(doorbell_range, 
BIF_SDMA0_DOORBELL_RANG

[PATCH 038/100] drm/amdgpu: don't validate TILE_SPLIT on GFX9

2017-03-20 Thread Alex Deucher

From: Marek Olšák 

Signed-off-by: Marek Olšák 
Acked-by: Alex Deucher 
Acked-by: Christian König 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index e1e673c..434c931 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -815,7 +815,10 @@ int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 
 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
 {
-   if (AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
+   struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+
+   if (adev->family <= AMDGPU_FAMILY_CZ &&
+   AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
return -EINVAL;
 
bo->tiling_flags = tiling_flags;
-- 
2.5.5

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[PATCH 084/100] drm/amdgpu/soc15: bypass PSP for VF

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

Bypass PSP block for VF device.

Signed-off-by: Xiangliang Yu 
Signed-off-by: Monk Liu 
Reviewed-by: Alex Deucher 
Reviewed-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 263f602..b197288 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -478,7 +478,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
-   amdgpu_ip_block_add(adev, &psp_v3_1_ip_block);
+   if (!amdgpu_sriov_vf(adev))
+   amdgpu_ip_block_add(adev, &psp_v3_1_ip_block);
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
 #if defined(CONFIG_DRM_AMD_DC)
if (amdgpu_device_has_dc_support(adev))
-- 
2.5.5

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[PATCH 071/100] drm/amdgpu: soc15 enable (v2)

2017-03-20 Thread Alex Deucher

From: Ken Wang 

Add soc15 support and enable all the IPs for vega10.

v2: squash in xclk fix

Signed-off-by: Ken Wang 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/Makefile |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c |   3 +
 drivers/gpu/drm/amd/amdgpu/soc15.c  | 813 
 3 files changed, 817 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15.c

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index bad4658..a377fdb 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -40,7 +40,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o 
kv_dpm.o \
 amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o 
dce_v6_0.o si_dpm.o si_smc.o
 
 amdgpu-y += \
-   vi.o mxgpu_vi.o nbio_v6_1.o
+   vi.o mxgpu_vi.o nbio_v6_1.o soc15.o
 
 # add GMC block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 1524d90..d6cbdbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -903,6 +903,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device 
*cgs_device,
case CHIP_POLARIS12:
strcpy(fw_name, "amdgpu/polaris12_smc.bin");
break;
+   case CHIP_VEGA10:
+   strcpy(fw_name, "amdgpu/vega10_smc.bin");
+   break;
default:
DRM_ERROR("SMC firmware not supported\n");
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
new file mode 100644
index 000..07e10f3
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -0,0 +1,813 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include 
+#include 
+#include 
+#include "drmP.h"
+#include "amdgpu.h"
+#include "amdgpu_atombios.h"
+#include "amdgpu_ih.h"
+#include "amdgpu_uvd.h"
+#include "amdgpu_vce.h"
+#include "amdgpu_ucode.h"
+#include "amdgpu_psp.h"
+#include "atom.h"
+#include "amd_pcie.h"
+
+#include "vega10/soc15ip.h"
+#include "vega10/UVD/uvd_7_0_offset.h"
+#include "vega10/GC/gc_9_0_offset.h"
+#include "vega10/GC/gc_9_0_sh_mask.h"
+#include "vega10/SDMA0/sdma0_4_0_offset.h"
+#include "vega10/SDMA1/sdma1_4_0_offset.h"
+#include "vega10/HDP/hdp_4_0_offset.h"
+#include "vega10/HDP/hdp_4_0_sh_mask.h"
+#include "vega10/MP/mp_9_0_offset.h"
+#include "vega10/MP/mp_9_0_sh_mask.h"
+#include "vega10/SMUIO/smuio_9_0_offset.h"
+#include "vega10/SMUIO/smuio_9_0_sh_mask.h"
+
+#include "soc15.h"
+#include "soc15_common.h"
+#include "gfx_v9_0.h"
+#include "gmc_v9_0.h"
+#include "gfxhub_v1_0.h"
+#include "mmhub_v1_0.h"
+#include "vega10_ih.h"
+#include "sdma_v4_0.h"
+#include "uvd_v7_0.h"
+#include "vce_v4_0.h"
+#include "amdgpu_powerplay.h"
+
+MODULE_FIRMWARE("amdgpu/vega10_smc.bin");
+
+#define mmFabricConfigAccessControl
0x0410
+#define mmFabricConfigAccessControl_BASE_IDX   
0
+#define mmFabricConfigAccessControl_DEFAULT
  0x
+//FabricConfigAccessControl
+#define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT  
   0x0
+#define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT 
   0x1
+#define FabricConfigAccessControl__CfgRegInstID__SHIFT 
   0x10
+#define FabricConfigAccessControl__CfgRegInstAccEn_MASK

[PATCH 073/100] drm/amdgpu: add Vega10 Device IDs

2017-03-20 Thread Alex Deucher

From: Junwei Zhang 

Signed-off-by: Junwei Zhang 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index ef3ed11..d7f286d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -450,7 +450,14 @@ static const struct pci_device_id pciidlist[] = {
{0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
{0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
{0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
-
+   /* Vega 10 */
+   {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
+   {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
+   {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
+   {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
+   {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
+   {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
+   {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
{0, 0, 0}
 };
 
-- 
2.5.5

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[PATCH 052/100] drm/amdgpu: add PSP driver for vega10

2017-03-20 Thread Alex Deucher

From: Huang Rui 

PSP is responsible for firmware loading on SOC-15 asics.

Signed-off-by: Huang Rui 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/Makefile|   5 +
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|   9 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c| 473 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h| 127 
 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h| 269 +++
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c  | 507 +
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.h  |  50 +++
 drivers/gpu/drm/amd/include/amd_shared.h   |   1 +
 9 files changed, 1442 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
 create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
 create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v3_1.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 2ba5671..bad4658 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -57,6 +57,11 @@ amdgpu-y += \
cz_ih.o \
vega10_ih.o
 
+# add PSP block
+amdgpu-y += \
+   amdgpu_psp.o \
+   psp_v3_1.o
+
 # add SMC block
 amdgpu-y += \
amdgpu_dpm.o \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index c453f5b..2675480 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -52,6 +52,7 @@
 #include "amdgpu_irq.h"
 #include "amdgpu_ucode.h"
 #include "amdgpu_ttm.h"
+#include "amdgpu_psp.h"
 #include "amdgpu_gds.h"
 #include "amdgpu_sync.h"
 #include "amdgpu_ring.h"
@@ -1215,6 +1216,10 @@ struct amdgpu_firmware {
struct amdgpu_bo *fw_buf;
unsigned int fw_size;
unsigned int max_ucodes;
+   /* firmwares are loaded by psp instead of smu from vega10 */
+   const struct amdgpu_psp_funcs *funcs;
+   struct amdgpu_bo *rbuf;
+   struct mutex mutex;
 };
 
 /*
@@ -1578,6 +1583,9 @@ struct amdgpu_device {
/* firmwares */
struct amdgpu_firmware  firmware;
 
+   /* PSP */
+   struct psp_context  psp;
+
/* GDS */
struct amdgpu_gds   gds;
 
@@ -1838,6 +1846,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_gfx_get_gpu_clock_counter(adev) 
(adev)->gfx.funcs->get_gpu_clock_counter((adev))
 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) 
(adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
 #define amdgpu_gds_switch(adev, r, v, d, w, a) 
(adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
+#define amdgpu_psp_check_fw_loading_status(adev, i) 
(adev)->firmware.funcs->check_fw_loading_status((adev), (i))
 
 /* Common functions */
 int amdgpu_gpu_reset(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 19d37a5..82e42ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1870,6 +1870,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 * can recall function without having locking issues */
mutex_init(&adev->vm_manager.lock);
atomic_set(&adev->irq.ih.lock, 0);
+   mutex_init(&adev->firmware.mutex);
mutex_init(&adev->pm.mutex);
mutex_init(&adev->gfx.gpu_clock_mutex);
mutex_init(&adev->srbm_mutex);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
new file mode 100644
index 000..89d1d2f
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -0,0 +1,473 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN TH

[PATCH 044/100] drm/amdgpu: handle PTE MTYPE in amdgpu_vm_bo_split_mapping

2017-03-20 Thread Alex Deucher

From: Alex Xie 

Signed-off-by: Alex Xie 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 52e349a..df615d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1045,6 +1045,9 @@ static int amdgpu_vm_bo_split_mapping(struct 
amdgpu_device *adev,
flags &= ~AMDGPU_PTE_EXECUTABLE;
flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
 
+   flags &= ~AMDGPU_PTE_MTYPE_MASK;
+   flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
+
trace_amdgpu_vm_bo_update(mapping);
 
pfn = mapping->offset >> PAGE_SHIFT;
-- 
2.5.5

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[PATCH 054/100] drm/amdgpu: add SMC firmware into global ucode list for psp loading

2017-03-20 Thread Alex Deucher

From: Huang Rui 

Signed-off-by: Huang Rui 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index d42eade..1524d90 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -837,6 +837,8 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device 
*cgs_device,
uint32_t ucode_start_address;
const uint8_t *src;
const struct smc_firmware_header_v1_0 *hdr;
+   const struct common_firmware_header *header;
+   struct amdgpu_firmware_info *ucode = NULL;
 
if (CGS_UCODE_ID_SMU_SK == type)
amdgpu_cgs_rel_firmware(cgs_device, CGS_UCODE_ID_SMU);
@@ -919,6 +921,15 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device 
*cgs_device,
adev->pm.fw = NULL;
return err;
}
+
+   if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+   ucode = 
&adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
+   ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
+   ucode->fw = adev->pm.fw;
+   header = (const struct common_firmware_header 
*)ucode->fw->data;
+   adev->firmware.fw_size +=
+   
ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+   }
}
 
hdr = (const struct smc_firmware_header_v1_0 *) 
adev->pm.fw->data;
-- 
2.5.5

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[PATCH 049/100] drm/amdgpu: add vega10 interrupt handler

2017-03-20 Thread Alex Deucher

From: Ken Wang 

Signed-off-by: Ken Wang 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/Makefile|   3 +-
 drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 424 +
 drivers/gpu/drm/amd/amdgpu/vega10_ih.h |  30 +++
 3 files changed, 456 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_ih.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_ih.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 61f090f..bc29569 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -54,7 +54,8 @@ amdgpu-y += \
amdgpu_ih.o \
iceland_ih.o \
tonga_ih.o \
-   cz_ih.o
+   cz_ih.o \
+   vega10_ih.o
 
 # add SMC block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c 
b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
new file mode 100644
index 000..23371e1
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -0,0 +1,424 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "drmP.h"
+#include "amdgpu.h"
+#include "amdgpu_ih.h"
+#include "soc15.h"
+
+
+#include "vega10/soc15ip.h"
+#include "vega10/OSSSYS/osssys_4_0_offset.h"
+#include "vega10/OSSSYS/osssys_4_0_sh_mask.h"
+
+#include "soc15_common.h"
+#include "vega10_ih.h"
+
+
+
+static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
+
+/**
+ * vega10_ih_enable_interrupts - Enable the interrupt ring buffer
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Enable the interrupt ring buffer (VEGA10).
+ */
+static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)
+{
+   u32 ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
+
+   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
+   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
+   WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl);
+   adev->irq.ih.enabled = true;
+}
+
+/**
+ * vega10_ih_disable_interrupts - Disable the interrupt ring buffer
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Disable the interrupt ring buffer (VEGA10).
+ */
+static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
+{
+   u32 ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
+
+   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
+   ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
+   WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl);
+   /* set rptr, wptr to 0 */
+   WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), 0);
+   WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR), 0);
+   adev->irq.ih.enabled = false;
+   adev->irq.ih.rptr = 0;
+}
+
+/**
+ * vega10_ih_irq_init - init and enable the interrupt ring
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Allocate a ring buffer for the interrupt controller,
+ * enable the RLC, disable interrupts, enable the IH
+ * ring buffer and enable it (VI).
+ * Called at device load and reume.
+ * Returns 0 for success, errors for failure.
+ */
+static int vega10_ih_irq_init(struct amdgpu_device *adev)
+{
+   int ret = 0;
+   int rb_bufsz;
+   u32 ih_rb_cntl, ih_doorbell_rtpr;
+   u32 tmp;
+   u64 wptr_off;
+
+   /* disable irqs */
+   vega10_ih_disable_interrupts(adev);
+
+   nbio_v6_1_ih_control(adev);
+
+   ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
+   /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the 
ring buffer*/
+   if (adev->irq.ih.use_bus_addr) {
+   WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), 
adev->irq.ih.rb_dma_addr >> 8);
+   WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), 
(adev->irq.ih.rb_dma_addr >> 40) &0xff);
+   ih_rb_cntl = REG_SET

[PATCH 027/100] drm/amdgpu: use new flag to handle different firmware loading method

2017-03-20 Thread Alex Deucher

From: Huang Rui 

This patch introduces a new flag named "amdgpu_firmware_load_type" to
handle different firmware loading method. Since Vega10, there are
three ways to load firmware. It would be better to use a flag and a
fw_load_type kernel parameter to configure it.

Signed-off-by: Huang Rui 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   | 10 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  6 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c |  4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 67 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h |  3 ++
 drivers/gpu/drm/amd/amdgpu/cik.c  |  2 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c |  6 +--
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c|  4 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c|  4 +-
 drivers/gpu/drm/amd/amdgpu/vi.c   |  4 +-
 10 files changed, 90 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b713f37..4d06de8b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -82,7 +82,7 @@ extern int amdgpu_pcie_gen2;
 extern int amdgpu_msi;
 extern int amdgpu_lockup_timeout;
 extern int amdgpu_dpm;
-extern int amdgpu_smc_load_fw;
+extern int amdgpu_fw_load_type;
 extern int amdgpu_aspm;
 extern int amdgpu_runtime_pm;
 extern unsigned amdgpu_ip_block_mask;
@@ -1065,9 +1065,15 @@ struct amdgpu_sdma {
 /*
  * Firmware
  */
+enum amdgpu_firmware_load_type {
+   AMDGPU_FW_LOAD_DIRECT = 0,
+   AMDGPU_FW_LOAD_SMU,
+   AMDGPU_FW_LOAD_PSP,
+};
+
 struct amdgpu_firmware {
struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
-   bool smu_load;
+   enum amdgpu_firmware_load_type load_type;
struct amdgpu_bo *fw_buf;
unsigned int fw_size;
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 296dcb7..3d0e8b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -79,7 +79,7 @@ int amdgpu_pcie_gen2 = -1;
 int amdgpu_msi = -1;
 int amdgpu_lockup_timeout = 0;
 int amdgpu_dpm = -1;
-int amdgpu_smc_load_fw = 1;
+int amdgpu_fw_load_type = -1;
 int amdgpu_aspm = -1;
 int amdgpu_runtime_pm = -1;
 unsigned amdgpu_ip_block_mask = 0x;
@@ -140,8 +140,8 @@ module_param_named(lockup_timeout, amdgpu_lockup_timeout, 
int, 0444);
 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
 module_param_named(dpm, amdgpu_dpm, int, 0444);
 
-MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)");
-module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444);
+MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 
= PSP, -1 = auto)");
+module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
 
 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
 module_param_named(aspm, amdgpu_aspm, int, 0444);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index d56d200..96a5113 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -163,7 +163,7 @@ static int amdgpu_pp_hw_init(void *handle)
int ret = 0;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-   if (adev->pp_enabled && adev->firmware.smu_load)
+   if (adev->pp_enabled && adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
amdgpu_ucode_init_bo(adev);
 
if (adev->powerplay.ip_funcs->hw_init)
@@ -190,7 +190,7 @@ static int amdgpu_pp_hw_fini(void *handle)
ret = adev->powerplay.ip_funcs->hw_fini(
adev->powerplay.pp_handle);
 
-   if (adev->pp_enabled && adev->firmware.smu_load)
+   if (adev->pp_enabled && adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
amdgpu_ucode_fini_bo(adev);
 
return ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index be16377..73c3e66 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -217,6 +217,49 @@ bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header 
*hdr,
return true;
 }
 
+enum amdgpu_firmware_load_type
+amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
+{
+   switch (adev->asic_type) {
+#ifdef CONFIG_DRM_AMDGPU_SI
+   case CHIP_TAHITI:
+   case CHIP_PITCAIRN:
+   case CHIP_VERDE:
+   case CHIP_OLAND:
+   return AMDGPU_FW_LOAD_DIRECT;
+#endif
+#ifdef CONFIG_DRM_AMDGPU_CIK
+   case CHIP_BONAIRE:
+   case CHIP_KAVERI:
+   case CHIP_KABINI:
+   case CHIP_HAWAII:
+   case CHIP_MULLINS:
+   return AMDGPU_FW_LOAD_DIRECT;
+#endif
+   case CHIP_TOPAZ:

[PATCH 026/100] drm/amdgpu: add clinetid definition for vega10

2017-03-20 Thread Alex Deucher

From: ken 

Signed-off-by: ken 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 42 --
 1 file changed, 40 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index 584136e..043620d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -25,10 +25,48 @@
 #define __AMDGPU_IH_H__
 
 struct amdgpu_device;
+ /*
+  * vega10+ IH clients
+ */
+enum amdgpu_ih_clientid
+{
+AMDGPU_IH_CLIENTID_IH  = 0x00,
+AMDGPU_IH_CLIENTID_ACP = 0x01,
+AMDGPU_IH_CLIENTID_ATHUB   = 0x02,
+AMDGPU_IH_CLIENTID_BIF = 0x03,
+AMDGPU_IH_CLIENTID_DCE = 0x04,
+AMDGPU_IH_CLIENTID_ISP = 0x05,
+AMDGPU_IH_CLIENTID_PCIE0   = 0x06,
+AMDGPU_IH_CLIENTID_RLC = 0x07,
+AMDGPU_IH_CLIENTID_SDMA0   = 0x08,
+AMDGPU_IH_CLIENTID_SDMA1   = 0x09,
+AMDGPU_IH_CLIENTID_SE0SH   = 0x0a,
+AMDGPU_IH_CLIENTID_SE1SH   = 0x0b,
+AMDGPU_IH_CLIENTID_SE2SH   = 0x0c,
+AMDGPU_IH_CLIENTID_SE3SH   = 0x0d,
+AMDGPU_IH_CLIENTID_SYSHUB  = 0x0e,
+AMDGPU_IH_CLIENTID_THM = 0x0f,
+AMDGPU_IH_CLIENTID_UVD = 0x10,
+AMDGPU_IH_CLIENTID_VCE0= 0x11,
+AMDGPU_IH_CLIENTID_VMC = 0x12,
+AMDGPU_IH_CLIENTID_XDMA= 0x13,
+AMDGPU_IH_CLIENTID_GRBM_CP = 0x14,
+AMDGPU_IH_CLIENTID_ATS = 0x15,
+AMDGPU_IH_CLIENTID_ROM_SMUIO= 0x16,
+AMDGPU_IH_CLIENTID_DF  = 0x17,
+AMDGPU_IH_CLIENTID_VCE1= 0x18,
+AMDGPU_IH_CLIENTID_PWR = 0x19,
+AMDGPU_IH_CLIENTID_UTCL2   = 0x1b,
+AMDGPU_IH_CLIENTID_EA  = 0x1c,
+AMDGPU_IH_CLIENTID_UTCL2LOG= 0x1d,
+AMDGPU_IH_CLIENTID_MP0 = 0x1e,
+AMDGPU_IH_CLIENTID_MP1 = 0x1f,
 
-#define AMDGPU_IH_CLIENTID_LEGACY 0
+AMDGPU_IH_CLIENTID_MAX
 
-#define AMDGPU_IH_CLIENTID_MAX 0x1f
+};
+
+#define AMDGPU_IH_CLIENTID_LEGACY 0
 
 /*
  * R6xx+ IH ring
-- 
2.5.5

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[PATCH 092/100] drm/amdgpu/vce4: enable doorbell for SRIOV

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

VCE SRIOV need use doorbell and only works on VCN0 ring now

Signed-off-by: Xiangliang Yu 
Signed-off-by: Monk Liu 
Reviewed-by: Alex Deucher 
Acked-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 25 -
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 74146be..21a86d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -78,6 +78,9 @@ static uint64_t vce_v4_0_ring_get_wptr(struct amdgpu_ring 
*ring)
 {
struct amdgpu_device *adev = ring->adev;
 
+   if (ring->use_doorbell)
+   return adev->wb.wb[ring->wptr_offs];
+
if (ring == &adev->vce.ring[0])
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR));
else if (ring == &adev->vce.ring[1])
@@ -97,6 +100,13 @@ static void vce_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 {
struct amdgpu_device *adev = ring->adev;
 
+   if (ring->use_doorbell) {
+   /* XXX check if swapping is necessary on BE */
+   adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+   WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
+   return;
+   }
+
if (ring == &adev->vce.ring[0])
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR),
lower_32_bits(ring->wptr));
@@ -220,7 +230,10 @@ static int vce_v4_0_early_init(void *handle)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-   adev->vce.num_rings = 3;
+   if (amdgpu_sriov_vf(adev)) /* currently only VCN0 support SRIOV */
+   adev->vce.num_rings = 1;
+   else
+   adev->vce.num_rings = 3;
 
vce_v4_0_set_ring_funcs(adev);
vce_v4_0_set_irq_funcs(adev);
@@ -266,6 +279,16 @@ static int vce_v4_0_sw_init(void *handle)
for (i = 0; i < adev->vce.num_rings; i++) {
ring = &adev->vce.ring[i];
sprintf(ring->name, "vce%d", i);
+   if (amdgpu_sriov_vf(adev)) {
+   /* DOORBELL only works under SRIOV */
+   ring->use_doorbell = true;
+   if (i == 0)
+   ring->doorbell_index = 
AMDGPU_DOORBELL64_RING0_1 * 2;
+   else if (i == 1)
+   ring->doorbell_index = 
AMDGPU_DOORBELL64_RING2_3 * 2;
+   else
+   ring->doorbell_index = 
AMDGPU_DOORBELL64_RING2_3 * 2 + 1;
+   }
r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0);
if (r)
return r;
-- 
2.5.5

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[PATCH 043/100] drm/amdgpu: handle PTE EXEC in amdgpu_vm_bo_split_mapping

2017-03-20 Thread Alex Deucher

From: Alex Xie 

Signed-off-by: Alex Xie 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 344b535..52e349a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1042,6 +1042,9 @@ static int amdgpu_vm_bo_split_mapping(struct 
amdgpu_device *adev,
if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
flags &= ~AMDGPU_PTE_WRITEABLE;
 
+   flags &= ~AMDGPU_PTE_EXECUTABLE;
+   flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
+
trace_amdgpu_vm_bo_update(mapping);
 
pfn = mapping->offset >> PAGE_SHIFT;
-- 
2.5.5

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[PATCH 039/100] drm/amdgpu: rework common ucode handling for vega10

2017-03-20 Thread Alex Deucher

From: Huang Rui 

Handle ucode differences in vega10.

Signed-off-by: Huang Rui 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 70 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h |  5 +++
 3 files changed, 53 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ad0e224..aaded8d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1183,6 +1183,7 @@ struct amdgpu_firmware {
enum amdgpu_firmware_load_type load_type;
struct amdgpu_bo *fw_buf;
unsigned int fw_size;
+   unsigned int max_ucodes;
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 73c3e66..a1891c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -260,10 +260,12 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, 
int load_type)
return AMDGPU_FW_LOAD_DIRECT;
 }
 
-static int amdgpu_ucode_init_single_fw(struct amdgpu_firmware_info *ucode,
-   uint64_t mc_addr, void *kptr)
+static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
+  struct amdgpu_firmware_info *ucode,
+  uint64_t mc_addr, void *kptr)
 {
const struct common_firmware_header *header = NULL;
+   const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
 
if (NULL == ucode->fw)
return 0;
@@ -276,11 +278,35 @@ static int amdgpu_ucode_init_single_fw(struct 
amdgpu_firmware_info *ucode,
 
header = (const struct common_firmware_header *)ucode->fw->data;
 
-   ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
-
-   memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
-  le32_to_cpu(header->ucode_array_offset_bytes)),
-  ucode->ucode_size);
+   cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
+
+   if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
+   (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
+ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&
+ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&
+ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT)) {
+   ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
+
+   memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
+ 
le32_to_cpu(header->ucode_array_offset_bytes)),
+  ucode->ucode_size);
+   } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 ||
+  ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) {
+   ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
+   le32_to_cpu(cp_hdr->jt_size) * 4;
+
+   memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
+ 
le32_to_cpu(header->ucode_array_offset_bytes)),
+  ucode->ucode_size);
+   } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
+  ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) {
+   ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
+
+   memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
+ 
le32_to_cpu(header->ucode_array_offset_bytes) +
+ le32_to_cpu(cp_hdr->jt_offset) * 
4),
+  ucode->ucode_size);
+   }
 
return 0;
 }
@@ -306,17 +332,18 @@ static int amdgpu_ucode_patch_jt(struct 
amdgpu_firmware_info *ucode,
   (le32_to_cpu(header->jt_offset) * 4);
memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
 
+   ucode->ucode_size += le32_to_cpu(header->jt_size) * 4;
+
return 0;
 }
 
-
 int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
 {
struct amdgpu_bo **bo = &adev->firmware.fw_buf;
uint64_t fw_mc_addr;
void *fw_buf_ptr = NULL;
uint64_t fw_offset = 0;
-   int i, err, max;
+   int i, err;
struct amdgpu_firmware_info *ucode = NULL;
const struct common_firmware_header *header = NULL;
 
@@ -349,29 +376,32 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
 
amdgpu_bo_unreserve(*bo);
 
+   memset(fw_buf_ptr, 0, adev->firmware.fw_size);
+
/*
 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
 * ucode info here
 */
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
-   max = AMDGPU_UCODE_ID_MAXIMUM - 3;
+   adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
else
-   max = AMDGPU_UCODE_ID_MAXIMUM;
+

[PATCH 002/100] amdgpu: detect if we are using atomfirm or atombios for vbios (v2)

2017-03-20 Thread Alex Deucher

Supposedly atomfirmware rom header is 3.3 atombios is 1.1.

v2: rebased on newer kernel

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 30 +++---
 2 files changed, 24 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 3b81ded..15e985e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1314,6 +1314,7 @@ struct amdgpu_device {
boolhave_disp_power_ref;
 
/* BIOS */
+   boolis_atom_fw;
uint8_t *bios;
uint32_tbios_size;
struct amdgpu_bo*stollen_vga_memory;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index 46ce883..f8d6f7b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -86,6 +86,18 @@ static bool check_atom_bios(uint8_t *bios, size_t size)
return false;
 }
 
+static bool is_atom_fw(uint8_t *bios)
+{
+   uint16_t bios_header_start = bios[0x48] | (bios[0x49] << 8);
+   uint8_t frev = bios[bios_header_start + 2];
+   uint8_t crev = bios[bios_header_start + 3];
+
+   if ((frev < 3) ||
+   ((frev == 3) && (crev < 3)))
+   return false;
+
+   return true;
+}
 
 /* If you boot an IGP board with a discrete card as the primary,
  * the IGP rom is not accessible via the rom bar as the IGP rom is
@@ -418,26 +430,30 @@ static inline bool amdgpu_acpi_vfct_bios(struct 
amdgpu_device *adev)
 bool amdgpu_get_bios(struct amdgpu_device *adev)
 {
if (amdgpu_atrm_get_bios(adev))
-   return true;
+   goto success;
 
if (amdgpu_acpi_vfct_bios(adev))
-   return true;
+   goto success;
 
if (igp_read_bios_from_vram(adev))
-   return true;
+   goto success;
 
if (amdgpu_read_bios(adev))
-   return true;
+   goto success;
 
if (amdgpu_read_bios_from_rom(adev))
-   return true;
+   goto success;
 
if (amdgpu_read_disabled_bios(adev))
-   return true;
+   goto success;
 
if (amdgpu_read_platform_bios(adev))
-   return true;
+   goto success;
 
DRM_ERROR("Unable to locate a BIOS ROM\n");
return false;
+
+success:
+   adev->is_atom_fw = is_atom_fw(adev->bios);
+   return true;
 }
-- 
2.5.5

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[PATCH 035/100] drm/amdgpu: add NGG parameters

2017-03-20 Thread Alex Deucher

NGG (Next Generation Graphics) is a new feature in GFX9.0.  This
adds the relevant parameters.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 29 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 21 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  7 +++
 include/uapi/drm/amdgpu_drm.h   |  8 
 4 files changed, 65 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f605219..ad0e224 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -105,6 +105,11 @@ extern char *amdgpu_disable_cu;
 extern char *amdgpu_virtual_display;
 extern unsigned amdgpu_pp_feature_mask;
 extern int amdgpu_vram_page_split;
+extern int amdgpu_ngg;
+extern int amdgpu_prim_buf_per_se;
+extern int amdgpu_pos_buf_per_se;
+extern int amdgpu_cntl_sb_buf_per_se;
+extern int amdgpu_param_buf_per_se;
 
 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
 #define AMDGPU_MAX_USEC_TIMEOUT10  /* 100 ms */
@@ -959,6 +964,28 @@ struct amdgpu_gfx_funcs {
void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, 
uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
 };
 
+struct amdgpu_ngg_buf {
+   struct amdgpu_bo*bo;
+   uint64_tgpu_addr;
+   uint32_tsize;
+   uint32_tbo_size;
+};
+
+enum {
+   PRIM = 0,
+   POS,
+   CNTL,
+   PARAM,
+   NGG_BUF_MAX
+};
+
+struct amdgpu_ngg {
+   struct amdgpu_ngg_buf   buf[NGG_BUF_MAX];
+   uint32_tgds_reserve_addr;
+   uint32_tgds_reserve_size;
+   boolinit;
+};
+
 struct amdgpu_gfx {
struct mutexgpu_clock_mutex;
struct amdgpu_gfx_configconfig;
@@ -1002,6 +1029,8 @@ struct amdgpu_gfx {
uint32_tgrbm_soft_reset;
uint32_tsrbm_soft_reset;
boolin_reset;
+   /* NGG */
+   struct amdgpu_ngg   ngg;
 };
 
 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 3d0e8b1..ef3ed11 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -103,6 +103,11 @@ unsigned amdgpu_pg_mask = 0x;
 char *amdgpu_disable_cu = NULL;
 char *amdgpu_virtual_display = NULL;
 unsigned amdgpu_pp_feature_mask = 0x;
+int amdgpu_ngg = 0;
+int amdgpu_prim_buf_per_se = 0;
+int amdgpu_pos_buf_per_se = 0;
+int amdgpu_cntl_sb_buf_per_se = 0;
+int amdgpu_param_buf_per_se = 0;
 
 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@@ -213,6 +218,22 @@ MODULE_PARM_DESC(virtual_display,
 "Enable virtual display feature (the virtual_display will be 
set like :xx:xx.x,x;:xx:xx.x,x)");
 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
 
+MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = 
disable(default depending on gfx))");
+module_param_named(ngg, amdgpu_ngg, int, 0444);
+
+MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader 
Engine (default depending on gfx)");
+module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444);
+
+MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader 
Engine (default depending on gfx)");
+module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444);
+
+MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader 
Engine (default depending on gfx)");
+module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
+
+MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per 
Shader Engine (default depending on gfx)");
+module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
+
+
 static const struct pci_device_id pciidlist[] = {
 #ifdef  CONFIG_DRM_AMDGPU_SI
{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 6906322..de0c776 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -542,6 +542,13 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
dev_info.gc_double_offchip_lds_buf =
adev->gfx.config.double_offchip_lds_buf;
 
+   if (amdgpu_ngg) {
+   dev_info.prim_buf_gpu_addr = 
adev->gfx.ngg.buf[PRIM].gpu_addr;
+   dev_info.pos_buf_gpu_addr = 
adev->gfx.ngg.buf[POS].gpu_addr;
+   dev_info.cntl_sb_buf_gpu_addr = 
adev->gfx.ngg.buf[CNTL

[PATCH 076/100] drm/amdgpu: add kiq ring for gfx9

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

Allocate KIQ ring in sw_init for gfx9.

Signed-off-by: Xiangliang Yu 
Signed-off-by: Monk Liu 
Reviewed-by: Alex Deucher 
Reviewed-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 88 +++
 1 file changed, 88 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 4704524..ad88c4b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -576,6 +576,74 @@ static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
return 0;
 }
 
+static void gfx_v9_0_kiq_fini(struct amdgpu_device *adev)
+{
+   struct amdgpu_kiq *kiq = &adev->gfx.kiq;
+
+   amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
+}
+
+static int gfx_v9_0_kiq_init(struct amdgpu_device *adev)
+{
+   int r;
+   u32 *hpd;
+   struct amdgpu_kiq *kiq = &adev->gfx.kiq;
+
+   r = amdgpu_bo_create_kernel(adev, MEC_HPD_SIZE, PAGE_SIZE,
+   AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
+   &kiq->eop_gpu_addr, (void **)&hpd);
+   if (r) {
+   dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
+   return r;
+   }
+
+   memset(hpd, 0, MEC_HPD_SIZE);
+
+   amdgpu_bo_kunmap(kiq->eop_obj);
+
+   return 0;
+}
+
+static int gfx_v9_0_kiq_init_ring(struct amdgpu_device *adev,
+ struct amdgpu_ring *ring,
+ struct amdgpu_irq_src *irq)
+{
+   int r = 0;
+
+   r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs);
+   if (r)
+   return r;
+
+   ring->adev = NULL;
+   ring->ring_obj = NULL;
+   ring->use_doorbell = true;
+   ring->doorbell_index = AMDGPU_DOORBELL_KIQ;
+   if (adev->gfx.mec2_fw) {
+   ring->me = 2;
+   ring->pipe = 0;
+   } else {
+   ring->me = 1;
+   ring->pipe = 1;
+   }
+
+   irq->data = ring;
+   ring->queue = 0;
+   sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue);
+   r = amdgpu_ring_init(adev, ring, 1024,
+irq, AMDGPU_CP_KIQ_IRQ_DRIVER0);
+   if (r)
+   dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
+
+   return r;
+}
+static void gfx_v9_0_kiq_free_ring(struct amdgpu_ring *ring,
+  struct amdgpu_irq_src *irq)
+{
+   amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
+   amdgpu_ring_fini(ring);
+   irq->data = NULL;
+}
+
 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, 
uint32_t wave, uint32_t address)
 {
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_INDEX),
@@ -898,6 +966,7 @@ static int gfx_v9_0_sw_init(void *handle)
 {
int i, r;
struct amdgpu_ring *ring;
+   struct amdgpu_kiq *kiq;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
/* EOP Event */
@@ -971,6 +1040,19 @@ static int gfx_v9_0_sw_init(void *handle)
return r;
}
 
+   if (amdgpu_sriov_vf(adev)) {
+   r = gfx_v9_0_kiq_init(adev);
+   if (r) {
+   DRM_ERROR("Failed to init KIQ BOs!\n");
+   return r;
+   }
+
+   kiq = &adev->gfx.kiq;
+   r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
+   if (r)
+   return r;
+   }
+
/* reserve GDS, GWS and OA resource for gfx */
r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
@@ -1016,6 +1098,11 @@ static int gfx_v9_0_sw_fini(void *handle)
for (i = 0; i < adev->gfx.num_compute_rings; i++)
amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
 
+   if (amdgpu_sriov_vf(adev)) {
+   gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
+   gfx_v9_0_kiq_fini(adev);
+   }
+
gfx_v9_0_mec_fini(adev);
gfx_v9_0_ngg_fini(adev);
 
@@ -1577,6 +1664,7 @@ static void gfx_v9_0_cp_compute_enable(struct 
amdgpu_device *adev, bool enable)
(CP_MEC_CNTL__MEC_ME1_HALT_MASK | 
CP_MEC_CNTL__MEC_ME2_HALT_MASK));
for (i = 0; i < adev->gfx.num_compute_rings; i++)
adev->gfx.compute_ring[i].ready = false;
+   adev->gfx.kiq.ring.ready = false;
}
udelay(50);
 }
-- 
2.5.5

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[PATCH 100/100] drm/amdgpu/gfx9: correct wptr pointer value

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

Wptr number should be align with buf_mask, otherwise will point
to wrong place.

Signed-off-by: Xiangliang Yu 
Signed-off-by: Monk Liu 
Reviewed-by: Ken Wang 
Reviewed-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 8e5367d..ad82ab7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3275,7 +3275,7 @@ static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct 
amdgpu_ring *ring)
amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
amdgpu_ring_write(ring, 0); /* discard following DWs if 
*cond_exec_gpu_addr==0 */
-   ret = ring->wptr;
+   ret = ring->wptr & ring->buf_mask;
amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
return ret;
 }
@@ -3283,9 +3283,10 @@ static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct 
amdgpu_ring *ring)
 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, 
unsigned offset)
 {
unsigned cur;
+   BUG_ON(offset > ring->buf_mask);
BUG_ON(ring->ring[offset] != 0x55aa55aa);
 
-   cur = ring->wptr - 1;
+   cur = (ring->wptr & ring->buf_mask) - 1;
if (likely(cur > offset))
ring->ring[offset] = cur - offset;
else
-- 
2.5.5

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[PATCH 069/100] drm/amd/display: need to handle DCE_Info table ver4.2

2017-03-20 Thread Alex Deucher

From: Charlene Liu 

Signed-off-by: Charlene Liu 
Acked-by: Harry Wentland 
Reviewed-by: Krunoslav Kovac 
Acked-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 79 +-
 1 file changed, 78 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c 
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index f6e77da..123942f 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -1137,6 +1137,81 @@ static enum bp_result get_ss_info_v4_1(
return result;
 }
 
+static enum bp_result get_ss_info_v4_2(
+   struct bios_parser *bp,
+   uint32_t id,
+   uint32_t index,
+   struct spread_spectrum_info *ss_info)
+{
+   enum bp_result result = BP_RESULT_OK;
+   struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
+   struct atom_smu_info_v3_1 *smu_tbl = NULL;
+
+   if (!ss_info)
+   return BP_RESULT_BADINPUT;
+
+   if (!DATA_TABLES(dce_info))
+   return BP_RESULT_BADBIOSTABLE;
+
+   if (!DATA_TABLES(smu_info))
+   return BP_RESULT_BADBIOSTABLE;
+
+   disp_cntl_tbl =  GET_IMAGE(struct atom_display_controller_info_v4_2,
+   DATA_TABLES(dce_info));
+   if (!disp_cntl_tbl)
+   return BP_RESULT_BADBIOSTABLE;
+
+   smu_tbl =  GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info));
+   if (!smu_tbl)
+   return BP_RESULT_BADBIOSTABLE;
+
+
+   ss_info->type.STEP_AND_DELAY_INFO = false;
+   ss_info->spread_percentage_divider = 1000;
+   /* BIOS no longer uses target clock.  Always enable for now */
+   ss_info->target_clock_range = 0x;
+
+   switch (id) {
+   case AS_SIGNAL_TYPE_DVI:
+   ss_info->spread_spectrum_percentage =
+   disp_cntl_tbl->dvi_ss_percentage;
+   ss_info->spread_spectrum_range =
+   disp_cntl_tbl->dvi_ss_rate_10hz * 10;
+   if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
+   ss_info->type.CENTER_MODE = true;
+   break;
+   case AS_SIGNAL_TYPE_HDMI:
+   ss_info->spread_spectrum_percentage =
+   disp_cntl_tbl->hdmi_ss_percentage;
+   ss_info->spread_spectrum_range =
+   disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
+   if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
+   ss_info->type.CENTER_MODE = true;
+   break;
+   /* TODO LVDS not support anymore? */
+   case AS_SIGNAL_TYPE_DISPLAY_PORT:
+   ss_info->spread_spectrum_percentage =
+   disp_cntl_tbl->dp_ss_percentage;
+   ss_info->spread_spectrum_range =
+   disp_cntl_tbl->dp_ss_rate_10hz * 10;
+   if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
+   ss_info->type.CENTER_MODE = true;
+   break;
+   case AS_SIGNAL_TYPE_GPU_PLL:
+   ss_info->spread_spectrum_percentage =
+   smu_tbl->gpuclk_ss_percentage;
+   ss_info->spread_spectrum_range =
+   smu_tbl->gpuclk_ss_rate_10hz * 10;
+   if (smu_tbl->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
+   ss_info->type.CENTER_MODE = true;
+   break;
+   default:
+   result = BP_RESULT_UNSUPPORTED;
+   }
+
+   return result;
+}
+
 /**
  * bios_parser_get_spread_spectrum_info
  * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
@@ -1177,6 +1252,8 @@ static enum bp_result 
bios_parser_get_spread_spectrum_info(
switch (tbl_revision.minor) {
case 1:
return get_ss_info_v4_1(bp, signal, index, ss_info);
+   case 2:
+   return get_ss_info_v4_2(bp, signal, index, ss_info);
default:
break;
}
@@ -1579,7 +1656,7 @@ static enum bp_result get_firmware_info_v3_1(
/* Hardcode frequency if BIOS gives no DCE Ref Clk */
if (info->pll_info.crystal_frequency == 0)
info->pll_info.crystal_frequency = 27000;
-
+   /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, 
but we don't use it*/
info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
 
-- 
2.5.5

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[PATCH 065/100] drm/amd/display: Add DCE12 i2c/aux support

2017-03-20 Thread Alex Deucher

From: Harry Wentland 

Signed-off-by: Harry Wentland 
Signed-off-by: Alex Deucher 
---
 .../amd/display/dc/i2caux/dce120/i2caux_dce120.c   | 125 +
 .../amd/display/dc/i2caux/dce120/i2caux_dce120.h   |  32 ++
 2 files changed, 157 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.h

diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c 
b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
new file mode 100644
index 000..9119829
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright 2012-16 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "include/i2caux_interface.h"
+#include "../i2caux.h"
+#include "../engine.h"
+#include "../i2c_engine.h"
+#include "../i2c_sw_engine.h"
+#include "../i2c_hw_engine.h"
+
+#include "../dce110/i2c_hw_engine_dce110.h"
+#include "../dce110/aux_engine_dce110.h"
+#include "../dce110/i2caux_dce110.h"
+
+#include "vega10/DC/dce_12_0_offset.h"
+#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "vega10/soc15ip.h"
+
+/* begin *
+ * macros to expend register list macro defined in HW object header file */
+
+#define BASE_INNER(seg) \
+   DCE_BASE__INST0_SEG ## seg
+
+/* compile time expand base address. */
+#define BASE(seg) \
+   BASE_INNER(seg)
+
+#define SR(reg_name)\
+   .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
+   mm ## reg_name
+
+#define SRI(reg_name, block, id)\
+   .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+   mm ## block ## id ## _ ## reg_name
+/* macros to expend register list macro defined in HW object header file
+ * end */
+
+#define aux_regs(id)\
+[id] = {\
+   AUX_COMMON_REG_LIST(id), \
+   .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK \
+}
+
+static const struct dce110_aux_registers dce120_aux_regs[] = {
+   aux_regs(0),
+   aux_regs(1),
+   aux_regs(2),
+   aux_regs(3),
+   aux_regs(4),
+   aux_regs(5),
+};
+
+#define hw_engine_regs(id)\
+{\
+   I2C_HW_ENGINE_COMMON_REG_LIST(id) \
+}
+
+static const struct dce110_i2c_hw_engine_registers dce120_hw_engine_regs[] = {
+   hw_engine_regs(1),
+   hw_engine_regs(2),
+   hw_engine_regs(3),
+   hw_engine_regs(4),
+   hw_engine_regs(5),
+   hw_engine_regs(6)
+};
+
+static const struct dce110_i2c_hw_engine_shift i2c_shift = {
+   I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
+};
+
+static const struct dce110_i2c_hw_engine_mask i2c_mask = {
+   I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
+};
+
+struct i2caux *dal_i2caux_dce120_create(
+   struct dc_context *ctx)
+{
+   struct i2caux_dce110 *i2caux_dce110 =
+   dm_alloc(sizeof(struct i2caux_dce110));
+
+   if (!i2caux_dce110) {
+   ASSERT_CRITICAL(false);
+   return NULL;
+   }
+
+   if (dal_i2caux_dce110_construct(
+   i2caux_dce110,
+   ctx,
+   dce120_aux_regs,
+   dce120_hw_engine_regs,
+   &i2c_shift,
+   &i2c_mask))
+   return &i2caux_dce110->base;
+
+   ASSERT_CRITICAL(false);
+
+   dm_free(i2caux_dce110);
+
+   return NULL;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.h 
b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.h
new file mode 100644
index 000..b6ac476
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/

[PATCH 037/100] drm/amdgpu: add tiling flags for GFX9

2017-03-20 Thread Alex Deucher

Signed-off-by: Alex Deucher 
---
 include/uapi/drm/amdgpu_drm.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 7cfdbd8..289b129 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -228,7 +228,11 @@ struct drm_amdgpu_gem_userptr {
 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK   0x3
 #define AMDGPU_TILING_NUM_BANKS_SHIFT  21
 #define AMDGPU_TILING_NUM_BANKS_MASK   0x3
+/* Tiling flags for GFX9. */
+#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT   0
+#define AMDGPU_TILING_SWIZZLE_MODE_MASK0x1f
 
+/* Set/Get helpers for tiling flags. */
 #define AMDGPU_TILING_SET(field, value) \
(((value) & AMDGPU_TILING_##field##_MASK) << 
AMDGPU_TILING_##field##_SHIFT)
 #define AMDGPU_TILING_GET(value, field) \
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 077/100] drm/amdgpu/gfx9: fullfill kiq funcs

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

Fullfill kiq funcs to support kiq ring.

Signed-off-by: Xiangliang Yu 
Signed-off-by: Monk Liu 
Reviewed-by: Alex Deucher 
Reviewed-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 79 +++
 1 file changed, 79 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ad88c4b..987587a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2696,6 +2696,31 @@ static void gfx_v9_0_ring_set_wptr_compute(struct 
amdgpu_ring *ring)
}
 }
 
+static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
+u64 seq, unsigned int flags)
+{
+   /* we only allocate 32bit for each seq wb address */
+   BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
+
+   /* write fence seq to the "addr" */
+   amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+   amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
+WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
+   amdgpu_ring_write(ring, lower_32_bits(addr));
+   amdgpu_ring_write(ring, upper_32_bits(addr));
+   amdgpu_ring_write(ring, lower_32_bits(seq));
+
+   if (flags & AMDGPU_FENCE_FLAG_INT) {
+   /* set register to trigger INT */
+   amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+   amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
+WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
+   amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, 
mmCPC_INT_STATUS));
+   amdgpu_ring_write(ring, 0);
+   amdgpu_ring_write(ring, 0x2000); /* src_id is 178 */
+   }
+}
+
 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
 {
amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
@@ -2731,6 +2756,32 @@ static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring 
*ring, uint32_t flags)
amdgpu_ring_write(ring, 0);
 }
 
+static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
+{
+   struct amdgpu_device *adev = ring->adev;
+
+   amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
+   amdgpu_ring_write(ring, 0 | /* src: register*/
+   (5 << 8) |  /* dst: memory */
+   (1 << 20)); /* write confirm */
+   amdgpu_ring_write(ring, reg);
+   amdgpu_ring_write(ring, 0);
+   amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
+   adev->virt.reg_val_offs * 4));
+   amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
+   adev->virt.reg_val_offs * 4));
+}
+
+static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
+ uint32_t val)
+{
+   amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+   amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
+   amdgpu_ring_write(ring, reg);
+   amdgpu_ring_write(ring, 0);
+   amdgpu_ring_write(ring, val);
+}
+
 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
 enum amdgpu_interrupt_state 
state)
 {
@@ -3021,11 +3072,39 @@ static const struct amdgpu_ring_funcs 
gfx_v9_0_ring_funcs_compute = {
.pad_ib = amdgpu_ring_generic_pad_ib,
 };
 
+static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
+   .type = AMDGPU_RING_TYPE_KIQ,
+   .align_mask = 0xff,
+   .nop = PACKET3(PACKET3_NOP, 0x3FFF),
+   .get_rptr = gfx_v9_0_ring_get_rptr_compute,
+   .get_wptr = gfx_v9_0_ring_get_wptr_compute,
+   .set_wptr = gfx_v9_0_ring_set_wptr_compute,
+   .emit_frame_size =
+   20 + /* gfx_v9_0_ring_emit_gds_switch */
+   7 + /* gfx_v9_0_ring_emit_hdp_flush */
+   5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
+   7 + /* gfx_v9_0_ring_emit_pipeline_sync */
+   64 + /* gfx_v9_0_ring_emit_vm_flush */
+   8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, 
vm fence */
+   .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
+   .emit_ib = gfx_v9_0_ring_emit_ib_compute,
+   .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
+   .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
+   .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
+   .test_ring = gfx_v9_0_ring_test_ring,
+   .test_ib = gfx_v9_0_ring_test_ib,
+   .insert_nop = amdgpu_ring_insert_nop,
+   .pad_ib = amdgpu_ring_generic_pad_ib,
+   .emit_rreg = gfx_v9_0_ring_emit_rreg,
+   .emit_wreg = gfx_v9_0_ring_emit_wreg,
+};
 
 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
 {
int i;
 
+   adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
+
for (i = 0; i <

[PATCH 051/100] drm/amdgpu: add initial vce 4.0 support for vega10

2017-03-20 Thread Alex Deucher

From: Leo Liu 

Signed-off-by: Leo Liu 
Reviewed-by: Alex Deucher 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/Makefile |   3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c |   7 +
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c   | 894 
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.h   |  29 ++
 4 files changed, 932 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v4_0.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 65829fa..2ba5671 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -90,7 +90,8 @@ amdgpu-y += \
 # add VCE block
 amdgpu-y += \
amdgpu_vce.o \
-   vce_v3_0.o
+   vce_v3_0.o \
+   vce_v4_0.o
 
 # add amdkfd interfaces
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index c46116c..647944b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -54,6 +54,8 @@
 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_vce.bin"
 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_vce.bin"
 
+#define FIRMWARE_VEGA10"amdgpu/vega10_vce.bin"
+
 #ifdef CONFIG_DRM_AMDGPU_CIK
 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
 MODULE_FIRMWARE(FIRMWARE_KABINI);
@@ -69,6 +71,8 @@ MODULE_FIRMWARE(FIRMWARE_POLARIS10);
 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
 
+MODULE_FIRMWARE(FIRMWARE_VEGA10);
+
 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
 
 /**
@@ -123,6 +127,9 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned 
long size)
case CHIP_POLARIS11:
fw_name = FIRMWARE_POLARIS11;
break;
+   case CHIP_VEGA10:
+   fw_name = FIRMWARE_VEGA10;
+   break;
case CHIP_POLARIS12:
fw_name = FIRMWARE_POLARIS12;
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
new file mode 100644
index 000..74146be
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -0,0 +1,894 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ */
+
+#include 
+#include 
+#include "amdgpu.h"
+#include "amdgpu_vce.h"
+#include "soc15d.h"
+#include "soc15_common.h"
+
+#include "vega10/soc15ip.h"
+#include "vega10/VCE/vce_4_0_offset.h"
+#include "vega10/VCE/vce_4_0_default.h"
+#include "vega10/VCE/vce_4_0_sh_mask.h"
+#include "vega10/MMHUB/mmhub_1_0_offset.h"
+#include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
+
+#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK  0x02
+
+#define VCE_V4_0_FW_SIZE   (384 * 1024)
+#define VCE_V4_0_STACK_SIZE(64 * 1024)
+#define VCE_V4_0_DATA_SIZE ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES) + (52 * 
1024))
+
+static void vce_v4_0_mc_resume(struct amdgpu_device *adev);
+static void vce_v4_0_set_ring_funcs(struct amdgpu_device *adev);
+static void vce_v4_0_set_irq_funcs(struct amdgpu_device *adev);
+
+/**
+ * vce_v4_0_ring_get_rptr - get read pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware read pointer
+ */
+static uint64_t vce_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
+{
+   struct amdgpu_device *adev = ring->adev;
+
+   if (ring == &adev->vce.ring[0])
+   return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR));
+   else if (ring == &adev->vce.ring[1])
+   return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2));
+   else
+   return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3));
+}
+
+/**
+ * vce_v4_0_ring_get_wptr - get write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns t

[PATCH 061/100] drm/amd/powerplay: add some display/powerplay interfaces

2017-03-20 Thread Alex Deucher

From: Eric Huang 

New interfaces needed to handle the new clock trees and
bandwidth requirements on vega10.

Signed-off-by: Eric Huang 
Acked-by: Alex Deucher 
Acked-by: Tony Cheng 
Acked-by: Harry Wentland 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 94 ++
 .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  | 49 +++
 drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h  | 28 ++-
 .../gpu/drm/amd/powerplay/inc/hardwaremanager.h| 11 +++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  | 10 +++
 5 files changed, 191 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 985ed21..9e84031 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1349,6 +1349,100 @@ int amd_powerplay_get_clock_by_type(void *handle, enum 
amd_pp_clock_type type, s
return ret;
 }
 
+int amd_powerplay_get_clock_by_type_with_latency(void *handle,
+   enum amd_pp_clock_type type,
+   struct pp_clock_levels_with_latency *clocks)
+{
+   struct pp_hwmgr *hwmgr;
+   struct pp_instance *pp_handle = (struct pp_instance *)handle;
+   int ret = 0;
+
+   ret = pp_check(pp_handle);
+   if (ret != 0)
+   return ret;
+
+   if (!clocks)
+   return -EINVAL;
+
+   mutex_lock(&pp_handle->pp_lock);
+   hwmgr = ((struct pp_instance *)handle)->hwmgr;
+   ret = phm_get_clock_by_type_with_latency(hwmgr, type, clocks);
+   mutex_unlock(&pp_handle->pp_lock);
+   return ret;
+}
+
+int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
+   enum amd_pp_clock_type type,
+   struct pp_clock_levels_with_voltage *clocks)
+{
+   struct pp_hwmgr *hwmgr;
+   struct pp_instance *pp_handle = (struct pp_instance *)handle;
+   int ret = 0;
+
+   ret = pp_check(pp_handle);
+   if (ret != 0)
+   return ret;
+
+   if (!clocks)
+   return -EINVAL;
+
+   hwmgr = ((struct pp_instance *)handle)->hwmgr;
+
+   mutex_lock(&pp_handle->pp_lock);
+
+   ret = phm_get_clock_by_type_with_voltage(hwmgr, type, clocks);
+
+   mutex_unlock(&pp_handle->pp_lock);
+   return ret;
+}
+
+int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
+   struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
+{
+   struct pp_hwmgr *hwmgr;
+   struct pp_instance *pp_handle = (struct pp_instance *)handle;
+   int ret = 0;
+
+   ret = pp_check(pp_handle);
+   if (ret != 0)
+   return ret;
+
+   if (!wm_with_clock_ranges)
+   return -EINVAL;
+
+   hwmgr = ((struct pp_instance *)handle)->hwmgr;
+
+   mutex_lock(&pp_handle->pp_lock);
+   ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
+   wm_with_clock_ranges);
+   mutex_unlock(&pp_handle->pp_lock);
+
+   return ret;
+}
+
+int amd_powerplay_display_clock_voltage_request(void *handle,
+   struct pp_display_clock_request *clock)
+{
+   struct pp_hwmgr *hwmgr;
+   struct pp_instance *pp_handle = (struct pp_instance *)handle;
+   int ret = 0;
+
+   ret = pp_check(pp_handle);
+   if (ret != 0)
+   return ret;
+
+   if (!clock)
+   return -EINVAL;
+
+   hwmgr = ((struct pp_instance *)handle)->hwmgr;
+
+   mutex_lock(&pp_handle->pp_lock);
+   ret = phm_display_clock_voltage_request(hwmgr, clock);
+   mutex_unlock(&pp_handle->pp_lock);
+
+   return ret;
+}
+
 int amd_powerplay_get_display_mode_validation_clocks(void *handle,
struct amd_pp_simple_clock_info *clocks)
 {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index 6013ef1..0a2076e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -443,6 +443,55 @@ int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum 
amd_pp_clock_type type, s
 
 }
 
+int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
+   enum amd_pp_clock_type type,
+   struct pp_clock_levels_with_latency *clocks)
+{
+   PHM_FUNC_CHECK(hwmgr);
+
+   if (hwmgr->hwmgr_func->get_clock_by_type_with_latency == NULL)
+   return -EINVAL;
+
+   return hwmgr->hwmgr_func->get_clock_by_type_with_latency(hwmgr, type, 
clocks);
+
+}
+
+int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
+   enum amd_pp_clock_type type,
+   struct pp_clock_levels_with_voltage *clocks)
+{
+   PHM_FUNC_CHECK(hwmgr);
+
+   if (hwmgr->hwmgr_func->get_clock_by_type_with_voltage == NULL)
+   return -EINVAL;
+
+   return hwmgr->hwmgr_func->get_clock_by_type_with_voltage(hwmgr, type, 
clocks);

[PATCH 024/100] drm/amdgpu: add common soc15 headers

2017-03-20 Thread Alex Deucher

From: Ken Wang 

These are used by various IP modules.

Signed-off-by: Ken Wang 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/soc15.h|  35 
 drivers/gpu/drm/amd/amdgpu/soc15_common.h |  57 ++
 drivers/gpu/drm/amd/amdgpu/soc15d.h   | 285 ++
 3 files changed, 377 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15.h
 create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15_common.h
 create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15d.h

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h 
b/drivers/gpu/drm/amd/amdgpu/soc15.h
new file mode 100644
index 000..378a46d
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __SOC15_H__
+#define __SOC15_H__
+
+#include "nbio_v6_1.h"
+
+extern const struct amd_ip_funcs soc15_common_ip_funcs;
+
+void soc15_grbm_select(struct amdgpu_device *adev,
+   u32 me, u32 pipe, u32 queue, u32 vmid);
+int soc15_set_ip_blocks(struct amdgpu_device *adev);
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h 
b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
new file mode 100644
index 000..2b96c80
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __SOC15_COMMON_H__
+#define __SOC15_COMMON_H__
+
+struct nbio_hdp_flush_reg {
+   u32 hdp_flush_req_offset;
+   u32 hdp_flush_done_offset;
+   u32 ref_and_mask_cp0;
+   u32 ref_and_mask_cp1;
+   u32 ref_and_mask_cp2;
+   u32 ref_and_mask_cp3;
+   u32 ref_and_mask_cp4;
+   u32 ref_and_mask_cp5;
+   u32 ref_and_mask_cp6;
+   u32 ref_and_mask_cp7;
+   u32 ref_and_mask_cp8;
+   u32 ref_and_mask_cp9;
+   u32 ref_and_mask_sdma0;
+   u32 ref_and_mask_sdma1;
+};
+
+struct nbio_pcie_index_data {
+   u32 index_offset;
+   u32 data_offset;
+};
+// Register Access Macro
+#define SOC15_REG_OFFSET(ip, inst, reg)   (0 == reg##_BASE_IDX ? 
ip##_BASE__INST##inst##_SEG0 + reg : \
+(1 == reg##_BASE_IDX ? 
ip##_BASE__INST##inst##_SEG1 + reg : \
+(2 == reg##_BASE_IDX ? 
ip##_BASE__INST##inst##_SEG2 + reg : \
+(3 == reg##_BASE_IDX ? 
ip##_BASE__INST##inst##_SEG3 + reg : \
+
(ip##_BASE__INST##inst##_SEG4 + reg)
+
+#endif
+
+
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h 
b/drivers/gpu/drm/amd/amdgpu/soc15d.h
new file mode 100644
index 000..c47715d
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h
@@ -0,0 +1,285 @@
+/*
+ * Copyri

[PATCH 064/100] drm/amd/display: Add DCE12 gpio support

2017-03-20 Thread Alex Deucher

From: Harry Wentland 

Signed-off-by: Harry Wentland 
Signed-off-by: Alex Deucher 
---
 .../amd/display/dc/gpio/dce120/hw_factory_dce120.c | 197 ++
 .../amd/display/dc/gpio/dce120/hw_factory_dce120.h |  32 ++
 .../display/dc/gpio/dce120/hw_translate_dce120.c   | 408 +
 .../display/dc/gpio/dce120/hw_translate_dce120.h   |  34 ++
 4 files changed, 671 insertions(+)
 create mode 100644 
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.h
 create mode 100644 
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.h

diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c 
b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
new file mode 100644
index 000..4ced9a7
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright 2013-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "include/gpio_types.h"
+#include "../hw_factory.h"
+
+
+#include "../hw_gpio.h"
+#include "../hw_ddc.h"
+#include "../hw_hpd.h"
+
+#include "hw_factory_dce120.h"
+
+#include "vega10/DC/dce_12_0_offset.h"
+#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "vega10/soc15ip.h"
+
+#define block HPD
+#define reg_num 0
+
+/* set field name */
+#define SF_HPD(reg_name, field_name, post_fix)\
+   .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
+
+/* set field name */
+#define SF_HPD(reg_name, field_name, post_fix)\
+   .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
+
+#define BASE_INNER(seg) \
+   DCE_BASE__INST0_SEG ## seg
+
+/* compile time expand base address. */
+#define BASE(seg) \
+   BASE_INNER(seg)
+
+#define REG(reg_name)\
+   BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
+
+#define REGI(reg_name, block, id)\
+   BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+   mm ## block ## id ## _ ## reg_name
+
+
+#include "reg_helper.h"
+#include "../hpd_regs.h"
+
+#define hpd_regs(id) \
+{\
+   HPD_REG_LIST(id)\
+}
+
+static const struct hpd_registers hpd_regs[] = {
+   hpd_regs(0),
+   hpd_regs(1),
+   hpd_regs(2),
+   hpd_regs(3),
+   hpd_regs(4),
+   hpd_regs(5)
+};
+
+static const struct hpd_sh_mask hpd_shift = {
+   HPD_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct hpd_sh_mask hpd_mask = {
+   HPD_MASK_SH_LIST(_MASK)
+};
+
+#include "../ddc_regs.h"
+
+ /* set field name */
+#define SF_DDC(reg_name, field_name, post_fix)\
+   .field_name = reg_name ## __ ## field_name ## post_fix
+
+static const struct ddc_registers ddc_data_regs[] = {
+   ddc_data_regs(1),
+   ddc_data_regs(2),
+   ddc_data_regs(3),
+   ddc_data_regs(4),
+   ddc_data_regs(5),
+   ddc_data_regs(6),
+   ddc_vga_data_regs,
+   ddc_i2c_data_regs
+};
+
+static const struct ddc_registers ddc_clk_regs[] = {
+   ddc_clk_regs(1),
+   ddc_clk_regs(2),
+   ddc_clk_regs(3),
+   ddc_clk_regs(4),
+   ddc_clk_regs(5),
+   ddc_clk_regs(6),
+   ddc_vga_clk_regs,
+   ddc_i2c_clk_regs
+};
+
+static const struct ddc_sh_mask ddc_shift = {
+   DDC_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct ddc_sh_mask ddc_mask = {
+   DDC_MASK_SH_LIST(_MASK)
+};
+
+static void define_ddc_registers(
+   struct hw_gpio_pin *pin,
+   uint32_t en)
+{
+   struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
+
+   switch (pin->id) {
+   case GPIO_ID_DDC_DATA:
+   ddc->regs = &ddc_data_regs[en];
+   ddc->base.regs = &ddc_data_regs[en].gpio;
+   break;
+   case GPIO_ID

[PATCH 033/100] drm/amdgpu: add IV trace point

2017-03-20 Thread Alex Deucher

From: Christian König 

This allows us to grab IVs without spamming the log.

Signed-off-by: Christian König 
Reviewed-by: Felix Kuehling 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c   |  3 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 37 +++
 2 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 9c98bee..1309886 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -33,6 +33,7 @@
 #include "amdgpu_ih.h"
 #include "atom.h"
 #include "amdgpu_connectors.h"
+#include "amdgpu_trace.h"
 
 #include 
 
@@ -367,6 +368,8 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev,
struct amdgpu_irq_src *src;
int r;
 
+   trace_amdgpu_iv(entry);
+
if (client_id >= AMDGPU_IH_CLIENTID_MAX) {
DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
return;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 03f598e..6d0a598 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -49,6 +49,43 @@ TRACE_EVENT(amdgpu_mm_wreg,
  (unsigned long)__entry->value)
 );
 
+TRACE_EVENT(amdgpu_iv,
+   TP_PROTO(struct amdgpu_iv_entry *iv),
+   TP_ARGS(iv),
+   TP_STRUCT__entry(
+__field(unsigned, client_id)
+__field(unsigned, src_id)
+__field(unsigned, ring_id)
+__field(unsigned, vm_id)
+__field(unsigned, vm_id_src)
+__field(uint64_t, timestamp)
+__field(unsigned, timestamp_src)
+__field(unsigned, pas_id)
+__array(unsigned, src_data, 4)
+   ),
+   TP_fast_assign(
+  __entry->client_id = iv->client_id;
+  __entry->src_id = iv->src_id;
+  __entry->ring_id = iv->ring_id;
+  __entry->vm_id = iv->vm_id;
+  __entry->vm_id_src = iv->vm_id_src;
+  __entry->timestamp = iv->timestamp;
+  __entry->timestamp_src = iv->timestamp_src;
+  __entry->pas_id = iv->pas_id;
+  __entry->src_data[0] = iv->src_data[0];
+  __entry->src_data[1] = iv->src_data[1];
+  __entry->src_data[2] = iv->src_data[2];
+  __entry->src_data[3] = iv->src_data[3];
+  ),
+   TP_printk("client_id:%u src_id:%u ring:%u vm_id:%u timestamp: %llu 
pas_id:%u src_data: %08x %08x %08x %08x\n",
+ __entry->client_id, __entry->src_id,
+ __entry->ring_id, __entry->vm_id,
+ __entry->timestamp, __entry->pas_id,
+ __entry->src_data[0], __entry->src_data[1],
+ __entry->src_data[2], __entry->src_data[3])
+);
+
+
 TRACE_EVENT(amdgpu_bo_create,
TP_PROTO(struct amdgpu_bo *bo),
TP_ARGS(bo),
-- 
2.5.5

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[PATCH 079/100] drm/amdgpu: init kiq and kcq for vega10

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

Init kiq via cpu mmio and init kcq through kiq.

Signed-off-by: Xiangliang Yu 
Signed-off-by: Monk Liu 
Reviewed-by: Alex Deucher 
Acked-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 464 +-
 drivers/gpu/drm/amd/amdgpu/soc15d.h   |   2 +
 2 files changed, 465 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d694af1..2f833ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -644,6 +644,60 @@ static void gfx_v9_0_kiq_free_ring(struct amdgpu_ring 
*ring,
irq->data = NULL;
 }
 
+/* create MQD for each compute queue */
+static int gfx_v9_0_compute_mqd_soft_init(struct amdgpu_device *adev)
+{
+   struct amdgpu_ring *ring = NULL;
+   int r, i;
+
+   /* create MQD for KIQ */
+   ring = &adev->gfx.kiq.ring;
+   if (!ring->mqd_obj) {
+   r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), 
PAGE_SIZE,
+   AMDGPU_GEM_DOMAIN_GTT, 
&ring->mqd_obj,
+   &ring->mqd_gpu_addr, (void 
**)&ring->mqd_ptr);
+   if (r) {
+   dev_warn(adev->dev, "failed to create ring mqd ob 
(%d)", r);
+   return r;
+   }
+
+   /*TODO: prepare MQD backup */
+   }
+
+   /* create MQD for each KCQ */
+   for (i = 0; i < adev->gfx.num_compute_rings; i++)
+   {
+   ring = &adev->gfx.compute_ring[i];
+   if (!ring->mqd_obj) {
+   r = amdgpu_bo_create_kernel(adev, sizeof(struct 
v9_mqd), PAGE_SIZE,
+   AMDGPU_GEM_DOMAIN_GTT, 
&ring->mqd_obj,
+   &ring->mqd_gpu_addr, 
(void **)&ring->mqd_ptr);
+   if (r) {
+   dev_warn(adev->dev, "failed to create ring mqd 
ob (%d)", r);
+   return r;
+   }
+
+   /* TODO: prepare MQD backup */
+   }
+   }
+
+   return 0;
+}
+
+static void gfx_v9_0_compute_mqd_soft_fini(struct amdgpu_device *adev)
+{
+   struct amdgpu_ring *ring = NULL;
+   int i;
+
+   for (i = 0; i < adev->gfx.num_compute_rings; i++) {
+   ring = &adev->gfx.compute_ring[i];
+   amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, 
(void **)&ring->mqd_ptr);
+   }
+
+   ring = &adev->gfx.kiq.ring;
+   amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void 
**)&ring->mqd_ptr);
+}
+
 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, 
uint32_t wave, uint32_t address)
 {
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_INDEX),
@@ -1051,6 +1105,11 @@ static int gfx_v9_0_sw_init(void *handle)
r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
if (r)
return r;
+
+   /* create MQD for all compute queues as wel as KIQ for SRIOV 
case */
+   r = gfx_v9_0_compute_mqd_soft_init(adev);
+   if (r)
+   return r;
}
 
/* reserve GDS, GWS and OA resource for gfx */
@@ -1099,6 +1158,7 @@ static int gfx_v9_0_sw_fini(void *handle)
amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
 
if (amdgpu_sriov_vf(adev)) {
+   gfx_v9_0_compute_mqd_soft_fini(adev);
gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
gfx_v9_0_kiq_fini(adev);
}
@@ -1757,6 +1817,393 @@ static int gfx_v9_0_cp_compute_resume(struct 
amdgpu_device *adev)
return 0;
 }
 
+/* KIQ functions */
+static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
+{
+   uint32_t tmp;
+   struct amdgpu_device *adev = ring->adev;
+
+   /* tell RLC which is KIQ queue */
+   tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS));
+   tmp &= 0xff00;
+   tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
+   WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), tmp);
+   tmp |= 0x80;
+   WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), tmp);
+}
+
+static void gfx_v9_0_kiq_enable(struct amdgpu_ring *ring)
+{
+   amdgpu_ring_alloc(ring, 8);
+   /* set resources */
+   amdgpu_ring_write(ring, PACKET3(PACKET3_SET_RESOURCES, 6));
+   amdgpu_ring_write(ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */
+   amdgpu_ring_write(ring, 0x00FF);/* queue mask lo */
+   amdgpu_ring_write(ring, 0); /* queue mask hi */
+   amdgpu_ring_write(ring, 0); /* gws mask lo */
+   amdgpu_ring_write(ring, 0); /* gws mask hi */
+   amdgpu_ring_write(ring, 0); /* oac mask */
+   amdgpu_ring_write(ring, 0);

[PATCH 090/100] drm/amdgpu/vega10:fix DOORBELL64 scheme

2017-03-20 Thread Alex Deucher

From: Monk Liu 

Signed-off-by: Monk Liu 
Signed-off-by: Xiangliang Yu 
Reviewed-by: Alex Deucher 
Acked-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 27 ++-
 1 file changed, 18 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 2675480..2e1c782 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -708,15 +708,24 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
AMDGPU_DOORBELL64_IH_RING1= 0xF5,  /* For page 
migration request log */
AMDGPU_DOORBELL64_IH_RING2= 0xF6,  /* For page 
migration translation/invalidation log */
 
-   /* VCN engine */
-   AMDGPU_DOORBELL64_VCN0= 0xF8,
-   AMDGPU_DOORBELL64_VCN1= 0xF9,
-   AMDGPU_DOORBELL64_VCN2= 0xFA,
-   AMDGPU_DOORBELL64_VCN3= 0xFB,
-   AMDGPU_DOORBELL64_VCN4= 0xFC,
-   AMDGPU_DOORBELL64_VCN5= 0xFD,
-   AMDGPU_DOORBELL64_VCN6= 0xFE,
-   AMDGPU_DOORBELL64_VCN7= 0xFF,
+   /* VCN engine use 32 bits doorbell  */
+   AMDGPU_DOORBELL64_VCN0_1  = 0xF8, /* lower 32 bits for 
VNC0 and upper 32 bits for VNC1 */
+   AMDGPU_DOORBELL64_VCN2_3  = 0xF9,
+   AMDGPU_DOORBELL64_VCN4_5  = 0xFA,
+   AMDGPU_DOORBELL64_VCN6_7  = 0xFB,
+
+   /* overlap the doorbell assignment with VCN as they are  mutually 
exclusive
+* VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
+*/
+   AMDGPU_DOORBELL64_RING0_1 = 0xF8,
+   AMDGPU_DOORBELL64_RING2_3 = 0xF9,
+   AMDGPU_DOORBELL64_RING4_5 = 0xFA,
+   AMDGPU_DOORBELL64_RING6_7 = 0xFB,
+
+   AMDGPU_DOORBELL64_UVD_RING0_1 = 0xFC,
+   AMDGPU_DOORBELL64_UVD_RING2_3 = 0xFD,
+   AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFE,
+   AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFF,
 
AMDGPU_DOORBELL64_MAX_ASSIGNMENT  = 0xFF,
AMDGPU_DOORBELL64_INVALID = 0x
-- 
2.5.5

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[PATCH 031/100] drm/amdgpu: use atomfirmware interfaces for scratch reg save/restore

2017-03-20 Thread Alex Deucher

If the board is atomfirmware based.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 20 
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7295cbc..19d37a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2196,7 +2196,10 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
suspend, bool fbcon)
 */
amdgpu_bo_evict_vram(adev);
 
-   amdgpu_atombios_scratch_regs_save(adev);
+   if (adev->is_atom_fw)
+   amdgpu_atomfirmware_scratch_regs_save(adev);
+   else
+   amdgpu_atombios_scratch_regs_save(adev);
pci_save_state(dev->pdev);
if (suspend) {
/* Shut down the device */
@@ -2248,7 +2251,10 @@ int amdgpu_device_resume(struct drm_device *dev, bool 
resume, bool fbcon)
return r;
}
}
-   amdgpu_atombios_scratch_regs_restore(adev);
+   if (adev->is_atom_fw)
+   amdgpu_atomfirmware_scratch_regs_restore(adev);
+   else
+   amdgpu_atombios_scratch_regs_restore(adev);
 
/* post card */
if (amdgpu_need_post(adev)) {
@@ -2655,9 +2661,15 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
amdgpu_display_stop_mc_access(adev, &save);
amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC);
}
-   amdgpu_atombios_scratch_regs_save(adev);
+   if (adev->is_atom_fw)
+   amdgpu_atomfirmware_scratch_regs_save(adev);
+   else
+   amdgpu_atombios_scratch_regs_save(adev);
r = amdgpu_asic_reset(adev);
-   amdgpu_atombios_scratch_regs_restore(adev);
+   if (adev->is_atom_fw)
+   amdgpu_atomfirmware_scratch_regs_restore(adev);
+   else
+   amdgpu_atombios_scratch_regs_restore(adev);
/* post card */
amdgpu_atom_asic_init(adev->mode_info.atom_context);
 
-- 
2.5.5

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[PATCH 083/100] drm/amdgpu/sdma4:re-org SDMA initial steps for sriov

2017-03-20 Thread Alex Deucher

From: Monk Liu 

Rework sdma init to support SR-IOV.

Signed-off-by: Monk Liu 
Signed-off-by: Xiangliang Yu 
Reviewed-by: Alex Deucher 
Acked-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index b460e00..ee3b4a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -522,6 +522,7 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
u32 wb_offset;
u32 doorbell;
u32 doorbell_offset;
+   u32 temp;
int i,r;
 
for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -576,6 +577,16 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
nbio_v6_1_sdma_doorbell_range(adev, i, ring->use_doorbell, 
ring->doorbell_index);
 
+   /* set utc l1 enable flag always to 1 */
+   temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL));
+   temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
+   WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), temp);
+
+   /* unhalt engine */
+   temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL));
+   temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
+   WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), temp);
+
/* enable DMA RB */
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 
1);
WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), 
rb_cntl);
@@ -690,6 +701,15 @@ static int sdma_v4_0_start(struct amdgpu_device *adev)
 {
int r;
 
+   if (amdgpu_sriov_vf(adev)) {
+   /* disable RB and halt engine */
+   sdma_v4_0_enable(adev, false);
+
+   /* set RB registers */
+   r = sdma_v4_0_gfx_resume(adev);
+   return r;
+   }
+
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
DRM_INFO("Loading via direct write\n");
r = sdma_v4_0_load_microcode(adev);
-- 
2.5.5

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[PATCH 072/100] drm/amdgpu: Set the IP blocks for vega10

2017-03-20 Thread Alex Deucher

From: Ken Wang 

Signed-off-by: Ken Wang 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 8e64437..47d1dcc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -50,6 +50,7 @@
 #include "cik.h"
 #endif
 #include "vi.h"
+#include "soc15.h"
 #include "bif/bif_4_1_d.h"
 #include 
 #include 
@@ -1433,6 +1434,13 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
return r;
break;
 #endif
+   case CHIP_VEGA10:
+   adev->family = AMDGPU_FAMILY_AI;
+
+   r = soc15_set_ip_blocks(adev);
+   if (r)
+   return r;
+   break;
default:
/* FIXME: not supported yet */
return -EINVAL;
-- 
2.5.5

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[PATCH 036/100] drm/amdgpu: Add asic family for vega10

2017-03-20 Thread Alex Deucher

Signed-off-by: Alex Deucher 
---
 include/uapi/drm/amdgpu_drm.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 1bf6b29..7cfdbd8 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -805,6 +805,7 @@ struct drm_amdgpu_info_vce_clock_table {
 #define AMDGPU_FAMILY_KV   125 /* Kaveri, Kabini, Mullins 
*/
 #define AMDGPU_FAMILY_VI   130 /* Iceland, Tonga */
 #define AMDGPU_FAMILY_CZ   135 /* Carrizo, Stoney */
+#define AMDGPU_FAMILY_AI   141 /* Vega10 */
 
 /*
  * Definition of free sync enter and exit signals
-- 
2.5.5

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[PATCH 086/100] drm/amdgpu/dce_virtual: bypass DPM for vf

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

If enable DPM for VF, always get lot of warn_slow_patch_null in
dmesg and vf doesn't support DPM.

Signed-off-by: Xiangliang Yu 
Signed-off-by: Monk Liu 
Reviewed-by: Alex Deucher 
Acked-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c 
b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 5ee139c..8bb9cfd 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -204,6 +204,9 @@ static void dce_virtual_crtc_dpms(struct drm_crtc *crtc, 
int mode)
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
unsigned type;
 
+   if (amdgpu_sriov_vf(adev))
+   return;
+
switch (mode) {
case DRM_MODE_DPMS_ON:
amdgpu_crtc->enabled = true;
-- 
2.5.5

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[PATCH 085/100] drm/amdgpu/gmc9: no need use kiq in vega10 tlb flush

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

two reasons:
1. there is a spinlock around;
2. vm register is pf/vf copy, vf can access via mmio safely.

Signed-off-by: Xiangliang Yu 
Signed-off-by: Monk Liu 
Reviewed-by: Alex Deucher 
Reviewed-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 5cf0fc3..51a1919 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -198,11 +198,11 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct 
amdgpu_device *adev,
struct amdgpu_vmhub *hub = &adev->vmhub[i];
u32 tmp = hub->get_invalidate_req(vmid);
 
-   WREG32(hub->vm_inv_eng0_req + eng, tmp);
+   WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
 
/* Busy wait for ACK.*/
for (j = 0; j < 100; j++) {
-   tmp = RREG32(hub->vm_inv_eng0_ack + eng);
+   tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
tmp &= 1 << vmid;
if (tmp)
break;
@@ -213,7 +213,7 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct 
amdgpu_device *adev,
 
/* Wait for ACK with a delay.*/
for (j = 0; j < adev->usec_timeout; j++) {
-   tmp = RREG32(hub->vm_inv_eng0_ack + eng);
+   tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
tmp &= 1 << vmid;
if (tmp)
break;
-- 
2.5.5

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[PATCH 053/100] drm/amdgpu: add psp firmware info into info query and debugfs

2017-03-20 Thread Alex Deucher

From: Huang Rui 

Signed-off-by: Huang Rui 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 25 +
 include/uapi/drm/amdgpu_drm.h   |  4 
 2 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index de0c776..a2f2b7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -209,6 +209,14 @@ static int amdgpu_firmware_info(struct 
drm_amdgpu_info_firmware *fw_info,
fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
fw_info->feature = 
adev->sdma.instance[query_fw->index].feature_version;
break;
+   case AMDGPU_INFO_FW_SOS:
+   fw_info->ver = adev->psp.sos_fw_version;
+   fw_info->feature = adev->psp.sos_feature_version;
+   break;
+   case AMDGPU_INFO_FW_ASD:
+   fw_info->ver = adev->psp.asd_fw_version;
+   fw_info->feature = adev->psp.asd_feature_version;
+   break;
default:
return -EINVAL;
}
@@ -1095,6 +1103,23 @@ static int amdgpu_debugfs_firmware_info(struct seq_file 
*m, void *data)
   fw_info.feature, fw_info.ver);
}
 
+   /* PSP SOS */
+   query_fw.fw_type = AMDGPU_INFO_FW_SOS;
+   ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
+   if (ret)
+   return ret;
+   seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
+  fw_info.feature, fw_info.ver);
+
+
+   /* PSP ASD */
+   query_fw.fw_type = AMDGPU_INFO_FW_ASD;
+   ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
+   if (ret)
+   return ret;
+   seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
+  fw_info.feature, fw_info.ver);
+
/* SMC */
query_fw.fw_type = AMDGPU_INFO_FW_SMC;
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 289b129..7da19cd 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -524,6 +524,10 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_FW_SMC  0x0a
/* Subquery id: Query SDMA firmware version */
#define AMDGPU_INFO_FW_SDMA 0x0b
+   /* Subquery id: Query PSP SOS firmware version */
+   #define AMDGPU_INFO_FW_SOS  0x0c
+   /* Subquery id: Query PSP ASD firmware version */
+   #define AMDGPU_INFO_FW_ASD  0x0d
 /* number of bytes moved for TTM migration */
 #define AMDGPU_INFO_NUM_BYTES_MOVED0x0f
 /* the used VRAM size */
-- 
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[PATCH 099/100] drm/amdgpu/vce4: impl vce & mmsch sriov start

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

For MM sriov, need use MMSCH to init engine and the init procedures
are all saved in mm table.

Signed-off-by: Xiangliang Yu 
Signed-off-by: Monk Liu 
Reviewed-by: Alex Deucher 
Acked-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 205 +-
 1 file changed, 204 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index b1b887e..15321495 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -30,6 +30,7 @@
 #include "amdgpu_vce.h"
 #include "soc15d.h"
 #include "soc15_common.h"
+#include "mmsch_v1_0.h"
 
 #include "vega10/soc15ip.h"
 #include "vega10/VCE/vce_4_0_offset.h"
@@ -48,6 +49,63 @@ static void vce_v4_0_mc_resume(struct amdgpu_device *adev);
 static void vce_v4_0_set_ring_funcs(struct amdgpu_device *adev);
 static void vce_v4_0_set_irq_funcs(struct amdgpu_device *adev);
 
+static inline void mmsch_insert_direct_wt(struct mmsch_v1_0_cmd_direct_write 
*direct_wt,
+ uint32_t *init_table,
+ uint32_t reg_offset,
+ uint32_t value)
+{
+   direct_wt->cmd_header.reg_offset = reg_offset;
+   direct_wt->reg_value = value;
+   memcpy((void *)init_table, direct_wt, sizeof(struct 
mmsch_v1_0_cmd_direct_write));
+}
+
+static inline void mmsch_insert_direct_rd_mod_wt(struct 
mmsch_v1_0_cmd_direct_read_modify_write *direct_rd_mod_wt,
+uint32_t *init_table,
+uint32_t reg_offset,
+uint32_t mask, uint32_t data)
+{
+   direct_rd_mod_wt->cmd_header.reg_offset = reg_offset;
+   direct_rd_mod_wt->mask_value = mask;
+   direct_rd_mod_wt->write_data = data;
+   memcpy((void *)init_table, direct_rd_mod_wt,
+  sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write));
+}
+
+static inline void mmsch_insert_direct_poll(struct 
mmsch_v1_0_cmd_direct_polling *direct_poll,
+   uint32_t *init_table,
+   uint32_t reg_offset,
+   uint32_t mask, uint32_t wait)
+{
+   direct_poll->cmd_header.reg_offset = reg_offset;
+   direct_poll->mask_value = mask;
+   direct_poll->wait_value = wait;
+   memcpy((void *)init_table, direct_poll, sizeof(struct 
mmsch_v1_0_cmd_direct_polling));
+}
+
+#define INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
+   mmsch_insert_direct_rd_mod_wt(&direct_rd_mod_wt, \
+ init_table, (reg), \
+ (mask), (data)); \
+   init_table += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)/4; 
\
+   table_size += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)/4; 
\
+}
+
+#define INSERT_DIRECT_WT(reg, value) { \
+   mmsch_insert_direct_wt(&direct_wt, \
+  init_table, (reg), \
+  (value)); \
+   init_table += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \
+   table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \
+}
+
+#define INSERT_DIRECT_POLL(reg, mask, wait) { \
+   mmsch_insert_direct_poll(&direct_poll, \
+init_table, (reg), \
+(mask), (wait)); \
+   init_table += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \
+   table_size += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \
+}
+
 /**
  * vce_v4_0_ring_get_rptr - get read pointer
  *
@@ -146,6 +204,148 @@ static int vce_v4_0_firmware_loaded(struct amdgpu_device 
*adev)
return -ETIMEDOUT;
 }
 
+static int vce_v4_0_mmsch_start(struct amdgpu_device *adev,
+   struct amdgpu_mm_table *table)
+{
+   uint32_t data = 0, loop;
+   uint64_t addr = table->gpu_addr;
+   struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header 
*)table->cpu_addr;
+   uint32_t size;
+
+   size = header->header_size + header->vce_table_size + 
header->uvd_table_size;
+
+   /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of 
memory descriptor location */
+   WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO), 
lower_32_bits(addr));
+   WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI), 
upper_32_bits(addr));
+
+   /* 2, update vmid of descriptor */
+   data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID));
+   data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK;
+   data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 
for MM scheduler */
+   WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID), data);
+
+   /* 3, notify mmsch about the size of this descriptor *

[PATCH 022/100] drm/amdgpu: add gfx9 clearstate header

2017-03-20 Thread Alex Deucher

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h | 941 +++
 1 file changed, 941 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h

diff --git a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h 
b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
new file mode 100644
index 000..18fd01f
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
@@ -0,0 +1,941 @@
+
+/*
+***
+*
+*  Trade secret of Advanced Micro Devices, Inc.
+*  Copyright (c) 2010 Advanced Micro Devices, Inc. (unpublished)
+*
+*  All rights reserved.  This notice is intended as a precaution against 
inadvertent publication and
+*  does not imply publication or any waiver of confidentiality.  The year 
included in the foregoing
+*  notice is the year of creation of the work.
+*
+***
+*/
+/**
+***
+* @brief gfx9 Clearstate Definitions
+***
+*
+*   Do not edit! This is a machine-generated file!
+*
+*/
+
+static const unsigned int gfx9_SECT_CONTEXT_def_1[] =
+{
+0x, // DB_RENDER_CONTROL
+0x, // DB_COUNT_CONTROL
+0x, // DB_DEPTH_VIEW
+0x, // DB_RENDER_OVERRIDE
+0x, // DB_RENDER_OVERRIDE2
+0x, // DB_HTILE_DATA_BASE
+0x, // DB_HTILE_DATA_BASE_HI
+0x, // DB_DEPTH_SIZE
+0x, // DB_DEPTH_BOUNDS_MIN
+0x, // DB_DEPTH_BOUNDS_MAX
+0x, // DB_STENCIL_CLEAR
+0x, // DB_DEPTH_CLEAR
+0x, // PA_SC_SCREEN_SCISSOR_TL
+0x40004000, // PA_SC_SCREEN_SCISSOR_BR
+0x, // DB_Z_INFO
+0x, // DB_STENCIL_INFO
+0x, // DB_Z_READ_BASE
+0x, // DB_Z_READ_BASE_HI
+0x, // DB_STENCIL_READ_BASE
+0x, // DB_STENCIL_READ_BASE_HI
+0x, // DB_Z_WRITE_BASE
+0x, // DB_Z_WRITE_BASE_HI
+0x, // DB_STENCIL_WRITE_BASE
+0x, // DB_STENCIL_WRITE_BASE_HI
+0x, // DB_DFSM_CONTROL
+0x, // DB_RENDER_FILTER
+0x, // DB_Z_INFO2
+0x, // DB_STENCIL_INFO2
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0x, // TA_BC_BASE_ADDR
+0x, // TA_BC_BASE_ADDR_HI
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0x, // COHER_DEST_BASE_HI_0
+0x, // COHER_DEST_BASE_HI_1
+0x, // COHER_DEST_BASE_HI_2
+0x, // COHER_DEST_BASE_HI_3
+0x, // COHER_DEST_BASE_2
+0x, // COHER_DEST_BASE_3
+0x, // PA_SC_WINDOW_OFFSET
+0x8000, // PA_SC_WINDOW_SCISSOR_TL
+0x40004000, // PA_SC_WINDOW_SCISSOR_BR
+0x, // PA_SC_CLIPRECT_RULE
+0x, // PA_SC_CLIPRECT_0_TL
+0x40004000, // PA_SC_CLIPRECT_0_BR
+0x, // PA_SC_CLIPRECT_1_TL
+0x40004000, // PA_SC_CLIPRECT_1_BR
+0x, // PA_SC_CLIPRECT_2_TL
+0x40004000, // PA_SC_CLIPRECT_2_BR
+0x, // PA_SC_CLIPRECT_3_TL
+0x40004000, // PA_SC_CLIPRECT_3_BR
+0xaa99, // PA_SC_EDGERULE
+0x, // PA_SU_HARDWARE_SCREEN_OFFSET
+0x, // CB_TARGET_MASK
+0x, // CB_SHADER_MASK
+0x8000, // PA_SC_GENERIC_SCISSOR_TL
+0x40004000, // PA_SC_GENERIC_SCISSOR_BR
+0x

[PATCH 005/100] drm/amdgpu: add soc15ip.h

2017-03-20 Thread Alex Deucher

This header defines the IP layout for soc15 based SoCs.

Signed-off-by: Alex Deucher 
---
 .../gpu/drm/amd/include/asic_reg/vega10/soc15ip.h  | 1343 
 1 file changed, 1343 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h 
b/drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h
new file mode 100644
index 000..1767db6
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h
@@ -0,0 +1,1343 @@
+/*
+ * Copyright (C) 2017  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _soc15ip_new_HEADER
+#define _soc15ip_new_HEADER
+
+// HW ID
+#define MP1_HWID   1
+#define MP2_HWID   2
+#define THM_HWID   3
+#define SMUIO_HWID 4
+#define FUSE_HWID  5
+#define CLKA_HWID  6
+#define PWR_HWID  10
+#define GC_HWID   11
+#define UVD_HWID  12
+#define VCN_HWID  UVD_HWID
+#define AUDIO_AZ_HWID 13
+#define ACP_HWID  14
+#define DCI_HWID  15
+#define DMU_HWID 271
+#define DCO_HWID  16
+#define DIO_HWID 272
+#define XDMA_HWID 17
+#define DCEAZ_HWID18
+#define DAZ_HWID 274
+#define SDPMUX_HWID   19
+#define NTB_HWID  20
+#define IOHC_HWID 24
+#define L2IMU_HWID28
+#define VCE_HWID  32
+#define MMHUB_HWID34
+#define ATHUB_HWID35
+#define DBGU_NBIO_HWID36
+#define DFX_HWID  37
+#define DBGU0_HWID38
+#define DBGU1_HWID39
+#define OSSSYS_HWID   40
+#define HDP_HWID  41
+#define SDMA0_HWID42
+#define SDMA1_HWID43
+#define ISP_HWID  44
+#define DBGU_IO_HWID  45
+#define DF_HWID   46
+#define CLKB_HWID 47
+#define FCH_HWID  48
+#define DFX_DAP_HWID  49
+#define L1IMU_PCIE_HWID   50
+#define L1IMU_NBIF_HWID   51
+#define L1IMU_IOAGR_HWID  52
+#define L1IMU3_HWID   53
+#define L1IMU4_HWID   54
+#define L1IMU5_HWID   55
+#define L1IMU6_HWID   56
+#define L1IMU7_HWID   57
+#define L1IMU8_HWID   58
+#define L1IMU9_HWID   59
+#define L1IMU10_HWID  60
+#define L1IMU11_HWID  61
+#define L1IM

[PATCH 068/100] drm/amd/display: Enable DCE12 support

2017-03-20 Thread Alex Deucher

From: Harry Wentland 

This wires DCE12 support into DC and enables it.

Signed-off-by: Harry Wentland 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   5 +-
 drivers/gpu/drm/amd/display/Kconfig|   7 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 145 +++-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c |  10 ++
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c|  20 ++-
 drivers/gpu/drm/amd/display/dc/Makefile|   4 +
 drivers/gpu/drm/amd/display/dc/bios/Makefile   |   8 ++
 .../amd/display/dc/bios/bios_parser_interface.c|  14 ++
 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c   | 117 
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  29 
 drivers/gpu/drm/amd/display/dc/core/dc_debug.c |  11 ++
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  |  19 +++
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |  14 ++
 drivers/gpu/drm/amd/display/dc/dc.h|  27 
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h   |  46 +++
 .../gpu/drm/amd/display/dc/dce/dce_clock_source.c  |   6 +
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c| 149 +
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h|  20 +++
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h |   8 ++
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h  |  14 ++
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c |  35 +
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h |  34 +
 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h   |  72 ++
 .../drm/amd/display/dc/dce/dce_stream_encoder.h| 100 ++
 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h |  68 ++
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  53 +++-
 .../drm/amd/display/dc/dce110/dce110_mem_input.c   |   3 +
 .../display/dc/dce110/dce110_timing_generator.h|   3 +
 drivers/gpu/drm/amd/display/dc/dce120/Makefile |  12 ++
 .../gpu/drm/amd/display/dc/dce80/dce80_mem_input.c |   3 +
 drivers/gpu/drm/amd/display/dc/dm_services.h   |  89 
 drivers/gpu/drm/amd/display/dc/dm_services_types.h |  27 
 drivers/gpu/drm/amd/display/dc/gpio/Makefile   |  11 ++
 drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c   |   9 ++
 drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c |   9 +-
 drivers/gpu/drm/amd/display/dc/i2caux/Makefile |  11 ++
 drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c |   8 ++
 .../gpu/drm/amd/display/dc/inc/bandwidth_calcs.h   |   3 +
 .../gpu/drm/amd/display/dc/inc/hw/display_clock.h  |  23 
 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h  |   4 +
 drivers/gpu/drm/amd/display/dc/irq/Makefile|  12 ++
 drivers/gpu/drm/amd/display/dc/irq/irq_service.c   |   3 +
 drivers/gpu/drm/amd/display/include/dal_asic_id.h  |   4 +
 drivers/gpu/drm/amd/display/include/dal_types.h|   3 +
 44 files changed, 1262 insertions(+), 10 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/Makefile

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 82e42ef..8e64437 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1777,15 +1777,16 @@ bool amdgpu_device_asic_has_dc_support(enum 
amd_asic_type asic_type)
 #if defined(CONFIG_DRM_AMD_DC)
case CHIP_BONAIRE:
case CHIP_HAWAII:
-   return amdgpu_dc != 0;
case CHIP_CARRIZO:
case CHIP_STONEY:
case CHIP_POLARIS11:
case CHIP_POLARIS10:
case CHIP_POLARIS12:
-   return amdgpu_dc != 0;
case CHIP_TONGA:
case CHIP_FIJI:
+#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
+   case CHIP_VEGA10:
+#endif
return amdgpu_dc != 0;
 #endif
default:
diff --git a/drivers/gpu/drm/amd/display/Kconfig 
b/drivers/gpu/drm/amd/display/Kconfig
index f652cc3..40d6386 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -9,6 +9,13 @@ config DRM_AMD_DC
 
   Will be deprecated when the DC component is upstream.
 
+config DRM_AMD_DC_DCE12_0
+bool "Vega10 family"
+depends on DRM_AMD_DC
+help
+ Choose this option if you want to have
+ VG family for display engine.
+
 config DEBUG_KERNEL_DC
 bool "Enable kgdb break in DC"
 depends on DRM_AMD_DC
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index da12e23..b570a18 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -894,6 +894,10 @@ static int dce110_register_irq_handlers(struct 
amdgpu_device *adev)
struct dc_interrupt_params int_params = {0};
int r;
int i;
+   unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
+
+   if (adev->asic_type == CHIP_VEGA10)
+

[PATCH 046/100] drm/amdgpu: Add GMC 9.0 support

2017-03-20 Thread Alex Deucher

From: Alex Xie 

On SOC-15 parts, the GMC (Graphics Memory Controller) consists
of two hubs: GFX (graphics and compute) and MM (sdma, uvd, vce).

Signed-off-by: Alex Xie 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/Makefile  |   6 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  30 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   |  28 +-
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 447 +
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h |  35 ++
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 826 +++
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h|  30 ++
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 585 ++
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h  |  35 ++
 drivers/gpu/drm/amd/include/amd_shared.h |   2 +
 10 files changed, 2016 insertions(+), 8 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
 create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
 create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 69823e8..b5046fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -45,7 +45,8 @@ amdgpu-y += \
 # add GMC block
 amdgpu-y += \
gmc_v7_0.o \
-   gmc_v8_0.o
+   gmc_v8_0.o \
+   gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o
 
 # add IH block
 amdgpu-y += \
@@ -74,7 +75,8 @@ amdgpu-y += \
 # add async DMA block
 amdgpu-y += \
sdma_v2_4.o \
-   sdma_v3_0.o
+   sdma_v3_0.o \
+   sdma_v4_0.o
 
 # add UVD block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index aaded8d..d7257b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -123,6 +123,11 @@ extern int amdgpu_param_buf_per_se;
 /* max number of IP instances */
 #define AMDGPU_MAX_SDMA_INSTANCES  2
 
+/* max number of VMHUB */
+#define AMDGPU_MAX_VMHUBS  2
+#define AMDGPU_MMHUB   0
+#define AMDGPU_GFXHUB  1
+
 /* hardcode that limit for now */
 #define AMDGPU_VA_RESERVED_SIZE(8 << 20)
 
@@ -310,6 +315,12 @@ struct amdgpu_gart_funcs {
 uint32_t flags);
 };
 
+/* provided by the mc block */
+struct amdgpu_mc_funcs {
+   /* adjust mc addr in fb for APU case */
+   u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr);
+};
+
 /* provided by the ih block */
 struct amdgpu_ih_funcs {
/* ring read/write ptr handling, called from interrupt context */
@@ -559,6 +570,21 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t 
offset,
 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
 
 /*
+ * VMHUB structures, functions & helpers
+ */
+struct amdgpu_vmhub {
+   uint32_tctx0_ptb_addr_lo32;
+   uint32_tctx0_ptb_addr_hi32;
+   uint32_tvm_inv_eng0_req;
+   uint32_tvm_inv_eng0_ack;
+   uint32_tvm_context0_cntl;
+   uint32_tvm_l2_pro_fault_status;
+   uint32_tvm_l2_pro_fault_cntl;
+   uint32_t(*get_invalidate_req)(unsigned int vm_id);
+   uint32_t(*get_vm_protection_bits)(void);
+};
+
+/*
  * GPU MC structures, functions & helpers
  */
 struct amdgpu_mc {
@@ -591,6 +617,9 @@ struct amdgpu_mc {
u64 shared_aperture_end;
u64 private_aperture_start;
u64 private_aperture_end;
+   /* protects concurrent invalidation */
+   spinlock_t  invalidate_lock;
+   const struct amdgpu_mc_funcs *mc_funcs;
 };
 
 /*
@@ -1479,6 +1508,7 @@ struct amdgpu_device {
struct amdgpu_gart  gart;
struct amdgpu_dummy_pagedummy_page;
struct amdgpu_vm_managervm_manager;
+   struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
 
/* memory management */
struct amdgpu_mman  mman;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index df615d7..47a8080 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -375,6 +375,16 @@ static bool amdgpu_vm_ring_has_compute_vm_bug(struct 
amdgpu_ring *ring)
return false;
 }
 
+static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr)
+{
+   u64 addr = mc_addr;
+
+   if (adev->mc.mc_funcs && adev->mc.mc_funcs->adjust_mc_addr)
+   addr = adev->mc.mc_funcs->adjust_mc_addr(adev, addr);
+
+   return addr;
+}
+
 /**
  * amdgpu_vm_flush - hardware flush the vm
  *

[PATCH 081/100] drm/amdgpu/gfx9: impl gfx9 meta data emit

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

Insert ce meta prior to cntx_cntl and de follow it.

Signed-off-by: Xiangliang Yu 
Signed-off-by: Monk Liu 
Reviewed-by: Alex Deucher 
Acked-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 47 ++
 drivers/gpu/drm/amd/include/v9_structs.h | 68 
 2 files changed, 115 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 6f266d0..2241075 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3189,10 +3189,54 @@ static void gfx_v9_ring_emit_sb(struct amdgpu_ring 
*ring)
amdgpu_ring_write(ring, 0);
 }
 
+static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
+{
+   static struct v9_ce_ib_state ce_payload = {0};
+   uint64_t csa_addr;
+   int cnt;
+
+   cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
+   csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
+
+   amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
+   amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
+WRITE_DATA_DST_SEL(8) |
+WR_CONFIRM) |
+WRITE_DATA_CACHE_POLICY(0));
+   amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct 
v9_gfx_meta_data, ce_payload)));
+   amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct 
v9_gfx_meta_data, ce_payload)));
+   amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 
sizeof(ce_payload) >> 2);
+}
+
+static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
+{
+   static struct v9_de_ib_state de_payload = {0};
+   uint64_t csa_addr, gds_addr;
+   int cnt;
+
+   csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
+   gds_addr = csa_addr + 4096;
+   de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
+   de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
+
+   cnt = (sizeof(de_payload) >> 2) + 4 - 2;
+   amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
+   amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
+WRITE_DATA_DST_SEL(8) |
+WR_CONFIRM) |
+WRITE_DATA_CACHE_POLICY(0));
+   amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct 
v9_gfx_meta_data, de_payload)));
+   amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct 
v9_gfx_meta_data, de_payload)));
+   amdgpu_ring_write_multiple(ring, (void *)&de_payload, 
sizeof(de_payload) >> 2);
+}
+
 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
 {
uint32_t dw2 = 0;
 
+   if (amdgpu_sriov_vf(ring->adev))
+   gfx_v9_0_ring_emit_ce_meta(ring);
+
dw2 |= 0x8000; /* set load_enable otherwise this package is just 
NOPs */
if (flags & AMDGPU_HAVE_CTX_SWITCH) {
/* set load_global_config & load_global_uconfig */
@@ -3216,6 +3260,9 @@ static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring 
*ring, uint32_t flags)
amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
amdgpu_ring_write(ring, dw2);
amdgpu_ring_write(ring, 0);
+
+   if (amdgpu_sriov_vf(ring->adev))
+   gfx_v9_0_ring_emit_de_meta(ring);
 }
 
 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
diff --git a/drivers/gpu/drm/amd/include/v9_structs.h 
b/drivers/gpu/drm/amd/include/v9_structs.h
index e7508a3..9a9e6c7 100644
--- a/drivers/gpu/drm/amd/include/v9_structs.h
+++ b/drivers/gpu/drm/amd/include/v9_structs.h
@@ -672,4 +672,72 @@ struct v9_mqd {
uint32_t reserved_511;
 };
 
+/* from vega10 all CSA format is shifted to chain ib compatible mode */
+struct v9_ce_ib_state {
+/* section of non chained ib part */
+uint32_t ce_ib_completion_status;
+uint32_t ce_constegnine_count;
+uint32_t ce_ibOffset_ib1;
+uint32_t ce_ibOffset_ib2;
+
+/* section of chained ib */
+uint32_t ce_chainib_addrlo_ib1;
+uint32_t ce_chainib_addrlo_ib2;
+uint32_t ce_chainib_addrhi_ib1;
+uint32_t ce_chainib_addrhi_ib2;
+uint32_t ce_chainib_size_ib1;
+uint32_t ce_chainib_size_ib2;
+}; /* total 10 DWORD */
+
+struct v9_de_ib_state {
+/* section of non chained ib part */
+uint32_t ib_completion_status;
+uint32_t de_constEngine_count;
+uint32_t ib_offset_ib1;
+uint32_t ib_offset_ib2;
+
+/* section of chained ib */
+uint32_t chain_ib_addrlo_ib1;
+uint32_t chain_ib_addrlo_ib2;
+uint32_t chain_ib_addrhi_ib1;
+uint32_t chain_ib_addrhi_ib2;
+uint32_t chain_ib_size_ib1;
+uint32_t chain_ib_size_ib2;
+
+/* section of non chained ib part */
+uint32_t preamble_begin_ib1;
+uint32_t preamble_begin_ib2;
+uint32_t preamble_end_ib1;
+uint32_t preamble_end_ib2;
+
+/* section of chained ib */
+

[PATCH 089/100] drm/amdgpu/soc15: enable virtual dce for vf

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

VF need virtual dce, enable it if device is vf.

Signed-off-by: Xiangliang Yu 
Reviewed-by: Alex Deucher 
Reviewed-by: Monk Liu 
Acked-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 46ccd60..a7b5338 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -58,6 +58,7 @@
 #include "uvd_v7_0.h"
 #include "vce_v4_0.h"
 #include "amdgpu_powerplay.h"
+#include "dce_virtual.h"
 #include "mxgpu_ai.h"
 
 MODULE_FIRMWARE("amdgpu/vega10_smc.bin");
@@ -485,8 +486,10 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
if (!amdgpu_sriov_vf(adev))
amdgpu_ip_block_add(adev, &psp_v3_1_ip_block);
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+   if (amdgpu_sriov_vf(adev))
+   amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
 #if defined(CONFIG_DRM_AMD_DC)
-   if (amdgpu_device_has_dc_support(adev))
+   else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block);
 #else
 #  warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
-- 
2.5.5

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[PATCH 066/100] drm/amd/display: Add DCE12 irq support

2017-03-20 Thread Alex Deucher

From: Harry Wentland 

Signed-off-by: Harry Wentland 
Signed-off-by: Alex Deucher 
---
 .../amd/display/dc/irq/dce120/irq_service_dce120.c | 293 +
 .../amd/display/dc/irq/dce120/irq_service_dce120.h |  34 +++
 2 files changed, 327 insertions(+)
 create mode 100644 
drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
 create mode 100644 
drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.h

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c 
b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
new file mode 100644
index 000..5a263b2
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
@@ -0,0 +1,293 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "include/logger_interface.h"
+
+#include "irq_service_dce120.h"
+#include "../dce110/irq_service_dce110.h"
+
+#include "vega10/DC/dce_12_0_offset.h"
+#include "vega10/DC/dce_12_0_sh_mask.h"
+#include "vega10/soc15ip.h"
+
+#include "ivsrcid/ivsrcid_vislands30.h"
+
+static bool hpd_ack(
+   struct irq_service *irq_service,
+   const struct irq_source_info *info)
+{
+   uint32_t addr = info->status_reg;
+   uint32_t value = dm_read_reg(irq_service->ctx, addr);
+   uint32_t current_status =
+   get_reg_field_value(
+   value,
+   HPD0_DC_HPD_INT_STATUS,
+   DC_HPD_SENSE_DELAYED);
+
+   dal_irq_service_ack_generic(irq_service, info);
+
+   value = dm_read_reg(irq_service->ctx, info->enable_reg);
+
+   set_reg_field_value(
+   value,
+   current_status ? 0 : 1,
+   HPD0_DC_HPD_INT_CONTROL,
+   DC_HPD_INT_POLARITY);
+
+   dm_write_reg(irq_service->ctx, info->enable_reg, value);
+
+   return true;
+}
+
+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
+   .set = NULL,
+   .ack = hpd_ack
+};
+
+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+   .set = NULL,
+   .ack = NULL
+};
+
+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
+   .set = NULL,
+   .ack = NULL
+};
+
+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
+   .set = NULL,
+   .ack = NULL
+};
+
+#define BASE_INNER(seg) \
+   DCE_BASE__INST0_SEG ## seg
+
+#define BASE(seg) \
+   BASE_INNER(seg)
+
+#define SRI(reg_name, block, id)\
+   BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+   mm ## block ## id ## _ ## reg_name
+
+
+#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
+   .enable_reg = SRI(reg1, block, reg_num),\
+   .enable_mask = \
+   block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
+   .enable_value = {\
+   block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
+   ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+   },\
+   .ack_reg = SRI(reg2, block, reg_num),\
+   .ack_mask = \
+   block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
+   .ack_value = \
+   block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
+
+#define hpd_int_entry(reg_num)\
+   [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
+   IRQ_REG_ENTRY(HPD, reg_num,\
+   DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
+   DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
+   .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
+   .funcs = &hpd_irq_info_funcs\
+   }
+
+#define hpd_rx_int_entry(reg_num)\
+   [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
+   IRQ_REG_ENTRY(HPD, reg_num,\
+   DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
+   DC_HPD_INT_CONTROL, DC_HPD_RX

[PATCH 047/100] drm/amdgpu: add SDMA v4.0 implementation

2017-03-20 Thread Alex Deucher

From: Ken Wang 

Signed-off-by: Ken Wang 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1553 
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.h |   30 +
 2 files changed, 1583 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.h

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
new file mode 100644
index 000..b460e00
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -0,0 +1,1553 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include 
+#include 
+#include "amdgpu.h"
+#include "amdgpu_ucode.h"
+#include "amdgpu_trace.h"
+
+#include "vega10/soc15ip.h"
+#include "vega10/SDMA0/sdma0_4_0_offset.h"
+#include "vega10/SDMA0/sdma0_4_0_sh_mask.h"
+#include "vega10/SDMA1/sdma1_4_0_offset.h"
+#include "vega10/SDMA1/sdma1_4_0_sh_mask.h"
+#include "vega10/MMHUB/mmhub_1_0_offset.h"
+#include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
+#include "vega10/HDP/hdp_4_0_offset.h"
+
+#include "soc15_common.h"
+#include "soc15.h"
+#include "vega10_sdma_pkt_open.h"
+
+MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
+MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
+
+static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
+static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
+static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
+static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
+
+static const u32 golden_settings_sdma_4[] =
+{
+   SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 
0x02831f07,
+   SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xff000ff0, 0x3f000100,
+   SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0100, 0x0100,
+   SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfff7, 
0x00403000,
+   SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL), 0x800f0100, 
0x0100,
+   SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL), 0xfff0, 
0x00403000,
+   SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0x003ff006, 0x0003c000,
+   SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0100, 
0x0100,
+   SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0xfff0, 
0x00403000,
+   SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0100, 
0x0100,
+   SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0xfff0, 
0x00403000,
+   SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x03ff, 0x03c0,
+   SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CHICKEN_BITS), 0xfe931f07, 
0x02831f07,
+   SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), 0x, 0x3f000100,
+   SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_IB_CNTL), 0x800f0100, 0x0100,
+   SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL), 0xfff0, 
0x00403000,
+   SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL), 0x800f0100, 
0x0100,
+   SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL), 0xfff0, 
0x00403000,
+   SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), 0x003ff000, 0x0003c000,
+   SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL), 0x800f0100, 
0x0100,
+   SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL), 0xfff0, 
0x00403000,
+   SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL), 0x800f0100, 
0x0100,
+   SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL), 0xfff0, 
0x00403000,
+   SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_UTCL1_PAGE), 0x03ff, 0x03c0
+};
+
+static const u32 golden_settings_sdma_vg10[] =
+{
+   SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 
0x00104002,
+   SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 
0x00104002,
+   SOC15_REG_OFFSET(SD

[PATCH 003/100] drm/amdgpu: move atom scratch setup into amdgpu_atombios.c

2017-03-20 Thread Alex Deucher

There will be a slightly different version for atomfirmware.

Reviewed-by: Ken Wang 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 28 
 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h |  3 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/atom.c| 26 --
 drivers/gpu/drm/amd/amdgpu/atom.h|  1 -
 5 files changed, 32 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index 56a86dd..f52b1bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -1748,3 +1748,31 @@ void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 
num_bytes, bool to_le)
memcpy(dst, src, num_bytes);
 #endif
 }
+
+int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev)
+{
+   struct atom_context *ctx = adev->mode_info.atom_context;
+   int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
+   uint16_t data_offset;
+   int usage_bytes = 0;
+   struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
+
+   if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, 
&data_offset)) {
+   firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE 
*)(ctx->bios + data_offset);
+
+   DRM_DEBUG("atom firmware requested %08x %dkb\n",
+ 
le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
+ 
le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
+
+   usage_bytes = 
le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 
1024;
+   }
+   ctx->scratch_size_bytes = 0;
+   if (usage_bytes == 0)
+   usage_bytes = 20 * 1024;
+   /* allocate some scratch memory */
+   ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
+   if (!ctx->scratch)
+   return -ENOMEM;
+   ctx->scratch_size_bytes = usage_bytes;
+   return 0;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
index 70e9ace..4e0f488 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
@@ -215,4 +215,7 @@ int amdgpu_atombios_get_clock_dividers(struct amdgpu_device 
*adev,
 int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,
  u8 voltage_type,
  u8 *svd_gpio_id, u8 *svc_gpio_id);
+
+int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev);
+
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 118f4e6..f87c1cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -993,7 +993,7 @@ static int amdgpu_atombios_init(struct amdgpu_device *adev)
 
mutex_init(&adev->mode_info.atom_context->mutex);
amdgpu_atombios_scratch_regs_init(adev);
-   amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
+   amdgpu_atombios_allocate_fb_scratch(adev);
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c 
b/drivers/gpu/drm/amd/amdgpu/atom.c
index 81c60a2..d69aa2e 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -1417,29 +1417,3 @@ bool amdgpu_atom_parse_cmd_header(struct atom_context 
*ctx, int index, uint8_t *
return true;
 }
 
-int amdgpu_atom_allocate_fb_scratch(struct atom_context *ctx)
-{
-   int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
-   uint16_t data_offset;
-   int usage_bytes = 0;
-   struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
-
-   if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, 
&data_offset)) {
-   firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE 
*)(ctx->bios + data_offset);
-
-   DRM_DEBUG("atom firmware requested %08x %dkb\n",
- 
le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
- 
le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
-
-   usage_bytes = 
le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 
1024;
-   }
-   ctx->scratch_size_bytes = 0;
-   if (usage_bytes == 0)
-   usage_bytes = 20 * 1024;
-   /* allocate some scratch memory */
-   ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
-   if (!ctx->scratch)
-   return -ENOMEM;
-   ctx->scratch_size_bytes = usage_bytes;
-   return 0;
-}
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h 
b/drivers/gpu/drm/amd/amdgpu/atom.h
index baa2438..ddd8045 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.h
+++ b/drivers/gpu/drm/amd/am

[PATCH 095/100] drm/amdgpu/virt: add structure for MM table

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

Add new structure for MM table for multi media scheduler of sriov.

Signed-off-by: Xiangliang Yu 
Reviewed-by: Alex Deucher 
Reviewed-by: Monk Liu 
Acked-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 846f29c..1ee0a19 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -30,6 +30,12 @@
 #define AMDGPU_PASSTHROUGH_MODE(1 << 3) /* thw whole GPU is pass 
through for VM */
 #define AMDGPU_SRIOV_CAPS_RUNTIME  (1 << 4) /* is out of full access mode 
*/
 
+struct amdgpu_mm_table {
+   struct amdgpu_bo*bo;
+   uint32_t*cpu_addr;
+   uint64_tgpu_addr;
+};
+
 /**
  * struct amdgpu_virt_ops - amdgpu device virt operations
  */
@@ -51,6 +57,7 @@ struct amdgpu_virt {
struct amdgpu_irq_src   ack_irq;
struct amdgpu_irq_src   rcv_irq;
struct work_struct  flr_work;
+   struct amdgpu_mm_table  mm_table;
const struct amdgpu_virt_ops*ops;
 };
 
-- 
2.5.5

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[PATCH 057/100] drm/amdgpu: add new atomfirmware based helpers for powerplay

2017-03-20 Thread Alex Deucher

From: Eric Huang 

New helpers for fetching info out of atomfirmware.

Signed-off-by: Eric Huang 
Reviewed-by: Ken Wang 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/Makefile   |   2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 396 +
 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h | 140 
 3 files changed, 537 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
 create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile 
b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
index 5fff1d6..ccb51c2 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
@@ -5,7 +5,7 @@
 HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
hardwaremanager.o pp_acpi.o cz_hwmgr.o \
cz_clockpowergating.o pppcielanes.o\
-   process_pptables_v1_0.o ppatomctrl.o \
+   process_pptables_v1_0.o ppatomctrl.o ppatomfwctrl.o \
smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \
smu7_clockpowergating.o
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
new file mode 100644
index 000..b71525f
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
@@ -0,0 +1,396 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "ppatomfwctrl.h"
+#include "atomfirmware.h"
+#include "pp_debug.h"
+
+
+static const union atom_voltage_object_v4 
*pp_atomfwctrl_lookup_voltage_type_v4(
+   const struct atom_voltage_objects_info_v4_1 
*voltage_object_info_table,
+   uint8_t voltage_type, uint8_t voltage_mode)
+{
+   unsigned int size = le16_to_cpu(
+   voltage_object_info_table->table_header.structuresize);
+   unsigned int offset =
+   offsetof(struct atom_voltage_objects_info_v4_1, 
voltage_object[0]);
+   unsigned long start = (unsigned long)voltage_object_info_table;
+
+   while (offset < size) {
+   const union atom_voltage_object_v4 *voltage_object =
+   (const union atom_voltage_object_v4 *)(start + 
offset);
+
+if (voltage_type == 
voltage_object->gpio_voltage_obj.header.voltage_type &&
+voltage_mode == 
voltage_object->gpio_voltage_obj.header.voltage_mode)
+return voltage_object;
+
+offset += 
le16_to_cpu(voltage_object->gpio_voltage_obj.header.object_size);
+
+}
+
+return NULL;
+}
+
+static struct atom_voltage_objects_info_v4_1 
*pp_atomfwctrl_get_voltage_info_table(
+   struct pp_hwmgr *hwmgr)
+{
+const void *table_address;
+uint16_t idx;
+
+idx = GetIndexIntoMasterDataTable(voltageobject_info);
+table_address =cgs_atom_get_data_table(hwmgr->device,
+   idx, NULL, NULL, NULL);
+
+PP_ASSERT_WITH_CODE( 
+table_address,
+"Error retrieving BIOS Table Address!",
+return NULL);
+
+return (struct atom_voltage_objects_info_v4_1 *)table_address;
+}
+
+/**
+* Returns TRUE if the given voltage type is controlled by GPIO pins.
+* voltage_type is one of SET_VOLTAGE_TYPE_ASIC_VDDC, 
SET_VOLTAGE_TYPE_ASIC_MVDDC, SET_VOLTAGE_TYPE_ASIC_MVDDQ.
+* voltage_mode is one of ATOM_SET_VOLTAGE, ATOM_SET_VOLTAGE_PHASE
+*/
+bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr,
+   uint8_t voltage_type, uint8_t voltage_mode)
+{
+   struct atom_voltage_objects_info_v4_1 *voltage_info =
+   (struct atom_voltage_objects_info_v4_1 *)
+   pp_atomfwctrl_get_voltage_info_table(hwmgr);
+   bool ret;
+
+   /* If we cannot find the table do NOT try to control

[PATCH 059/100] drm/amd/powerplay: add some new structures for Vega10

2017-03-20 Thread Alex Deucher

From: Eric Huang 

Signed-off-by: Eric Huang 
Reviewed-by: Ken Wang 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h|  16 ++-
 .../gpu/drm/amd/powerplay/inc/hardwaremanager.h|  32 ++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  | 112 -
 3 files changed, 155 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h
index 2930a33..c0193e0 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h
@@ -30,15 +30,17 @@
 
 struct phm_ppt_v1_clock_voltage_dependency_record {
uint32_t clk;
-   uint8_t vddInd;
+   uint8_t  vddInd;
+   uint8_t  vddciInd;
+   uint8_t  mvddInd;
uint16_t vdd_offset;
uint16_t vddc;
uint16_t vddgfx;
uint16_t vddci;
uint16_t mvdd;
-   uint8_t phases;
-   uint8_t cks_enable;
-   uint8_t cks_voffset;
+   uint8_t  phases;
+   uint8_t  cks_enable;
+   uint8_t  cks_voffset;
uint32_t sclk_offset;
 };
 
@@ -94,6 +96,7 @@ struct phm_ppt_v1_pcie_record {
uint8_t gen_speed;
uint8_t lane_width;
uint16_t usreserved;
+   uint16_t reserved;
uint32_t pcie_sclk;
 };
 typedef struct phm_ppt_v1_pcie_record phm_ppt_v1_pcie_record;
@@ -104,5 +107,10 @@ struct phm_ppt_v1_pcie_table {
 };
 typedef struct phm_ppt_v1_pcie_table phm_ppt_v1_pcie_table;
 
+struct phm_ppt_v1_gpio_table {
+   uint8_t vrhot_triggered_sclk_dpm_index;   /* SCLK DPM level 
index to switch to when VRHot is triggered */
+};
+typedef struct phm_ppt_v1_gpio_table phm_ppt_v1_gpio_table;
+
 #endif
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h 
b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
index 2612997..c5279c2 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
@@ -182,6 +182,7 @@ enum phm_platform_caps {
PHM_PlatformCaps_Thermal2GPIO17,/* indicates 
thermal2GPIO17 table support */
PHM_PlatformCaps_ThermalOutGPIO,/* indicates 
ThermalOutGPIO support, pin number is assigned by VBIOS */
PHM_PlatformCaps_DisableMclkSwitchingForFrameLock,  /* Disable 
memory clock switch during Framelock */
+   PHM_PlatformCaps_ForceMclkHigh, /* Disable 
memory clock switching by forcing memory clock high */
PHM_PlatformCaps_VRHotGPIOConfigurable, /* indicates 
VR_HOT GPIO configurable */
PHM_PlatformCaps_TempInversion, /* enable Temp 
Inversion feature */
PHM_PlatformCaps_IOIC3,
@@ -212,6 +213,20 @@ enum phm_platform_caps {
PHM_PlatformCaps_TablelessHardwareInterface,
PHM_PlatformCaps_EnableDriverEVV,
PHM_PlatformCaps_SPLLShutdownSupport,
+   PHM_PlatformCaps_VirtualBatteryState,
+   PHM_PlatformCaps_IgnoreForceHighClockRequestsInAPUs,
+   PHM_PlatformCaps_DisableMclkSwitchForVR,
+   PHM_PlatformCaps_SMU8,
+   PHM_PlatformCaps_VRHotPolarityHigh,
+   PHM_PlatformCaps_IPS_UlpsExclusive,
+   PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme,
+   PHM_PlatformCaps_GeminiAsymmetricPower,
+   PHM_PlatformCaps_OCLPowerOptimization,
+   PHM_PlatformCaps_MaxPCIEBandWidth,
+   PHM_PlatformCaps_PerfPerWattOptimizationSupport,
+   PHM_PlatformCaps_UVDClientMCTuning,
+   PHM_PlatformCaps_ODNinACSupport,
+   PHM_PlatformCaps_ODNinDCSupport,
PHM_PlatformCaps_Max
 };
 
@@ -290,6 +305,8 @@ struct PP_Clocks {
uint32_t memoryClock;
uint32_t BusBandwidth;
uint32_t engineClockInSR;
+   uint32_t dcefClock;
+   uint32_t dcefClockInSR;
 };
 
 struct pp_clock_info {
@@ -334,6 +351,21 @@ struct phm_clocks {
uint32_t clock[MAX_NUM_CLOCKS];
 };
 
+struct phm_odn_performance_level {
+   uint32_t clock;
+   uint32_t vddc;
+   bool enabled;
+};
+
+struct phm_odn_clock_levels {
+   uint32_t size;
+   uint32_t options;
+   uint32_t flags;
+   uint32_t number_of_performance_levels;
+   /* variable-sized array, specify by ulNumberOfPerformanceLevels. */
+   struct phm_odn_performance_level performance_level_entries[8];
+};
+
 extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
 extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
 extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 
b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index d5aa6cd..02185d4 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -83,7 +83,8 @@ enum PP_FEATURE_MASK {
PP_ULV_MASK = 0x100,
PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
PP_CLOCK_STRETCH_MASK = 0x400,
-   P

[PATCH 055/100] drm/amd/powerplay: add smu9 header files for Vega10

2017-03-20 Thread Alex Deucher

From: Eric Huang 

Signed-off-by: Eric Huang 
Reviewed-by: Ken Wang 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/inc/smu9.h   | 147 
 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h | 418 +
 2 files changed, 565 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu9.h
 create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu9.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu9.h
new file mode 100644
index 000..9ef2490
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu9.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef SMU9_H
+#define SMU9_H
+
+#pragma pack(push, 1)
+
+#define ENABLE_DEBUG_FEATURES
+
+/* Feature Control Defines */
+#define FEATURE_DPM_PREFETCHER_BIT  0
+#define FEATURE_DPM_GFXCLK_BIT  1
+#define FEATURE_DPM_UCLK_BIT2
+#define FEATURE_DPM_SOCCLK_BIT  3
+#define FEATURE_DPM_UVD_BIT 4
+#define FEATURE_DPM_VCE_BIT 5
+#define FEATURE_ULV_BIT 6
+#define FEATURE_DPM_MP0CLK_BIT  7
+#define FEATURE_DPM_LINK_BIT8
+#define FEATURE_DPM_DCEFCLK_BIT 9
+#define FEATURE_AVFS_BIT10
+#define FEATURE_DS_GFXCLK_BIT   11
+#define FEATURE_DS_SOCCLK_BIT   12
+#define FEATURE_DS_LCLK_BIT 13
+#define FEATURE_PPT_BIT 14
+#define FEATURE_TDC_BIT 15
+#define FEATURE_THERMAL_BIT 16
+#define FEATURE_GFX_PER_CU_CG_BIT   17
+#define FEATURE_RM_BIT  18
+#define FEATURE_DS_DCEFCLK_BIT  19
+#define FEATURE_ACDC_BIT20
+#define FEATURE_VR0HOT_BIT  21
+#define FEATURE_VR1HOT_BIT  22
+#define FEATURE_FW_CTF_BIT  23
+#define FEATURE_LED_DISPLAY_BIT 24
+#define FEATURE_FAN_CONTROL_BIT 25
+#define FEATURE_VOLTAGE_CONTROLLER_BIT  26
+#define FEATURE_SPARE_27_BIT27
+#define FEATURE_SPARE_28_BIT28
+#define FEATURE_SPARE_29_BIT29
+#define FEATURE_SPARE_30_BIT30
+#define FEATURE_SPARE_31_BIT31
+
+#define NUM_FEATURES32
+
+#define FFEATURE_DPM_PREFETCHER_MASK (1 << FEATURE_DPM_PREFETCHER_BIT )
+#define FFEATURE_DPM_GFXCLK_MASK (1 << FEATURE_DPM_GFXCLK_BIT )
+#define FFEATURE_DPM_UCLK_MASK   (1 << FEATURE_DPM_UCLK_BIT   )
+#define FFEATURE_DPM_SOCCLK_MASK (1 << FEATURE_DPM_SOCCLK_BIT )
+#define FFEATURE_DPM_UVD_MASK(1 << FEATURE_DPM_UVD_BIT)
+#define FFEATURE_DPM_VCE_MASK(1 << FEATURE_DPM_VCE_BIT)
+#define FFEATURE_ULV_MASK(1 << FEATURE_ULV_BIT)
+#define FFEATURE_DPM_MP0CLK_MASK (1 << FEATURE_DPM_MP0CLK_BIT )
+#define FFEATURE_DPM_LINK_MASK   (1 << FEATURE_DPM_LINK_BIT   )
+#define FFEATURE_DPM_DCEFCLK_MASK(1 << FEATURE_DPM_DCEFCLK_BIT)
+#define FFEATURE_AVFS_MASK   (1 << FEATURE_AVFS_BIT   )
+#define FFEATURE_DS_GFXCLK_MASK  (1 << FEATURE_DS_GFXCLK_BIT  )
+#define FFEATURE_DS_SOCCLK_MASK  (1 << FEATURE_DS_SOCCLK_BIT  )
+#define FFEATURE_DS_LCLK_MASK(1 << FEATURE_DS_LCLK_BIT)
+#define FFEATURE_PPT_MASK(1 << FEATURE_PPT_BIT)
+#define FFEATURE_TDC_MASK(1 << FEATURE_TDC_BIT)
+#define FFEATURE_THERMAL_MASK(1 << FEATURE_THERMAL_BIT)
+#define FFEATURE_GFX_PER_CU_CG_MASK  (1 << FEATURE_GFX_PER_CU_CG_BIT  )
+#define FFEATURE_RM_MASK (1 << FEATURE_RM_BIT )
+#define FFEATURE_DS_DCEFCLK_MASK (1 << FEATURE_DS_DCEFC

[PATCH 088/100] drm/amdgpu/soc15: init virt ops for vf

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

If gpu device is vf, set virt ops so that guest can talk with GPU
hypervisor.

Signed-off-by: Xiangliang Yu 
Reviewed-by: Alex Deucher 
Reviewed-by: Monk Liu 
Acked-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index b197288..46ccd60 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -58,6 +58,7 @@
 #include "uvd_v7_0.h"
 #include "vce_v4_0.h"
 #include "amdgpu_powerplay.h"
+#include "mxgpu_ai.h"
 
 MODULE_FIRMWARE("amdgpu/vega10_smc.bin");
 
@@ -471,6 +472,9 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
 {
nbio_v6_1_detect_hw_virt(adev);
 
+   if (amdgpu_sriov_vf(adev))
+   adev->virt.ops = &xgpu_ai_virt_ops;
+
switch (adev->asic_type) {
case CHIP_VEGA10:
amdgpu_ip_block_add(adev, &vega10_common_ip_block);
-- 
2.5.5

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[PATCH 042/100] drm/amdgpu: gart fixes for vega10

2017-03-20 Thread Alex Deucher

Flags need to be 0 to be considered invalid.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index 2916fab..6d691ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -229,7 +229,8 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, 
uint64_t offset,
unsigned p;
int i, j;
u64 page_base;
-   uint64_t flags = AMDGPU_PTE_SYSTEM;
+   /* Starting from VEGA10, system bit must be 0 to mean invalid. */
+   uint64_t flags = 0;
 
if (!adev->gart.ready) {
WARN(1, "trying to unbind memory from uninitialized GART !\n");
-- 
2.5.5

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[PATCH 029/100] drm/amdgpu: add 64bit doorbell assignments

2017-03-20 Thread Alex Deucher

From: Ken Wang 

Change-Id: Ic1859520f98c45f0db982a5093a3207da9fcfa5d
Signed-off-by: Ken Wang 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 68 +
 1 file changed, 68 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ae4cb07..f605219 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -620,6 +620,74 @@ struct amdgpu_doorbell {
u32 num_doorbells;  /* Number of doorbells actually 
reserved for amdgpu. */
 };
 
+/*
+ * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
+ */
+typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
+{
+   /*
+* All compute related doorbells: kiq, hiq, diq, traditional compute 
queue, user queue, should locate in
+* a continues range so that programming 
CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
+*  Compute related doorbells are allocated from 0x00 to 0x8a
+*/
+
+
+   /* kernel scheduling */
+   AMDGPU_DOORBELL64_KIQ = 0x00,
+
+   /* HSA interface queue and debug queue */
+   AMDGPU_DOORBELL64_HIQ = 0x01,
+   AMDGPU_DOORBELL64_DIQ = 0x02,
+
+   /* Compute engines */
+   AMDGPU_DOORBELL64_MEC_RING0   = 0x03,
+   AMDGPU_DOORBELL64_MEC_RING1   = 0x04,
+   AMDGPU_DOORBELL64_MEC_RING2   = 0x05,
+   AMDGPU_DOORBELL64_MEC_RING3   = 0x06,
+   AMDGPU_DOORBELL64_MEC_RING4   = 0x07,
+   AMDGPU_DOORBELL64_MEC_RING5   = 0x08,
+   AMDGPU_DOORBELL64_MEC_RING6   = 0x09,
+   AMDGPU_DOORBELL64_MEC_RING7   = 0x0a,
+
+   /* User queue doorbell range (128 doorbells) */
+   AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
+   AMDGPU_DOORBELL64_USERQUEUE_END   = 0x8a,
+
+   /* Graphics engine */
+   AMDGPU_DOORBELL64_GFX_RING0   = 0x8b,
+
+   /*
+* Other graphics doorbells can be allocated here: from 0x8c to 0xef
+* Graphics voltage island aperture 1
+* default non-graphics QWORD index is 0xF0 - 0xFF inclusive
+*/
+
+   /* sDMA engines */
+   AMDGPU_DOORBELL64_sDMA_ENGINE0= 0xF0,
+   AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
+   AMDGPU_DOORBELL64_sDMA_ENGINE1= 0xF2,
+   AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
+
+   /* Interrupt handler */
+   AMDGPU_DOORBELL64_IH  = 0xF4,  /* For legacy 
interrupt ring buffer */
+   AMDGPU_DOORBELL64_IH_RING1= 0xF5,  /* For page 
migration request log */
+   AMDGPU_DOORBELL64_IH_RING2= 0xF6,  /* For page 
migration translation/invalidation log */
+
+   /* VCN engine */
+   AMDGPU_DOORBELL64_VCN0= 0xF8,
+   AMDGPU_DOORBELL64_VCN1= 0xF9,
+   AMDGPU_DOORBELL64_VCN2= 0xFA,
+   AMDGPU_DOORBELL64_VCN3= 0xFB,
+   AMDGPU_DOORBELL64_VCN4= 0xFC,
+   AMDGPU_DOORBELL64_VCN5= 0xFD,
+   AMDGPU_DOORBELL64_VCN6= 0xFE,
+   AMDGPU_DOORBELL64_VCN7= 0xFF,
+
+   AMDGPU_DOORBELL64_MAX_ASSIGNMENT  = 0xFF,
+   AMDGPU_DOORBELL64_INVALID = 0x
+} AMDGPU_DOORBELL64_ASSIGNMENT;
+
+
 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
phys_addr_t *aperture_base,
size_t *aperture_size,
-- 
2.5.5

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[PATCH 082/100] drm/amdgpu:bypass RLC init for SRIOV

2017-03-20 Thread Alex Deucher

From: Monk Liu 

one issue unresolved for RLC:
rlc will go wrong completely if there is a soft_reset
before RLC ucode loading.

to workaround above issue, we can totally ignore RLC
in guest driver side due to there was already full
initialization on RLC side by GIM

Signed-off-by: Monk Liu 
Signed-off-by: Xiangliang Yu 
Reviewed-by: Alex Deucher 
Acked-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 2241075..8e5367d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1459,6 +1459,9 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
 {
int r;
 
+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
gfx_v9_0_rlc_stop(adev);
 
/* disable CG */
-- 
2.5.5

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[PATCH 041/100] drm/amdgpu: get display info from DC when DC enabled.

2017-03-20 Thread Alex Deucher

From: Rex Zhu 

Signed-off-by: Rex Zhu 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 59 +++--
 1 file changed, 34 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index f0e3624..d42eade 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -999,10 +999,6 @@ static int amdgpu_cgs_get_active_displays_info(struct 
cgs_device *cgs_device,
  struct cgs_display_info *info)
 {
CGS_FUNC_ADEV;
-   struct amdgpu_crtc *amdgpu_crtc;
-   struct drm_device *ddev = adev->ddev;
-   struct drm_crtc *crtc;
-   uint32_t line_time_us, vblank_lines;
struct cgs_mode_info *mode_info;
 
if (info == NULL)
@@ -1010,30 +1006,43 @@ static int amdgpu_cgs_get_active_displays_info(struct 
cgs_device *cgs_device,
 
mode_info = info->mode_info;
 
-   if (adev->mode_info.num_crtc && 
adev->mode_info.mode_config_initialized) {
-   list_for_each_entry(crtc,
-   &ddev->mode_config.crtc_list, head) {
-   amdgpu_crtc = to_amdgpu_crtc(crtc);
-   if (crtc->enabled) {
-   info->active_display_mask |= (1 << 
amdgpu_crtc->crtc_id);
-   info->display_count++;
-   }
-   if (mode_info != NULL &&
-   crtc->enabled && amdgpu_crtc->enabled &&
-   amdgpu_crtc->hw_mode.clock) {
-   line_time_us = 
(amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
-   
amdgpu_crtc->hw_mode.clock;
-   vblank_lines = 
amdgpu_crtc->hw_mode.crtc_vblank_end -
-   
amdgpu_crtc->hw_mode.crtc_vdisplay +
-   (amdgpu_crtc->v_border 
* 2);
-   mode_info->vblank_time_us = vblank_lines * 
line_time_us;
-   mode_info->refresh_rate = 
drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
-   mode_info->ref_clock = 
adev->clock.spll.reference_freq;
-   mode_info = NULL;
+   if (!amdgpu_device_has_dc_support(adev)) {
+   struct amdgpu_crtc *amdgpu_crtc;
+   struct drm_device *ddev = adev->ddev;
+   struct drm_crtc *crtc;
+   uint32_t line_time_us, vblank_lines;
+
+   if (adev->mode_info.num_crtc && 
adev->mode_info.mode_config_initialized) {
+   list_for_each_entry(crtc,
+   &ddev->mode_config.crtc_list, head) {
+   amdgpu_crtc = to_amdgpu_crtc(crtc);
+   if (crtc->enabled) {
+   info->active_display_mask |= (1 << 
amdgpu_crtc->crtc_id);
+   info->display_count++;
+   }
+   if (mode_info != NULL &&
+   crtc->enabled && amdgpu_crtc->enabled &&
+   amdgpu_crtc->hw_mode.clock) {
+   line_time_us = 
(amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
+   
amdgpu_crtc->hw_mode.clock;
+   vblank_lines = 
amdgpu_crtc->hw_mode.crtc_vblank_end -
+   
amdgpu_crtc->hw_mode.crtc_vdisplay +
+   
(amdgpu_crtc->v_border * 2);
+   mode_info->vblank_time_us = 
vblank_lines * line_time_us;
+   mode_info->refresh_rate = 
drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
+   mode_info->ref_clock = 
adev->clock.spll.reference_freq;
+   mode_info = NULL;
+   }
}
}
+   } else {
+   info->display_count = adev->pm.pm_display_cfg.num_display;
+   if (mode_info != NULL) {
+   mode_info->vblank_time_us = 
adev->pm.pm_display_cfg.min_vblank_time;
+   mode_info->refresh_rate = 
adev->pm.pm_display_cfg.vrefresh;
+   mode_info->ref_clock = adev->clock.spll.reference_freq;
+   }
}
-
return 0;
 }
 
-- 
2.5.5

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[PATCH 078/100] drm/amdgpu/gfx9: fullfill kiq irq funcs

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

Fullfill KIQ irq funcs to support kiq interrupt.

Signed-off-by: Xiangliang Yu 
Signed-off-by: Monk Liu 
Reviewed-by: Alex Deucher 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 74 +++
 1 file changed, 74 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 987587a..d694af1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2993,6 +2993,72 @@ static int gfx_v9_0_priv_inst_irq(struct amdgpu_device 
*adev,
return 0;
 }
 
+static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
+   struct amdgpu_irq_src *src,
+   unsigned int type,
+   enum amdgpu_interrupt_state state)
+{
+   uint32_t tmp, target;
+   struct amdgpu_ring *ring = (struct amdgpu_ring *)src->data;
+
+   BUG_ON(!ring || (ring->funcs->type != AMDGPU_RING_TYPE_KIQ));
+
+   if (ring->me == 1)
+   target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
+   else
+   target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
+   target += ring->pipe;
+
+   switch (type) {
+   case AMDGPU_CP_KIQ_IRQ_DRIVER0:
+   if (state == AMDGPU_IRQ_STATE_DISABLE) {
+   tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL));
+   tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
+GENERIC2_INT_ENABLE, 0);
+   WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), tmp);
+
+   tmp = RREG32(target);
+   tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
+GENERIC2_INT_ENABLE, 0);
+   WREG32(target, tmp);
+   } else {
+   tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL));
+   tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
+GENERIC2_INT_ENABLE, 1);
+   WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), tmp);
+
+   tmp = RREG32(target);
+   tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
+GENERIC2_INT_ENABLE, 1);
+   WREG32(target, tmp);
+   }
+   break;
+   default:
+   BUG(); /* kiq only support GENERIC2_INT now */
+   break;
+   }
+   return 0;
+}
+
+static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
+   struct amdgpu_irq_src *source,
+   struct amdgpu_iv_entry *entry)
+{
+   u8 me_id, pipe_id, queue_id;
+   struct amdgpu_ring *ring = (struct amdgpu_ring *)source->data;
+
+   BUG_ON(!ring || (ring->funcs->type != AMDGPU_RING_TYPE_KIQ));
+
+   me_id = (entry->ring_id & 0x0c) >> 2;
+   pipe_id = (entry->ring_id & 0x03) >> 0;
+   queue_id = (entry->ring_id & 0x70) >> 4;
+   DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
+  me_id, pipe_id, queue_id);
+
+   amdgpu_fence_process(ring);
+   return 0;
+}
+
 const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
.name = "gfx_v9_0",
.early_init = gfx_v9_0_early_init,
@@ -3112,6 +3178,11 @@ static void gfx_v9_0_set_ring_funcs(struct amdgpu_device 
*adev)
adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
 }
 
+static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
+   .set = gfx_v9_0_kiq_set_interrupt_state,
+   .process = gfx_v9_0_kiq_irq,
+};
+
 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
.set = gfx_v9_0_set_eop_interrupt_state,
.process = gfx_v9_0_eop_irq,
@@ -3137,6 +3208,9 @@ static void gfx_v9_0_set_irq_funcs(struct amdgpu_device 
*adev)
 
adev->gfx.priv_inst_irq.num_types = 1;
adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
+
+   adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
+   adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
 }
 
 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
-- 
2.5.5

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[PATCH 040/100] drm/amdgpu: add psp firmware header info

2017-03-20 Thread Alex Deucher

From: Huang Rui 

Defines the header info for the psp firmware.

Signed-off-by: Huang Rui 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index 39a0749..758f03a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -50,6 +50,14 @@ struct smc_firmware_header_v1_0 {
 };
 
 /* version_major=1, version_minor=0 */
+struct psp_firmware_header_v1_0 {
+   struct common_firmware_header header;
+   uint32_t ucode_feature_version;
+   uint32_t sos_offset_bytes;
+   uint32_t sos_size_bytes;
+};
+
+/* version_major=1, version_minor=0 */
 struct gfx_firmware_header_v1_0 {
struct common_firmware_header header;
uint32_t ucode_feature_version;
@@ -110,6 +118,7 @@ union amdgpu_firmware_header {
struct common_firmware_header common;
struct mc_firmware_header_v1_0 mc;
struct smc_firmware_header_v1_0 smc;
+   struct psp_firmware_header_v1_0 psp;
struct gfx_firmware_header_v1_0 gfx;
struct rlc_firmware_header_v1_0 rlc;
struct rlc_firmware_header_v2_0 rlc_v2_0;
-- 
2.5.5

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[PATCH 087/100] drm/amdgpu/virt: impl mailbox for ai

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

Implement mailbox protocol for AI so that guest vf can communicate
with GPU hypervisor.

Signed-off-by: Xiangliang Yu 
Reviewed-by: Alex Deucher 
Reviewed-by: Monk Liu 
Acked-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/Makefile   |   2 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 207 ++
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h |  47 
 3 files changed, 255 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index a377fdb..d227695 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -40,7 +40,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o 
kv_dpm.o \
 amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o 
dce_v6_0.o si_dpm.o si_smc.o
 
 amdgpu-y += \
-   vi.o mxgpu_vi.o nbio_v6_1.o soc15.o
+   vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o
 
 # add GMC block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c 
b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
new file mode 100644
index 000..cfd5e54
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -0,0 +1,207 @@
+/*
+ * Copyright 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+#include "vega10/soc15ip.h"
+#include "vega10/NBIO/nbio_6_1_offset.h"
+#include "vega10/NBIO/nbio_6_1_sh_mask.h"
+#include "vega10/GC/gc_9_0_offset.h"
+#include "vega10/GC/gc_9_0_sh_mask.h"
+#include "soc15.h"
+#include "soc15_common.h"
+#include "mxgpu_ai.h"
+
+static void xgpu_ai_mailbox_send_ack(struct amdgpu_device *adev)
+{
+   u32 reg;
+   int timeout = AI_MAILBOX_TIMEDOUT;
+   u32 mask = REG_FIELD_MASK(BIF_BX_PF0_MAILBOX_CONTROL, RCV_MSG_VALID);
+
+   reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
+mmBIF_BX_PF0_MAILBOX_CONTROL));
+   reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_CONTROL, RCV_MSG_ACK, 1);
+   WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
+  mmBIF_BX_PF0_MAILBOX_CONTROL), reg);
+
+   /*Wait for RCV_MSG_VALID to be 0*/
+   reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
+mmBIF_BX_PF0_MAILBOX_CONTROL));
+   while (reg & mask) {
+   if (timeout <= 0) {
+   pr_err("RCV_MSG_VALID is not cleared\n");
+   break;
+   }
+   mdelay(1);
+   timeout -=1;
+
+   reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
+
mmBIF_BX_PF0_MAILBOX_CONTROL));
+   }
+}
+
+static void xgpu_ai_mailbox_set_valid(struct amdgpu_device *adev, bool val)
+{
+   u32 reg;
+
+   reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
+mmBIF_BX_PF0_MAILBOX_CONTROL));
+   reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_CONTROL,
+   TRN_MSG_VALID, val ? 1 : 0);
+   WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL),
+ reg);
+}
+
+static void xgpu_ai_mailbox_trans_msg(struct amdgpu_device *adev,
+ enum idh_request req)
+{
+   u32 reg;
+
+   reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
+
mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0));
+   reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0,
+   MSGBUF_DATA, req);
+   WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, 
mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0),
+ reg);
+
+   xgpu_ai_mailbox_set_valid(adev, true);
+}
+
+static int xgpu_ai_mailbox_rcv_msg(struc

[PATCH 060/100] drm/amd: add structures for display/powerplay interface

2017-03-20 Thread Alex Deucher

From: Eric Huang 

Signed-off-by: Eric Huang 
Acked-by: Alex Deucher 
Acked-by: Tony Cheng 
Acked-by: Harry Wentland 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/include/dm_pp_interface.h | 83 +++
 1 file changed, 83 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/include/dm_pp_interface.h

diff --git a/drivers/gpu/drm/amd/include/dm_pp_interface.h 
b/drivers/gpu/drm/amd/include/dm_pp_interface.h
new file mode 100644
index 000..7343aed
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/dm_pp_interface.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _DM_PP_INTERFACE_
+#define _DM_PP_INTERFACE_
+
+#define PP_MAX_CLOCK_LEVELS 8
+
+struct pp_clock_with_latency {
+   uint32_t clocks_in_khz;
+   uint32_t latency_in_us;
+};
+
+struct pp_clock_levels_with_latency {
+   uint32_t num_levels;
+   struct pp_clock_with_latency data[PP_MAX_CLOCK_LEVELS];
+};
+
+struct pp_clock_with_voltage {
+   uint32_t clocks_in_khz;
+   uint32_t voltage_in_mv;
+};
+
+struct pp_clock_levels_with_voltage {
+   uint32_t num_levels;
+   struct pp_clock_with_voltage data[PP_MAX_CLOCK_LEVELS];
+};
+
+#define PP_MAX_WM_SETS 4
+
+enum pp_wm_set_id {
+   DC_WM_SET_A = 0,
+   DC_WM_SET_B,
+   DC_WM_SET_C,
+   DC_WM_SET_D,
+   DC_WM_SET_INVALID = 0x,
+};
+
+struct pp_wm_set_with_dmif_clock_range_soc15 {
+   enum pp_wm_set_id wm_set_id;
+   uint32_t wm_min_dcefclk_in_khz;
+   uint32_t wm_max_dcefclk_in_khz;
+   uint32_t wm_min_memclk_in_khz;
+   uint32_t wm_max_memclk_in_khz;
+};
+
+struct pp_wm_set_with_mcif_clock_range_soc15 {
+   enum pp_wm_set_id wm_set_id;
+   uint32_t wm_min_socclk_in_khz;
+   uint32_t wm_max_socclk_in_khz;
+   uint32_t wm_min_memclk_in_khz;
+   uint32_t wm_max_memclk_in_khz;
+};
+
+struct pp_wm_sets_with_clock_ranges_soc15 {
+   uint32_t num_wm_sets_dmif;
+   uint32_t num_wm_sets_mcif;
+   struct pp_wm_set_with_dmif_clock_range_soc15
+   wm_sets_dmif[PP_MAX_WM_SETS];
+   struct pp_wm_set_with_mcif_clock_range_soc15
+   wm_sets_mcif[PP_MAX_WM_SETS];
+};
+
+#endif /* _DM_PP_INTERFACE_ */
-- 
2.5.5

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[PATCH 004/100] drm/amdgpu: add basic support for atomfirmware.h (v3)

2017-03-20 Thread Alex Deucher

This adds basic support for asics that use atomfirmware.h
to define their vbios tables.

v2: rebase
v3: squash in num scratch reg fix

Reviewed-by: Ken Wang 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/Makefile  |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  |   3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 112 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h |  33 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   |  38 +---
 5 files changed, 173 insertions(+), 15 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 8870e2e..fbf6474 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -30,7 +30,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
atombios_encoders.o amdgpu_sa.o atombios_i2c.o \
amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
-   amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o
+   amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o
 
 # add asic specific block
 amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 15e985e..b713f37 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -113,7 +113,7 @@ extern int amdgpu_vram_page_split;
 #define AMDGPU_IB_POOL_SIZE16
 #define AMDGPU_DEBUGFS_MAX_COMPONENTS  32
 #define AMDGPUFB_CONN_LIMIT4
-#define AMDGPU_BIOS_NUM_SCRATCH8
+#define AMDGPU_BIOS_NUM_SCRATCH16
 
 /* max number of IP instances */
 #define AMDGPU_MAX_SDMA_INSTANCES  2
@@ -1318,6 +1318,7 @@ struct amdgpu_device {
uint8_t *bios;
uint32_tbios_size;
struct amdgpu_bo*stollen_vga_memory;
+   uint32_tbios_scratch_reg_offset;
uint32_tbios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
 
/* Register/doorbell mmio */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
new file mode 100644
index 000..4b9abd6
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include 
+#include 
+#include "amdgpu.h"
+#include "atomfirmware.h"
+#include "amdgpu_atomfirmware.h"
+#include "atom.h"
+
+#define get_index_into_master_table(master_table, table_name) (offsetof(struct 
master_table, table_name) / sizeof(uint16_t))
+
+bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device 
*adev)
+{
+   int index = 
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+   firmwareinfo);
+   uint16_t data_offset;
+
+   if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, 
NULL,
+ NULL, NULL, &data_offset)) {
+   struct atom_firmware_info_v3_1 *firmware_info =
+   (struct atom_firmware_info_v3_1 
*)(adev->mode_info.atom_context->bios +
+  data_offset);
+
+   if (le32_to_cpu(firmware_info->firmware_capability) &
+   ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION)
+   return true;
+   }
+   return false;
+}
+
+void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
+{
+

[PATCH 093/100] drm/amdgpu: disable uvd for sriov

2017-03-20 Thread Alex Deucher

From: Xiangliang Yu 

disable uvd for sriov temporarily.

Signed-off-by: Xiangliang Yu 
Signed-off-by: Monk Liu 
Reviewed-by: Alex Deucher 
Acked-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index a7b5338..54cb0b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -496,7 +496,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
 #endif
amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
-   amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block);
+   if (!amdgpu_sriov_vf(adev))
+   amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block);
amdgpu_ip_block_add(adev, &vce_v4_0_ip_block);
break;
default:
-- 
2.5.5

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[PATCH 021/100] drm/amd: Add MQD structs for GFX V9

2017-03-20 Thread Alex Deucher

From: Felix Kuehling 

This header defines the gfx v9 MEC structures.

Signed-off-by: Felix Kuehling 
Reviewed-by: Shaoyun Liu 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/include/v9_structs.h | 675 +++
 1 file changed, 675 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/include/v9_structs.h

diff --git a/drivers/gpu/drm/amd/include/v9_structs.h 
b/drivers/gpu/drm/amd/include/v9_structs.h
new file mode 100644
index 000..e7508a3
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/v9_structs.h
@@ -0,0 +1,675 @@
+/*
+ * Copyright 2012-2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef V9_STRUCTS_H_
+#define V9_STRUCTS_H_
+
+struct v9_sdma_mqd {
+   uint32_t sdmax_rlcx_rb_cntl;
+   uint32_t sdmax_rlcx_rb_base;
+   uint32_t sdmax_rlcx_rb_base_hi;
+   uint32_t sdmax_rlcx_rb_rptr;
+   uint32_t sdmax_rlcx_rb_wptr;
+   uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
+   uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;
+   uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;
+   uint32_t sdmax_rlcx_rb_rptr_addr_hi;
+   uint32_t sdmax_rlcx_rb_rptr_addr_lo;
+   uint32_t sdmax_rlcx_ib_cntl;
+   uint32_t sdmax_rlcx_ib_rptr;
+   uint32_t sdmax_rlcx_ib_offset;
+   uint32_t sdmax_rlcx_ib_base_lo;
+   uint32_t sdmax_rlcx_ib_base_hi;
+   uint32_t sdmax_rlcx_ib_size;
+   uint32_t sdmax_rlcx_skip_cntl;
+   uint32_t sdmax_rlcx_context_status;
+   uint32_t sdmax_rlcx_doorbell;
+   uint32_t sdmax_rlcx_virtual_addr;
+   uint32_t sdmax_rlcx_ape1_cntl;
+   uint32_t sdmax_rlcx_doorbell_log;
+   uint32_t reserved_22;
+   uint32_t reserved_23;
+   uint32_t reserved_24;
+   uint32_t reserved_25;
+   uint32_t reserved_26;
+   uint32_t reserved_27;
+   uint32_t reserved_28;
+   uint32_t reserved_29;
+   uint32_t reserved_30;
+   uint32_t reserved_31;
+   uint32_t reserved_32;
+   uint32_t reserved_33;
+   uint32_t reserved_34;
+   uint32_t reserved_35;
+   uint32_t reserved_36;
+   uint32_t reserved_37;
+   uint32_t reserved_38;
+   uint32_t reserved_39;
+   uint32_t reserved_40;
+   uint32_t reserved_41;
+   uint32_t reserved_42;
+   uint32_t reserved_43;
+   uint32_t reserved_44;
+   uint32_t reserved_45;
+   uint32_t reserved_46;
+   uint32_t reserved_47;
+   uint32_t reserved_48;
+   uint32_t reserved_49;
+   uint32_t reserved_50;
+   uint32_t reserved_51;
+   uint32_t reserved_52;
+   uint32_t reserved_53;
+   uint32_t reserved_54;
+   uint32_t reserved_55;
+   uint32_t reserved_56;
+   uint32_t reserved_57;
+   uint32_t reserved_58;
+   uint32_t reserved_59;
+   uint32_t reserved_60;
+   uint32_t reserved_61;
+   uint32_t reserved_62;
+   uint32_t reserved_63;
+   uint32_t reserved_64;
+   uint32_t reserved_65;
+   uint32_t reserved_66;
+   uint32_t reserved_67;
+   uint32_t reserved_68;
+   uint32_t reserved_69;
+   uint32_t reserved_70;
+   uint32_t reserved_71;
+   uint32_t reserved_72;
+   uint32_t reserved_73;
+   uint32_t reserved_74;
+   uint32_t reserved_75;
+   uint32_t reserved_76;
+   uint32_t reserved_77;
+   uint32_t reserved_78;
+   uint32_t reserved_79;
+   uint32_t reserved_80;
+   uint32_t reserved_81;
+   uint32_t reserved_82;
+   uint32_t reserved_83;
+   uint32_t reserved_84;
+   uint32_t reserved_85;
+   uint32_t reserved_86;
+   uint32_t reserved_87;
+   uint32_t reserved_88;
+   uint32_t reserved_89;
+   uint32_t reserved_90;
+   uint32_t reserved_91;
+   uint32_t reserved_92;
+   uint32_t reserved_93;
+   uint32_t reserved_94;
+   uint32_t reserved_95;
+   uint32_t reserved_96;
+   uint32_t reserved_97;
+   uint32_t reserved

[PATCH 080/100] drm/amdgpu:impl gfx9 cond_exec

2017-03-20 Thread Alex Deucher

From: Monk Liu 

it is needed for virtualization

Signed-off-by: Monk Liu 
Signed-off-by: Xiangliang Yu 
Reviewed-by: Alex Deucher 
Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 2f833ca..6f266d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3218,6 +3218,30 @@ static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring 
*ring, uint32_t flags)
amdgpu_ring_write(ring, 0);
 }
 
+static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
+{
+   unsigned ret;
+   amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
+   amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
+   amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
+   amdgpu_ring_write(ring, 0); /* discard following DWs if 
*cond_exec_gpu_addr==0 */
+   ret = ring->wptr;
+   amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
+   return ret;
+}
+
+static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, 
unsigned offset)
+{
+   unsigned cur;
+   BUG_ON(ring->ring[offset] != 0x55aa55aa);
+
+   cur = ring->wptr - 1;
+   if (likely(cur > offset))
+   ring->ring[offset] = cur - offset;
+   else
+   ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
+}
+
 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
 {
struct amdgpu_device *adev = ring->adev;
@@ -3569,6 +3593,8 @@ static const struct amdgpu_ring_funcs 
gfx_v9_0_ring_funcs_gfx = {
.pad_ib = amdgpu_ring_generic_pad_ib,
.emit_switch_buffer = gfx_v9_ring_emit_sb,
.emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
+   .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
+   .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
 };
 
 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
-- 
2.5.5

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[PATCH 001/100] drm/amdgpu: add the new atomfirmware interface header

2017-03-20 Thread Alex Deucher

soc15 asics have a new vbios interface.  These headers
define that interface.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/include/atomfirmware.h   | 2385 ++
 drivers/gpu/drm/amd/include/atomfirmwareid.h |   86 +
 drivers/gpu/drm/amd/include/displayobject.h  |  249 +++
 3 files changed, 2720 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/include/atomfirmware.h
 create mode 100644 drivers/gpu/drm/amd/include/atomfirmwareid.h
 create mode 100644 drivers/gpu/drm/amd/include/displayobject.h

diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h 
b/drivers/gpu/drm/amd/include/atomfirmware.h
new file mode 100644
index 000..d386875
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -0,0 +1,2385 @@
+/\
+* 
+*  File Name  atomfirmware.h
+*  ProjectThis is an interface header file between atombios and OS GPU 
drivers for SoC15 products
+*
+*  Descriptionheader file of general definitions for OS nd pre-OS video 
drivers 
+*
+*  Copyright 2014 Advanced Micro Devices, Inc.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy 
of this software 
+* and associated documentation files (the "Software"), to deal in the Software 
without restriction,
+* including without limitation the rights to use, copy, modify, merge, 
publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the 
Software is furnished to do so,
+* subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in 
all copies or substantial
+* portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+\/
+
+/*IMPORTANT NOTES
+* If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and 
forward products, then the change is only needed in this atomfirmware.h header 
file.
+* If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 
products, then the change is only needed in atombios.h header file.
+* If a change is needed for both pre and post SoC15 products, then the change 
has to be made separately and might be differently in both atomfirmware.h and 
atombios.h.
+*/
+
+#ifndef _ATOMFIRMWARE_H_
+#define _ATOMFIRMWARE_H_
+
+enum  atom_bios_header_version_def{
+  ATOM_MAJOR_VERSION=0x0003,
+  ATOM_MINOR_VERSION=0x0003,
+};
+
+#ifdef _H2INC
+  #ifndef uint32_t
+typedef unsigned long uint32_t;
+  #endif
+
+  #ifndef uint16_t
+typedef unsigned short uint16_t;
+  #endif
+
+  #ifndef uint8_t 
+typedef unsigned char uint8_t;
+  #endif
+#endif
+
+enum atom_crtc_def{
+  ATOM_CRTC1  =0,
+  ATOM_CRTC2  =1,
+  ATOM_CRTC3  =2,
+  ATOM_CRTC4  =3,
+  ATOM_CRTC5  =4,
+  ATOM_CRTC6  =5,
+  ATOM_CRTC_INVALID  =0xff,
+};
+
+enum atom_ppll_def{
+  ATOM_PPLL0  =2,
+  ATOM_GCK_DFS=8,
+  ATOM_FCH_CLK=9,
+  ATOM_DP_DTO =11,
+  ATOM_COMBOPHY_PLL0  =20,
+  ATOM_COMBOPHY_PLL1  =21,
+  ATOM_COMBOPHY_PLL2  =22,
+  ATOM_COMBOPHY_PLL3  =23,
+  ATOM_COMBOPHY_PLL4  =24,
+  ATOM_COMBOPHY_PLL5  =25,
+  ATOM_PPLL_INVALID   =0xff,
+};
+
+// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel
+enum atom_dig_def{
+  ASIC_INT_DIG1_ENCODER_ID  =0x03,
+  ASIC_INT_DIG2_ENCODER_ID  =0x09,
+  ASIC_INT_DIG3_ENCODER_ID  =0x0a,
+  ASIC_INT_DIG4_ENCODER_ID  =0x0b,
+  ASIC_INT_DIG5_ENCODER_ID  =0x0c,
+  ASIC_INT_DIG6_ENCODER_ID  =0x0d,
+  ASIC_INT_DIG7_ENCODER_ID  =0x0e,
+};
+
+//ucEncoderMode
+enum atom_encode_mode_def
+{
+  ATOM_ENCODER_MODE_DP  =0,
+  ATOM_ENCODER_MODE_DP_SST  =0,
+  ATOM_ENCODER_MODE_LVDS=1,
+  ATOM_ENCODER_MODE_DVI =2,
+  ATOM_ENCODER_MODE_HDMI=3,
+  ATOM_ENCODER_MODE_DP_AUDIO=5,
+  ATOM_ENCODER_MODE_DP_MST  =5,
+  ATOM_ENCODER_MODE_CRT =15,
+  ATOM_ENCODER_MODE_DVO =16,
+};
+
+enum atom_encoder_refclk_src_def{
+  ENCODER_REFCLK_SRC_P1PLL  =0,
+  ENCODER_REFCLK_SRC_P2PLL  =1,
+  ENCODER_REFCLK_SRC_P3PLL  =2,
+  ENCODER_REFCLK_SRC_EXTCLK =3,
+  ENCODER_REFCLK_SRC_INVALID=0xff,
+};
+
+enum atom_scaler_def{
+  ATOM_SCALER_DISABLE  =0,  /*scaler bypass mode, auto-center & no 
replication*/
+  ATOM_SCALER_CENTER   =1,  //For Fudo, it's bypass and auto-center & 
auto replication
+  ATOM_SCALER_EXPANSION=2,  /*scaler expansion by 2 tap alpha blending 
mo

[PATCH 056/100] drm/amd/powerplay: add new Vega10's ppsmc header file

2017-03-20 Thread Alex Deucher

From: Eric Huang 

Signed-off-by: Eric Huang 
Reviewed-by: Ken Wang 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h | 131 +++
 1 file changed, 131 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h

diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h 
b/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
new file mode 100644
index 000..90beef3
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef PP_SMC_H
+#define PP_SMC_H
+
+#pragma pack(push, 1)
+
+#define SMU_UCODE_VERSION  0x001c0800
+
+/* SMU Response Codes: */
+#define PPSMC_Result_OK0x1
+#define PPSMC_Result_Failed0xFF
+#define PPSMC_Result_UnknownCmd0xFE
+#define PPSMC_Result_CmdRejectedPrereq 0xFD
+#define PPSMC_Result_CmdRejectedBusy   0xFC
+
+typedef uint16_t PPSMC_Result;
+
+/* Message Definitions */
+#define PPSMC_MSG_TestMessage0x1
+#define PPSMC_MSG_GetSmuVersion  0x2
+#define PPSMC_MSG_GetDriverIfVersion 0x3
+#define PPSMC_MSG_EnableSmuFeatures  0x4
+#define PPSMC_MSG_DisableSmuFeatures 0x5
+#define PPSMC_MSG_GetEnabledSmuFeatures  0x6
+#define PPSMC_MSG_SetWorkloadMask0x7
+#define PPSMC_MSG_SetPptLimit0x8
+#define PPSMC_MSG_SetDriverDramAddrHigh  0x9
+#define PPSMC_MSG_SetDriverDramAddrLow   0xA
+#define PPSMC_MSG_SetToolsDramAddrHigh   0xB
+#define PPSMC_MSG_SetToolsDramAddrLow0xC
+#define PPSMC_MSG_TransferTableSmu2Dram  0xD
+#define PPSMC_MSG_TransferTableDram2Smu  0xE
+#define PPSMC_MSG_UseDefaultPPTable  0xF
+#define PPSMC_MSG_UseBackupPPTable   0x10
+#define PPSMC_MSG_RunBtc 0x11
+#define PPSMC_MSG_RequestI2CBus  0x12
+#define PPSMC_MSG_ReleaseI2CBus  0x13
+#define PPSMC_MSG_ConfigureTelemetry 0x14
+#define PPSMC_MSG_SetUlvIpMask   0x15
+#define PPSMC_MSG_SetSocVidOffset0x16
+#define PPSMC_MSG_SetMemVidOffset0x17
+#define PPSMC_MSG_GetSocVidOffset0x18
+#define PPSMC_MSG_GetMemVidOffset0x19
+#define PPSMC_MSG_SetFloorSocVoltage 0x1A
+#define PPSMC_MSG_SoftReset  0x1B
+#define PPSMC_MSG_StartBacoMonitor   0x1C
+#define PPSMC_MSG_CancelBacoMonitor  0x1D
+#define PPSMC_MSG_EnterBaco  0x1E
+#define PPSMC_MSG_AllowLowGfxclkInterrupt0x1F
+#define PPSMC_MSG_SetLowGfxclkInterruptThreshold 0x20
+#define PPSMC_MSG_SetSoftMinGfxclkByIndex0x21
+#define PPSMC_MSG_SetSoftMaxGfxclkByIndex0x22
+#define PPSMC_MSG_GetCurrentGfxclkIndex  0x23
+#define PPSMC_MSG_SetSoftMinUclkByIndex  0x24
+#define PPSMC_MSG_SetSoftMaxUclkByIndex  0x25
+#define PPSMC_MSG_GetCurrentUclkIndex0x26
+#define PPSMC_MSG_SetSoftMinUvdByIndex   0x27
+#define PPSMC_MSG_SetSoftMaxUvdByIndex   0x28
+#define PPSMC_MSG_GetCurrentUvdIndex 0x29
+#define PPSMC_MSG_SetSoftMinVceByIndex   0x2A
+#define PPSMC_MSG_SetSoftMaxVceByIndex   0x2B
+#define PPSMC_MSG_SetHardMinVceByIndex   0x2C
+#define PPSMC_MSG_GetCurrentVceIndex 0x2D
+#define PPSMC_MSG_SetSoftMinSocclkByIndex0x2E
+#define PPSMC_MSG_SetHardMinSocclkByIndex0x2F
+#define PPSMC_MSG_SetSoftMaxSocclkByIndex0x30
+#define PPSMC_MSG_GetCurrentSocclkIndex  0x31
+#define PPSMC_MSG_SetMinLinkDpmByIndex   0x32
+#define PPSMC_MSG_GetCurrentLinkIndex0x33
+#define PPSMC_MSG_GetAverageGfxclk

[PATCH 032/100] drm/amdgpu: update IH IV ring entry for soc-15

2017-03-20 Thread Alex Deucher

Reflect the new format on soc-15 asics.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index 043620d..a3da1a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -93,11 +93,14 @@ struct amdgpu_ih_ring {
 struct amdgpu_iv_entry {
unsigned client_id;
unsigned src_id;
-   unsigned src_data[AMDGPU_IH_SRC_DATA_MAX_SIZE_DW];
unsigned ring_id;
unsigned vm_id;
unsigned vm_id_src;
+   uint64_t timestamp;
+   unsigned timestamp_src;
unsigned pas_id;
+   unsigned pasid_src;
+   unsigned src_data[AMDGPU_IH_SRC_DATA_MAX_SIZE_DW];
const uint32_t *iv_entry;
 };
 
-- 
2.5.5

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[PATCH 034/100] drm/amdgpu: add PTE defines for MTYPE

2017-03-20 Thread Alex Deucher

New on SOC-15 asics.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 8e5abd2..c2e4604 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -67,6 +67,10 @@ struct amdgpu_bo_list_entry;
 
 #define AMDGPU_PTE_PRT (1ULL << 63)
 
+/* VEGA10 only */
+#define AMDGPU_PTE_MTYPE(a)((uint64_t)a << 57)
+#define AMDGPU_PTE_MTYPE_MASK  AMDGPU_PTE_MTYPE(3ULL)
+
 /* How to programm VM fault handling */
 #define AMDGPU_VM_FAULT_STOP_NEVER 0
 #define AMDGPU_VM_FAULT_STOP_FIRST 1
-- 
2.5.5

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[PATCH 025/100] drm/amdgpu: add vega10 chip name

2017-03-20 Thread Alex Deucher

From: Ken Wang 

Signed-off-by: Ken Wang 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
 drivers/gpu/drm/amd/include/amd_shared.h   | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5a17899..7295cbc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -76,6 +76,7 @@ static const char *amdgpu_asic_name[] = {
"POLARIS10",
"POLARIS11",
"POLARIS12",
+   "VEGA10",
"LAST",
 };
 
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h 
b/drivers/gpu/drm/amd/include/amd_shared.h
index 4f61879..717d6be 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -47,6 +47,7 @@ enum amd_asic_type {
CHIP_POLARIS10,
CHIP_POLARIS11,
CHIP_POLARIS12,
+   CHIP_VEGA10,
CHIP_LAST,
 };
 
-- 
2.5.5

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[PATCH 030/100] drm/amdgpu: Add MTYPE flags to GPU VM IOCTL interface

2017-03-20 Thread Alex Deucher

From: Alex Xie 

Signed-off-by: Alex Xie 
Reviewed-by: Alex Deucher 
Reviewed-by: Christian KÃ¶nig 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c |  2 +-
 include/uapi/drm/amdgpu_drm.h   | 12 
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index ba9077b..f9bea8b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -557,7 +557,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 {
const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
-   AMDGPU_VM_PAGE_EXECUTABLE;
+   AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK;
const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
AMDGPU_VM_PAGE_PRT;
 
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index dd6c934..d4ad2a1 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -365,6 +365,18 @@ struct drm_amdgpu_gem_op {
 #define AMDGPU_VM_PAGE_EXECUTABLE  (1 << 3)
 /* partially resident texture */
 #define AMDGPU_VM_PAGE_PRT (1 << 4)
+/* MTYPE flags use bit 5 to 8 */
+#define AMDGPU_VM_MTYPE_MASK   (0xf << 5)
+/* Default MTYPE. Pre-AI must use this.  Recommended for newer ASICs. */
+#define AMDGPU_VM_MTYPE_DEFAULT(0 << 5)
+/* Use NC MTYPE instead of default MTYPE */
+#define AMDGPU_VM_MTYPE_NC (1 << 5)
+/* Use WC MTYPE instead of default MTYPE */
+#define AMDGPU_VM_MTYPE_WC (2 << 5)
+/* Use CC MTYPE instead of default MTYPE */
+#define AMDGPU_VM_MTYPE_CC (3 << 5)
+/* Use UC MTYPE instead of default MTYPE */
+#define AMDGPU_VM_MTYPE_UC (4 << 5)
 
 struct drm_amdgpu_gem_va {
/** GEM object handle */
-- 
2.5.5

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[PATCH 050/100] drm/amdgpu: add initial uvd 7.0 support for vega10

2017-03-20 Thread Alex Deucher

From: Leo Liu 

Signed-off-by: Leo Liu 
Reviewed-by: Alex Deucher 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/Makefile |3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c |   52 +-
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c   | 1543 +++
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.h   |   29 +
 4 files changed, 1615 insertions(+), 12 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.h

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index bc29569..65829fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -84,7 +84,8 @@ amdgpu-y += \
 amdgpu-y += \
amdgpu_uvd.o \
uvd_v5_0.o \
-   uvd_v6_0.o
+   uvd_v6_0.o \
+   uvd_v7_0.o
 
 # add VCE block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 02b8613..b2e1d3b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -67,6 +67,14 @@
 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin"
 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin"
 
+#define FIRMWARE_VEGA10"amdgpu/vega10_uvd.bin"
+
+#define mmUVD_GPCOM_VCPU_DATA0_VEGA10 (0x03c4 + 0x7e00)
+#define mmUVD_GPCOM_VCPU_DATA1_VEGA10 (0x03c5 + 0x7e00)
+#define mmUVD_GPCOM_VCPU_CMD_VEGA10 (0x03c3 + 0x7e00)
+#define mmUVD_NO_OP_VEGA10 (0x03ff + 0x7e00)
+#define mmUVD_ENGINE_CNTL_VEGA10 (0x03c6 + 0x7e00)
+
 /**
  * amdgpu_uvd_cs_ctx - Command submission parser context
  *
@@ -101,6 +109,8 @@ MODULE_FIRMWARE(FIRMWARE_POLARIS10);
 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
 
+MODULE_FIRMWARE(FIRMWARE_VEGA10);
+
 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
 
 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
@@ -151,6 +161,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
case CHIP_POLARIS11:
fw_name = FIRMWARE_POLARIS11;
break;
+   case CHIP_VEGA10:
+   fw_name = FIRMWARE_VEGA10;
+   break;
case CHIP_POLARIS12:
fw_name = FIRMWARE_POLARIS12;
break;
@@ -203,9 +216,11 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too 
old.\n",
  version_major, version_minor);
 
-   bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
- +  AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
+   bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
  +  AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
+   if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
+   bo_size += 
AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
+
r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.vcpu_bo,
&adev->uvd.gpu_addr, &adev->uvd.cpu_addr);
@@ -319,11 +334,13 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev)
unsigned offset;
 
hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
-   offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
-   memcpy_toio(adev->uvd.cpu_addr, adev->uvd.fw->data + offset,
-   le32_to_cpu(hdr->ucode_size_bytes));
-   size -= le32_to_cpu(hdr->ucode_size_bytes);
-   ptr += le32_to_cpu(hdr->ucode_size_bytes);
+   if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+   offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
+   memcpy_toio(adev->uvd.cpu_addr, adev->uvd.fw->data + 
offset,
+   le32_to_cpu(hdr->ucode_size_bytes));
+   size -= le32_to_cpu(hdr->ucode_size_bytes);
+   ptr += le32_to_cpu(hdr->ucode_size_bytes);
+   }
memset_io(ptr, 0, size);
}
 
@@ -936,6 +953,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, 
struct amdgpu_bo *bo,
struct fence *f = NULL;
struct amdgpu_device *adev = ring->adev;
uint64_t addr;
+   uint32_t data[4];
int i, r;
 
memset(&tv, 0, sizeof(tv));
@@ -961,16 +979,28 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, 
struct amdgpu_bo *bo,
if (r)
goto err;
 
+   if (adev->asic_type >= CHIP_VEGA10) {
+   data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0_VEGA10, 0);
+   data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1_VEGA10, 0);
+   data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD_VEGA10, 0);
+   data[3] = PACKET0(mmUVD_NO_OP_VEGA10, 0);
+   } else {
+   data[0] = PACKET0(mmUVD_

[PATCH 028/100] drm/amdgpu: gb_addr_config struct

2017-03-20 Thread Alex Deucher

From: Andrey Grodzovsky 

Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Ken Wang 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 4d06de8b..ae4cb07 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -831,6 +831,15 @@ struct amdgpu_rb_config {
uint32_t raster_config_1;
 };
 
+struct gb_addr_config {
+   uint16_t pipe_interleave_size;
+   uint8_t num_pipes;
+   uint8_t max_compress_frags;
+   uint8_t num_banks;
+   uint8_t num_se;
+   uint8_t num_rb_per_se;
+};
+
 struct amdgpu_gfx_config {
unsigned max_shader_engines;
unsigned max_tile_pipes;
@@ -860,6 +869,7 @@ struct amdgpu_gfx_config {
uint32_t tile_mode_array[32];
uint32_t macrotile_mode_array[16];
 
+   struct gb_addr_config gb_addr_config_fields;
struct amdgpu_rb_config 
rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
 
/* gfx configure feature */
-- 
2.5.5

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[PATCH 000/100] Add Vega10 Support

2017-03-20 Thread Alex Deucher

This patch set adds support for vega10.  Major changes and supported
features:
- new vbios interface
- Lots of new hw IPs
- Support for video decode using UVD
- Support for video encode using VCE
- Support for 3D via radeonsi
- Power management
- Full display support via DC
- Support for SR-IOV

I did not send out the register headers since they are huge.  You can find them
along with all the other patches in this series here:
https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-4.9

Please review.

Thanks,

Alex

Alex Deucher (29):
  drm/amdgpu: add the new atomfirmware interface header
  amdgpu: detect if we are using atomfirm or atombios for vbios (v2)
  drm/amdgpu: move atom scratch setup into amdgpu_atombios.c
  drm/amdgpu: add basic support for atomfirmware.h (v3)
  drm/amdgpu: add soc15ip.h
  drm/amdgpu: add vega10_enum.h
  drm/amdgpu: Add ATHUB 1.0 register headers
  drm/amdgpu: Add the DCE 12.0 register headers
  drm/amdgpu: add the GC 9.0 register headers
  drm/amdgpu: add the HDP 4.0 register headers
  drm/amdgpu: add the MMHUB 1.0 register headers
  drm/amdgpu: add MP 9.0 register headers
  drm/amdgpu: add NBIF 6.1 register headers
  drm/amdgpu: add NBIO 6.1 register headers
  drm/amdgpu: add OSSSYS 4.0 register headers
  drm/amdgpu: add SDMA 4.0 register headers
  drm/amdgpu: add SMUIO 9.0 register headers
  drm/amdgpu: add THM 9.0 register headers
  drm/amdgpu: add the UVD 7.0 register headers
  drm/amdgpu: add the VCE 4.0 register headers
  drm/amdgpu: add gfx9 clearstate header
  drm/amdgpu: add SDMA 4.0 packet header
  drm/amdgpu: use atomfirmware interfaces for scratch reg save/restore
  drm/amdgpu: update IH IV ring entry for soc-15
  drm/amdgpu: add PTE defines for MTYPE
  drm/amdgpu: add NGG parameters
  drm/amdgpu: Add asic family for vega10
  drm/amdgpu: add tiling flags for GFX9
  drm/amdgpu: gart fixes for vega10

Alex Xie (4):
  drm/amdgpu: Add MTYPE flags to GPU VM IOCTL interface
  drm/amdgpu: handle PTE EXEC in amdgpu_vm_bo_split_mapping
  drm/amdgpu: handle PTE MTYPE in amdgpu_vm_bo_split_mapping
  drm/amdgpu: Add GMC 9.0 support

Andrey Grodzovsky (1):
  drm/amdgpu: gb_addr_config struct

Charlene Liu (1):
  drm/amd/display: need to handle DCE_Info table ver4.2

Christian König (1):
  drm/amdgpu: add IV trace point

Eric Huang (7):
  drm/amd/powerplay: add smu9 header files for Vega10
  drm/amd/powerplay: add new Vega10's ppsmc header file
  drm/amdgpu: add new atomfirmware based helpers for powerplay
  drm/amd/powerplay: add some new structures for Vega10
  drm/amd: add structures for display/powerplay interface
  drm/amd/powerplay: add some display/powerplay interfaces
  drm/amd/powerplay: add Vega10 powerplay support

Felix Kuehling (1):
  drm/amd: Add MQD structs for GFX V9

Harry Wentland (6):
  drm/amd/display: Add DCE12 bios parser support
  drm/amd/display: Add DCE12 gpio support
  drm/amd/display: Add DCE12 i2c/aux support
  drm/amd/display: Add DCE12 irq support
  drm/amd/display: Add DCE12 core support
  drm/amd/display: Enable DCE12 support

Huang Rui (6):
  drm/amdgpu: use new flag to handle different firmware loading method
  drm/amdgpu: rework common ucode handling for vega10
  drm/amdgpu: add psp firmware header info
  drm/amdgpu: add PSP driver for vega10
  drm/amdgpu: add psp firmware info into info query and debugfs
  drm/amdgpu: add SMC firmware into global ucode list for psp loading

Jordan Lazare (1):
  drm/amd/display: Less log spam

Junwei Zhang (2):
  drm/amdgpu: add NBIO 6.1 driver
  drm/amdgpu: add Vega10 Device IDs

Ken Wang (8):
  drm/amdgpu: add common soc15 headers
  drm/amdgpu: add vega10 chip name
  drm/amdgpu: add 64bit doorbell assignments
  drm/amdgpu: add SDMA v4.0 implementation
  drm/amdgpu: implement GFX 9.0 support
  drm/amdgpu: add vega10 interrupt handler
  drm/amdgpu: soc15 enable (v2)
  drm/amdgpu: Set the IP blocks for vega10

Leo Liu (2):
  drm/amdgpu: add initial uvd 7.0 support for vega10
  drm/amdgpu: add initial vce 4.0 support for vega10

Marek Olšák (1):
  drm/amdgpu: don't validate TILE_SPLIT on GFX9

Monk Liu (5):
  drm/amdgpu/gfx9: programing wptr_poll_addr register
  drm/amdgpu:impl gfx9 cond_exec
  drm/amdgpu:bypass RLC init for SRIOV
  drm/amdgpu/sdma4:re-org SDMA initial steps for sriov
  drm/amdgpu/vega10:fix DOORBELL64 scheme

Rex Zhu (2):
  drm/amdgpu: get display info from DC when DC enabled.
  drm/amd/powerplay: add global PowerPlay mutex.

Xiangliang Yu (22):
  drm/amdgpu: impl sriov detection for vega10
  drm/amdgpu: add kiq ring for gfx9
  drm/amdgpu/gfx9: fullfill kiq funcs
  drm/amdgpu/gfx9: fullfill kiq irq funcs
  drm/amdgpu: init kiq and kcq for vega10
  drm/amdgpu/gfx9: impl gfx9 meta data emit
  drm/amdgpu/soc15: bypass PSP for VF
  drm/amdgpu/gmc9: no need use kiq in vega10 tlb flush
  drm/amdgpu/dce_virtual: bypass DPM for vf
  drm/amdgpu/virt: impl mailbox for ai
  drm/amdgpu/soc15: init virt ops for vf
  drm/amdgpu/soc15: enable virtual dce for vf
  drm/amdgpu: Don't touch PG&CG for SRIOV M

[PATCH umr] Add more PKT3 decoders ...

2017-03-20 Thread Tom St Denis

Various SI related PKT3 decoders.

Signed-off-by: Tom St Denis 
---
 src/lib/ring_decode.c | 52 +++
 1 file changed, 52 insertions(+)

diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c
index a991f5ffa237..ab1cb9d46411 100644
--- a/src/lib/ring_decode.c
+++ b/src/lib/ring_decode.c
@@ -322,8 +322,20 @@ static void print_decode_pm4_pkt3(struct umr_asic *asic, 
struct umr_ring_decoder
static const char *op_3c_functions[] = { "true", "<", "<=", "==", "!=", 
">=", ">", "reserved" };
static const char *op_37_engines[] = { "ME", "PFP", "CE", "DE" };
static const char *op_37_dst_sel[] = { "mem-mapped reg", "memory sync", 
"TC/L2", "GDS", "reserved", "memory async", "reserved", "reserved" };
+   struct umr_reg *reg;
printf("   PKT3 OPCODE 0x%02x, word %u: ", 
(unsigned)decoder->pm4.cur_opcode, (unsigned)decoder->pm4.cur_word);
switch (decoder->pm4.cur_opcode) {
+   case 0x28: // CONTEXT_CONTROL
+   switch (decoder->pm4.cur_word) {
+   case 0: printf("LOAD_EN: %lu, LOAD_CS: %lu, 
LOAD_GFX: %lu, LOAD_MULTI: %lu, LOAD_SINGLE: %lu",
+   BITS(ib, 31, 32), BITS(ib, 24, 
25), BITS(ib, 16,17), BITS(ib, 1,2), BITS(ib, 0, 1));
+   break;
+   case 1: printf("SHADOW_EN: %lu, SHADOW_CS: %lu, 
SHADOW_GFX: %lu, SHADOW_MULTI: %lu, SHADOW_SINGLE: %lu",
+   BITS(ib, 31, 32), BITS(ib, 24, 
25), BITS(ib, 16,17), BITS(ib, 1,2), BITS(ib, 0, 1));
+   break;
+   default: printf("Invalid word for opcode 
0x%02lx", (unsigned long)decoder->pm4.cur_opcode);
+   }
+   break;
case 0x3f: // INDIRECT_BUFFER_CIK
case 0x33: // INDIRECT_BUFFER_CONST
switch (decoder->pm4.cur_word) {
@@ -388,6 +400,37 @@ static void print_decode_pm4_pkt3(struct umr_asic *asic, 
struct umr_ring_decoder
default: printf("Invalid word for opcode 
0x%02lx", (unsigned long)decoder->pm4.cur_opcode);
}
break;
+   case 0x43: // SURFACE_SYNC
+   switch (decoder->pm4.cur_word) {
+   case 0: printf("ENGINE: %s, COHER_CNTL: 
0x%08lx",
+   BITS(ib, 31, 32) ? "ME" : "PFP",
+   BITS(ib, 0, 29));
+   reg = umr_find_reg_data(asic, 
"mmCP_COHER_CNTL");
+   if (reg && reg->bits) {
+   int i, k;
+   k = 0;
+   printf(" (");
+   for (i = 0; i < reg->no_bits; 
i++) {
+   if (ib & (1UL << 
reg->bits[i].start)) {
+   printf("%s%s", 
k ? ", " : "", reg->bits[i].regname);
+   ++k;
+   }
+   }
+   printf(")");
+   }
+   break;
+   case 1:
+   printf("COHER_SIZE: 0x%08lx", (unsigned 
long)ib);
+   break;
+   case 2:
+   printf("COHER_BASE: 0x%08lx", (unsigned 
long)ib);
+   break;
+   case 3:
+   printf("POLL_INTERVAL: %lu", BITS(ib, 
0, 16));
+   break;
+   default: printf("Invalid word for opcode 
0x%02lx", (unsigned long)decoder->pm4.cur_opcode);
+   }
+   break;
case 0x47: // EVENT_WRITE_EOP
switch(decoder->pm4.cur_word) {
case 0: printf("INV_L2:%lu, EVENT_INDEX:%lu, 
EVENT_TYPE:%lu",
@@ -429,6 +472,15 @@ static void print_decode_pm4_pkt3(struct umr_asic *asic, 
struct umr_ring_decoder
default: printf("Invalid word for opcode 
0x%02lx", (unsigned long)decoder->pm4.cur_opcode);
}
break;
+   case 0x68: // SET_CONFIG_REG
+   switch(decoder->pm4.cur_word) {
+   case 0: decoder->pm4.next_write_mem.addr_lo = 
BITS(ib, 0, 16

[PATCH umr] sync up registers/bits with staging tree

2017-03-20 Thread Tom St Denis

Signed-off-by: Tom St Denis 
---
 scripts/parse_bits.sh| 4 +++-
 src/lib/ip/dce60_bits.i  | 1 +
 src/lib/ip/smu712_regs.i | 1 +
 src/lib/ip/smu713_regs.i | 1 +
 4 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/scripts/parse_bits.sh b/scripts/parse_bits.sh
index ebaa6aefb1fa..14df5e831b01 100755
--- a/scripts/parse_bits.sh
+++ b/scripts/parse_bits.sh
@@ -4,7 +4,9 @@
 # ASICs
 
 #this is the path to the tree (not necessarily the one running on your host)
-pk=/nas/work/repos/linux/drivers/gpu/drm/amd/include/asic_reg/
+if [ "$pk" == "" ]; then
+   pk=/nas/work/repos/linux/drivers/gpu/drm/amd/include/asic_reg/
+fi
 
 # parse_bits /path/to/asic_reg/foo/block /path/to/umr/file
 parse_bits() {
diff --git a/src/lib/ip/dce60_bits.i b/src/lib/ip/dce60_bits.i
index 50ae01e400d5..7ced97afed5d 100644
--- a/src/lib/ip/dce60_bits.i
+++ b/src/lib/ip/dce60_bits.i
@@ -2488,6 +2488,7 @@ static struct umr_bitfield mmCC_DC_PIPE_DIS[] = {
 };
 static struct umr_bitfield mmAZALIA_F0_CODEC_ENDPOINT_INDEX[] = {
 { "AZALIA_ENDPOINT_REG_INDEX", 0, 7, &umr_bitfield_default },
+{ "AZALIA_ENDPOINT_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
 };
 static struct umr_bitfield mmAZALIA_F0_CODEC_ENDPOINT_DATA[] = {
 { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
diff --git a/src/lib/ip/smu712_regs.i b/src/lib/ip/smu712_regs.i
index eb030979eaec..f718b000b84b 100644
--- a/src/lib/ip/smu712_regs.i
+++ b/src/lib/ip/smu712_regs.i
@@ -1222,6 +1222,7 @@
{ "ixCG_THERMAL_INT_ENA", REG_SMC, 0xc2100024, 
&ixCG_THERMAL_INT_ENA[0], 
sizeof(ixCG_THERMAL_INT_ENA)/sizeof(ixCG_THERMAL_INT_ENA[0]), 0, 0 },
{ "ixCG_THERMAL_INT_CTRL", REG_SMC, 0xc2100028, 
&ixCG_THERMAL_INT_CTRL[0], 
sizeof(ixCG_THERMAL_INT_CTRL)/sizeof(ixCG_THERMAL_INT_CTRL[0]), 0, 0 },
{ "ixCG_THERMAL_INT_STATUS", REG_SMC, 0xc210002c, 
&ixCG_THERMAL_INT_STATUS[0], 
sizeof(ixCG_THERMAL_INT_STATUS)/sizeof(ixCG_THERMAL_INT_STATUS[0]), 0, 0 },
+   { "ixCURRENT_PG_STATUS_APU", REG_SMC, 0xd020029c, NULL, 0, 0, 0 },
{ "ixSMU_MAIN_PLL_OP_FREQ", REG_SMC, 0xe0003020, 
&ixSMU_MAIN_PLL_OP_FREQ[0], 
sizeof(ixSMU_MAIN_PLL_OP_FREQ)/sizeof(ixSMU_MAIN_PLL_OP_FREQ[0]), 0, 0 },
{ "ixSMU_STATUS", REG_SMC, 0xe0003088, &ixSMU_STATUS[0], 
sizeof(ixSMU_STATUS)/sizeof(ixSMU_STATUS[0]), 0, 0 },
{ "ixSMU_FIRMWARE", REG_SMC, 0xe00030a4, &ixSMU_FIRMWARE[0], 
sizeof(ixSMU_FIRMWARE)/sizeof(ixSMU_FIRMWARE[0]), 0, 0 },
diff --git a/src/lib/ip/smu713_regs.i b/src/lib/ip/smu713_regs.i
index 0f1d79aa2b9f..8a632b41624e 100644
--- a/src/lib/ip/smu713_regs.i
+++ b/src/lib/ip/smu713_regs.i
@@ -1192,6 +1192,7 @@
{ "ixGC_CAC_ACC_CU13", REG_SMC, 0xc7, &ixGC_CAC_ACC_CU13[0], 
sizeof(ixGC_CAC_ACC_CU13)/sizeof(ixGC_CAC_ACC_CU13[0]), 0, 0 },
{ "ixGC_CAC_ACC_CU14", REG_SMC, 0xc8, &ixGC_CAC_ACC_CU14[0], 
sizeof(ixGC_CAC_ACC_CU14)/sizeof(ixGC_CAC_ACC_CU14[0]), 0, 0 },
{ "ixGC_CAC_ACC_CU15", REG_SMC, 0xc9, &ixGC_CAC_ACC_CU15[0], 
sizeof(ixGC_CAC_ACC_CU15)/sizeof(ixGC_CAC_ACC_CU15[0]), 0, 0 },
+   { "ixCURRENT_PG_STATUS_APU", REG_SMC, 0xd020029c, NULL, 0, 0, 0 },
{ "ixSMU_MAIN_PLL_OP_FREQ", REG_SMC, 0xe0003020, 
&ixSMU_MAIN_PLL_OP_FREQ[0], 
sizeof(ixSMU_MAIN_PLL_OP_FREQ)/sizeof(ixSMU_MAIN_PLL_OP_FREQ[0]), 0, 0 },
{ "ixSMU_STATUS", REG_SMC, 0xe0003088, &ixSMU_STATUS[0], 
sizeof(ixSMU_STATUS)/sizeof(ixSMU_STATUS[0]), 0, 0 },
{ "ixSMU_FIRMWARE", REG_SMC, 0xe00030a4, &ixSMU_FIRMWARE[0], 
sizeof(ixSMU_FIRMWARE)/sizeof(ixSMU_FIRMWARE[0]), 0, 0 },
-- 
2.12.0

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Re: [PATCH] drm: add check for plane functions

2017-03-20 Thread Shirish S

On Mon, Mar 20, 2017 at 1:51 PM, Daniel Vetter  wrote:
> On Mon, Mar 20, 2017 at 09:58:01AM +0530, Shirish S wrote:
>> First of all, thanks for your comments/insights.
>>
>> On Sat, Mar 18, 2017 at 12:59 AM, Eric Anholt  wrote:
>> > Ville Syrjälä  writes:
>> >
>> >> On Fri, Mar 17, 2017 at 05:57:52PM +0100, Daniel Vetter wrote:
>> >>> On Fri, Mar 17, 2017 at 01:08:43PM +0200, Ville Syrjälä wrote:
>> >>> > On Fri, Mar 17, 2017 at 03:46:34PM +0530, Shirish S wrote:
>> >>> > > On Fri, Mar 17, 2017 at 3:26 PM, Ville Syrjälä
>> >>> > >  wrote:
>> >>> > > > On Fri, Mar 17, 2017 at 01:25:08PM +0530, Shirish S wrote:
>> >>> > > >> update_plane() and disable_plane() functions
>> >>> > > >> assoiciated with setting plane are called
>> >>> > > >> without any check, causing kernel panic.
>> >>> > > >
>> >>> > > > Why are you registering a plane without the funcs?
>> >>> > > >
>> >>> > > Basically, enabling planes and making them fully functional is
>> >>> > > generally a 2 -step process,
>> >>> > > so i suggest for new drivers wanting to implement/re-design  planes,
>> >>> > > would like to tap
>> >>> > > the flow at enabling(listing caps) and later at ensuring it works.
>> >>> >
>> >>> > I don't think there's much point in exposing something that
>> >>> > doesn't work. And even if you do, you could always just use
>> >>> > stub functions.
>> >>>
>> >>> Yes, just wire up stub functions if you want to enable planes with
>> >>> multi-step patch series.
>> >>>
>> >>> > > I noticed that there is a underlying assumption only for
>> >>> > > plane->(funcs) are implemented, whereas for
>> >>> > > other function for crtc/connector/encoder function calls there is a
>> >>> > > sanity check(or WARN_ON) through out the framework.
>> >>> > >
>> >>> > > I believe this check wont cause any performance/functional impact.
>> >>> > > Please let me know if am missing anything.
>> >>> > > And further more help developers to focus on enabling planes via
>> >>> > > various tests without causing reboots/system hangs.
>> >>> >
>> >>> > I don't particularly like adding more unconditional runtime checks
>> >>> > that just to protect developers from themselves. If you really
>> >>> > think there's value in these, then at least add the checks into
>> >>> > the plane init codepath so that it's a one time cost.
>> >>> >
>> All the plane->funcs are guarded before being called , be it:
>>  late_register()
>>  early_unregister()
>> atomic_destroy_state() etc.,
>> only update/disable_plane() are called without checking their
>> existence, am just extending  the protocol.
>> >>> > The same approach could be used for all the other non-optional
>> >>> > hooks. Otherwise the same WARN_ON()s would have to be sprinkled
>> >>> > all over the place, and there's always the risk of missing a few
>> >>> > codepaths that call a specific hook.
>> >>>
>> >>> I think for these here there's negative value - it allows developers to
>> >>> create completely broken planes. Stub functions really seem like a much
>> >>> better idea.
>> >>
>> >> I was thinking
>> >>
>> >> drm_whatever_init()
>> >> {
>> >>   if (WARN_ON(!funcs->mandatory_thing))
>> >>   return -EINVAL;
>> >> }
>> >>
>> I think since the motive here is to
>> * convey user space that it does not have permissions to
>> update/disable available plane due to implementation issues.
>> * Keeping system alive/usable after non-permitted call.
>> Adding  a WARN_ON() trace showing something is missing at boot/insmod
>> time, wont solve the purpose.
>>
>> This  development phase here could be setting-up infra for adding a
>> plane available on hardware,populate its capabilities
>> and to know how user space reads it and tweak it before moving to
>> configuring registers.
>>
>> To add to what @Eric Anholt mentioned, without this patch developer
>> comes to know about
>> the mandatory functions required in a real tough way of panic and
>> system freezes,
>> just because the core framework invokes a NULL function pointer
>> without checking.
>> (Am re-stressing here, that only update/disable planes are exceptions
>> rest all have required checks.)
>
> Eric acked Ville's idea, not your patch.
>>
>> >> rather than putting the WARN_ON()s around each call of
>> >> funcs->mandatory_thing().
>> >>
>> There are similar checks around every
>> "[crtc/encoder]->funcs->[hooked_up_function specific to vendor]",
>> including  plane functions called in drm_plane.c & other places like:
>>  drivers/gpu/drm/drm_crtc_helper.c:1074: if
>> (plane->funcs->atomic_duplicate_state)
>>  drivers/gpu/drm/drm_mode_config.c:176:  if (plane->funcs->reset)
>>  drivers/gpu/drm/drm_plane.c:162:if
>> (plane->funcs->late_register)
>>  drivers/gpu/drm/drm_plane.c:242:if (plane->state &&
>> plane->funcs->atomic_destroy_state)
>> and so on...
>> For consistency sake lets have this check.
>
> Those are different functions. They are in transitional helpers, where

Re: [rfc/repost] amdgpu/sync_file shared semaphores

2017-03-20 Thread Daniel Vetter

On Mon, Mar 20, 2017 at 05:03:03PM +1000, Dave Airlie wrote:
> This is a repost of the file_sync semaphore support.
> 
> The main difference in this patch is patch1 does a lot
> better at handling NULL fences in some places. The poll code
> and ioctls should handle ending up with fence being NULL properly now.

btw on this I realized that sync_file_get_fence can already return NULL,
so no problem really and no need for a dummy fence. Silly me :-)
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 1/4] sync_file: add a mutex to protect fence and callback members. (v3)

2017-03-20 Thread Daniel Vetter

On Mon, Mar 20, 2017 at 08:16:36AM +, Chris Wilson wrote:
> On Mon, Mar 20, 2017 at 05:03:04PM +1000, Dave Airlie wrote:
> > From: Dave Airlie 
> > 
> > This patch allows the underlying fence in a sync_file to be changed
> > or set to NULL. This isn't currently required but for Vulkan
> > semaphores we need to be able to swap and reset the fence.
> > 
> > In order to faciliate this, it uses rcu to protect the fence,
> > along with a new mutex. The mutex also protects the callback.
> > It also checks for NULL when retrieving the rcu protected
> > fence in case it has been reset.
> > 
> > v1.1: fix the locking (Julia Lawall).
> > v2: use rcu try one
> > v3: fix poll to use proper rcu, fixup merge/fill ioctls
> > to not crash on NULL fence cases.
> > 
> > Signed-off-by: Dave Airlie 
> > ---
> > @@ -80,7 +87,9 @@ struct sync_file *sync_file_create(struct dma_fence 
> > *fence)
> > if (!sync_file)
> > return NULL;
> >  
> > -   sync_file->fence = dma_fence_get(fence);
> > +   dma_fence_get(fence);
> > +
> > +   RCU_INIT_POINTER(sync_file->fence, fence);
> >  
> > snprintf(sync_file->name, sizeof(sync_file->name), "%s-%s%llu-%d",
> >  fence->ops->get_driver_name(fence),
> > @@ -124,13 +133,26 @@ struct dma_fence *sync_file_get_fence(int fd)
> > if (!sync_file)
> > return NULL;
> >  
> > -   fence = dma_fence_get(sync_file->fence);
> > +   if (!rcu_access_pointer(sync_file->fence))
> > +   return NULL;
> 
> Missed fput.
> 
> > +
> > +   rcu_read_lock();
> > +   fence = dma_fence_get_rcu_safe(&sync_file->fence);
> > +   rcu_read_unlock();
> > +
> > fput(sync_file->file);
> >  
> > return fence;
> >  }
> >  EXPORT_SYMBOL(sync_file_get_fence);
> >  
> > @@ -204,10 +234,16 @@ static struct sync_file *sync_file_merge(const char 
> > *name, struct sync_file *a,
> > if (!sync_file)
> > return NULL;
> >  
> > +   mutex_lock(&a->lock);
> > +   mutex_lock(&b->lock);
> 
> This allows userspace to trigger lockdep (just merge the same pair of
> sync_files again in opposite order). if (b < a) swap(a, b); ?

Do we even need the look? 1) rcu-lookup the fences (which are invariant)
2) merge them 3) create new syncfile for them. I don't see a need for
taking locks here.

> 
> > a_fences = get_fences(a, &a_num_fences);
> > b_fences = get_fences(b, &b_num_fences);
> > -   if (a_num_fences > INT_MAX - b_num_fences)
> > -   return NULL;
> > +   if (!a_num_fences || !b_num_fences)
> > +   goto unlock;
> > +
> > +   if (a_num_fences > INT_MAX - b_num_fences) {
> > +   goto unlock;
> > +   }
> >  
> > num_fences = a_num_fences + b_num_fences;
> >  
> > @@ -281,10 +323,15 @@ static void sync_file_free(struct kref *kref)
> >  {
> > struct sync_file *sync_file = container_of(kref, struct sync_file,
> >  kref);
> > +   struct dma_fence *fence;
> > +
> 
> Somewhere, here?, it would be useful to add a comment that the rcu
> delayed free is provided by fput.
> 
> > +   fence = rcu_dereference_protected(sync_file->fence, 1);
> > +   if (fence) {
> > +   if (test_bit(POLL_ENABLED, &fence->flags))
> > +   dma_fence_remove_callback(fence, &sync_file->cb);
> > +   dma_fence_put(fence);
> > +   }
> >  
> > -   if (test_bit(POLL_ENABLED, &sync_file->fence->flags))
> > -   dma_fence_remove_callback(sync_file->fence, &sync_file->cb);
> > -   dma_fence_put(sync_file->fence);
> > kfree(sync_file);
> >  }
> >  
> > @@ -299,16 +346,25 @@ static int sync_file_release(struct inode *inode, 
> > struct file *file)
> >  static unsigned int sync_file_poll(struct file *file, poll_table *wait)
> >  {
> > struct sync_file *sync_file = file->private_data;
> > +   unsigned int ret_val = 0;
> > +   struct dma_fence *fence;
> >  
> > poll_wait(file, &sync_file->wq, wait);
> >  
> > -   if (!test_and_set_bit(POLL_ENABLED, &sync_file->fence->flags)) {
> > -   if (dma_fence_add_callback(sync_file->fence, &sync_file->cb,
> > -  fence_check_cb_func) < 0)
> > -   wake_up_all(&sync_file->wq);
> > +   mutex_lock(&sync_file->lock);
> > +
> > +   fence = sync_file_get_fence_locked(sync_file);
> 
> Why do you need the locked version here and not just the rcu variant?

+1 :-) I think the lock should only be needed when you update the fence,
everywhere else we should be able to get away with rcu.

> > +   if (fence) {
> > +   if (!test_and_set_bit(POLL_ENABLED, &fence->flags)) {
> > +   if (dma_fence_add_callback(fence, &sync_file->cb,
> > +  fence_check_cb_func) < 0)
> > +   wake_up_all(&sync_file->wq);
> > +   }
> > +   ret_val = dma_fence_is_signaled(fence) ? POLLIN : 0;
> > }
> > +   mutex_unlock(&sync_file->lock);
> 
> So an empty sync_file is incomplete and blocks forever? Why? It's the
>

Re: [PATCH 1/4] sync_file: add a mutex to protect fence and callback members. (v3)

2017-03-20 Thread Chris Wilson

On Mon, Mar 20, 2017 at 05:03:04PM +1000, Dave Airlie wrote:
> From: Dave Airlie 
> 
> This patch allows the underlying fence in a sync_file to be changed
> or set to NULL. This isn't currently required but for Vulkan
> semaphores we need to be able to swap and reset the fence.
> 
> In order to faciliate this, it uses rcu to protect the fence,
> along with a new mutex. The mutex also protects the callback.
> It also checks for NULL when retrieving the rcu protected
> fence in case it has been reset.
> 
> v1.1: fix the locking (Julia Lawall).
> v2: use rcu try one
> v3: fix poll to use proper rcu, fixup merge/fill ioctls
> to not crash on NULL fence cases.
> 
> Signed-off-by: Dave Airlie 
> ---
> @@ -124,13 +133,26 @@ struct dma_fence *sync_file_get_fence(int fd)
>   if (!sync_file)
>   return NULL;
>  
> - fence = dma_fence_get(sync_file->fence);
> + if (!rcu_access_pointer(sync_file->fence))
> + return NULL;
> +
> + rcu_read_lock();
> + fence = dma_fence_get_rcu_safe(&sync_file->fence);
> + rcu_read_unlock();
> +
>   fput(sync_file->file);

So poll will wait until the fence is set before the sync_file is
signaled, but here we return NULL. At the moment this is interpretted by
the callers as an error (since we can't distinguish between the lookup
error and the empty sync_file). However, if it is empty we also want to
delay the dependent execution until the fence is set to match the poll
semantics.
-Chris

-- 
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Re: [PATCH] drm: add check for plane functions

2017-03-20 Thread Daniel Vetter

On Mon, Mar 20, 2017 at 09:58:01AM +0530, Shirish S wrote:
> First of all, thanks for your comments/insights.
> 
> On Sat, Mar 18, 2017 at 12:59 AM, Eric Anholt  wrote:
> > Ville Syrjälä  writes:
> >
> >> On Fri, Mar 17, 2017 at 05:57:52PM +0100, Daniel Vetter wrote:
> >>> On Fri, Mar 17, 2017 at 01:08:43PM +0200, Ville Syrjälä wrote:
> >>> > On Fri, Mar 17, 2017 at 03:46:34PM +0530, Shirish S wrote:
> >>> > > On Fri, Mar 17, 2017 at 3:26 PM, Ville Syrjälä
> >>> > >  wrote:
> >>> > > > On Fri, Mar 17, 2017 at 01:25:08PM +0530, Shirish S wrote:
> >>> > > >> update_plane() and disable_plane() functions
> >>> > > >> assoiciated with setting plane are called
> >>> > > >> without any check, causing kernel panic.
> >>> > > >
> >>> > > > Why are you registering a plane without the funcs?
> >>> > > >
> >>> > > Basically, enabling planes and making them fully functional is
> >>> > > generally a 2 -step process,
> >>> > > so i suggest for new drivers wanting to implement/re-design  planes,
> >>> > > would like to tap
> >>> > > the flow at enabling(listing caps) and later at ensuring it works.
> >>> >
> >>> > I don't think there's much point in exposing something that
> >>> > doesn't work. And even if you do, you could always just use
> >>> > stub functions.
> >>>
> >>> Yes, just wire up stub functions if you want to enable planes with
> >>> multi-step patch series.
> >>>
> >>> > > I noticed that there is a underlying assumption only for
> >>> > > plane->(funcs) are implemented, whereas for
> >>> > > other function for crtc/connector/encoder function calls there is a
> >>> > > sanity check(or WARN_ON) through out the framework.
> >>> > >
> >>> > > I believe this check wont cause any performance/functional impact.
> >>> > > Please let me know if am missing anything.
> >>> > > And further more help developers to focus on enabling planes via
> >>> > > various tests without causing reboots/system hangs.
> >>> >
> >>> > I don't particularly like adding more unconditional runtime checks
> >>> > that just to protect developers from themselves. If you really
> >>> > think there's value in these, then at least add the checks into
> >>> > the plane init codepath so that it's a one time cost.
> >>> >
> All the plane->funcs are guarded before being called , be it:
>  late_register()
>  early_unregister()
> atomic_destroy_state() etc.,
> only update/disable_plane() are called without checking their
> existence, am just extending  the protocol.
> >>> > The same approach could be used for all the other non-optional
> >>> > hooks. Otherwise the same WARN_ON()s would have to be sprinkled
> >>> > all over the place, and there's always the risk of missing a few
> >>> > codepaths that call a specific hook.
> >>>
> >>> I think for these here there's negative value - it allows developers to
> >>> create completely broken planes. Stub functions really seem like a much
> >>> better idea.
> >>
> >> I was thinking
> >>
> >> drm_whatever_init()
> >> {
> >>   if (WARN_ON(!funcs->mandatory_thing))
> >>   return -EINVAL;
> >> }
> >>
> I think since the motive here is to
> * convey user space that it does not have permissions to
> update/disable available plane due to implementation issues.
> * Keeping system alive/usable after non-permitted call.
> Adding  a WARN_ON() trace showing something is missing at boot/insmod
> time, wont solve the purpose.
> 
> This  development phase here could be setting-up infra for adding a
> plane available on hardware,populate its capabilities
> and to know how user space reads it and tweak it before moving to
> configuring registers.
> 
> To add to what @Eric Anholt mentioned, without this patch developer
> comes to know about
> the mandatory functions required in a real tough way of panic and
> system freezes,
> just because the core framework invokes a NULL function pointer
> without checking.
> (Am re-stressing here, that only update/disable planes are exceptions
> rest all have required checks.)

Eric acked Ville's idea, not your patch.
> 
> >> rather than putting the WARN_ON()s around each call of
> >> funcs->mandatory_thing().
> >>
> There are similar checks around every
> "[crtc/encoder]->funcs->[hooked_up_function specific to vendor]",
> including  plane functions called in drm_plane.c & other places like:
>  drivers/gpu/drm/drm_crtc_helper.c:1074: if
> (plane->funcs->atomic_duplicate_state)
>  drivers/gpu/drm/drm_mode_config.c:176:  if (plane->funcs->reset)
>  drivers/gpu/drm/drm_plane.c:162:if
> (plane->funcs->late_register)
>  drivers/gpu/drm/drm_plane.c:242:if (plane->state &&
> plane->funcs->atomic_destroy_state)
> and so on...
> For consistency sake lets have this check.

Those are different functions. They are in transitional helpers, where
we explicitly assume not all the atomic bits are ready yet.

Different use-case, different semantics.

> >> That will fail gracefully (which I guess is what people

Re: [PATCH 1/4] sync_file: add a mutex to protect fence and callback members. (v3)

2017-03-20 Thread Chris Wilson

On Mon, Mar 20, 2017 at 05:03:04PM +1000, Dave Airlie wrote:
> From: Dave Airlie 
> 
> This patch allows the underlying fence in a sync_file to be changed
> or set to NULL. This isn't currently required but for Vulkan
> semaphores we need to be able to swap and reset the fence.
> 
> In order to faciliate this, it uses rcu to protect the fence,
> along with a new mutex. The mutex also protects the callback.
> It also checks for NULL when retrieving the rcu protected
> fence in case it has been reset.
> 
> v1.1: fix the locking (Julia Lawall).
> v2: use rcu try one
> v3: fix poll to use proper rcu, fixup merge/fill ioctls
> to not crash on NULL fence cases.
> 
> Signed-off-by: Dave Airlie 
> ---
> @@ -80,7 +87,9 @@ struct sync_file *sync_file_create(struct dma_fence *fence)
>   if (!sync_file)
>   return NULL;
>  
> - sync_file->fence = dma_fence_get(fence);
> + dma_fence_get(fence);
> +
> + RCU_INIT_POINTER(sync_file->fence, fence);
>  
>   snprintf(sync_file->name, sizeof(sync_file->name), "%s-%s%llu-%d",
>fence->ops->get_driver_name(fence),
> @@ -124,13 +133,26 @@ struct dma_fence *sync_file_get_fence(int fd)
>   if (!sync_file)
>   return NULL;
>  
> - fence = dma_fence_get(sync_file->fence);
> + if (!rcu_access_pointer(sync_file->fence))
> + return NULL;

Missed fput.

> +
> + rcu_read_lock();
> + fence = dma_fence_get_rcu_safe(&sync_file->fence);
> + rcu_read_unlock();
> +
>   fput(sync_file->file);
>  
>   return fence;
>  }
>  EXPORT_SYMBOL(sync_file_get_fence);
>  
> @@ -204,10 +234,16 @@ static struct sync_file *sync_file_merge(const char 
> *name, struct sync_file *a,
>   if (!sync_file)
>   return NULL;
>  
> + mutex_lock(&a->lock);
> + mutex_lock(&b->lock);

This allows userspace to trigger lockdep (just merge the same pair of
sync_files again in opposite order). if (b < a) swap(a, b); ?

>   a_fences = get_fences(a, &a_num_fences);
>   b_fences = get_fences(b, &b_num_fences);
> - if (a_num_fences > INT_MAX - b_num_fences)
> - return NULL;
> + if (!a_num_fences || !b_num_fences)
> + goto unlock;
> +
> + if (a_num_fences > INT_MAX - b_num_fences) {
> + goto unlock;
> + }
>  
>   num_fences = a_num_fences + b_num_fences;
>  
> @@ -281,10 +323,15 @@ static void sync_file_free(struct kref *kref)
>  {
>   struct sync_file *sync_file = container_of(kref, struct sync_file,
>kref);
> + struct dma_fence *fence;
> +

Somewhere, here?, it would be useful to add a comment that the rcu
delayed free is provided by fput.

> + fence = rcu_dereference_protected(sync_file->fence, 1);
> + if (fence) {
> + if (test_bit(POLL_ENABLED, &fence->flags))
> + dma_fence_remove_callback(fence, &sync_file->cb);
> + dma_fence_put(fence);
> + }
>  
> - if (test_bit(POLL_ENABLED, &sync_file->fence->flags))
> - dma_fence_remove_callback(sync_file->fence, &sync_file->cb);
> - dma_fence_put(sync_file->fence);
>   kfree(sync_file);
>  }
>  
> @@ -299,16 +346,25 @@ static int sync_file_release(struct inode *inode, 
> struct file *file)
>  static unsigned int sync_file_poll(struct file *file, poll_table *wait)
>  {
>   struct sync_file *sync_file = file->private_data;
> + unsigned int ret_val = 0;
> + struct dma_fence *fence;
>  
>   poll_wait(file, &sync_file->wq, wait);
>  
> - if (!test_and_set_bit(POLL_ENABLED, &sync_file->fence->flags)) {
> - if (dma_fence_add_callback(sync_file->fence, &sync_file->cb,
> -fence_check_cb_func) < 0)
> - wake_up_all(&sync_file->wq);
> + mutex_lock(&sync_file->lock);
> +
> + fence = sync_file_get_fence_locked(sync_file);

Why do you need the locked version here and not just the rcu variant?

> + if (fence) {
> + if (!test_and_set_bit(POLL_ENABLED, &fence->flags)) {
> + if (dma_fence_add_callback(fence, &sync_file->cb,
> +fence_check_cb_func) < 0)
> + wake_up_all(&sync_file->wq);
> + }
> + ret_val = dma_fence_is_signaled(fence) ? POLLIN : 0;
>   }
> + mutex_unlock(&sync_file->lock);

So an empty sync_file is incomplete and blocks forever? Why? It's the
opposite behaviour to e.g. reservation_object so a quick explanation of
how that is used by VkSemaphore will cement the differences.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[PATCH 3/4] amdgpu/cs: split out fence dependency checking

2017-03-20 Thread Dave Airlie

From: Dave Airlie 

This just splits out the fence depenency checking into it's
own function to make it easier to add semaphore dependencies.

Signed-off-by: Dave Airlie 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 86 +++---
 1 file changed, 48 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 99424cb..4671432 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -963,56 +963,66 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
return 0;
 }
 
-static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
- struct amdgpu_cs_parser *p)
+static int amdgpu_process_fence_dep(struct amdgpu_device *adev,
+   struct amdgpu_cs_parser *p,
+   struct amdgpu_cs_chunk *chunk)
 {
struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
-   int i, j, r;
-
-   for (i = 0; i < p->nchunks; ++i) {
-   struct drm_amdgpu_cs_chunk_dep *deps;
-   struct amdgpu_cs_chunk *chunk;
-   unsigned num_deps;
+   unsigned num_deps;
+   int i, r;
+   struct drm_amdgpu_cs_chunk_dep *deps;
 
-   chunk = &p->chunks[i];
+   deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
+   num_deps = chunk->length_dw * 4 /
+   sizeof(struct drm_amdgpu_cs_chunk_dep);
 
-   if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
-   continue;
+   for (i = 0; i < num_deps; ++i) {
+   struct amdgpu_ring *ring;
+   struct amdgpu_ctx *ctx;
+   struct dma_fence *fence;
 
-   deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
-   num_deps = chunk->length_dw * 4 /
-   sizeof(struct drm_amdgpu_cs_chunk_dep);
+   r = amdgpu_cs_get_ring(adev, deps[i].ip_type,
+  deps[i].ip_instance,
+  deps[i].ring, &ring);
+   if (r)
+   return r;
 
-   for (j = 0; j < num_deps; ++j) {
-   struct amdgpu_ring *ring;
-   struct amdgpu_ctx *ctx;
-   struct dma_fence *fence;
+   ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
+   if (ctx == NULL)
+   return -EINVAL;
 
-   r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
-  deps[j].ip_instance,
-  deps[j].ring, &ring);
+   fence = amdgpu_ctx_get_fence(ctx, ring,
+deps[i].handle);
+   if (IS_ERR(fence)) {
+   r = PTR_ERR(fence);
+   amdgpu_ctx_put(ctx);
+   return r;
+   } else if (fence) {
+   r = amdgpu_sync_fence(adev, &p->job->sync,
+ fence);
+   dma_fence_put(fence);
+   amdgpu_ctx_put(ctx);
if (r)
return r;
+   }
+   }
+   return 0;
+}
 
-   ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
-   if (ctx == NULL)
-   return -EINVAL;
+static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
+ struct amdgpu_cs_parser *p)
+{
+   int i, r;
 
-   fence = amdgpu_ctx_get_fence(ctx, ring,
-deps[j].handle);
-   if (IS_ERR(fence)) {
-   r = PTR_ERR(fence);
-   amdgpu_ctx_put(ctx);
-   return r;
+   for (i = 0; i < p->nchunks; ++i) {
+   struct amdgpu_cs_chunk *chunk;
 
-   } else if (fence) {
-   r = amdgpu_sync_fence(adev, &p->job->sync,
- fence);
-   dma_fence_put(fence);
-   amdgpu_ctx_put(ctx);
-   if (r)
-   return r;
-   }
+   chunk = &p->chunks[i];
+
+   if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
+   r = amdgpu_process_fence_dep(adev, p, chunk);
+   if (r)
+   return r;
}
}
 
-- 
2.7.4

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