Re: [PATCH 2/4] drm/amdgpu: return -ENODEV to user space when vram is lost v2

[zhoucm1]

On 2017年05月23日 23:16, Christian König wrote:

Am 23.05.2017 um 17:08 schrieb Deucher, Alexander:

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Chunming Zhou
Sent: Tuesday, May 16, 2017 5:26 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou, David(ChunMing)
Subject: [PATCH 2/4] drm/amdgpu: return -ENODEV to user space when
vram is lost v2

below ioctl will return -ENODEV:
amdgpu_cs_ioctl
amdgpu_cs_wait_ioctl
amdgpu_cs_wait_fences_ioctl
amdgpu_gem_va_ioctl
amdgpu_info_ioctl
Do we want to block the info ioctl?  Isn't that where the lost 
context query is?


No, that's amdgpu_ctx_ioctl.

But I think the conclusion is that we want to move the vram_lost 
counter to be per CTX and not per device.

Yes, Monk is working on it for virt case, after it, I think we can reuse it.

Regards,
David zhou


Christian.



Alex


v2: only for map and replace cases in amdgpu_gem_va_ioctl

Change-Id: I8970cde3301b7cfeb4263cc0f0e54aece215c98e
Signed-off-by: Chunming Zhou 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  4 
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |  9 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  4 +++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c|  5 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 10 ++
  5 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f9da215..dcd6203 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -855,6 +855,7 @@ struct amdgpu_fpriv {
  struct amdgpu_ctx_mgrctx_mgr;
  spinlock_tsem_handles_lock;
  struct idrsem_handles;
+u32vram_lost_counter;
  };

  /*
@@ -1607,6 +1608,7 @@ struct amdgpu_device {
  atomic64_tnum_bytes_moved;
  atomic64_tnum_evictions;
  atomic_tgpu_reset_counter;
+atomic_tvram_lost_counter;

  /* data for buffer migration throttling */
  struct {
@@ -2005,6 +2007,8 @@ static inline void
amdgpu_unregister_atpx_handler(void) {}
  extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
  extern const int amdgpu_max_kms_ioctl;

+bool amdgpu_kms_vram_lost(struct amdgpu_device *adev,
+  struct amdgpu_fpriv *fpriv);
  int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long 
flags);

  int amdgpu_driver_unload_kms(struct drm_device *dev);
  void amdgpu_driver_lastclose_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index b803412..911aa02 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1097,6 +1097,7 @@ static int amdgpu_cs_submit(struct
amdgpu_cs_parser *p,
  int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct 
drm_file

*filp)
  {
  struct amdgpu_device *adev = dev->dev_private;
+struct amdgpu_fpriv *fpriv = filp->driver_priv;
  union drm_amdgpu_cs *cs = data;
  struct amdgpu_cs_parser parser = {};
  bool reserved_buffers = false;
@@ -1104,6 +1105,8 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void
*data, struct drm_file *filp)

  if (!adev->accel_working)
  return -EBUSY;
+if (amdgpu_kms_vram_lost(adev, fpriv))
+return -ENODEV;

  parser.adev = adev;
  parser.filp = filp;
@@ -1165,12 +1168,15 @@ int amdgpu_cs_wait_ioctl(struct drm_device
*dev, void *data,
  {
  union drm_amdgpu_wait_cs *wait = data;
  struct amdgpu_device *adev = dev->dev_private;
+struct amdgpu_fpriv *fpriv = filp->driver_priv;
  unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
  struct amdgpu_ring *ring = NULL;
  struct amdgpu_ctx *ctx;
  struct fence *fence;
  long r;

+if (amdgpu_kms_vram_lost(adev, fpriv))
+return -ENODEV;
  r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait-

in.ip_instance,

 wait->in.ring, &ring);
  if (r)
@@ -1344,12 +1350,15 @@ int amdgpu_cs_wait_fences_ioctl(struct
drm_device *dev, void *data,
  struct drm_file *filp)
  {
  struct amdgpu_device *adev = dev->dev_private;
+struct amdgpu_fpriv *fpriv = filp->driver_priv;
  union drm_amdgpu_wait_fences *wait = data;
  uint32_t fence_count = wait->in.fence_count;
  struct drm_amdgpu_fence *fences_user;
  struct drm_amdgpu_fence *fences;
  int r;

+if (amdgpu_kms_vram_lost(adev, fpriv))
+return -ENODEV;
  /* Get the fences from userspace */
  fences = kmalloc_array(fence_count, sizeof(struct
drm_amdgpu_fence),
  GFP_KERNEL);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c56ae4a..2f0fcf8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2913,8 +2913,10 @@ int amdgpu_gpu_reset(struct amdgpu_device
*adev)
   

[PATCH xf86-video-amdgpu 1/1] Update URLs

[Michel Dänzer]

From: Michel Dänzer 

* Point to the amd-gfx mailing list
* Specify the component in all bugzilla URLs
* Use https:// for all HTML URLs

(Ported from radeon commit d80d01a73c2eaba2e3649b7bc0a3541b3ff782f6)

Signed-off-by: Michel Dänzer 
---
 README | 14 +++---
 configure.ac   |  2 +-
 man/amdgpu.man |  6 +++---
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/README b/README
index 98deab952..1a74a1281 100644
--- a/README
+++ b/README
@@ -1,25 +1,25 @@
 xf86-video-amdgpu - AMD Radeon video driver for the Xorg X server
 
-All questions regarding this software should be directed at the
-Xorg mailing list:
+Patches and questions regarding this software should be directed at the
+amd-gfx mailing list:
 
-http://lists.freedesktop.org/mailman/listinfo/xorg
+https://lists.freedesktop.org/mailman/listinfo/amd-gfx
 
 Please submit bug reports to the Xorg bugzilla:
 
-https://bugs.freedesktop.org/enter_bug.cgi?product=xorg
+
https://bugs.freedesktop.org/enter_bug.cgi?product=xorg&component=Driver/AMDgpu
 
 The master development code repository can be found at:
 
 git://anongit.freedesktop.org/git/xorg/driver/xf86-video-amdgpu
 
-http://cgit.freedesktop.org/xorg/driver/xf86-video-amdgpu
+https://cgit.freedesktop.org/xorg/driver/xf86-video-amdgpu
 
 For patch submission instructions, see:
 
-   http://www.x.org/wiki/Development/Documentation/SubmittingPatches
+https://www.x.org/wiki/Development/Documentation/SubmittingPatches
 
 For more information on the git code manager, see:
 
-http://wiki.x.org/wiki/GitPage
+https://wiki.x.org/wiki/GitPage
 
diff --git a/configure.ac b/configure.ac
index 9110f3545..26eb52ddc 100644
--- a/configure.ac
+++ b/configure.ac
@@ -24,7 +24,7 @@
 AC_PREREQ([2.60])
 AC_INIT([xf86-video-amdgpu],
 [1.3.99],
-[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
+
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg&component=Driver/AMDgpu],
 [xf86-video-amdgpu])
 
 AC_CONFIG_SRCDIR([Makefile.am])
diff --git a/man/amdgpu.man b/man/amdgpu.man
index 13ffb7a27..d6904b818 100644
--- a/man/amdgpu.man
+++ b/man/amdgpu.man
@@ -115,17 +115,17 @@ __xservername__(__appmansuffix__), 
__xconfigfile__(__filemansuffix__), Xserver(_
 .IP " 1." 4
 Wiki page:
 .RS 4
-http://www.x.org/wiki/radeon
+https://www.x.org/wiki/radeon
 .RE
 .IP " 2." 4
 Overview about amdgpu development code:
 .RS 4
-http://cgit.freedesktop.org/xorg/driver/xf86-video-amdgpu/
+https://cgit.freedesktop.org/xorg/driver/xf86-video-amdgpu/
 .RE
 .IP " 3." 4
 Mailing list:
 .RS 4
-http://lists.freedesktop.org/mailman/listinfo/amd-gfx
+https://lists.freedesktop.org/mailman/listinfo/amd-gfx
 .RE
 .IP " 4." 4
 IRC channel:
-- 
2.11.0

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Re: [PATCH] drm/amd/display: Limit DCN to x86 arch

[Michel Dänzer]

On 23/05/17 10:37 PM, Harry Wentland wrote:
> On 2017-05-20 04:13 AM, Christian König wrote:
>> Am 19.05.2017 um 22:28 schrieb Harry Wentland:
>>> 
>>> I realize this is raising a lot of concern. I was concerned myself
>>> when I first saw this. Beside calling kernel_fpu_begin() and
>>> kernel_fpu_end() are there other things to watch out for?
>>
>> Yeah, especially setting "-msse" is rather questionable. As far as I
>> know on 64bit systems it is the default, but on 32bit systems that
>> could silently break some assumptions.
>>
>> Additional to that as far as I know "-msse" is just for optimization
>> and that isn't performance critical code, so why exactly do we need it?
> 
> Once we enable multi-plane code this code becomes performance critical
> as I believe it gets executed when resizing an underlay surface, such as
> a video player.

That should still only happen once per frame though, i.e. on the order
of 10s to 100s of times per second.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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RE: [PATCH 0/5] GFX9 KIQ

[Liu, Shaoyun]

I don't have any test for KCQ ,  but KFD use the  KIQ to invalidate_tlbs ,  I 
try to add some print message in the code to prove  it go through the new code 
path , but seems I don't  see any messages I added. I tried pr_info , pr_err 
and  printk , DRM_ERROR and  nothing  works , anything changed in amdgpu side 
to prevent the  message print ? 
 
Regards
shaoyun.liu

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Alex 
Deucher
Sent: Tuesday, May 23, 2017 5:31 PM
To: StDenis, Tom
Cc: amd-gfx list
Subject: Re: [PATCH 0/5] GFX9 KIQ

On Fri, May 12, 2017 at 7:11 AM, Tom St Denis  wrote:
> On 11/05/17 07:33 PM, Tom St Denis wrote:
>>
>> On 11/05/17 02:35 PM, Alex Deucher wrote:
>>>
>>> These are the laste of the gfx9 KIQ patches that haven't landed yet.  
>>> Can someone with gfx9 capable hw test this (vega10 or raven)?  This 
>>> is needed to enable powergating on gfx9.
>>>
>>> Thanks,
>>
>>
>> If nobody gets to it by morning I'll try it out first thing on my 
>> vega10 though my VBIOS might need updating...
>
>
>
> They don't apply on top of either 4.9 nor 4.11...

Odd.  They applied for me (at least to the 4.11 tree I had checked out when I 
left town).  Attached again just in case.

Alex

>
>
> Tom
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RE: [PATCH] drm/amd/amdgpu: Return error if initiating read out of range on vram

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Tuesday, May 23, 2017 11:59 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH] drm/amd/amdgpu: Return error if initiating read out of
> range on vram
> 
> If you initiate a read that is out of the VRAM address space return
> ENXIO instead of 0.
> 
> Reads that begin below that point will read upto the VRAM limit as
> before.
> 
> Signed-off-by: Tom St Denis 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 522f773203c8..399209495265 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1468,6 +1468,9 @@ static ssize_t amdgpu_ttm_vram_read(struct file
> *f, char __user *buf,
>   if (size & 0x3 || *pos & 0x3)
>   return -EINVAL;
> 
> + if (*pos >= adev->mc.mc_vram_size)
> + return -ENXIO;
> +
>   while (size) {
>   unsigned long flags;
>   uint32_t value;
> --
> 2.12.0
> 
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Re: [PATCH 0/5] GFX9 KIQ

[Alex Deucher]

On Tue, May 23, 2017 at 5:31 PM, Alex Deucher  wrote:
> On Fri, May 12, 2017 at 7:11 AM, Tom St Denis  wrote:
>> On 11/05/17 07:33 PM, Tom St Denis wrote:
>>>
>>> On 11/05/17 02:35 PM, Alex Deucher wrote:

 These are the laste of the gfx9 KIQ patches that haven't landed yet.  Can
 someone with gfx9 capable hw test this (vega10 or raven)?  This is needed
 to enable powergating on gfx9.

 Thanks,
>>>
>>>
>>> If nobody gets to it by morning I'll try it out first thing on my vega10
>>> though my VBIOS might need updating...
>>
>>
>>
>> They don't apply on top of either 4.9 nor 4.11...
>
> Odd.  They applied for me (at least to the 4.11 tree I had checked out
> when I left town).  Attached again just in case.
>
> Alex
>
>>
>>
>> Tom
>> ___
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
From c053a709b9fcf8e3a2f99807e15d84c504a044e3 Mon Sep 17 00:00:00 2001
From: Alex Deucher 
Date: Mon, 17 Apr 2017 17:24:47 -0400
Subject: [PATCH 4/5] drm/amdgpu/gfx9: fix resume of KIQ and KCQs (v2)

No need to reset the wptr and clear the rings.  The UNMAP_QUEUES
packet writes the current MQD state back the MQD on suspend,
so there is no need to reset it as well.

v2: fix from gfx8 (Rex)

Ack-by: monk liu 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 28 +++-
 1 file changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 9051590..42390c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2797,18 +2797,7 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
 
 	gfx_v9_0_kiq_setting(ring);
 
-	if (!adev->gfx.in_reset) {
-		memset((void *)mqd, 0, sizeof(*mqd));
-		mutex_lock(&adev->srbm_mutex);
-		soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
-		gfx_v9_0_mqd_init(ring);
-		gfx_v9_0_kiq_init_register(ring);
-		soc15_grbm_select(adev, 0, 0, 0, 0);
-		mutex_unlock(&adev->srbm_mutex);
-
-		if (adev->gfx.mec.mqd_backup[mqd_idx])
-			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
-	} else { /* for GPU_RESET case */
+	if (adev->gfx.in_reset) { /* for GPU_RESET case */
 		/* reset MQD to a clean status */
 		if (adev->gfx.mec.mqd_backup[mqd_idx])
 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
@@ -2822,6 +2811,17 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
 		gfx_v9_0_kiq_init_register(ring);
 		soc15_grbm_select(adev, 0, 0, 0, 0);
 		mutex_unlock(&adev->srbm_mutex);
+	} else {
+		memset((void *)mqd, 0, sizeof(*mqd));
+		mutex_lock(&adev->srbm_mutex);
+		soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
+		gfx_v9_0_mqd_init(ring);
+		gfx_v9_0_kiq_init_register(ring);
+		soc15_grbm_select(adev, 0, 0, 0, 0);
+		mutex_unlock(&adev->srbm_mutex);
+
+		if (adev->gfx.mec.mqd_backup[mqd_idx])
+			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
 	}
 
 	return 0;
@@ -2843,7 +2843,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
 
 		if (adev->gfx.mec.mqd_backup[mqd_idx])
 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
-	} else { /* for GPU_RESET case */
+	} else if (adev->gfx.in_reset) { /* for GPU_RESET case */
 		/* reset MQD to a clean status */
 		if (adev->gfx.mec.mqd_backup[mqd_idx])
 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
@@ -2851,6 +2851,8 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
 		/* reset ring buffer */
 		ring->wptr = 0;
 		amdgpu_ring_clear_ring(ring);
+	} else {
+		amdgpu_ring_clear_ring(ring);
 	}
 
 	return 0;
-- 
2.5.5

From 81da96f2dfb733480ee6cb5146d9e9d7c08e45ed Mon Sep 17 00:00:00 2001
From: Alex Deucher 
Date: Mon, 17 Apr 2017 17:10:11 -0400
Subject: [PATCH 3/5] drm/amdgpu/gfx9: move SET_RESOURCES into the same command
 stream

As the KCQ setup.  This way we only have to wait once for the
entire MEC.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 73 +++
 1 file changed, 14 insertions(+), 59 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 7be71fb..9051590 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2478,59 +2478,7 @@ static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
 	WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
 }
 
-static int gfx_v9_0_kiq_enable(struct amdgpu_ring *ring)
-{
-	struct amdgpu_device *adev = ring->adev;
-	uint32_t scratch, tmp = 0;
-	int r, i;
-
-	r = amdgpu_gfx_scratch_get(adev, &scratch);
-	if (r) {
-		DRM_ERROR("Failed to get scratch reg (%d).\n", r);
-		return r;
-	}
-	WREG32(scratch, 0xCAFEDEAD);
-
-	r = amdgpu_ring_alloc(ring, 8);
-	if (r) {
-		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
-		amdgpu_gfx_scratch_free(adev

Re: [PATCH 0/5] GFX9 KIQ

[Alex Deucher]

On Fri, May 12, 2017 at 7:11 AM, Tom St Denis  wrote:
> On 11/05/17 07:33 PM, Tom St Denis wrote:
>>
>> On 11/05/17 02:35 PM, Alex Deucher wrote:
>>>
>>> These are the laste of the gfx9 KIQ patches that haven't landed yet.  Can
>>> someone with gfx9 capable hw test this (vega10 or raven)?  This is needed
>>> to enable powergating on gfx9.
>>>
>>> Thanks,
>>
>>
>> If nobody gets to it by morning I'll try it out first thing on my vega10
>> though my VBIOS might need updating...
>
>
>
> They don't apply on top of either 4.9 nor 4.11...

Odd.  They applied for me (at least to the 4.11 tree I had checked out
when I left town).  Attached again just in case.

Alex

>
>
> Tom
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[PATCH 2/4] drm/radeon/ci: disable mclk switching for high refresh rates (v2)

[Alex Deucher]

Even if the vblank period would allow it, it still seems to
be problematic on some cards.

v2: fix logic inversion (Nils)

bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/ci_dpm.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index 7ba4508..ea36dc4 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -776,6 +776,12 @@ bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
u32 vblank_time = r600_dpm_get_vblank_time(rdev);
u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
 
+   /* disable mclk switching if the refresh is >120Hz, even if the
+* blanking period would allow it
+*/
+   if (r600_dpm_get_vrefresh(rdev) > 120)
+   return true;
+
if (vblank_time < switch_limit)
return true;
else
-- 
2.5.5

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[PATCH 3/4] drm/amd/powerplay/smu7: add vblank check for mclk switching (v2)

[Alex Deucher]

Check to make sure the vblank period is long enough to support
mclk switching.

v2: drop needless initial assignment (Nils)

bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 31 +---
 1 file changed, 27 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index a74a3db..1445c51 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2655,6 +2655,28 @@ static int smu7_get_power_state_size(struct pp_hwmgr 
*hwmgr)
return sizeof(struct smu7_power_state);
 }
 
+static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr,
+uint32_t vblank_time_us)
+{
+   struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+   uint32_t switch_limit_us;
+
+   switch (hwmgr->chip_id) {
+   case CHIP_POLARIS10:
+   case CHIP_POLARIS11:
+   case CHIP_POLARIS12:
+   switch_limit_us = data->is_memory_gddr5 ? 190 : 150;
+   break;
+   default:
+   switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
+   break;
+   }
+
+   if (vblank_time_us < switch_limit_us)
+   return true;
+   else
+   return false;
+}
 
 static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
struct pp_power_state *request_ps,
@@ -2669,6 +2691,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr 
*hwmgr,
bool disable_mclk_switching;
bool disable_mclk_switching_for_frame_lock;
struct cgs_display_info info = {0};
+   struct cgs_mode_info mode_info = {0};
const struct phm_clock_and_voltage_limits *max_limits;
uint32_t i;
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -2677,6 +2700,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr 
*hwmgr,
int32_t count;
int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
 
+   info.mode_info = &mode_info;
data->battery_state = (PP_StateUILabel_Battery ==
request_ps->classification.ui_label);
 
@@ -2703,8 +2727,6 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr 
*hwmgr,
 
cgs_get_active_displays_info(hwmgr->device, &info);
 
-   /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
-
minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
 
@@ -2769,8 +2791,9 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr 
*hwmgr,

PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
 
 
-   disable_mclk_switching = (1 < info.display_count) ||
-   disable_mclk_switching_for_frame_lock;
+   disable_mclk_switching = ((1 < info.display_count) ||
+ disable_mclk_switching_for_frame_lock ||
+ smu7_vblank_too_short(hwmgr, 
mode_info.vblank_time_us));
 
sclk = smu7_ps->performance_levels[0].engine_clock;
mclk = smu7_ps->performance_levels[0].memory_clock;
-- 
2.5.5

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[PATCH 1/4] drm/amdgpu/ci: disable mclk switching for high refresh rates (v2)

[Alex Deucher]

Even if the vblank period would allow it, it still seems to
be problematic on some cards.

v2: fix logic inversion (Nils)

bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c 
b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 6dc1410..ec93714 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -906,6 +906,12 @@ static bool ci_dpm_vblank_too_short(struct amdgpu_device 
*adev)
u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 
300;
 
+   /* disable mclk switching if the refresh is >120Hz, even if the
+* blanking period would allow it
+*/
+   if (amdgpu_dpm_get_vrefresh(adev) > 120)
+   return true;
+
if (vblank_time < switch_limit)
return true;
else
-- 
2.5.5

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[PATCH 4/4] drm/amd/powerplay/smu7: disable mclk switching for high refresh rates

[Alex Deucher]

Even if the vblank period would allow it, it still seems to
be problematic on some cards.

bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 1445c51..102eb6d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2793,7 +2793,8 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr 
*hwmgr,
 
disable_mclk_switching = ((1 < info.display_count) ||
  disable_mclk_switching_for_frame_lock ||
- smu7_vblank_too_short(hwmgr, 
mode_info.vblank_time_us));
+ smu7_vblank_too_short(hwmgr, 
mode_info.vblank_time_us) ||
+ (mode_info.refresh_rate > 120));
 
sclk = smu7_ps->performance_levels[0].engine_clock;
mclk = smu7_ps->performance_levels[0].memory_clock;
-- 
2.5.5

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Re: [PATCH] winsys/amdgpu: align VA allocations to fragment size

[Marek Olšák]

On Tue, May 23, 2017 at 6:43 PM, Christian König
 wrote:
> From: Christian König 
>
> BOs larger than the minimum fragment size should have their VA
> alignet to at least the fragment size for optimal performance.
>
> Signed-off-by: Christian König 
> ---
>  src/amd/common/ac_gpu_info.c  | 1 +
>  src/amd/common/ac_gpu_info.h  | 1 +
>  src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 2 ++
>  src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h | 1 +
>  4 files changed, 5 insertions(+)
>
> diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
> index cf5d6e1..0b4933e 100644
> --- a/src/amd/common/ac_gpu_info.c
> +++ b/src/amd/common/ac_gpu_info.c
> @@ -281,6 +281,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
> memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
> sizeof(amdinfo->gb_macro_tile_mode));
>
> +   info->pte_fragment_size = alignment_info.size_local;
> info->gart_page_size = alignment_info.size_remote;
>
> if (info->chip_class == SI)
> diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
> index d8029ef..3785eb4 100644
> --- a/src/amd/common/ac_gpu_info.h
> +++ b/src/amd/common/ac_gpu_info.h
> @@ -45,6 +45,7 @@ struct radeon_info {
> uint32_tpci_id;
> enum radeon_family  family;
> enum chip_class chip_class;
> +   uint32_tpte_fragment_size;
> uint32_tgart_page_size;
> uint64_tgart_size;
> uint64_tvram_size;
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
> b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
> index 6bdcce5..4017411 100644
> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
> @@ -415,6 +415,8 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct 
> amdgpu_winsys *ws,
> }
>
> va_gap_size = ws->check_vm ? MAX2(4 * alignment, 64 * 1024) : 0;
> +   if (size > ws->info.pte_fragment_size)
> +  alignment = MAX2(alignment, ws->info.pte_fragment_size);
> r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general,
>   size + va_gap_size, alignment, 0, &va, 
> &va_handle, 0);
> if (r)
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h 
> b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
> index 896a463..88975e2 100644
> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
> @@ -73,6 +73,7 @@ struct amdgpu_winsys {
>
> struct amdgpu_gpu_info amdinfo;
> ADDR_HANDLE addrlib;
> +   struct amdgpu_buffer_size_alignmentsalignments;
>
> bool check_vm;

This hunk seems unnecessary. If you remove it, the patch is:

Reviewed-by: Marek Olšák 

Marek
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Re: [PATCH] drm/radeon: Fix oops upon driver load on PowerXpress laptops

[Alex Deucher]

On Tue, May 23, 2017 at 2:47 PM, Deucher, Alexander
 wrote:
>> -Original Message-
>> From: Lukas Wunner [mailto:lu...@wunner.de]
>> Sent: Monday, May 22, 2017 11:51 PM
>> To: Michel Dänzer
>> Cc: Nicolai Stange; Sean Paul; Deucher, Alexander; dri-
>> de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Koenig,
>> Christian
>> Subject: Re: [PATCH] drm/radeon: Fix oops upon driver load on PowerXpress
>> laptops
>>
>> On Tue, May 23, 2017 at 12:09:49PM +0900, Michel Dänzer wrote:
>> > On 22/05/17 11:04 PM, Lukas Wunner wrote:
>> > > On Sun, May 21, 2017 at 09:31:09AM +0200, Nicolai Stange wrote:
>> > >> On Thu, May 18 2017, Lukas Wunner wrote:
>> > > [snip]
>> > >>> Reported-by: Nicolai Stange 
>> > >>> Fixes: 7ffb0ce31cf9 ("drm/radeon: Don't register Thunderbolt eGPU
>> with vga_switcheroo")
>> > >>> Signed-off-by: Lukas Wunner 
>> > >>> ---
>> > >>>
>> > >>> Awaiting a Tested-by: from Nicolai, but it's clear this is a bug and
>> > >>> needs to be fixed, so sending out with a proper commit message now.
>> > >>> The bug was only introduced to radeon, not amdgpu.
>> > >>
>> > >> Tested-by: Nicolai Stange 
>> > >>
>> > >> Thanks for the quick fix!
>> > >>
>> > >>> @Alex Deucher: I could push this to drm-misc-fixes but then it
>> wouldn't
>> > >>> land before -rc3 because Sean Paul has already sent out the -rc2 pull.
>> > >>> I notice you haven't sent out a pull for -rc2 yet, so maybe you want to
>> > >>> take it yourself?  Whichever you prefer.  Thanks & sorry for the
>> breakage!
>> > >
>> > > I've learned this morning that Alex is on vacation.
>> >
>> > Christian König is standing in for Alex.
>>
>> By his own account, he already has "all hands full replacing him [Alex]",
>> explicitly asked Daniel to merge an amdgpu patch through drm-misc-next for
>> this reason and lacks permission to update branches in Alex' repo on fdo:
>>
>> "One lesson learned from the past week is that Alex needs to stop using
>> his personal repository on fdo.
>> We were asked a couple of times if I couldn't update a branch there from
>> different directions, which we obviously can't do."
>>
>> https://lists.freedesktop.org/archives/dri-devel/2017-May/142376.html
>> https://lists.freedesktop.org/archives/dri-devel/2017-May/142380.html
>>
>
> What tree we use for pull requests is irrelevant.  We need to follow the 
> proper protocol.  In the future patches like this should have an ack or rb 
> and should flow through the radeon tree.
>
>>
>> > > I've pushed the patch to drm-misc-fixes so that the issue is fixed in
>> > > 4.12-rc3.
>> >
>> > I don't think there was any particular need to bypass the normal radeon
>> > tree for this. There was plenty of time for the fix to get into 4.12
>> > final, even after Alex is back.
>>
>> Well, it wouldn't be nice towards users affected by the same issue
>> who may waste time with bisecting to just sit on a fix twiddling thumbs.
>
> We also need to try and avoid regressions and try and flow changes through 
> proper trees.  There is always going to be some delay in getting changes 
> upstream.

Sorry for piling on, I hadn't quite caught up with the whole thread
yet.  In the end no harm done.

Alex

>
> Alex
>
>>
>> Thanks,
>>
>> Lukas
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Re: [PATCH 7/7] drm/amdgpu: enable huge page handling in the VM v2

[Felix Kuehling]

Do you need something in amdgpu_vm_update_level to stop it from
overwriting huge page PTEs?

Regards,
  Felix


On 17-05-23 12:52 PM, Christian König wrote:
> From: Christian König 
>
> The hardware can use huge pages to map 2MB of address space with only one PDE.
>
> v2: few cleanups and rebased
>
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 95 
> +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  4 ++
>  2 files changed, 75 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index f7afdfa..f07c9b8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -325,6 +325,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device 
> *adev,
>  
>   entry->bo = pt;
>   entry->addr = 0;
> + entry->huge_page = false;
>   }
>  
>   if (level < adev->vm_manager.num_level) {
> @@ -1013,7 +1014,8 @@ static int amdgpu_vm_update_level(struct amdgpu_device 
> *adev,
>  
>   pt = amdgpu_bo_gpu_offset(bo);
>   pt = amdgpu_gart_get_vm_pde(adev, pt);
> - if (parent->entries[pt_idx].addr == pt)
> + if (parent->entries[pt_idx].addr == pt ||
> + parent->entries[pt_idx].huge_page)
>   continue;
>  
>   parent->entries[pt_idx].addr = pt;
> @@ -1145,29 +1147,69 @@ int amdgpu_vm_update_directories(struct amdgpu_device 
> *adev,
>  }
>  
>  /**
> - * amdgpu_vm_find_pt - find the page table for an address
> + * amdgpu_vm_handle_huge_pages - handle updating the PD with huge pages
>   *
>   * @p: see amdgpu_pte_update_params definition
>   * @addr: virtual address in question
> + * @nptes: number of PTEs updated with this operation
> + * @dst: destination address where the PTEs should point to
> + * @flags: access flags fro the PTEs
> + * @bo: resulting page tables BO
>   *
> - * Find the page table BO for a virtual address, return NULL when none found.
> + * Check if we can update the PD with a huge page. Also finds the page table
> + * BO for a virtual address, returns -ENOENT when nothing found.
>   */
> -static struct amdgpu_bo *amdgpu_vm_get_pt(struct amdgpu_pte_update_params *p,
> -   uint64_t addr)
> +static int amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
> +uint64_t addr, unsigned nptes,
> +uint64_t dst, uint64_t flags,
> +struct amdgpu_bo **bo)
>  {
> - struct amdgpu_vm_pt *entry = &p->vm->root;
> - unsigned idx, level = p->adev->vm_manager.num_level;
> + unsigned pt_idx, level = p->adev->vm_manager.num_level;
> + struct amdgpu_vm_pt *entry = &p->vm->root, *parent;
> + uint64_t pd_addr, pde;
>  
> - while (entry->entries) {
> - idx = addr >> (p->adev->vm_manager.block_size * level--);
> - idx %= amdgpu_bo_size(entry->bo) / 8;
> - entry = &entry->entries[idx];
> - }
> + do {
> + pt_idx = addr >> (p->adev->vm_manager.block_size * level--);
> + pt_idx %= amdgpu_bo_size(entry->bo) / 8;
> + parent = entry;
> + entry = &entry->entries[pt_idx];
> + } while (entry->entries);
>  
>   if (level)
> - return NULL;
> + return -ENOENT;
> +
> + *bo = entry->bo;
> +
> + /* In the case of a mixed PT the PDE must point to it*/
> + if (p->adev->asic_type < CHIP_VEGA10 ||
> + nptes != AMDGPU_VM_PTE_COUNT(p->adev) ||
> + p->func != amdgpu_vm_do_set_ptes ||
> + !(flags & AMDGPU_PTE_VALID)) {
> +
> + dst = amdgpu_bo_gpu_offset(*bo);
> + dst = amdgpu_gart_get_vm_pde(p->adev, dst);
> + flags = AMDGPU_PTE_VALID;
> + } else {
> + flags |= AMDGPU_PDE_PTE;
> + }
>  
> - return entry->bo;
> + if (entry->addr == dst &&
> + entry->huge_page == !!(flags & AMDGPU_PDE_PTE))
> + return 0;
> +
> + entry->addr = dst;
> + entry->huge_page = !!(flags & AMDGPU_PDE_PTE);
> +
> + if (parent->bo->shadow) {
> + pd_addr = amdgpu_bo_gpu_offset(parent->bo->shadow);
> + pde = pd_addr + pt_idx * 8;
> + amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags);
> + }
> +
> + pd_addr = amdgpu_bo_gpu_offset(parent->bo);
> + pde = pd_addr + pt_idx * 8;
> + amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags);
> + return 0;
>  }
>  
>  /**
> @@ -1193,14 +1235,20 @@ static int amdgpu_vm_update_ptes(struct 
> amdgpu_pte_update_params *params,
>   uint64_t addr, pe_start;
>   struct amdgpu_bo *pt;
>   unsigned nptes;
> + int r;
>  
>   /* walk over the address space and update the page tables */
>   for (addr = st

Re: [PATCH 1/7] drm/amdgpu: cleanup adjust_mc_addr handling v3

[Felix Kuehling]

On 17-05-23 12:52 PM, Christian König wrote:
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -395,7 +395,13 @@
>  static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev, 
>   return pte_flag; 
>  }   
> +static uint64_t gmc_v6_0_get_vm_pde(struct amdgpu_device *adev,
> uint64_t addr)
> +{
> + BUG_ON(addr & 0xF000FFFULL);
> + return addr;
> +}
> +

The mask in the BUG_ON leaves out the highest 4 bits (63-60). Is that
intentional? Same for gmc_v7_0.c.

> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 3b5ea0f..f05c034 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -656,7 +656,13 @@
>  static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev, 
>   return pte_flag; 
>  } 
>   
> +static uint64_t gmc_v8_0_get_vm_pde(struct amdgpu_device *adev,
> uint64_t addr)
> +{
> + BUG_ON(addr & 0xFFF00FFFULL);
> + return addr;
> +}
> +

This looks like you're allowing 52bit physical addresses for GFX 8.
AFAIK the HW only supports 40 bits. Is that intentional?

Other than that, the patch is Reviewed-by: Felix Kuehling


Regards,
  Felix
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[PATCH umr] Add error checking to umr_read_vram().

[Tom St Denis]

Signed-off-by: Tom St Denis 
---
 src/lib/read_vram.c | 27 ++-
 1 file changed, 18 insertions(+), 9 deletions(-)

diff --git a/src/lib/read_vram.c b/src/lib/read_vram.c
index deb958dc4c88..80ef4a5664de 100644
--- a/src/lib/read_vram.c
+++ b/src/lib/read_vram.c
@@ -155,7 +155,8 @@ static int umr_read_vram_vi(struct umr_asic *asic, uint32_t 
vmid, uint64_t addre
DEBUG("pde_idx=%llx, frag_size=%u, 
pte_base_addr=0x%llx, valid=%d\n", (unsigned long long)pde_idx, 
(unsigned)pde_fields.frag_size, (unsigned long long)pde_fields.pte_base_addr, 
(int)pde_fields.valid);
 
// now read PTE entry for this page
-   umr_read_vram(asic, 0x, pde_fields.pte_base_addr + 
pte_idx*8, 8, &pte_entry);
+   if (umr_read_vram(asic, 0x, 
pde_fields.pte_base_addr + pte_idx*8, 8, &pte_entry) < 0)
+   return -1;
 
// decode PTE values
pte_fields.page_base_addr = pte_entry & 0xFFF000ULL;
@@ -170,7 +171,8 @@ static int umr_read_vram_vi(struct umr_asic *asic, uint32_t 
vmid, uint64_t addre
// depth == 0 == PTE only
pte_idx = (address >> 12);
 
-   umr_read_vram(asic, 0x, page_table_base_addr + 
pte_idx * 8, 8, &pte_entry);
+   if (umr_read_vram(asic, 0x, page_table_base_addr + 
pte_idx * 8, 8, &pte_entry) < 0)
+   return -1;
 
// decode PTE values
pte_fields.page_base_addr = pte_entry & 0xFFF000ULL;
@@ -280,8 +282,8 @@ static int umr_read_vram_ai(struct umr_asic *asic, uint32_t 
vmid, uint64_t addre
 
address -= page_table_start_addr;
 
-   first = 1;
while (size) {
+   first = 1;
if (page_table_depth >= 1) {
// mask off valid bit
page_table_base_addr &= ~1ULL;
@@ -306,7 +308,8 @@ static int umr_read_vram_ai(struct umr_asic *asic, uint32_t 
vmid, uint64_t addre
DEBUG("selector mask == %llx\n", ((unsigned 
long long)511 << ((page_table_depth-1)*9 + (12 + 9 + page_table_size;
 
// read PDE entry
-   umr_read_vram(asic, 0x, pde_address + 
pde_idx * 8, 8, &pde_entry);
+   if (umr_read_vram(asic, 0x, pde_address + 
pde_idx * 8, 8, &pde_entry) < 0)
+   return -1;
 
// decode PDE values
pde_fields.frag_size = (pde_entry >> 59) & 
0x1F;
@@ -326,7 +329,8 @@ static int umr_read_vram_ai(struct umr_asic *asic, uint32_t 
vmid, uint64_t addre
}
 
// now read PTE entry for this page
-   umr_read_vram(asic, 0x, pde_fields.pte_base_addr + 
pte_idx*8, 8, &pte_entry);
+   if (umr_read_vram(asic, 0x, 
pde_fields.pte_base_addr + pte_idx*8, 8, &pte_entry) < 0)
+   return -1;
 
// decode PTE values
pte_fields.page_base_addr = pte_entry & 
0xF000ULL;
@@ -346,15 +350,17 @@ static int umr_read_vram_ai(struct umr_asic *asic, 
uint32_t vmid, uint64_t addre
pde_idx = 0; // unused
pde_fields.frag_size = (page_table_base_addr >> 59) 
& 0x1F;
pde_fields.pte_base_addr = page_table_base_addr & 
0xF000ULL;
+   pde_fields.system= (page_table_base_addr >> 1) 
& 1;
pde_fields.valid = page_table_base_addr & 1;
-   DEBUG("pde_idx=%llx, frag_size=%u, 
pte_base_addr=0x%llx, valid=%d\n",
+   DEBUG("pde_idx=%llx, frag_size=%u, 
pte_base_addr=0x%llx, system=%d, valid=%d\n",
(unsigned long long)pde_idx, 
(unsigned)pde_fields.frag_size, (unsigned long long)pde_fields.pte_base_addr,
-   (int)pde_fields.valid);
+   (int)pde_fields.system, (int)pde_fields.valid);
 
// PTE addr = baseaddr[47:6] + (logical - start) >> 
fragsize)
pte_idx = (address >> (12 + pde_fields.frag_size));
 
-   umr_read_vram(asic, 0x, pde_fields.pte_base_addr + 
pte_idx * 8, 8, &pte_entry);
+   if (umr_read_vram(asic, 0x, 
pde_fields.pte_base_addr + pte_idx * 8, 8, &pte_entry) < 0)
+   return -1;
 
// decode PTE values
pte_fields.page_base_addr = pte_entry & 
0x000ULL;
@@ -414,7 +420,10 @@ int umr_read_vram(struct umr_asic *asic, uint32_t vmid, 
uint64_t address, uint32
// addressing i

RE: [PATCH] drm/radeon: Fix oops upon driver load on PowerXpress laptops

[Deucher, Alexander]

> -Original Message-
> From: Lukas Wunner [mailto:lu...@wunner.de]
> Sent: Monday, May 22, 2017 11:51 PM
> To: Michel Dänzer
> Cc: Nicolai Stange; Sean Paul; Deucher, Alexander; dri-
> de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Koenig,
> Christian
> Subject: Re: [PATCH] drm/radeon: Fix oops upon driver load on PowerXpress
> laptops
> 
> On Tue, May 23, 2017 at 12:09:49PM +0900, Michel Dänzer wrote:
> > On 22/05/17 11:04 PM, Lukas Wunner wrote:
> > > On Sun, May 21, 2017 at 09:31:09AM +0200, Nicolai Stange wrote:
> > >> On Thu, May 18 2017, Lukas Wunner wrote:
> > > [snip]
> > >>> Reported-by: Nicolai Stange 
> > >>> Fixes: 7ffb0ce31cf9 ("drm/radeon: Don't register Thunderbolt eGPU
> with vga_switcheroo")
> > >>> Signed-off-by: Lukas Wunner 
> > >>> ---
> > >>>
> > >>> Awaiting a Tested-by: from Nicolai, but it's clear this is a bug and
> > >>> needs to be fixed, so sending out with a proper commit message now.
> > >>> The bug was only introduced to radeon, not amdgpu.
> > >>
> > >> Tested-by: Nicolai Stange 
> > >>
> > >> Thanks for the quick fix!
> > >>
> > >>> @Alex Deucher: I could push this to drm-misc-fixes but then it
> wouldn't
> > >>> land before -rc3 because Sean Paul has already sent out the -rc2 pull.
> > >>> I notice you haven't sent out a pull for -rc2 yet, so maybe you want to
> > >>> take it yourself?  Whichever you prefer.  Thanks & sorry for the
> breakage!
> > >
> > > I've learned this morning that Alex is on vacation.
> >
> > Christian König is standing in for Alex.
> 
> By his own account, he already has "all hands full replacing him [Alex]",
> explicitly asked Daniel to merge an amdgpu patch through drm-misc-next for
> this reason and lacks permission to update branches in Alex' repo on fdo:
> 
> "One lesson learned from the past week is that Alex needs to stop using
> his personal repository on fdo.
> We were asked a couple of times if I couldn't update a branch there from
> different directions, which we obviously can't do."
> 
> https://lists.freedesktop.org/archives/dri-devel/2017-May/142376.html
> https://lists.freedesktop.org/archives/dri-devel/2017-May/142380.html
> 

What tree we use for pull requests is irrelevant.  We need to follow the proper 
protocol.  In the future patches like this should have an ack or rb and should 
flow through the radeon tree.

> 
> > > I've pushed the patch to drm-misc-fixes so that the issue is fixed in
> > > 4.12-rc3.
> >
> > I don't think there was any particular need to bypass the normal radeon
> > tree for this. There was plenty of time for the fix to get into 4.12
> > final, even after Alex is back.
> 
> Well, it wouldn't be nice towards users affected by the same issue
> who may waste time with bisecting to just sit on a fix twiddling thumbs.

We also need to try and avoid regressions and try and flow changes through 
proper trees.  There is always going to be some delay in getting changes 
upstream.

Alex

> 
> Thanks,
> 
> Lukas
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH 1/2] drm/amdgpu: fix null point error when rmmod amdgpu.

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Monday, May 22, 2017 5:10 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 1/2] drm/amdgpu: fix null point error when rmmod amdgpu.
> 
> this bug happened when amdgpu load failed.
> 
> [   75.740951] BUG: unable to handle kernel paging request at
> 31c0
> [   75.748167] IP: []
> amdgpu_fbdev_restore_mode+0x20/0x60 [amdgpu]
> [   75.755774] PGD 0
> 
> [   75.759185] Oops:  [#1] SMP
> [   75.762408] Modules linked in: amdgpu(OE-) ttm(OE) drm_kms_helper(OE)
> drm(OE) i2c_algo_bit(E) fb_sys_fops(E) syscopyarea(E) sysfillrect(E)
> sysimgblt(E) rpcsec_gss_krb5(E) nfsv4(E) nfs(E) fscache(E) eeepc_wmi(E)
> asus_wmi(E) sparse_keymap(E) intel_rapl(E) snd_hda_codec_hdmi(E)
> snd_hda_codec_realtek(E) snd_hda_codec_generic(E) snd_hda_intel(E)
> snd_hda_codec(E) snd_hda_core(E) x86_pkg_temp_thermal(E)
> intel_powerclamp(E) snd_hwdep(E) snd_pcm(E) snd_seq_midi(E)
> coretemp(E) kvm_intel(E) snd_seq_midi_event(E) snd_rawmidi(E) kvm(E)
> snd_seq(E) joydev(E) snd_seq_device(E) snd_timer(E) irqbypass(E)
> crct10dif_pclmul(E) crc32_pclmul(E) mei_me(E) ghash_clmulni_intel(E)
> snd(E) aesni_intel(E) mei(E) soundcore(E) aes_x86_64(E) shpchp(E)
> serio_raw(E) lrw(E) acpi_pad(E) gf128mul(E) glue_helper(E) ablk_helper(E)
> mac_hid(E)
> [   75.835574]  cryptd(E) parport_pc(E) ppdev(E) lp(E) nfsd(E) parport(E)
> auth_rpcgss(E) nfs_acl(E) lockd(E) grace(E) sunrpc(E) autofs4(E)
> hid_generic(E) usbhid(E) mxm_wmi(E) psmouse(E) e1000e(E) ptp(E)
> pps_core(E) ahci(E) libahci(E) wmi(E) video(E) i2c_hid(E) hid(E)
> [   75.858489] CPU: 5 PID: 1603 Comm: rmmod Tainted: G   OE   4.9.0-
> custom #2
> [   75.866183] Hardware name: System manufacturer System Product
> Name/Z170-A, BIOS 0901 08/31/2015
> [   75.875050] task: 88045d1bbb80 task.stack: c90002de4000
> [   75.881094] RIP: 0010:[]  []
> amdgpu_fbdev_restore_mode+0x20/0x60 [amdgpu]
> [   75.891238] RSP: 0018:c90002de7d48  EFLAGS: 00010286
> [   75.896648] RAX:  RBX:  RCX:
> 0001
> [   75.903933] RDX:  RSI: 88045d1bbb80 RDI:
> 0286
> [   75.911183] RBP: c90002de7d50 R08: 0502 R09:
> 0004
> [   75.918449] R10:  R11: 0001 R12:
> 880464bf
> [   75.925675] R13: a0853000 R14:  R15:
> 564e44f88210
> [   75.932980] FS:  7f13d5400700() GS:88047654()
> knlGS:
> [   75.941238] CS:  0010 DS:  ES:  CR0: 80050033
> [   75.947088] CR2: 31c0 CR3: 00045fd0b000 CR4:
> 003406e0
> [   75.954332] DR0:  DR1:  DR2:
> 
> [   75.961566] DR3:  DR6: fffe0ff0 DR7:
> 0400
> [   75.968834] Stack:
> [   75.970881]  880464bf c90002de7d60 a0636592
> c90002de7d80
> [   75.978454]  a059015f 880464bf 880464bf
> c90002de7da8
> [   75.986076]  a0595216 880464bf 880460f4d000
> a0853000
> [   75.993692] Call Trace:
> [   75.996177]  [] amdgpu_driver_lastclose_kms+0x12/0x20
> [amdgpu]
> [   76.003700]  [] drm_lastclose+0x2f/0xd0 [drm]
> [   76.009777]  [] drm_dev_unregister+0x16/0xd0 [drm]
> [   76.016255]  [] drm_put_dev+0x34/0x70 [drm]
> [   76.022139]  [] amdgpu_pci_remove+0x15/0x20
> [amdgpu]
> [   76.028800]  [] pci_device_remove+0x39/0xc0
> [   76.034661]  [] __device_release_driver+0x9a/0x140
> [   76.041121]  [] driver_detach+0xb8/0xc0
> [   76.046575]  [] bus_remove_driver+0x55/0xd0
> [   76.052401]  [] driver_unregister+0x2c/0x50
> [   76.058244]  [] pci_unregister_driver+0x29/0x90
> [   76.064466]  [] drm_pci_exit+0x9e/0xb0 [drm]
> [   76.070507]  [] amdgpu_exit+0x1c/0x32 [amdgpu]
> [   76.076609]  [] SyS_delete_module+0x1a0/0x200
> [   76.082627]  [] ? rcu_eqs_enter.isra.36+0x4a/0x50
> [   76.089001]  [] do_syscall_64+0x6e/0x180
> [   76.094583]  [] entry_SYSCALL64_slow_path+0x25/0x25
> [   76.101114] Code: 94 c0 c3 31 c0 5d c3 0f 1f 40 00 0f 1f 44 00 00 55 31 c0 
> 48 89
> e5 53 48 89 fb 48 c7 c7 1d 21 84 a0 e8 ab 77 b3 e0 e8 fc 8b d7 e0 <48> 8b bb 
> c0
> 31 00 00 48 85 ff 74 09 e8 ff eb fc ff 85 c0 75 03
> [   76.121432] RIP  []
> amdgpu_fbdev_restore_mode+0x20/0x60 [amdgpu]
> 
> Change-Id: I8021d72a3381bc68b6724b43b7a12cb6c5acbe9a
> Signed-off-by: Rex Zhu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> index e869e60..667996b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
> @@ -430,10 +430,15 @@ bool amdgpu_fbdev_robj_is_fb(struct
> amdgpu_device *adev, struct amdgpu_bo *robj)
> 
>  void amdg

RE: [PATCH] drm/amd: include instead of "linux/delay.h"

[Deucher, Alexander]

> -Original Message-
> From: Koenig, Christian
> Sent: Monday, May 22, 2017 4:12 AM
> To: Christian König; Masahiro Yamada; dri-de...@lists.freedesktop.org;
> Daniel Vetter; Deucher, Alexander; Daenzer, Michel; linux-
> ker...@vger.kernel.org; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amd: include  instead of
> "linux/delay.h"
> 
> Am 22.05.2017 um 10:06 schrieb Daniel Vetter:
> > On Mon, May 22, 2017 at 09:55:46AM +0200, Christian König wrote:
> >> Am 22.05.2017 um 09:39 schrieb Daniel Vetter:
> >>> On Thu, May 18, 2017 at 08:47:34AM +0200, Christian König wrote:
>  Am 18.05.2017 um 06:43 schrieb Masahiro Yamada:
> > Use <...> notation to include headers located in include/linux.
> > While we are here, tweak the includes order a bit to sort them
> > alphabetically.
> >
> > Signed-off-by: Masahiro Yamada
> 
>  Reviewed-by: Christian König 
> >>> I think I'll leave this one for Alex, but I guess I can pick it up into
> >>> drm-misc too if that's simpler ... All the other include patches are in
> >>> there already.
> >> Please pick that up for drm-misc. Alex is on vacation this week and I
> >> already have all hands full replacing him.
> > Done. Aside: Switching to commit rights is a nice way to make maintainer
> > vacations real smooth :-) I wanted to chat with Alex about that anyway, I
> > guess I'll ping him when he's back.
> 
> Completely agree. One lesson learned from the past week is that Alex
> needs to stop using his personal repository on fdo.
> 
> We were asked a couple of times if I couldn't update a branch there from
> different directions, which we obviously can't do.

Regardless of what tree we use for -fixes and -next pulls or who happens to be 
on vacation, we can still pull patches like this into our internal tree for 
testing and eventual integration into -fixes or -next.  The same as any other 
patches we integrate.

Alex

> 
> Christian.
> 
> >
> > Cheers, Daniel
> >
> >> Christian.
> >>
> >>> -Daniel
> > ---
> >
> > drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 4 ++--
> > drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c  | 2 +-
> > drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 4 ++--
> > drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 5
> +++--
> > drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c   | 8
> +---
> > drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c  | 5 +++--
> > 6 files changed, 16 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> > index ff4ae3d..963a9e0 100644
> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> > @@ -22,10 +22,10 @@
> >  */
> > #include "pp_debug.h"
> > -#include "linux/delay.h"
> > -#include 
> > +#include 
> > #include 
> > #include 
> > +#include 
> > #include 
> > #include "cgs_common.h"
> > #include "power_state.h"
> > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c
> > index f5e8fda..f6b4dd9 100644
> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c
> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_acpi.c
> > @@ -21,8 +21,8 @@
> >  *
> >  */
> > +#include 
> > #include 
> > -#include "linux/delay.h"
> > #include "hwmgr.h"
> > #include "amd_acpi.h"
> > #include "pp_acpi.h"
> > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> > index 8f663ab..581374d 100644
> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> > @@ -21,11 +21,11 @@
> >  *
> >  */
> > #include "pp_debug.h"
> > +#include 
> > +#include 
> > #include 
> > #include 
> > -#include 
> > #include 
> > -#include "linux/delay.h"
> > #include "pp_acpi.h"
> > #include "ppatomctrl.h"
> > #include "atombios.h"
> > diff --git
> a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> > index 8394955..f4ab81b 100644
> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> > @@ -20,10 +20,11 @@
> >  * OTHER DEALINGS IN THE SOFTWARE.
> >  *
> >  */
> > +
> > +#include 
> > +#include 
> > #include 
> > #include 
> > -#include 
> > -#include "linux/delay.h"
> > #include "hwmgr.h"
> > #include "amd_powerplay.h"
> > diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
> b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
> >

RE: [PATCH] iommu/amd: flush IOTLB for specific domains only (v3)

[Deucher, Alexander]

> -Original Message-
> From: Arindam Nath [mailto:anath@gmail.com] On Behalf Of
> arindam.n...@amd.com
> Sent: Monday, May 22, 2017 3:48 AM
> To: io...@lists.linux-foundation.org
> Cc: amd-gfx@lists.freedesktop.org; Joerg Roedel; Deucher, Alexander;
> Bridgman, John; dr...@endlessm.com; Suthikulpanit, Suravee;
> li...@endlessm.com; Craig Stein; mic...@daenzer.net; Kuehling, Felix;
> sta...@vger.kernel.org; Nath, Arindam
> Subject: [PATCH] iommu/amd: flush IOTLB for specific domains only (v3)
> 
> From: Arindam Nath 
> 
> Change History
> --
> 
> v3:
> - add Fixes and CC tags
> - add link to Bugzilla
> 
> v2: changes suggested by Joerg
> - add flush flag to improve efficiency of flush operation
> 
> v1:
> - The idea behind flush queues is to defer the IOTLB flushing
>   for domains for which the mappings are no longer valid. We
>   add such domains in queue_add(), and when the queue size
>   reaches FLUSH_QUEUE_SIZE, we perform __queue_flush().
> 
>   Since we have already taken lock before __queue_flush()
>   is called, we need to make sure the IOTLB flushing is
>   performed as quickly as possible.
> 
>   In the current implementation, we perform IOTLB flushing
>   for all domains irrespective of which ones were actually
>   added in the flush queue initially. This can be quite
>   expensive especially for domains for which unmapping is
>   not required at this point of time.
> 
>   This patch makes use of domain information in
>   'struct flush_queue_entry' to make sure we only flush
>   IOTLBs for domains who need it, skipping others.
> 
> Bugzilla: https://bugs.freedesktop.org/101029
> Fixes: b1516a14657a ("iommu/amd: Implement flush queue")
> Cc: sta...@vger.kernel.org
> Suggested-by: Joerg Roedel 
> Signed-off-by: Arindam Nath 

Acked-by: Alex Deucher 

> ---
>  drivers/iommu/amd_iommu.c   | 27 ---
>  drivers/iommu/amd_iommu_types.h |  2 ++
>  2 files changed, 22 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
> index 63cacf5..1edeebec 100644
> --- a/drivers/iommu/amd_iommu.c
> +++ b/drivers/iommu/amd_iommu.c
> @@ -2227,15 +2227,26 @@ static struct iommu_group
> *amd_iommu_device_group(struct device *dev)
> 
>  static void __queue_flush(struct flush_queue *queue)
>  {
> - struct protection_domain *domain;
> - unsigned long flags;
>   int idx;
> 
> - /* First flush TLB of all known domains */
> - spin_lock_irqsave(&amd_iommu_pd_lock, flags);
> - list_for_each_entry(domain, &amd_iommu_pd_list, list)
> - domain_flush_tlb(domain);
> - spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
> + /* First flush TLB of all domains which were added to flush queue */
> + for (idx = 0; idx < queue->next; ++idx) {
> + struct flush_queue_entry *entry;
> +
> + entry = queue->entries + idx;
> +
> + /*
> +  * There might be cases where multiple IOVA entries for the
> +  * same domain are queued in the flush queue. To avoid
> +  * flushing the same domain again, we check whether the
> +  * flag is set or not. This improves the efficiency of
> +  * flush operation.
> +  */
> + if (!entry->dma_dom->domain.already_flushed) {
> + entry->dma_dom->domain.already_flushed = true;
> + domain_flush_tlb(&entry->dma_dom->domain);
> + }
> + }
> 
>   /* Wait until flushes have completed */
>   domain_flush_complete(NULL);
> @@ -2289,6 +2300,8 @@ static void queue_add(struct dma_ops_domain
> *dma_dom,
>   pages = __roundup_pow_of_two(pages);
>   address >>= PAGE_SHIFT;
> 
> + dma_dom->domain.already_flushed = false;
> +
>   queue = get_cpu_ptr(&flush_queue);
>   spin_lock_irqsave(&queue->lock, flags);
> 
> diff --git a/drivers/iommu/amd_iommu_types.h
> b/drivers/iommu/amd_iommu_types.h
> index 4de8f41..4f5519d 100644
> --- a/drivers/iommu/amd_iommu_types.h
> +++ b/drivers/iommu/amd_iommu_types.h
> @@ -454,6 +454,8 @@ struct protection_domain {
>   bool updated;   /* complete domain flush required */
>   unsigned dev_cnt;   /* devices assigned to this domain */
>   unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference
> count */
> + bool already_flushed;   /* flag to avoid flushing the same domain
> again
> +in a single invocation of __queue_flush() */
>  };
> 
>  /*
> --
> 2.7.4

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RE: [PATCH] drm/amdgpu: fix ocl test performance drop

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Flora Cui
> Sent: Thursday, May 18, 2017 11:37 PM
> To: Christian K�nig
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: fix ocl test performance drop
> 
> btw, what's about gfx9 for amdgpu_vm_ring_has_compute_vm_bug()? Is
> the
> workaround still needed?

Gfx9 is not affected by that issue.

Alex

> 
> On Fri, May 19, 2017 at 10:25:19AM +0800, Flora Cui wrote:
> > On Thu, May 18, 2017 at 01:38:15PM +0200, Christian König wrote:
> > > Am 18.05.2017 um 09:45 schrieb Flora Cui:
> > > >partial revert commit <6971d3d> - drm/amdgpu: cleanup logic in
> > > >amdgpu_vm_flush
> > > >
> > > >Change-Id: Iadce9d613dfe9a739643a74050cea55854832adb
> > > >Signed-off-by: Flora Cui 
> > >
> > > I don't see how the revert should be faster than the original.
> > >
> > > Especially that amdgpu_vm_had_gpu_reset() is now called twice sounds
> like
> > > more overhead than necessary.
> > >
> > > Please explain further.
> > >
> > > Christian.
> > >
> > > >---
> > > >  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 +-
> > > >  1 file changed, 5 insertions(+), 9 deletions(-)
> > > >
> > > >diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> > > >index 88420dc..a96bad6 100644
> > > >--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> > > >+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> > > >@@ -743,23 +743,19 @@ int amdgpu_vm_flush(struct amdgpu_ring
> *ring, struct amdgpu_job *job)
> > > > id->gws_size != job->gws_size ||
> > > > id->oa_base != job->oa_base ||
> > > > id->oa_size != job->oa_size);
> > > >-bool vm_flush_needed = job->vm_needs_flush ||
> > > >-amdgpu_vm_ring_has_compute_vm_bug(ring);
> > > > unsigned patch_offset = 0;
> > > > int r;
> > > >-if (amdgpu_vm_had_gpu_reset(adev, id)) {
> > > >-gds_switch_needed = true;
> > > >-vm_flush_needed = true;
> > > >-}
> > > >-
> > > >-if (!vm_flush_needed && !gds_switch_needed)
> > > >+if (!job->vm_needs_flush && !gds_switch_needed &&
> > > >+!amdgpu_vm_had_gpu_reset(adev, id) &&
> > > >+!amdgpu_vm_ring_has_compute_vm_bug(ring))
> > > > return 0;
> > > > if (ring->funcs->init_cond_exec)
> > > > patch_offset = amdgpu_ring_init_cond_exec(ring);
> > > >-if (ring->funcs->emit_vm_flush && vm_flush_needed) {
> > [flora]: for compute ring & amdgpu_vm_ring_has_compute_vm_bug(), a
> vm_flush is
> > inserted. This might cause performance drop.
> > > >+if (ring->funcs->emit_vm_flush &&
> > > >+(job->vm_needs_flush || amdgpu_vm_had_gpu_reset(adev, id)))
> {
> > > > struct fence *fence;
> > > > trace_amdgpu_vm_flush(ring, job->vm_id, job-
> >vm_pd_addr);
> > >
> > >
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH xf86-video-ati] Update URLs

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Michel Dänzer
> Sent: Wednesday, May 17, 2017 10:17 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH xf86-video-ati] Update URLs
> 
> From: Michel Dänzer 
> 
> * Point to the amd-gfx mailing list
> * Specify the component in all bugzilla URLs
> * Use https:// for all HTML URLs
> 
> Signed-off-by: Michel Dänzer 

Reviewed-by: Alex Deucher 

> ---
>  README | 14 +++---
>  configure.ac   |  2 +-
>  man/radeon.man |  6 +++---
>  3 files changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/README b/README
> index 4b92a1858..db982fbed 100644
> --- a/README
> +++ b/README
> @@ -1,25 +1,25 @@
> -xf86-video-ati - ATI Radeon video driver for the Xorg X server
> +xf86-video-ati - ATI/AMD Radeon video driver for the Xorg X server
> 
>  All questions regarding this software should be directed at the
> -Xorg mailing list:
> +amd-gfx mailing list:
> 
> -http://lists.freedesktop.org/mailman/listinfo/xorg
> +https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> 
>  Please submit bug reports to the Xorg bugzilla:
> 
> -https://bugs.freedesktop.org/enter_bug.cgi?product=xorg
> +
> https://bugs.freedesktop.org/enter_bug.cgi?product=xorg&component=Dri
> ver/Radeon
> 
>  The master development code repository can be found at:
> 
>  git://anongit.freedesktop.org/git/xorg/driver/xf86-video-ati
> 
> -http://cgit.freedesktop.org/xorg/driver/xf86-video-ati
> +https://cgit.freedesktop.org/xorg/driver/xf86-video-ati
> 
>  For patch submission instructions, see:
> 
> -
>   http://www.x.org/wiki/Development/Documentation/SubmittingPa
> tches
> +
>   https://www.x.org/wiki/Development/Documentation/SubmittingP
> atches
> 
>  For more information on the git code manager, see:
> 
> -http://wiki.x.org/wiki/GitPage
> +https://wiki.x.org/wiki/GitPage
> 
> diff --git a/configure.ac b/configure.ac
> index c9ccfb3dc..700e01a5a 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -24,7 +24,7 @@
>  AC_PREREQ([2.60])
>  AC_INIT([xf86-video-ati],
>  [7.9.99],
> -[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
> +
> [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg&component=Dr
> iver/Radeon],
>  [xf86-video-ati])
> 
>  AC_CONFIG_SRCDIR([Makefile.am])
> diff --git a/man/radeon.man b/man/radeon.man
> index 9334d9e86..3e1723f21 100644
> --- a/man/radeon.man
> +++ b/man/radeon.man
> @@ -392,17 +392,17 @@ __xservername__(__appmansuffix__),
> __xconfigfile__(__filemansuffix__), Xserver(_
>  .IP " 1." 4
>  Wiki page:
>  .RS 4
> -http://www.x.org/wiki/radeon
> +https://www.x.org/wiki/radeon
>  .RE
>  .IP " 2." 4
>  Overview about radeon development code:
>  .RS 4
> -http://cgit.freedesktop.org/xorg/driver/xf86-video-ati/
> +https://cgit.freedesktop.org/xorg/driver/xf86-video-ati/
>  .RE
>  .IP " 3." 4
>  Mailing list:
>  .RS 4
> -http://lists.x.org/mailman/listinfo/xorg-driver-ati
> +https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>  .RE
>  .IP " 4." 4
>  IRC channel:
> --
> 2.11.0
> 
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Huge page support for Vega10

[Christian König]

another round of this patch set, I've dropped all not necessary patches.

Going to handle all the cleanups later on when I have more time to test.

Anyway huge pages now at least not cause any any performance regression any 
more, but they still doesn't seem to have the desired effect speedup effect. I 
probably need to dig deeper into TLB handling.

Additional to that I didn't had time to answer all the questions on the last 
set in detail, going to do so tomorrow.

Regards,
Christian.

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[PATCH 2/7] drm/amdgpu: add some extra VM error handling

[Christian König]

From: Christian König 

If updating the PDs fails we now invalidate all entries to try again later.

Signed-off-by: Christian König 
Reviewed-by: Chunming Zhou 
Reviewed-by: Junwei Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 +-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index c119032..6af2d3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1104,6 +1104,32 @@ static int amdgpu_vm_update_level(struct amdgpu_device 
*adev,
 }
 
 /*
+ * amdgpu_vm_invalidate_level - mark all PD levels as invalid
+ *
+ * @parent: parent PD
+ *
+ * Mark all PD level as invalid after an error.
+ */
+static void amdgpu_vm_invalidate_level(struct amdgpu_vm_pt *parent)
+{
+   unsigned pt_idx;
+
+   /*
+* Recurse into the subdirectories. This recursion is harmless because
+* we only have a maximum of 5 layers.
+*/
+   for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
+   struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
+
+   if (!entry->bo)
+   continue;
+
+   entry->addr = ~0ULL;
+   amdgpu_vm_invalidate_level(entry);
+   }
+}
+
+/*
  * amdgpu_vm_update_directories - make sure that all directories are valid
  *
  * @adev: amdgpu_device pointer
@@ -1115,7 +1141,13 @@ static int amdgpu_vm_update_level(struct amdgpu_device 
*adev,
 int amdgpu_vm_update_directories(struct amdgpu_device *adev,
 struct amdgpu_vm *vm)
 {
-   return amdgpu_vm_update_level(adev, vm, &vm->root, 0);
+   int r;
+
+   r = amdgpu_vm_update_level(adev, vm, &vm->root, 0);
+   if (r)
+   amdgpu_vm_invalidate_level(&vm->root);
+
+   return r;
 }
 
 /**
-- 
2.7.4

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[PATCH 6/7] drm/amdgpu: increase fragmentation size for Vega10

[Christian König]

From: Christian König 

The fragment bits work differently for Vega10 compared to previous generations.

Increase the fragment size to 2MB for now to better handle that.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 5 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 5 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  | 4 +++-
 3 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index f6edf68..83c4d0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -548,8 +548,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
dev_info.virtual_address_max = 
(uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
dev_info.virtual_address_alignment = max((int)PAGE_SIZE, 
AMDGPU_GPU_PAGE_SIZE);
-   dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) *
-AMDGPU_GPU_PAGE_SIZE;
+   dev_info.pte_fragment_size =
+   (1 << AMDGPU_LOG2_PAGES_PER_FRAG(adev)) *
+   AMDGPU_GPU_PAGE_SIZE;
dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 
dev_info.cu_active_number = adev->gfx.cu_info.number;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 062dadc..f7afdfa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1262,8 +1262,9 @@ static int amdgpu_vm_frag_ptes(struct 
amdgpu_pte_update_params*params,
 */
 
/* SI and newer are optimized for 64KB */
-   uint64_t frag_flags = AMDGPU_PTE_FRAG(AMDGPU_LOG2_PAGES_PER_FRAG);
-   uint64_t frag_align = 1 << AMDGPU_LOG2_PAGES_PER_FRAG;
+   unsigned pages_per_frag = AMDGPU_LOG2_PAGES_PER_FRAG(params->adev);
+   uint64_t frag_flags = AMDGPU_PTE_FRAG(pages_per_frag);
+   uint64_t frag_align = 1 << pages_per_frag;
 
uint64_t frag_start = ALIGN(start, frag_align);
uint64_t frag_end = end & ~(frag_align - 1);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 8309bc7..0f83fe3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -51,7 +51,9 @@ struct amdgpu_bo_list_entry;
 #define AMDGPU_VM_PTB_ALIGN_SIZE   32768
 
 /* LOG2 number of continuous pages for the fragment field */
-#define AMDGPU_LOG2_PAGES_PER_FRAG 4
+#define AMDGPU_LOG2_PAGES_PER_FRAG(adev) \
+   ((adev)->asic_type < CHIP_VEGA10 ? 4 : \
+(adev)->vm_manager.block_size)
 
 #define AMDGPU_PTE_VALID   (1ULL << 0)
 #define AMDGPU_PTE_SYSTEM  (1ULL << 1)
-- 
2.7.4

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[PATCH 1/7] drm/amdgpu: cleanup adjust_mc_addr handling v3

[Christian König]

From: Christian König 

Rename adjust_mc_addr to get_vm_pde and check the address bits in one place.

v2: handle vcn as well, keep setting the valid bit manually,
add a BUG_ON() for GMC v6, v7 and v8 as well.
v3: handle vcn_v1_0_enc_ring_emit_vm_flush as well.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  5 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 26 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  6 ++
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c  |  7 +++
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  |  9 -
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  |  9 -
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 10 ++
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |  6 ++
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  | 12 
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c  |  6 ++
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c  | 12 
 11 files changed, 55 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 5f7c408..72f4fad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -309,8 +309,8 @@ struct amdgpu_gart_funcs {
/* set pte flags based per asic */
uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
 uint32_t flags);
-   /* adjust mc addr in fb for APU case */
-   u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr);
+   /* get the pde for a given mc addr */
+   u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr);
uint32_t (*get_invalidate_req)(unsigned int vm_id);
 };
 
@@ -1820,6 +1820,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_asic_get_config_memsize(adev) 
(adev)->asic_funcs->get_config_memsize((adev))
 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) 
(adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) 
(adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
+#define amdgpu_gart_get_vm_pde(adev, addr) 
(adev)->gart.gart_funcs->get_vm_pde((adev), (addr))
 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) 
((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) 
((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), 
(incr)))
 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) 
((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), 
(incr), (flags)))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 3ecde81..c119032 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -682,16 +682,6 @@ static bool amdgpu_vm_ring_has_compute_vm_bug(struct 
amdgpu_ring *ring)
return false;
 }
 
-static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr)
-{
-   u64 addr = mc_addr;
-
-   if (adev->gart.gart_funcs->adjust_mc_addr)
-   addr = adev->gart.gart_funcs->adjust_mc_addr(adev, addr);
-
-   return addr;
-}
-
 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
  struct amdgpu_job *job)
 {
@@ -1033,18 +1023,18 @@ static int amdgpu_vm_update_level(struct amdgpu_device 
*adev,
(count == AMDGPU_VM_MAX_UPDATE_SIZE)) {
 
if (count) {
-   uint64_t pt_addr =
-   amdgpu_vm_adjust_mc_addr(adev, last_pt);
+   uint64_t entry;
 
+   entry = amdgpu_gart_get_vm_pde(adev, last_pt);
if (shadow)
amdgpu_vm_do_set_ptes(¶ms,
  last_shadow,
- pt_addr, count,
+ entry, count,
  incr,
  AMDGPU_PTE_VALID);
 
amdgpu_vm_do_set_ptes(¶ms, last_pde,
- pt_addr, count, incr,
+ entry, count, incr,
  AMDGPU_PTE_VALID);
}
 
@@ -1058,13 +1048,15 @@ static int amdgpu_vm_update_level(struct amdgpu_device 
*adev,
}
 
if (count) {
-   uint64_t pt_addr = amdgpu_vm_adjust_mc_addr(adev, last_pt);
+   uint64_t entry;
+
+   entry = amdgpu_gart_get_vm_pde(adev, last_pt);
 
if (vm->root.bo->shadow)
-   amdgpu_vm_do_set_ptes(¶ms, last_shadow, 

[PATCH 4/7] drm/amdgpu: cache the complete pde

[Christian König]

From: Christian König 

Makes it easier to update the PDE with huge pages.

Signed-off-by: Christian König 
Reviewed-by: Junwei Zhang 
Reviewed-by: Chunming Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 16 +---
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index b2384b8..ecb2814 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1012,6 +1012,7 @@ static int amdgpu_vm_update_level(struct amdgpu_device 
*adev,
}
 
pt = amdgpu_bo_gpu_offset(bo);
+   pt = amdgpu_gart_get_vm_pde(adev, pt);
if (parent->entries[pt_idx].addr == pt)
continue;
 
@@ -1023,18 +1024,15 @@ static int amdgpu_vm_update_level(struct amdgpu_device 
*adev,
(count == AMDGPU_VM_MAX_UPDATE_SIZE)) {
 
if (count) {
-   uint64_t entry;
-
-   entry = amdgpu_gart_get_vm_pde(adev, last_pt);
if (shadow)
amdgpu_vm_do_set_ptes(¶ms,
  last_shadow,
- entry, count,
+ last_pt, count,
  incr,
  AMDGPU_PTE_VALID);
 
amdgpu_vm_do_set_ptes(¶ms, last_pde,
- entry, count, incr,
+ last_pt, count, incr,
  AMDGPU_PTE_VALID);
}
 
@@ -1048,15 +1046,11 @@ static int amdgpu_vm_update_level(struct amdgpu_device 
*adev,
}
 
if (count) {
-   uint64_t entry;
-
-   entry = amdgpu_gart_get_vm_pde(adev, last_pt);
-
if (vm->root.bo->shadow)
-   amdgpu_vm_do_set_ptes(¶ms, last_shadow, entry,
+   amdgpu_vm_do_set_ptes(¶ms, last_shadow, last_pt,
  count, incr, AMDGPU_PTE_VALID);
 
-   amdgpu_vm_do_set_ptes(¶ms, last_pde, entry,
+   amdgpu_vm_do_set_ptes(¶ms, last_pde, last_pt,
  count, incr, AMDGPU_PTE_VALID);
}
 
-- 
2.7.4

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[PATCH 5/7] drm/amdgpu: stop joining VM PTE updates

[Christian König]

From: Christian König 

This isn't beneficial any more since VRAM allocations are now split
so that they fits into a single page table.

Signed-off-by: Christian König 
Reviewed-by: Junwei Zhang 
Reviewed-by: Chunming Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 61 --
 1 file changed, 7 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index ecb2814..062dadc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1190,41 +1190,12 @@ static int amdgpu_vm_update_ptes(struct 
amdgpu_pte_update_params *params,
struct amdgpu_device *adev = params->adev;
const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1;
 
-   uint64_t cur_pe_start, cur_nptes, cur_dst;
-   uint64_t addr; /* next GPU address to be updated */
+   uint64_t addr, pe_start;
struct amdgpu_bo *pt;
-   unsigned nptes; /* next number of ptes to be updated */
-   uint64_t next_pe_start;
-
-   /* initialize the variables */
-   addr = start;
-   pt = amdgpu_vm_get_pt(params, addr);
-   if (!pt) {
-   pr_err("PT not found, aborting update_ptes\n");
-   return -EINVAL;
-   }
-
-   if (params->shadow) {
-   if (!pt->shadow)
-   return 0;
-   pt = pt->shadow;
-   }
-   if ((addr & ~mask) == (end & ~mask))
-   nptes = end - addr;
-   else
-   nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask);
-
-   cur_pe_start = amdgpu_bo_gpu_offset(pt);
-   cur_pe_start += (addr & mask) * 8;
-   cur_nptes = nptes;
-   cur_dst = dst;
-
-   /* for next ptb*/
-   addr += nptes;
-   dst += nptes * AMDGPU_GPU_PAGE_SIZE;
+   unsigned nptes;
 
/* walk over the address space and update the page tables */
-   while (addr < end) {
+   for (addr = start; addr < end; addr += nptes) {
pt = amdgpu_vm_get_pt(params, addr);
if (!pt) {
pr_err("PT not found, aborting update_ptes\n");
@@ -1242,33 +1213,15 @@ static int amdgpu_vm_update_ptes(struct 
amdgpu_pte_update_params *params,
else
nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask);
 
-   next_pe_start = amdgpu_bo_gpu_offset(pt);
-   next_pe_start += (addr & mask) * 8;
-
-   if ((cur_pe_start + 8 * cur_nptes) == next_pe_start &&
-   ((cur_nptes + nptes) <= AMDGPU_VM_MAX_UPDATE_SIZE)) {
-   /* The next ptb is consecutive to current ptb.
-* Don't call the update function now.
-* Will update two ptbs together in future.
-   */
-   cur_nptes += nptes;
-   } else {
-   params->func(params, cur_pe_start, cur_dst, cur_nptes,
-AMDGPU_GPU_PAGE_SIZE, flags);
+   pe_start = amdgpu_bo_gpu_offset(pt);
+   pe_start += (addr & mask) * 8;
 
-   cur_pe_start = next_pe_start;
-   cur_nptes = nptes;
-   cur_dst = dst;
-   }
+   params->func(params, pe_start, dst, nptes,
+AMDGPU_GPU_PAGE_SIZE, flags);
 
-   /* for next ptb*/
-   addr += nptes;
dst += nptes * AMDGPU_GPU_PAGE_SIZE;
}
 
-   params->func(params, cur_pe_start, cur_dst, cur_nptes,
-AMDGPU_GPU_PAGE_SIZE, flags);
-
return 0;
 }
 
-- 
2.7.4

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[PATCH 3/7] drm/amdgpu: Return EINVAL if no PT BO

[Christian König]

From: Harish Kasiviswanathan 

This change is also useful for the upcoming changes where page tables
can be updated by CPU.

Change-Id: I07510ed60c94cf1944ee96bb4b16c40ec88ea17c
Signed-off-by: Harish Kasiviswanathan 
Reviewed-by: Christian König 
Reviewed-by: Junwei Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 48 +-
 1 file changed, 30 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 6af2d3c..b2384b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1187,8 +1187,9 @@ static struct amdgpu_bo *amdgpu_vm_get_pt(struct 
amdgpu_pte_update_params *p,
  * @flags: mapping flags
  *
  * Update the page tables in the range @start - @end.
+ * Returns 0 for success, -EINVAL for failure.
  */
-static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
+static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
  uint64_t start, uint64_t end,
  uint64_t dst, uint64_t flags)
 {
@@ -1206,12 +1207,12 @@ static void amdgpu_vm_update_ptes(struct 
amdgpu_pte_update_params *params,
pt = amdgpu_vm_get_pt(params, addr);
if (!pt) {
pr_err("PT not found, aborting update_ptes\n");
-   return;
+   return -EINVAL;
}
 
if (params->shadow) {
if (!pt->shadow)
-   return;
+   return 0;
pt = pt->shadow;
}
if ((addr & ~mask) == (end & ~mask))
@@ -1233,12 +1234,12 @@ static void amdgpu_vm_update_ptes(struct 
amdgpu_pte_update_params *params,
pt = amdgpu_vm_get_pt(params, addr);
if (!pt) {
pr_err("PT not found, aborting update_ptes\n");
-   return;
+   return -EINVAL;
}
 
if (params->shadow) {
if (!pt->shadow)
-   return;
+   return 0;
pt = pt->shadow;
}
 
@@ -1273,6 +1274,8 @@ static void amdgpu_vm_update_ptes(struct 
amdgpu_pte_update_params *params,
 
params->func(params, cur_pe_start, cur_dst, cur_nptes,
 AMDGPU_GPU_PAGE_SIZE, flags);
+
+   return 0;
 }
 
 /*
@@ -1284,11 +1287,14 @@ static void amdgpu_vm_update_ptes(struct 
amdgpu_pte_update_params *params,
  * @end: last PTE to handle
  * @dst: addr those PTEs should point to
  * @flags: hw mapping flags
+ * Returns 0 for success, -EINVAL for failure.
  */
-static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params*params,
+static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params,
uint64_t start, uint64_t end,
uint64_t dst, uint64_t flags)
 {
+   int r;
+
/**
 * The MC L1 TLB supports variable sized pages, based on a fragment
 * field in the PTE. When this field is set to a non-zero value, page
@@ -1317,28 +1323,30 @@ static void amdgpu_vm_frag_ptes(struct 
amdgpu_pte_update_params *params,
 
/* system pages are non continuously */
if (params->src || !(flags & AMDGPU_PTE_VALID) ||
-   (frag_start >= frag_end)) {
-
-   amdgpu_vm_update_ptes(params, start, end, dst, flags);
-   return;
-   }
+   (frag_start >= frag_end))
+   return amdgpu_vm_update_ptes(params, start, end, dst, flags);
 
/* handle the 4K area at the beginning */
if (start != frag_start) {
-   amdgpu_vm_update_ptes(params, start, frag_start,
- dst, flags);
+   r = amdgpu_vm_update_ptes(params, start, frag_start,
+ dst, flags);
+   if (r)
+   return r;
dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE;
}
 
/* handle the area in the middle */
-   amdgpu_vm_update_ptes(params, frag_start, frag_end, dst,
- flags | frag_flags);
+   r = amdgpu_vm_update_ptes(params, frag_start, frag_end, dst,
+ flags | frag_flags);
+   if (r)
+   return r;
 
/* handle the 4K area at the end */
if (frag_end != end) {
dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE;
-   amdgpu_vm_update_ptes(params, frag_end, end, dst, flags);
+   r = amdgpu_vm_update_ptes(params, frag_end, end, dst, flags);
}
+   return r;
 }
 
 /**
@@ -1459,9 +1467,13 @@ static int amdgpu_vm_bo_update_mapping(struct 
amdgpu_device *adev,
goto error_free;
 
params.shadow = true;
-   amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags);

[PATCH 7/7] drm/amdgpu: enable huge page handling in the VM v2

[Christian König]

From: Christian König 

The hardware can use huge pages to map 2MB of address space with only one PDE.

v2: few cleanups and rebased

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 95 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  4 ++
 2 files changed, 75 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index f7afdfa..f07c9b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -325,6 +325,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device 
*adev,
 
entry->bo = pt;
entry->addr = 0;
+   entry->huge_page = false;
}
 
if (level < adev->vm_manager.num_level) {
@@ -1013,7 +1014,8 @@ static int amdgpu_vm_update_level(struct amdgpu_device 
*adev,
 
pt = amdgpu_bo_gpu_offset(bo);
pt = amdgpu_gart_get_vm_pde(adev, pt);
-   if (parent->entries[pt_idx].addr == pt)
+   if (parent->entries[pt_idx].addr == pt ||
+   parent->entries[pt_idx].huge_page)
continue;
 
parent->entries[pt_idx].addr = pt;
@@ -1145,29 +1147,69 @@ int amdgpu_vm_update_directories(struct amdgpu_device 
*adev,
 }
 
 /**
- * amdgpu_vm_find_pt - find the page table for an address
+ * amdgpu_vm_handle_huge_pages - handle updating the PD with huge pages
  *
  * @p: see amdgpu_pte_update_params definition
  * @addr: virtual address in question
+ * @nptes: number of PTEs updated with this operation
+ * @dst: destination address where the PTEs should point to
+ * @flags: access flags fro the PTEs
+ * @bo: resulting page tables BO
  *
- * Find the page table BO for a virtual address, return NULL when none found.
+ * Check if we can update the PD with a huge page. Also finds the page table
+ * BO for a virtual address, returns -ENOENT when nothing found.
  */
-static struct amdgpu_bo *amdgpu_vm_get_pt(struct amdgpu_pte_update_params *p,
- uint64_t addr)
+static int amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
+  uint64_t addr, unsigned nptes,
+  uint64_t dst, uint64_t flags,
+  struct amdgpu_bo **bo)
 {
-   struct amdgpu_vm_pt *entry = &p->vm->root;
-   unsigned idx, level = p->adev->vm_manager.num_level;
+   unsigned pt_idx, level = p->adev->vm_manager.num_level;
+   struct amdgpu_vm_pt *entry = &p->vm->root, *parent;
+   uint64_t pd_addr, pde;
 
-   while (entry->entries) {
-   idx = addr >> (p->adev->vm_manager.block_size * level--);
-   idx %= amdgpu_bo_size(entry->bo) / 8;
-   entry = &entry->entries[idx];
-   }
+   do {
+   pt_idx = addr >> (p->adev->vm_manager.block_size * level--);
+   pt_idx %= amdgpu_bo_size(entry->bo) / 8;
+   parent = entry;
+   entry = &entry->entries[pt_idx];
+   } while (entry->entries);
 
if (level)
-   return NULL;
+   return -ENOENT;
+
+   *bo = entry->bo;
+
+   /* In the case of a mixed PT the PDE must point to it*/
+   if (p->adev->asic_type < CHIP_VEGA10 ||
+   nptes != AMDGPU_VM_PTE_COUNT(p->adev) ||
+   p->func != amdgpu_vm_do_set_ptes ||
+   !(flags & AMDGPU_PTE_VALID)) {
+
+   dst = amdgpu_bo_gpu_offset(*bo);
+   dst = amdgpu_gart_get_vm_pde(p->adev, dst);
+   flags = AMDGPU_PTE_VALID;
+   } else {
+   flags |= AMDGPU_PDE_PTE;
+   }
 
-   return entry->bo;
+   if (entry->addr == dst &&
+   entry->huge_page == !!(flags & AMDGPU_PDE_PTE))
+   return 0;
+
+   entry->addr = dst;
+   entry->huge_page = !!(flags & AMDGPU_PDE_PTE);
+
+   if (parent->bo->shadow) {
+   pd_addr = amdgpu_bo_gpu_offset(parent->bo->shadow);
+   pde = pd_addr + pt_idx * 8;
+   amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags);
+   }
+
+   pd_addr = amdgpu_bo_gpu_offset(parent->bo);
+   pde = pd_addr + pt_idx * 8;
+   amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags);
+   return 0;
 }
 
 /**
@@ -1193,14 +1235,20 @@ static int amdgpu_vm_update_ptes(struct 
amdgpu_pte_update_params *params,
uint64_t addr, pe_start;
struct amdgpu_bo *pt;
unsigned nptes;
+   int r;
 
/* walk over the address space and update the page tables */
for (addr = start; addr < end; addr += nptes) {
-   pt = amdgpu_vm_get_pt(params, addr);
-   if (!pt) {
-   pr_err("PT not found, aborting update_ptes\n");
-   return -EINVAL;
-   }
+
+   if ((addr & ~mask)

[PATCH] winsys/amdgpu: align VA allocations to fragment size

[Christian König]

From: Christian König 

BOs larger than the minimum fragment size should have their VA
alignet to at least the fragment size for optimal performance.

Signed-off-by: Christian König 
---
 src/amd/common/ac_gpu_info.c  | 1 +
 src/amd/common/ac_gpu_info.h  | 1 +
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 2 ++
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h | 1 +
 4 files changed, 5 insertions(+)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index cf5d6e1..0b4933e 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -281,6 +281,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
sizeof(amdinfo->gb_macro_tile_mode));
 
+   info->pte_fragment_size = alignment_info.size_local;
info->gart_page_size = alignment_info.size_remote;
 
if (info->chip_class == SI)
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index d8029ef..3785eb4 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -45,6 +45,7 @@ struct radeon_info {
uint32_tpci_id;
enum radeon_family  family;
enum chip_class chip_class;
+   uint32_tpte_fragment_size;
uint32_tgart_page_size;
uint64_tgart_size;
uint64_tvram_size;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 6bdcce5..4017411 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -415,6 +415,8 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct 
amdgpu_winsys *ws,
}
 
va_gap_size = ws->check_vm ? MAX2(4 * alignment, 64 * 1024) : 0;
+   if (size > ws->info.pte_fragment_size)
+  alignment = MAX2(alignment, ws->info.pte_fragment_size);
r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general,
  size + va_gap_size, alignment, 0, &va, 
&va_handle, 0);
if (r)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h 
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
index 896a463..88975e2 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
@@ -73,6 +73,7 @@ struct amdgpu_winsys {
 
struct amdgpu_gpu_info amdinfo;
ADDR_HANDLE addrlib;
+   struct amdgpu_buffer_size_alignmentsalignments;
 
bool check_vm;
 
-- 
2.7.4

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Re: [PATCH] drm/amd/amdgpu: Return error if initiating read out of range on vram

[Christian König]

Am 23.05.2017 um 17:59 schrieb Tom St Denis:

If you initiate a read that is out of the VRAM address space return
ENXIO instead of 0.

Reads that begin below that point will read upto the VRAM limit as
before.

Signed-off-by: Tom St Denis 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 522f773203c8..399209495265 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1468,6 +1468,9 @@ static ssize_t amdgpu_ttm_vram_read(struct file *f, char 
__user *buf,
if (size & 0x3 || *pos & 0x3)
return -EINVAL;
  
+	if (*pos >= adev->mc.mc_vram_size)

+   return -ENXIO;
+
while (size) {
unsigned long flags;
uint32_t value;



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RE: [PATCH] drm/amdgpu: add an INFO query for monitoring VRAM CPU page faults

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Marek Olšák
> Sent: Wednesday, May 17, 2017 2:06 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH] drm/amdgpu: add an INFO query for monitoring VRAM
> CPU page faults
> 
> From: Marek Olšák 
> 
> Signed-off-by: Marek Olšák 

Please bump the driver version as well.  With that fixed:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 3 +++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 1 +
>  include/uapi/drm/amdgpu_drm.h  | 2 ++
>  4 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index fadeb55..251e5de 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1525,20 +1525,21 @@ struct amdgpu_device {
> 
>   /* memory management */
>   struct amdgpu_mman  mman;
>   struct amdgpu_vram_scratch  vram_scratch;
>   struct amdgpu_wbwb;
>   atomic64_t  vram_usage;
>   atomic64_t  vram_vis_usage;
>   atomic64_t  gtt_usage;
>   atomic64_t  num_bytes_moved;
>   atomic64_t  num_evictions;
> + atomic64_t  num_vram_cpu_page_faults;
>   atomic_tgpu_reset_counter;
> 
>   /* data for buffer migration throttling */
>   struct {
>   spinlock_t  lock;
>   s64 last_update_us;
>   s64 accum_us; /* accumulated
> microseconds */
>   u32 log2_max_MBps;
>   } mm_stats;
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index d167949..81291d8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -407,20 +407,23 @@ static int amdgpu_info_ioctl(struct drm_device
> *dev, void *data, struct drm_file
> 
>   return copy_to_user(out, &fw_info,
>   min((size_t)size, sizeof(fw_info))) ? -
> EFAULT : 0;
>   }
>   case AMDGPU_INFO_NUM_BYTES_MOVED:
>   ui64 = atomic64_read(&adev->num_bytes_moved);
>   return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
>   case AMDGPU_INFO_NUM_EVICTIONS:
>   ui64 = atomic64_read(&adev->num_evictions);
>   return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
> + case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
> + ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
> + return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
>   case AMDGPU_INFO_VRAM_USAGE:
>   ui64 = atomic64_read(&adev->vram_usage);
>   return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
>   case AMDGPU_INFO_VIS_VRAM_USAGE:
>   ui64 = atomic64_read(&adev->vram_vis_usage);
>   return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
>   case AMDGPU_INFO_GTT_USAGE:
>   ui64 = atomic64_read(&adev->gtt_usage);
>   return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
>   case AMDGPU_INFO_GDS_CONFIG: {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 6bc52cc..b6da86e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -953,20 +953,21 @@ int amdgpu_bo_fault_reserve_notify(struct
> ttm_buffer_object *bo)
>   offset = bo->mem.start << PAGE_SHIFT;
>   /* TODO: figure out how to map scattered VRAM to the CPU */
>   if ((offset + size) <= adev->mc.visible_vram_size)
>   return 0;
> 
>   /* Can't move a pinned BO to visible VRAM */
>   if (abo->pin_count > 0)
>   return -EINVAL;
> 
>   /* hurrah the memory is not visible ! */
> + atomic64_inc(&adev->num_vram_cpu_page_faults);
>   amdgpu_ttm_placement_from_domain(abo,
> AMDGPU_GEM_DOMAIN_VRAM);
>   lpfn =  adev->mc.visible_vram_size >> PAGE_SHIFT;
>   for (i = 0; i < abo->placement.num_placement; i++) {
>   /* Force into visible VRAM */
>   if ((abo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
>   (!abo->placements[i].lpfn ||
>abo->placements[i].lpfn > lpfn))
>   abo->placements[i].lpfn = lpfn;
>   }
>   r = ttm_bo_validate(bo, &abo->placement, false, false);
> diff --git a/include/uapi/drm/amdgpu_drm.h
> b/include/uapi/drm/amdgpu_drm.h
> index c99fe63..4f34394 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -598,20 +598,22 @@ struct drm_amdgpu_cs_chunk_data 

[PATCH] drm/amd/amdgpu: Return error if initiating read out of range on vram

[Tom St Denis]

If you initiate a read that is out of the VRAM address space return
ENXIO instead of 0.

Reads that begin below that point will read upto the VRAM limit as
before.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 522f773203c8..399209495265 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1468,6 +1468,9 @@ static ssize_t amdgpu_ttm_vram_read(struct file *f, char 
__user *buf,
if (size & 0x3 || *pos & 0x3)
return -EINVAL;
 
+   if (*pos >= adev->mc.mc_vram_size)
+   return -ENXIO;
+
while (size) {
unsigned long flags;
uint32_t value;
-- 
2.12.0

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Re: [PATCH 6/6] drm/amd/display: Tidy up mem_input_program_surface_flip_and_addr()

[Harry Wentland]

On 2017-05-23 11:17 AM, Deucher, Alexander wrote:

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Tom St Denis
Sent: Tuesday, May 16, 2017 10:22 AM
To: amd-gfx@lists.freedesktop.org
Cc: StDenis, Tom
Subject: [PATCH 6/6] drm/amd/display: Tidy up
mem_input_program_surface_flip_and_addr()

Signed-off-by: Tom St Denis 


Patches are Acked-by: Alex Deucher 

If Harry is ok with them, please coordinate to pull them through the dal tree.



Thanks, Alex.

Already part of the internal dal tree and on the way for amd-staging-4.9 
as part of today's set of DC patches.


Harry



Alex


---
  .../drm/amd/display/dc/dce120/dce120_mem_input.c   | 27 ---
---
  1 file changed, 9 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
index c0677211bd93..5a7edfd8fbf7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
@@ -195,20 +195,12 @@ static bool
mem_input_program_surface_flip_and_addr(
 * non-XDMA Mode: GRPH_SURFACE_UPDATE_IMMEDIATE_EN = 1
 * XDMA Mode: GRPH_SURFACE_UPDATE_H_RETRACE_EN = 1
 */
-   DCP_REG_UPDATE(DCP0_GRPH_UPDATE,
-   GRPH_UPDATE_LOCK, 1);
-
-   if (flip_immediate) {
-   DCP_REG_UPDATE_2(
-   DCP0_GRPH_FLIP_CONTROL,
-   GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
-   GRPH_SURFACE_UPDATE_H_RETRACE_EN, 1);
-   } else {
-   DCP_REG_UPDATE_2(
-   DCP0_GRPH_FLIP_CONTROL,
-   GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
-   GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
-   }
+   DCP_REG_UPDATE(DCP0_GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
+
+   DCP_REG_UPDATE_2(
+   DCP0_GRPH_FLIP_CONTROL,
+   GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
+   GRPH_SURFACE_UPDATE_H_RETRACE_EN, flip_immediate ?
1 : 0);

switch (address->type) {
case PLN_ADDR_TYPE_GRAPHICS:
@@ -217,8 +209,8 @@ static bool
mem_input_program_surface_flip_and_addr(
program_pri_addr(mem_input110, address->grph.addr);
break;
case PLN_ADDR_TYPE_GRPH_STEREO:
-   if (address->grph_stereo.left_addr.quad_part == 0
-   || address->grph_stereo.right_addr.quad_part == 0)
+   if (address->grph_stereo.left_addr.quad_part == 0 ||
+   address->grph_stereo.right_addr.quad_part == 0)
break;
program_pri_addr(mem_input110, address-

grph_stereo.left_addr);

program_sec_addr(mem_input110, address-

grph_stereo.right_addr);

@@ -234,8 +226,7 @@ static bool
mem_input_program_surface_flip_and_addr(
if (flip_immediate)
mem_input->current_address = *address;

-   DCP_REG_UPDATE(DCP0_GRPH_UPDATE,
-   GRPH_UPDATE_LOCK, 0);
+   DCP_REG_UPDATE(DCP0_GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);

return true;
  }
--
2.12.0

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RE: [PATCH] drm/amdgpu: update golden settings

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Ken Wang
> Sent: Wednesday, May 17, 2017 5:08 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Wang, Ken
> Subject: [PATCH] drm/amdgpu: update golden settings
> 
> Change-Id: Ifcc39748c36273fa764cd2641d4b44405dbf59a5
> Signed-off-by: Ken Wang 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 20 
>  1 file changed, 16 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 39ae97b..de35de2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -86,14 +86,27 @@ static const struct amdgpu_gds_reg_offset
> amdgpu_gds_reg_offset[] =
> 
>  static const u32 golden_settings_gc_9_0[] =
>  {
> - SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00ffeff,
> 0x0400,
> + SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x0800,
> 0x0880,
> + SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x0800,
> 0x0880,
> + SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x0800,
> 0x0880,
> + SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00f, 0x0420,
> + SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x000f,
> 0x,
> + SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x0800,
> 0x0880,
>   SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3),
> 0x0003, 0x82400024,
>   SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fff,
> 0x0001,
>   SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE),
> 0xff0f, 0x,
> + SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0),
> 0x0800, 0x0880,
> + SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1),
> 0x0800, 0x0880,
> + SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2),
> 0x0800, 0x0880,
> + SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL),
> 0x0800, 0x0880,
> + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x0800,
> 0x0880,
> + SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x000f,
> 0x01000107,
>   SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfeef,
> 0x010b,
>   SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0x,
> 0x4a2c0e68,
>   SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0x,
> 0xb5d3f197,
> - SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID),
> 0x0fff, 0x03ff
> + SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION),
> 0x3fff3af3, 0x1920,
> + SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID),
> 0x0fff, 0x03ff,
> + SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x0800,
> 0x0880
>  };
> 
>  static const u32 golden_settings_gc_9_0_vg10[] =
> @@ -104,8 +117,7 @@ static const u32 golden_settings_gc_9_0_vg10[] =
>   SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ),
> 0x77ff, 0x2a114042,
>   SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x8000,
> 0x00048000,
>   SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x0003,
> 0x0002,
> - SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x1800, 0x0800,
> - SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1),0x000f,
> 0x0007
> + SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x1800, 0x0800
>  };
> 
>  #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
> --
> 2.7.4
> 
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RE: [PATCH] gpu: drm: radeon: refactor code

[Deucher, Alexander]

> -Original Message-
> From: Koenig, Christian
> Sent: Wednesday, May 17, 2017 4:23 AM
> To: Gustavo A. R. Silva; Deucher, Alexander; David Airlie
> Cc: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH] gpu: drm: radeon: refactor code
> 
> Am 17.05.2017 um 04:20 schrieb Gustavo A. R. Silva:
> > Local variable _color_ is assigned to a constant value and it is
> > never updated again. Remove this variable and refactor the code it
> > affects.
> >
> > Addresses-Coverity-ID: 1226745
> > Signed-off-by: Gustavo A. R. Silva 
> 
> Mhm, on the one hand it looks like a valid cleanup. On the other that is
> legacy code we haven't touched in a while.
> 
> Feel free to put my Reviewed-by: Christian König
>  on it, but I'm not sure if Alex will pick it up.

It's like that to show how to do color vs. mono load detection.  It's not 
something we supported, but others using the hw may be interested.

Alex

> 
> Regards,
> Christian.
> 
> > ---
> >   drivers/gpu/drm/radeon/radeon_legacy_encoders.c | 8 +---
> >   1 file changed, 1 insertion(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
> b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
> > index 222a1fa..7235d0c 100644
> > --- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
> > +++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
> > @@ -640,7 +640,6 @@ static enum drm_connector_status
> radeon_legacy_primary_dac_detect(struct drm_enc
> > uint32_t vclk_ecp_cntl, crtc_ext_cntl;
> > uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
> > enum drm_connector_status found =
> connector_status_disconnected;
> > -   bool color = true;
> >
> > /* just don't bother on RN50 those chip are often connected to
> remoting
> >  * console hw and often we get failure to load detect those. So to
> make
> > @@ -665,12 +664,7 @@ static enum drm_connector_status
> radeon_legacy_primary_dac_detect(struct drm_enc
> > WREG32(RADEON_CRTC_EXT_CNTL, tmp);
> >
> > tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
> > -   RADEON_DAC_FORCE_DATA_EN;
> > -
> > -   if (color)
> > -   tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
> > -   else
> > -   tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
> > +   RADEON_DAC_FORCE_DATA_EN |
> RADEON_DAC_FORCE_DATA_SEL_RGB;
> >
> > if (ASIC_IS_R300(rdev))
> > tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
> 

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RE: [PATCH xf86-video-amdgpu] Use plain glamor_egl_create_textured_screen().

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Michel Dänzer
> Sent: Wednesday, May 17, 2017 3:16 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH xf86-video-amdgpu] Use plain
> glamor_egl_create_textured_screen().
> 
> From: Eric Anholt 
> 
> Since 5064ffab631 (2014), glamor's implementation of _ext just drops the
> back_pixmap arg, which we were passing NULL (the default) to anyway.
> 
> Signed-off-by: Eric Anholt 
> (Ported from radeon commit 2b7d77b90108911777a11ecaa63435552000c958)
> 
> Signed-off-by: Michel Dänzer 

Reviewed-by: Alex Deucher 

> ---
>  src/amdgpu_glamor.c | 7 +++
>  1 file changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/src/amdgpu_glamor.c b/src/amdgpu_glamor.c
> index 1c5dfc2d1..5583cd382 100644
> --- a/src/amdgpu_glamor.c
> +++ b/src/amdgpu_glamor.c
> @@ -66,10 +66,9 @@ Bool
> amdgpu_glamor_create_screen_resources(ScreenPtr screen)
>  #endif
> 
>   if (!amdgpu_bo_get_handle(info->front_buffer, &bo_handle) ||
> - !glamor_egl_create_textured_screen_ext(screen,
> -bo_handle,
> -scrn->displayWidth *
> -info->pixel_bytes, NULL)) {
> + !glamor_egl_create_textured_screen(screen, bo_handle,
> +scrn->displayWidth *
> +info->pixel_bytes)) {
>   return FALSE;
>   }
> 
> --
> 2.11.0
> 
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Re: [PATCH] drm/amd/display: Limit DCN to x86 arch

[Felix Kuehling]

On 17-05-23 09:37 AM, Harry Wentland wrote:
>
>
> On 2017-05-20 04:13 AM, Christian König wrote:
>> Are you aware of anyone using our GPUs on non-X86 architectures? If
>> so, I never heard of it.
>>
>> Yeah, there are actually quite a number of people. That's one of the
>> reasons why we still have a bunch of "#ifdef __BIG_ENDIAN" in the
>> amdgpu source.
>>
>
> Interesting. I'd love to know more about this, like which platforms,
> etc, since sadly we've been pretty unaware of this.

For ROCm we're working on supporting ARMv8 and Power8. This is for
compute, so mostly headless. Not sure if they would care about display
in the future.

Regards,
  Felix

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Re: [PATCH 2/4] drm/amdgpu: return -ENODEV to user space when vram is lost v2

[Christian König]

Am 23.05.2017 um 17:08 schrieb Deucher, Alexander:

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Chunming Zhou
Sent: Tuesday, May 16, 2017 5:26 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou, David(ChunMing)
Subject: [PATCH 2/4] drm/amdgpu: return -ENODEV to user space when
vram is lost v2

below ioctl will return -ENODEV:
amdgpu_cs_ioctl
amdgpu_cs_wait_ioctl
amdgpu_cs_wait_fences_ioctl
amdgpu_gem_va_ioctl
amdgpu_info_ioctl

Do we want to block the info ioctl?  Isn't that where the lost context query is?


No, that's amdgpu_ctx_ioctl.

But I think the conclusion is that we want to move the vram_lost counter 
to be per CTX and not per device.


Christian.



Alex


v2: only for map and replace cases in amdgpu_gem_va_ioctl

Change-Id: I8970cde3301b7cfeb4263cc0f0e54aece215c98e
Signed-off-by: Chunming Zhou 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  4 
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |  9 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  4 +++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c|  5 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 10 ++
  5 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f9da215..dcd6203 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -855,6 +855,7 @@ struct amdgpu_fpriv {
struct amdgpu_ctx_mgr   ctx_mgr;
spinlock_t  sem_handles_lock;
struct idr  sem_handles;
+   u32 vram_lost_counter;
  };

  /*
@@ -1607,6 +1608,7 @@ struct amdgpu_device {
atomic64_t  num_bytes_moved;
atomic64_t  num_evictions;
atomic_tgpu_reset_counter;
+   atomic_tvram_lost_counter;

/* data for buffer migration throttling */
struct {
@@ -2005,6 +2007,8 @@ static inline void
amdgpu_unregister_atpx_handler(void) {}
  extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
  extern const int amdgpu_max_kms_ioctl;

+bool amdgpu_kms_vram_lost(struct amdgpu_device *adev,
+ struct amdgpu_fpriv *fpriv);
  int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
  int amdgpu_driver_unload_kms(struct drm_device *dev);
  void amdgpu_driver_lastclose_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index b803412..911aa02 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1097,6 +1097,7 @@ static int amdgpu_cs_submit(struct
amdgpu_cs_parser *p,
  int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file
*filp)
  {
struct amdgpu_device *adev = dev->dev_private;
+   struct amdgpu_fpriv *fpriv = filp->driver_priv;
union drm_amdgpu_cs *cs = data;
struct amdgpu_cs_parser parser = {};
bool reserved_buffers = false;
@@ -1104,6 +1105,8 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void
*data, struct drm_file *filp)

if (!adev->accel_working)
return -EBUSY;
+   if (amdgpu_kms_vram_lost(adev, fpriv))
+   return -ENODEV;

parser.adev = adev;
parser.filp = filp;
@@ -1165,12 +1168,15 @@ int amdgpu_cs_wait_ioctl(struct drm_device
*dev, void *data,
  {
union drm_amdgpu_wait_cs *wait = data;
struct amdgpu_device *adev = dev->dev_private;
+   struct amdgpu_fpriv *fpriv = filp->driver_priv;
unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
struct amdgpu_ring *ring = NULL;
struct amdgpu_ctx *ctx;
struct fence *fence;
long r;

+   if (amdgpu_kms_vram_lost(adev, fpriv))
+   return -ENODEV;
r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait-

in.ip_instance,

   wait->in.ring, &ring);
if (r)
@@ -1344,12 +1350,15 @@ int amdgpu_cs_wait_fences_ioctl(struct
drm_device *dev, void *data,
struct drm_file *filp)
  {
struct amdgpu_device *adev = dev->dev_private;
+   struct amdgpu_fpriv *fpriv = filp->driver_priv;
union drm_amdgpu_wait_fences *wait = data;
uint32_t fence_count = wait->in.fence_count;
struct drm_amdgpu_fence *fences_user;
struct drm_amdgpu_fence *fences;
int r;

+   if (amdgpu_kms_vram_lost(adev, fpriv))
+   return -ENODEV;
/* Get the fences from userspace */
fences = kmalloc_array(fence_count, sizeof(struct
drm_amdgpu_fence),
GFP_KERNEL);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c56ae4a..2f0fcf8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -29

RE: [PATCH 6/6] drm/amd/display: Tidy up mem_input_program_surface_flip_and_addr()

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Tuesday, May 16, 2017 10:22 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH 6/6] drm/amd/display: Tidy up
> mem_input_program_surface_flip_and_addr()
> 
> Signed-off-by: Tom St Denis 

Patches are Acked-by: Alex Deucher 

If Harry is ok with them, please coordinate to pull them through the dal tree.

Alex

> ---
>  .../drm/amd/display/dc/dce120/dce120_mem_input.c   | 27 ---
> ---
>  1 file changed, 9 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
> b/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
> index c0677211bd93..5a7edfd8fbf7 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
> @@ -195,20 +195,12 @@ static bool
> mem_input_program_surface_flip_and_addr(
>* non-XDMA Mode: GRPH_SURFACE_UPDATE_IMMEDIATE_EN = 1
>* XDMA Mode: GRPH_SURFACE_UPDATE_H_RETRACE_EN = 1
>*/
> - DCP_REG_UPDATE(DCP0_GRPH_UPDATE,
> - GRPH_UPDATE_LOCK, 1);
> -
> - if (flip_immediate) {
> - DCP_REG_UPDATE_2(
> - DCP0_GRPH_FLIP_CONTROL,
> - GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
> - GRPH_SURFACE_UPDATE_H_RETRACE_EN, 1);
> - } else {
> - DCP_REG_UPDATE_2(
> - DCP0_GRPH_FLIP_CONTROL,
> - GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
> - GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
> - }
> + DCP_REG_UPDATE(DCP0_GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
> +
> + DCP_REG_UPDATE_2(
> + DCP0_GRPH_FLIP_CONTROL,
> + GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
> + GRPH_SURFACE_UPDATE_H_RETRACE_EN, flip_immediate ?
> 1 : 0);
> 
>   switch (address->type) {
>   case PLN_ADDR_TYPE_GRAPHICS:
> @@ -217,8 +209,8 @@ static bool
> mem_input_program_surface_flip_and_addr(
>   program_pri_addr(mem_input110, address->grph.addr);
>   break;
>   case PLN_ADDR_TYPE_GRPH_STEREO:
> - if (address->grph_stereo.left_addr.quad_part == 0
> - || address->grph_stereo.right_addr.quad_part == 0)
> + if (address->grph_stereo.left_addr.quad_part == 0 ||
> + address->grph_stereo.right_addr.quad_part == 0)
>   break;
>   program_pri_addr(mem_input110, address-
> >grph_stereo.left_addr);
>   program_sec_addr(mem_input110, address-
> >grph_stereo.right_addr);
> @@ -234,8 +226,7 @@ static bool
> mem_input_program_surface_flip_and_addr(
>   if (flip_immediate)
>   mem_input->current_address = *address;
> 
> - DCP_REG_UPDATE(DCP0_GRPH_UPDATE,
> - GRPH_UPDATE_LOCK, 0);
> + DCP_REG_UPDATE(DCP0_GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
> 
>   return true;
>  }
> --
> 2.12.0
> 
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RE: [PATCH 2/4] drm/amdgpu: return -ENODEV to user space when vram is lost v2

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Chunming Zhou
> Sent: Tuesday, May 16, 2017 5:26 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhou, David(ChunMing)
> Subject: [PATCH 2/4] drm/amdgpu: return -ENODEV to user space when
> vram is lost v2
> 
> below ioctl will return -ENODEV:
> amdgpu_cs_ioctl
> amdgpu_cs_wait_ioctl
> amdgpu_cs_wait_fences_ioctl
> amdgpu_gem_va_ioctl
> amdgpu_info_ioctl

Do we want to block the info ioctl?  Isn't that where the lost context query is?

Alex

> 
> v2: only for map and replace cases in amdgpu_gem_va_ioctl
> 
> Change-Id: I8970cde3301b7cfeb4263cc0f0e54aece215c98e
> Signed-off-by: Chunming Zhou 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  4 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |  9 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  4 +++-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c|  5 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 10 ++
>  5 files changed, 31 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index f9da215..dcd6203 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -855,6 +855,7 @@ struct amdgpu_fpriv {
>   struct amdgpu_ctx_mgr   ctx_mgr;
>   spinlock_t  sem_handles_lock;
>   struct idr  sem_handles;
> + u32 vram_lost_counter;
>  };
> 
>  /*
> @@ -1607,6 +1608,7 @@ struct amdgpu_device {
>   atomic64_t  num_bytes_moved;
>   atomic64_t  num_evictions;
>   atomic_tgpu_reset_counter;
> + atomic_tvram_lost_counter;
> 
>   /* data for buffer migration throttling */
>   struct {
> @@ -2005,6 +2007,8 @@ static inline void
> amdgpu_unregister_atpx_handler(void) {}
>  extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
>  extern const int amdgpu_max_kms_ioctl;
> 
> +bool amdgpu_kms_vram_lost(struct amdgpu_device *adev,
> +   struct amdgpu_fpriv *fpriv);
>  int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
>  int amdgpu_driver_unload_kms(struct drm_device *dev);
>  void amdgpu_driver_lastclose_kms(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index b803412..911aa02 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -1097,6 +1097,7 @@ static int amdgpu_cs_submit(struct
> amdgpu_cs_parser *p,
>  int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file
> *filp)
>  {
>   struct amdgpu_device *adev = dev->dev_private;
> + struct amdgpu_fpriv *fpriv = filp->driver_priv;
>   union drm_amdgpu_cs *cs = data;
>   struct amdgpu_cs_parser parser = {};
>   bool reserved_buffers = false;
> @@ -1104,6 +1105,8 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void
> *data, struct drm_file *filp)
> 
>   if (!adev->accel_working)
>   return -EBUSY;
> + if (amdgpu_kms_vram_lost(adev, fpriv))
> + return -ENODEV;
> 
>   parser.adev = adev;
>   parser.filp = filp;
> @@ -1165,12 +1168,15 @@ int amdgpu_cs_wait_ioctl(struct drm_device
> *dev, void *data,
>  {
>   union drm_amdgpu_wait_cs *wait = data;
>   struct amdgpu_device *adev = dev->dev_private;
> + struct amdgpu_fpriv *fpriv = filp->driver_priv;
>   unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
>   struct amdgpu_ring *ring = NULL;
>   struct amdgpu_ctx *ctx;
>   struct fence *fence;
>   long r;
> 
> + if (amdgpu_kms_vram_lost(adev, fpriv))
> + return -ENODEV;
>   r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait-
> >in.ip_instance,
>  wait->in.ring, &ring);
>   if (r)
> @@ -1344,12 +1350,15 @@ int amdgpu_cs_wait_fences_ioctl(struct
> drm_device *dev, void *data,
>   struct drm_file *filp)
>  {
>   struct amdgpu_device *adev = dev->dev_private;
> + struct amdgpu_fpriv *fpriv = filp->driver_priv;
>   union drm_amdgpu_wait_fences *wait = data;
>   uint32_t fence_count = wait->in.fence_count;
>   struct drm_amdgpu_fence *fences_user;
>   struct drm_amdgpu_fence *fences;
>   int r;
> 
> + if (amdgpu_kms_vram_lost(adev, fpriv))
> + return -ENODEV;
>   /* Get the fences from userspace */
>   fences = kmalloc_array(fence_count, sizeof(struct
> drm_amdgpu_fence),
>   GFP_KERNEL);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index c56ae4a..2f0fcf8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2913,8 +2913,10 @@ int amdgpu_gpu_reset(struct amdgpu_device
> *adev)
> 

RE: [PATCH 2/2] drm/amd/amdgpu: Clean up gmc6 wait_for_idle

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Monday, May 15, 2017 2:26 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH 2/2] drm/amd/amdgpu: Clean up gmc6 wait_for_idle
> 
> Signed-off-by: Tom St Denis 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 8 +---
>  1 file changed, 1 insertion(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index 81f5aa9ff719..27db0710e9ab 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -984,16 +984,10 @@ static bool gmc_v6_0_is_idle(void *handle)
>  static int gmc_v6_0_wait_for_idle(void *handle)
>  {
>   unsigned i;
> - uint32_t tmp;
>   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
>   for (i = 0; i < adev->usec_timeout; i++) {
> - tmp = RREG32(mmSRBM_STATUS) &
> (SRBM_STATUS__MCB_BUSY_MASK |
> -
> SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
> -
> SRBM_STATUS__MCC_BUSY_MASK |
> -
> SRBM_STATUS__MCD_BUSY_MASK |
> -
> SRBM_STATUS__VMC_BUSY_MASK);
> - if (!tmp)
> + if (gmc_v6_0_is_idle(handle))
>   return 0;
>   udelay(1);
>   }
> --
> 2.12.0
> 
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RE: [PATCH 2/2] drm/amd/amdgpu: Tidy up static int dce_v6_0_get_num_crtc()

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Monday, May 15, 2017 10:58 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH 2/2] drm/amd/amdgpu: Tidy up static int
> dce_v6_0_get_num_crtc()
> 
> Signed-off-by: Tom St Denis 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 11 +++
>  1 file changed, 3 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index 1b6b9b22d780..ec7f7bb77f50 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -514,21 +514,16 @@ static void dce_v6_0_set_vga_render_state(struct
> amdgpu_device *adev,
> 
>  static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev)
>  {
> - int num_crtc = 0;
> -
>   switch (adev->asic_type) {
>   case CHIP_TAHITI:
>   case CHIP_PITCAIRN:
>   case CHIP_VERDE:
> - num_crtc = 6;
> - break;
> + return 6;
>   case CHIP_OLAND:
> - num_crtc = 2;
> - break;
> + return 2;
>   default:
> - num_crtc = 0;
> + return 0;
>   }
> - return num_crtc;
>  }
> 
>  void dce_v6_0_disable_dce(struct amdgpu_device *adev)
> --
> 2.12.0
> 
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Re: [PATCH 5/5] drm/amd/amdgpu: Use modern 32/64-bit types in gfx6

[Tom St Denis]

On 23/05/17 10:28 AM, Deucher, Alexander wrote:

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Tom St Denis
Sent: Monday, May 15, 2017 9:49 AM
To: amd-gfx@lists.freedesktop.org
Cc: StDenis, Tom
Subject: [PATCH 5/5] drm/amd/amdgpu: Use modern 32/64-bit types in gfx6

Switch to uintNN_t from "uNN" types to be more consistent
with modern coding styles.


I think technically the uNN types are native for the kernel.  the c99 
types are just for convenience.  Seems like a lot of churn to me.


Alex


Fair enough but amdgpu is littered with files that use one or the other 
or sometimes both.  :-)


I agree it's low priority which is why I was attacking the lesser active 
SI code :-)


Though I'm not offended if they're NAK'ed either way.

Cheers,
Tom
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RE: [PATCH 1/5] drm/amd/amdgpu: Clean up GFX6 tilemode programming

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Monday, May 15, 2017 9:49 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH 1/5] drm/amd/amdgpu: Clean up GFX6 tilemode
> programming
> 
> Signed-off-by: Tom St Denis 

Patches 1-4 are:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 1556 ++-
> --
>  1 file changed, 676 insertions(+), 880 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 5d9e95bcd011..36a70e93b293 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -393,8 +393,11 @@ static int gfx_v6_0_init_microcode(struct
> amdgpu_device *adev)
> 
>  static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
>  {
> - const u32 num_tile_mode_states = 32;
> - u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
> + const u32 num_tile_mode_states = ARRAY_SIZE(adev-
> >gfx.config.tile_mode_array);
> + u32 reg_offset, split_equal_to_row_size, *tilemode;
> +
> + memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev-
> >gfx.config.tile_mode_array));
> + tilemode = adev->gfx.config.tile_mode_array;
> 
>   switch (adev->gfx.config.mem_row_size_in_kb) {
>   case 1:
> @@ -410,887 +413,680 @@ static void
> gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
>   }
> 
>   if (adev->asic_type == CHIP_VERDE) {
> - for (reg_offset = 0; reg_offset < num_tile_mode_states;
> reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 1:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 2:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 3:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_8_BANK) |
> -
> TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 4:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16));
> - break;
> - case 5:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 6:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 7:
> - gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> -
> T

RE: [PATCH 5/5] drm/amd/amdgpu: Use modern 32/64-bit types in gfx6

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Monday, May 15, 2017 9:49 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH 5/5] drm/amd/amdgpu: Use modern 32/64-bit types in gfx6
> 
> Switch to uintNN_t from "uNN" types to be more consistent
> with modern coding styles.

I think technically the uNN types are native for the kernel.  the c99 types are 
just for convenience.  Seems like a lot of churn to me.

Alex

> 
> Signed-off-by: Tom St Denis 
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 150 +--
> ---
>  1 file changed, 75 insertions(+), 75 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 1351f9230fcd..a6c88f98df08 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -68,8 +68,8 @@ MODULE_FIRMWARE("radeon/hainan_me.bin");
>  MODULE_FIRMWARE("radeon/hainan_ce.bin");
>  MODULE_FIRMWARE("radeon/hainan_rlc.bin");
> 
> -static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
> -static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile
> u32 *buffer);
> +static uint32_t gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
> +static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile
> uint32_t *buffer);
>  //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
>  static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
> 
> @@ -83,7 +83,7 @@ static void gfx_v6_0_init_pg(struct amdgpu_device
> *adev);
>  #define MACRO_TILE_ASPECT(x) ((x) << 18)
>  #define NUM_BANKS(x) ((x) << 20)
> 
> -static const u32 verde_rlc_save_restore_register_list[] =
> +static const uint32_t verde_rlc_save_restore_register_list[] =
>  {
>   (0x8000 << 16) | (0x98f4 >> 2),
>   0x,
> @@ -393,8 +393,8 @@ static int gfx_v6_0_init_microcode(struct
> amdgpu_device *adev)
> 
>  static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
>  {
> - const u32 num_tile_mode_states = ARRAY_SIZE(adev-
> >gfx.config.tile_mode_array);
> - u32 reg_offset, split_equal_to_row_size, *tilemode;
> + const uint32_t num_tile_mode_states = ARRAY_SIZE(adev-
> >gfx.config.tile_mode_array);
> + uint32_t reg_offset, split_equal_to_row_size, *tilemode;
> 
>   memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev-
> >gfx.config.tile_mode_array));
>   tilemode = adev->gfx.config.tile_mode_array;
> @@ -1089,10 +1089,10 @@ static void
> gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
>   }
>  }
> 
> -static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32
> se_num,
> -   u32 sh_num, u32 instance)
> +static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, uint32_t
> se_num,
> +   uint32_t sh_num, uint32_t instance)
>  {
> - u32 data;
> + uint32_t data;
> 
>   if (instance == 0x)
>   data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
> INSTANCE_BROADCAST_WRITES, 1);
> @@ -1114,14 +1114,14 @@ static void gfx_v6_0_select_se_sh(struct
> amdgpu_device *adev, u32 se_num,
>   WREG32(mmGRBM_GFX_INDEX, data);
>  }
> 
> -static u32 gfx_v6_0_create_bitmask(u32 bit_width)
> +static uint32_t gfx_v6_0_create_bitmask(uint32_t bit_width)
>  {
> - return (u32)(((u64)1 << bit_width) - 1);
> + return (uint32_t)(((uint64_t)1 << bit_width) - 1);
>  }
> 
> -static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
> +static uint32_t gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device
> *adev)
>  {
> - u32 data, mask;
> + uint32_t data, mask;
> 
>   data = RREG32(mmCC_RB_BACKEND_DISABLE) |
>   RREG32(mmGC_USER_RB_BACKEND_DISABLE);
> @@ -1134,7 +1134,7 @@ static u32 gfx_v6_0_get_rb_active_bitmap(struct
> amdgpu_device *adev)
>   return ~data & mask;
>  }
> 
> -static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32
> *rconf)
> +static void gfx_v6_0_raster_config(struct amdgpu_device *adev, uint32_t
> *rconf)
>  {
>   switch (adev->asic_type) {
>   case CHIP_TAHITI:
> @@ -1167,7 +1167,7 @@ static void gfx_v6_0_raster_config(struct
> amdgpu_device *adev, u32 *rconf)
>  }
> 
>  static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device
> *adev,
> - u32 raster_config, unsigned
> rb_mask,
> + uint32_t raster_config,
> unsigned rb_mask,
>   unsigned num_rb)
>  {
>   unsigned sh_per_se = max_t(unsigned, adev-
> >gfx.config.max_sh_per_se, 1);
> @@ -1259,10 +1259,10 @@ static void
> gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
>  static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
>  {
>   int i, j;
> - u32 data;
> - u

[PATCH 27/31] drm/amd/display: fix YUV surface address programming sequence

[Harry Wentland]

From: Tony Cheng 

need to program DCSURF_PRIMARY_SURFACE_ADDRESS last as HW automatically
latch rest of addr regs on write when SURFACE_UPDATE_LOCK is not used

Change-Id: I9284f3cebd02ed3c25c844bc14a95ecc45b1d123
Signed-off-by: Tony Cheng 
Reviewed-by: Yongqiang Sun 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 42 +++---
 1 file changed, 20 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
index 587ded13140b..a52c614ec5b4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
@@ -237,16 +237,23 @@ static bool mem_input_program_surface_flip_and_addr(
struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
 
/* program flip type */
-
REG_UPDATE(DCSURF_FLIP_CONTROL,
SURFACE_FLIP_TYPE, flip_immediate);
 
-   /* REG_UPDATE(FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1); */
-
-
-   /* program high first and then the low addr, order matters! */
+   /* HW automatically latch rest of address register on write to
+* DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
+*
+* program high first and then the low addr, order matters!
+*/
switch (address->type) {
case PLN_ADDR_TYPE_GRAPHICS:
+   /* DCN1.0 does not support const color
+* TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
+* base on address->grph.dcc_const_color
+* x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
+* x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
+*/
+
if (address->grph.addr.quad_part == 0)
break;
 
@@ -268,14 +275,6 @@ static bool mem_input_program_surface_flip_and_addr(
REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
PRIMARY_SURFACE_ADDRESS,
address->grph.addr.low_part);
-
-
-   /* DCN1.0 does not support const color
-* TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
-* base on address->grph.dcc_const_color
-* x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
-* x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
-*/
break;
case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
if (address->video_progressive.luma_addr.quad_part == 0
@@ -301,14 +300,6 @@ static bool mem_input_program_surface_flip_and_addr(

address->video_progressive.chroma_meta_addr.low_part);
}
 
-   REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
-   PRIMARY_SURFACE_ADDRESS_HIGH,
-   address->video_progressive.luma_addr.high_part);
-
-   REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
-   PRIMARY_SURFACE_ADDRESS,
-   address->video_progressive.luma_addr.low_part);
-
REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C,
PRIMARY_SURFACE_ADDRESS_HIGH_C,
address->video_progressive.chroma_addr.high_part);
@@ -317,6 +308,14 @@ static bool mem_input_program_surface_flip_and_addr(
PRIMARY_SURFACE_ADDRESS_C,
address->video_progressive.chroma_addr.low_part);
 
+   REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
+   PRIMARY_SURFACE_ADDRESS_HIGH,
+   address->video_progressive.luma_addr.high_part);
+
+   REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
+   PRIMARY_SURFACE_ADDRESS,
+   address->video_progressive.luma_addr.low_part);
+
break;
case PLN_ADDR_TYPE_GRPH_STEREO:
if (address->grph_stereo.left_addr.quad_part == 0)
@@ -365,7 +364,6 @@ static bool mem_input_program_surface_flip_and_addr(
BREAK_TO_DEBUGGER();
break;
}
-   /* REG_UPDATE(FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0); */
 
mem_input->request_address = *address;
 
-- 
2.11.0

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[PATCH 20/31] drm/amd/display: Fix indentation in dce120_tg_program_timing()

[Harry Wentland]

From: Tom St Denis 

Change-Id: I8f7cb2a366d112414fe4058affe36b14b38e7105
Signed-off-by: Tom St Denis 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 13cc0d49e007..1c25dc66ff4f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -733,9 +733,9 @@ void dce120_tg_program_timing(struct timing_generator *tg,
bool use_vbios)
 {
if (use_vbios)
-   dce110_timing_generator_program_timing_generator(tg, 
timing);
-   else
-   dce120_timing_generator_program_blanking(tg, timing);
+   dce110_timing_generator_program_timing_generator(tg, timing);
+   else
+   dce120_timing_generator_program_blanking(tg, timing);
 }
 
 bool dce120_tg_is_blanked(struct timing_generator *tg)
-- 
2.11.0

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[PATCH 30/31] drm/amd/display: Remove unused addr var in TG

[Harry Wentland]

Change-Id: I3a2032942816f66fc8a89ea0911d3cac3d187d19
Signed-off-by: Harry Wentland 
Reviewed-by: Sun peng Li 
Reviewed-by: Roman Li 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index c208196864ad..03b21e9a1156 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -386,34 +386,27 @@ bool dce120_timing_generator_did_triggered_reset_occur(
 /* Move to enable accelerated mode */
 void dce120_timing_generator_disable_vga(struct timing_generator *tg)
 {
-   uint32_t addr = 0;
uint32_t offset = 0;
uint32_t value = 0;
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
 
switch (tg110->controller_id) {
case CONTROLLER_ID_D0:
-   addr = mmD1VGA_CONTROL;
offset = 0;
break;
case CONTROLLER_ID_D1:
-   addr = mmD2VGA_CONTROL;
offset = mmD2VGA_CONTROL - mmD1VGA_CONTROL;
break;
case CONTROLLER_ID_D2:
-   addr = mmD3VGA_CONTROL;
offset = mmD3VGA_CONTROL - mmD1VGA_CONTROL;
break;
case CONTROLLER_ID_D3:
-   addr = mmD4VGA_CONTROL;
offset = mmD4VGA_CONTROL - mmD1VGA_CONTROL;
break;
case CONTROLLER_ID_D4:
-   addr = mmD1VGA_CONTROL;
offset = mmD5VGA_CONTROL - mmD1VGA_CONTROL;
break;
case CONTROLLER_ID_D5:
-   addr = mmD6VGA_CONTROL;
offset = mmD6VGA_CONTROL - mmD1VGA_CONTROL;
break;
default:
-- 
2.11.0

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[PATCH 08/31] drm/amd/display: Fix dcn10 cursor set position hang

[Harry Wentland]

From: "Leo (Sunpeng) Li" 

Calling dcn10_cursor_set_position() before dcn10_cursor_set_attributes()
with invalid (0-value) attributes can cause the ASIC to hang. This fix
checks that address.quadpart is non-zero within set_position before calling
set_attributes.

Change-Id: I89d45b5e66b60bb936c02b97bcec36ff8c10465c
Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Harry Wentland 
Reviewed-by: Tony Cheng 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
index 3062b7de4fe2..082c98c11293 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
@@ -614,6 +614,16 @@ static void dcn10_cursor_set_position(
uint32_t cur_en = pos->enable ? 1 : 0;
uint32_t dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
 
+   /*
+* Guard aganst cursor_set_position() from being called with invalid
+* attributes
+*
+* TODO: Look at combining cursor_set_position() and
+* cursor_set_attributes() into cursor_update()
+*/
+   if (ippn10->curs_attr.address.quad_part == 0)
+   return;
+
dst_x_offset *= param->ref_clk_khz;
dst_x_offset /= param->pixel_clk_khz;
 
-- 
2.11.0

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[PATCH 25/31] drm/amd/display: Query for update plane type.

[Harry Wentland]

From: Andrey Grodzovsky 

Use DC interface to query for plane update type
so in case of FULL update you flush any outstanding
commits.

Change-Id: If9104ba3072f115a2fe2fe1e86882b1a8b07bb5e
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Harry Wentland 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 69 +-
 1 file changed, 68 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index ab6a969743a0..74981c24d6a6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -3048,6 +3048,61 @@ static uint32_t remove_from_val_sets(
return set_count;
 }
 
+
+static enum surface_update_type  amdgpu_dm_check_surfaces_update_type(
+   struct dc *dc,
+   const struct dc_surface **new_surfaces,
+   uint8_t new_surface_count,
+   const struct dc_stream *dc_stream)
+{
+   struct dc_surface_update srf_updates[MAX_SURFACES];
+   struct dc_flip_addrs flip_addr[MAX_SURFACES];
+   struct dc_plane_info plane_info[MAX_SURFACES];
+   struct dc_scaling_info scaling_info[MAX_SURFACES];
+   int i;
+   const struct dc_stream_status *stream_status =
+   dc_stream_get_status(dc_stream);
+   enum surface_update_type update_type;
+
+   ASSERT(stream_status);
+
+
+   memset(srf_updates, 0, sizeof(srf_updates));
+   memset(flip_addr, 0, sizeof(flip_addr));
+   memset(plane_info, 0, sizeof(plane_info));
+   memset(scaling_info, 0, sizeof(scaling_info));
+
+   for (i = 0; i < new_surface_count; i++) {
+   srf_updates[i].surface = new_surfaces[i];
+   srf_updates[i].gamma =
+   (struct dc_gamma *)new_surfaces[i]->gamma_correction;
+   flip_addr[i].address = new_surfaces[i]->address;
+   flip_addr[i].flip_immediate = new_surfaces[i]->flip_immediate;
+   plane_info[i].color_space = new_surfaces[i]->color_space;
+   plane_info[i].format = new_surfaces[i]->format;
+   plane_info[i].plane_size = new_surfaces[i]->plane_size;
+   plane_info[i].rotation = new_surfaces[i]->rotation;
+   plane_info[i].horizontal_mirror = 
new_surfaces[i]->horizontal_mirror;
+   plane_info[i].stereo_format = new_surfaces[i]->stereo_format;
+   plane_info[i].tiling_info = new_surfaces[i]->tiling_info;
+   plane_info[i].visible = new_surfaces[i]->visible;
+   plane_info[i].dcc = new_surfaces[i]->dcc;
+   scaling_info[i].scaling_quality = 
new_surfaces[i]->scaling_quality;
+   scaling_info[i].src_rect = new_surfaces[i]->src_rect;
+   scaling_info[i].dst_rect = new_surfaces[i]->dst_rect;
+   scaling_info[i].clip_rect = new_surfaces[i]->clip_rect;
+
+   srf_updates[i].flip_addr = &flip_addr[i];
+   srf_updates[i].plane_info = &plane_info[i];
+   srf_updates[i].scaling_info = &scaling_info[i];
+   }
+
+   update_type = dc_check_update_surfaces_for_stream(
+   dc, srf_updates, new_surface_count, NULL, 
stream_status);
+
+   return update_type;
+}
+
 int amdgpu_dm_atomic_check(struct drm_device *dev,
struct drm_atomic_state *state)
 {
@@ -3292,13 +3347,25 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
surface);
 
need_to_validate = true;
-   wait_for_prev_commits = true;
}
}
}
 
context = dc_get_validate_context(dc, set, set_count);
 
+   for (i = 0; i < set_count; i++) {
+   for (j = 0; j < set[i].surface_count; j++) {
+   if (amdgpu_dm_check_surfaces_update_type(
+   dc,
+   set[i].surfaces,
+   set[i].surface_count,
+   set[i].stream) > UPDATE_TYPE_MED) {
+   wait_for_prev_commits = true;
+   break;
+   }
+   }
+   }
+
if (need_to_validate == false || set_count == 0 || context) {
 
ret = 0;
-- 
2.11.0

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[PATCH 26/31] drm/amd/display: Remove redundant condition.

[Harry Wentland]

From: Andrey Grodzovsky 

You cannot have modeset and flip in the same call for
same CRTC, in such case it will be set mode and set plane,
not a flip.

Change-Id: If7e7ef4a62dfc1c62b2a3fef63a4a6316d0155d3
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Andrey Grodzovsky 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 8 +---
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 74981c24d6a6..5d34ce6c7faf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -3296,15 +3296,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 
action = get_dm_commit_action(crtc->state);
 
-   /* Surfaces are created under two scenarios:
-* 1. This commit is not a page flip.
-* 2. This commit is a page flip, and streams are 
created.
-*/
crtc_state = drm_atomic_get_crtc_state(state, crtc);
pflip_needed = !state->allow_modeset;
-   if (!pflip_needed ||
-   action == DM_COMMIT_ACTION_DPMS_ON ||
-   action == DM_COMMIT_ACTION_SET) {
+   if (!pflip_needed) {
struct dc_surface *surface;
 
list_for_each_entry(connector,
-- 
2.11.0

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[PATCH 31/31] drm/amd/display: No need to assert on stream_status

[Harry Wentland]

This will be NULL on a new stream. DC handles it gracefully.

Signed-off-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 5d34ce6c7faf..7182425bbcc2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -3064,9 +3064,6 @@ static enum surface_update_type  
amdgpu_dm_check_surfaces_update_type(
dc_stream_get_status(dc_stream);
enum surface_update_type update_type;
 
-   ASSERT(stream_status);
-
-
memset(srf_updates, 0, sizeof(srf_updates));
memset(flip_addr, 0, sizeof(flip_addr));
memset(plane_info, 0, sizeof(plane_info));
-- 
2.11.0

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[PATCH 22/31] drm/amd/display: Clean up indentation in dce120_tg_set_blank()

[Harry Wentland]

From: Tom St Denis 

Change-Id: Ib2f7b1a4c55033028b88351e8d278cfb77b71c4d
Signed-off-by: Tom St Denis 
Reviewed-by: Harry Wentland 
---
 .../drm/amd/display/dc/dce120/dce120_timing_generator.c  | 16 +---
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 1e2843e5d97e..c208196864ad 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -768,17 +768,11 @@ void dce120_tg_set_blank(struct timing_generator *tg,
CRTC0_CRTC_DOUBLE_BUFFER_CONTROL,
CRTC_BLANK_DATA_DOUBLE_BUFFER_EN, 0);
 
-   if (enable_blanking) {
-   CRTC_REG_SET(
-   CRTC0_CRTC_BLANK_CONTROL,
-   CRTC_BLANK_DATA_EN, 1);
-
-   } else
-   dm_write_reg_soc15(
-   tg->ctx,
-   mmCRTC0_CRTC_BLANK_CONTROL,
-   tg110->offsets.crtc,
-   0);
+   if (enable_blanking)
+   CRTC_REG_SET(CRTC0_CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
+   else
+   dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_BLANK_CONTROL,
+   tg110->offsets.crtc, 0);
 }
 
 bool dce120_tg_validate_timing(struct timing_generator *tg,
-- 
2.11.0

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[PATCH 28/31] drm/amd/display: remove GRPH_SURFACE_UPDATE_IMMEDIATE_EN field programming

[Harry Wentland]

From: Dmytro Laktyushkin 

This is causing asserts for dce 8 and 10 since they do not contain this
field. It is also unnecessary for later DCEs as it is left in it's
default state of 0

Change-Id: Icdc977f8f1990065d3762efda5dd85224d9c534b
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 7 +--
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 2 --
 2 files changed, 1 insertion(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 673371e5f9f0..157f4e1680e3 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -621,15 +621,10 @@ static bool dce_mi_program_surface_flip_and_addr(
 {
struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mem_input);
 
-   /* TODO: Figure out if two modes are needed:
-* non-XDMA Mode: GRPH_SURFACE_UPDATE_IMMEDIATE_EN = 1
-* XDMA Mode: GRPH_SURFACE_UPDATE_H_RETRACE_EN = 1
-*/
REG_UPDATE(GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
 
-   REG_UPDATE_2(
+   REG_UPDATE(
GRPH_FLIP_CONTROL,
-   GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
GRPH_SURFACE_UPDATE_H_RETRACE_EN, flip_immediate ? 1 : 0);
 
switch (address->type) {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index 9d083cd79b4c..05d39c0cbe87 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -162,7 +162,6 @@ struct dce_mem_input_registers {
SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh)
 
 #define MI_DCP_DCE11_MASK_SH_LIST(mask_sh, blk)\
-   SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN, mask_sh),\
SFB(blk, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, 
GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, mask_sh)
 
 #define MI_DCP_PTE_MASK_SH_LIST(mask_sh, blk)\
@@ -278,7 +277,6 @@ struct dce_mem_input_registers {
type GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; \
type GRPH_PRIMARY_SURFACE_ADDRESS; \
type GRPH_SURFACE_UPDATE_PENDING; \
-   type GRPH_SURFACE_UPDATE_IMMEDIATE_EN; \
type GRPH_SURFACE_UPDATE_H_RETRACE_EN; \
type GRPH_UPDATE_LOCK; \
type PIXEL_DURATION; \
-- 
2.11.0

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[PATCH 19/31] drm/amd/display: Tidy up dce120_timing_generator_enable_advanced_request()

[Harry Wentland]

From: Tom St Denis 

Simplify the function by removing identical looking code blocks.

Change-Id: Ibaad41529f5657189599328493d12d951de1e304
Signed-off-by: Tom St Denis 
Reviewed-by: Harry Wentland 
---
 .../display/dc/dce120/dce120_timing_generator.c| 37 +++---
 1 file changed, 12 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index dc8eeac6ac96..13cc0d49e007 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -669,36 +669,23 @@ void dce120_timing_generator_enable_advanced_request(
mmCRTC0_CRTC_START_LINE_CONTROL,
tg110->offsets.crtc);
 
-
-   if (enable) {
-   set_reg_field_value(
-   value,
-   0,
-   CRTC0_CRTC_START_LINE_CONTROL,
-   CRTC_LEGACY_REQUESTOR_EN);
-   } else {
-   set_reg_field_value(
-   value,
-   1,
-   CRTC0_CRTC_START_LINE_CONTROL,
-   CRTC_LEGACY_REQUESTOR_EN);
-   }
+   set_reg_field_value(
+   value,
+   enable ? 0 : 1,
+   CRTC0_CRTC_START_LINE_CONTROL,
+   CRTC_LEGACY_REQUESTOR_EN);
 
/* Program advanced line position acc.to the best case from fetching 
data perspective to hide MC latency
 * and prefilling Line Buffer in V Blank (to 10 lines as LB can store 
max 10 lines)
 */
if (v_sync_width_and_b_porch > 10)
-   set_reg_field_value(
-   value,
-   10,
-   CRTC0_CRTC_START_LINE_CONTROL,
-   CRTC_ADVANCED_START_LINE_POSITION);
-   else
-   set_reg_field_value(
-   value,
-   v_sync_width_and_b_porch,
-   CRTC0_CRTC_START_LINE_CONTROL,
-   CRTC_ADVANCED_START_LINE_POSITION);
+   v_sync_width_and_b_porch = 10;
+
+   set_reg_field_value(
+   value,
+   v_sync_width_and_b_porch,
+   CRTC0_CRTC_START_LINE_CONTROL,
+   CRTC_ADVANCED_START_LINE_POSITION);
 
dm_write_reg_soc15(tg->ctx,
mmCRTC0_CRTC_START_LINE_CONTROL,
-- 
2.11.0

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[PATCH 11/31] drm/amd/display: read VM settings from MMHUB

[Harry Wentland]

From: Tony Cheng 

instead of GC, as after GFX off, GC can be power gated any time

Change-Id: Ia40d341ffd06fb1928bd8d95a4b3ef7eca4f73d1
Signed-off-by: Tony Cheng 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 24 +++---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  | 14 ++---
 2 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
index 4a5eb6ae3524..20bd0f5d7b17 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
@@ -130,18 +130,18 @@
SR(DCHUBBUB_ARB_SAT_LEVEL),\
SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
/* todo:  get these from GVM instead of reading registers ourselves */\
-   GC_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
-   GC_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
-   GC_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\
-   GC_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\
-   GC_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\
-   GC_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\
-   GC_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\
-   GC_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\
-   GC_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
-   GC_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\
-   GC_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
-   GC_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
+   MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
+   MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
+   MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\
+   MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\
+   MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\
+   MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\
+   MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\
+   MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\
+   MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
+   MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\
+   MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
+   MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
 
 struct dcn_mi_registers {
uint32_t DCHUBP_CNTL;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 4e5b225a2a08..7fdc5860857b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -122,15 +122,15 @@ enum dcn10_clk_src_array_id {
.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) +  \
mm ## reg_name
 
-/* GC */
-#define GC_BASE_INNER(seg) \
-   GC_BASE__INST0_SEG ## seg
+/* MMHUB */
+#define MMHUB_BASE_INNER(seg) \
+   MMHUB_BASE__INST0_SEG ## seg
 
-#define GC_BASE(seg) \
-   GC_BASE_INNER(seg)
+#define MMHUB_BASE(seg) \
+   MMHUB_BASE_INNER(seg)
 
-#define GC_SR(reg_name)\
-   .reg_name = GC_BASE(mm ## reg_name ## _BASE_IDX) +  \
+#define MMHUB_SR(reg_name)\
+   .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) +  \
mm ## reg_name
 
 /* macros to expend register list macro defined in HW object header file
-- 
2.11.0

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[PATCH 29/31] drm/amd/display: fix flip register write sequence

[Harry Wentland]

From: Dmytro Laktyushkin 

Change-Id: I0a1b924f5a9e66b3e24f8ac2ca1b6597da919305
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 56 ++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h |  2 +
 2 files changed, 28 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
index a52c614ec5b4..da2f99dcd766 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
@@ -237,7 +237,7 @@ static bool mem_input_program_surface_flip_and_addr(
struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
 
/* program flip type */
-   REG_UPDATE(DCSURF_FLIP_CONTROL,
+   REG_SET(DCSURF_FLIP_CONTROL, 0,
SURFACE_FLIP_TYPE, flip_immediate);
 
/* HW automatically latch rest of address register on write to
@@ -258,21 +258,20 @@ static bool mem_input_program_surface_flip_and_addr(
break;
 
if (address->grph.meta_addr.quad_part != 0) {
-
-   REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
+   REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
PRIMARY_META_SURFACE_ADDRESS_HIGH,
address->grph.meta_addr.high_part);
 
-   REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
+   REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
PRIMARY_META_SURFACE_ADDRESS,
address->grph.meta_addr.low_part);
}
 
-   REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
+   REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
PRIMARY_SURFACE_ADDRESS_HIGH,
address->grph.addr.high_part);
 
-   REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
+   REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
PRIMARY_SURFACE_ADDRESS,
address->grph.addr.low_part);
break;
@@ -282,40 +281,38 @@ static bool mem_input_program_surface_flip_and_addr(
break;
 
if (address->video_progressive.luma_meta_addr.quad_part != 0) {
+   REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
+   PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
+   
address->video_progressive.chroma_meta_addr.high_part);
 
-   REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
+   REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
+   PRIMARY_META_SURFACE_ADDRESS_C,
+   
address->video_progressive.chroma_meta_addr.low_part);
+
+   REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
PRIMARY_META_SURFACE_ADDRESS_HIGH,

address->video_progressive.luma_meta_addr.high_part);
 
-   REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
+   REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
PRIMARY_META_SURFACE_ADDRESS,

address->video_progressive.luma_meta_addr.low_part);
-
-   REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
-   PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
-   
address->video_progressive.chroma_meta_addr.high_part);
-
-   REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C,
-   PRIMARY_META_SURFACE_ADDRESS_C,
-   
address->video_progressive.chroma_meta_addr.low_part);
}
 
-   REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C,
+   REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
PRIMARY_SURFACE_ADDRESS_HIGH_C,
address->video_progressive.chroma_addr.high_part);
 
-   REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_C,
+   REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
PRIMARY_SURFACE_ADDRESS_C,
address->video_progressive.chroma_addr.low_part);
 
-   REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
+   REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
PRIMARY_SURFACE_ADDRESS_HIGH,
address->video_progressive.luma_addr.high_part);
 
-   REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
+   REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
P

[PATCH 18/31] drm/amd/display: Fix ASSR enablement on DP to EDP converter

[Harry Wentland]

From: Ayyappa Chandolu 

ASSR mode is not enable when we connect eDP panel via DP to eDP converter.
connector_signal is coming as SIGNAL_TYPE_DISPLAY_PORT. Present code
ignoring panel_mode_edp for SIGNAL_TYPE_DISPLAY_PORT. Added checking
panel_mode_edp for all signals.

Change-Id: I2dbfe6aea7ad6035f59760f9e1244d54532de71b
Signed-off-by: Ayyappa Chandolu 
Reviewed-by: Tony Cheng 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 316df150c1d9..4f46ff14fb69 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -203,10 +203,10 @@ enum dp_panel_mode dp_get_panel_mode(struct core_link 
*link)
default:
break;
}
+   }
 
-   if (link->dpcd_caps.panel_mode_edp) {
-   return DP_PANEL_MODE_EDP;
-   }
+   if (link->dpcd_caps.panel_mode_edp) {
+   return DP_PANEL_MODE_EDP;
}
 
return DP_PANEL_MODE_DEFAULT;
-- 
2.11.0

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[PATCH 24/31] drm/amd/display: Tidy up mem_input_program_surface_flip_and_addr()

[Harry Wentland]

From: Tom St Denis 

Change-Id: I0f893a9abad76da9b403da6103b192af39174088
Signed-off-by: Tom St Denis 
Reviewed-by: Harry Wentland 
Reviewed-by: Tony Cheng 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 25 --
 1 file changed, 9 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 718688c41f7b..673371e5f9f0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -625,18 +625,12 @@ static bool dce_mi_program_surface_flip_and_addr(
 * non-XDMA Mode: GRPH_SURFACE_UPDATE_IMMEDIATE_EN = 1
 * XDMA Mode: GRPH_SURFACE_UPDATE_H_RETRACE_EN = 1
 */
-   REG_UPDATE(GRPH_UPDATE,
-   GRPH_UPDATE_LOCK, 1);
-
-   if (flip_immediate) {
-   REG_UPDATE_2(GRPH_FLIP_CONTROL,
-   GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
-   GRPH_SURFACE_UPDATE_H_RETRACE_EN, 1);
-   } else {
-   REG_UPDATE_2(GRPH_FLIP_CONTROL,
-   GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
-   GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
-   }
+   REG_UPDATE(GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
+
+   REG_UPDATE_2(
+   GRPH_FLIP_CONTROL,
+   GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,
+   GRPH_SURFACE_UPDATE_H_RETRACE_EN, flip_immediate ? 1 : 0);
 
switch (address->type) {
case PLN_ADDR_TYPE_GRAPHICS:
@@ -645,8 +639,8 @@ static bool dce_mi_program_surface_flip_and_addr(
program_pri_addr(dce_mi, address->grph.addr);
break;
case PLN_ADDR_TYPE_GRPH_STEREO:
-   if (address->grph_stereo.left_addr.quad_part == 0
-   || address->grph_stereo.right_addr.quad_part == 0)
+   if (address->grph_stereo.left_addr.quad_part == 0 ||
+   address->grph_stereo.right_addr.quad_part == 0)
break;
program_pri_addr(dce_mi, address->grph_stereo.left_addr);
program_sec_addr(dce_mi, address->grph_stereo.right_addr);
@@ -662,8 +656,7 @@ static bool dce_mi_program_surface_flip_and_addr(
if (flip_immediate)
mem_input->current_address = *address;
 
-   REG_UPDATE(GRPH_UPDATE,
-   GRPH_UPDATE_LOCK, 0);
+   REG_UPDATE(GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
 
return true;
 }
-- 
2.11.0

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[PATCH 17/31] drm/amd/display: Add missed wait_for_prev_commits.

[Harry Wentland]

From: Andrey Grodzovsky 

Change-Id: Ie5f33497e8ab22da8ae3549028023e0e5837867f
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 6d8a1277d59e..ab6a969743a0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -3292,6 +3292,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
surface);
 
need_to_validate = true;
+   wait_for_prev_commits = true;
}
}
}
-- 
2.11.0

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[PATCH 13/31] drm/amd/display: make dc_get_validate_context re-entrant

[Harry Wentland]

From: Dmytro Laktyushkin 

Change-Id: Ie999d2dc977f0018ee289bfaee48e84d6135de2e
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 44 ++
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 30 +++
 .../drm/amd/display/dc/dce100/dce100_resource.c| 22 ++-
 .../drm/amd/display/dc/dce110/dce110_resource.c| 22 ++-
 .../drm/amd/display/dc/dce112/dce112_resource.c| 27 +++--
 .../drm/amd/display/dc/dce112/dce112_resource.h|  3 +-
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c  | 22 ++-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  | 24 ++--
 drivers/gpu/drm/amd/display/dc/inc/core_types.h|  3 +-
 drivers/gpu/drm/amd/display/dc/inc/resource.h  |  9 +++--
 10 files changed, 92 insertions(+), 114 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index b5ba822df55e..0aafcc088284 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -653,40 +653,6 @@ void dc_destroy(struct dc **dc)
*dc = NULL;
 }
 
-static bool is_validation_required(
-   const struct core_dc *dc,
-   const struct dc_validation_set set[],
-   int set_count)
-{
-   const struct validate_context *context = dc->current_context;
-   int i, j;
-
-   if (context->stream_count != set_count)
-   return true;
-
-   for (i = 0; i < set_count; i++) {
-
-   if (set[i].surface_count != 
context->stream_status[i].surface_count)
-   return true;
-   if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), 
context->streams[i]))
-   return true;
-
-   for (j = 0; j < set[i].surface_count; j++) {
-   struct dc_surface temp_surf = { 0 };
-
-   temp_surf = *context->stream_status[i].surfaces[j];
-   temp_surf.clip_rect = set[i].surfaces[j]->clip_rect;
-   temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x;
-   temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y;
-
-   if (memcmp(&temp_surf, set[i].surfaces[j], 
sizeof(temp_surf)) != 0)
-   return true;
-   }
-   }
-
-   return false;
-}
-
 struct validate_context *dc_get_validate_context(
const struct dc *dc,
const struct dc_validation_set set[],
@@ -700,13 +666,8 @@ struct validate_context *dc_get_validate_context(
if(context == NULL)
goto context_alloc_fail;
 
-   if (!is_validation_required(core_dc, set, set_count)) {
-   
dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);
-   return context;
-   }
-
result = core_dc->res_pool->funcs->validate_with_context(
-   core_dc, set, set_count, 
context);
+   core_dc, set, set_count, context, NULL);
 
 context_alloc_fail:
if (result != DC_OK) {
@@ -903,7 +864,8 @@ bool dc_commit_streams(
if (context == NULL)
goto context_alloc_fail;
 
-   result = core_dc->res_pool->funcs->validate_with_context(core_dc, set, 
stream_count, context);
+   result = core_dc->res_pool->funcs->validate_with_context(
+   core_dc, set, stream_count, context, 
core_dc->current_context);
if (result != DC_OK){
dm_logger_write(core_dc->ctx->logger, LOG_ERROR,
"%s: Context validation failed! 
dc_status:%d\n",
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 7ca03d1ad163..ec5045734378 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1148,7 +1148,7 @@ bool resource_validate_attach_surfaces(
int i, j;
 
for (i = 0; i < set_count; i++) {
-   for (j = 0; j < old_context->stream_count; j++)
+   for (j = 0; old_context && j < old_context->stream_count; j++)
if (is_stream_unchanged(
old_context->streams[j],
context->streams[i])) {
@@ -1387,9 +1387,7 @@ static int get_norm_pix_clk(const struct dc_crtc_timing 
*timing)
return normalized_pix_clk;
 }
 
-static void calculate_phy_pix_clks(
-   const struct core_dc *dc,
-   struct validate_context *context)
+static void calculate_phy_pix_clks(struct validate_context *context)
 {
int i;
 
@@ -1410,21 +1408,22 @@ static void calculate_phy_pix_clks(
 
 enum dc_status resource_map_pool_resources(
con

[PATCH 10/31] drm/amd/display: Unify loop for surface update and page flip.

[Harry Wentland]

From: Andrey Grodzovsky 

Remove extra loop we have for page flips and do flips in same loop we do
for surface create/update.
Add documentation for synchronization between commits on different crtcs.
Rename function to have DM prefix.

Change-Id: Ibb6644b15f75981eae7c65a891a9314fb5c23fe9
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Harry Wentland 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 88 +++---
 1 file changed, 42 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index de5c63f42d65..6d8a1277d59e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -2562,10 +2562,11 @@ static void amdgpu_dm_do_flip(
 acrtc->crtc_id);
 }
 
-void dc_commit_surfaces(struct drm_atomic_state *state,
+static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state,
struct drm_device *dev,
struct amdgpu_display_manager *dm,
-   struct drm_crtc *pcrtc)
+   struct drm_crtc *pcrtc,
+   bool *wait_for_vblank)
 {
uint32_t i;
struct drm_plane *plane;
@@ -2578,10 +2579,11 @@ void dc_commit_surfaces(struct drm_atomic_state *state,
for_each_plane_in_state(state, plane, old_plane_state, i) {
struct drm_plane_state *plane_state = plane->state;
struct drm_crtc *crtc = plane_state->crtc;
+   struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(crtc);
struct drm_framebuffer *fb = plane_state->fb;
struct drm_connector *connector;
struct dm_connector_state *dm_state = NULL;
-   struct amdgpu_crtc *acrtc_attach;
+
enum dm_commit_action action;
bool pflip_needed;
 
@@ -2590,13 +2592,13 @@ void dc_commit_surfaces(struct drm_atomic_state *state,
 
action = get_dm_commit_action(crtc->state);
 
-   /* Surfaces are created under two scenarios:
-* 1. This commit is not a page flip.
-* 2. This commit is a page flip, and streams are created.
+   /*
+* TODO - TO decide if it's a flip or surface update
+* stop relying on allow_modeset flag and query DC
+* using dc_check_update_surfaces_for_stream.
 */
pflip_needed = !state->allow_modeset;
-   if (!pflip_needed || action == DM_COMMIT_ACTION_DPMS_ON
-   || action == DM_COMMIT_ACTION_SET) {
+   if (!pflip_needed) {
list_for_each_entry(connector,
&dev->mode_config.connector_list,
head) {
@@ -2626,11 +2628,23 @@ void dc_commit_surfaces(struct drm_atomic_state *state,
if (crtc == pcrtc) {
add_surface(dm->dc, crtc, plane,

&dc_surfaces_constructed[planes_count]);
-   acrtc_attach = to_amdgpu_crtc(crtc);
dc_stream_attach = acrtc_attach->stream;
planes_count++;
}
+   } else if (crtc->state->planes_changed) {
+   *wait_for_vblank =
+   acrtc_attach->flip_flags & 
DRM_MODE_PAGE_FLIP_ASYNC ?
+   false : true;
+
+   amdgpu_dm_do_flip(
+   crtc,
+   fb,
+   drm_crtc_vblank_count(crtc) + *wait_for_vblank);
+
+   /*clean up the flags for next usage*/
+   acrtc_attach->flip_flags = 0;
}
+
}
 
if (planes_count) {
@@ -2652,8 +2666,6 @@ void amdgpu_dm_atomic_commit_tail(
struct drm_device *dev = state->dev;
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_display_manager *dm = &adev->dm;
-   struct drm_plane *plane;
-   struct drm_plane_state *old_plane_state;
uint32_t i, j;
uint32_t commit_streams_count = 0;
uint32_t new_crtcs_count = 0;
@@ -2818,7 +2830,7 @@ void amdgpu_dm_atomic_commit_tail(
 
/* update planes when needed per crtc*/
for_each_crtc_in_state(state, pcrtc, old_crtc_state, j)
-   dc_commit_surfaces(state, dev, dm, pcrtc);
+   amdgpu_dm_commit_surfaces(state, dev, dm, pcrtc, 
&wait_for_vblank);
 
for (i = 0; i < new_crtcs_count; i++) {
/*
@@ -2832,34 +2844,6 @@ void amdgpu_dm_atomic_commit_tail(
 
manage_dm_interrupts(adev, acrtc, true);
  

[PATCH 16/31] drm/amd/display: Implement input gamma LUT

[Harry Wentland]

From: "Leo (Sunpeng) Li" 

1. Implemented dcn10_ipp_program_input_lut(), following the existing
   interface.
2. Added missing registers as needed
3. Change to REG_GET for *ram_select() funcs.
4. Removed gamma table init from DiagsDM::make_surface() for resolving
   CRC errors. Reason: Legacy LUT will be deprecated soon for Raven in
   favor of degamma/regamma.

Change-Id: I4c25bd0b70603d5aeae5b171b83e739e4b1382c5
Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  6 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c   | 82 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h   | 22 ++
 3 files changed, 108 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 28b47bed72cf..62a77f48d437 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -29,9 +29,9 @@
 #include "core_types.h"
 #include "core_status.h"
 #include "resource.h"
-#include "hw_sequencer.h"
 #include "dcn10_hw_sequencer.h"
 #include "dce110/dce110_hw_sequencer.h"
+#include "dce/dce_hwseq.h"
 #include "abm.h"
 
 #include "dcn10/dcn10_transform.h"
@@ -952,6 +952,10 @@ static bool dcn10_set_input_transfer_func(
if (surface->public.in_transfer_func)
tf = DC_TRANSFER_FUNC_TO_CORE(surface->public.in_transfer_func);
 
+   if (surface->public.gamma_correction && dce_use_lut(surface))
+   ipp->funcs->ipp_program_input_lut(ipp,
+   surface->public.gamma_correction);
+
if (tf == NULL)
ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
else if (tf->public.type == TF_TYPE_PREDEFINED) {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
index 082c98c11293..1e7a55d9e9ec 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
@@ -814,7 +814,9 @@ static bool dcn10_degamma_ram_inuse(struct 
input_pixel_processor *ipp,
uint32_t status_reg = 0;
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
 
-   status_reg = (REG_READ(CM_IGAM_LUT_RW_CONTROL) & 0x0F00) >>16;
+   REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS,
+   &status_reg);
+
if (status_reg == 9) {
*ram_a_inuse = true;
ret = true;
@@ -825,6 +827,28 @@ static bool dcn10_degamma_ram_inuse(struct 
input_pixel_processor *ipp,
return ret;
 }
 
+static bool dcn10_ingamma_ram_inuse(struct input_pixel_processor *ipp,
+   bool *ram_a_inuse)
+{
+   bool in_use = false;
+   uint32_t status_reg = 0;
+   struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
+
+   REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS,
+   &status_reg);
+
+   // 1 => IGAM_RAMA, 3 => IGAM_RAMA & DGAM_ROMA, 4 => IGAM_RAMA & 
DGAM_ROMB
+   if (status_reg == 1 || status_reg == 3 || status_reg == 4) {
+   *ram_a_inuse = true;
+   in_use = true;
+   // 2 => IGAM_RAMB, 5 => IGAM_RAMB & DGAM_ROMA, 6 => IGAM_RAMB & 
DGAM_ROMB
+   } else if (status_reg == 2 || status_reg == 5 || status_reg == 6) {
+   *ram_a_inuse = false;
+   in_use = true;
+   }
+   return in_use;
+}
+
 static void dcn10_degamma_ram_select(struct input_pixel_processor *ipp,
bool use_ram_a)
 {
@@ -855,6 +879,61 @@ static void dcn10_ipp_set_degamma_pwl(struct 
input_pixel_processor *ipp,
dcn10_degamma_ram_select(ipp, !is_ram_a);
 }
 
+/*
+ * Input gamma LUT currently supports 256 values only. This means input color
+ * can have a maximum of 8 bits per channel (= 256 possible values) in order to
+ * have a one-to-one mapping with the LUT. Truncation will occur with color
+ * values greater than 8 bits.
+ *
+ * In the future, this function should support additional input gamma methods,
+ * such as piecewise linear mapping, and input gamma bypass.
+ */
+void dcn10_ipp_program_input_lut(
+   struct input_pixel_processor *ipp,
+   const struct dc_gamma *gamma)
+{
+   int i;
+   struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
+   bool rama_occupied = false;
+   uint32_t ram_num;
+   // Power on LUT memory.
+   REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 1);
+   dcn10_ipp_enable_cm_block(ipp);
+   // Determine whether to use RAM A or RAM B
+   dcn10_ingamma_ram_inuse(ipp, &rama_occupied);
+   if (!rama_occupied)
+   REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 0);
+   else
+   REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 1);
+

[PATCH 14/31] drm/amd/display: revert dc_get_validate_context re-entrancy fix

[Harry Wentland]

From: Dmytro Laktyushkin 

Apply dc_get_validate_context re-entrancy fix to dc_validate_resources instead

Change-Id: I8502010ff24f6b3b4ea932e1042fdca1a02a5a0c
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 71 
 1 file changed, 62 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 0aafcc088284..773f0efc449b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -653,6 +653,40 @@ void dc_destroy(struct dc **dc)
*dc = NULL;
 }
 
+static bool is_validation_required(
+   const struct core_dc *dc,
+   const struct dc_validation_set set[],
+   int set_count)
+{
+   const struct validate_context *context = dc->current_context;
+   int i, j;
+
+   if (context->stream_count != set_count)
+   return true;
+
+   for (i = 0; i < set_count; i++) {
+
+   if (set[i].surface_count != 
context->stream_status[i].surface_count)
+   return true;
+   if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), 
context->streams[i]))
+   return true;
+
+   for (j = 0; j < set[i].surface_count; j++) {
+   struct dc_surface temp_surf = { 0 };
+
+   temp_surf = *context->stream_status[i].surfaces[j];
+   temp_surf.clip_rect = set[i].surfaces[j]->clip_rect;
+   temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x;
+   temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y;
+
+   if (memcmp(&temp_surf, set[i].surfaces[j], 
sizeof(temp_surf)) != 0)
+   return true;
+   }
+   }
+
+   return false;
+}
+
 struct validate_context *dc_get_validate_context(
const struct dc *dc,
const struct dc_validation_set set[],
@@ -663,11 +697,16 @@ struct validate_context *dc_get_validate_context(
struct validate_context *context;
 
context = dm_alloc(sizeof(struct validate_context));
-   if(context == NULL)
+   if (context == NULL)
goto context_alloc_fail;
 
+   if (!is_validation_required(core_dc, set, set_count)) {
+   
dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);
+   return context;
+   }
+
result = core_dc->res_pool->funcs->validate_with_context(
-   core_dc, set, set_count, context, NULL);
+   core_dc, set, set_count, context, 
core_dc->current_context);
 
 context_alloc_fail:
if (result != DC_OK) {
@@ -690,16 +729,30 @@ bool dc_validate_resources(
const struct dc_validation_set set[],
uint8_t set_count)
 {
-   struct validate_context *ctx;
+   struct core_dc *core_dc = DC_TO_CORE(dc);
+   enum dc_status result = DC_ERROR_UNEXPECTED;
+   struct validate_context *context;
 
-   ctx = dc_get_validate_context(dc, set, set_count);
-   if (ctx) {
-   dc_resource_validate_ctx_destruct(ctx);
-   dm_free(ctx);
-   return true;
+   context = dm_alloc(sizeof(struct validate_context));
+   if (context == NULL)
+   goto context_alloc_fail;
+
+   result = core_dc->res_pool->funcs->validate_with_context(
+   core_dc, set, set_count, context, NULL);
+
+context_alloc_fail:
+   if (result != DC_OK) {
+   dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
+   "%s:resource validation failed, dc_status:%d\n",
+   __func__,
+   result);
}
 
-   return false;
+   dc_resource_validate_ctx_destruct(context);
+   dm_free(context);
+   context = NULL;
+
+   return result == DC_OK;
 }
 
 bool dc_validate_guaranteed(
-- 
2.11.0

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[PATCH 23/31] drm/amd/display: Tidy up dce120_clock_source_create()

[Harry Wentland]

From: Tom St Denis 

Also change sizeof to be automatic based on type declaration.

Change-Id: I0353d84fdbc889ba0be162566e711a8a7fbc0256
Signed-off-by: Tom St Denis 
Reviewed-by: Harry Wentland 
Reviewed-by: Tony Cheng 
---
 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 1276dabfb208..ec485353ea4f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -398,13 +398,13 @@ struct clock_source *dce120_clock_source_create(
bool dp_clk_src)
 {
struct dce110_clk_src *clk_src =
-   dm_alloc(sizeof(struct dce110_clk_src));
+   dm_alloc(sizeof(*clk_src));
 
if (!clk_src)
return NULL;
 
if (dce110_clk_src_construct(clk_src, ctx, bios, id,
-   regs, &cs_shift, &cs_mask)) {
+regs, &cs_shift, &cs_mask)) {
clk_src->base.dp_clk_src = dp_clk_src;
return &clk_src->base;
}
-- 
2.11.0

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[PATCH 21/31] drm/amd/display: Make dce120_tg_is_blanked() more legible

[Harry Wentland]

From: Tom St Denis 

Change-Id: I0a0cb44a5224a74dd4f0a819c3e8c38c2afca8a1
Signed-off-by: Tom St Denis 
Reviewed-by: Harry Wentland 
---
 .../drm/amd/display/dc/dce120/dce120_timing_generator.c | 17 -
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 1c25dc66ff4f..1e2843e5d97e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -746,15 +746,14 @@ bool dce120_tg_is_blanked(struct timing_generator *tg)
mmCRTC0_CRTC_BLANK_CONTROL,
tg110->offsets.crtc);
 
-   if (
-   get_reg_field_value(
-   value,
-   CRTC0_CRTC_BLANK_CONTROL,
-   CRTC_BLANK_DATA_EN) == 1&&
-   get_reg_field_value(
-   value,
-   CRTC0_CRTC_BLANK_CONTROL,
-   CRTC_CURRENT_BLANK_STATE) == 1)
+   if (get_reg_field_value(
+   value,
+   CRTC0_CRTC_BLANK_CONTROL,
+   CRTC_BLANK_DATA_EN) == 1 &&
+   get_reg_field_value(
+   value,
+   CRTC0_CRTC_BLANK_CONTROL,
+   CRTC_CURRENT_BLANK_STATE) == 1)
return true;
 
return false;
-- 
2.11.0

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[PATCH 02/31] drm/amd/display: fix mpo blanking out on one of planes being set not visible

[Harry Wentland]

From: Dmytro Laktyushkin 

Change-Id: Ib270db25b4bcb14226f740aa5a8926d0f9c736ca
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c |  3 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h |  3 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c| 10 +++---
 .../drm/amd/display/dc/dce110/dce110_mem_input_v.c |  3 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 41 ++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 20 +++
 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h  |  8 ++---
 7 files changed, 51 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 9da539db287c..0552fc5f7ecc 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -403,8 +403,7 @@ void dce_mem_input_program_surface_config(struct mem_input 
*mi,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
-   bool horizontal_mirror,
-   bool visible)
+   bool horizontal_mirror)
 {
REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index be37f52e9ba1..4977f5f6e7e2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -277,8 +277,7 @@ void dce_mem_input_program_surface_config(struct mem_input 
*mi,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
-   bool horizontal_mirror,
-   bool visible);
+   bool horizontal_mirror);
 
 void dce_mem_input_allocate_dmif(struct mem_input *mi,
uint32_t h_total,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 8a663003017c..20ad1cb263db 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1986,8 +1986,9 @@ static void set_plane_config(
&surface->public.plane_size,
surface->public.rotation,
NULL,
-   false,
-   pipe_ctx->surface->public.visible);
+   false);
+   if (mi->funcs->set_blank)
+   mi->funcs->set_blank(mi, pipe_ctx->surface->public.visible);
 
if (dc->public.config.gpu_vm_support)
mi->funcs->mem_input_program_pte_vm(
@@ -2432,8 +2433,9 @@ static void dce110_program_front_end_for_pipe(
&surface->public.plane_size,
surface->public.rotation,
NULL,
-   false,
-   pipe_ctx->surface->public.visible);
+   false);
+   if (mi->funcs->set_blank)
+   mi->funcs->set_blank(mi, pipe_ctx->surface->public.visible);
 
if (dc->public.config.gpu_vm_support)
mi->funcs->mem_input_program_pte_vm(
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
index 02739d3efa97..78dd3ae3af5f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
@@ -664,8 +664,7 @@ void dce110_mem_input_v_program_surface_config(
union plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
-   bool horizotal_mirror,
-   bool visible)
+   bool horizotal_mirror)
 {
struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 6cb3924225da..28b47bed72cf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -848,7 +848,7 @@ static void reset_front_end_for_pipe(
 
unlock_master_tg_and_wait(dc->ctx, pipe_ctx->tg->inst);
 
-   pipe_ctx->mi->funcs->disable_request(pipe_ctx->mi);
+   pipe_ctx->mi->funcs->set_blank(pipe_ctx->mi, true);
 
wait_no_outstanding_request(dc->ctx, pipe_ctx->pipe_idx);
 
@@ -1513,6 +1513,35 @@ static void program_gamut_remap(struct pipe_ctx 
*pipe_ctx)
pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust);
 }
 
+static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
+{
+   if (pipe_ctx->surface->public.visible)
+   return true;
+   if (pipe_ctx->bottom_pipe && 
is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
+  

[PATCH 05/31] drm/amd/display: dce 8 - 12 mem_input refactor to new style

[Harry Wentland]

From: Dmytro Laktyushkin 

Change-Id: Ie24528a1e8e70a94eb4f029289ea1c4e8f8722b7
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 306 +--
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 115 --
 .../drm/amd/display/dc/dce100/dce100_resource.c|  78 +---
 drivers/gpu/drm/amd/display/dc/dce110/Makefile |   3 +-
 .../drm/amd/display/dc/dce110/dce110_mem_input.c   | 437 -
 .../drm/amd/display/dc/dce110/dce110_mem_input.h   | 121 --
 .../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 155 +++-
 .../drm/amd/display/dc/dce110/dce110_mem_input_v.h |  66 +---
 .../drm/amd/display/dc/dce110/dce110_resource.c|  58 +--
 drivers/gpu/drm/amd/display/dc/dce112/Makefile |   2 +-
 .../drm/amd/display/dc/dce112/dce112_mem_input.c   |  54 ---
 .../drm/amd/display/dc/dce112/dce112_mem_input.h   |  38 --
 .../drm/amd/display/dc/dce112/dce112_resource.c|  77 +---
 drivers/gpu/drm/amd/display/dc/dce120/Makefile |   2 +-
 .../drm/amd/display/dc/dce120/dce120_mem_input.c   | 340 
 .../drm/amd/display/dc/dce120/dce120_mem_input.h   |  37 --
 .../drm/amd/display/dc/dce120/dce120_resource.c|  75 +---
 drivers/gpu/drm/amd/display/dc/dce80/Makefile  |   3 +-
 .../gpu/drm/amd/display/dc/dce80/dce80_mem_input.c |  83 
 .../gpu/drm/amd/display/dc/dce80/dce80_mem_input.h |  36 --
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c  |  78 +---
 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h  |   8 -
 22 files changed, 476 insertions(+), 1696 deletions(-)
 delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c
 delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h
 delete mode 100644 drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.c
 delete mode 100644 drivers/gpu/drm/amd/display/dc/dce112/dce112_mem_input.h
 delete mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
 delete mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.h
 delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c
 delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.h

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 0552fc5f7ecc..718688c41f7b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -23,18 +23,18 @@
  *
  */
 
-#include "mem_input.h"
+#include "dce_mem_input.h"
 #include "reg_helper.h"
 #include "basics/conversion.h"
 
 #define CTX \
-   mi->ctx
+   dce_mi->base.ctx
 #define REG(reg)\
-   mi->regs->reg
+   dce_mi->regs->reg
 
 #undef FN
 #define FN(reg_name, field_name) \
-   mi->shifts->field_name, mi->masks->field_name
+   dce_mi->shifts->field_name, dce_mi->masks->field_name
 
 struct pte_setting {
unsigned int bpp;
@@ -130,11 +130,13 @@ static bool is_vert_scan(enum dc_rotation_angle rotation)
}
 }
 
-void dce_mem_input_program_pte_vm(struct mem_input *mi,
+static void dce_mi_program_pte_vm(
+   struct mem_input *mi,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
enum dc_rotation_angle rotation)
 {
+   struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
enum mi_bits_per_pixel mi_bpp = get_mi_bpp(format);
enum mi_tiling_format mi_tiling = get_mi_tiling(tiling_info);
const struct pte_setting *pte = &pte_settings[mi_tiling][mi_bpp];
@@ -158,7 +160,8 @@ void dce_mem_input_program_pte_vm(struct mem_input *mi,
DVMM_MAX_PTE_REQ_OUTSTANDING, 0xff);
 }
 
-static void program_urgency_watermark(struct mem_input *mi,
+static void program_urgency_watermark(
+   struct dce_mem_input *dce_mi,
uint32_t wm_select,
uint32_t urgency_low_wm,
uint32_t urgency_high_wm)
@@ -171,7 +174,8 @@ static void program_urgency_watermark(struct mem_input *mi,
URGENCY_HIGH_WATERMARK, urgency_high_wm);
 }
 
-static void program_nbp_watermark(struct mem_input *mi,
+static void program_nbp_watermark(
+   struct dce_mem_input *dce_mi,
uint32_t wm_select,
uint32_t nbp_wm)
 {
@@ -202,7 +206,8 @@ static void program_nbp_watermark(struct mem_input *mi,
}
 }
 
-static void program_stutter_watermark(struct mem_input *mi,
+static void program_stutter_watermark(
+   struct dce_mem_input *dce_mi,
uint32_t wm_select,
uint32_t stutter_mark)
 {
@@ -217,41 +222,67 @@ static void program_stutter_watermark(struct mem_input 
*mi,
STUTTER_EXIT_SELF_REFRESH_WATERMARK, 
stutter_mark);
 }
 
-void dce_mem_input_program_display_marks(struct mem_input *mi,
+static void dce_mi_program_display_marks(
+   struct mem_input *mi,
struct dce_watermarks nbp,
  

[PATCH 12/31] drm/amd/display: Fix 5th display lightup on Vega10

[Harry Wentland]

From: Roman Li 

- fixing bug in calculation of reg offset for D5VGA_CONTROL

Change-Id: I0e08d59d03c8daaaf4848a71fac38c37eba492c5
Signed-off-by: Roman Li 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 245356e72b36..dc8eeac6ac96 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -410,7 +410,7 @@ void dce120_timing_generator_disable_vga(struct 
timing_generator *tg)
break;
case CONTROLLER_ID_D4:
addr = mmD1VGA_CONTROL;
-   offset = mmD1VGA_CONTROL - mmD1VGA_CONTROL;
+   offset = mmD5VGA_CONTROL - mmD1VGA_CONTROL;
break;
case CONTROLLER_ID_D5:
addr = mmD6VGA_CONTROL;
-- 
2.11.0

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[PATCH 15/31] drm/amd/display: Refactor use_lut() from dce110 to dce

[Harry Wentland]

From: "Leo (Sunpeng) Li" 

use_lut() checks if the input surface's pixel format is compatible with
a 256 entry LUT. This function can be used across different versions and
not just dce11.

Change-Id: Ia2813007c91f39939e0ceef65e2f68af0a5e235c
Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c  | 12 
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h  |  2 ++
 .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 17 ++---
 3 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
index 34c18712970c..cc3178acfc54 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
@@ -191,3 +191,15 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
   clk_src->id, tg_inst);
}
 }
+
+/* Only use LUT for 8 bit formats */
+bool dce_use_lut(const struct core_surface *surface)
+{
+   switch (surface->public.format) {
+   case SURFACE_PIXEL_FORMAT_GRPH_ARGB:
+   case SURFACE_PIXEL_FORMAT_GRPH_ABGR:
+   return true;
+   default:
+   return false;
+   }
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index dd13f47b6446..112f9c85c142 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -256,4 +256,6 @@ void dce_clock_gating_power_up(struct dce_hwseq *hws,
 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
struct clock_source *clk_src,
unsigned int tg_inst);
+
+bool dce_use_lut(const struct core_surface *surface);
 #endif   /*__DCE_HWSEQ_H__*/
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 20ad1cb263db..65c691569eb7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -28,10 +28,10 @@
 #include "core_types.h"
 #include "core_status.h"
 #include "resource.h"
-#include "hw_sequencer.h"
 #include "dm_helpers.h"
 #include "dce110_hw_sequencer.h"
 #include "dce110_timing_generator.h"
+#include "dce/dce_hwseq.h"
 
 #include "bios/bios_parser_helper.h"
 #include "timing_generator.h"
@@ -233,19 +233,6 @@ static void build_prescale_params(struct 
ipp_prescale_params *prescale_params,
}
 }
 
-
-/* Only use LUT for 8 bit formats */
-static bool use_lut(const struct core_surface *surface)
-{
-   switch (surface->public.format) {
-   case SURFACE_PIXEL_FORMAT_GRPH_ARGB:
-   case SURFACE_PIXEL_FORMAT_GRPH_ABGR:
-   return true;
-   default:
-   return false;
-   }
-}
-
 static bool dce110_set_input_transfer_func(
struct pipe_ctx *pipe_ctx,
const struct core_surface *surface)
@@ -264,7 +251,7 @@ static bool dce110_set_input_transfer_func(
build_prescale_params(&prescale_params, surface);
ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
 
-   if (surface->public.gamma_correction && use_lut(surface))
+   if (surface->public.gamma_correction && dce_use_lut(surface))
ipp->funcs->ipp_program_input_lut(ipp, 
surface->public.gamma_correction);
 
if (tf == NULL) {
-- 
2.11.0

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[PATCH 06/31] drm/amd/display: Use dc_update_surfaces_for_stream for flip.

[Harry Wentland]

From: Andrey Grodzovsky 

Today we use special interface for flip because of fear of cuncurency issues
over dc->current_ctx. This should be no longer an issue when flipping on
multiple CRTCs concurently since for fast update (as flip is) no new context
is created and the exsisitng is not destroyed. For full updates case when
removing or adding streams on once CRTC while flipping on another
Adding all current active CRTC's states to the atomic commit in
amdgpu_dm_atomic_check will garntee that any such full update commit
will wait for completion of any outstanding flip.

Change-Id: I0c7e972eec82ae6f61706800ef5d40ed480683d9
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Andrey Grodzovsky 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |  9 ++---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 23 +-
 2 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index cd06229bef2e..36fe956b0a89 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1355,6 +1355,7 @@ static void dm_page_flip(struct amdgpu_device *adev,
struct amdgpu_crtc *acrtc;
const struct dc_stream *stream;
struct dc_flip_addrs addr = { {0} };
+   struct dc_surface_update surface_updates[1] = { {0} };
 
/*
 * TODO risk of concurrency issues
@@ -1417,9 +1418,11 @@ static void dm_page_flip(struct amdgpu_device *adev,
acrtc->base.state->event = NULL;
}
 
-   dc_flip_surface_addrs(adev->dm.dc,
- dc_stream_get_status(stream)->surfaces,
- &addr, 1);
+   surface_updates->surface = dc_stream_get_status(stream)->surfaces[0];
+   surface_updates->flip_addr = &addr;
+
+
+   dc_update_surfaces_for_stream(adev->dm.dc, surface_updates, 1, stream);
 
DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
 __func__,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 8aeb10786b94..de5c63f42d65 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -3082,6 +3082,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
struct dc *dc = adev->dm.dc;
bool need_to_validate = false;
struct validate_context *context;
+   bool wait_4_prev_commits = false;
 
ret = drm_atomic_helper_check(dev, state);
 
@@ -3158,6 +3159,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 
new_stream_count++;
need_to_validate = true;
+   wait_4_prev_commits = true;
break;
}
 
@@ -3203,6 +3205,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 
new_stream_count++;
need_to_validate = true;
+   wait_4_prev_commits = true;
 
break;
}
@@ -3214,6 +3217,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
set,
set_count,
acrtc->stream);
+   wait_4_prev_commits = true;
}
break;
}
@@ -3306,9 +3310,26 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 
context = dc_get_validate_context(dc, set, set_count);
 
-   if (need_to_validate == false || set_count == 0 || context)
+   if (need_to_validate == false || set_count == 0 || context) {
+
ret = 0;
 
+   if (wait_4_prev_commits) {
+   list_for_each_entry(crtc, &dev->mode_config.crtc_list, 
head) {
+   struct amdgpu_crtc *acrtc = 
to_amdgpu_crtc(crtc);
+   struct drm_crtc_state *crtc_state;
+
+   if (acrtc->stream) {
+   crtc_state = 
drm_atomic_get_crtc_state(state, crtc);
+   if (IS_ERR(crtc_state)) {
+   ret = PTR_ERR(crtc_state);
+   break;
+   }
+   }
+   }
+   }
+   }
+
if (context) {
dc_resource_validate_ctx_destruct(context);
dm_free(context);
-- 
2.11.0

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[PATCH 07/31] drm/amd/display: Clen unused interface.

[Harry Wentland]

From: Andrey Grodzovsky 

Change-Id: Icf443def80e33f255d2d4c151a36c06951d275d2
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 26 --
 drivers/gpu/drm/amd/display/dc/dc.h  | 12 
 2 files changed, 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 6d56cb0c29cc..b5ba822df55e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1515,32 +1515,6 @@ const struct audio **dc_get_audios(struct dc *dc)
return (const struct audio **)core_dc->res_pool->audios;
 }
 
-void dc_flip_surface_addrs(
-   struct dc *dc,
-   const struct dc_surface *const surfaces[],
-   struct dc_flip_addrs flip_addrs[],
-   uint32_t count)
-{
-   struct core_dc *core_dc = DC_TO_CORE(dc);
-   int i, j;
-
-   for (i = 0; i < count; i++) {
-   struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]);
-
-   surface->public.address = flip_addrs[i].address;
-   surface->public.flip_immediate = flip_addrs[i].flip_immediate;
-
-   for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
-   struct pipe_ctx *pipe_ctx = 
&core_dc->current_context->res_ctx.pipe_ctx[j];
-
-   if (pipe_ctx->surface != surface)
-   continue;
-
-   core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
-   }
-   }
-}
-
 enum dc_irq_source dc_interrupt_to_irq_source(
struct dc *dc,
uint32_t src_id,
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 0610805cdb05..f2efa32fe4ac 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -394,18 +394,6 @@ struct dc_flip_addrs {
 };
 
 /*
- * Optimized flip address update function.
- *
- * After this call:
- *   Surface addresses and flip attributes are programmed.
- *   Surface flip occur at next configured time (h_sync or v_sync flip)
- */
-void dc_flip_surface_addrs(struct dc *dc,
-   const struct dc_surface *const surfaces[],
-   struct dc_flip_addrs flip_addrs[],
-   uint32_t count);
-
-/*
  * Set up surface attributes and associate to a stream
  * The surfaces parameter is an absolute set of all surface active for the 
stream.
  * If no surfaces are provided, the stream will be blanked; no memory read.
-- 
2.11.0

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[PATCH 04/31] drm/amd/display: Disable ABM when eDP is disabled

[Harry Wentland]

From: Amy Zhang 

- Add immediate ABM disable when eDP is disabled
- Fix purple screen when ABM is mistakenly enabled
on non eDP display

Change-Id: Iff09807f7051126ba95b043061a2f7b1600b34a2
Signed-off-by: Amy Zhang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 16 
 drivers/gpu/drm/amd/display/dc/dc.h   |  2 ++
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c  | 21 +
 drivers/gpu/drm/amd/display/dc/inc/hw/abm.h   |  1 +
 4 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index ffc0eeaad175..59977640f938 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1415,6 +1415,22 @@ bool dc_link_set_backlight_level(const struct dc_link 
*dc_link, uint32_t level,
return true;
 }
 
+
+bool dc_link_set_abm_disable(const struct dc_link *dc_link)
+{
+   struct core_link *link = DC_LINK_TO_CORE(dc_link);
+   struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc);
+   struct abm *abm = core_dc->res_pool->abm;
+
+   if ((abm == NULL) || (abm->funcs->set_backlight_level == NULL))
+   return false;
+
+   abm->funcs->set_abm_immediate_disable(abm);
+
+   return true;
+}
+
+
 bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable)
 {
struct core_link *link = DC_LINK_TO_CORE(dc_link);
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 9a19d6f5a6a3..0610805cdb05 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -714,6 +714,8 @@ const struct graphics_object_id dc_get_link_id_at_index(
 bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level,
uint32_t frame_ramp, const struct dc_stream *stream);
 
+bool dc_link_set_abm_disable(const struct dc_link *dc_link);
+
 bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable);
 
 bool dc_link_setup_psr(const struct dc_link *dc_link,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
index cefffe164fe0..b4fa78292ad2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
@@ -49,6 +49,8 @@
 #define MCP_ABM_PIPE_SET 0x66
 #define MCP_BL_SET 0x67
 
+#define MCP_DISABLE_ABM_IMMEDIATELY 255
+
 struct abm_backlight_registers {
unsigned int BL_PWM_CNTL;
unsigned int BL_PWM_CNTL2;
@@ -315,6 +317,24 @@ static bool dce_abm_set_level(struct abm *abm, uint32_t 
level)
return true;
 }
 
+static bool dce_abm_immediate_disable(struct abm *abm)
+{
+   struct dce_abm *abm_dce = TO_DCE_ABM(abm);
+
+   REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
+   100, 800);
+
+   /* setDMCUParam_ABMLevel */
+   REG_UPDATE_2(MASTER_COMM_CMD_REG,
+   MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET,
+   MASTER_COMM_CMD_REG_BYTE2, MCP_DISABLE_ABM_IMMEDIATELY);
+
+   /* notifyDMCUMsg */
+   REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
+
+   return true;
+}
+
 static bool dce_abm_init_backlight(struct abm *abm)
 {
struct dce_abm *abm_dce = TO_DCE_ABM(abm);
@@ -414,6 +434,7 @@ static const struct abm_funcs dce_funcs = {
.init_backlight = dce_abm_init_backlight,
.set_backlight_level = dce_abm_set_backlight_level,
.get_current_backlight_8_bit = dce_abm_get_current_backlight_8_bit,
+   .set_abm_immediate_disable = dce_abm_immediate_disable,
.is_dmcu_initialized = is_dmcu_initialized
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
index da465b3e98e8..c93b9b9a817c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
@@ -35,6 +35,7 @@ struct abm {
 struct abm_funcs {
void (*abm_init)(struct abm *abm);
bool (*set_abm_level)(struct abm *abm, unsigned int abm_level);
+   bool (*set_abm_immediate_disable)(struct abm *abm);
bool (*init_backlight)(struct abm *abm);
bool (*set_backlight_level)(struct abm *abm,
unsigned int backlight_level,
-- 
2.11.0

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[PATCH 03/31] drm/amd/display: Fix slow FPS.

[Harry Wentland]

From: Andrey Grodzovsky 

Typo in expresion.

Change-Id: I156388e19ccfa40996a16383c1532ffde687427e
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Andrey Grodzovsky 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 9813688fdec1..cd06229bef2e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -141,8 +141,8 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device 
*adev, int crtc,
 &h_position,
 &v_position);
 
-   *position = (v_position) || (h_position << 16);
-   *vbl = (v_blank_start) || (v_blank_end << 16);
+   *position = v_position | (h_position << 16);
+   *vbl = v_blank_start | (v_blank_end << 16);
}
 
return 0;
-- 
2.11.0

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[PATCH 01/31] drm/amd/display: Program CSC Mode For BT2020

[Harry Wentland]

From: Amy Zhang 

- Add BT2020 color space in the set output csc default

Change-Id: I50a4aa392b0bfb403b9e633c083ae230485b2f35
Signed-off-by: Amy Zhang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
index fce08e5235e6..148e192f5f76 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -338,9 +338,11 @@ static void opp_set_output_csc_default(
if (default_adjust != NULL) {
switch (default_adjust->out_color_space) {
case COLOR_SPACE_SRGB:
+   case COLOR_SPACE_2020_RGB_FULLRANGE:
ocsc_mode = 0;
break;
case COLOR_SPACE_SRGB_LIMITED:
+   case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
ocsc_mode = 1;
break;
case COLOR_SPACE_YCBCR601:
@@ -349,6 +351,7 @@ static void opp_set_output_csc_default(
break;
case COLOR_SPACE_YCBCR709:
case COLOR_SPACE_YCBCR709_LIMITED:
+   case COLOR_SPACE_2020_YCBCR:
ocsc_mode = 3;
break;
case COLOR_SPACE_UNKNOWN:
-- 
2.11.0

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[PATCH 09/31] drm/amd/display: add missing GRPH_UPDATE_LOCK field macro for dce_mem_input

[Harry Wentland]

From: Dmytro Laktyushkin 

Change-Id: I891ab6c4681da08dd2d9111cb77a1f87348b2420
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index 55481f5adcdf..9d083cd79b4c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -158,6 +158,7 @@ struct dce_mem_input_registers {
SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 
GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS, GRPH_PRIMARY_SURFACE_ADDRESS, 
mask_sh),\
SFB(blk, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, mask_sh),\
+   SFB(blk, GRPH_UPDATE, GRPH_UPDATE_LOCK, mask_sh),\
SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh)
 
 #define MI_DCP_DCE11_MASK_SH_LIST(mask_sh, blk)\
-- 
2.11.0

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[PATCH 00/31] DC Linux Patches May 23, 2017

[Harry Wentland]

 * Use update_surfaces for stream instead of special casing it
 * Fix wrong scanline reporting
 * Bunch of other bug fixes for Raven, Vega, and others
 * Some small cleanups and a large cleanup in memory interface

Amy Zhang (2):
  drm/amd/display: Program CSC Mode For BT2020
  drm/amd/display: Disable ABM when eDP is disabled

Andrey Grodzovsky (7):
  drm/amd/display: Fix slow FPS.
  drm/amd/display: Use dc_update_surfaces_for_stream for flip.
  drm/amd/display: Clen unused interface.
  drm/amd/display: Unify loop for surface update and page flip.
  drm/amd/display: Add missed wait_for_prev_commits.
  drm/amd/display: Query for update plane type.
  drm/amd/display: Remove redundant condition.

Ayyappa Chandolu (1):
  drm/amd/display: Fix ASSR enablement on DP to EDP converter

Dmytro Laktyushkin (7):
  drm/amd/display: fix mpo blanking out on one of planes being set not
visible
  drm/amd/display: dce 8 - 12 mem_input refactor to new style
  drm/amd/display: add missing GRPH_UPDATE_LOCK field macro for
dce_mem_input
  drm/amd/display: make dc_get_validate_context re-entrant
  drm/amd/display: revert dc_get_validate_context re-entrancy fix
  drm/amd/display: remove GRPH_SURFACE_UPDATE_IMMEDIATE_EN field
programming
  drm/amd/display: fix flip register write sequence

Harry Wentland (2):
  drm/amd/display: Remove unused addr var in TG
  drm/amd/display: No need to assert on stream_status

Leo (Sunpeng) Li (3):
  drm/amd/display: Fix dcn10 cursor set position hang
  drm/amd/display: Refactor use_lut() from dce110 to dce
  drm/amd/display: Implement input gamma LUT

Roman Li (1):
  drm/amd/display: Fix 5th display lightup on Vega10

Tom St Denis (6):
  drm/amd/display: Tidy up
dce120_timing_generator_enable_advanced_request()
  drm/amd/display: Fix indentation in dce120_tg_program_timing()
  drm/amd/display: Make dce120_tg_is_blanked() more legible
  drm/amd/display: Clean up indentation in dce120_tg_set_blank()
  drm/amd/display: Tidy up dce120_clock_source_create()
  drm/amd/display: Tidy up mem_input_program_surface_flip_and_addr()

Tony Cheng (2):
  drm/amd/display: read VM settings from MMHUB
  drm/amd/display: fix YUV surface address programming sequence

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |  13 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 172 +---
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  61 ++-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  |  16 +
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c |   6 +-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |  30 +-
 drivers/gpu/drm/amd/display/dc/dc.h|  14 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c   |  21 +
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c |  12 +
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h |   2 +
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 297 --
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 115 --
 .../drm/amd/display/dc/dce100/dce100_resource.c| 100 ++---
 drivers/gpu/drm/amd/display/dc/dce110/Makefile |   3 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  27 +-
 .../drm/amd/display/dc/dce110/dce110_mem_input.c   | 437 -
 .../drm/amd/display/dc/dce110/dce110_mem_input.h   | 121 --
 .../drm/amd/display/dc/dce110/dce110_mem_input_v.c | 158 
 .../drm/amd/display/dc/dce110/dce110_mem_input_v.h |  66 +---
 .../drm/amd/display/dc/dce110/dce110_resource.c|  80 ++--
 drivers/gpu/drm/amd/display/dc/dce112/Makefile |   2 +-
 .../drm/amd/display/dc/dce112/dce112_mem_input.c   |  54 ---
 .../drm/amd/display/dc/dce112/dce112_mem_input.h   |  38 --
 .../drm/amd/display/dc/dce112/dce112_resource.c| 104 ++---
 .../drm/amd/display/dc/dce112/dce112_resource.h|   3 +-
 drivers/gpu/drm/amd/display/dc/dce120/Makefile |   2 +-
 .../drm/amd/display/dc/dce120/dce120_mem_input.c   | 340 
 .../drm/amd/display/dc/dce120/dce120_mem_input.h   |  37 --
 .../drm/amd/display/dc/dce120/dce120_resource.c|  79 +---
 .../display/dc/dce120/dce120_timing_generator.c|  85 ++--
 drivers/gpu/drm/amd/display/dc/dce80/Makefile  |   3 +-
 .../gpu/drm/amd/display/dc/dce80/dce80_mem_input.c |  83 
 .../gpu/drm/amd/display/dc/dce80/dce80_mem_input.h |  36 --
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c  | 100 ++---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  47 ++-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c   |  92 -
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h   |  22 ++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 112 +++---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h |  26 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c   |   3 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  38 +-
 drivers/gpu/drm/amd/display/dc/inc/core_types.h|   3 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/abm.h|   1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h  |  16 +-
 drivers/gpu/dr

Re: [PATCH] drm/radeon: fix "force the UVD DPB into VRAM as well"

[Alex Deucher]

On Thu, May 18, 2017 at 8:24 AM, Christian König
 wrote:
> From: Christian König 
>
> The DPB must be in VRAM, but not in the first segment.
>
> Signed-off-by: Christian König 
> Tested-by: Arthur Marsh 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/radeon/radeon_uvd.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c 
> b/drivers/gpu/drm/radeon/radeon_uvd.c
> index fad4a11..0cd0e7b 100644
> --- a/drivers/gpu/drm/radeon/radeon_uvd.c
> +++ b/drivers/gpu/drm/radeon/radeon_uvd.c
> @@ -621,7 +621,7 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
> }
>
> /* TODO: is this still necessary on NI+ ? */
> -   if ((cmd == 0 || cmd == 1 || cmd == 0x3) &&
> +   if ((cmd == 0 || cmd == 0x3) &&
> (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
> DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
>   start, end);
> --
> 2.7.4
>
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Re: [PATCH] drm/amdgpu: correct emit frame size for vcn dec/enc ring

[Alex Deucher]

On Mon, May 15, 2017 at 6:16 AM, Hawking Zhang  wrote:
> only mmhub will be invalidated during vcn dec/enc vm flush
>
> Change-Id: Ide47c892c98a12c6a50918237595135fd7bf208b
> Signed-off-by: Hawking Zhang 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
> b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 6bd9bb7..8a25bba 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -,7 +,7 @@ static const struct amdgpu_ring_funcs 
> vcn_v1_0_dec_ring_vm_funcs = {
> .set_wptr = vcn_v1_0_dec_ring_set_wptr,
> .emit_frame_size =
> 2 + /* vcn_v1_0_dec_ring_emit_hdp_invalidate */
> -   34 * AMDGPU_MAX_VMHUBS + /* vcn_v1_0_dec_ring_emit_vm_flush */
> +   34 + /* vcn_v1_0_dec_ring_emit_vm_flush */
> 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
> 6,
> .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
> @@ -1139,7 +1139,7 @@ static const struct amdgpu_ring_funcs 
> vcn_v1_0_enc_ring_vm_funcs = {
> .get_wptr = vcn_v1_0_enc_ring_get_wptr,
> .set_wptr = vcn_v1_0_enc_ring_set_wptr,
> .emit_frame_size =
> -   17 * AMDGPU_MAX_VMHUBS + /* vcn_v1_0_enc_ring_emit_vm_flush */
> +   17 + /* vcn_v1_0_enc_ring_emit_vm_flush */
> 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
> 1, /* vcn_v1_0_enc_ring_insert_end */
> .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
> --
> 2.7.4
>
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Re: [PATCH] drm/amdgpu: correct vmhub for vcn dec/enc ring

[Alex Deucher]

On Mon, May 15, 2017 at 5:06 AM, Hawking Zhang  wrote:
> Change-Id: I63002c95c25cc3e2df3931d7d0e6b886b1b7e373
> Signed-off-by: Hawking Zhang 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
> b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 61a25a1..6bd9bb7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -1105,6 +1105,7 @@ static const struct amdgpu_ring_funcs 
> vcn_v1_0_dec_ring_vm_funcs = {
> .align_mask = 0xf,
> .nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
> .support_64bit_ptrs = false,
> +   .vmhub = AMDGPU_MMHUB,
> .get_rptr = vcn_v1_0_dec_ring_get_rptr,
> .get_wptr = vcn_v1_0_dec_ring_get_wptr,
> .set_wptr = vcn_v1_0_dec_ring_set_wptr,
> @@ -1133,6 +1134,7 @@ static const struct amdgpu_ring_funcs 
> vcn_v1_0_enc_ring_vm_funcs = {
> .align_mask = 0x3f,
> .nop = VCN_ENC_CMD_NO_OP,
> .support_64bit_ptrs = false,
> +   .vmhub = AMDGPU_MMHUB,
> .get_rptr = vcn_v1_0_enc_ring_get_rptr,
> .get_wptr = vcn_v1_0_enc_ring_get_wptr,
> .set_wptr = vcn_v1_0_enc_ring_set_wptr,
> --
> 2.7.4
>
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Re: [PATCH] drm/amd/display: Limit DCN to x86 arch

[Harry Wentland]

On 2017-05-20 04:13 AM, Christian König wrote:

Am 19.05.2017 um 22:28 schrieb Harry Wentland:



On 2017-05-19 04:18 PM, Dave Airlie wrote:

On 20 May 2017 at 05:36, Harry Wentland  wrote:

On 2017-05-19 11:02 AM, Christian König wrote:


Am 19.05.2017 um 16:01 schrieb Harry Wentland:


DCN bw calcs currently rely on the following gcc options:
-mhard-float -msse -mpreferred-stack-boundary=4



Mhm, price question: Why does DCN rely on the gcc options?



Tony and Dmytro can probably provide more info here but my 
understanding is
that DCN bandwidth calcs requires floating point support. This code 
comes
pretty much straight from hardware teams with a guarantee that the 
output is

good.

If we were to rewrite bandwidth calculations that guarantee would 
basically

fly out the window, which means when there's a bandwidth bug we cannot
easily get HW support unless we can prove that our calculations 
yield the
exact same results in all cases as HWs formula. Covering all 
scenarios that
bandwidth calcs covers would be quite an extensive undertaking and 
I'm sure

we'd miss important cases.


Is this only going to happen for X86 APUs? Using floating point in the
kernel requires
a lot of care to be taken, are we doing it properly?



This case would be only for AMD X86 APUs, although I wouldn't be 
surprised if we'd see something similar for discrete ASICs in the future.




Ok, that makes at least a bit more sense. On APUs we obviously know 
exactly what CPU we have.


Are you aware of anyone using our GPUs on non-X86 architectures? If 
so, I never heard of it.


Yeah, there are actually quite a number of people. That's one of the 
reasons why we still have a bunch of "#ifdef __BIG_ENDIAN" in the amdgpu 
source.




Interesting. I'd love to know more about this, like which platforms, 
etc, since sadly we've been pretty unaware of this.


I realize this is raising a lot of concern. I was concerned myself 
when I first saw this. Beside calling kernel_fpu_begin() and 
kernel_fpu_end() are there other things to watch out for?


Yeah, especially setting "-msse" is rather questionable. As far as I 
know on 64bit systems it is the default, but on 32bit systems that could 
silently break some assumptions.


Additional to that as far as I know "-msse" is just for optimization and 
that isn't performance critical code, so why exactly do we need it?




Once we enable multi-plane code this code becomes performance critical 
as I believe it gets executed when resizing an underlay surface, such as 
a video player.


I don't we've tried running without -msse, though. It might be good enough.

Harry


Christian.



Harry

Really rewriting the calcs in fixed point is the best option, maybe 
push back on

the hardware team to have a fixed point version created.

Dave.


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Re: [PATCH] drm/radeon: Fix oops upon driver load on PowerXpress laptops

[Daniel Vetter]

On Tue, May 23, 2017 at 12:00:16PM +0200, Lukas Wunner wrote:
> On Mon, May 22, 2017 at 09:24:34PM +0200, Daniel Vetter wrote:
> > On Thu, May 18, 2017 at 09:33:44PM +0200, Lukas Wunner wrote:
> > > Nicolai Stange reports the following oops which is caused by
> > > dereferencing rdev->pdev before it's subsequently set by
> > > radeon_device_init().  Fix it.
> > > 
> > >   BUG: unable to handle kernel NULL pointer dereference at 
> > > 07cb
> > >   IP: radeon_driver_load_kms+0xeb/0x230 [radeon]
> > >   PGD 0
> > >   P4D 0
> > > 
> > >   Oops:  [#1] SMP
> > >   Modules linked in: amdkfd amd_iommu_v2 i915(+) radeon(+) i2c_algo_bit 
> > > drm_kms_helper ttm e1000e drm sdhci_pci sdhci_acpi ptp sdhci crc32c_intel 
> > > serio_raw mmc_core pps_core video i2c_hid hid_plantronics
> > >   CPU: 4 PID: 389 Comm: systemd-udevd Not tainted 
> > > 4.12.0-rc1-next-20170515+ #1
> > >   Hardware name: Dell Inc. Latitude E6540/0725FP, BIOS A10 06/26/2014
> > >   task: 97d62c8f task.stack: b96f01478000
> > >   RIP: 0010:radeon_driver_load_kms+0xeb/0x230 [radeon]
> > >   RSP: 0018:b96f0147b9d0 EFLAGS: 00010246
> > >   RAX:  RBX: 97d620085000 RCX: 00610037
> > >   RDX:  RSI: 002b RDI: 
> > >   RBP: b96f0147b9e8 R08: 0002 R09: b96f0147b924
> > >   R10:  R11: 97d62edd2ec0 R12: 97d628d5c000
> > >   R13: 00610037 R14: c0698280 R15: 
> > >   FS:  7f496363d8c0() GS:97d62eb0() 
> > > knlGS:
> > >   CS:  0010 DS:  ES:  CR0: 80050033
> > >   CR2: 07cb CR3: 00022c14c000 CR4: 001406e0
> > >   Call Trace:
> > >drm_dev_register+0x146/0x1d0 [drm]
> > >drm_get_pci_dev+0x9a/0x180 [drm]
> > >radeon_pci_probe+0xb8/0xe0 [radeon]
> > >local_pci_probe+0x45/0xa0
> > >pci_device_probe+0x14f/0x1a0
> > >driver_probe_device+0x29c/0x450
> > >__driver_attach+0xdf/0xf0
> > >? driver_probe_device+0x450/0x450
> > >bus_for_each_dev+0x6c/0xc0
> > >driver_attach+0x1e/0x20
> > >bus_add_driver+0x170/0x270
> > >driver_register+0x60/0xe0
> > >? 0xc0508000
> > >__pci_register_driver+0x4c/0x50
> > >drm_pci_init+0xeb/0x100 [drm]
> > >? vga_switcheroo_register_handler+0x6a/0x90
> > >? 0xc0508000
> > >radeon_init+0x98/0xb6 [radeon]
> > >do_one_initcall+0x52/0x1a0
> > >? __vunmap+0x81/0xb0
> > >? kmem_cache_alloc_trace+0x159/0x1b0
> > >? do_init_module+0x27/0x1f8
> > >do_init_module+0x5f/0x1f8
> > >load_module+0x27ce/0x2be0
> > >SYSC_finit_module+0xdf/0x110
> > >? SYSC_finit_module+0xdf/0x110
> > >SyS_finit_module+0xe/0x10
> > >do_syscall_64+0x67/0x150
> > >entry_SYSCALL64_slow_path+0x25/0x25
> > >   RIP: 0033:0x7f4962295679
> > >   RSP: 002b:7ffdd8c4f878 EFLAGS: 0246 ORIG_RAX: 0139
> > >   RAX: ffda RBX: 55c014ed8200 RCX: 7f4962295679
> > >   RDX:  RSI: 7f4962dd19c5 RDI: 0010
> > >   RBP: 7f4962dd19c5 R08:  R09: 7ffdd8c4f990
> > >   R10: 0010 R11: 0246 R12: 
> > >   R13: 55c014ed81a0 R14: 0002 R15: 55c0149d1fca
> > >   Code: 5d 5d c3 8b 05 a7 05 14 00 49 81 cd 00 00 08 00 85 c0 74 a3 e8 e7 
> > > c0 0e 00 84 c0 74 9a 41 f7 c5 00 00 02 00 75 91 49 8b 44 24 10 <0f> b6 90 
> > > cb 07 00 00 f6 c2 20 74 1e e9 7b ff ff ff 48 8b 40 38
> > >   RIP: radeon_driver_load_kms+0xeb/0x230 [radeon] RSP: b96f0147b9d0
> > >   CR2: 07cb
> > >   ---[ end trace 89cc4ba7e569c65c ]---
> > > 
> > > Reported-by: Nicolai Stange 
> > > Fixes: 7ffb0ce31cf9 ("drm/radeon: Don't register Thunderbolt eGPU with 
> > > vga_switcheroo")
> > > Signed-off-by: Lukas Wunner 
> > > ---
> > > 
> > > Awaiting a Tested-by: from Nicolai, but it's clear this is a bug and
> > > needs to be fixed, so sending out with a proper commit message now.
> > > The bug was only introduced to radeon, not amdgpu.
> > > 
> > > @Alex Deucher: I could push this to drm-misc-fixes but then it wouldn't
> > > land before -rc3 because Sean Paul has already sent out the -rc2 pull.
> > > I notice you haven't sent out a pull for -rc2 yet, so maybe you want to
> > > take it yourself?  Whichever you prefer.  Thanks & sorry for the breakage!
> > 
> > Just noticed that this has landed already in drm-misc-fixes, without any
> > r-b or at least an ack from radeon driver folks. That's breaking the
> > drm-misc rules, we need at least an ack for small drivers (which radeon
> > really isn't) and a full reviewed-by tag on everything else.
> > 
> > Patch doesn't look wrong, so not much harm, but please follow the ground
> > rules and especially don't ever push your own patches without any peer
> > feedback.
> 
> I was aware of that rule and that the available peer feedback (Nicolai's
> Tested-by) wa

RE: [PATCH xf86-video-amdgpu] Simplify tracking of PRIME scanout pixmap

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Michel Dänzer
> Sent: Friday, May 12, 2017 6:11 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH xf86-video-amdgpu] Simplify tracking of PRIME scanout
> pixmap
> 
> From: Michel Dänzer 
> 
> Remember the shared pixmap passed to drmmode_set_scanout_pixmap for
> each
> CRTC, and just compare against that.
> 
> Fixes leaving stale entries in ScreenRec::pixmap_dirty_list under some
> circumstances, which would usually result in use-after-free and a crash
> down the line.
> 
> (Ported from radeon commit 7dc68e26755466f9056f8c72195ab8690660693d)
> 
> Signed-off-by: Michel Dänzer 

Reviewed-by: Alex Deucher 

> ---
>  src/amdgpu_kms.c  |  7 ++-
>  src/drmmode_display.c | 21 +++--
>  src/drmmode_display.h |  3 +++
>  3 files changed, 16 insertions(+), 15 deletions(-)
> 
> diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
> index 4df81f993..a418cf9d3 100644
> --- a/src/amdgpu_kms.c
> +++ b/src/amdgpu_kms.c
> @@ -562,8 +562,7 @@ amdgpu_prime_dirty_to_crtc(PixmapDirtyUpdatePtr
> dirty)
>   xf86CrtcPtr xf86_crtc = xf86_config->crtc[c];
>   drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc-
> >driver_private;
> 
> - if (drmmode_crtc->scanout[0].pixmap == dirty->slave_dst ||
> - drmmode_crtc->scanout[1].pixmap == dirty-
> >slave_dst)
> + if (drmmode_crtc->prime_scanout_pixmap == dirty->src)
>   return xf86_crtc;
>   }
> 
> @@ -576,13 +575,11 @@ amdgpu_prime_scanout_do_update(xf86CrtcPtr
> crtc, unsigned scanout_id)
>   ScrnInfoPtr scrn = crtc->scrn;
>   ScreenPtr screen = scrn->pScreen;
>   drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
> - PixmapPtr scanoutpix = crtc->randr_crtc->scanout_pixmap;
>   PixmapDirtyUpdatePtr dirty;
>   Bool ret = FALSE;
> 
>   xorg_list_for_each_entry(dirty, &screen->pixmap_dirty_list, ent) {
> - if (dirty->src == scanoutpix && dirty->slave_dst ==
> - drmmode_crtc->scanout[scanout_id ^ drmmode_crtc-
> >tear_free].pixmap) {
> + if (dirty->src == drmmode_crtc->prime_scanout_pixmap) {
>   RegionPtr region;
> 
>   if (master_has_sync_shared_pixmap(scrn, dirty))
> diff --git a/src/drmmode_display.c b/src/drmmode_display.c
> index 9996d2f70..add8287a0 100644
> --- a/src/drmmode_display.c
> +++ b/src/drmmode_display.c
> @@ -681,9 +681,7 @@ drmmode_crtc_prime_scanout_update(xf86CrtcPtr
> crtc, DisplayModePtr mode,
> 
>   xorg_list_for_each_entry(dirty, &screen->pixmap_dirty_list,
>ent) {
> - if (dirty->src == crtc->randr_crtc->scanout_pixmap
> &&
> - dirty->slave_dst ==
> - drmmode_crtc->scanout[drmmode_crtc-
> >scanout_id].pixmap) {
> + if (dirty->src == drmmode_crtc-
> >prime_scanout_pixmap) {
>   dirty->slave_dst =
>   drmmode_crtc-
> >scanout[scanout_id].pixmap;
>   break;
> @@ -838,7 +836,7 @@ drmmode_set_mode_major(xf86CrtcPtr crtc,
> DisplayModePtr mode,
> 
>   fb_id = drmmode->fb_id;
>  #ifdef AMDGPU_PIXMAP_SHARING
> - if (crtc->randr_crtc && crtc->randr_crtc->scanout_pixmap) {
> + if (drmmode_crtc->prime_scanout_pixmap) {
>   drmmode_crtc_prime_scanout_update(crtc, mode,
> scanout_id,
> &fb_id, &x, &y);
>   } else
> @@ -1242,14 +1240,15 @@ static Bool
> drmmode_set_scanout_pixmap(xf86CrtcPtr crtc, PixmapPtr ppix)
>   PixmapDirtyUpdatePtr dirty;
> 
>   xorg_list_for_each_entry(dirty, &screen->pixmap_dirty_list, ent) {
> - if (dirty->slave_dst != drmmode_crtc-
> >scanout[scanout_id].pixmap)
> - continue;
> -
> - PixmapStopDirtyTracking(dirty->src, dirty->slave_dst);
> - drmmode_crtc_scanout_free(drmmode_crtc);
> - break;
> + if (dirty->src == drmmode_crtc->prime_scanout_pixmap) {
> + PixmapStopDirtyTracking(dirty->src, dirty-
> >slave_dst);
> + break;
> + }
>   }
> 
> + drmmode_crtc_scanout_free(drmmode_crtc);
> + drmmode_crtc->prime_scanout_pixmap = NULL;
> +
>   if (!ppix)
>   return TRUE;
> 
> @@ -1266,6 +1265,8 @@ static Bool
> drmmode_set_scanout_pixmap(xf86CrtcPtr crtc, PixmapPtr ppix)
>   return FALSE;
>   }
> 
> + drmmode_crtc->prime_scanout_pixmap = ppix;
> +
>  #ifdef HAS_DIRTYTRACKING_ROTATION
>   PixmapStartDirtyTracking(ppix, drmmode_crtc-
> >scanout[scanout_id].pixmap,
>0, 0, 0, 0, RR_Rotate_0);
> diff --git a/src/drmmode_display.h b/src/drmmode_display.h
> index

RE: [PATCH 1/1] amdgpu: move asic id table to a separate file

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Michel Dänzer
> Sent: Thursday, May 11, 2017 8:50 PM
> To: Li, Samuel
> Cc: amd-gfx@lists.freedesktop.org; Yuan, Xiaojie
> Subject: Re: [PATCH 1/1] amdgpu: move asic id table to a separate file
> 
> On 12/05/17 06:13 AM, Li, Samuel wrote:
> > Submitted a request to create a new repo on freedesktop.
> 
> What's the point of having a separate repository upstream? Can't we just
> keep it in the libdrm repository?

There's no need for a separate repo upstream.  It's purely to aid internal 
packaging.

Alex

> 
> 
> --
> Earthling Michel Dänzer   |   http://www.amd.com
> Libre software enthusiast | Mesa and X developer
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Re: [PATCH 0/3] drm/amdgpu: Tweaks for high pressure on CPU visible VRAM

[Marek Olšák]

On Tue, May 23, 2017 at 2:45 AM, Michel Dänzer  wrote:
> On 22/05/17 07:09 PM, Marek Olšák wrote:
>> On Mon, May 22, 2017 at 12:00 PM, Michel Dänzer  wrote:
>>> On 20/05/17 06:26 PM, Marek Olšák wrote:
 On May 20, 2017 3:26 AM, "Michel Dänzer" >>> > wrote:

 On 20/05/17 01:14 AM, Marek Olšák wrote:
 > Hi Michel,
 >
 > I've applied your series

 Thanks for testing it.

 > and it doesn't help with low Dirt Rally performance on Fiji. I see 
 TTM
 > buffer moves at 800MB/s and many VRAM page faults.

 Did you see this:

 >> Note that there's only little if any improvement of the average
 framerate
 >> reported, but the minimum framerate as seen on the HUD goes from
 ~10 fps
 >> to ~17.

 I.e. it mostly affects the minimum framerate and smoothness for me
 as well.


 Without the series, I get 70 average fps. With the series, I get 30
 average fps. That might just be random bad luck. I don't know.
>>>
>>> Hmm, yeah, maybe that was just one of the random slowdowns you've been
>>> talking about in other threads and on IRC?
>>>
>>> I can't reproduce any slowdown with these patches, even leaving visible
>>> VRAM size at 256 MB.
>>
>> The random slowdowns with Dirt Rally are only caused by the pressure
>> on visible VRAM. This whole thread is about those random slowdowns.
>
> No, this thread is about the scenario described in the cover letter of
> this patch series.
>
>
>> If you're saying "maybe it was just one of the random slowdowns", you're
>> saying "maybe it was just the visible VRAM pressure". It's only
>> random with Dirt Rally, which makes it difficult to believe statements
>> such as "I can't reproduce any slowdown".
>
> I could say the same thing about you seeing random slowdowns... I've
> never seen that, I had to artificially limit the size of visible VRAM to
> 64 MB to make it significantly affect the benchmark result.
>
> How many times do you need to run the benchmark on average to hit a
> random slowdown? Which desktop environment and other X clients are
> running during the benchmark? Which tab is active in the Steam window
> while the benchmark runs?
>
> In my case, it's only xfwm4, xterm and steam on the Dirt Rally page in
> the library.

Ubuntu Unity, Steam small mode (there are no tabs), Ultra settings in
Dirt Rally.

Every single time I run the game with this series, I get 700-1000MB/s
of TTM BO moves. There doesn't seem to be any randomness.

It was better without this series. (meaning it was sometimes OK, sometimes bad)

Marek
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Re: [PATCH] drm/radeon: Fix oops upon driver load on PowerXpress laptops

[Christian König]

Am 23.05.2017 um 12:14 schrieb Lukas Wunner:

On Tue, May 23, 2017 at 09:32:38AM +0200, Christian König wrote:

Am 23.05.2017 um 05:55 schrieb Michel Dänzer:

On 23/05/17 12:50 PM, Lukas Wunner wrote:

On Tue, May 23, 2017 at 12:09:49PM +0900, Michel Dänzer wrote:

On 22/05/17 11:04 PM, Lukas Wunner wrote:

On Sun, May 21, 2017 at 09:31:09AM +0200, Nicolai Stange wrote:

On Thu, May 18 2017, Lukas Wunner wrote:

[snip]

Reported-by: Nicolai Stange 
Fixes: 7ffb0ce31cf9 ("drm/radeon: Don't register Thunderbolt eGPU with 
vga_switcheroo")
Signed-off-by: Lukas Wunner 
---

Awaiting a Tested-by: from Nicolai, but it's clear this is a bug and
needs to be fixed, so sending out with a proper commit message now.
The bug was only introduced to radeon, not amdgpu.

Tested-by: Nicolai Stange 

Thanks for the quick fix!


@Alex Deucher: I could push this to drm-misc-fixes but then it wouldn't
land before -rc3 because Sean Paul has already sent out the -rc2 pull.
I notice you haven't sent out a pull for -rc2 yet, so maybe you want to
take it yourself?  Whichever you prefer.  Thanks & sorry for the breakage!

I've learned this morning that Alex is on vacation.

Christian König is standing in for Alex.

By his own account, he already has "all hands full replacing him [Alex]",
explicitly asked Daniel to merge an amdgpu patch through drm-misc-next for
this reason and lacks permission to update branches in Alex' repo on fdo:

"One lesson learned from the past week is that Alex needs to stop using
his personal repository on fdo.
We were asked a couple of times if I couldn't update a branch there from
different directions, which we obviously can't do."

https://lists.freedesktop.org/archives/dri-devel/2017-May/142376.html
https://lists.freedesktop.org/archives/dri-devel/2017-May/142380.html

The important point being that Christian reviewed that patch and
explicitly asked Daniel to pick it up.

Wow, wait a second. I'm just catching up on this thread.

Lukas didn't committed the patch to drm-misc without a review, didn't you?

I was intentionally holding back a rb because that isn't my field of
expertise and I was only briefly involved in the original patch.

It would have been helpful if you had communicated that, I explicitly
asked Alex which tree he'd prefer merging through.  If you're his
stand-in then why didn't you reply?


Alex will be back before the weekend and probably sending another fixes 
pull for the rc.


PowerXpress is not my field of expertise, but Alex is deeply into so 
I've ignore that issue for now.



I was already wondering why you took the time to reply to Daniel's patch
(which went into drm-misc-next, so queued for 4.13), but didn't reply
at all to my patch (which affects 4.12, so arguably has higher priority).

I'd dispute that the issue at hand requires specific domain knowlege,
it's a trivial dereference of a pointer before it's set.


After taking the time this morning to take a look at the patch and the 
original code I can confirm that it is indeed completely trivial.



Alex should
be back by the end of the week, so no need for a rush like that.

End of the week means the patch would miss another rc cycle, and the
DRM subsystem is getting enough criticism for causing regressions as
it is, isn't it? :-(


Yeah, but in this case just ping me and not commit without any peer review.

For stuff like this we will get even more criticism from Linus than 
causing regressions.


Anyway no harm done, let's just merge this one through drm-misc-fixes 
and everything is fine.


Regards,
Christian.



Thanks,

Lukas



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Re: [PATCH] drm/radeon: Fix oops upon driver load on PowerXpress laptops

[Lukas Wunner]

On Tue, May 23, 2017 at 09:32:38AM +0200, Christian König wrote:
> Am 23.05.2017 um 05:55 schrieb Michel Dänzer:
> >On 23/05/17 12:50 PM, Lukas Wunner wrote:
> >>On Tue, May 23, 2017 at 12:09:49PM +0900, Michel Dänzer wrote:
> >>>On 22/05/17 11:04 PM, Lukas Wunner wrote:
> On Sun, May 21, 2017 at 09:31:09AM +0200, Nicolai Stange wrote:
> >On Thu, May 18 2017, Lukas Wunner wrote:
> [snip]
> >>Reported-by: Nicolai Stange 
> >>Fixes: 7ffb0ce31cf9 ("drm/radeon: Don't register Thunderbolt eGPU with 
> >>vga_switcheroo")
> >>Signed-off-by: Lukas Wunner 
> >>---
> >>
> >>Awaiting a Tested-by: from Nicolai, but it's clear this is a bug and
> >>needs to be fixed, so sending out with a proper commit message now.
> >>The bug was only introduced to radeon, not amdgpu.
> >Tested-by: Nicolai Stange 
> >
> >Thanks for the quick fix!
> >
> >>@Alex Deucher: I could push this to drm-misc-fixes but then it wouldn't
> >>land before -rc3 because Sean Paul has already sent out the -rc2 pull.
> >>I notice you haven't sent out a pull for -rc2 yet, so maybe you want to
> >>take it yourself?  Whichever you prefer.  Thanks & sorry for the 
> >>breakage!
> I've learned this morning that Alex is on vacation.
> >>>Christian König is standing in for Alex.
> >>By his own account, he already has "all hands full replacing him [Alex]",
> >>explicitly asked Daniel to merge an amdgpu patch through drm-misc-next for
> >>this reason and lacks permission to update branches in Alex' repo on fdo:
> >>
> >>"One lesson learned from the past week is that Alex needs to stop using
> >>his personal repository on fdo.
> >>We were asked a couple of times if I couldn't update a branch there from
> >>different directions, which we obviously can't do."
> >>
> >>https://lists.freedesktop.org/archives/dri-devel/2017-May/142376.html
> >>https://lists.freedesktop.org/archives/dri-devel/2017-May/142380.html
> >The important point being that Christian reviewed that patch and
> >explicitly asked Daniel to pick it up.
> 
> Wow, wait a second. I'm just catching up on this thread.
> 
> Lukas didn't committed the patch to drm-misc without a review, didn't you?
> 
> I was intentionally holding back a rb because that isn't my field of
> expertise and I was only briefly involved in the original patch.

It would have been helpful if you had communicated that, I explicitly
asked Alex which tree he'd prefer merging through.  If you're his
stand-in then why didn't you reply?

I was already wondering why you took the time to reply to Daniel's patch
(which went into drm-misc-next, so queued for 4.13), but didn't reply
at all to my patch (which affects 4.12, so arguably has higher priority).

I'd dispute that the issue at hand requires specific domain knowlege,
it's a trivial dereference of a pointer before it's set.


> Alex should
> be back by the end of the week, so no need for a rush like that.

End of the week means the patch would miss another rc cycle, and the
DRM subsystem is getting enough criticism for causing regressions as
it is, isn't it? :-(

Thanks,

Lukas
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Re: [PATCH] drm/radeon: Fix oops upon driver load on PowerXpress laptops

[Lukas Wunner]

On Mon, May 22, 2017 at 09:24:34PM +0200, Daniel Vetter wrote:
> On Thu, May 18, 2017 at 09:33:44PM +0200, Lukas Wunner wrote:
> > Nicolai Stange reports the following oops which is caused by
> > dereferencing rdev->pdev before it's subsequently set by
> > radeon_device_init().  Fix it.
> > 
> >   BUG: unable to handle kernel NULL pointer dereference at 07cb
> >   IP: radeon_driver_load_kms+0xeb/0x230 [radeon]
> >   PGD 0
> >   P4D 0
> > 
> >   Oops:  [#1] SMP
> >   Modules linked in: amdkfd amd_iommu_v2 i915(+) radeon(+) i2c_algo_bit 
> > drm_kms_helper ttm e1000e drm sdhci_pci sdhci_acpi ptp sdhci crc32c_intel 
> > serio_raw mmc_core pps_core video i2c_hid hid_plantronics
> >   CPU: 4 PID: 389 Comm: systemd-udevd Not tainted 4.12.0-rc1-next-20170515+ 
> > #1
> >   Hardware name: Dell Inc. Latitude E6540/0725FP, BIOS A10 06/26/2014
> >   task: 97d62c8f task.stack: b96f01478000
> >   RIP: 0010:radeon_driver_load_kms+0xeb/0x230 [radeon]
> >   RSP: 0018:b96f0147b9d0 EFLAGS: 00010246
> >   RAX:  RBX: 97d620085000 RCX: 00610037
> >   RDX:  RSI: 002b RDI: 
> >   RBP: b96f0147b9e8 R08: 0002 R09: b96f0147b924
> >   R10:  R11: 97d62edd2ec0 R12: 97d628d5c000
> >   R13: 00610037 R14: c0698280 R15: 
> >   FS:  7f496363d8c0() GS:97d62eb0() 
> > knlGS:
> >   CS:  0010 DS:  ES:  CR0: 80050033
> >   CR2: 07cb CR3: 00022c14c000 CR4: 001406e0
> >   Call Trace:
> >drm_dev_register+0x146/0x1d0 [drm]
> >drm_get_pci_dev+0x9a/0x180 [drm]
> >radeon_pci_probe+0xb8/0xe0 [radeon]
> >local_pci_probe+0x45/0xa0
> >pci_device_probe+0x14f/0x1a0
> >driver_probe_device+0x29c/0x450
> >__driver_attach+0xdf/0xf0
> >? driver_probe_device+0x450/0x450
> >bus_for_each_dev+0x6c/0xc0
> >driver_attach+0x1e/0x20
> >bus_add_driver+0x170/0x270
> >driver_register+0x60/0xe0
> >? 0xc0508000
> >__pci_register_driver+0x4c/0x50
> >drm_pci_init+0xeb/0x100 [drm]
> >? vga_switcheroo_register_handler+0x6a/0x90
> >? 0xc0508000
> >radeon_init+0x98/0xb6 [radeon]
> >do_one_initcall+0x52/0x1a0
> >? __vunmap+0x81/0xb0
> >? kmem_cache_alloc_trace+0x159/0x1b0
> >? do_init_module+0x27/0x1f8
> >do_init_module+0x5f/0x1f8
> >load_module+0x27ce/0x2be0
> >SYSC_finit_module+0xdf/0x110
> >? SYSC_finit_module+0xdf/0x110
> >SyS_finit_module+0xe/0x10
> >do_syscall_64+0x67/0x150
> >entry_SYSCALL64_slow_path+0x25/0x25
> >   RIP: 0033:0x7f4962295679
> >   RSP: 002b:7ffdd8c4f878 EFLAGS: 0246 ORIG_RAX: 0139
> >   RAX: ffda RBX: 55c014ed8200 RCX: 7f4962295679
> >   RDX:  RSI: 7f4962dd19c5 RDI: 0010
> >   RBP: 7f4962dd19c5 R08:  R09: 7ffdd8c4f990
> >   R10: 0010 R11: 0246 R12: 
> >   R13: 55c014ed81a0 R14: 0002 R15: 55c0149d1fca
> >   Code: 5d 5d c3 8b 05 a7 05 14 00 49 81 cd 00 00 08 00 85 c0 74 a3 e8 e7 
> > c0 0e 00 84 c0 74 9a 41 f7 c5 00 00 02 00 75 91 49 8b 44 24 10 <0f> b6 90 
> > cb 07 00 00 f6 c2 20 74 1e e9 7b ff ff ff 48 8b 40 38
> >   RIP: radeon_driver_load_kms+0xeb/0x230 [radeon] RSP: b96f0147b9d0
> >   CR2: 07cb
> >   ---[ end trace 89cc4ba7e569c65c ]---
> > 
> > Reported-by: Nicolai Stange 
> > Fixes: 7ffb0ce31cf9 ("drm/radeon: Don't register Thunderbolt eGPU with 
> > vga_switcheroo")
> > Signed-off-by: Lukas Wunner 
> > ---
> > 
> > Awaiting a Tested-by: from Nicolai, but it's clear this is a bug and
> > needs to be fixed, so sending out with a proper commit message now.
> > The bug was only introduced to radeon, not amdgpu.
> > 
> > @Alex Deucher: I could push this to drm-misc-fixes but then it wouldn't
> > land before -rc3 because Sean Paul has already sent out the -rc2 pull.
> > I notice you haven't sent out a pull for -rc2 yet, so maybe you want to
> > take it yourself?  Whichever you prefer.  Thanks & sorry for the breakage!
> 
> Just noticed that this has landed already in drm-misc-fixes, without any
> r-b or at least an ack from radeon driver folks. That's breaking the
> drm-misc rules, we need at least an ack for small drivers (which radeon
> really isn't) and a full reviewed-by tag on everything else.
> 
> Patch doesn't look wrong, so not much harm, but please follow the ground
> rules and especially don't ever push your own patches without any peer
> feedback.

I was aware of that rule and that the available peer feedback (Nicolai's
Tested-by) was thin.  I misinterpreted Christian's remark that he has
"all hands full replacing" Alex such that he is swamped in work and
didn't get the chance to look at my patch so far.  Christian was already
cc'ed on Nicolai's regression report and on every single e-mail that
fo

Re: [PATCH] drm/radeon: Fix oops upon driver load on PowerXpress laptops

[Lukas Wunner]

On Mon, May 22, 2017 at 03:35:48PM -0400, Sean Paul wrote:
> On Mon, May 22, 2017 at 04:04:07PM +0200, Lukas Wunner wrote:
> > On Sun, May 21, 2017 at 09:31:09AM +0200, Nicolai Stange wrote:
> > > On Thu, May 18 2017, Lukas Wunner wrote:
> > [snip]
> > > > Reported-by: Nicolai Stange 
> > > > Fixes: 7ffb0ce31cf9 ("drm/radeon: Don't register Thunderbolt eGPU with 
> > > > vga_switcheroo")
> > > > Signed-off-by: Lukas Wunner 
> > > > ---
> > > >
> > > > Awaiting a Tested-by: from Nicolai, but it's clear this is a bug and
> > > > needs to be fixed, so sending out with a proper commit message now.
> > > > The bug was only introduced to radeon, not amdgpu.
> > > 
> > > Tested-by: Nicolai Stange 
> > > 
> > > Thanks for the quick fix!
> > >
> > > > @Alex Deucher: I could push this to drm-misc-fixes but then it wouldn't
> > > > land before -rc3 because Sean Paul has already sent out the -rc2 pull.
> > > > I notice you haven't sent out a pull for -rc2 yet, so maybe you want to
> > > > take it yourself?  Whichever you prefer.  Thanks & sorry for the 
> > > > breakage!
> > 
> > I've learned this morning that Alex is on vacation.  I've pushed
> > the patch to drm-misc-fixes so that the issue is fixed in 4.12-rc3.
> > 
> > @Sean Paul: I've fast-forwarded to 4.12-rc2 before pushing, please
> > shout if I've done anything wrong.  First time I'm doing this.
> 
> No shouting, but a heads-up on IRC is probably warranted for both pushing a
> patch without R-b and fast-forwarding one of the branches.

Thanks, noted.  I'm not paid for work on the DRM subsystem, so I have to
do this during breaks at $DAYJOB where I have no access to IRC, but I will
ask via e-mail in the future before going out on a limb.

Not being able to dedicate my full attention to this all the time is also
the reason why it's hard for me to get the timing perfect:  I had already
submitted a fix before you sent out your -rc2 pull and I would have hated
missing another rc cycle, yet wasn't sure when exactly you were going to
send out your -rc3 pull this week and whether I would be able to carve out
enough time to push the patch before that date without hurriedly making
major mistakes.

Kind regards,

Lukas
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Re: [PATCH] drm/radeon: Fix oops upon driver load on PowerXpress laptops

[Christian König]

Am 23.05.2017 um 09:36 schrieb Daniel Vetter:

On Tue, May 23, 2017 at 09:32:38AM +0200, Christian König wrote:

Am 23.05.2017 um 05:55 schrieb Michel Dänzer:

On 23/05/17 12:50 PM, Lukas Wunner wrote:

On Tue, May 23, 2017 at 12:09:49PM +0900, Michel Dänzer wrote:

On 22/05/17 11:04 PM, Lukas Wunner wrote:

On Sun, May 21, 2017 at 09:31:09AM +0200, Nicolai Stange wrote:

On Thu, May 18 2017, Lukas Wunner wrote:

[snip]

Reported-by: Nicolai Stange 
Fixes: 7ffb0ce31cf9 ("drm/radeon: Don't register Thunderbolt eGPU with 
vga_switcheroo")
Signed-off-by: Lukas Wunner 
---

Awaiting a Tested-by: from Nicolai, but it's clear this is a bug and
needs to be fixed, so sending out with a proper commit message now.
The bug was only introduced to radeon, not amdgpu.

Tested-by: Nicolai Stange 

Thanks for the quick fix!


@Alex Deucher: I could push this to drm-misc-fixes but then it wouldn't
land before -rc3 because Sean Paul has already sent out the -rc2 pull.
I notice you haven't sent out a pull for -rc2 yet, so maybe you want to
take it yourself?  Whichever you prefer.  Thanks & sorry for the breakage!

I've learned this morning that Alex is on vacation.

Christian König is standing in for Alex.

By his own account, he already has "all hands full replacing him [Alex]",
explicitly asked Daniel to merge an amdgpu patch through drm-misc-next for
this reason and lacks permission to update branches in Alex' repo on fdo:

"One lesson learned from the past week is that Alex needs to stop using
his personal repository on fdo.
We were asked a couple of times if I couldn't update a branch there from
different directions, which we obviously can't do."

https://lists.freedesktop.org/archives/dri-devel/2017-May/142376.html
https://lists.freedesktop.org/archives/dri-devel/2017-May/142380.html

The important point being that Christian reviewed that patch and
explicitly asked Daniel to pick it up.

Wow, wait a second. I'm just catching up on this thread.

Lukas didn't committed the patch to drm-misc without a review, didn't you?

I was intentionally holding back a rb because that isn't my field of
expertise and I was only briefly involved in the original patch. Alex should
be back by the end of the week, so no need for a rush like that.

Daniels patch was a global cleanup of include path done by search and
replace a complete different story.

Want me to drop the patch until Alex is back? We're generally trying
really hard to refrain from rebasing drm-misc branches, but for -fixes
it's doable (since much less patch traffic there).


No, that would probably hurt more than it helps.

The patch is trivial and I just double checked the code and it should be 
fine.


Christian.

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Re: [PATCH] drm/radeon: Fix oops upon driver load on PowerXpress laptops

[Daniel Vetter]

On Tue, May 23, 2017 at 09:36:44AM +0200, Daniel Vetter wrote:
> On Tue, May 23, 2017 at 09:32:38AM +0200, Christian König wrote:
> > Am 23.05.2017 um 05:55 schrieb Michel Dänzer:
> > > On 23/05/17 12:50 PM, Lukas Wunner wrote:
> > > > On Tue, May 23, 2017 at 12:09:49PM +0900, Michel Dänzer wrote:
> > > > > On 22/05/17 11:04 PM, Lukas Wunner wrote:
> > > > > > On Sun, May 21, 2017 at 09:31:09AM +0200, Nicolai Stange wrote:
> > > > > > > On Thu, May 18 2017, Lukas Wunner wrote:
> > > > > > [snip]
> > > > > > > > Reported-by: Nicolai Stange 
> > > > > > > > Fixes: 7ffb0ce31cf9 ("drm/radeon: Don't register Thunderbolt 
> > > > > > > > eGPU with vga_switcheroo")
> > > > > > > > Signed-off-by: Lukas Wunner 
> > > > > > > > ---
> > > > > > > > 
> > > > > > > > Awaiting a Tested-by: from Nicolai, but it's clear this is a 
> > > > > > > > bug and
> > > > > > > > needs to be fixed, so sending out with a proper commit message 
> > > > > > > > now.
> > > > > > > > The bug was only introduced to radeon, not amdgpu.
> > > > > > > Tested-by: Nicolai Stange 
> > > > > > > 
> > > > > > > Thanks for the quick fix!
> > > > > > > 
> > > > > > > > @Alex Deucher: I could push this to drm-misc-fixes but then it 
> > > > > > > > wouldn't
> > > > > > > > land before -rc3 because Sean Paul has already sent out the 
> > > > > > > > -rc2 pull.
> > > > > > > > I notice you haven't sent out a pull for -rc2 yet, so maybe you 
> > > > > > > > want to
> > > > > > > > take it yourself?  Whichever you prefer.  Thanks & sorry for 
> > > > > > > > the breakage!
> > > > > > I've learned this morning that Alex is on vacation.
> > > > > Christian König is standing in for Alex.
> > > > By his own account, he already has "all hands full replacing him 
> > > > [Alex]",
> > > > explicitly asked Daniel to merge an amdgpu patch through drm-misc-next 
> > > > for
> > > > this reason and lacks permission to update branches in Alex' repo on 
> > > > fdo:
> > > > 
> > > > "One lesson learned from the past week is that Alex needs to stop using
> > > > his personal repository on fdo.
> > > > We were asked a couple of times if I couldn't update a branch there from
> > > > different directions, which we obviously can't do."
> > > > 
> > > > https://lists.freedesktop.org/archives/dri-devel/2017-May/142376.html
> > > > https://lists.freedesktop.org/archives/dri-devel/2017-May/142380.html
> > > The important point being that Christian reviewed that patch and
> > > explicitly asked Daniel to pick it up.
> > 
> > Wow, wait a second. I'm just catching up on this thread.
> > 
> > Lukas didn't committed the patch to drm-misc without a review, didn't you?
> > 
> > I was intentionally holding back a rb because that isn't my field of
> > expertise and I was only briefly involved in the original patch. Alex should
> > be back by the end of the week, so no need for a rush like that.
> > 
> > Daniels patch was a global cleanup of include path done by search and
> > replace a complete different story.
> 
> Want me to drop the patch until Alex is back? We're generally trying
> really hard to refrain from rebasing drm-misc branches, but for -fixes
> it's doable (since much less patch traffic there).

Also, I guess putting this as requirement number one in the drm-misc docs
wasn't visible enough:

"Patch is properly reviewed or at least Ack, i.e. don't just push your own
stuff directly."

It would be nice if we could check this somehow using scripting, but since
we add the r-b/a-b tags only after they're applied that's a bit hard to
pull off. Maybe a sanity check when pushing that all the new patches
authored by the committer have an r-b/a-b would be useful ... Lukas, can
you pls look into that?

Thanks, Daniel
-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH] drm/radeon: Fix oops upon driver load on PowerXpress laptops

[Daniel Vetter]

On Tue, May 23, 2017 at 09:32:38AM +0200, Christian König wrote:
> Am 23.05.2017 um 05:55 schrieb Michel Dänzer:
> > On 23/05/17 12:50 PM, Lukas Wunner wrote:
> > > On Tue, May 23, 2017 at 12:09:49PM +0900, Michel Dänzer wrote:
> > > > On 22/05/17 11:04 PM, Lukas Wunner wrote:
> > > > > On Sun, May 21, 2017 at 09:31:09AM +0200, Nicolai Stange wrote:
> > > > > > On Thu, May 18 2017, Lukas Wunner wrote:
> > > > > [snip]
> > > > > > > Reported-by: Nicolai Stange 
> > > > > > > Fixes: 7ffb0ce31cf9 ("drm/radeon: Don't register Thunderbolt eGPU 
> > > > > > > with vga_switcheroo")
> > > > > > > Signed-off-by: Lukas Wunner 
> > > > > > > ---
> > > > > > > 
> > > > > > > Awaiting a Tested-by: from Nicolai, but it's clear this is a bug 
> > > > > > > and
> > > > > > > needs to be fixed, so sending out with a proper commit message 
> > > > > > > now.
> > > > > > > The bug was only introduced to radeon, not amdgpu.
> > > > > > Tested-by: Nicolai Stange 
> > > > > > 
> > > > > > Thanks for the quick fix!
> > > > > > 
> > > > > > > @Alex Deucher: I could push this to drm-misc-fixes but then it 
> > > > > > > wouldn't
> > > > > > > land before -rc3 because Sean Paul has already sent out the -rc2 
> > > > > > > pull.
> > > > > > > I notice you haven't sent out a pull for -rc2 yet, so maybe you 
> > > > > > > want to
> > > > > > > take it yourself?  Whichever you prefer.  Thanks & sorry for the 
> > > > > > > breakage!
> > > > > I've learned this morning that Alex is on vacation.
> > > > Christian König is standing in for Alex.
> > > By his own account, he already has "all hands full replacing him [Alex]",
> > > explicitly asked Daniel to merge an amdgpu patch through drm-misc-next for
> > > this reason and lacks permission to update branches in Alex' repo on fdo:
> > > 
> > > "One lesson learned from the past week is that Alex needs to stop using
> > > his personal repository on fdo.
> > > We were asked a couple of times if I couldn't update a branch there from
> > > different directions, which we obviously can't do."
> > > 
> > > https://lists.freedesktop.org/archives/dri-devel/2017-May/142376.html
> > > https://lists.freedesktop.org/archives/dri-devel/2017-May/142380.html
> > The important point being that Christian reviewed that patch and
> > explicitly asked Daniel to pick it up.
> 
> Wow, wait a second. I'm just catching up on this thread.
> 
> Lukas didn't committed the patch to drm-misc without a review, didn't you?
> 
> I was intentionally holding back a rb because that isn't my field of
> expertise and I was only briefly involved in the original patch. Alex should
> be back by the end of the week, so no need for a rush like that.
> 
> Daniels patch was a global cleanup of include path done by search and
> replace a complete different story.

Want me to drop the patch until Alex is back? We're generally trying
really hard to refrain from rebasing drm-misc branches, but for -fixes
it's doable (since much less patch traffic there).
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH] drm/radeon: Fix oops upon driver load on PowerXpress laptops

[Christian König]

Am 23.05.2017 um 05:55 schrieb Michel Dänzer:

On 23/05/17 12:50 PM, Lukas Wunner wrote:

On Tue, May 23, 2017 at 12:09:49PM +0900, Michel Dänzer wrote:

On 22/05/17 11:04 PM, Lukas Wunner wrote:

On Sun, May 21, 2017 at 09:31:09AM +0200, Nicolai Stange wrote:

On Thu, May 18 2017, Lukas Wunner wrote:

[snip]

Reported-by: Nicolai Stange 
Fixes: 7ffb0ce31cf9 ("drm/radeon: Don't register Thunderbolt eGPU with 
vga_switcheroo")
Signed-off-by: Lukas Wunner 
---

Awaiting a Tested-by: from Nicolai, but it's clear this is a bug and
needs to be fixed, so sending out with a proper commit message now.
The bug was only introduced to radeon, not amdgpu.

Tested-by: Nicolai Stange 

Thanks for the quick fix!


@Alex Deucher: I could push this to drm-misc-fixes but then it wouldn't
land before -rc3 because Sean Paul has already sent out the -rc2 pull.
I notice you haven't sent out a pull for -rc2 yet, so maybe you want to
take it yourself?  Whichever you prefer.  Thanks & sorry for the breakage!

I've learned this morning that Alex is on vacation.

Christian König is standing in for Alex.

By his own account, he already has "all hands full replacing him [Alex]",
explicitly asked Daniel to merge an amdgpu patch through drm-misc-next for
this reason and lacks permission to update branches in Alex' repo on fdo:

"One lesson learned from the past week is that Alex needs to stop using
his personal repository on fdo.
We were asked a couple of times if I couldn't update a branch there from
different directions, which we obviously can't do."

https://lists.freedesktop.org/archives/dri-devel/2017-May/142376.html
https://lists.freedesktop.org/archives/dri-devel/2017-May/142380.html

The important point being that Christian reviewed that patch and
explicitly asked Daniel to pick it up.


Wow, wait a second. I'm just catching up on this thread.

Lukas didn't committed the patch to drm-misc without a review, didn't you?

I was intentionally holding back a rb because that isn't my field of 
expertise and I was only briefly involved in the original patch. Alex 
should be back by the end of the week, so no need for a rush like that.


Daniels patch was a global cleanup of include path done by search and 
replace a complete different story.


Regards,
Christian.
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