[PATCH 3/3] drm/amd/display: Fix copyright notice in DC code
[Why & How] Fix incomplete copyright notice in DC code. Signed-off-by: Stylon Wang --- .../drm/amd/display/dc/dcn303/dcn303_dccg.h | 18 ++ .../drm/amd/display/dc/dcn303/dcn303_init.c | 18 ++ .../drm/amd/display/dc/dcn303/dcn303_init.h | 18 ++ .../amd/display/dc/dcn303/dcn303_resource.c | 18 ++ .../amd/display/dc/dcn303/dcn303_resource.h | 18 ++ drivers/gpu/drm/amd/display/dc/dcn31/Makefile | 2 +- .../gpu/drm/amd/display/dc/dcn35/dcn35_dpp.c | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_dpp.h | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_dsc.c | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_dsc.h | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_dwb.h | 2 ++ .../drm/amd/display/dc/dcn35/dcn35_hubbub.c | 2 ++ .../drm/amd/display/dc/dcn35/dcn35_hubbub.h | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_hubp.c | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_hubp.h | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_init.c | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_init.h | 2 ++ .../drm/amd/display/dc/dcn35/dcn35_mmhubbub.c | 2 ++ .../drm/amd/display/dc/dcn35/dcn35_mmhubbub.h | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_opp.c | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_opp.h | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_optc.c | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_optc.h | 2 ++ .../drm/amd/display/dc/dcn35/dcn35_pg_cntl.c | 2 ++ .../drm/amd/display/dc/dcn35/dcn35_pg_cntl.h | 2 ++ .../drm/amd/display/dc/dcn35/dcn35_resource.c | 2 ++ .../drm/amd/display/dc/dcn35/dcn35_resource.h | 2 ++ drivers/gpu/drm/amd/display/dc/hdcp/Makefile | 2 +- .../amd/display/dc/hwss/dcn303/dcn303_hwseq.c | 19 +++ .../amd/display/dc/hwss/dcn303/dcn303_hwseq.h | 19 +++ .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 2 ++ .../amd/display/dc/hwss/dcn35/dcn35_hwseq.h | 2 ++ .../dc/irq/dcn201/irq_service_dcn201.c| 2 +- .../dc/irq/dcn303/irq_service_dcn303.c| 19 +++ .../dc/irq/dcn303/irq_service_dcn303.h| 19 +++ 35 files changed, 215 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_dccg.h index 294bd757bcb5..2e12fb643005 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_dccg.h @@ -2,6 +2,24 @@ /* * Copyright (C) 2021 Advanced Micro Devices, Inc. * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * * Authors: AMD */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.c b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.c index 39cf7a50bd26..edb4d68b8187 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.c @@ -2,6 +2,24 @@ /* * Copyright (C) 2021 Advanced Micro Devices, Inc. * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES
[PATCH 2/3] drm/amd/display: Fix copyright notice in DML2 code
[Why & How] Fix incomplete copyright notice in DML2 code. Signed-off-by: Stylon Wang --- drivers/gpu/drm/amd/display/dc/dml2/Makefile | 4 +++- drivers/gpu/drm/amd/display/dc/dml2/cmntypes.h| 2 ++ drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c | 2 ++ .../gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h | 2 ++ .../gpu/drm/amd/display/dc/dml2/display_mode_lib_defines.h| 2 ++ drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.c | 2 ++ drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.h | 2 ++ drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c | 2 ++ drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.h | 2 ++ drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_types.h | 2 ++ drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h | 2 ++ drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c | 2 ++ drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.h | 2 ++ drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c | 2 ++ drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c | 2 ++ drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.h | 2 ++ drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c | 2 ++ drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c| 2 ++ drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h| 2 ++ drivers/gpu/drm/amd/display/dc/dml2/dml_assert.h | 2 ++ drivers/gpu/drm/amd/display/dc/dml2/dml_depedencies.h | 2 ++ drivers/gpu/drm/amd/display/dc/dml2/dml_logging.h | 2 ++ 22 files changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/Makefile b/drivers/gpu/drm/amd/display/dc/dml2/Makefile index f35ed8de260d..d9137675d8b4 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml2/Makefile @@ -20,7 +20,9 @@ # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR # OTHER DEALINGS IN THE SOFTWARE. # -# makefile for dml2 +# Authors: AMD +# +# Makefile for dml2. ifdef CONFIG_X86 dml2_ccflags-$(CONFIG_CC_IS_GCC) := -mhard-float diff --git a/drivers/gpu/drm/amd/display/dc/dml2/cmntypes.h b/drivers/gpu/drm/amd/display/dc/dml2/cmntypes.h index 5450aa5295f7..e450445bc05d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/cmntypes.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/cmntypes.h @@ -20,6 +20,8 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * + * Authors: AMD + * */ #ifndef __CMNTYPES_H__ diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c index cff53d28d3c5..4f906fcd83d0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c @@ -20,6 +20,8 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * + * Authors: AMD + * */ #include "display_mode_core.h" diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h index c2fa28ff57ab..b274bfb4225f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h @@ -20,6 +20,8 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * + * Authors: AMD + * */ #ifndef __DISPLAY_MODE_CORE_STRUCT_H__ diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_lib_defines.h b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_lib_defines.h index 99bdb2ddd8ab..de63364be01d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_lib_defines.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_lib_defines.h @@ -20,6 +20,8 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * + * Authors: AMD + * */ #ifndef __DISPLAY_MODE_LIB_DEFINES_H__ diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.c b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.c index 7dd1f8a12582..c247aee89caf 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.c @@ -20,6 +20,8 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * + * Authors: AMD + * */ #include "display_mode_util.h" diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.h b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.h index fb74385e1060..113b0265e1d1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_util.h @@ -20,6 +20,8 @@ * ARISING FROM,
[PATCH 1/3] drm/amd/display: Add missing copyright notice in DMUB
[Why & How] Add missing/incomplete copyright notice in DMUB files Signed-off-by: Stylon Wang --- .../drm/amd/display/dmub/src/dmub_dcn303.c| 19 +++ .../drm/amd/display/dmub/src/dmub_dcn303.h| 19 +++ 2 files changed, 38 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.c index b42369984473..878700160fa9 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.c @@ -2,7 +2,26 @@ /* * Copyright (C) 2021 Advanced Micro Devices, Inc. * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * * Authors: AMD + * */ #include "../dmub_srv.h" diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.h index 84141d450256..abe087251cc1 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.h +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.h @@ -2,7 +2,26 @@ /* * Copyright (C) 2021 Advanced Micro Devices, Inc. * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * * Authors: AMD + * */ #ifndef _DMUB_DCN303_H_ -- 2.42.0
[PATCH 0/3]Reduce code delta with copyright notice
Many of the DC files have either incomplete or incorrect copyright notice. This patchset aims to address this and also make lives less difficult for those doing backport/upstream activities. Stylon Wang (3): drm/amd/display: Add missing copyright notice in DMUB drm/amd/display: Fix copyright notice in DML2 code drm/amd/display: Fix copyright notice in DC code .../drm/amd/display/dc/dcn303/dcn303_dccg.h | 18 ++ .../drm/amd/display/dc/dcn303/dcn303_init.c | 18 ++ .../drm/amd/display/dc/dcn303/dcn303_init.h | 18 ++ .../amd/display/dc/dcn303/dcn303_resource.c | 18 ++ .../amd/display/dc/dcn303/dcn303_resource.h | 18 ++ drivers/gpu/drm/amd/display/dc/dcn31/Makefile | 2 +- .../gpu/drm/amd/display/dc/dcn35/dcn35_dpp.c | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_dpp.h | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_dsc.c | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_dsc.h | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_dwb.h | 2 ++ .../drm/amd/display/dc/dcn35/dcn35_hubbub.c | 2 ++ .../drm/amd/display/dc/dcn35/dcn35_hubbub.h | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_hubp.c | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_hubp.h | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_init.c | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_init.h | 2 ++ .../drm/amd/display/dc/dcn35/dcn35_mmhubbub.c | 2 ++ .../drm/amd/display/dc/dcn35/dcn35_mmhubbub.h | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_opp.c | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_opp.h | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_optc.c | 2 ++ .../gpu/drm/amd/display/dc/dcn35/dcn35_optc.h | 2 ++ .../drm/amd/display/dc/dcn35/dcn35_pg_cntl.c | 2 ++ .../drm/amd/display/dc/dcn35/dcn35_pg_cntl.h | 2 ++ .../drm/amd/display/dc/dcn35/dcn35_resource.c | 2 ++ .../drm/amd/display/dc/dcn35/dcn35_resource.h | 2 ++ drivers/gpu/drm/amd/display/dc/dml2/Makefile | 4 +++- .../gpu/drm/amd/display/dc/dml2/cmntypes.h| 2 ++ .../amd/display/dc/dml2/display_mode_core.c | 2 ++ .../dc/dml2/display_mode_core_structs.h | 2 ++ .../dc/dml2/display_mode_lib_defines.h| 2 ++ .../amd/display/dc/dml2/display_mode_util.c | 2 ++ .../amd/display/dc/dml2/display_mode_util.h | 2 ++ .../display/dc/dml2/dml2_dc_resource_mgmt.c | 2 ++ .../display/dc/dml2/dml2_dc_resource_mgmt.h | 2 ++ .../drm/amd/display/dc/dml2/dml2_dc_types.h | 2 ++ .../amd/display/dc/dml2/dml2_internal_types.h | 2 ++ .../amd/display/dc/dml2/dml2_mall_phantom.c | 2 ++ .../amd/display/dc/dml2/dml2_mall_phantom.h | 2 ++ .../gpu/drm/amd/display/dc/dml2/dml2_policy.c | 2 ++ .../display/dc/dml2/dml2_translation_helper.c | 2 ++ .../display/dc/dml2/dml2_translation_helper.h | 2 ++ .../gpu/drm/amd/display/dc/dml2/dml2_utils.c | 2 ++ .../drm/amd/display/dc/dml2/dml2_wrapper.c| 2 ++ .../drm/amd/display/dc/dml2/dml2_wrapper.h| 2 ++ .../gpu/drm/amd/display/dc/dml2/dml_assert.h | 2 ++ .../drm/amd/display/dc/dml2/dml_depedencies.h | 2 ++ .../gpu/drm/amd/display/dc/dml2/dml_logging.h | 2 ++ drivers/gpu/drm/amd/display/dc/hdcp/Makefile | 2 +- .../amd/display/dc/hwss/dcn303/dcn303_hwseq.c | 19 +++ .../amd/display/dc/hwss/dcn303/dcn303_hwseq.h | 19 +++ .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 2 ++ .../amd/display/dc/hwss/dcn35/dcn35_hwseq.h | 2 ++ .../dc/irq/dcn201/irq_service_dcn201.c| 2 +- .../dc/irq/dcn303/irq_service_dcn303.c| 19 +++ .../dc/irq/dcn303/irq_service_dcn303.h| 19 +++ .../drm/amd/display/dmub/src/dmub_dcn303.c| 19 +++ .../drm/amd/display/dmub/src/dmub_dcn303.h| 19 +++ 59 files changed, 298 insertions(+), 4 deletions(-) -- 2.42.0
[PATCH] drm/amd/display: Remove brackets in macro to conform to coding style
[Why] Many of the register macros defined ind dcn32_resource.h have extra brackets. This is not conforming to the style of those defined in other DC header files. [How] Remove these brackets in dcn32_resource.h Reviewed-by: Aurabindo Pillai Signed-off-by: Stylon Wang --- .../drm/amd/display/dc/dcn32/dcn32_resource.h | 154 -- 1 file changed, 36 insertions(+), 118 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h index f075982363be..b931008114c9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h @@ -187,7 +187,6 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int /* CLK SRC */ #define CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) \ - ( \ SRI_ARR_ALPHABET(PIXCLK_RESYNC_CNTL, PHYPLL, index, pllid), \ SRII_ARR_2(PHASE, DP_DTO, 0, index), \ SRII_ARR_2(PHASE, DP_DTO, 1, index), \ @@ -200,12 +199,10 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 0, index), \ SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 1, index), \ SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 2, index), \ - SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 3, index) \ - ) + SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 3, index) /* ABM */ #define ABM_DCN32_REG_LIST_RI(id) \ - ( \ SRI_ARR(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ SRI_ARR(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ SRI_ARR(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ @@ -217,12 +214,10 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int SRI_ARR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ SRI_ARR(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ SRI_ARR(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \ - SRI_ARR(DC_ABM1_ACE_THRES_12, ABM, id), NBIO_SR_ARR(BIOS_SCRATCH_2, id) \ - ) + SRI_ARR(DC_ABM1_ACE_THRES_12, ABM, id), NBIO_SR_ARR(BIOS_SCRATCH_2, id) /* Audio */ #define AUD_COMMON_REG_LIST_RI(id) \ - ( \ SRI_ARR(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZF0ENDPOINT, id), \ SRI_ARR(AZALIA_F0_CODEC_ENDPOINT_DATA, AZF0ENDPOINT, id), \ SR_ARR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS, id), \ @@ -231,41 +226,33 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int SR_ARR(DCCG_AUDIO_DTO_SOURCE, id), SR_ARR(DCCG_AUDIO_DTO0_MODULE, id), \ SR_ARR(DCCG_AUDIO_DTO0_PHASE, id), SR_ARR(DCCG_AUDIO_DTO1_MODULE, id), \ SR_ARR(DCCG_AUDIO_DTO1_PHASE, id) \ - ) /* VPG */ #define VPG_DCN3_REG_LIST_RI(id) \ - ( \ SRI_ARR(VPG_GENERIC_STATUS, VPG, id), \ SRI_ARR(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \ SRI_ARR(VPG_GENERIC_PACKET_DATA, VPG, id), \ SRI_ARR(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \ - SRI_ARR(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id) \ - ) + SRI_ARR(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id) /* AFMT */ #define AFMT_DCN3_REG_LIST_RI(id) \ - ( \ SRI_ARR(AFMT_INFOFRAME_CONTROL0, AFMT, id), \ SRI_ARR(AFMT_VBI_PACKET_CONTROL, AFMT, id), \ SRI_ARR(AFMT_AUDIO_PACKET_CONTROL, AFMT, id), \ SRI_ARR(AFMT_AUDIO_PACKET_CONTROL2, AFMT, id), \ SRI_ARR(AFMT_AUDIO_SRC_CONTROL, AFMT, id), \ SRI_ARR(AFMT_60958_0, AFMT, id), SRI_ARR(AFMT_60958_1, AFMT, id), \ - SRI_ARR(AFMT_60958_2, AFMT, id), SRI_ARR(AFMT_MEM_PWR, AFMT, id) \ - ) + SRI_ARR(AFMT_60958_2, AFMT, id), SRI_ARR(AFMT_MEM_PWR, AFMT, id) /* APG */ #define APG_DCN31_REG_LIST_RI(id) \ - (\ SRI_ARR(APG_CONTROL, APG, id), SRI_ARR(APG_CONTROL2, APG, id), \ - SRI_ARR(APG_MEM_PWR, APG, id), SRI_ARR(APG_DBG_GEN_CONTROL, APG, id) \ - ) + SRI_ARR(APG_MEM_PWR, APG, id), SRI_ARR(APG_DBG_GEN_CONTROL, APG, id) /* Stream
[PATCH] drm/amd/display: Add missing lines of code in dc.c
[Why & How]
A critial part of "drm/amd/display: Fix windowed MPO video with ODM
combine for DCN32" is lost during promotion to upstream. This patch
addes the code back to dc.c.
Signed-off-by: Stylon Wang
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f602ff0d4146..e13d8bab0b33 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3096,6 +3096,9 @@ static bool update_planes_and_stream_state(struct dc *dc,
if (update_type >= update_surface_trace_level)
update_surface_trace(dc, srf_updates, surface_count);
+ for (i = 0; i < surface_count; i++)
+ copy_surface_update_to_plane(srf_updates[i].surface,
_updates[i]);
+
if (update_type >= UPDATE_TYPE_FULL) {
struct dc_plane_state *new_planes[MAX_SURFACES] = {0};
@@ -3137,8 +3140,6 @@ static bool update_planes_and_stream_state(struct dc *dc,
for (i = 0; i < surface_count; i++) {
struct dc_plane_state *surface = srf_updates[i].surface;
- copy_surface_update_to_plane(surface, _updates[i]);
-
if (update_type >= UPDATE_TYPE_MED) {
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx =
>res_ctx.pipe_ctx[j];
--
2.42.0
[PATCH] drm/amd/display: Remove unused DPCD declarations
[Why & How]
These DPCD addresses are either declared in other header files
where it makes more sense or simply not used by any DC code.
Remove them to reduce redundancies and potential confusion.
Signed-off-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 59 +---
1 file changed, 1 insertion(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index cfaa39c5dd16..35ae245ef722 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -916,73 +916,16 @@ struct dpcd_usb4_dp_tunneling_info {
uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN];
};
-#ifndef DP_MAIN_LINK_CHANNEL_CODING_CAP
-#define DP_MAIN_LINK_CHANNEL_CODING_CAP0x006
-#endif
-#ifndef DP_SINK_VIDEO_FALLBACK_FORMATS
-#define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020
-#endif
-#ifndef DP_FEC_CAPABILITY_1
-#define DP_FEC_CAPABILITY_10x091
-#endif
#ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT
#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT0x0A3
#endif
-#ifndef DP_DSC_CONFIGURATION
-#define DP_DSC_CONFIGURATION 0x161
-#endif
-#ifndef DP_PHY_SQUARE_PATTERN
-#define DP_PHY_SQUARE_PATTERN 0x249
-#endif
-#ifndef DP_128b_132b_SUPPORTED_LINK_RATES
-#define DP_128b_132b_SUPPORTED_LINK_RATES 0x2215
-#endif
-#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL
-#define DP_128b_132b_TRAINING_AUX_RD_INTERVAL 0x2216
-#endif
#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0
#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0X2230
#endif
#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256
#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250
#endif
-#ifndef DP_DSC_SUPPORT_AND_DECODER_COUNT
-#define DP_DSC_SUPPORT_AND_DECODER_COUNT 0x2260
-#endif
-#ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0
-#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270
-#endif
-#ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK
-#define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
-#endif
-#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK
-#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
-#endif
-#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT
-#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
-#endif
-#ifndef DP_DSC_DECODER_COUNT_MASK
-#define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
-#endif
-#ifndef DP_DSC_DECODER_COUNT_SHIFT
-#define DP_DSC_DECODER_COUNT_SHIFT 5
-#endif
-#ifndef DP_MAIN_LINK_CHANNEL_CODING_SET
-#define DP_MAIN_LINK_CHANNEL_CODING_SET0x108
-#endif
-#ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER
-#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
-#endif
-#ifndef DP_PHY_REPEATER_128b_132b_RATES
-#define DP_PHY_REPEATER_128b_132b_RATES0xF0007
-#endif
-#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1
-#define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER10xF0022
-#endif
-#ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION
-#define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3)
-/* TODO - Use DRM header to replace above once available */
-#endif // DP_INTRA_HOP_AUX_REPLY_INDICATION
+
union dp_main_line_channel_coding_cap {
struct {
uint8_t DP_8b_10b_SUPPORTED :1;
--
2.42.0
[PATCH 27/28] drm/amd/display: move odm power optimization decision after subvp optimization
From: Wenjing Liu [why] ODM power optimization excludes subvp power optimization but subvp optimization can override ODM power optimization even if subvp optimization configuration is not found. This happens with 4k144hz + 1 5k desktop plane. We could have applied ODM power optimization however this is overridden by subvp but subvp ends up deciding not apply its optimization. [how] Move ODM power optimization decision after subvp so it will try ODM power optimization after subvp optimization is not possible. Reviewed-by: Dillon Varone Acked-by: Stylon Wang Signed-off-by: Wenjing Liu --- drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index 92e2d1df5b32..1f53883d8f56 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -1441,10 +1441,6 @@ static void dcn32_full_validate_bw_helper(struct dc *dc, vba->VoltageLevel = *vlevel; } - if (should_allow_odm_power_optimization(dc, context, vba, split, merge)) - try_odm_power_optimization_and_revalidate( - dc, context, pipes, split, merge, vlevel, *pipe_cnt); - /* Conditions for setting up phantom pipes for SubVP: * 1. Not force disable SubVP * 2. Full update (i.e. !fast_validate) @@ -1563,6 +1559,11 @@ static void dcn32_full_validate_bw_helper(struct dc *dc, assign_subvp_index(dc, context); } } + + if (should_allow_odm_power_optimization(dc, context, vba, split, merge)) + try_odm_power_optimization_and_revalidate( + dc, context, pipes, split, merge, vlevel, *pipe_cnt); + } static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) -- 2.42.0
[PATCH 28/28] drm/amd/display: add skip_implict_edp_power_control flag for dcn32
From: Ian Chen Add flag skip_implict_edp_power_control check in function dcn32_disable_link_output to fix DCN35 issue. Reviewed-by: Robin Chen Acked-by: Stylon Wang Signed-off-by: Ian Chen --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c index 018376146d97..e8a989a50afa 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c @@ -1322,7 +1322,8 @@ void dcn32_disable_link_output(struct dc_link *link, struct dmcu *dmcu = dc->res_pool->dmcu; if (signal == SIGNAL_TYPE_EDP && - link->dc->hwss.edp_backlight_control) + link->dc->hwss.edp_backlight_control && + !link->skip_implict_edp_power_control) link->dc->hwss.edp_backlight_control(link, false); else if (dmcu != NULL && dmcu->funcs->lock_phy) dmcu->funcs->lock_phy(dmcu); @@ -1331,7 +1332,8 @@ void dcn32_disable_link_output(struct dc_link *link, link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; if (signal == SIGNAL_TYPE_EDP && - link->dc->hwss.edp_backlight_control) + link->dc->hwss.edp_backlight_control && + !link->skip_implict_edp_power_control) link->dc->hwss.edp_power_control(link, false); else if (dmcu != NULL && dmcu->funcs->lock_phy) dmcu->funcs->unlock_phy(dmcu); -- 2.42.0
[PATCH 26/28] drm/amd/display: add seamless pipe topology transition check
From: Wenjing Liu
[why]
We have a few cases where we need to perform update topology update
in dc update interface. However some of the updates are not seamless
This could cause user noticible glitches. To enforce seamless transition
we are adding a checking condition and error logging so the corruption
as result of non seamless transition can be easily spotted.
Reviewed-by: Dillon Varone
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +++
.../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 52 +++
.../drm/amd/display/dc/dcn32/dcn32_hwseq.h| 4 ++
.../gpu/drm/amd/display/dc/dcn32/dcn32_init.c | 1 +
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 ++
5 files changed, 68 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index a857de5ebe85..f91d0f6b0d7d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -4370,6 +4370,14 @@ bool dc_update_planes_and_stream(struct dc *dc,
update_type,
context);
} else {
+ if (!stream_update &&
+ dc->hwss.is_pipe_topology_transition_seamless &&
+ !dc->hwss.is_pipe_topology_transition_seamless(
+ dc, dc->current_state,
context)) {
+
+ DC_LOG_ERROR("performing non-seamless pipe topology
transition with surface only update!\n");
+ BREAK_TO_DEBUGGER();
+ }
commit_planes_for_stream(
dc,
srf_updates,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index cae5e1e68c86..018376146d97 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -1619,3 +1619,55 @@ void dcn32_blank_phantom(struct dc *dc,
if (tg->funcs->is_tg_enabled(tg))
hws->funcs.wait_for_blank_complete(opp);
}
+
+bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc,
+ const struct dc_state *cur_ctx,
+ const struct dc_state *new_ctx)
+{
+ int i;
+ const struct pipe_ctx *cur_pipe, *new_pipe;
+ bool is_seamless = true;
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ cur_pipe = _ctx->res_ctx.pipe_ctx[i];
+ new_pipe = _ctx->res_ctx.pipe_ctx[i];
+
+ if (resource_is_pipe_type(cur_pipe, FREE_PIPE) ||
+ resource_is_pipe_type(new_pipe, FREE_PIPE))
+ /* adding or removing free pipes is always seamless */
+ continue;
+ else if (resource_is_pipe_type(cur_pipe, OTG_MASTER)) {
+ if (resource_is_pipe_type(new_pipe, OTG_MASTER))
+ if (cur_pipe->stream->stream_id ==
new_pipe->stream->stream_id)
+ /* OTG master with the same stream is seamless
*/
+ continue;
+ } else if (resource_is_pipe_type(cur_pipe, OPP_HEAD)) {
+ if (resource_is_pipe_type(new_pipe, OPP_HEAD)) {
+ if (cur_pipe->stream_res.tg ==
new_pipe->stream_res.tg)
+ /*
+* OPP heads sharing the same timing
+* generator is seamless
+*/
+ continue;
+ }
+ } else if (resource_is_pipe_type(cur_pipe, DPP_PIPE)) {
+ if (resource_is_pipe_type(new_pipe, DPP_PIPE)) {
+ if (cur_pipe->stream_res.opp ==
new_pipe->stream_res.opp)
+ /*
+* DPP pipes sharing the same OPP head
is
+* seamless
+*/
+ continue;
+ }
+ }
+
+ /*
+* This pipe's transition doesn't fall under any seamless
+* conditions
+*/
+ is_seamless = false;
+ break;
+ }
+
+ return is_seamless;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
index 616d5219119e..9992e40acd21 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h
@@ -120,4 +120,8 @@ voi
[PATCH 25/28] drm/amd/display: minior logging improvements
From: Wenjing Liu
[how]
- Add minimial transition log with reason and base state.
- Do not log set dpms interfaces for virtual signal in stream.
Reviewed-by: Dillon Varone
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 7 +++
drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 10 --
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 8e8362026825..a857de5ebe85 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -4069,6 +4069,13 @@ static bool commit_minimal_transition_state(struct dc
*dc,
return true;
}
+ DC_LOG_DC("%s base = %s state, reason = %s\n", __func__,
+ dc->current_state == transition_base_context ?
"current" : "new",
+ subvp_in_use ? "Subvp In Use" :
+ odm_in_use ? "ODM in Use" :
+ dc->debug.pipe_split_policy != MPC_SPLIT_AVOID ? "MPC
in Use" :
+ "Unknown");
+
if (!dc->config.is_vmin_only_asic) {
tmp_mpc_policy = dc->debug.pipe_split_policy;
dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index cd9dd270b05f..d8327911c467 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -2269,6 +2269,8 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)
if (dp_is_128b_132b_signal(pipe_ctx))
vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
+ if (dc_is_virtual_signal(pipe_ctx->stream->signal))
+ return;
DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
@@ -2281,9 +2283,6 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)
}
}
- if (dc_is_virtual_signal(pipe_ctx->stream->signal))
- return;
-
if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
set_avmute(pipe_ctx, true);
@@ -2382,6 +2381,8 @@ void link_set_dpms_on(
if (dp_is_128b_132b_signal(pipe_ctx))
vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
+ if (dc_is_virtual_signal(pipe_ctx->stream->signal))
+ return;
DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
@@ -2394,9 +2395,6 @@ void link_set_dpms_on(
}
}
- if (dc_is_virtual_signal(pipe_ctx->stream->signal))
- return;
-
link_enc = link_enc_cfg_get_link_enc(link);
ASSERT(link_enc);
--
2.42.0
[PATCH 23/28] drm/amd/display: 3.2.250
From: Aric Cyr Acked-by: Stylon Wang Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 05ab24c81041..bece61d2508b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -47,7 +47,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.249" +#define DC_VER "3.2.250" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.42.0
[PATCH 24/28] drm/amd/display: do not skip ODM minimal transition based on new state
From: Wenjing Liu
[why]
During 8k video plane resizing we could transition from MPC combine mode
back to ODM combine 2:1 + 8k video plane. In this transition minimal
transition state is based on new state with ODM combine enabled.
We are skipping this and it causes corruption because we have to reassign
a current DPP pipe to a different MPC blending tree which is not supported
seamlessly.
Reviewed-by: Dillon Varone
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 0320bc49458c..8e8362026825 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -4048,10 +4048,10 @@ static bool commit_minimal_transition_state(struct dc
*dc,
* pipe, we must use the minimal transition.
*/
for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *pipe = >current_state->res_ctx.pipe_ctx[i];
+ struct pipe_ctx *pipe =
_base_context->res_ctx.pipe_ctx[i];
- if (pipe->stream && pipe->next_odm_pipe) {
- odm_in_use = true;
+ if (resource_is_pipe_type(pipe, OTG_MASTER)) {
+ odm_in_use = resource_get_odm_slice_count(pipe) > 1;
break;
}
}
--
2.42.0
[PATCH 22/28] drm/amd/display: Fix MST recognizes connected displays as one
From: Muhammad Ahmed
[What]
MST now recognizes both connected displays
Reviewed-by: Charlene Liu
Acked-by: Stylon Wang
Signed-off-by: Muhammad Ahmed
---
.../display/dc/dce110/dce110_hw_sequencer.c | 30 +++
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 8 ++---
.../gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c | 2 +-
3 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 31454db00ed5..2701620350af 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1178,12 +1178,15 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
dto_params.otg_inst = tg->inst;
dto_params.timing = _ctx->stream->timing;
dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
- dccg->funcs->set_dtbclk_dto(dccg, _params);
- dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
- dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst,
dp_hpo_inst);
- } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST &&
dccg->funcs->disable_symclk_se)
+ if (dccg) {
+ dccg->funcs->set_dtbclk_dto(dccg, _params);
+ dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
+ dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst,
dp_hpo_inst);
+ }
+ } else if (dccg && dccg->funcs->disable_symclk_se) {
dccg->funcs->disable_symclk_se(dccg,
stream_enc->stream_enc_inst,
link_enc->transmitter - TRANSMITTER_UNIPHY_A);
+ }
if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
/* TODO: This looks like a bug to me as we are disabling HPO IO
when
@@ -2655,11 +2658,11 @@ void dce110_prepare_bandwidth(
struct clk_mgr *dccg = dc->clk_mgr;
dce110_set_safe_displaymarks(>res_ctx, dc->res_pool);
-
- dccg->funcs->update_clocks(
- dccg,
- context,
- false);
+ if (dccg)
+ dccg->funcs->update_clocks(
+ dccg,
+ context,
+ false);
}
void dce110_optimize_bandwidth(
@@ -2670,10 +2673,11 @@ void dce110_optimize_bandwidth(
dce110_set_displaymarks(dc, context);
- dccg->funcs->update_clocks(
- dccg,
- context,
- true);
+ if (dccg)
+ dccg->funcs->update_clocks(
+ dccg,
+ context,
+ true);
}
static void dce110_program_front_end_for_pipe(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 37cab11d1b31..19ab08f5122e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2710,8 +2710,6 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
struct dce_hwseq *hws = dc->hwseq;
unsigned int k1_div = PIXEL_RATE_DIV_NA;
unsigned int k2_div = PIXEL_RATE_DIV_NA;
- struct link_encoder *link_enc =
link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
- struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
if (dc->hwseq->funcs.setup_hpo_hw_control)
@@ -2731,10 +2729,8 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
dto_params.timing = _ctx->stream->timing;
dto_params.ref_dtbclk_khz =
dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
dccg->funcs->set_dtbclk_dto(dccg, _params);
- } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST &&
dccg->funcs->enable_symclk_se)
- dccg->funcs->enable_symclk_se(dccg,
- stream_enc->stream_enc_inst, link_enc->transmitter -
TRANSMITTER_UNIPHY_A);
-
+ } else {
+ }
if (hws->funcs.calculate_dccg_k1_k2_values &&
dc->res_pool->dccg->funcs->set_pixel_rate_div) {
hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, _div,
_div);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
index 3082da04a63d..1d052f08aff5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
+++ b/drivers/gpu/drm
[PATCH 21/28] drm/amd/display: fix some non-initialized register mask and setting
From: Charlene Liu
[why]
fix some non-initialized register mask and update golden setting
Reviewed-by: Duncan Ma
Acked-by: Stylon Wang
Signed-off-by: Charlene Liu
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 56 ++-
.../display/dc/dcn10/dcn10_stream_encoder.h | 5 +-
.../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 6 +-
.../amd/display/dc/inc/hw/clk_mgr_internal.h | 16 +-
4 files changed, 65 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 4fd25bb1ab92..37ffa0050e60 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -53,6 +53,14 @@
#define mmCLK1_CLK3_DFS_CNTL0x16E72
#define mmCLK1_CLK4_DFS_CNTL0x16E75
+#define mmCLK1_CLK0_CURRENT_CNT 0x16EE7
+#define mmCLK1_CLK1_CURRENT_CNT 0x16EE8
+#define mmCLK1_CLK2_CURRENT_CNT 0x16EE9
+#define mmCLK1_CLK3_CURRENT_CNT 0x16EEA
+#define mmCLK1_CLK4_CURRENT_CNT 0x16EEB
+
+#define mmCLK4_CLK0_CURRENT_CNT 0x1B0C9
+
#define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x01ffUL
#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0xf000UL
#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xUL
@@ -452,6 +460,26 @@ static int dcn32_get_dispclk_from_dentist(struct clk_mgr
*clk_mgr_base)
static void dcn32_auto_dpm_test_log(struct dc_clocks *new_clocks, struct
clk_mgr_internal *clk_mgr)
{
+unsigned int dispclk_khz_reg= REG_READ(CLK1_CLK0_CURRENT_CNT); //
DISPCLK
+unsigned int dppclk_khz_reg = REG_READ(CLK1_CLK1_CURRENT_CNT); //
DPPCLK
+unsigned int dprefclk_khz_reg = REG_READ(CLK1_CLK2_CURRENT_CNT); //
DPREFCLK
+unsigned int dcfclk_khz_reg = REG_READ(CLK1_CLK3_CURRENT_CNT); //
DCFCLK
+unsigned int dtbclk_khz_reg = REG_READ(CLK1_CLK4_CURRENT_CNT); //
DTBCLK
+unsigned int fclk_khz_reg = REG_READ(CLK4_CLK0_CURRENT_CNT); // FCLK
+
+// Overrides for these clocks in case there is no p_state change support
+int dramclk_khz_override = new_clocks->dramclk_khz;
+int fclk_khz_override = new_clocks->fclk_khz;
+
+int num_fclk_levels =
clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1;
+
+if (!new_clocks->p_state_change_support) {
+ dramclk_khz_override = clk_mgr->base.bw_params->max_memclk_mhz *
1000;
+}
+if (!new_clocks->fclk_p_state_change_support) {
+ fclk_khz_override =
clk_mgr->base.bw_params->clk_table.entries[num_fclk_levels].fclk_mhz * 1000;
+}
+
// IMPORTANT: When adding more clocks to these logs, do NOT
put a newline
// anywhere other than at the very end of
the string.
@@ -466,20 +494,20 @@ static void dcn32_auto_dpm_test_log(struct dc_clocks
*new_clocks, struct clk_mgr
new_clocks->dcfclk_khz > 0 &&
new_clocks->dppclk_khz > 0) {
- if (new_clocks->p_state_change_support) {
- DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk_khz:%d -
fclk_khz:%d - "
-"dcfclk_khz:%d -
dppclk_khz:%d\n",
-new_clocks->dramclk_khz,
-new_clocks->fclk_khz,
-new_clocks->dcfclk_khz,
-new_clocks->dppclk_khz);
- } else {
- DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk_khz:1249000
- fclk_khz:%d - "
-"dcfclk_khz:%d -
dppclk_khz:%d\n",
-new_clocks->fclk_khz,
-new_clocks->dcfclk_khz,
-new_clocks->dppclk_khz);
- }
+ DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk:%d - fclk:%d - "
+ "dcfclk:%d - dppclk:%d - dispclk_hw:%d - "
+ "dppclk_hw:%d - dprefclk_hw:%d - dcfclk_hw:%d - "
+ "dtbclk_hw:%d - fclk_hw:%d\n",
+ dramclk_khz_override,
+ fclk_khz_override,
+ new_clocks->dcfclk_khz,
+ new_clocks->dppclk_khz,
+ dispclk_khz_reg,
+ dppclk_khz_reg
[PATCH 20/28] drm/amd/display: Add check for vrr_active_fixed
From: Austin Zheng
Why:
vrr_active_fixed should also be checked when
determining if DRR is in use
How:
Add check for vrr_active_fixed when allow_freesync
and vrr_active_variable are also checked
Reviewed-by: Alvin Lee
Acked-by: Stylon Wang
Signed-off-by: Austin Zheng
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 979f52ee5604..2f98dfa06dad 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -554,7 +554,7 @@ static void populate_subvp_cmd_vblank_pipe_info(struct dc
*dc,
vblank_pipe->stream->timing.v_total -
vblank_pipe->stream->timing.v_front_porch -
vblank_pipe->stream->timing.v_addressable;
if (vblank_pipe->stream->ignore_msa_timing_param &&
- (vblank_pipe->stream->allow_freesync ||
vblank_pipe->stream->vrr_active_variable))
+ (vblank_pipe->stream->allow_freesync ||
vblank_pipe->stream->vrr_active_variable ||
vblank_pipe->stream->vrr_active_fixed))
populate_subvp_cmd_drr_info(dc, pipe, vblank_pipe, pipe_data);
}
@@ -648,7 +648,7 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc,
pipe_data->pipe_config.subvp_data.mall_region_lines =
phantom_timing->v_addressable;
pipe_data->pipe_config.subvp_data.main_pipe_index =
subvp_pipe->stream_res.tg->inst;
pipe_data->pipe_config.subvp_data.is_drr =
subvp_pipe->stream->ignore_msa_timing_param &&
- (subvp_pipe->stream->allow_freesync ||
subvp_pipe->stream->vrr_active_variable);
+ (subvp_pipe->stream->allow_freesync ||
subvp_pipe->stream->vrr_active_variable ||
subvp_pipe->stream->vrr_active_fixed);
/* Calculate the scaling factor from the src and dst height.
* e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor
is 1/2.
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index f5705b3e6e42..bc5f0db23d0c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -706,7 +706,7 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct
dc_state *context)
non_subvp_pipes++;
drr_psr_capable = (drr_psr_capable ||
dcn32_is_psr_capable(pipe));
if (pipe->stream->ignore_msa_timing_param &&
- (pipe->stream->allow_freesync
|| pipe->stream->vrr_active_variable)) {
+ (pipe->stream->allow_freesync
|| pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {
drr_pipe_found = true;
}
}
@@ -764,7 +764,7 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct
dc_state *context, int
non_subvp_pipes++;
vblank_psr_capable = (vblank_psr_capable ||
dcn32_is_psr_capable(pipe));
if (pipe->stream->ignore_msa_timing_param &&
- (pipe->stream->allow_freesync
|| pipe->stream->vrr_active_variable)) {
+ (pipe->stream->allow_freesync
|| pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {
drr_pipe_found = true;
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 2358c9100cff..92e2d1df5b32 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -822,7 +822,7 @@ static bool subvp_drr_schedulable(struct dc *dc, struct
dc_state *context)
continue;
if (drr_pipe->stream->mall_stream_config.type == SUBVP_NONE &&
drr_pipe->stream->ignore_msa_timing_param &&
- (drr_pipe->stream->allow_freesync ||
drr_pipe->stream->vrr_active_variable))
+ (drr_pipe->stream->allow_freesync ||
drr_pipe->stream->vrr_active_variable || drr_pipe->stream->vrr_active_fixed))
break;
}
--
2.42.0
[PATCH 19/28] drm/amd/display: dc cleanup for tests
From: Sridevi Arvindekar
[WHY]
Code cleanup found in internal tests
Reviewed-by: Dillon Varone
Acked-by: Stylon Wang
Signed-off-by: Sridevi Arvindekar
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 5ac85df158b9..37cab11d1b31 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2855,7 +2855,7 @@ void dcn20_fpga_init_hw(struct dc *dc)
res_pool->mpc->funcs->mpc_init(res_pool->mpc);
/* initialize OPP mpc_tree parameter */
- for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
res_pool->opps[i]->mpc_tree_params.opp_id =
res_pool->opps[i]->inst;
res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
for (j = 0; j < MAX_PIPES; j++)
--
2.42.0
[PATCH 18/28] drm/amd/display: Drop unused registers
From: Qingqing Zhuo [Why & How] Some registers are never used in the driver but defined. Remove them. Reviewed-by: Roman Li Acked-by: Stylon Wang Signed-off-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.h index 013029f2e257..dc7331dc3b65 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hubbub.h @@ -37,8 +37,6 @@ SR(DCHUBBUB_ARB_SAT_LEVEL),\ SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ - SR(DCHUBBUB_TEST_DEBUG_INDEX), \ - SR(DCHUBBUB_TEST_DEBUG_DATA),\ SR(DCHUBBUB_SOFT_RESET),\ SR(DCHUBBUB_CRC_CTRL), \ SR(DCN_VM_FB_LOCATION_BASE),\ -- 2.42.0
[PATCH 17/28] drm/amd/display: add dp dto programming function to dccg
From: Dillon Varone
[WHY]
Add support for programming dp dto via dccg.
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 1 +
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 10 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index ed8936405dfa..75cf4ab8ae3c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -34,6 +34,7 @@
#include "dce_clock_source.h"
#include "clk_mgr.h"
+#include "dccg.h"
#include "reg_helper.h"
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index 3e2f0f64c98c..65bb7cd05385 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -56,6 +56,13 @@ enum dentist_dispclk_change_mode {
DISPCLK_CHANGE_MODE_RAMPING,
};
+struct dp_dto_params {
+ int otg_inst;
+ enum signal_type signal;
+ long long pixclk_hz;
+ long long refclk_hz;
+};
+
enum pixel_rate_div {
PIXEL_RATE_DIV_BY_1 = 0,
PIXEL_RATE_DIV_BY_2 = 1,
@@ -182,6 +189,9 @@ struct dccg_funcs {
struct dccg *dccg,
uint32_t stream_enc_inst,
uint32_t link_enc_inst);
+ void (*set_dp_dto)(
+ struct dccg *dccg,
+ const struct dp_dto_params *params);
};
#endif //__DAL_DCCG_H__
--
2.42.0
[PATCH 15/28] drm/amd/display: do not attempt ODM power optimization if minimal transition doesn't exist
From: Wenjing Liu
[why]
In some cases such as 8k desktop surface with 144Hz timing, we decide to
enable ODM power optimization but this surface doesn't have a minimum
transition state. Therefore we cannot switch off ODM power optimization
seamlessly
This creates path depedency on ODM power optimization decision. i.e
whether or not we should switch off ODM power optimization is dependent
on if the transition to switch off ODM power optimization from current state
is seamless. We don't desire a path dependent power optimization policy
as it is too dynamic and difficult to maintain.
[how]
Attempt ODM power optimization only after we can validate new state without
using pipe combine.
Reviewed-by: Dillon Varone
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 76 +--
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 487 +++---
2 files changed, 306 insertions(+), 257 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 8cb6b94e83d2..a74d4cab5a7d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -1885,67 +1885,6 @@ bool dcn32_validate_bandwidth(struct dc *dc,
return out;
}
-static bool should_allow_odm_power_optimization(struct dc *dc,
- struct dc_state *context)
-{
- struct dc_stream_state *stream = context->streams[0];
-
- /*
-* this debug flag allows us to disable ODM power optimization feature
-* unconditionally. we force the feature off if this is set to false.
-*/
- if (!dc->debug.enable_single_display_2to1_odm_policy)
- return false;
-
- /* current design and test coverage is only limited to allow ODM power
-* optimization for single stream. Supporting it for multiple streams
-* use case would require additional algorithm to decide how to
-* optimize power consumption when there are not enough free pipes to
-* allocate for all the streams. This level of optimization would
-* require multiple attempts of revalidation to make an optimized
-* decision. Unfortunately We do not support revalidation flow in
-* current version of DML.
-*/
- if (context->stream_count != 1)
- return false;
-
- /*
-* Our hardware doesn't support ODM for HDMI TMDS
-*/
- if (dc_is_hdmi_signal(stream->signal))
- return false;
-
- /*
-* ODM Combine 2:1 requires horizontal timing divisible by 2 so each
-* ODM segment has the same size.
-*/
- if (!is_h_timing_divisible_by_2(stream))
- return false;
-
- /*
-* No power benefits if the timing's pixel clock is not high enough to
-* raise display clock from minimum power state.
-*/
- if (stream->timing.pix_clk_100hz * 100 <= DCN3_2_VMIN_DISPCLK_HZ)
- return false;
-
- /* the new ODM power optimization feature reduces software design
-* limitation and allows ODM power optimization to be supported even
-* with presence of overlay planes. The new feature is enabled based on
-* enable_windowed_mpo_odm flag. If the flag is not set, we limit our
-* feature scope due to previous software design limitation */
- if (!dc->config.enable_windowed_mpo_odm) {
- if (context->stream_status[0].plane_count != 1)
- return false;
-
- if (stream->src.width >= 5120 &&
- stream->src.width > stream->dst.width)
- return false;
- }
-
- return true;
-}
-
int dcn32_populate_dml_pipes_from_context(
struct dc *dc, struct dc_state *context,
display_e2e_pipe_params_st *pipes,
@@ -1959,20 +1898,6 @@ int dcn32_populate_dml_pipes_from_context(
dcn20_populate_dml_pipes_from_context(dc, context, pipes,
fast_validate);
- /*
-* Apply pipe split policy first so we can predict the pipe split
correctly
-* (dcn32_predict_pipe_split).
-*/
- for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
- if (!res_ctx->pipe_ctx[i].stream)
- continue;
- if (should_allow_odm_power_optimization(dc, context))
- pipes[pipe_cnt].pipe.dest.odm_combine_policy =
dm_odm_combine_policy_2to1;
- else
- pipes[pipe_cnt].pipe.dest.odm_combine_policy =
dm_odm_combine_policy_dal;
- pipe_cnt++;
- }
-
for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
if (!res_ctx->pipe_ctx[i].stream)
@@ -1985,6 +1910,7 @@ int dcn32_populate_dml_pipes_fro
[PATCH 16/28] drm/amd/display: only allow ODM power optimization if surface is within guaranteed viewport size
From: Wenjing Liu
[why]
Current dc update design has limitation to support transition from
ODM combine to minimum transition to MPC combine state seamlessly
at the capability boundary when MPO plane is resizing. This will
require dc update high level refactor in order to remove the design
limitation. The decision is to block such use case for existing products
by limiting ODM power optimization support for only those surfaces
within guaranteed viewport size. This will prevent us from transitioning
to MPC combine state when ODM power optimization is enabled.
Reviewed-by: Dillon Varone
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 36 +++
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 27 ++
2 files changed, 63 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index dcedda85dcdb..0320bc49458c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3881,6 +3881,7 @@ static void commit_planes_for_stream(struct dc *dc,
*/
static bool could_mpcc_tree_change_for_active_pipes(struct dc *dc,
struct dc_stream_state *stream,
+ struct dc_surface_update *srf_updates,
int surface_count,
bool *is_plane_addition)
{
@@ -3918,6 +3919,40 @@ static bool
could_mpcc_tree_change_for_active_pipes(struct dc *dc,
*is_plane_addition = true;
}
}
+ if (dc->config.enable_windowed_mpo_odm) {
+ const struct rect *guaranteed_viewport = >src;
+ const struct rect *surface_src, *surface_dst;
+ bool are_cur_planes_guaranteed = true;
+ bool are_new_planes_guaranteed = true;
+
+ for (i = 0; i < cur_stream_status->plane_count; i++) {
+ surface_src =
_stream_status->plane_states[i]->src_rect;
+ surface_dst =
_stream_status->plane_states[i]->dst_rect;
+ if ((surface_src->height > surface_dst->height
&& surface_src->height > guaranteed_viewport->height) ||
+ (surface_src->width >
surface_dst->width && surface_src->width > guaranteed_viewport->width))
+ are_cur_planes_guaranteed = false;
+ }
+
+ for (i = 0; i < surface_count; i++) {
+ if (srf_updates[i].scaling_info) {
+ surface_src =
_updates[i].scaling_info->src_rect;
+ surface_dst =
_updates[i].scaling_info->dst_rect;
+ } else {
+ surface_src =
_updates[i].surface->src_rect;
+ surface_dst =
_updates[i].surface->dst_rect;
+ }
+ if ((surface_src->height > surface_dst->height
&& surface_src->height > guaranteed_viewport->height) ||
+ (surface_src->width >
surface_dst->width && surface_src->width > guaranteed_viewport->width))
+ are_new_planes_guaranteed = false;
+ }
+
+ if (are_cur_planes_guaranteed &&
!are_new_planes_guaranteed) {
+ force_minimal_pipe_splitting = true;
+ *is_plane_addition = true;
+ } else if (!are_cur_planes_guaranteed &&
are_new_planes_guaranteed) {
+ force_minimal_pipe_splitting = true;
+ }
+ }
}
for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -4270,6 +4305,7 @@ bool dc_update_planes_and_stream(struct dc *dc,
force_minimal_pipe_splitting = could_mpcc_tree_change_for_active_pipes(
dc,
stream,
+ srf_updates,
surface_count,
_plane_addition);
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 883e90be2257..2358c9100cff 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1267,6 +1267,8 @@ static bool should_allow_odm_power_optimization(struct dc
*dc,
{
struct dc_stream_state *stream = context->streams[0];
struct pipe_slice_table slice_table;
+ struct dc_pla
[PATCH 14/28] drm/amd/display: remove a function that does complex calculation in every frame but not used
From: Wenjing Liu
[why]
The result of predict_pipe_split calculation is no longer used but the
function is not removed. This will cause unnecessary calculation
of pipe split prediction in every frame update.
Reviewed-by: Dillon Varone
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 3 -
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 84 ---
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.h | 3 -
3 files changed, 90 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index fd12791995a7..8cb6b94e83d2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -2031,9 +2031,6 @@ int dcn32_populate_dml_pipes_from_context(
}
}
- DC_FP_START();
- dcn32_predict_pipe_split(context, [pipe_cnt]);
- DC_FP_END();
pipe_cnt++;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 0c68cd97a461..496f0f58fa7d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -348,90 +348,6 @@ void dcn32_helper_populate_phantom_dlg_params(struct dc
*dc,
}
}
-/**
- * dcn32_predict_pipe_split - Predict if pipe split will occur for a given DML
pipe
- * @context: [in] New DC state to be programmed
- * @pipe_e2e: [in] DML pipe end to end context
- *
- * This function takes in a DML pipe (pipe_e2e) and predicts if pipe split is
required (both
- * ODM and MPC). For pipe split, ODM combine is determined by the ODM mode,
and MPC combine is
- * determined by DPPClk requirements
- *
- * This function follows the same policy as DML:
- * - Check for ODM combine requirements / policy first
- * - MPC combine is only chosen if there is no ODM combine requirements /
policy in place, and
- * MPC is required
- *
- * Return: Number of splits expected (1 for 2:1 split, 3 for 4:1 split, 0 for
no splits).
- */
-uint8_t dcn32_predict_pipe_split(struct dc_state *context,
- display_e2e_pipe_params_st *pipe_e2e)
-{
- double pscl_throughput;
- double pscl_throughput_chroma;
- double dpp_clk_single_dpp, clock;
- double clk_frequency = 0.0;
- double vco_speed = context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz;
- bool total_available_pipes_support = false;
- uint32_t number_of_dpp = 0;
- enum odm_combine_mode odm_mode = dm_odm_combine_mode_disabled;
- double req_dispclk_per_surface = 0;
- uint8_t num_splits = 0;
-
- dc_assert_fp_enabled();
-
-
dml32_CalculateODMMode(context->bw_ctx.dml.ip.maximum_pixels_per_line_per_dsc_unit,
- pipe_e2e->pipe.dest.hactive,
- pipe_e2e->dout.output_format,
- pipe_e2e->dout.output_type,
- pipe_e2e->pipe.dest.odm_combine_policy,
-
context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states -
1].dispclk_mhz,
-
context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states -
1].dispclk_mhz,
- pipe_e2e->dout.dsc_enable != 0,
- 0, /* TotalNumberOfActiveDPP can be 0 since we're
predicting pipe split requirement */
- context->bw_ctx.dml.ip.max_num_dpp,
- pipe_e2e->pipe.dest.pixel_rate_mhz,
- context->bw_ctx.dml.soc.dcn_downspread_percent,
- context->bw_ctx.dml.ip.dispclk_ramp_margin_percent,
- context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz,
- pipe_e2e->dout.dsc_slices,
- /* Output */
- _available_pipes_support,
- _of_dpp,
- _mode,
- _dispclk_per_surface);
-
-
dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(pipe_e2e->pipe.scale_ratio_depth.hscl_ratio,
- pipe_e2e->pipe.scale_ratio_depth.hscl_ratio_c,
- pipe_e2e->pipe.scale_ratio_depth.vscl_ratio,
- pipe_e2e->pipe.scale_ratio_depth.vscl_ratio_c,
- context->bw_ctx.dml.ip.max_dchub_pscl_bw_pix_per_clk,
- context->bw_ctx.dml.ip.max_pscl_lb_bw_pix_per_clk,
- pipe_e2e->pipe.dest.pixel_rate_mhz,
- pipe_e2e->pipe.src.source_format,
- pipe_e2e->pipe.scale_taps.htaps,
- pipe_e2e->pipe.scale_taps.htaps_c,
- pipe_e2e->pipe.scale_taps.vtaps,
-
[PATCH 13/28] drm/amd/display: Add DCHUBBUB callback to report MALL status
From: Aurabindo Pillai
[Why]
For enabling automated testing, add a hook to DCHUBBUB interface so that
mall status can be queried by userspace through debugfs. This removes
dependence on requiring a userspace tool like UMR for querying status
for MALL static screen IGT test.
Reviewed-by: Alvin Lee
Acked-by: Stylon Wang
Signed-off-by: Aurabindo Pillai
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 13 ++---
.../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h| 5 -
.../gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c| 14 +-
.../gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h| 6 +-
.../gpu/drm/amd/display/dc/dcn32/dcn32_resource.h | 1 +
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 1 +
6 files changed, 34 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 05c1ad98a1f6..1259d6351c50 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -37,6 +37,7 @@
#include "link_hwss.h"
#include "dc/dc_dmub_srv.h"
#include "link/protocols/link_dp_capability.h"
+#include "inc/hw/dchubbub.h"
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
#include "amdgpu_dm_psr.h"
@@ -3642,10 +3643,16 @@ DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops,
disable_hpd_get,
static int capabilities_show(struct seq_file *m, void *unused)
{
struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
- struct dc_caps caps = adev->dm.dc->caps;
- bool mall_supported = caps.mall_size_total;
+ struct dc *dc = adev->dm.dc;
+ bool mall_supported = dc->caps.mall_size_total;
+ unsigned int mall_in_use = false;
+ struct hubbub *hubbub = dc->res_pool->hubbub;
+
+ if (hubbub->funcs->get_mall_en)
+ hubbub->funcs->get_mall_en(hubbub, _in_use);
- seq_printf(m, "mall: %s\n", mall_supported ? "yes" : "no");
+ seq_printf(m, "mall supported: %s, enabled: %s\n",
+ mall_supported ? "yes" : "no", mall_in_use ? "yes" :
"no");
return 0;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
index adc876156d2e..5ddf2b36986e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -171,6 +171,7 @@ struct dcn_hubbub_registers {
uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B;
uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C;
uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D;
+ uint32_t DCHUBBUB_ARB_MALL_CNTL;
uint32_t SDPIF_REQUEST_RATE_LIMIT;
uint32_t DCHUBBUB_SDPIF_CFG0;
uint32_t DCHUBBUB_SDPIF_CFG1;
@@ -194,7 +195,9 @@ struct dcn_hubbub_registers {
type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A;\
type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B;\
type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C;\
- type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D
+ type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D;\
+ type MALL_PREFETCH_COMPLETE;\
+ type MALL_IN_USE
#define HUBBUB_REG_FIELD_LIST_DCN35(type) \
type DCHUBBUB_FGCG_REP_DIS
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
index 8bfef6d095b2..88dfc907553d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
@@ -945,6 +945,17 @@ void hubbub32_force_wm_propagate_to_pipes(struct hubbub
*hubbub)
DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
}
+void hubbub32_get_mall_en(struct hubbub *hubbub, unsigned int *mall_in_use)
+{
+ struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+ uint32_t prefetch_complete, mall_en;
+
+ REG_GET_2(DCHUBBUB_ARB_MALL_CNTL, MALL_IN_USE, _en,
+ MALL_PREFETCH_COMPLETE, _complete);
+
+ *mall_in_use = prefetch_complete && mall_en;
+}
+
void hubbub32_init(struct hubbub *hubbub)
{
struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
@@ -995,7 +1006,8 @@ static const struct hubbub_funcs hubbub32_funcs = {
.init_crb = dcn32_init_crb,
.hubbub_read_state = hubbub2_read_state,
.force_usr_retraining_allow = hubbub32_force_usr_retraining_allow,
- .set_request_limit = hubbub32_set_request_limit
+ .set_request_limit = hubbub32_set_request_limit,
+ .get_mall_en = hubbub32_get_mall_en,
};
void hubbub32_construct(struct dcn20_hubbub *hubbub2,
diff --git a/drivers/gpu/drm/am
[PATCH 12/28] drm/amd/display: Add new logs for AutoDPMTest
From: Ethan Bitnun
[Description]
- Add new logs to be used by the AutoDPMTest
- Enclose AutoDPMTest logs in settings
- Add logging definition
Reviewed-by: Alvin Lee
Acked-by: Stylon Wang
Signed-off-by: Ethan Bitnun
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 36 +++
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../drm/amd/display/include/logger_types.h| 5 ++-
3 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 984b52923534..4fd25bb1ab92 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -450,6 +450,38 @@ static int dcn32_get_dispclk_from_dentist(struct clk_mgr
*clk_mgr_base)
return 0;
}
+static void dcn32_auto_dpm_test_log(struct dc_clocks *new_clocks, struct
clk_mgr_internal *clk_mgr)
+{
+
+ // IMPORTANT: When adding more clocks to these logs, do NOT
put a newline
+ // anywhere other than at the very end of
the string.
+ //
+ // Formatting example (make sure to have " - " between each entry):
+ //
+ // AutoDPMTest: clk1:%d - clk2:%d -
clk3:%d - clk4:%d\n"
+
+ if (new_clocks &&
+ new_clocks->dramclk_khz > 0 &&
+ new_clocks->fclk_khz > 0 &&
+ new_clocks->dcfclk_khz > 0 &&
+ new_clocks->dppclk_khz > 0) {
+
+ if (new_clocks->p_state_change_support) {
+ DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk_khz:%d -
fclk_khz:%d - "
+"dcfclk_khz:%d -
dppclk_khz:%d\n",
+new_clocks->dramclk_khz,
+new_clocks->fclk_khz,
+new_clocks->dcfclk_khz,
+new_clocks->dppclk_khz);
+ } else {
+ DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk_khz:1249000
- fclk_khz:%d - "
+"dcfclk_khz:%d -
dppclk_khz:%d\n",
+new_clocks->fclk_khz,
+new_clocks->dcfclk_khz,
+new_clocks->dppclk_khz);
+ }
+ }
+}
static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
struct dc_state *context,
@@ -646,6 +678,10 @@ static void dcn32_update_clocks(struct clk_mgr
*clk_mgr_base,
/*update dmcu for wait_loop count*/
dmcu->funcs->set_psr_wait_loop(dmcu,
clk_mgr_base->clks.dispclk_khz / 1000 / 7);
+
+ if (dc->config.enable_auto_dpm_test_logs) {
+ dcn32_auto_dpm_test_log(new_clocks, clk_mgr);
+ }
}
static uint32_t dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal
*clk_mgr)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 7e6f819a9952..05ab24c81041 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -420,6 +420,7 @@ struct dc_config {
int sdpif_request_limit_words_per_umc;
bool use_old_fixed_vs_sequence;
bool dc_mode_clk_limit_support;
+ bool enable_auto_dpm_test_logs;
};
enum visual_confirm {
diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h
b/drivers/gpu/drm/amd/display/include/logger_types.h
index 3bf08a60c45c..fb657f7408a7 100644
--- a/drivers/gpu/drm/amd/display/include/logger_types.h
+++ b/drivers/gpu/drm/amd/display/include/logger_types.h
@@ -73,6 +73,7 @@
#define DC_LOG_SMU(...) pr_debug("[SMU_MSG]:"__VA_ARGS__)
#define DC_LOG_DWB(...) DRM_DEBUG_KMS(__VA_ARGS__)
#define DC_LOG_DP2(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_AUTO_DPM_TEST(...) pr_debug("[AutoDPMTest]: "__VA_ARGS__)
struct dal_logger;
@@ -128,6 +129,7 @@ enum dc_log_type {
LOG_SAMPLE_1DLUT,
LOG_DP2,
LOG_DC2RESERVED12,
+ LOG_AUTO_DPM_TEST,
};
#define DC_MIN_LOG_MASK ((1 << LOG_ERROR) | \
@@ -157,7 +159,8 @@ enum dc_log_type {
(1ULL << LOG_IF_TRACE) | \
(1ULL << LOG_HDMI_FRL) | \
(1ULL << LOG_SCALER) | \
- (1ULL << LOG_DTN) /* | \
+ (1ULL << LOG_DTN) | \
+ (1ULL << LOG_AUTO_DPM_TEST)/* | \
(1ULL << LOG_DEBUG) | \
(1ULL << LOG_BIOS) | \
(1ULL << LOG_SURFACE) | \
--
2.42.0
[PATCH 11/28] drm/amd/display: support main link off before specific vertical line
From: Paul Hsieh
[Why]
Some panels request main link off before specific vertical line.
If source turn off main link after specific vertical line then
panel defect will be exposed.
[How]
Add interface to support turn off main link before specific
vertical line
Reviewed-by: Robin Chen
Acked-by: Stylon Wang
Signed-off-by: Paul Hsieh
---
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 10 +-
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h| 4 ++--
.../gpu/drm/amd/display/include/ddc_service_types.h| 1 +
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 0f24b6fbd220..f27cc8f9d0aa 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -35,6 +35,7 @@
static const uint8_t DP_SINK_DEVICE_STR_ID_1[] = {7, 1, 8, 7, 3};
static const uint8_t DP_SINK_DEVICE_STR_ID_2[] = {7, 1, 8, 7, 5};
+static const uint8_t DP_SINK_DEVICE_STR_ID_3[] = {0x42, 0x61, 0x6c, 0x73,
0x61};
/*
* Convert dmcub psr state to dmcu psr state.
@@ -295,7 +296,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
struct psr_context *psr_context,
uint8_t panel_inst)
{
- union dmub_rb_cmd cmd;
+ union dmub_rb_cmd cmd = { 0 };
struct dc_context *dc = dmub->ctx;
struct dmub_cmd_psr_copy_settings_data *copy_settings_data
= _copy_settings.psr_copy_settings_data;
@@ -408,6 +409,13 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
else
copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 0;
+ if (link->psr_settings.psr_version == DC_PSR_VERSION_1 &&
+ link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_0022B9 &&
+ !memcmp(link->dpcd_caps.sink_dev_id_str,
DP_SINK_DEVICE_STR_ID_3,
+ sizeof(DP_SINK_DEVICE_STR_ID_3))) {
+ copy_settings_data->poweroff_before_vertical_line = 16;
+ }
+
//WA for PSR1 on specific TCON, require frame delay for frame re-lock
copy_settings_data->relock_delay_frame_cnt = 0;
if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 0367d0850495..6e705b219872 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -2283,9 +2283,9 @@ struct dmub_cmd_psr_copy_settings_data {
*/
uint16_t dsc_slice_height;
/**
-* Explicit padding to 4 byte boundary.
+* Some panels request main link off before xth vertical line
*/
- uint16_t pad;
+ uint16_t poweroff_before_vertical_line;
};
/**
diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
index 68dfc7968017..1c603b12957f 100644
--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
@@ -39,6 +39,7 @@
#define DP_BRANCH_HW_REV_10 0x10
#define DP_BRANCH_HW_REV_20 0x20
+#define DP_DEVICE_ID_0022B9 0x0022B9
#define DP_DEVICE_ID_38EC11 0x38EC11
#define DP_DEVICE_ID_BA4159 0xBA4159
#define DP_FORCE_PSRSU_CAPABILITY 0x40F
--
2.42.0
[PATCH 10/28] drm/amd/display: Adjust the MST resume flow
From: Wayne Lin
[Why]
In drm_dp_mst_topology_mgr_resume() today, it will resume the
mst branch to be ready handling mst mode and also consecutively do
the mst topology probing. Which will cause the dirver have chance
to fire hotplug event before restoring the old state. Then Userspace
will react to the hotplug event based on a wrong state.
[How]
Adjust the mst resume flow as:
1. set dpcd to resume mst branch status
2. restore source old state
3. Do mst resume topology probing
For drm_dp_mst_topology_mgr_resume(), it's better to adjust it to
pull out topology probing work into a 2nd part procedure of the mst
resume. Will have a follow up patch in drm.
Reviewed-by: Chao-kai Wang
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Stylon Wang
Signed-off-by: Wayne Lin
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 93 ---
1 file changed, 80 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 93f8ec2acb4a..15bd87200f6d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2350,14 +2350,62 @@ static int dm_late_init(void *handle)
return detect_mst_link_for_all_connectors(adev_to_drm(adev));
}
+static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
+{
+ int ret;
+ u8 guid[16];
+ u64 tmp64;
+
+ mutex_lock(>lock);
+ if (!mgr->mst_primary)
+ goto out_fail;
+
+ if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) {
+ drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during
suspend?\n");
+ goto out_fail;
+ }
+
+ ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
+DP_MST_EN |
+DP_UP_REQ_EN |
+DP_UPSTREAM_IS_SRC);
+ if (ret < 0) {
+ drm_dbg_kms(mgr->dev, "mst write failed - undocked during
suspend?\n");
+ goto out_fail;
+ }
+
+ /* Some hubs forget their guids after they resume */
+ ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
+ if (ret != 16) {
+ drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during
suspend?\n");
+ goto out_fail;
+ }
+
+ if (memchr_inv(guid, 0, 16) == NULL) {
+ tmp64 = get_jiffies_64();
+ memcpy([0], , sizeof(u64));
+ memcpy([8], , sizeof(u64));
+
+ ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16);
+
+ if (ret != 16) {
+ drm_dbg_kms(mgr->dev, "check mstb guid failed -
undocked during suspend?\n");
+ goto out_fail;
+ }
+ }
+
+ memcpy(mgr->mst_primary->guid, guid, 16);
+
+out_fail:
+ mutex_unlock(>lock);
+}
+
static void s3_handle_mst(struct drm_device *dev, bool suspend)
{
struct amdgpu_dm_connector *aconnector;
struct drm_connector *connector;
struct drm_connector_list_iter iter;
struct drm_dp_mst_topology_mgr *mgr;
- int ret;
- bool need_hotplug = false;
drm_connector_list_iter_begin(dev, );
drm_for_each_connector_iter(connector, ) {
@@ -2379,18 +2427,15 @@ static void s3_handle_mst(struct drm_device *dev, bool
suspend)
if (!dp_is_lttpr_present(aconnector->dc_link))
try_to_configure_aux_timeout(aconnector->dc_link->ddc,
LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
- ret = drm_dp_mst_topology_mgr_resume(mgr, true);
- if (ret < 0) {
-
dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
- aconnector->dc_link);
- need_hotplug = true;
- }
+ /* TODO: move resume_mst_branch_status() into drm mst
resume again
+* once topology probing work is pulled out from mst
resume into mst
+* resume 2nd step. mst resume 2nd step should be
called after old
+* state getting restored (i.e.
drm_atomic_helper_resume()).
+*/
+ resume_mst_branch_status(mgr);
}
}
drm_connector_list_iter_end();
-
- if (need_hotplug)
- drm_kms_helper_hotplug_event(dev);
}
static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
@@ -2784,7 +2829,8 @@ static int dm_resume(void *handle)
struct dm_atomic_state *dm_state =
to_dm_atomic_state(dm->atomic_obj.state);
enum dc_connection_type new_connection_type = dc_connection_none;
[PATCH 09/28] drm/amd/display: Fix 2nd DPIA encoder Assignment
From: Mustapha Ghaddar
[HOW & Why]
There seems to be an issue with 2nd DPIA acquiring link encoder for tiled
displays.
Solution is to remove check for eng_id before we get first dynamic encoder for
it
Reviewed-by: Cruise Hung
Reviewed-by: Meenakshikumar Somasundaram
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Stylon Wang
Signed-off-by: Mustapha Ghaddar
---
drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
index b66eeac4d3d2..be5a6d008b29 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
@@ -395,8 +395,7 @@ void link_enc_cfg_link_encs_assign(
stream->link->dpia_preferred_eng_id !=
ENGINE_ID_UNKNOWN)
eng_id_req =
stream->link->dpia_preferred_eng_id;
- if (eng_id == ENGINE_ID_UNKNOWN)
- eng_id = find_first_avail_link_enc(stream->ctx,
state, eng_id_req);
+ eng_id = find_first_avail_link_enc(stream->ctx, state,
eng_id_req);
}
else
eng_id = link_enc->preferred_engine;
@@ -501,7 +500,6 @@ struct dc_link *link_enc_cfg_get_link_using_link_enc(
if (stream)
link = stream->link;
- // dm_output_to_console("%s: No link using DIG(%d).\n", __func__,
eng_id);
return link;
}
--
2.42.0
[PATCH 08/28] drm/amd/display: do not block ODM + OPM on one side of the screen
From: Wenjing Liu
[why]
build scaling param is overriding validation policy regarding small viewport
support. Even if ODM + windowed MPO is not supported. The decision has
to be made at the time of validation. When building scaling params, we might
be building an initial dc state as an input to DML validation. The initial state
is not supposed to be always valid and we rely on DML to modify the initial
dc state and determine the final validation result. This check is pre judging
validation result when building the initial dc state.
This causes an issue where we are transitioning from desktop only ODM
combine 2:1 to ODM bypass with 2 planes. In this case we are building
an initial state with with ODM 2:1 combine + 2 planes. This is indeed not
supported but DML is about to modify the state so it no longer uses ODM
combine. Before it reaches DML, dc resource already fails validation because
it checks that the initial state is not supported by our policy. This overrides
the ODM decision to validate this state with ODM combine disabled. Therefore
causes an unexpected validation failure when the secondary plane is added
on one side of the screen.
Reviewed-by: Dillon Varone
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index c929003825f4..494efbede0b2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1371,13 +1371,6 @@ bool resource_build_scaling_params(struct pipe_ctx
*pipe_ctx)
/* depends on scaling ratios and recout, does not calculate offset yet
*/
calculate_viewport_size(pipe_ctx);
- if (!pipe_ctx->stream->ctx->dc->config.enable_windowed_mpo_odm) {
- /* Stopgap for validation of ODM + MPO on one side of screen
case */
- if (pipe_ctx->plane_res.scl_data.viewport.height < 1 ||
- pipe_ctx->plane_res.scl_data.viewport.width < 1)
- return false;
- }
-
/*
* LB calculations depend on vp size, h/v_active and scaling ratios
* Setting line buffer pixel depth to 24bpp yields banding
--
2.42.0
[PATCH 07/28] drm/amd/display: Fix DML calculation errors
From: Nicholas Susanto
[Why]
DML calculations differ with DCN3.1 spreadsheet values due to
translations errors from the visual basic code
[How]
Add missing calculations that set the value for DSCDelay
Reviewed-by: Nicholas Kazlauskas
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
Signed-off-by: Nicholas Susanto
---
.../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c| 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
index a94aa0f21a7f..88e56889a68c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -2311,6 +2311,7 @@ static void
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
v->OutputFormat[k],
v->Output[k]) +
dscComputeDelay(v->OutputFormat[k], v->Output[k]));
}
+ v->DSCDelay[k] = v->DSCDelay[k] + (v->HTotal[k] -
v->HActive[k]) * dml_ceil((double) v->DSCDelay[k] / v->HActive[k], 1);
v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] /
v->PixelClockBackEnd[k];
} else {
v->DSCDelay[k] = 0;
@@ -4719,6 +4720,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_
v->OutputFormat[k],
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
}
+ v->DSCDelayPerState[i][k] =
v->DSCDelayPerState[i][k] + (v->HTotal[k] - v->HActive[k]) * dml_ceil((double)
v->DSCDelayPerState[i][k] / v->HActive[k], 1.0);
v->DSCDelayPerState[i][k] =
v->DSCDelayPerState[i][k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
} else {
v->DSCDelayPerState[i][k] = 0.0;
--
2.42.0
[PATCH 06/28] drm/amd/display: [FW Promotion] Release 0.0.181.0
From: Anthony Koo
- Add new params to dmub_feature_caps for checking replay
support in FW
Acked-by: Stylon Wang
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index e2aebba29f68..0367d0850495 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -450,6 +450,8 @@ struct dmub_feature_caps {
uint8_t reserved[4];
uint8_t subvp_psr_support;
uint8_t gecc_enable;
+ uint8_t replay_supported;
+ uint8_t replay_reserved[3];
};
struct dmub_visual_confirm_color {
--
2.42.0
[PATCH 05/28] drm/amd/display: Don't check registers, if using AUX BL control
From: Swapnil Patel
[Why]
Currently the driver looks DCN registers to access if BL is on or not.
This check is not valid if we are using AUX based brightness control.
This causes driver to not send out "backlight off" command during power off
sequence as it already thinks it is off.
[How]
Only check DCN registers if we aren't using AUX based brightness control.
Reviewed-by: Wenjing Liu
Acked-by: Stylon Wang
Signed-off-by: Swapnil Patel
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 602fb149dc10..31454db00ed5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -964,7 +964,9 @@ void dce110_edp_backlight_control(
return;
}
- if (link->panel_cntl) {
+ if (link->panel_cntl && !(link->dpcd_sink_ext_caps.bits.oled ||
+ link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
+ link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
bool is_backlight_on =
link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl);
if ((enable && is_backlight_on) || (!enable &&
!is_backlight_on)) {
--
2.42.0
[PATCH 04/28] drm/amd/display: Add dirty rect support for Replay
From: Bhawanpreet Lakha
Dirty rect can be used with replay, so enable them to allow for more
powersaving.
Reviewed-by: Sun peng Li
Acked-by: Stylon Wang
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1bb1a394f55f..93f8ec2acb4a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8103,7 +8103,8 @@ static void amdgpu_dm_commit_planes(struct
drm_atomic_state *state,
bundle->surface_updates[planes_count].plane_info =
>plane_infos[planes_count];
- if
(acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
+ if (acrtc_state->stream->link->psr_settings.psr_feature_enabled
||
+
acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
fill_dc_dirty_rects(plane, old_plane_state,
new_plane_state, new_crtc_state,
>flip_addrs[planes_count],
--
2.42.0
[PATCH 03/28] drm/amd/display: set default return value for ODM Combine debugfs
From: Aurabindo Pillai
[Why]
Set a default return value of -ENOTSUPP to indicate that the hardware
does not support querying ODM Combine mode.
Reviewed-by: Rodrigo Siqueira
Acked-by: Stylon Wang
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 17d1990ea832..05c1ad98a1f6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -1211,7 +1211,7 @@ static int odm_combine_segments_show(struct seq_file *m,
void *unused)
struct amdgpu_dm_connector *aconnector =
to_amdgpu_dm_connector(connector);
struct dc_link *link = aconnector->dc_link;
struct pipe_ctx *pipe_ctx = NULL;
- int i, segments = 0;
+ int i, segments = -EOPNOTSUPP;
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx = >dc->current_state->res_ctx.pipe_ctx[i];
--
2.42.0
[PATCH 02/28] drm/amd/display: Don't lock phantom pipe on disabling
From: Alvin Lee [Description] - When disabling a phantom pipe, we first enable the phantom OTG so the double buffer update can successfully take place - However, want to avoid locking the phantom otherwise setting DPG_EN=1 for the phantom pipe is blocked (without this we could hit underflow due to phantom HUBP being blanked by default) Reviewed-by: Samson Tam Acked-by: Stylon Wang Signed-off-by: Alvin Lee --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 9834b75f1837..79befa17bb03 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -111,7 +111,8 @@ void dcn10_lock_all_pipes(struct dc *dc, if (pipe_ctx->top_pipe || !pipe_ctx->stream || (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) || - !tg->funcs->is_tg_enabled(tg)) + !tg->funcs->is_tg_enabled(tg) || + pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) continue; if (lock) -- 2.42.0
[PATCH 01/28] drm/amd/display: Blank phantom OTG before enabling
From: Alvin Lee
[Description]
Before enabling the phantom OTG for an update we
must enable DPG to avoid underflow.
Reviewed-by: Samson Tam
Acked-by: Stylon Wang
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 50 +--
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 10 +++-
.../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 46 +
.../drm/amd/display/dc/dcn32/dcn32_hwseq.h| 5 ++
.../gpu/drm/amd/display/dc/dcn32/dcn32_init.c | 1 +
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 5 ++
6 files changed, 68 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 20a3b4c81d4b..dcedda85dcdb 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1070,53 +1070,6 @@ static void apply_ctx_interdependent_lock(struct dc *dc,
}
}
-static void phantom_pipe_blank(
- struct dc *dc,
- struct timing_generator *tg,
- int width,
- int height)
-{
- struct dce_hwseq *hws = dc->hwseq;
- enum dc_color_space color_space;
- struct tg_color black_color = {0};
- struct output_pixel_processor *opp = NULL;
- uint32_t num_opps, opp_id_src0, opp_id_src1;
- uint32_t otg_active_width, otg_active_height;
- uint32_t i;
-
- /* program opp dpg blank color */
- color_space = COLOR_SPACE_SRGB;
- color_space_to_black_color(dc, color_space, _color);
-
- otg_active_width = width;
- otg_active_height = height;
-
- /* get the OPTC source */
- tg->funcs->get_optc_source(tg, _opps, _id_src0, _id_src1);
- ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);
-
- for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
- if (dc->res_pool->opps[i] != NULL &&
dc->res_pool->opps[i]->inst == opp_id_src0) {
- opp = dc->res_pool->opps[i];
- break;
- }
- }
-
- if (opp && opp->funcs->opp_set_disp_pattern_generator)
- opp->funcs->opp_set_disp_pattern_generator(
- opp,
- CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
- CONTROLLER_DP_COLOR_SPACE_UDEFINED,
- COLOR_DEPTH_UNDEFINED,
- _color,
- otg_active_width,
- otg_active_height,
- 0);
-
- if (tg->funcs->is_tg_enabled(tg))
- hws->funcs.wait_for_blank_complete(opp);
-}
-
static void dc_update_viusal_confirm_color(struct dc *dc, struct dc_state
*context, struct pipe_ctx *pipe_ctx)
{
if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
@@ -1207,7 +1160,8 @@ static void disable_dangling_plane(struct dc *dc, struct
dc_state *context)
main_pipe_width =
old_stream->mall_stream_config.paired_stream->dst.width;
main_pipe_height =
old_stream->mall_stream_config.paired_stream->dst.height;
- phantom_pipe_blank(dc, tg,
main_pipe_width, main_pipe_height);
+ if (dc->hwss.blank_phantom)
+ dc->hwss.blank_phantom(dc, tg,
main_pipe_width, main_pipe_height);
tg->funcs->enable_crtc(tg);
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index ad82f19fe36a..5ac85df158b9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1840,8 +1840,16 @@ void dcn20_program_front_end_for_ctx(
dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.type ==
SUBVP_PHANTOM) {
struct timing_generator *tg =
dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;
- if (tg->funcs->enable_crtc)
+ if (tg->funcs->enable_crtc) {
+ if (dc->hwss.blank_phantom) {
+ int main_pipe_width, main_pipe_height;
+
+ main_pipe_width =
dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.paired_stream->dst.width;
+ main_pipe_height =
dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.paired_stream->dst.height;
+
[PATCH 00/28] DC Patches Sep 8, 2023
This DC patchset brings improvements in multiple areas. In summary, we have: - Fix MST bugs - Fix ODM combine debugfs - Fix DML calculations - Fix 2nd DPIA encoder issue - Fix AUX-based backlight control - Fix on MPO+ODM use case - Fix DCCG clock programming - Improvements on replay - Improvements on logging and reporting - Improvements on pipe and OTG handling - Improvements and bug fixes on power optimization - Improvements on VRR - Code clean up and fix un-initialized values Cc: Daniel Wheeler Alvin Lee (2): drm/amd/display: Blank phantom OTG before enabling drm/amd/display: Don't lock phantom pipe on disabling Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.181.0 Aric Cyr (1): drm/amd/display: 3.2.250 Aurabindo Pillai (2): drm/amd/display: set default return value for ODM Combine debugfs drm/amd/display: Add DCHUBBUB callback to report MALL status Austin Zheng (1): drm/amd/display: Add check for vrr_active_fixed Bhawanpreet Lakha (1): drm/amd/display: Add dirty rect support for Replay Charlene Liu (1): drm/amd/display: fix some non-initialized register mask and setting Dillon Varone (1): drm/amd/display: add dp dto programming function to dccg Ethan Bitnun (1): drm/amd/display: Add new logs for AutoDPMTest Ian Chen (1): drm/amd/display: add skip_implict_edp_power_control flag for dcn32 Muhammad Ahmed (1): drm/amd/display: Fix MST recognizes connected displays as one Mustapha Ghaddar (1): drm/amd/display: Fix 2nd DPIA encoder Assignment Nicholas Susanto (1): drm/amd/display: Fix DML calculation errors Paul Hsieh (1): drm/amd/display: support main link off before specific vertical line Qingqing Zhuo (1): drm/amd/display: Drop unused registers Sridevi Arvindekar (1): drm/amd/display: dc cleanup for tests Swapnil Patel (1): drm/amd/display: Don't check registers, if using AUX BL control Wayne Lin (1): drm/amd/display: Adjust the MST resume flow Wenjing Liu (8): drm/amd/display: do not block ODM + OPM on one side of the screen drm/amd/display: remove a function that does complex calculation in every frame but not used drm/amd/display: do not attempt ODM power optimization if minimal transition doesn't exist drm/amd/display: only allow ODM power optimization if surface is within guaranteed viewport size drm/amd/display: do not skip ODM minimal transition based on new state drm/amd/display: minior logging improvements drm/amd/display: add seamless pipe topology transition check drm/amd/display: move odm power optimization decision after subvp optimization .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 96 ++- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 15 +- .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 64 ++ drivers/gpu/drm/amd/display/dc/core/dc.c | 107 ++-- .../drm/amd/display/dc/core/dc_link_enc_cfg.c | 4 +- .../gpu/drm/amd/display/dc/core/dc_resource.c | 7 - drivers/gpu/drm/amd/display/dc/dc.h | 3 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 4 +- .../drm/amd/display/dc/dce/dce_clock_source.c | 1 + drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 10 +- .../display/dc/dce110/dce110_hw_sequencer.c | 34 +- .../drm/amd/display/dc/dcn10/dcn10_hubbub.h | 5 +- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 +- .../display/dc/dcn10/dcn10_stream_encoder.h | 5 +- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 20 +- .../drm/amd/display/dc/dcn32/dcn32_hubbub.c | 14 +- .../drm/amd/display/dc/dcn32/dcn32_hubbub.h | 6 +- .../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 104 ++- .../drm/amd/display/dc/dcn32/dcn32_hwseq.h| 9 + .../gpu/drm/amd/display/dc/dcn32/dcn32_init.c | 2 + .../gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c | 2 +- .../drm/amd/display/dc/dcn32/dcn32_resource.c | 79 +-- .../drm/amd/display/dc/dcn32/dcn32_resource.h | 1 + .../display/dc/dcn32/dcn32_resource_helpers.c | 4 +- .../drm/amd/display/dc/dcn35/dcn35_hubbub.h | 2 - .../dc/dml/dcn314/display_mode_vba_314.c | 2 + .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 601 ++ .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.h | 3 - .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 6 +- .../amd/display/dc/inc/hw/clk_mgr_internal.h | 16 +- drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 10 + .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 1 + .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 8 + .../gpu/drm/amd/display/dc/link/link_dpms.c | 10 +- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 6 +- .../amd/display/include/ddc_service_types.h | 1 + .../drm/amd/display/include/logger_types.h| 5 +- 37 files changed, 793 insertions(+), 477 deletions(-) -- 2.42.0
[PATCH 15/15] drm/amd/display: Promote DAL to 3.2.247
From: Aric Cyr This version brings along following fixes: - Improve power saving feature - Clean up for code clarity - Fix MST issues in system resume - Fix crashing bug - Fix pipe allocation for older ASIC - Fix for gamut remap - Fix 8K 60Hz display in test cases - Fix bug in clock gating - Improve DP2 compliance Acked-by: Stylon Wang Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index fc9756ea7cc5..0d0bef8eb331 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -47,7 +47,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.246" +#define DC_VER "3.2.247" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.41.0
[PATCH 14/15] drm/amd/display: [FW Promotion] Release 0.0.179.0
From: Anthony Koo
- Add defines to specify new PHY power states
Acked-by: Stylon Wang
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 6a1571ffeaf9..7afa78b918b5 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -2144,6 +2144,10 @@ enum dmub_phy_fsm_state {
DMUB_PHY_FSM_PLL_EN,
DMUB_PHY_FSM_TX_EN,
DMUB_PHY_FSM_FAST_LP,
+ DMUB_PHY_FSM_P2_PLL_OFF_CPM,
+ DMUB_PHY_FSM_P2_PLL_OFF_PG,
+ DMUB_PHY_FSM_P2_PLL_OFF,
+ DMUB_PHY_FSM_P2_PLL_ON,
};
/**
--
2.41.0
[PATCH 13/15] drm/amd/display: Remove freesync video mode amdgpu parameter
From: Aurabindo Pillai [Why] Freesync Video mode was enabled by default. Hence no need for the module parameter, so remove it completely Acked-by: Stylon Wang Signed-off-by: Aurabindo Pillai Reviewed-by: Stylon Wang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 27 - 2 files changed, 28 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 2e3c7c15cb8e..4de074243c4d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -193,7 +193,6 @@ extern int amdgpu_emu_mode; extern uint amdgpu_smu_memory_pool_size; extern int amdgpu_smu_pptable_id; extern uint amdgpu_dc_feature_mask; -extern uint amdgpu_freesync_vid_mode; extern uint amdgpu_dc_debug_mask; extern uint amdgpu_dc_visual_confirm; extern uint amdgpu_dm_abm_level; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 0fec81d6a7df..8f7d0f8e57ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -187,7 +187,6 @@ int amdgpu_mes_kiq; int amdgpu_noretry = -1; int amdgpu_force_asic_type = -1; int amdgpu_tmz = -1; /* auto */ -uint amdgpu_freesync_vid_mode; int amdgpu_reset_method = -1; /* auto */ int amdgpu_num_kcq = -1; int amdgpu_smartshift_bias; @@ -885,32 +884,6 @@ module_param_named(backlight, amdgpu_backlight, bint, 0444); MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); module_param_named(tmz, amdgpu_tmz, int, 0444); -/** - * DOC: freesync_video (uint) - * Enable the optimization to adjust front porch timing to achieve seamless - * mode change experience when setting a freesync supported mode for which full - * modeset is not needed. - * - * The Display Core will add a set of modes derived from the base FreeSync - * video mode into the corresponding connector's mode list based on commonly - * used refresh rates and VRR range of the connected display, when users enable - * this feature. From the userspace perspective, they can see a seamless mode - * change experience when the change between different refresh rates under the - * same resolution. Additionally, userspace applications such as Video playback - * can read this modeset list and change the refresh rate based on the video - * frame rate. Finally, the userspace can also derive an appropriate mode for a - * particular refresh rate based on the FreeSync Mode and add it to the - * connector's mode list. - * - * Note: This is an experimental feature. - * - * The default value: 0 (off). - */ -MODULE_PARM_DESC( - freesync_video, - "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); -module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); - /** * DOC: reset_method (int) * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) -- 2.41.0
[PATCH 12/15] drm/amd/display: enable low power mode for VGA memory
From: Aurabindo Pillai
[Why]
When unused, all memory blocks should be put in a low power state
[How]
Check the value of enable_mem_low_power.bits.vga and set
corresponding bit in the hardware register
Acked-by: Stylon Wang
Signed-off-by: Aurabindo Pillai
Reviewed-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 4cd4ae07d73d..6cef62d7a2e5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -461,6 +461,11 @@ void dcn30_init_hw(struct dc *dc)
REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3,
ODM_MEM_VBLANK_PWR_MODE, 1);
}
+ if (dc->debug.enable_mem_low_power.bits.vga) {
+ // Power down VGA memory
+ REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
+ }
+
if (dc->ctx->dc_bios->fw_info_valid) {
res_pool->ref_clocks.xtalin_clock_inKhz =
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
--
2.41.0
[PATCH 11/15] drm/amd/display: Add some missing register definitions
From: Aurabindo Pillai
[Why]
Add some missing register definitions and rearrange some others to
maintain consistency with related definitions.
Acked-by: Stylon Wang
Signed-off-by: Aurabindo Pillai
Reviewed-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/dce/dce_hwseq.h| 69 +++
.../include/asic_reg/dcn/dcn_3_0_0_offset.h | 5 ++
.../include/asic_reg/dcn/dcn_3_0_0_sh_mask.h | 5 ++
.../include/asic_reg/dcn/dcn_3_0_2_offset.h | 4 ++
.../include/asic_reg/dcn/dcn_3_0_2_sh_mask.h | 5 +-
5 files changed, 58 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index a3fee929cd12..86233f94db4a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -98,6 +98,29 @@
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
+#define HWSEQ_PIXEL_RATE_REG_LIST_302(blk) \
+ SRII(PIXEL_RATE_CNTL, blk, 0), \
+ SRII(PIXEL_RATE_CNTL, blk, 1),\
+ SRII(PIXEL_RATE_CNTL, blk, 2),\
+ SRII(PIXEL_RATE_CNTL, blk, 3), \
+ SRII(PIXEL_RATE_CNTL, blk, 4)
+
+#define HWSEQ_PHYPLL_REG_LIST_302(blk) \
+ SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
+ SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\
+ SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\
+ SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
+ SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4)
+
+#define HWSEQ_PIXEL_RATE_REG_LIST_303(blk) \
+ SRII(PIXEL_RATE_CNTL, blk, 0), \
+ SRII(PIXEL_RATE_CNTL, blk, 1)
+
+#define HWSEQ_PHYPLL_REG_LIST_303(blk) \
+ SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
+ SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1)
+
+
#define HWSEQ_PHYPLL_REG_LIST_201(blk) \
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1)
@@ -387,7 +410,11 @@
SR(MPC_CRC_RESULT_C), \
SR(MPC_CRC_RESULT_AR), \
SR(AZALIA_AUDIO_DTO), \
- SR(AZALIA_CONTROLLER_CLOCK_GATING)
+ SR(AZALIA_CONTROLLER_CLOCK_GATING), \
+ SR(HPO_TOP_CLOCK_CONTROL), \
+ SR(ODM_MEM_PWR_CTRL3), \
+ SR(DMU_MEM_PWR_CNTL), \
+ SR(MMHUBBUB_MEM_PWR_CNTL)
#define HWSEQ_DCN301_REG_LIST()\
SR(REFCLK_CNTL), \
@@ -508,8 +535,11 @@
SR(D5VGA_CONTROL), \
SR(D6VGA_CONTROL), \
SR(DC_IP_REQUEST_CNTL), \
+ HWSEQ_PIXEL_RATE_REG_LIST_302(OTG), \
+ HWSEQ_PHYPLL_REG_LIST_302(OTG), \
SR(AZALIA_AUDIO_DTO), \
- SR(AZALIA_CONTROLLER_CLOCK_GATING)
+ SR(AZALIA_CONTROLLER_CLOCK_GATING), \
+ SR(HPO_TOP_CLOCK_CONTROL)
#define HWSEQ_DCN303_REG_LIST() \
HWSEQ_DCN_REG_LIST(), \
@@ -540,28 +570,6 @@
SR(AZALIA_CONTROLLER_CLOCK_GATING), \
SR(HPO_TOP_CLOCK_CONTROL)
-#define HWSEQ_PIXEL_RATE_REG_LIST_302(blk) \
- SRII(PIXEL_RATE_CNTL, blk, 0), \
- SRII(PIXEL_RATE_CNTL, blk, 1),\
- SRII(PIXEL_RATE_CNTL, blk, 2),\
- SRII(PIXEL_RATE_CNTL, blk, 3), \
- SRII(PIXEL_RATE_CNTL, blk, 4)
-
-#define HWSEQ_PHYPLL_REG_LIST_302(blk) \
- SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
- SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\
- SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\
- SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
- SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4)
-
-#define HWSEQ_PIXEL_RATE_REG_LIST_303(blk) \
- SRII(PIXEL_RATE_CNTL, blk, 0), \
- SRII(PIXEL_RATE_CNTL, blk, 1)
-
-#define HWSEQ_PHYPLL_REG_LIST_303(blk) \
- SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
- SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1)
-
struct dce_hwseq_registers {
uint32_t DCFE_CLOCK_CONTROL[6];
uint32_t DCFEV_CLOCK_CONTROL;
@@ -663,14 +671,15 @@ struct dce_hwseq_registers {
uint32_t MC_VM_XGMI_LFB_CNTL;
uint32_t AZALIA_AUDIO_DTO;
uint32_t AZALIA_CONTROLLER_CLOCK_GATING;
+ /* MMHUB VM */
+ uint32_t MC_VM_FB_LOCATION_BASE;
+ uint32_t MC_VM_FB_LOCATION_TOP;
+ uint32_t MC_VM_FB_OFFSET;
+ uint32_t MMHUBBUB_MEM_PWR_CNTL;
uint32_t HPO_TOP_CLOCK_CONTROL;
uint32_t ODM_MEM_PWR_CTRL3;
uint32_t DMU_MEM_PWR_CNTL;
- uint32_t MMHUBBUB_MEM_PWR_CNTL;
uint32_t DCHUBBUB_ARB_HOSTVM_CNTL;
- uint32_t MC_VM_FB_LOCATION_BASE;
- uint32_t MC_VM_FB_LOCATION_TOP;
- uint32_t MC_VM_FB_OFFSET;
uint32_t HPO_TOP_HW_CONTROL;
};
/* set field name */
@@ -915,6 +924,7 @@ struct dce_hwseq_registers {
#define HWSEQ_DCN30_MASK_SH_LIST(mask_sh)\
HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \
HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
+ HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_GATE_DIS, mask_sh), \
HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
@@ -1012,7 +1022,8 @@ struct dce_hwseq_registers
[PATCH 10/15] drm/amd/display: implement pipe type definition and adding accessors
From: Wenjing Liu
[why]
There is a lack of encapsulation of pipe connection representation in pipe
context.
This has caused many challenging bugs and coding errors with repeated
logic to identify the same pipe type.
[how]
Formally define pipe types and provide getters to identify a pipe type and
find a pipe based on specific requirements. Update existing logic in non dcn
specific files and dcn32 and future versions to use the new accessors.
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 41 +---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 186 ---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 22 +-
.../amd/display/dc/dce100/dce100_resource.c | 2 +-
.../amd/display/dc/dce110/dce110_resource.c | 2 +-
.../amd/display/dc/dce112/dce112_resource.c | 4 +-
.../drm/amd/display/dc/dcn10/dcn10_resource.c | 6 +-
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 18 +-
.../amd/display/dc/dcn201/dcn201_resource.c | 4 +-
.../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 12 +-
.../drm/amd/display/dc/dcn32/dcn32_resource.c | 4 +-
.../display/dc/dcn32/dcn32_resource_helpers.c | 12 +-
.../drm/amd/display/dc/dml/calcs/dce_calcs.c | 2 +-
.../drm/amd/display/dc/dml/calcs/dcn_calcs.c | 2 +-
.../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 2 +-
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 11 +-
drivers/gpu/drm/amd/display/dc/inc/resource.h | 220 --
.../display/dc/link/accessories/link_dp_cts.c | 3 +-
.../gpu/drm/amd/display/dc/link/link_dpms.c | 7 +-
19 files changed, 375 insertions(+), 185 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 8504e6ee9582..b87422eb7e1a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -586,18 +586,15 @@ dc_stream_forward_crc_window(struct dc_stream_state
*stream,
bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
struct crc_params *crc_window, bool enable, bool
continuous)
{
- int i;
struct pipe_ctx *pipe;
struct crc_params param;
struct timing_generator *tg;
- for (i = 0; i < MAX_PIPES; i++) {
- pipe = >current_state->res_ctx.pipe_ctx[i];
- if (pipe->stream == stream && !pipe->top_pipe &&
!pipe->prev_odm_pipe)
- break;
- }
+ pipe = resource_get_otg_master_for_stream(
+ >current_state->res_ctx, stream);
+
/* Stream not found */
- if (i == MAX_PIPES)
+ if (pipe == NULL)
return false;
/* By default, capture the full frame */
@@ -1064,7 +1061,7 @@ static void apply_ctx_interdependent_lock(struct dc *dc,
// Copied conditions that were previously in
dce110_apply_ctx_for_surface
if (stream == pipe_ctx->stream) {
- if (!pipe_ctx->top_pipe &&
+ if (resource_is_pipe_type(pipe_ctx, OPP_HEAD) &&
(pipe_ctx->plane_state ||
old_pipe_ctx->plane_state))
dc->hwss.pipe_control_lock(dc,
pipe_ctx, lock);
}
@@ -3164,7 +3161,7 @@ static void commit_planes_do_stream_update(struct dc *dc,
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[j];
- if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe &&
pipe_ctx->stream == stream) {
+ if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) &&
pipe_ctx->stream == stream) {
if (stream_update->periodic_interrupt &&
dc->hwss.setup_periodic_interrupt)
dc->hwss.setup_periodic_interrupt(dc, pipe_ctx);
@@ -3443,16 +3440,9 @@ static void commit_planes_for_stream_fast(struct dc *dc,
struct pipe_ctx *top_pipe_to_program = NULL;
dc_z10_restore(dc);
- for (j = 0; j < dc->res_pool->pipe_count; j++) {
- struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[j];
-
- if (!pipe_ctx->top_pipe &&
- !pipe_ctx->prev_odm_pipe &&
- pipe_ctx->stream &&
- pipe_ctx->stream == stream) {
- top_pipe_to_program = pipe_ctx;
- }
- }
+ top_pipe_to_program = resource_get_otg_master_for_stream(
+ >res_ctx,
+ stream);
if (dc->debug.visual_confirm) {
for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -3557,16 +3547
[PATCH 09/15] drm/amd/display: avoid crash and add z8_marks related in dml
From: Charlene Liu
[why]
add dml1 used calculate_wm_and_dlg function pointer check to prevent crash.
add z8 watermarks to struct for later asic use
Reviewed-by: Alvin Lee
Acked-by: Stylon Wang
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 4 ++--
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h| 2 ++
4 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index e6220ecf1d7d..88c0b24a3249 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2063,7 +2063,8 @@ bool dcn30_validate_bandwidth(struct dc *dc,
}
DC_FP_START();
- dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt,
vlevel);
+ if (dc->res_pool->funcs->calculate_wm_and_dlg)
+ dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes,
pipe_cnt, vlevel);
DC_FP_END();
BW_VAL_TRACE_END_WATERMARKS();
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index cdaa33707f5c..82de4fe2637f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1781,8 +1781,8 @@ bool dcn31_validate_bandwidth(struct dc *dc,
BW_VAL_TRACE_SKIP(fast);
goto validate_out;
}
-
- dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt,
vlevel);
+ if (dc->res_pool->funcs->calculate_wm_and_dlg)
+ dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes,
pipe_cnt, vlevel);
BW_VAL_TRACE_END_WATERMARKS();
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 4e09ba4f2806..1c1fb2fa0822 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -1740,8 +1740,8 @@ bool dcn314_validate_bandwidth(struct dc *dc,
BW_VAL_TRACE_SKIP(fast);
goto validate_out;
}
-
- dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt,
vlevel);
+ if (dc->res_pool->funcs->calculate_wm_and_dlg)
+ dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes,
pipe_cnt, vlevel);
BW_VAL_TRACE_END_WATERMARKS();
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index aaa293613846..f5677dbb4e7d 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -49,6 +49,8 @@ struct dcn_hubbub_wm_set {
uint32_t dram_clk_change;
uint32_t usr_retrain;
uint32_t fclk_pstate_change;
+ uint32_t sr_enter_exit_Z8;
+ uint32_t sr_enter_Z8;
};
struct dcn_hubbub_wm {
--
2.41.0
[PATCH 08/15] drm/amd/display: Adjust the resume flow
From: Wayne Lin
[Why]
In current dm_resume, dm->cached_state is restored after link get
detected and updated which will cause problems especially for MST
case.
In drm_dp_mst_topology_mgr_resume() today, it will resume the
mst branch to be ready handling mst mode and also consecutively do
the mst topology probing. Which will cause the dirver have chance
to fire hotplug event before restoring the old state. Then Userspace
will react to the hotplug event based on a wrong state.
[How]
Adjust the resume flow as:
1. restore old state first
2. link detect/topology probing and notify userspace
3. userspace commits new state
For drm_dp_mst_topology_mgr_resume(), it's better to adjust it to
pull out topology probing work into a 2nd part procedure of the mst
resume. Will have a follow up patch in drm.
Reviewed-by: Stylon Wang
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Stylon Wang
Signed-off-by: Wayne Lin
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 185 +-
1 file changed, 131 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index a4d57289d07a..2a6ffe11be72 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2334,14 +2334,62 @@ static int dm_late_init(void *handle)
return detect_mst_link_for_all_connectors(adev_to_drm(adev));
}
+static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
+{
+ int ret;
+ u8 guid[16];
+ u64 tmp64;
+
+ mutex_lock(>lock);
+ if (!mgr->mst_primary)
+ goto out_fail;
+
+ if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) {
+ drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during
suspend?\n");
+ goto out_fail;
+ }
+
+ ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
+DP_MST_EN |
+DP_UP_REQ_EN |
+DP_UPSTREAM_IS_SRC);
+ if (ret < 0) {
+ drm_dbg_kms(mgr->dev, "mst write failed - undocked during
suspend?\n");
+ goto out_fail;
+ }
+
+ /* Some hubs forget their guids after they resume */
+ ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
+ if (ret != 16) {
+ drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during
suspend?\n");
+ goto out_fail;
+ }
+
+ if (memchr_inv(guid, 0, 16) == NULL) {
+ tmp64 = get_jiffies_64();
+ memcpy([0], , sizeof(u64));
+ memcpy([8], , sizeof(u64));
+
+ ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16);
+
+ if (ret != 16) {
+ drm_dbg_kms(mgr->dev, "check mstb guid failed -
undocked during suspend?\n");
+ goto out_fail;
+ }
+ }
+
+ memcpy(mgr->mst_primary->guid, guid, 16);
+
+out_fail:
+ mutex_unlock(>lock);
+}
+
static void s3_handle_mst(struct drm_device *dev, bool suspend)
{
struct amdgpu_dm_connector *aconnector;
struct drm_connector *connector;
struct drm_connector_list_iter iter;
struct drm_dp_mst_topology_mgr *mgr;
- int ret;
- bool need_hotplug = false;
drm_connector_list_iter_begin(dev, );
drm_for_each_connector_iter(connector, ) {
@@ -2363,18 +2411,15 @@ static void s3_handle_mst(struct drm_device *dev, bool
suspend)
if (!dp_is_lttpr_present(aconnector->dc_link))
try_to_configure_aux_timeout(aconnector->dc_link->ddc,
LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
- ret = drm_dp_mst_topology_mgr_resume(mgr, true);
- if (ret < 0) {
-
dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
- aconnector->dc_link);
- need_hotplug = true;
- }
+ /* TODO: move resume_mst_branch_status() into drm mst
resume again
+* once topology probing work is pulled out from mst
resume into mst
+* resume 2nd step. mst resume 2nd step should be
called after old
+* state getting restored (i.e.
drm_atomic_helper_resume()).
+*/
+ resume_mst_branch_status(mgr);
}
}
drm_connector_list_iter_end();
-
- if (need_hotplug)
- drm_kms_helper_hotplug_event(dev);
}
static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
@@ -2751,14 +2796,80 @@ static void dm_gpureset_commit_state(struct dc_state
[PATCH 07/15] drm/amd/display: fix incorrect stream_res allocation for older ASIC
From: Wenjing Liu
[why]
There is a recent work for developing a new pipe resource allocation
policy used for new ASIC. The new code change needs to modify asic
independent pipe resource allocation flow and hook up the new allocation
policy in asic dependent layer. Unfortunately this change revealed a
hidden bug in the old pipe resource allocation sequence used for older
asics. In the older version of acquiring pipe for layer, we are always
assigning otg master's opp and tg to the newly allocated secondary dpp
pipe. This logic is incorrect when the secodnary dpp
pipe is connected to a secondary opp head pipe in ODM combine
configuration. Before the recent change, we will overwrite this wrong
assignement in asic independent layer again. This covers up the issue.
With the recent change, we will no longer cover up this in upper layer
and therefore causes wrong tg and opp assignement to the secondary
dpp pipe connected to a secondary opp head.
[how]
Always assign tg and opp from its own opp head instead of otg master.
Reviewed-by: Martin Leung
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index dfecb9602f49..efa600e46194 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2151,28 +2151,27 @@ struct pipe_ctx *dcn20_acquire_free_pipe_for_layer(
const struct dc_state *cur_ctx,
struct dc_state *new_ctx,
const struct resource_pool *pool,
- const struct pipe_ctx *opp_head_pipe)
+ const struct pipe_ctx *opp_head)
{
struct resource_context *res_ctx = _ctx->res_ctx;
- struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx,
opp_head_pipe->stream);
- struct pipe_ctx *idle_pipe = find_free_secondary_pipe_legacy(res_ctx,
pool, head_pipe);
+ struct pipe_ctx *otg_master =
resource_get_head_pipe_for_stream(res_ctx, opp_head->stream);
+ struct pipe_ctx *sec_dpp_pipe =
find_free_secondary_pipe_legacy(res_ctx, pool, otg_master);
- if (!head_pipe)
- ASSERT(0);
+ ASSERT(otg_master);
- if (!idle_pipe)
+ if (!sec_dpp_pipe)
return NULL;
- idle_pipe->stream = head_pipe->stream;
- idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
- idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
+ sec_dpp_pipe->stream = opp_head->stream;
+ sec_dpp_pipe->stream_res.tg = opp_head->stream_res.tg;
+ sec_dpp_pipe->stream_res.opp = opp_head->stream_res.opp;
- idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
- idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
- idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
- idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
+ sec_dpp_pipe->plane_res.hubp = pool->hubps[sec_dpp_pipe->pipe_idx];
+ sec_dpp_pipe->plane_res.ipp = pool->ipps[sec_dpp_pipe->pipe_idx];
+ sec_dpp_pipe->plane_res.dpp = pool->dpps[sec_dpp_pipe->pipe_idx];
+ sec_dpp_pipe->plane_res.mpcc_inst =
pool->dpps[sec_dpp_pipe->pipe_idx]->inst;
- return idle_pipe;
+ return sec_dpp_pipe;
}
bool dcn20_get_dcc_compression_cap(const struct dc *dc,
--
2.41.0
[PATCH 06/15] drm/amd/display: PMFW to wait for DMCUB ack for FPO cases
From: Alvin Lee
[Description]
We want PMFW to wait for DMCUB to ACK the MCLK end message
for FPO cases as well.
Reviewed-by: Samson Tam
Acked-by: Stylon Wang
Signed-off-by: Alvin Lee
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 5 +
.../amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c | 7 +++
.../amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h | 1 +
3 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 2f65591d2f62..c224c6eb879d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -555,6 +555,11 @@ static void dcn32_update_clocks(struct clk_mgr
*clk_mgr_base,
}
}
+ if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
+ dcn32_smu_wait_for_dmub_ack_mclk(clk_mgr, true);
+ else
+ dcn32_smu_wait_for_dmub_ack_mclk(clk_mgr, false);
+
/* Always update saved value, even if new value not set due to
P-State switching unsupported. Also check safe_to_lower for FCLK */
if (safe_to_lower &&
(clk_mgr_base->clks.fclk_p_state_change_support !=
clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
update_fclk = true;
diff --git
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
index fb524fe4ab26..700ce42036d7 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
@@ -139,3 +139,10 @@ unsigned int dcn32_smu_set_hard_min_by_freq(struct
clk_mgr_internal *clk_mgr, ui
return response;
}
+
+void dcn32_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool
enable)
+{
+ smu_print("PMFW to wait for DMCUB ack for MCLK : %d\n", enable);
+
+ dcn32_smu_send_msg_with_param(clk_mgr, 0x14, enable ? 1 : 0, NULL);
+}
diff --git
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
index a68038a41972..a34c258c19dc 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h
@@ -43,5 +43,6 @@ void dcn32_smu_set_pme_workaround(struct clk_mgr_internal
*clk_mgr);
void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr,
unsigned int num_ways);
void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr,
uint32_t clk, uint16_t freq_mhz);
+void dcn32_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool
enable);
#endif /* __DCN32_CLK_MGR_SMU_MSG_H_ */
--
2.41.0
[PATCH 05/15] drm/amd/display: Enable subvp high refresh up to 175hz
From: Alvin Lee
[Description]
Expand the SubVP policy to include up to 175hz displays
for better power saving on more display configs.
Reviewed-by: Chaitanya Dhere
Acked-by: Stylon Wang
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 2 +-
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index ea3d4b328e8e..cd5243c59d2d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -322,7 +322,7 @@ static bool is_subvp_high_refresh_candidate(struct
dc_stream_state *stream)
* remain in HW cursor mode if there's no cursor update which will
* then cause corruption.
*/
- if ((refresh_rate >= 120 && refresh_rate <= 165 &&
+ if ((refresh_rate >= 120 && refresh_rate <= 175 &&
stream->timing.v_addressable >= 1440 &&
stream->timing.v_addressable <= 2160) &&
(dc->current_state->stream_count > 1 ||
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 0f882b879b0d..6d60ae0133ee 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -37,7 +37,7 @@
static const struct subvp_high_refresh_list subvp_high_refresh_list = {
.min_refresh = 120,
- .max_refresh = 165,
+ .max_refresh = 175,
.res = {
{.width = 3840, .height = 2160, },
{.width = 3440, .height = 1440, },
@@ -1064,7 +1064,8 @@ static bool subvp_subvp_admissable(struct dc *dc,
}
if (subvp_count == 2 && ((min_refresh < 120 && max_refresh < 120) ||
- (min_refresh >= 120 && max_refresh <= 165)))
+ (min_refresh >= subvp_high_refresh_list.min_refresh &&
+ max_refresh <=
subvp_high_refresh_list.max_refresh)))
result = true;
return result;
--
2.41.0
[PATCH 04/15] drm/amd/display: Gamut remap only changes missed
From: Krunoslav Kovac
[WHY]
If surface format is dynamically changed within app without changing
timing / whole plane, we don't reprogram gamut remap matrix.
Issue example:
Linear FP16 scRGB going to PQ+BT.2020 monitor.
Remap = scRGB->BT.2020
App switches swapchain format to 10-bit PQ+BT.2020.
SW calculates correctly that new Remap = bypass (in=-out=BT.2020).
But update not applied in HW.
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
Signed-off-by: Krunoslav Kovac
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index b196b7ff1a0d..65fa9e21ad9c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1638,6 +1638,7 @@ static void dcn20_update_dchubp_dpp(
if (pipe_ctx->update_flags.bits.enable ||
pipe_ctx->update_flags.bits.opp_changed
|| pipe_ctx->update_flags.bits.plane_changed
|| pipe_ctx->stream->update_flags.bits.gamut_remap
+ || plane_state->update_flags.bits.gamut_remap_change
|| pipe_ctx->stream->update_flags.bits.out_csc) {
/* dpp/cm gamut remap*/
dc->hwss.program_gamut_remap(pipe_ctx);
--
2.41.0
[PATCH 03/15] drm/amd/display: Enable 8k60hz mode on single display
From: Nicholas Susanto
[Why]
8k60hz compliace test failing because we restrict it single memory
channels. Workaround by not restricting it on single displays.
[How]
Adding an additional check to DCN314 to restrict 8k60hz mode if it has
more than 1 display connected.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Stylon Wang
Signed-off-by: Nicholas Susanto
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 5e9459e26469..4e09ba4f2806 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -1689,7 +1689,9 @@ static bool
filter_modes_for_single_channel_workaround(struct dc *dc,
struct dc_state *context)
{
// Filter 2K@240Hz+8K@24fps above combination timing if memory only has
single dimm LPDDR
- if (dc->clk_mgr->bw_params->vram_type == 34 &&
dc->clk_mgr->bw_params->num_channels < 2) {
+ if (dc->clk_mgr->bw_params->vram_type == 34 &&
+ dc->clk_mgr->bw_params->num_channels < 2 &&
+ context->stream_count > 1) {
int total_phy_pix_clk = 0;
for (int i = 0; i < context->stream_count; i++)
--
2.41.0
[PATCH 01/15] drm/amd/display: Support Compliance Test Pattern Generation with DP2 Retimer
From: Michael Strauss
[WHY]
Certain retimer requires workarounds in order to correctly output test patterns.
[HOW]
Add vendor-specific aux sequences to program retimer's TX and pattern generator
when specific compliance test patterns are requested by sink.
Note: SQ128 w/a in DPMF mode only works in one flip orientation currently
Reviewed-by: Hansen Dsouza
Reviewed-by: Wenjing Liu
Acked-by: Stylon Wang
Signed-off-by: Michael Strauss
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 8 +-
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/inc/link.h | 4 +
drivers/gpu/drm/amd/display/dc/link/Makefile | 3 +-
.../display/dc/link/accessories/link_dp_cts.c | 3 +
.../amd/display/dc/link/hwss/link_hwss_dio.c | 2 +-
.../amd/display/dc/link/hwss/link_hwss_dio.h | 3 +
.../hwss/link_hwss_dio_fixed_vs_pe_retimer.c | 200
.../hwss/link_hwss_dio_fixed_vs_pe_retimer.h | 37 +++
.../display/dc/link/hwss/link_hwss_hpo_dp.c | 22 +-
.../display/dc/link/hwss/link_hwss_hpo_dp.h | 28 +-
.../link_hwss_hpo_fixed_vs_pe_retimer_dp.c| 229 +
.../link_hwss_hpo_fixed_vs_pe_retimer_dp.h| 33 ++
.../drm/amd/display/dc/link/link_factory.c| 1 +
.../amd/display/dc/link/protocols/link_ddc.c | 82 +
.../amd/display/dc/link/protocols/link_ddc.h | 14 +
.../link_dp_training_fixed_vs_pe_retimer.c| 305 +-
17 files changed, 738 insertions(+), 237 deletions(-)
create mode 100644
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c
create mode 100644
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h
create mode 100644
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c
create mode 100644
drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 7561fe748c72..853e5b99dd62 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -45,6 +45,8 @@
#include "link/hwss/link_hwss_dio.h"
#include "link/hwss/link_hwss_dpia.h"
#include "link/hwss/link_hwss_hpo_dp.h"
+#include "link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h"
+#include "link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h"
#if defined(CONFIG_DRM_AMD_DC_SI)
#include "dce60/dce60_resource.h"
@@ -4198,11 +4200,13 @@ const struct link_hwss *get_link_hwss(const struct
dc_link *link,
* with an hpo encoder. Or we can return a very dummy one that
doesn't
* do work for all functions
*/
- return get_hpo_dp_link_hwss();
+ return (requires_fixed_vs_pe_retimer_hpo_link_hwss(link) ?
+ get_hpo_fixed_vs_pe_retimer_dp_link_hwss() :
get_hpo_dp_link_hwss());
else if (can_use_dpia_link_hwss(link, link_res))
return get_dpia_link_hwss();
else if (can_use_dio_link_hwss(link, link_res))
- return get_dio_link_hwss();
+ return (requires_fixed_vs_pe_retimer_dio_link_hwss(link)) ?
+ get_dio_fixed_vs_pe_retimer_link_hwss() :
get_dio_link_hwss();
else
return get_virtual_link_hwss();
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 44b6172da170..fc9756ea7cc5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1498,6 +1498,7 @@ struct dc_link {
enum engine_id eng_id;
bool test_pattern_enabled;
+ enum dp_test_pattern current_test_pattern;
union compliance_test_state compliance_test_state;
void *priv;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link.h
b/drivers/gpu/drm/amd/display/dc/inc/link.h
index c07096e59201..e3e8c76c17cf 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link.h
@@ -179,6 +179,10 @@ struct link_service {
int (*aux_transfer_raw)(struct ddc_service *ddc,
struct aux_payload *payload,
enum aux_return_code_type *operation_result);
+ bool (*configure_fixed_vs_pe_retimer)(
+ struct ddc_service *ddc,
+ const uint8_t *data,
+ uint32_t len);
bool (*aux_transfer_with_retries_no_mutex)(struct ddc_service *ddc,
struct aux_payload *payload);
bool (*is_in_aux_transaction_mode)(struct ddc_service *ddc);
diff --git a/drivers/gpu/drm/amd/display/dc/link/Makefile
b/drivers/gpu/drm/amd/display/dc/link/Makefile
index a52b56e2859e..6af8a97d4a77 100644
--- a/drivers/gpu/drm/amd/display/dc/link/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/link/Makefile
@@ -4
[PATCH 02/15] drm/amd/display: disable clock gating logic reversed bug fix
From: Muhammad Ahmed [Why] disable clock gating logic reversed bug fix Reviewed-by: Charlene Liu Acked-by: Stylon Wang Signed-off-by: Muhammad Ahmed --- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c index 7445ed27852a..1f4e0b6261ad 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c @@ -1018,8 +1018,8 @@ void hubbub31_init(struct hubbub *hubbub) /*done in hwseq*/ /*REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);*/ REG_UPDATE_2(DCHUBBUB_CLOCK_CNTL, - DISPCLK_R_DCHUBBUB_GATE_DIS, 0, - DCFCLK_R_DCHUBBUB_GATE_DIS, 0); + DISPCLK_R_DCHUBBUB_GATE_DIS, 1, + DCFCLK_R_DCHUBBUB_GATE_DIS, 1); } /* diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c index a18b9c0c5709..8bfef6d095b2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c @@ -955,8 +955,8 @@ void hubbub32_init(struct hubbub *hubbub) /*REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);*/ REG_UPDATE_2(DCHUBBUB_CLOCK_CNTL, - DISPCLK_R_DCHUBBUB_GATE_DIS, 0, - DCFCLK_R_DCHUBBUB_GATE_DIS, 0); + DISPCLK_R_DCHUBBUB_GATE_DIS, 1, + DCFCLK_R_DCHUBBUB_GATE_DIS, 1); } /* ignore the "df_pre_cstate_req" from the SDP port control. -- 2.41.0
[PATCH 00/15] DC Patches August 11, 2023
This DC patchset brings improvements in multiple areas. In summary, we have: - Improve power saving feature - Clean up for code clarity - Fix MST issues in system resume - Fix crashing bug - Fix pipe allocation for older ASIC - Fix for gamut remap - Fix 8K 60Hz display in test cases - Fix bug in clock gating - Improve DP2 compliance Cc: Daniel Wheeler Alvin Lee (2): drm/amd/display: Enable subvp high refresh up to 175hz drm/amd/display: PMFW to wait for DMCUB ack for FPO cases Anthony Koo (1): drm/amd/display: [FW Promotion] Release 0.0.179.0 Aric Cyr (1): drm/amd/display: Promote DAL to 3.2.247 Aurabindo Pillai (3): drm/amd/display: Add some missing register definitions drm/amd/display: enable low power mode for VGA memory drm/amd/display: Remove freesync video mode amdgpu parameter Charlene Liu (1): drm/amd/display: avoid crash and add z8_marks related in dml Krunoslav Kovac (1): drm/amd/display: Gamut remap only changes missed Michael Strauss (1): drm/amd/display: Support Compliance Test Pattern Generation with DP2 Retimer Muhammad Ahmed (1): drm/amd/display: disable clock gating logic reversed bug fix Nicholas Susanto (1): drm/amd/display: Enable 8k60hz mode on single display Wayne Lin (1): drm/amd/display: Adjust the resume flow Wenjing Liu (2): drm/amd/display: fix incorrect stream_res allocation for older ASIC drm/amd/display: implement pipe type definition and adding accessors drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 27 -- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 185 +++ .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 5 + .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c | 7 + .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h | 1 + drivers/gpu/drm/amd/display/dc/core/dc.c | 41 +-- .../gpu/drm/amd/display/dc/core/dc_resource.c | 194 ++- .../gpu/drm/amd/display/dc/core/dc_stream.c | 2 +- drivers/gpu/drm/amd/display/dc/dc.h | 3 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 22 +- .../gpu/drm/amd/display/dc/dce/dce_hwseq.h| 69 ++-- .../amd/display/dc/dce100/dce100_resource.c | 2 +- .../amd/display/dc/dce110/dce110_resource.c | 2 +- .../amd/display/dc/dce112/dce112_resource.c | 4 +- .../drm/amd/display/dc/dcn10/dcn10_resource.c | 6 +- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 1 + .../drm/amd/display/dc/dcn20/dcn20_resource.c | 41 ++- .../amd/display/dc/dcn201/dcn201_resource.c | 4 +- .../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 5 + .../drm/amd/display/dc/dcn30/dcn30_resource.c | 3 +- .../drm/amd/display/dc/dcn31/dcn31_hubbub.c | 4 +- .../drm/amd/display/dc/dcn31/dcn31_resource.c | 4 +- .../amd/display/dc/dcn314/dcn314_resource.c | 8 +- .../drm/amd/display/dc/dcn32/dcn32_hubbub.c | 4 +- .../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 12 +- .../drm/amd/display/dc/dcn32/dcn32_resource.c | 4 +- .../display/dc/dcn32/dcn32_resource_helpers.c | 12 +- .../drm/amd/display/dc/dml/calcs/dce_calcs.c | 2 +- .../drm/amd/display/dc/dml/calcs/dcn_calcs.c | 2 +- .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 2 +- .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 16 +- .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 2 + drivers/gpu/drm/amd/display/dc/inc/link.h | 4 + drivers/gpu/drm/amd/display/dc/inc/resource.h | 220 - drivers/gpu/drm/amd/display/dc/link/Makefile | 3 +- .../display/dc/link/accessories/link_dp_cts.c | 6 +- .../amd/display/dc/link/hwss/link_hwss_dio.c | 2 +- .../amd/display/dc/link/hwss/link_hwss_dio.h | 3 + .../hwss/link_hwss_dio_fixed_vs_pe_retimer.c | 200 .../hwss/link_hwss_dio_fixed_vs_pe_retimer.h | 37 +++ .../display/dc/link/hwss/link_hwss_hpo_dp.c | 22 +- .../display/dc/link/hwss/link_hwss_hpo_dp.h | 28 +- .../link_hwss_hpo_fixed_vs_pe_retimer_dp.c| 229 + .../link_hwss_hpo_fixed_vs_pe_retimer_dp.h| 33 ++ .../gpu/drm/amd/display/dc/link/link_dpms.c | 7 +- .../drm/amd/display/dc/link/link_factory.c| 1 + .../amd/display/dc/link/protocols/link_ddc.c | 82 + .../amd/display/dc/link/protocols/link_ddc.h | 14 + .../link_dp_training_fixed_vs_pe_retimer.c| 305 +- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 + .../include/asic_reg/dcn/dcn_3_0_0_offset.h | 5 + .../include/asic_reg/dcn/dcn_3_0_0_sh_mask.h | 5 + .../include/asic_reg/dcn/dcn_3_0_2_offset.h | 4 + .../include/asic_reg/dcn/dcn_3_0_2_sh_mask.h | 5 +- 55 files changed, 1356 insertions(+), 560 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c create mode 100644 drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h create mode 100644 drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c create mode 100644
[PATCH] drm/amdgpu: Add dcdebugmask option to enable DPIA trace
[Why & How]
It's useful to be able to enable DPIA trace with dcdebugmask
option, especially to debug DPIA issues involved in transition
of system power states.
This patch adds an option to amdgpu.dcdebugmask to be picked up
by amdgpu DM to enable DPIA trace.
Signed-off-by: Stylon Wang
---
drivers/gpu/drm/amd/include/amd_shared.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
b/drivers/gpu/drm/amd/include/amd_shared.h
index f175e65b853a..abe829bbd54a 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -250,6 +250,7 @@ enum DC_DEBUG_MASK {
DC_DISABLE_PSR = 0x10,
DC_FORCE_SUBVP_MCLK_SWITCH = 0x20,
DC_DISABLE_MPO = 0x40,
+ DC_ENABLE_DPIA_TRACE = 0x80,
};
enum amd_dpm_forced_level;
--
2.40.1
[PATCH 20/20] drm/amd/display: 3.2.239
From: Aric Cyr This version brings along following fixes: - Improvement on eDP - PSR bug fixes - SubVP bug fixes - Improvements on pipe handling to address potential issues - Freesync bug fix - DPIA bug fix - Fix multi-display issues Acked-by: Stylon Wang Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index a239dcd8e9fb..26d05e225088 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.238" +#define DC_VER "3.2.239" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.40.1
[PATCH 19/20] drm/amd/display: fix pixel rate update sequence
From: Dmytro Laktyushkin
The k1/k2 pixel rate dividers in dccg should only be updated on stream enable
and do not actually depend on whether odm combine is active.
This removes an on flip update of these and fixes the calculate function
to ignore odm status for dp steams.
Acked-by: Stylon Wang
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Ariel Bernstein
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c| 11 ---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c | 9 ++---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h | 2 +-
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c| 8 ++--
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h| 2 +-
.../gpu/drm/amd/display/dc/inc/hw_sequencer_private.h | 2 +-
6 files changed, 7 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 20f668d28364..eaf9e9ccad2a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1741,17 +1741,6 @@ static void dcn20_program_pipe(
if (hws->funcs.setup_vupdate_interrupt)
hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
-
- if (hws->funcs.calculate_dccg_k1_k2_values &&
dc->res_pool->dccg->funcs->set_pixel_rate_div) {
- unsigned int k1_div, k2_div;
-
- hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx,
_div, _div);
-
- dc->res_pool->dccg->funcs->set_pixel_rate_div(
- dc->res_pool->dccg,
- pipe_ctx->stream_res.tg->inst,
- k1_div, k2_div);
- }
}
if (pipe_ctx->update_flags.bits.odm)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
index 4d2820ffe468..32a1c3105089 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
@@ -337,14 +337,13 @@ void dcn314_enable_power_gating_plane(struct dce_hwseq
*hws, bool enable)
REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
}
-unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx,
unsigned int *k1_div, unsigned int *k2_div)
+void dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned
int *k1_div, unsigned int *k2_div)
{
struct dc_stream_state *stream = pipe_ctx->stream;
- unsigned int odm_combine_factor = 0;
bool two_pix_per_container = false;
two_pix_per_container =
optc2_is_two_pixels_per_containter(>timing);
- odm_combine_factor = get_odm_config(pipe_ctx, NULL);
+ get_odm_config(pipe_ctx, NULL);
if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
*k1_div = PIXEL_RATE_DIV_BY_1;
@@ -362,15 +361,11 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct
pipe_ctx *pipe_ctx, unsig
} else {
*k1_div = PIXEL_RATE_DIV_BY_1;
*k2_div = PIXEL_RATE_DIV_BY_4;
- if (odm_combine_factor == 2)
- *k2_div = PIXEL_RATE_DIV_BY_2;
}
}
if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
ASSERT(false);
-
- return odm_combine_factor;
}
void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
index eafcc4ea6d24..3841da67a737 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
@@ -37,7 +37,7 @@ void dcn314_dsc_pg_control(struct dce_hwseq *hws, unsigned
int dsc_inst, bool po
void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
-unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx,
unsigned int *k1_div, unsigned int *k2_div);
+void dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned
int *k1_div, unsigned int *k2_div);
void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index e5bd76c6b1d3..c586468872e2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -1141,10 +1141,9 @@ void dcn32_update_odm(struct dc *dc, struct dc_state
*context, struct pipe_ctx *
}
}
-unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx,
unsigned int *k1_div, unsigned int *k2_div)
+void dcn32_calculate_dccg_k1_k2_values(stru
[PATCH 18/20] Revert "drm/amd/display: reallocate DET for dual displays with high pixel rate ratio"
From: Samson Tam
Revert commit b957de69c4c8 ("drm/amd/display: reallocate DET for dual displays
with high pixel rate ratio")
[Why]
Previously had modified DET allocation algorithm to allocate less DET
segments for lower pixel rate display and more DET segments for higher
pixel rate display. But noticed it is causing underflow when higher
pixel rate display is not displaying at higher mode
[How]
Roll back change
Acked-by: Stylon Wang
Signed-off-by: Samson Tam
Reviewed-by: Alvin Lee
---
.../display/dc/dcn32/dcn32_resource_helpers.c | 51 ++-
1 file changed, 5 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index 7eec39576e2c..4882c3684b82 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -255,8 +255,6 @@ bool dcn32_is_psr_capable(struct pipe_ctx *pipe)
return psr_capable;
}
-#define DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER 7
-
/**
* dcn32_determine_det_override(): Determine DET allocation for each pipe
*
@@ -267,6 +265,7 @@ bool dcn32_is_psr_capable(struct pipe_ctx *pipe)
* If there is a plane that's driven by more than 1 pipe (i.e. pipe split),
then the
* number of DET for that given plane will be split among the pipes driving
that plane.
*
+ *
* High level algorithm:
* 1. Split total DET among number of streams
* 2. For each stream, split DET among the planes
@@ -274,21 +273,9 @@ bool dcn32_is_psr_capable(struct pipe_ctx *pipe)
*among those pipes.
* 4. Assign the DET override to the DML pipes.
*
- * Special cases:
- *
- * For two displays that have a large difference in pixel rate, we may
experience
- * underflow on the larger display when we divide the DET equally. For this,
we
- * will implement a modified algorithm to assign more DET to larger display.
- *
- * 1. Calculate difference in pixel rates ( multiplier ) between two displays
- * 2. If the multiplier exceeds DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER, then
- *implement the modified DET override algorithm.
- * 3. Assign smaller DET size for lower pixel display and higher DET size for
- *higher pixel display
- *
- * @dc: Current DC state
- * @context: New DC state to be programmed
- * @pipes: Array of DML pipes
+ * @param [in]: dc: Current DC state
+ * @param [in]: context: New DC state to be programmed
+ * @param [in]: pipes: Array of DML pipes
*
* Return: void
*/
@@ -303,31 +290,10 @@ void dcn32_determine_det_override(struct dc *dc,
struct dc_plane_state *current_plane = NULL;
uint8_t stream_count = 0;
- int phy_pix_clk_mult, lower_mode_stream_index;
- int phy_pix_clk[MAX_PIPES] = {0};
- bool use_new_det_override_algorithm = false;
-
for (i = 0; i < context->stream_count; i++) {
/* Don't count SubVP streams for DET allocation */
- if (context->streams[i]->mall_stream_config.type !=
SUBVP_PHANTOM) {
- phy_pix_clk[i] = context->streams[i]->phy_pix_clk;
+ if (context->streams[i]->mall_stream_config.type !=
SUBVP_PHANTOM)
stream_count++;
- }
- }
-
- /* Check for special case with two displays, one with much higher pixel
rate */
- if (stream_count == 2) {
- ASSERT((phy_pix_clk[0] > 0) && (phy_pix_clk[1] > 0));
- if (phy_pix_clk[0] < phy_pix_clk[1]) {
- lower_mode_stream_index = 0;
- phy_pix_clk_mult = phy_pix_clk[1] / phy_pix_clk[0];
- } else {
- lower_mode_stream_index = 1;
- phy_pix_clk_mult = phy_pix_clk[0] / phy_pix_clk[1];
- }
-
- if (phy_pix_clk_mult >= DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER)
- use_new_det_override_algorithm = true;
}
if (stream_count > 0) {
@@ -336,13 +302,6 @@ void dcn32_determine_det_override(struct dc *dc,
if (context->streams[i]->mall_stream_config.type ==
SUBVP_PHANTOM)
continue;
- if (use_new_det_override_algorithm) {
- if (i == lower_mode_stream_index)
- stream_segments = 4;
- else
- stream_segments = 14;
- }
-
if (context->stream_status[i].plane_count > 0)
plane_segments = stream_segments /
context->stream_status[i].plane_count;
else
--
2.40.1
[PATCH 17/20] drm/amd/display: limit DPIA link rate to HBR3
From: Peichen Huang [Why] DPIA doesn't support UHBR, driver should not enable UHBR for dp tunneling [How] limit DPIA link rate to HBR3 Cc: Mario Limonciello Cc: Alex Deucher Cc: sta...@vger.kernel.org Acked-by: Stylon Wang Signed-off-by: Peichen Huang Reviewed-by: Mustapha Ghaddar --- drivers/gpu/drm/amd/display/dc/link/link_detection.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index 17904de4f155..8041b8369e45 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -984,6 +984,11 @@ static bool detect_link_and_local_sink(struct dc_link *link, (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)) converter_disable_audio = true; + + /* limited link rate to HBR3 for DPIA until we implement USB4 V2 */ + if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && + link->reported_link_cap.link_rate > LINK_RATE_HIGH3) + link->reported_link_cap.link_rate = LINK_RATE_HIGH3; break; } -- 2.40.1
[PATCH 16/20] drm/amd/display: Include CSC updates in new fast update path
From: Alvin Lee
[Description]
- Missed color / CSC updates in fast update path
which caused Custom Color to break.
- Add color / CSC updates to new fast update path
to fix custom color
Acked-by: Stylon Wang
Signed-off-by: Alvin Lee
Reviewed-by: Jun Lei
---
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 70 +++
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 32 +
2 files changed, 102 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 182c42c63bc5..d7d00fefaab9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -562,6 +562,29 @@ void hwss_build_fast_sequence(struct dc *dc,
(*num_steps)++;
}
+ if
(current_mpc_pipe->stream->update_flags.bits.out_csc) {
+
block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc =
dc->res_pool->mpc;
+
block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id =
current_mpc_pipe->plane_res.hubp->inst;
+
block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.power_on = true;
+ block_sequence[*num_steps].func =
MPC_POWER_ON_MPC_MEM_PWR;
+ (*num_steps)++;
+
+ if
(current_mpc_pipe->stream->csc_color_matrix.enable_adjustment == true) {
+
block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc;
+
block_sequence[*num_steps].params.set_output_csc_params.opp_id =
current_mpc_pipe->stream_res.opp->inst;
+
block_sequence[*num_steps].params.set_output_csc_params.regval =
current_mpc_pipe->stream->csc_color_matrix.matrix;
+
block_sequence[*num_steps].params.set_output_csc_params.ocsc_mode =
MPC_OUTPUT_CSC_COEF_A;
+ block_sequence[*num_steps].func =
MPC_SET_OUTPUT_CSC;
+ (*num_steps)++;
+ } else {
+
block_sequence[*num_steps].params.set_ocsc_default_params.mpc =
dc->res_pool->mpc;
+
block_sequence[*num_steps].params.set_ocsc_default_params.opp_id =
current_mpc_pipe->stream_res.opp->inst;
+
block_sequence[*num_steps].params.set_ocsc_default_params.color_space =
current_mpc_pipe->stream->output_color_space;
+
block_sequence[*num_steps].params.set_ocsc_default_params.ocsc_mode =
MPC_OUTPUT_CSC_COEF_A;
+ block_sequence[*num_steps].func =
MPC_SET_OCSC_DEFAULT;
+ (*num_steps)++;
+ }
+ }
current_mpc_pipe = current_mpc_pipe->bottom_pipe;
}
current_pipe = current_pipe->next_odm_pipe;
@@ -661,6 +684,15 @@ void hwss_execute_sequence(struct dc *dc,
params->update_visual_confirm_params.pipe_ctx,
params->update_visual_confirm_params.mpcc_id);
break;
+ case MPC_POWER_ON_MPC_MEM_PWR:
+ hwss_power_on_mpc_mem_pwr(params);
+ break;
+ case MPC_SET_OUTPUT_CSC:
+ hwss_set_output_csc(params);
+ break;
+ case MPC_SET_OCSC_DEFAULT:
+ hwss_set_ocsc_default(params);
+ break;
case DMUB_SEND_DMCUB_CMD:
hwss_send_dmcub_cmd(params);
break;
@@ -718,6 +750,44 @@ void hwss_program_bias_and_scale(union
block_sequence_params *params)
dpp->funcs->dpp_program_bias_and_scale(dpp, _params);
}
+void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params)
+{
+ struct mpc *mpc = params->power_on_mpc_mem_pwr_params.mpc;
+ int mpcc_id = params->power_on_mpc_mem_pwr_params.mpcc_id;
+ bool power_on = params->power_on_mpc_mem_pwr_params.power_on;
+
+ if (mpc->funcs->power_on_mpc_mem_pwr)
+ mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on);
+}
+
+void hwss_set_output_csc(union block_sequence_params *params)
+{
+ struct mpc *mpc = params->set_output_csc_params.mpc;
+ int opp_id = params->set_output_csc_params.opp_id;
+ const uint16_t *matrix = params->set_output_csc_params.regval;
+
[PATCH 15/20] drm/amd/display: Limit Minimum FreeSync Refresh Rate
From: Austin Zheng
Why:
Some EDIDs report a minimum refresh rate lower than what HW can support
How:
Add a check to calculate minimum supported refresh rate with current timing
and use that as the minimum if a lower one is passed in
Acked-by: Stylon Wang
Signed-off-by: Austin Zheng
Reviewed-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 1 +
.../gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 1 +
.../gpu/drm/amd/display/dc/dcn303/dcn303_resource.c | 1 +
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 1 +
.../gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 1 +
.../gpu/drm/amd/display/modules/freesync/freesync.c | 11 +--
7 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 5c906b007e4d..a239dcd8e9fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -266,6 +266,7 @@ struct dc_caps {
uint16_t subvp_pstate_allow_width_us;
uint16_t subvp_vertical_int_margin_us;
bool seamless_odm;
+ uint32_t max_v_total;
uint8_t subvp_drr_vblank_start_margin_us;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index f4ee4b3df596..1a0284a068b2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2328,6 +2328,7 @@ static bool dcn30_resource_construct(
dc->caps.color.mpc.ocsc = 1;
dc->caps.dp_hdmi21_pcon_support = true;
+ dc->caps.max_v_total = (1 << 15) - 1;
/* read VBIOS LTTPR caps */
{
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index 93f42132c900..7dc065ea247a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -1227,6 +1227,7 @@ static bool dcn302_resource_construct(
dc->caps.force_dp_tps4_for_cp2520 = true;
dc->caps.extended_aux_timeout_support = true;
dc->caps.dmcub_support = true;
+ dc->caps.max_v_total = (1 << 15) - 1;
/* Color pipeline capabilities */
dc->caps.color.dpp.dcn_arch = 1;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
index f35514188a5c..6d9761395288 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
@@ -1152,6 +1152,7 @@ static bool dcn303_resource_construct(
dc->caps.force_dp_tps4_for_cp2520 = true;
dc->caps.extended_aux_timeout_support = true;
dc->caps.dmcub_support = true;
+ dc->caps.max_v_total = (1 << 15) - 1;
/* Color pipeline capabilities */
dc->caps.color.dpp.dcn_arch = 1;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 8c9e15952a49..19f134caa8ad 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -2175,6 +2175,7 @@ static bool dcn32_resource_construct(
dc->caps.extended_aux_timeout_support = true;
dc->caps.dmcub_support = true;
dc->caps.seamless_odm = true;
+ dc->caps.max_v_total = (1 << 15) - 1;
/* Color pipeline capabilities */
dc->caps.color.dpp.dcn_arch = 1;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index ee07ee340171..ea204742ad35 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -1718,6 +1718,7 @@ static bool dcn321_resource_construct(
dc->caps.edp_dsc_support = true;
dc->caps.extended_aux_timeout_support = true;
dc->caps.dmcub_support = true;
+ dc->caps.max_v_total = (1 << 15) - 1;
/* Color pipeline capabilities */
dc->caps.color.dpp.dcn_arch = 1;
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 5798c0eafa1f..dbd60811f95d 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2016 Advanced Micro Devices, Inc.
+ * Copyright 2016-2023 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -989,6 +989,7 @@ void mod_freesync_build
[PATCH 14/20] drm/amd/display: Bug fix in dcn315_populate_dml_pipes_from_context
From: Artem Grishin
[Why]
When iterating over all pipes in the loop, the CRB allocation algorithm
may potentially skip some of the pipes. Previously, the current pipe
index didn't get updated in this case, causing incorrect outcome.
[How]
Increment the pipe index when skipping over a pipe in the loop.
Acked-by: Stylon Wang
Signed-off-by: Artem Grishin
Reviewed-by: Dmytro Laktyushkin
---
drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
index 0cc853964781..f1153941907e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -1742,6 +1742,7 @@ static int dcn315_populate_dml_pipes_from_context(
/* Do not use asymetric crb if not enough for pstate
support */
if (remaining_det_segs < 0) {
pipes[pipe_cnt].pipe.src.det_size_override = 0;
+ pipe_cnt++;
continue;
}
--
2.40.1
[PATCH 13/20] Revert "drm/amd/display: Move DCN314 DOMAIN power control to DMCUB"
From: Daniel Miess
Revert commit 6c2c207e4a24 ("drm/amd/display: Move DCN314 DOMAIN power control
to DMCUB")
[Why]
Controling hubp power gating using the DMCUB isn't stable so we
are reverting this change to move control back into the driver
Acked-by: Stylon Wang
Signed-off-by: Daniel Miess
Reviewed-by: Nicholas Kazlauskas
---
.../drm/amd/display/dc/dcn314/dcn314_hwseq.c | 21 ---
.../drm/amd/display/dc/dcn314/dcn314_hwseq.h | 2 --
.../drm/amd/display/dc/dcn314/dcn314_init.c | 2 +-
3 files changed, 1 insertion(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
index ce7e6f20b31f..4d2820ffe468 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
@@ -429,27 +429,6 @@ void dcn314_dpp_root_clock_control(struct dce_hwseq *hws,
unsigned int dpp_inst,
hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);
}
-void dcn314_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst,
bool power_on)
-{
- struct dc_context *ctx = hws->ctx;
- union dmub_rb_cmd cmd;
-
- if (hws->ctx->dc->debug.disable_hubp_power_gate)
- return;
-
- PERF_TRACE();
-
- memset(, 0, sizeof(cmd));
- cmd.domain_control.header.type = DMUB_CMD__VBIOS;
- cmd.domain_control.header.sub_type = DMUB_CMD__VBIOS_DOMAIN_CONTROL;
- cmd.domain_control.header.payload_bytes =
sizeof(cmd.domain_control.data);
- cmd.domain_control.data.inst = hubp_inst;
- cmd.domain_control.data.power_gate = !power_on;
-
- dm_execute_dmub_cmd(ctx, , DM_DMUB_WAIT_TYPE_WAIT);
-
- PERF_TRACE();
-}
static void apply_symclk_on_tx_off_wa(struct dc_link *link)
{
/* There are use cases where SYMCLK is referenced by OTG. For instance
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
index 559d71002e8a..eafcc4ea6d24 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
@@ -43,8 +43,6 @@ void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct
dc_state *context);
-void dcn314_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst,
bool power_on);
-
void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int
dpp_inst, bool clock_on);
void dcn314_disable_link_output(struct dc_link *link, const struct
link_resource *link_res, enum signal_type signal);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
index 86d6a514dec0..ca8fe55c33b8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
@@ -139,7 +139,7 @@ static const struct hwseq_private_funcs
dcn314_private_funcs = {
.plane_atomic_power_down = dcn10_plane_atomic_power_down,
.enable_power_gating_plane = dcn314_enable_power_gating_plane,
.dpp_root_clock_control = dcn314_dpp_root_clock_control,
- .hubp_pg_control = dcn314_hubp_pg_control,
+ .hubp_pg_control = dcn31_hubp_pg_control,
.program_all_writeback_pipes_in_tree =
dcn30_program_all_writeback_pipes_in_tree,
.update_odm = dcn314_update_odm,
.dsc_pg_control = dcn314_dsc_pg_control,
--
2.40.1
[PATCH 12/20] drm/amd/display: Block SubVP + DRR if the DRR is PSR capable
From: Alvin Lee
[Description]
PSR implementation in FW has inline polling which can poll for up
to 1ms. This will interfere with SubVP because SubVP is timing
sensitive and can't tolerate up to 1ms worth of delay before
handling vertical or VLINE interrupts. Therefore block SubVP + DRR
cases if DRR is PSR capable
Acked-by: Stylon Wang
Signed-off-by: Alvin Lee
Reviewed-by: Saaem Rizvi
---
.../drm/amd/display/dc/dcn32/dcn32_resource_helpers.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index 578070e7d44b..7eec39576e2c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -672,6 +672,7 @@ bool dcn32_check_native_scaling_for_res(struct pipe_ctx
*pipe, unsigned int widt
* - Config must have 2 displays (i.e., 2 non-phantom master pipes)
* - One display is SubVP
* - Other display must have Freesync enabled
+ * - The potential DRR display must not be PSR capable
*
* @return: True if admissible, false otherwise
*
@@ -684,6 +685,7 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct
dc_state *context)
uint8_t subvp_count = 0;
uint8_t non_subvp_pipes = 0;
bool drr_pipe_found = false;
+ bool drr_psr_capable = false;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
@@ -696,6 +698,7 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct
dc_state *context)
subvp_count++;
if (pipe->stream->mall_stream_config.type ==
SUBVP_NONE) {
non_subvp_pipes++;
+ drr_psr_capable = (drr_psr_capable ||
dcn32_is_psr_capable(pipe));
if (pipe->stream->ignore_msa_timing_param &&
(pipe->stream->allow_freesync
|| pipe->stream->vrr_active_variable)) {
drr_pipe_found = true;
@@ -704,7 +707,7 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct
dc_state *context)
}
}
- if (subvp_count == 1 && non_subvp_pipes == 1 && drr_pipe_found)
+ if (subvp_count == 1 && non_subvp_pipes == 1 && drr_pipe_found &&
!drr_psr_capable)
result = true;
return result;
@@ -722,6 +725,7 @@ bool dcn32_subvp_drr_admissable(struct dc *dc, struct
dc_state *context)
* - One display is SubVP
* - Other display must not have Freesync capability
* - DML must have output DRAM clock change support as SubVP + Vblank
+ * - The potential vblank display must not be PSR capable
*
* @return: True if admissible, false otherwise
*
@@ -735,6 +739,7 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct
dc_state *context, int
uint8_t non_subvp_pipes = 0;
bool drr_pipe_found = false;
struct vba_vars_st *vba = >bw_ctx.dml.vba;
+ bool vblank_psr_capable = false;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
@@ -747,6 +752,7 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct
dc_state *context, int
subvp_count++;
if (pipe->stream->mall_stream_config.type ==
SUBVP_NONE) {
non_subvp_pipes++;
+ vblank_psr_capable = (vblank_psr_capable ||
dcn32_is_psr_capable(pipe));
if (pipe->stream->ignore_msa_timing_param &&
(pipe->stream->allow_freesync
|| pipe->stream->vrr_active_variable)) {
drr_pipe_found = true;
@@ -755,7 +761,7 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct
dc_state *context, int
}
}
- if (subvp_count == 1 && non_subvp_pipes == 1 && !drr_pipe_found &&
+ if (subvp_count == 1 && non_subvp_pipes == 1 && !drr_pipe_found &&
!vblank_psr_capable &&
vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] ==
dm_dram_clock_change_vblank_w_mall_sub_vp)
result = true;
--
2.40.1
[PATCH 11/20] drm/amd/display: Do not disable phantom pipes in driver
From: Saaem Rizvi
[Why and How]
We should not disable phantom pipes in this sequence, as this should be
controlled by FW. Furthermore, the previous programming sequence would
have enabled the phantom pipe in driver as well, causing corruption.
This change should avoid this from occuring.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Stylon Wang
Signed-off-by: Saaem Rizvi
Reviewed-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 00f32ffe0079..e5bd76c6b1d3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -1211,7 +1211,8 @@ void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws,
struct dc *dc, struct dc_
if (pipe->top_pipe || pipe->prev_odm_pipe)
continue;
- if (pipe->stream && (pipe->stream->dpms_off ||
dc_is_virtual_signal(pipe->stream->signal))) {
+ if (pipe->stream && (pipe->stream->dpms_off ||
dc_is_virtual_signal(pipe->stream->signal))
+ && pipe->stream->mall_stream_config.type !=
SUBVP_PHANTOM) {
pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
reset_sync_context_for_pipe(dc, context, i);
otg_disabled[i] = true;
--
2.40.1
[PATCH 10/20] drm/amd/display: Re-enable SubVP high refresh
From: Alvin Lee
Re-enable SubVP high refresh now that it is fixed
for displays with high refresh rates.
Acked-by: Stylon Wang
Signed-off-by: Alvin Lee
Reviewed-by: Saaem Rizvi
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index 2e6b39fe2613..8c9e15952a49 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -728,7 +728,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.fpo_vactive_margin_us = 2000, // 2000us
.disable_fpo_vactive = false,
.disable_boot_optimizations = false,
- .disable_subvp_high_refresh = true,
+ .disable_subvp_high_refresh = false,
.disable_dp_plus_plus_wa = true,
.fpo_vactive_min_active_margin_us = 200,
.fpo_vactive_max_blank_us = 1000,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index bbcd3579fea6..ee07ee340171 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -727,7 +727,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.fpo_vactive_margin_us = 2000, // 2000us
.disable_fpo_vactive = false,
.disable_boot_optimizations = false,
- .disable_subvp_high_refresh = true,
+ .disable_subvp_high_refresh = false,
.fpo_vactive_min_active_margin_us = 200,
.fpo_vactive_max_blank_us = 1000,
};
--
2.40.1
[PATCH 09/20] drm/amd/display: Re-enable DPP/HUBP Power Gating
From: Daniel Miess
[Why & How]
Bugs preventing DPP/HUBP power gating have been addressed
so this should be reenabled on dcn314 for sufficient
hardware rev versions
Acked-by: Stylon Wang
Signed-off-by: Daniel Miess
Reviewed-by: Nicholas Kazlauskas
---
.../gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 7957ad4d6a34..a840b008d660 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -874,8 +874,8 @@ static const struct dc_debug_options debug_defaults_drv = {
.force_abm_enable = false,
.timing_trace = false,
.clock_trace = true,
- .disable_dpp_power_gate = true,
- .disable_hubp_power_gate = true,
+ .disable_dpp_power_gate = false,
+ .disable_hubp_power_gate = false,
.disable_pplib_clock_request = false,
.pipe_split_policy = MPC_SPLIT_DYNAMIC,
.force_single_disp_pipe_split = false,
@@ -1883,6 +1883,13 @@ static bool dcn314_resource_construct(
/* Use pipe context based otg sync logic */
dc->config.use_pipe_ctx_sync_logic = true;
+ /* Disable pipe power gating when unsupported */
+ if (ctx->asic_id.hw_internal_rev == 0x01 ||
+ ctx->asic_id.hw_internal_rev == 0x80) {
+ dc->debug.disable_dpp_power_gate = true;
+ dc->debug.disable_hubp_power_gate = true;
+ }
+
/* read VBIOS LTTPR caps */
{
if (ctx->dc_bios->funcs->get_lttpr_caps) {
--
2.40.1
[PATCH 08/20] drm/amd/display: SubVP high refresh only if all displays >= 120hz
From: Alvin Lee
[Description]
- SubVP high refresh should only be enabled if all displays
are >= 120hz. We do not want to accidentally enables configs
such as 60hz[SubVP] + 120hz[SubVP]
- Ensure that the SubVP config generation code does not produce
configs such as 60hz[SubVP] + 120hz[SubVP]
- Also add admissibility checks to ensure these configs do not
pass as valid configs
Acked-by: Stylon Wang
Signed-off-by: Alvin Lee
Reviewed-by: Dillon Varone
---
.../drm/amd/display/dc/dcn32/dcn32_resource.h | 4 +
.../display/dc/dcn32/dcn32_resource_helpers.c | 101 ++
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 178 +++---
3 files changed, 217 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
index 2f34f01b3ea1..81e443170829 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
@@ -169,6 +169,10 @@ double dcn32_determine_max_vratio_prefetch(struct dc *dc,
struct dc_state *conte
bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int
width, unsigned int height);
+bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context);
+
+bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context,
int vlevel);
+
/* definitions for run time init of reg offsets */
/* CLK SRC */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
index 1d13fd797212..578070e7d44b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
@@ -660,3 +660,104 @@ bool dcn32_check_native_scaling_for_res(struct pipe_ctx
*pipe, unsigned int widt
return is_native_scaling;
}
+
+/**
+ *
+ * dcn32_subvp_drr_admissable: Determine if SubVP + DRR config is admissible
+ *
+ * @param [in]: dc: Current DC state
+ * @param [in]: context: New DC state to be programmed
+ *
+ * SubVP + DRR is admissible under the following conditions:
+ * - Config must have 2 displays (i.e., 2 non-phantom master pipes)
+ * - One display is SubVP
+ * - Other display must have Freesync enabled
+ *
+ * @return: True if admissible, false otherwise
+ *
+ *
+ */
+bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)
+{
+ bool result = false;
+ uint32_t i;
+ uint8_t subvp_count = 0;
+ uint8_t non_subvp_pipes = 0;
+ bool drr_pipe_found = false;
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
+
+ if (!pipe->stream)
+ continue;
+
+ if (pipe->plane_state && !pipe->top_pipe) {
+ if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
+ subvp_count++;
+ if (pipe->stream->mall_stream_config.type ==
SUBVP_NONE) {
+ non_subvp_pipes++;
+ if (pipe->stream->ignore_msa_timing_param &&
+ (pipe->stream->allow_freesync
|| pipe->stream->vrr_active_variable)) {
+ drr_pipe_found = true;
+ }
+ }
+ }
+ }
+
+ if (subvp_count == 1 && non_subvp_pipes == 1 && drr_pipe_found)
+ result = true;
+
+ return result;
+}
+
+/**
+ *
+ * dcn32_subvp_vblank_admissable: Determine if SubVP + Vblank config is
admissible
+ *
+ * @param [in]: dc: Current DC state
+ * @param [in]: context: New DC state to be programmed
+ *
+ * SubVP + Vblank is admissible under the following conditions:
+ * - Config must have 2 displays (i.e., 2 non-phantom master pipes)
+ * - One display is SubVP
+ * - Other display must not have Freesync capability
+ * - DML must have output DRAM clock change support as SubVP + Vblank
+ *
+ * @return: True if admissible, false otherwise
+ *
+ *
+ */
+bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context,
int vlevel)
+{
+ bool result = false;
+ uint32_t i;
+ uint8_t subvp_count = 0;
+ uint8_t non_subvp_pipes = 0;
+ bool drr_pipe_found = false;
+ struct vba_vars_st *vba = >bw_ctx.dml.vba;
+
+ for (i = 0; i < dc->res_pool->pipe_count
[PATCH 07/20] drm/amd/display: Fix disbling PSR slow response issue
From: Tom Chung
[Why]
dmub_psr_get_state() return an invalid PSR state while disable
the PSR because convert_psr_state() doesn't recognize the state
that return from DMCUB.
[How]
Add a PSR state to make the dmub_psr_get_state() return a
correct PSR state.
Acked-by: Stylon Wang
Signed-off-by: Tom Chung
Reviewed-by: Wayne Lin
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 1 +
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 6b4731b5e975..0ce7728a5a4b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -597,6 +597,7 @@ enum dc_psr_state {
PSR_STATE4b_FULL_FRAME,
PSR_STATE4c_FULL_FRAME,
PSR_STATE4_FULL_FRAME_POWERUP,
+ PSR_STATE4_FULL_FRAME_HW_LOCK,
PSR_STATE5,
PSR_STATE5a,
PSR_STATE5b,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 4000a834592c..0f24b6fbd220 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -87,6 +87,8 @@ static enum dc_psr_state convert_psr_state(uint32_t raw_state)
state = PSR_STATE4c_FULL_FRAME;
else if (raw_state == 0x4E)
state = PSR_STATE4_FULL_FRAME_POWERUP;
+ else if (raw_state == 0x4F)
+ state = PSR_STATE4_FULL_FRAME_HW_LOCK;
else if (raw_state == 0x60)
state = PSR_STATE_HWLOCK_MGR;
else if (raw_state == 0x61)
--
2.40.1
[PATCH 06/20] drm/amd/display: fix the system hang while disable PSR
From: Tom Chung [Why] When the PSR enabled. If you try to adjust the timing parameters, it may cause system hang. Because the timing mismatch with the DMCUB settings. [How] Disable the PSR before adjusting timing parameters. Cc: Mario Limonciello Cc: Alex Deucher Cc: sta...@vger.kernel.org Acked-by: Stylon Wang Signed-off-by: Tom Chung Reviewed-by: Wayne Lin --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9279c1d474f2..cfd1a67cf7d0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8244,6 +8244,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) bundle->stream_update.abm_level = _state->abm_level; + mutex_lock(>dc_lock); + if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && + acrtc_state->stream->link->psr_settings.psr_allow_active) + amdgpu_dm_psr_disable(acrtc_state->stream); + mutex_unlock(>dc_lock); + /* * If FreeSync state on the stream has changed then we need to * re-adjust the min/max bounds now that DC doesn't handle this @@ -8257,10 +8263,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, spin_unlock_irqrestore(>dev->event_lock, flags); } mutex_lock(>dc_lock); - if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && - acrtc_state->stream->link->psr_settings.psr_allow_active) - amdgpu_dm_psr_disable(acrtc_state->stream); - update_planes_and_stream_adapter(dm->dc, acrtc_state->update_type, planes_count, -- 2.40.1
[PATCH 05/20] drm/amd/display: Promote DAL to 3.2.238
From: Aric Cyr Acked-by: Stylon Wang Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7cf3e9510043..5c906b007e4d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,7 +45,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.237" +#define DC_VER "3.2.238" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.40.1
[PATCH 04/20] drm/amd/display: Add Error Code for Dml Validation Failure
From: Fangzhi Zuo
Any invalid mode from hw perspective should be given corresponding
error code, otherwise it leads to confusing warning message
"[drm] Mode Validation Warning: Validation OK failed validation."
Acked-by: Stylon Wang
Signed-off-by: Fangzhi Zuo
Reviewed-by: Dmytro Laktyushkin
---
.../dc/dml/dcn314/display_mode_vba_314.c | 59 +++
.../amd/display/dc/dml/display_mode_enums.h | 8 +++
2 files changed, 67 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
index 1532a7e0ed6c..9010c47476e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -5557,6 +5557,65 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_
}
}
}
+ for (i = v->soc.num_states; i >= 0; i--) {
+ for (j = 0; j < 2; j++) {
+ enum dm_validation_status status = DML_VALIDATION_OK;
+
+ if (!v->ScaleRatioAndTapsSupport) {
+ status = DML_FAIL_SCALE_RATIO_TAP;
+ } else if (!v->SourceFormatPixelAndScanSupport) {
+ status = DML_FAIL_SOURCE_PIXEL_FORMAT;
+ } else if (!v->ViewportSizeSupport[i][j]) {
+ status = DML_FAIL_VIEWPORT_SIZE;
+ } else if (P2IWith420) {
+ status = DML_FAIL_P2I_WITH_420;
+ } else if (DSCOnlyIfNecessaryWithBPP) {
+ status =
DML_FAIL_DSC_ONLY_IF_NECESSARY_WITH_BPP;
+ } else if (DSC422NativeNotSupported) {
+ status = DML_FAIL_NOT_DSC422_NATIVE;
+ } else if (!v->ODMCombine4To1SupportCheckOK[i]) {
+ status = DML_FAIL_ODM_COMBINE4TO1;
+ } else if (v->NotEnoughDSCUnits[i]) {
+ status = DML_FAIL_NOT_ENOUGH_DSC;
+ } else if (!v->ROBSupport[i][j]) {
+ status = DML_FAIL_REORDERING_BUFFER;
+ } else if (!v->DISPCLK_DPPCLK_Support[i][j]) {
+ status = DML_FAIL_DISPCLK_DPPCLK;
+ } else if (!v->TotalAvailablePipesSupport[i][j]) {
+ status = DML_FAIL_TOTAL_AVAILABLE_PIPES;
+ } else if (!EnoughWritebackUnits) {
+ status = DML_FAIL_ENOUGH_WRITEBACK_UNITS;
+ } else if (!v->WritebackLatencySupport) {
+ status = DML_FAIL_WRITEBACK_LATENCY;
+ } else if (!v->WritebackScaleRatioAndTapsSupport) {
+ status = DML_FAIL_WRITEBACK_SCALE_RATIO_TAP;
+ } else if (!v->CursorSupport) {
+ status = DML_FAIL_CURSOR_SUPPORT;
+ } else if (!v->PitchSupport) {
+ status = DML_FAIL_PITCH_SUPPORT;
+ } else if (ViewportExceedsSurface) {
+ status = DML_FAIL_VIEWPORT_EXCEEDS_SURFACE;
+ } else if (!v->PrefetchSupported[i][j]) {
+ status = DML_FAIL_PREFETCH_SUPPORT;
+ } else if (!v->DynamicMetadataSupported[i][j]) {
+ status = DML_FAIL_DYNAMIC_METADATA;
+ } else if
(!v->TotalVerticalActiveBandwidthSupport[i][j]) {
+ status = DML_FAIL_TOTAL_V_ACTIVE_BW;
+ } else if (!v->VRatioInPrefetchSupported[i][j]) {
+ status = DML_FAIL_V_RATIO_PREFETCH;
+ } else if (!v->PTEBufferSizeNotExceeded[i][j]) {
+ status = DML_FAIL_PTE_BUFFER_SIZE;
+ } else if (v->NonsupportedDSCInputBPC) {
+ status = DML_FAIL_DSC_INPUT_BPC;
+ } else if ((v->HostVMEnable
+ &&
!v->ImmediateFlipSupportedForState[i][j])) {
+ status = DML_FAIL_HOST_VM_IMMEDIATE_FLIP;
+ } else if (FMTBufferExceeded) {
+ status = DML_FAIL_FMT_BUFFER_EXCEEDED;
+ }
+ mode_lib->vba.ValidationStatus[i] = status;
+ }
+ }
{
unsigned int MaximumMPCCombine = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
b/drivers/gpu/drm/amd/display/dc/dml/display_mod
[PATCH 03/20] drm/amd/display: Add DP2 Metrics
From: Austin Zheng
Why:
Log DP2 data to be used for debugging purposes
How:
Check the reported link rate of the DP connection and
translate it to the DP version.
Acked-by: Stylon Wang
Signed-off-by: Austin Zheng
Reviewed-by: Martin Leung
---
drivers/gpu/drm/amd/display/dc/dc.h | 6 --
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 360dd83b1a7a..7cf3e9510043 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2012-14 Advanced Micro Devices, Inc.
+ * Copyright 2012-2023 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -60,7 +60,9 @@ struct dc_versions {
};
enum dp_protocol_version {
- DP_VERSION_1_4,
+ DP_VERSION_1_4 = 0,
+ DP_VERSION_2_1,
+ DP_VERSION_UNKNOWN,
};
enum dc_plane_type {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index 4a7f6497dc5a..55139d7bf422 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -61,7 +61,7 @@ enum dc_link_rate {
*/
LINK_RATE_UHBR10 = 1000,// UHBR10 - 10.0 Gbps/Lane
LINK_RATE_UHBR13_5 = 1350, // UHBR13.5 - 13.5 Gbps/Lane
- LINK_RATE_UHBR20 = 2000,// UHBR10 - 20.0 Gbps/Lane
+ LINK_RATE_UHBR20 = 2000,// UHBR20 - 20.0 Gbps/Lane
};
enum dc_link_spread {
--
2.40.1
[PATCH 02/20] drm/amd/display: add debugfs for allow_edp_hotplug_detection
From: Hersen Wu
[Why] within dc_link_detect, edp edid is read only for the first time
and saved. edid will not be read after the first time read. to run edp
edid read test, need read edp edid for each dc_link_detect. dc->config
flag allow_edp_hotplug_detection could be used for edp edid test.
[How] add debugfs for dc->config.allow_edp_hotplug_detection
Acked-by: Stylon Wang
Signed-off-by: Hersen Wu
Reviewed-by: Aurabindo Pillai
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 32 +++
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 82234397dd44..2ff88562c27a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -2705,6 +2705,32 @@ static int psr_read_residency(void *data, u64 *val)
return 0;
}
+/* read allow_edp_hotplug_detection */
+static int allow_edp_hotplug_detection_get(void *data, u64 *val)
+{
+ struct amdgpu_dm_connector *aconnector = data;
+ struct drm_connector *connector = >base;
+ struct drm_device *dev = connector->dev;
+ struct amdgpu_device *adev = drm_to_adev(dev);
+
+ *val = adev->dm.dc->config.allow_edp_hotplug_detection;
+
+ return 0;
+}
+
+/* set allow_edp_hotplug_detection */
+static int allow_edp_hotplug_detection_set(void *data, u64 val)
+{
+ struct amdgpu_dm_connector *aconnector = data;
+ struct drm_connector *connector = >base;
+ struct drm_device *dev = connector->dev;
+ struct amdgpu_device *adev = drm_to_adev(dev);
+
+ adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val;
+
+ return 0;
+}
+
/*
* Set dmcub trace event IRQ enable or disable.
* Usage to enable dmcub trace event IRQ: echo 1 >
/sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
@@ -2743,6 +2769,10 @@ DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL,
"%llu\n");
DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL,
"%llu\n");
+DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops,
+ allow_edp_hotplug_detection_get,
+ allow_edp_hotplug_detection_set, "%llu\n");
+
DEFINE_SHOW_ATTRIBUTE(current_backlight);
DEFINE_SHOW_ATTRIBUTE(target_backlight);
@@ -2913,6 +2943,8 @@ void connector_debugfs_init(struct amdgpu_dm_connector
*connector)
_backlight_fops);
debugfs_create_file("ilr_setting", 0644, dir, connector,
_ilr_debugfs_fops);
+ debugfs_create_file("allow_edp_hotplug_detection", 0644, dir,
connector,
+ _edp_hotplug_detection_fops);
}
for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
--
2.40.1
[PATCH 01/20] drm/amd/display: edp do not add non-edid timings
From: Hersen Wu
[Why] most edp support only timings from edid. applying
non-edid timings, especially those timings out of edp
bandwidth, may damage edp.
[How] do not add non-edid timings for edp.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Stylon Wang
Signed-off-by: Hersen Wu
Reviewed-by: Roman Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 59badb125736..9279c1d474f2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7236,7 +7236,13 @@ static int amdgpu_dm_connector_get_modes(struct
drm_connector *connector)
drm_add_modes_noedid(connector, 1920, 1080);
} else {
amdgpu_dm_connector_ddc_get_modes(connector, edid);
- amdgpu_dm_connector_add_common_modes(encoder, connector);
+ /* most eDP supports only timings from its edid,
+* usually only detailed timings are available
+* from eDP edid. timings which are not from edid
+* may damage eDP
+*/
+ if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
+ amdgpu_dm_connector_add_common_modes(encoder,
connector);
amdgpu_dm_connector_add_freesync_modes(connector, edid);
}
amdgpu_dm_fbc_init(connector);
--
2.40.1
[PATCH 00/20] DC Patches June 9, 2023
This DC patchset brings improvements in multiple areas. In summary, we highlight: - Improvement on eDP - PSR bug fixes - SubVP bug fixes - Improvements on pipe handling to address potential issues - Freesync bug fix - DPIA bug fix - Fix multi-display issues Cc: Daniel Wheeler Alvin Lee (4): drm/amd/display: SubVP high refresh only if all displays >= 120hz drm/amd/display: Re-enable SubVP high refresh drm/amd/display: Block SubVP + DRR if the DRR is PSR capable drm/amd/display: Include CSC updates in new fast update path Aric Cyr (2): drm/amd/display: Promote DAL to 3.2.238 drm/amd/display: 3.2.239 Artem Grishin (1): drm/amd/display: Bug fix in dcn315_populate_dml_pipes_from_context Austin Zheng (2): drm/amd/display: Add DP2 Metrics drm/amd/display: Limit Minimum FreeSync Refresh Rate Daniel Miess (2): drm/amd/display: Re-enable DPP/HUBP Power Gating Revert "drm/amd/display: Move DCN314 DOMAIN power control to DMCUB" Dmytro Laktyushkin (1): drm/amd/display: fix pixel rate update sequence Fangzhi Zuo (1): drm/amd/display: Add Error Code for Dml Validation Failure Hersen Wu (2): drm/amd/display: edp do not add non-edid timings drm/amd/display: add debugfs for allow_edp_hotplug_detection Peichen Huang (1): drm/amd/display: limit DPIA link rate to HBR3 Saaem Rizvi (1): drm/amd/display: Do not disable phantom pipes in driver Samson Tam (1): Revert "drm/amd/display: reallocate DET for dual displays with high pixel rate ratio" Tom Chung (2): drm/amd/display: fix the system hang while disable PSR drm/amd/display: Fix disbling PSR slow response issue .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 +- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 32 .../drm/amd/display/dc/core/dc_hw_sequencer.c | 70 +++ drivers/gpu/drm/amd/display/dc/dc.h | 9 +- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 2 +- drivers/gpu/drm/amd/display/dc/dc_types.h | 1 + drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 2 + .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 11 -- .../drm/amd/display/dc/dcn30/dcn30_resource.c | 1 + .../amd/display/dc/dcn302/dcn302_resource.c | 1 + .../amd/display/dc/dcn303/dcn303_resource.c | 1 + .../drm/amd/display/dc/dcn314/dcn314_hwseq.c | 30 +-- .../drm/amd/display/dc/dcn314/dcn314_hwseq.h | 4 +- .../drm/amd/display/dc/dcn314/dcn314_init.c | 2 +- .../amd/display/dc/dcn314/dcn314_resource.c | 11 +- .../amd/display/dc/dcn315/dcn315_resource.c | 1 + .../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 11 +- .../drm/amd/display/dc/dcn32/dcn32_hwseq.h| 2 +- .../drm/amd/display/dc/dcn32/dcn32_resource.c | 3 +- .../drm/amd/display/dc/dcn32/dcn32_resource.h | 4 + .../display/dc/dcn32/dcn32_resource_helpers.c | 158 +++- .../amd/display/dc/dcn321/dcn321_resource.c | 3 +- .../dc/dml/dcn314/display_mode_vba_314.c | 59 ++ .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 178 +++--- .../amd/display/dc/dml/display_mode_enums.h | 8 + .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 32 .../amd/display/dc/inc/hw_sequencer_private.h | 2 +- .../drm/amd/display/dc/link/link_detection.c | 5 + .../amd/display/modules/freesync/freesync.c | 11 +- 29 files changed, 493 insertions(+), 179 deletions(-) -- 2.40.1
[PATCH 13/14] drm/amd/display: Skip DPP DTO update if root clock is gated
From: Nicholas Kazlauskas
[Why]
Hardware implements root clock gating by utilizing the DPP DTO registers
with a special case of DTO enabled, phase = 0, modulo = 1. This
conflicts with our policy to always update the DPPDTO for cases where
it's expected to be disabled.
The pipes unexpectedly enter a higher power state than expected because
of this programming flow.
[How]
Guard the upper layers of HWSS against this hardware quirk with
programming the register with an internal state flag in DCCG.
While technically acting as global state for the DCCG, HWSS shouldn't be
expected to understand the hardware quirk for having DTO disabled
causing more power than DTO enabled with this specific setting.
This also prevents sequencing errors from occuring in the future if
we have to program DPP DTO in multiple locations.
Acked-by: Stylon Wang
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Jun Lei
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 8
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c | 5 +
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h| 1 +
3 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 4c2fdfea162f..65c1d754e2d6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -47,6 +47,14 @@ void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst,
int req_dppclk)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+ if (dccg->dpp_clock_gated[dpp_inst]) {
+ /*
+* Do not update the DPPCLK DTO if the clock is stopped.
+* It is treated the same as if the pipe itself were in PG.
+*/
+ return;
+ }
+
if (dccg->ref_dppclk && req_dppclk) {
int ref_dppclk = dccg->ref_dppclk;
int modulo, phase;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
index e0e7d32bb1a0..cf23d7bc560a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
@@ -332,6 +332,9 @@ static void dccg314_dpp_root_clock_control(
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+ if (dccg->dpp_clock_gated[dpp_inst] == clock_on)
+ return;
+
if (clock_on) {
/* turn off the DTO and leave phase/modulo at max */
REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 0);
@@ -345,6 +348,8 @@ static void dccg314_dpp_root_clock_control(
DPPCLK0_DTO_PHASE, 0,
DPPCLK0_DTO_MODULO, 1);
}
+
+ dccg->dpp_clock_gated[dpp_inst] = !clock_on;
}
static const struct dccg_funcs dccg314_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index 0b700b3d7d97..8dc804bbe98b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -68,6 +68,7 @@ struct dccg {
const struct dccg_funcs *funcs;
int pipe_dppclk_khz[MAX_PIPES];
int ref_dppclk;
+ bool dpp_clock_gated[MAX_PIPES];
//int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */
//int audio_dtbclk_khz;/* TODO needs to be removed */
//int ref_dtbclk_khz;/* TODO needs to be removed */
--
2.40.1
[PATCH 14/14] drm/amd/display: Enable dcn314 DPP RCO
From: Daniel Miess
[Why and How]
Add back debug bits enabling RCO for dcn314 as underflow
associated with this change has been resolved
Acked-by: Stylon Wang
Signed-off-by: Daniel Miess
Reviewed-by: Jun Lei
---
.../drm/amd/display/dc/dcn314/dcn314_resource.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 3592efcc7fae..fbed835ffb54 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -921,6 +921,22 @@ static const struct dc_debug_options debug_defaults_drv = {
.afmt = true,
}
},
+
+ .root_clock_optimization = {
+ .bits = {
+ .dpp = true,
+ .dsc = false,
+ .hdmistream = false,
+ .hdmichar = false,
+ .dpstream = false,
+ .symclk32_se = false,
+ .symclk32_le = false,
+ .symclk_fe = false,
+ .physymclk = false,
+ .dpiasymclk = false,
+ }
+ },
+
.seamless_boot_odm_combine = true
};
--
2.40.1
[PATCH 12/14] drm/amd/display: Filter out AC mode frequencies on DC mode systems
From: Austin Zheng
Why:
Limit maximum clock speeds to DC mode limits for DC mode systems
How:
Store DC mode limits when individual clocks are initialized and
cap the values when building the clock table
Acked-by: Stylon Wang
Signed-off-by: Austin Zheng
Reviewed-by: Alvin Lee
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 13 +-
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 140 -
.../amd/display/dc/dml/dcn321/dcn321_fpu.c| 144 +-
.../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 1 +
5 files changed, 216 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 20bff6a346ba..96fa68f166e0 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -182,23 +182,32 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
dcn32_init_single_clock(clk_mgr, PPCLK_DCFCLK,
_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
_entries_per_clk->num_dcfclk_levels);
+ clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz =
dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
/* SOCCLK */
dcn32_init_single_clock(clk_mgr, PPCLK_SOCCLK,
_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
_entries_per_clk->num_socclk_levels);
+ clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz =
dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);
/* DTBCLK */
- if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch)
+ if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch) {
dcn32_init_single_clock(clk_mgr, PPCLK_DTBCLK,
_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
_entries_per_clk->num_dtbclk_levels);
+ clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz =
+ dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr,
PPCLK_DTBCLK);
+ }
/* DISPCLK */
dcn32_init_single_clock(clk_mgr, PPCLK_DISPCLK,
_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
_entries_per_clk->num_dispclk_levels);
num_levels = num_entries_per_clk->num_dispclk_levels;
+ clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz =
dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);
+ //HW recommends limit of 1950 MHz in display clock for all DCN3.2.x
+ if (clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz > 1950)
+ clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 1950;
if (num_entries_per_clk->num_dcfclk_levels &&
num_entries_per_clk->num_dtbclk_levels &&
@@ -817,6 +826,7 @@ static void dcn32_get_memclk_states_from_smu(struct clk_mgr
*clk_mgr_base)
dcn32_init_single_clock(clk_mgr, PPCLK_UCLK,
_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
_entries_per_clk->num_memclk_levels);
+ clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz =
dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
/* memclk must have at least one level */
num_entries_per_clk->num_memclk_levels =
num_entries_per_clk->num_memclk_levels ? num_entries_per_clk->num_memclk_levels
: 1;
@@ -824,6 +834,7 @@ static void dcn32_get_memclk_states_from_smu(struct clk_mgr
*clk_mgr_base)
dcn32_init_single_clock(clk_mgr, PPCLK_FCLK,
_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
_entries_per_clk->num_fclk_levels);
+ clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz =
dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);
if (num_entries_per_clk->num_memclk_levels >=
num_entries_per_clk->num_fclk_levels) {
num_levels = num_entries_per_clk->num_memclk_levels;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 7ded574f84ff..360dd83b1a7a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -897,6 +897,7 @@ struct dc_debug_options {
uint32_t fpo_vactive_min_active_margin_us;
uint32_t fpo_vactive_max_blank_us;
bool enable_legacy_fast_update;
+ bool disable_dc_mode_overwrite;
};
struct gpu_info_soc_bounding_box_v1_0;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index b17f30afa18
[PATCH 11/14] drm/amd/display: DSC Programming Deltas
From: Sridevi
[Why]
Programming register delta for DSC sub-block
[How]
Change DSC, resource files for programming register delta.
Acked-by: Stylon Wang
Signed-off-by: Sridevi
Reviewed-by: Chris Park
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 29 +++
.../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h | 28 ++
2 files changed, 38 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index 5bd698cd6d20..5eebe7f03ddc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -30,22 +30,13 @@
#include "dsc/dscc_types.h"
#include "dsc/rc_calc.h"
-static void dsc_log_pps(struct display_stream_compressor *dsc, struct
drm_dsc_config *pps);
-static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct
dsc_reg_values *dsc_reg_vals,
- struct dsc_optc_config *dsc_optc_cfg);
-static void dsc_init_reg_values(struct dsc_reg_values *reg_vals);
-static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals,
const struct dsc_parameters *dsc_params);
static void dsc_write_to_registers(struct display_stream_compressor *dsc,
const struct dsc_reg_values *reg_vals);
-static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum
dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple);
-static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum
dc_color_depth);
/* Object I/F functions */
-static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int
pixel_clock_100Hz);
static void dsc2_read_state(struct display_stream_compressor *dsc, struct
dcn_dsc_state *s);
static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const
struct dsc_config *dsc_cfg);
static void dsc2_set_config(struct display_stream_compressor *dsc, const
struct dsc_config *dsc_cfg,
struct dsc_optc_config *dsc_optc_cfg);
-static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const
struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps);
static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe);
static void dsc2_disable(struct display_stream_compressor *dsc);
static void dsc2_disconnect(struct display_stream_compressor *dsc);
@@ -108,7 +99,7 @@ void dsc2_construct(struct dcn20_dsc *dsc,
/* This returns the capabilities for a single DSC encoder engine. Number of
slices and total throughput
* can be doubled, tripled etc. by using additional DSC engines.
*/
-static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int
pixel_clock_100Hz)
+void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int
pixel_clock_100Hz)
{
dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in
reverse order and we kept it */
@@ -184,7 +175,7 @@ static bool dsc2_validate_stream(struct
display_stream_compressor *dsc, const st
}
-static void dsc_config_log(struct display_stream_compressor *dsc, const struct
dsc_config *config)
+void dsc_config_log(struct display_stream_compressor *dsc, const struct
dsc_config *config)
{
DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h);
DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v);
@@ -211,7 +202,7 @@ static void dsc2_set_config(struct
display_stream_compressor *dsc, const struct
}
-static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const
struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps)
+bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct
dsc_config *dsc_cfg, uint8_t *dsc_packed_pps)
{
bool is_config_ok;
struct dsc_reg_values dsc_reg_vals;
@@ -291,7 +282,7 @@ static void dsc2_disconnect(struct
display_stream_compressor *dsc)
}
/* This module's internal functions */
-static void dsc_log_pps(struct display_stream_compressor *dsc, struct
drm_dsc_config *pps)
+void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config
*pps)
{
int i;
int bits_per_pixel = pps->bits_per_pixel;
@@ -345,7 +336,7 @@ static void dsc_log_pps(struct display_stream_compressor
*dsc, struct drm_dsc_co
}
}
-static void dsc_override_rc_params(struct rc_params *rc, const struct
dc_dsc_rc_params_override *override)
+void dsc_override_rc_params(struct rc_params *rc, const struct
dc_dsc_rc_params_override *override)
{
uint8_t i;
@@ -372,7 +363,7 @@ static void dsc_override_rc_params(struct rc_params *rc,
const struct dc_dsc_rc_
rc->flatness_det_thresh = override->flatness_det_thresh;
}
-static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct
dsc_reg_values *dsc_reg_vals,
+bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct
dsc_reg_values *dsc_reg_vals,
struct dsc_optc_config
[PATCH 10/14] Revert "drm/amd/display: cache trace buffer size"
From: Leo Ma
Revert commit 9caa026e4e65 ("drm/amd/display: cache trace buffer size")
to fix regression found in tests.
Acked-by: Stylon Wang
Signed-off-by: Leo Ma
Reviewed-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 -
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 2 --
2 files changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index e210cb082ebd..7c9a2b34bd05 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -428,7 +428,6 @@ struct dmub_srv {
enum dmub_asic asic;
void *user_ctx;
uint32_t fw_version;
- uint32_t trace_buffer_size;
bool is_virtual;
struct dmub_fb scratch_mem_fb;
volatile const struct dmub_fw_state *fw_state;
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 8b9af18e84fe..9e9a6a44a7ac 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -427,8 +427,6 @@ dmub_srv_calc_region_info(struct dmub_srv *dmub,
dmub->fw_version = fw_info->fw_version;
}
- dmub->trace_buffer_size = trace_buffer_size;
-
trace_buff->base = dmub_align(mail->top, 256);
trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64);
--
2.40.1
[PATCH 09/14] drm/amd/display: add NULL pointer check
From: Charlene Liu [why] check dmub_Srv exist or not before accessing dmub. Acked-by: Stylon Wang Signed-off-by: Charlene Liu Reviewed-by: Zhan Liu --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 0d3ec50b1385..41b4c360c5b2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -276,7 +276,7 @@ static void program_cursor_attributes( } dc->hwss.set_cursor_attribute(pipe_ctx); - + if (dc->ctx->dmub_srv) dc_send_update_cursor_info_to_dmu(pipe_ctx, i); if (dc->hwss.set_cursor_sdr_white_level) dc->hwss.set_cursor_sdr_white_level(pipe_ctx); @@ -396,7 +396,7 @@ static void program_cursor_position( } dc->hwss.set_cursor_position(pipe_ctx); - + if (dc->ctx->dmub_srv) dc_send_update_cursor_info_to_dmu(pipe_ctx, i); } -- 2.40.1
[PATCH 08/14] drm/amd/display: Enable Freesync Video Mode by default
From: Aurabindo Pillai
Revert commit d54f66bc9c37 ("Revert drm/amd/display: Enable Freesync Video Mode
by default")
Enables freesync video by default, since the hang and corruption issue
on eDP panels are now fixed.
Acked-by: Stylon Wang
Signed-off-by: Aurabindo Pillai
Reviewed-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index a69f4a39d92a..52dca7898390 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6017,8 +6017,7 @@ create_stream_for_sink(struct amdgpu_dm_connector
*aconnector,
*/
DRM_DEBUG_DRIVER("No preferred mode found\n");
} else {
- recalculate_timing = amdgpu_freesync_vid_mode &&
-is_freesync_video_mode(, aconnector);
+ recalculate_timing = is_freesync_video_mode(, aconnector);
if (recalculate_timing) {
freesync_mode =
get_highest_refresh_rate_mode(aconnector, false);
drm_mode_copy(_mode, );
@@ -7201,7 +7200,7 @@ static void amdgpu_dm_connector_add_freesync_modes(struct
drm_connector *connect
struct amdgpu_dm_connector *amdgpu_dm_connector =
to_amdgpu_dm_connector(connector);
- if (!(amdgpu_freesync_vid_mode && edid))
+ if (!edid)
return;
if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq >
10)
@@ -9246,8 +9245,7 @@ static int dm_update_crtc_state(struct
amdgpu_display_manager *dm,
* TODO: Refactor this function to allow this check to work
* in all conditions.
*/
- if (amdgpu_freesync_vid_mode &&
- dm_new_crtc_state->stream &&
+ if (dm_new_crtc_state->stream &&
is_timing_unchanged_for_freesync(new_crtc_state,
old_crtc_state))
goto skip_modeset;
@@ -9289,7 +9287,7 @@ static int dm_update_crtc_state(struct
amdgpu_display_manager *dm,
}
/* Now check if we should set freesync video mode */
- if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
+ if (dm_new_crtc_state->stream &&
dc_is_stream_unchanged(new_stream,
dm_old_crtc_state->stream) &&
dc_is_stream_scaling_unchanged(new_stream,
dm_old_crtc_state->stream) &&
is_timing_unchanged_for_freesync(new_crtc_state,
@@ -9303,7 +9301,7 @@ static int dm_update_crtc_state(struct
amdgpu_display_manager *dm,
set_freesync_fixed_config(dm_new_crtc_state);
goto skip_modeset;
- } else if (amdgpu_freesync_vid_mode && aconnector &&
+ } else if (aconnector &&
is_freesync_video_mode(_crtc_state->mode,
aconnector)) {
struct drm_display_mode *high_mode;
--
2.40.1
[PATCH 07/14] drm/amd/display: Reduce sdp bw after urgent to 90%
From: Alvin Lee
[Description]
Reduce expected SDP bandwidth due to poor QoS and
arbitration issues on high bandwidth configs
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Stylon Wang
Signed-off-by: Alvin Lee
Reviewed-by: Nevenko Stupar
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 137ff970c9aa..b17f30afa189 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -147,7 +147,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
- .pct_ideal_sdp_bw_after_urgent = 100.0,
+ .pct_ideal_sdp_bw_after_urgent = 90.0,
.pct_ideal_fabric_bw_after_urgent = 67.0,
.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,
.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for
now keep as is until DML implemented
--
2.40.1
[PATCH 06/14] drm/amd/display: Add control flag to dc_stream_state to skip eDP BL off/link off
From: Max Tseng
Add control flag to dc_stream_state to skip eDP BL off/link off.
Acked-by: Stylon Wang
Signed-off-by: Max Tseng
Reviewed-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dc/dc_stream.h | 1 +
.../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c| 3 ++-
drivers/gpu/drm/amd/display/dc/link/link_dpms.c| 7 ---
3 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index d5b3e3a32cc6..3697ea1d14c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -302,6 +302,7 @@ struct dc_stream_state {
bool vblank_synchronized;
bool fpo_in_use;
struct mall_stream_config mall_stream_config;
+ bool skip_edp_power_down;
};
#define ABM_LEVEL_IMMEDIATE_DISABLE 255
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index d4cacb8df631..6c9ca43d1040 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1216,7 +1216,8 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
struct dce_hwseq *hws = link->dc->hwseq;
if (link->local_sink && link->local_sink->sink_signal ==
SIGNAL_TYPE_EDP) {
- hws->funcs.edp_backlight_control(link, false);
+ if (!stream->skip_edp_power_down)
+ hws->funcs.edp_backlight_control(link, false);
link->dc->hwss.set_abm_immediate_disable(pipe_ctx);
}
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index 2963267fe74a..d719a666f974 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -2207,9 +2207,8 @@ static enum dc_status enable_link(
* link settings. Need to call disable first before enabling at
* new link settings.
*/
- if (link->link_status.link_active) {
+ if (link->link_status.link_active && !stream->skip_edp_power_down)
disable_link(link, _ctx->link_res,
pipe_ctx->stream->signal);
- }
switch (pipe_ctx->stream->signal) {
case SIGNAL_TYPE_DISPLAY_PORT:
@@ -2327,7 +2326,9 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)
dc->hwss.disable_stream(pipe_ctx);
} else {
dc->hwss.disable_stream(pipe_ctx);
- disable_link(pipe_ctx->stream->link, _ctx->link_res,
pipe_ctx->stream->signal);
+ if (!pipe_ctx->stream->skip_edp_power_down) {
+ disable_link(pipe_ctx->stream->link,
_ctx->link_res, pipe_ctx->stream->signal);
+ }
}
if (pipe_ctx->stream->timing.flags.DSC) {
--
2.40.1
[PATCH 04/14] drm/amd/display: Refactor fast update to use new HWSS build sequence
From: Alvin Lee
[Description]
- Refactor HW sequencer to use a build / execute sequence
- Also move gamma updates to become fast
Acked-by: Stylon Wang
Signed-off-by: Alvin Lee
Reviewed-by: Jun Lei
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 271 --
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 255
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../amd/display/dc/dce100/dce100_resource.c | 5 +
.../amd/display/dc/dce110/dce110_resource.c | 5 +
.../amd/display/dc/dce112/dce112_resource.c | 5 +
.../amd/display/dc/dce120/dce120_resource.c | 1 +
.../drm/amd/display/dc/dce80/dce80_resource.c | 6 +
.../drm/amd/display/dc/dcn10/dcn10_resource.c | 1 +
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 1 +
.../amd/display/dc/dcn201/dcn201_resource.c | 1 +
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 1 +
.../drm/amd/display/dc/dcn31/dcn31_resource.c | 1 +
.../amd/display/dc/dcn315/dcn315_resource.c | 1 +
.../amd/display/dc/dcn316/dcn316_resource.c | 1 +
.../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 24 ++
.../drm/amd/display/dc/dcn32/dcn32_hwseq.h| 2 +
.../gpu/drm/amd/display/dc/dcn32/dcn32_init.c | 1 +
.../gpu/drm/amd/display/dc/inc/core_types.h | 11 +
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 126
20 files changed, 690 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 2ad4293bb3e5..172bae983425 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2589,15 +2589,19 @@ static enum surface_update_type
det_surface_update(const struct dc *dc,
elevate_update_type(_type, type);
}
- if (update_flags->bits.input_csc_change
- || update_flags->bits.coeff_reduction_change
- || update_flags->bits.lut_3d
- || update_flags->bits.gamma_change
- || update_flags->bits.gamut_remap_change) {
+ if (update_flags->bits.lut_3d) {
type = UPDATE_TYPE_FULL;
elevate_update_type(_type, type);
}
+ if (dc->debug.enable_legacy_fast_update &&
+ (update_flags->bits.gamma_change ||
+ update_flags->bits.gamut_remap_change ||
+ update_flags->bits.input_csc_change ||
+ update_flags->bits.coeff_reduction_change)) {
+ type = UPDATE_TYPE_FULL;
+ elevate_update_type(_type, type);
+ }
return overall_type;
}
@@ -2630,7 +2634,7 @@ static enum surface_update_type
check_update_surfaces_for_stream(
stream_update->integer_scaling_update)
su_flags->bits.scaling = 1;
- if (stream_update->out_transfer_func)
+ if (dc->debug.enable_legacy_fast_update &&
stream_update->out_transfer_func)
su_flags->bits.out_tf = 1;
if (stream_update->abm_level)
@@ -2661,6 +2665,12 @@ static enum surface_update_type
check_update_surfaces_for_stream(
if (stream_update->output_csc_transform ||
stream_update->output_color_space)
su_flags->bits.out_csc = 1;
+
+ /* Output transfer function changes do not require bandwidth
recalculation,
+* so don't trigger a full update
+*/
+ if (!dc->debug.enable_legacy_fast_update &&
stream_update->out_transfer_func)
+ su_flags->bits.out_tf = 1;
}
for (i = 0 ; i < surface_count; i++) {
@@ -3412,6 +3422,163 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
}
}
+static void build_dmub_update_dirty_rect(
+ struct dc *dc,
+ int surface_count,
+ struct dc_stream_state *stream,
+ struct dc_surface_update *srf_updates,
+ struct dc_state *context,
+ struct dc_dmub_cmd dc_dmub_cmd[],
+ unsigned int *dmub_cmd_count)
+{
+ union dmub_rb_cmd cmd;
+ struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
+ unsigned int i, j;
+ unsigned int panel_inst = 0;
+
+ if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
+ return;
+
+ if (!dc_get_edp_link_panel_inst(dc, stream->link, _inst))
+ return;
+
+ memset(, 0x0, sizeof(cmd));
+ cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
+ cmd.update_dirty_rect.header.sub_type = 0;
+ cmd.update_dirty_rect.header.payload_bytes =
+ sizeof(cmd.update_dirty_rect) -
+ sizeof(cmd.update_dirty_rect.header);
+ update_dirty_rect = _dirty_rect.update_dirty_rect_
[PATCH 05/14] drm/amd/display: Wrong index type for pipe iterator
From: Saaem Rizvi
[Why and How]
Type mismatch in index and pipe count might cause an infinite loop. code
Change should resolve this issue.
Acked-by: Stylon Wang
Signed-off-by: Saaem Rizvi
Reviewed-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
index 46b6f4f9e1fd..ce7e6f20b31f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
@@ -392,7 +392,7 @@ void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct
dc_state *context)
{
- uint8_t i;
+ unsigned int i;
struct pipe_ctx *pipe = NULL;
bool otg_disabled[MAX_PIPES] = {false};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 3f11992e380b..00f32ffe0079 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -1201,7 +1201,7 @@ void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct
dc_state *context)
{
- uint8_t i;
+ unsigned int i;
struct pipe_ctx *pipe = NULL;
bool otg_disabled[MAX_PIPES] = {false};
--
2.40.1
[PATCH 03/14] drm/amd/display: fix dcn315 single stream crb allocation
From: Dmytro Laktyushkin
Change to improve avoiding asymetric crb calculations for single stream
scenarios.
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Stylon Wang
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
---
.../drm/amd/display/dc/dcn315/dcn315_resource.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
index cb95e978417b..8570bdc292b4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -1628,6 +1628,10 @@ static bool allow_pixel_rate_crb(struct dc *dc, struct
dc_state *context)
int i;
struct resource_context *res_ctx = >res_ctx;
+ /*Don't apply for single stream*/
+ if (context->stream_count < 2)
+ return false;
+
for (i = 0; i < dc->res_pool->pipe_count; i++) {
if (!res_ctx->pipe_ctx[i].stream)
continue;
@@ -1727,19 +1731,23 @@ static int dcn315_populate_dml_pipes_from_context(
pipe_cnt++;
}
- /* Spread remaining unreserved crb evenly among all pipes, use default
policy if not enough det or single pipe */
+ /* Spread remaining unreserved crb evenly among all pipes*/
if (pixel_rate_crb) {
for (i = 0, pipe_cnt = 0, crb_idx = 0; i <
dc->res_pool->pipe_count; i++) {
pipe = _ctx->pipe_ctx[i];
if (!pipe->stream)
continue;
+ /* Do not use asymetric crb if not enough for pstate
support */
+ if (remaining_det_segs < 0) {
+ pipes[pipe_cnt].pipe.src.det_size_override = 0;
+ continue;
+ }
+
if (!pipe->top_pipe && !pipe->prev_odm_pipe) {
bool split_required =
pipe->stream->timing.pix_clk_100hz >=
dcn_get_max_non_odm_pix_rate_100hz(>dml.soc)
|| (pipe->plane_state &&
pipe->plane_state->src_rect.width > 5120);
- if (remaining_det_segs < 0 || crb_pipes == 1)
-
pipes[pipe_cnt].pipe.src.det_size_override = 0;
if (remaining_det_segs > MIN_RESERVED_DET_SEGS)
pipes[pipe_cnt].pipe.src.det_size_override += (remaining_det_segs -
MIN_RESERVED_DET_SEGS) / crb_pipes +
(crb_idx <
(remaining_det_segs - MIN_RESERVED_DET_SEGS) % crb_pipes ? 1 : 0);
@@ -1755,6 +1763,7 @@ static int dcn315_populate_dml_pipes_from_context(
}
/* Convert segments into size for DML use */
pipes[pipe_cnt].pipe.src.det_size_override *=
DCN3_15_CRB_SEGMENT_SIZE_KB;
+
crb_idx++;
}
pipe_cnt++;
--
2.40.1
[PATCH 01/14] drm/amd/display: add ODM case when looking for first split pipe
From: Samson Tam
[Why]
When going from ODM 2:1 single display case to max displays, second
odm pipe needs to be repurposed for one of the new single displays.
However, acquire_first_split_pipe() only handles MPC case and not
ODM case
[How]
Add ODM conditions in acquire_first_split_pipe()
Add commit_minimal_transition_state() in commit_streams() to handle
odm 2:1 exit first, and then process new streams
Handle ODM condition in commit_minimal_transition_state()
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Stylon Wang
Signed-off-by: Samson Tam
Reviewed-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 36 ++-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 20 +++
2 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f3820c5e63af..2ad4293bb3e5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2008,6 +2008,9 @@ static enum dc_status dc_commit_state_no_check(struct dc
*dc, struct dc_state *c
return result;
}
+static bool commit_minimal_transition_state(struct dc *dc,
+ struct dc_state *transition_base_context);
+
/**
* dc_commit_streams - Commit current stream state
*
@@ -2029,6 +2032,8 @@ enum dc_status dc_commit_streams(struct dc *dc,
struct dc_state *context;
enum dc_status res = DC_OK;
struct dc_validation_set set[MAX_STREAMS] = {0};
+ struct pipe_ctx *pipe;
+ bool handle_exit_odm2to1 = false;
if (dc->ctx->dce_environment == DCE_ENV_VIRTUAL_HW)
return res;
@@ -2053,6 +2058,22 @@ enum dc_status dc_commit_streams(struct dc *dc,
}
}
+ /* Check for case where we are going from odm 2:1 to max
+* pipe scenario. For these cases, we will call
+* commit_minimal_transition_state() to exit out of odm 2:1
+* first before processing new streams
+*/
+ if (stream_count == dc->res_pool->pipe_count) {
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ pipe = >current_state->res_ctx.pipe_ctx[i];
+ if (pipe->next_odm_pipe)
+ handle_exit_odm2to1 = true;
+ }
+ }
+
+ if (handle_exit_odm2to1)
+ res = commit_minimal_transition_state(dc, dc->current_state);
+
context = dc_create_state(dc);
if (!context)
goto context_alloc_fail;
@@ -3912,6 +3933,7 @@ static bool commit_minimal_transition_state(struct dc *dc,
unsigned int i, j;
unsigned int pipe_in_use = 0;
bool subvp_in_use = false;
+ bool odm_in_use = false;
if (!transition_context)
return false;
@@ -3940,6 +3962,18 @@ static bool commit_minimal_transition_state(struct dc
*dc,
}
}
+ /* If ODM is enabled and we are adding or removing planes from any ODM
+* pipe, we must use the minimal transition.
+*/
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = >current_state->res_ctx.pipe_ctx[i];
+
+ if (pipe->stream && pipe->next_odm_pipe) {
+ odm_in_use = true;
+ break;
+ }
+ }
+
/* When the OS add a new surface if we have been used all of pipes with
odm combine
* and mpc split feature, it need use commit_minimal_transition_state
to transition safely.
* After OS exit MPO, it will back to use odm and mpc split with all of
pipes, we need
@@ -3948,7 +3982,7 @@ static bool commit_minimal_transition_state(struct dc *dc,
* Reduce the scenarios to use dc_commit_state_no_check in the stage of
flip. Especially
* enter/exit MPO when DCN still have enough resources.
*/
- if (pipe_in_use != dc->res_pool->pipe_count && !subvp_in_use) {
+ if (pipe_in_use != dc->res_pool->pipe_count && !subvp_in_use &&
!odm_in_use) {
dc_release_state(transition_context);
return true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 7e1e5532f88f..c72540d37aef 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1445,6 +1445,26 @@ static int acquire_first_split_pipe(
split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
split_pipe->pipe_idx = i;
+ split_pipe->stream = stream;
+ return i;
+ } else if (split_pipe->prev_odm_pipe &&
+
[PATCH 02/14] drm/amd/display: fix seamless odm transitions
From: Dmytro Laktyushkin
Add missing programming and function pointers
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Acked-by: Stylon Wang
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 11 +++
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h | 1 +
3 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index eaf9e9ccad2a..20f668d28364 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1741,6 +1741,17 @@ static void dcn20_program_pipe(
if (hws->funcs.setup_vupdate_interrupt)
hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
+
+ if (hws->funcs.calculate_dccg_k1_k2_values &&
dc->res_pool->dccg->funcs->set_pixel_rate_div) {
+ unsigned int k1_div, k2_div;
+
+ hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx,
_div, _div);
+
+ dc->res_pool->dccg->funcs->set_pixel_rate_div(
+ dc->res_pool->dccg,
+ pipe_ctx->stream_res.tg->inst,
+ k1_div, k2_div);
+ }
}
if (pipe_ctx->update_flags.bits.odm)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
index 6ef56fb32131..2cffedea2df5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
@@ -98,7 +98,7 @@ static void optc32_set_odm_combine(struct timing_generator
*optc, int *opp_id, i
optc1->opp_count = opp_cnt;
}
-static void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc,
bool manual_mode)
+void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool
manual_mode)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
index b92ba8c75694..abf0121a1006 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.h
@@ -179,5 +179,6 @@
SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
void dcn32_timing_generator_init(struct optc *optc1);
+void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool
manual_mode);
#endif /* __DC_OPTC_DCN32_H__ */
--
2.40.1
[PATCH 00/14] DC Patches June 2, 2023
This DC patchset brings improvements in multiple areas. In summary, we have: * Clock optimiation for DCN 3.1.4 * Performance improvements * Improvements on power saving * Fix screen flash in high resolution displays * Enable Freesync video mode by default * Bug fixed on hang or crashes in various cases * Improved code robustness in corner cases Cc: Daniel Wheeler Alvin Lee (2): drm/amd/display: Refactor fast update to use new HWSS build sequence drm/amd/display: Reduce sdp bw after urgent to 90% Aurabindo Pillai (1): drm/amd/display: Enable Freesync Video Mode by default Austin Zheng (1): drm/amd/display: Filter out AC mode frequencies on DC mode systems Charlene Liu (1): drm/amd/display: add NULL pointer check Daniel Miess (1): drm/amd/display: Enable dcn314 DPP RCO Dmytro Laktyushkin (2): drm/amd/display: fix seamless odm transitions drm/amd/display: fix dcn315 single stream crb allocation Leo Ma (1): Revert "drm/amd/display: cache trace buffer size" Max Tseng (1): drm/amd/display: Add control flag to dc_stream_state to skip eDP BL off/link off Nicholas Kazlauskas (1): drm/amd/display: Skip DPP DTO update if root clock is gated Saaem Rizvi (1): drm/amd/display: Wrong index type for pipe iterator Samson Tam (1): drm/amd/display: add ODM case when looking for first split pipe Sridevi (1): drm/amd/display: DSC Programming Deltas .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +- .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 13 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 307 -- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 255 +++ .../gpu/drm/amd/display/dc/core/dc_resource.c | 20 ++ .../gpu/drm/amd/display/dc/core/dc_stream.c | 4 +- drivers/gpu/drm/amd/display/dc/dc.h | 2 + drivers/gpu/drm/amd/display/dc/dc_stream.h| 1 + .../amd/display/dc/dce100/dce100_resource.c | 5 + .../display/dc/dce110/dce110_hw_sequencer.c | 3 +- .../amd/display/dc/dce110/dce110_resource.c | 5 + .../amd/display/dc/dce112/dce112_resource.c | 5 + .../amd/display/dc/dce120/dce120_resource.c | 1 + .../drm/amd/display/dc/dce80/dce80_resource.c | 6 + .../drm/amd/display/dc/dcn10/dcn10_resource.c | 1 + .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 29 +- .../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h | 28 ++ .../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 11 + .../drm/amd/display/dc/dcn20/dcn20_resource.c | 1 + .../amd/display/dc/dcn201/dcn201_resource.c | 1 + .../drm/amd/display/dc/dcn21/dcn21_resource.c | 1 + .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 8 + .../drm/amd/display/dc/dcn31/dcn31_resource.c | 1 + .../drm/amd/display/dc/dcn314/dcn314_dccg.c | 5 + .../drm/amd/display/dc/dcn314/dcn314_hwseq.c | 2 +- .../amd/display/dc/dcn314/dcn314_resource.c | 16 + .../amd/display/dc/dcn315/dcn315_resource.c | 16 +- .../amd/display/dc/dcn316/dcn316_resource.c | 1 + .../drm/amd/display/dc/dcn32/dcn32_hwseq.c| 26 +- .../drm/amd/display/dc/dcn32/dcn32_hwseq.h| 2 + .../gpu/drm/amd/display/dc/dcn32/dcn32_init.c | 1 + .../gpu/drm/amd/display/dc/dcn32/dcn32_optc.c | 2 +- .../gpu/drm/amd/display/dc/dcn32/dcn32_optc.h | 1 + .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 142 +--- .../amd/display/dc/dml/dcn321/dcn321_fpu.c| 144 +--- .../gpu/drm/amd/display/dc/inc/core_types.h | 11 + .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 1 + drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 1 + .../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 126 +++ .../gpu/drm/amd/display/dc/link/link_dpms.c | 7 +- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 - .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 2 - 42 files changed, 1071 insertions(+), 156 deletions(-) -- 2.40.1
[PATCH 14/14] drm/amd/display: 3.2.215
From: Aric Cyr Acked-by: Stylon Wang Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 3cb8cf065204..85ebeaa2de18 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -47,7 +47,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.214" +#define DC_VER "3.2.215" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.25.1
[PATCH 13/14] drm/amd/display: set optimized required for comp buf changes
From: Dillon Varone
[Description]
When compressed buffer allocation changes, optimized required flag should be
set to trigger an update in optimize bandwidth.
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index bc4a303cd864..6291a241158a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2011,10 +2011,13 @@ void dcn20_prepare_bandwidth(
/* decrease compbuf size */
if (hubbub->funcs->program_compbuf_size) {
- if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes)
+ if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) {
compbuf_size_kb =
context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes;
- else
+ dc->wm_optimized_required |= (compbuf_size_kb !=
dc->current_state->bw_ctx.dml.ip.min_comp_buffer_size_kbytes);
+ } else {
compbuf_size_kb =
context->bw_ctx.bw.dcn.compbuf_size_kb;
+ dc->wm_optimized_required |= (compbuf_size_kb !=
dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb);
+ }
hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb,
false);
}
--
2.25.1
[PATCH 12/14] drm/amd/display: Add debug option to skip PSR CRTC disable
From: Nicholas Kazlauskas
[Why]
It's currently tied to Z10 support, and is required for Z10, but
we can still support Z10 display off without PSR.
We currently need to skip the PSR CRTC disable to prevent stuttering
and underflow from occuring during PSR-SU.
[How]
Add a debug option to allow specifying this separately.
Reviewed-by: Robin Chen
Acked-by: Stylon Wang
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 1 +
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 5304e9daf90a..342e906ae26e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3378,7 +3378,7 @@ bool dc_link_setup_psr(struct dc_link *link,
case FAMILY_YELLOW_CARP:
case AMDGPU_FAMILY_GC_10_3_6:
case AMDGPU_FAMILY_GC_11_0_1:
- if (dc->debug.disable_z10)
+ if (dc->debug.disable_z10 ||
dc->debug.psr_skip_crtc_disable)
psr_context->psr_level.bits.SKIP_CRTC_DISABLE =
true;
break;
default:
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 4a7c0356d9c7..3cb8cf065204 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -844,6 +844,7 @@ struct dc_debug_options {
int crb_alloc_policy_min_disp_count;
bool disable_z10;
bool enable_z9_disable_interface;
+ bool psr_skip_crtc_disable;
union dpia_debug_options dpia_debug;
bool disable_fixed_vs_aux_timeout_wa;
bool force_disable_subvp;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 4fffc7bb8088..f9ea1e86707f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -886,6 +886,7 @@ static const struct dc_plane_cap plane_cap = {
static const struct dc_debug_options debug_defaults_drv = {
.disable_z10 = false,
.enable_z9_disable_interface = true,
+ .psr_skip_crtc_disable = true,
.disable_dmcu = true,
.force_abm_enable = false,
.timing_trace = false,
--
2.25.1
[PATCH 11/14] drm/amd/display: correct DML calc error of UrgentLatency
From: Zhongwei [Why] The input UrgentLatency in CalculateUrgentBurstFactor of prefect check is wrong. [How] Correct to the correct one to keep same as HW formula Reviewed-by: Charlene Liu Acked-by: Stylon Wang Signed-off-by: Zhongwei --- drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 2 +- drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 2 +- .../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c| 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index 479e2c1a1301..379729b02847 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -4851,7 +4851,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->SwathHeightYThisState[k], v->SwathHeightCThisState[k], v->HTotal[k] / v->PixelClock[k], - v->UrgentLatency, + v->UrgLatency[i], v->CursorBufferSize, v->CursorWidth[k][0], v->CursorBPP[k][0], diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c index 4e45c6d9ecdc..ec351c8418cb 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c @@ -5082,7 +5082,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l v->SwathHeightYThisState[k], v->SwathHeightCThisState[k], v->HTotal[k] / v->PixelClock[k], - v->UrgentLatency, + v->UrgLatency[i], v->CursorBufferSize, v->CursorWidth[k][0], v->CursorBPP[k][0], diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c index 41f0b4c1c72f..950669f2c10d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c @@ -5179,7 +5179,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ v->SwathHeightYThisState[k], v->SwathHeightCThisState[k], v->HTotal[k] / v->PixelClock[k], - v->UrgentLatency, + v->UrgLatency[i], v->CursorBufferSize, v->CursorWidth[k][0], v->CursorBPP[k][0], -- 2.25.1
[PATCH 10/14] drm/amd/display: correct static_screen_event_mask
From: Charlene Liu
[why]
HW register bit define changed.
Reviewed-by: Zhan Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Stylon Wang
Signed-off-by: Charlene Liu
---
.../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 40 +++
.../drm/amd/display/dc/dcn31/dcn31_hwseq.h| 4 ++
.../gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 4 +-
.../gpu/drm/amd/display/dc/dcn31/dcn31_optc.c | 29 +-
.../gpu/drm/amd/display/dc/dcn31/dcn31_optc.h | 5 ++-
.../drm/amd/display/dc/dcn314/dcn314_init.c | 4 +-
.../drm/amd/display/dc/dcn314/dcn314_optc.c | 2 +-
7 files changed, 81 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 165c920ca776..4226a051df41 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -623,3 +623,43 @@ void dcn31_setup_hpo_hw_control(const struct dce_hwseq
*hws, bool enable)
if (hws->ctx->dc->debug.hpo_optimization)
REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable);
}
+void dcn31_set_drr(struct pipe_ctx **pipe_ctx,
+ int num_pipes, struct dc_crtc_timing_adjust adjust)
+{
+ int i = 0;
+ struct drr_params params = {0};
+ unsigned int event_triggers = 0x2;/*Bit[1]: OTG_TRIG_A*/
+ unsigned int num_frames = 2;
+ params.vertical_total_max = adjust.v_total_max;
+ params.vertical_total_min = adjust.v_total_min;
+ params.vertical_total_mid = adjust.v_total_mid;
+ params.vertical_total_mid_frame_num = adjust.v_total_mid_frame_num;
+ for (i = 0; i < num_pipes; i++) {
+ if ((pipe_ctx[i]->stream_res.tg != NULL) &&
pipe_ctx[i]->stream_res.tg->funcs) {
+ if (pipe_ctx[i]->stream_res.tg->funcs->set_drr)
+ pipe_ctx[i]->stream_res.tg->funcs->set_drr(
+ pipe_ctx[i]->stream_res.tg, );
+ if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
+ if
(pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control)
+
pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
+ pipe_ctx[i]->stream_res.tg,
+ event_triggers, num_frames);
+ }
+ }
+}
+void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx,
+ int num_pipes, const struct dc_static_screen_params *params)
+{
+ unsigned int i;
+ unsigned int triggers = 0;
+ if (params->triggers.surface_update)
+ triggers |= 0x600;/*bit 9 and bit10 : 110 */
+ if (params->triggers.cursor_update)
+ triggers |= 0x10;/*bit4*/
+ if (params->triggers.force_trigger)
+ triggers |= 0x1;
+ for (i = 0; i < num_pipes; i++)
+ pipe_ctx[i]->stream_res.tg->funcs->
+ set_static_screen_control(pipe_ctx[i]->stream_res.tg,
+ triggers, params->num_frames);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h
index edfc01d6ad73..e7e03a8722e0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h
@@ -56,4 +56,8 @@ bool dcn31_is_abm_supported(struct dc *dc,
void dcn31_init_pipes(struct dc *dc, struct dc_state *context);
void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);
+void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx,
+ int num_pipes, const struct dc_static_screen_params *params);
+void dcn31_set_drr(struct pipe_ctx **pipe_ctx,
+ int num_pipes, struct dc_crtc_timing_adjust adjust);
#endif /* __DC_HWSS_DCN31_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
index 3a32810bbe38..7c2da70ffe21 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
@@ -64,9 +64,9 @@ static const struct hw_sequencer_funcs dcn31_funcs = {
.prepare_bandwidth = dcn20_prepare_bandwidth,
.optimize_bandwidth = dcn20_optimize_bandwidth,
.update_bandwidth = dcn20_update_bandwidth,
- .set_drr = dcn10_set_drr,
+ .set_drr = dcn31_set_drr,
.get_position = dcn10_get_position,
- .set_static_screen_control = dcn10_set_static_screen_control,
+ .set_static_screen_control = dcn31_set_static_screen_control,
.setup_stereo = dcn10_setup_stereo,
.set_avmute = dcn30_set_avmute,
.log_hw_state = dcn10_log_hw_state,
diff --git a/drivers/gpu/drm
[PATCH 09/14] drm/amd/display: Ensure commit_streams returns the DC return code
From: Alvin Lee
[Description]
- Ensure dc_commit_streams returns the correct return code so any
failures can be handled properly in DM layer
- If set timings fail and we have to remove MPO planes, do so
unconditionally but make sure to mark for removal so we report
the VSYNC and prevent timeout
- Failure to remove MPO plane results in set timings failure due
to lack of resources
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 486d18290b9f..0cb8d1f934d1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1988,7 +1988,7 @@ enum dc_status dc_commit_streams(struct dc *dc,
DC_LOG_DC("%s Finished.\n", __func__);
- return (res == DC_OK);
+ return res;
}
/* TODO: When the transition to the new commit sequence is done, remove this
--
2.25.1
[PATCH 08/14] drm/amd/display: read invalid ddc pin status cause engine busy
From: Paul Hsieh
[Why]
There is no DDC_6 pin on new asic cause the mapping table is
incorrect. When app try to access DDC_VGA port, driver read
an invalid ddc pin status and report engine busy.
[How]
Add dummy DDC_6 pin to align gpio structure.
Reviewed-by: Alvin Lee
Acked-by: Stylon Wang
Signed-off-by: Paul Hsieh
---
drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
index 0ea52ba5ac82..9fd8b269dd79 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c
@@ -256,8 +256,8 @@ static const struct hw_factory_funcs funcs = {
*/
void dal_hw_factory_dcn32_init(struct hw_factory *factory)
{
- factory->number_of_pins[GPIO_ID_DDC_DATA] = 6;
- factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 6;
+ factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
+ factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
factory->number_of_pins[GPIO_ID_GENERIC] = 4;
factory->number_of_pins[GPIO_ID_HPD] = 5;
factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
--
2.25.1
[PATCH 07/14] drm/amd/display: Bypass DET swath fill check for max clocks
From: Dillon Varone [Description] If validating for max voltage level (therefore max clocks) always pass over the DET swath fill latency hiding check. Reviewed-by: Alvin Lee Acked-by: Stylon Wang Signed-off-by: Dillon Varone --- drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c index 820042f6aaca..4b8f5fa0f0ad 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c @@ -1683,8 +1683,9 @@ static void mode_support_configuration(struct vba_vars_st *v, && mode_lib->vba.PTEBufferSizeNotExceeded[i][j] == true && mode_lib->vba.DCCMetaBufferSizeNotExceeded[i][j] == true && mode_lib->vba.NonsupportedDSCInputBPC == false - && mode_lib->vba.NotEnoughDETSwathFillLatencyHidingPerState[i][j] == false && !mode_lib->vba.ExceededMALLSize + && (mode_lib->vba.NotEnoughDETSwathFillLatencyHidingPerState[i][j] == false + || i == v->soc.num_states - 1) && ((mode_lib->vba.HostVMEnable == false && !mode_lib->vba.ImmediateFlipRequiredFinal) || mode_lib->vba.ImmediateFlipSupportedForState[i][j]) -- 2.25.1
[PATCH 06/14] drm/amd/display: Disable uclk pstate for subvp pipes
From: Dillon Varone
[Description]
When subvp is in use, main pipes should block unintended natural uclk pstate
changes to prevent disruption to the state machine.
Reviewed-by: Alvin Lee
Acked-by: Stylon Wang
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index c9b2343947be..b8767be1e4c5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -703,11 +703,7 @@ void dcn32_subvp_update_force_pstate(struct dc *dc, struct
dc_state *context)
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
- // For SubVP + DRR, also force disallow on the DRR pipe
- // (We will force allow in the DMUB sequence -- some DRR
timings by default won't allow P-State so we have
- // to force once the vblank is stretched).
- if (pipe->stream && pipe->plane_state &&
(pipe->stream->mall_stream_config.type == SUBVP_MAIN ||
- (pipe->stream->mall_stream_config.type ==
SUBVP_NONE && pipe->stream->ignore_msa_timing_param))) {
+ if (pipe->stream && pipe->plane_state &&
(pipe->stream->mall_stream_config.type == SUBVP_MAIN)) {
struct hubp *hubp = pipe->plane_res.hubp;
if (hubp &&
hubp->funcs->hubp_update_force_pstate_disallow)
@@ -785,6 +781,10 @@ void dcn32_program_mall_pipe_config(struct dc *dc, struct
dc_state *context)
if (hws && hws->funcs.update_mall_sel)
hws->funcs.update_mall_sel(dc, context);
+ //update subvp force pstate
+ if (hws && hws->funcs.subvp_update_force_pstate)
+ dc->hwseq->funcs.subvp_update_force_pstate(dc, context);
+
// Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp
pipes
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
--
2.25.1
[PATCH 05/14] drm/amd/display: Fix DCN2.1 default DSC clocks
From: Michael Strauss
[WHY]
Low dscclk in high vlevels blocks some DSC modes.
[HOW]
Update dscclk to 1/3 of dispclk.
Reviewed-by: Charlene Liu
Acked-by: Stylon Wang
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index c4eca10587a6..c26da3bb2892 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -565,7 +565,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
.dppclk_mhz = 847.06,
.phyclk_mhz = 810.0,
.socclk_mhz = 953.0,
- .dscclk_mhz = 489.0,
+ .dscclk_mhz = 300.0,
.dram_speed_mts = 2400.0,
},
{
@@ -576,7 +576,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
.dppclk_mhz = 960.00,
.phyclk_mhz = 810.0,
.socclk_mhz = 278.0,
- .dscclk_mhz = 287.67,
+ .dscclk_mhz = 342.86,
.dram_speed_mts = 2666.0,
},
{
@@ -587,7 +587,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
.dppclk_mhz = 1028.57,
.phyclk_mhz = 810.0,
.socclk_mhz = 715.0,
- .dscclk_mhz = 318.334,
+ .dscclk_mhz = 369.23,
.dram_speed_mts = 3200.0,
},
{
--
2.25.1
[PATCH 04/14] drm/amd/display: Enable dp_hdmi21_pcon support
From: David Galiffi
[Why]
It is not enabled for DCN3.0.1, 3.0.2, 3.0.3.
[How]
Add `dc->caps.dp_hdmi21_pcon_support = true` to these DCN versions.
Reviewed-by: Martin Leung
Acked-by: Stylon Wang
Signed-off-by: David Galiffi
---
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 2 ++
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 2 ++
drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c | 2 ++
3 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 480145f09246..8cf10351f271 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -1493,6 +1493,8 @@ static bool dcn301_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
+ dc->caps.dp_hdmi21_pcon_support = true;
+
/* read VBIOS LTTPR caps */
if (ctx->dc_bios->funcs->get_lttpr_caps) {
enum bp_result bp_query_result;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index 7d11c2a43cbe..47cffd0e6830 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -1281,6 +1281,8 @@ static bool dcn302_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
+ dc->caps.dp_hdmi21_pcon_support = true;
+
/* read VBIOS LTTPR caps */
if (ctx->dc_bios->funcs->get_lttpr_caps) {
enum bp_result bp_query_result;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
index 92393b04cc44..c14d35894b2e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
@@ -1212,6 +1212,8 @@ static bool dcn303_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
+ dc->caps.dp_hdmi21_pcon_support = true;
+
/* read VBIOS LTTPR caps */
if (ctx->dc_bios->funcs->get_lttpr_caps) {
enum bp_result bp_query_result;
--
2.25.1
