Re: Looking for a good book on ECKD EXCP, CCWs, etc.
I believe that the basic ECKD stuff is pretty much the same for everybody, but if you have to deal with the various remote copy and mirroring options then you need documentation specific to the gear that you're using. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Steve Marak Sent: Friday, July 19, 2024 4:36 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Looking for a good book on ECKD EXCP, CCWs, etc. Tony, I wished for the book you wanted in the original post many times and never found it. I wound up cobbling together a bunch of sources. The PoP was essential for the basics of the channel subsystem, but you have to go to the various device manuals for anything specific to them. For ECKD, the only authoritative references I found were the storage controller (what we used to call the control unit) references. I started with the 3990 Storage Control Reference, which IIRC was strangely hard to find as a PDF - I had a tattered hardcopy I kept locked away in my office for years. Later I used the IBM Enterprise Storage Server System/390 Command Reference 2105 Models E10, E20, F10, and F20 (SC26-7298) - newer, though it's old now too, and it was available in PDF. Some of the equivalent manuals for other brands of ECKD storage subsystems also have good information but as usual be very careful about applying it beyond the hardware for which it was written. Those are good for technical details of the various CCWs, error conditions, and sense information, but they had no practical examples. I was fortunate to always have VM systems available, and I shamelessly scrounged through the optional source code to see how the IBM developers coded their channel programs, and learned a lot. I also found some interesting channel programs in the sources for the Linux z distros - not all of the device specific stuff is closed source. The Hercules project also has some good stuff online. I wrote a lot of channel programs that ran on z/OS or its precursors, but even allowing for my VM bias I believe it's a lot easier to learn this stuff, and debug when you're doing something new, by experimenting on VM. You're a lot closer to the action, the CP diagnose interface allows you to execute channel programs synchronously with CP handling the interrupts and gathering sense info for you, the CP tracing facilities are very powerful and helpful, and CP provides extremely strong isolation that kept me from ever shooting anyone's feet but my own. Saved me huge amounts of time. Good luck! Steve On 7/19/2024 12:45 PM, Tony Thigpen wrote: > SA22-1025-00 > Internal Disk Subsystem: > Reference Guide > Multiprise 3000 Enterprise Server > > Tony Thigpen > > Michael Watkins wrote on 7/19/24 1:29 PM: >> What is the full title of the 'MP3k' book? Is it an IBM document? >> >> -Original Message- >> From: IBM Mainframe Assembler List >> On Behalf Of Tony Thigpen >> Sent: Thursday, July 18, 2024 5:57 PM >> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU >> Subject: Re: Looking for a good book on ECKD EXCP, CCWs, etc. >> >> CAUTION: This email originated from outside of the Texas >> Comptroller's email system. >> DO NOT click links or open attachments unless you expect them from >> the sender and know the content is safe. >> >> Thanks Ed. I do have that book. It's actually better indexed than the >> other book I was using as a reference even though the MP3K book was >> dated a few months earlier. >> >> Tony Thigpen >> >> Ed Jaffe wrote on 7/18/24 5:46 PM: >>> The reference I learned from was the MP3000 book describing the CCWs >>> available on its integrated SSD RAID DASD. >>> >>> On 7/18/2024 1:13 PM, Tony Thigpen wrote: >>>> I have several books that include basic EXCP/CCW dasd programming, >>>> but nothing that I would consider 'deep' enough on ECKD programming. >>>> Some of the books I have are were good with CKD, but not ECKD. >>>> >>>> So, I am looking for suggestions for books that are designed to teach >>>> someone complex ECKD programming within the restrictions imposed by >>>> the OS. >>>> >>>> Tony Thigpen >>>> >>> -- >>> -- This e-mail message, including any attachments, appended >>> messages and the information contained therein, is for the sole use of >>> the intended recipient(s). If you are not an intended recipient or >>> have otherwise received this email message in error, any use, >>
Re: Looking for a good book on ECKD EXCP, CCWs, etc.
Where did you find it? looked in what I thought were the obvious directories and all I could find was two editions of the introduction. Of curse, those might be useful reading prior to tackling the reference. Was what you found for the model 6? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Michael Watkins <0dc76944fa9c-dmarc-requ...@listserv.uga.edu> Sent: Friday, July 19, 2024 2:56 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Looking for a good book on ECKD EXCP, CCWs, etc. I've found a few of the reference manuals for the 3990 on bitsavers and other wayback-type websites. Thanks. -Original Message- From: IBM Mainframe Assembler List On Behalf Of Seymour J Metz Sent: Friday, July 19, 2024 1:44 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Looking for a good book on ECKD EXCP, CCWs, etc. Just the 3390 or both 3390 and 3990? I've found a few of the 3990 reference manual on bitsavers and other wayback-type webites. Thanks -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר That requires downloading an extension. Do you have links to reference manuals for, e.g., 2105, 3990? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
Re: Looking for a good book on ECKD EXCP, CCWs, etc.
Just the 3390 or both 3390 and 3990? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Michael Watkins <0dc76944fa9c-dmarc-requ...@listserv.uga.edu> Sent: Friday, July 19, 2024 2:37 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Looking for a good book on ECKD EXCP, CCWs, etc. You are correct; Ed's suggestion also requires downloading an executable. I do have current and some past reference manuals for the 3390. -Original Message- From: IBM Mainframe Assembler List On Behalf Of Seymour J Metz Sent: Friday, July 19, 2024 1:29 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Looking for a good book on ECKD EXCP, CCWs, etc. CAUTION: This email originated from outside of the Texas Comptroller's email system. DO NOT click links or open attachments unless you expect them from the sender and know the content is safe. That requires downloading an extension. Do you have links to reference manuals for, e.g., 2105, 3990? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Ed Jaffe <17285f33d197-dmarc-requ...@listserv.uga.edu> Sent: Friday, July 19, 2024 2:24 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Looking for a good book on ECKD EXCP, CCWs, etc. You can download it yourself from: https://www.manualslib.com/manual/882015/Ibm-Multiprise-3000.html On 7/19/2024 11:00 AM, Michael Watkins wrote: > Thanks. I can find i SA22-1025-00 on OneLaunch, but my employer's security > policy does not allow me to install this. Do you happen to have a .PDF of > either SA22-1025-00 or SA22-1026-00 that you could email to > michael.watk...@cpa.texas.gov? > > -Original Message- > From: IBM Mainframe Assembler List > On Behalf Of Tony Thigpen > Sent: Friday, July 19, 2024 12:46 PM > To: ASSEMBLER-LIST@LISTSERV.UGA.EDU > Subject: Re: Looking for a good book on ECKD EXCP, CCWs, etc. > > SA22-1025-00 > Internal Disk Subsystem: > Reference Guide > Multiprise 3000 Enterprise Server > > Tony Thigpen > > Michael Watkins wrote on 7/19/24 1:29 PM: >> What is the full title of the 'MP3k' book? Is it an IBM document? >> >> -Original Message- >> From: IBM Mainframe Assembler List >> On Behalf Of Tony Thigpen >> Sent: Thursday, July 18, 2024 5:57 PM >> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU >> Subject: Re: Looking for a good book on ECKD EXCP, CCWs, etc. >> >> Thanks Ed. I do have that book. It's actually better indexed than the other >> book I was using as a reference even though the MP3K book was dated a few >> months earlier. >> >> Tony Thigpen >> >> Ed Jaffe wrote on 7/18/24 5:46 PM: The reference I learned from was the MP3000 book describing the CCWs available on its integrated SSD RAID DASD. >>> >>> On 7/18/2024 1:13 PM, Tony Thigpen wrote: I have several books that include basic EXCP/CCW dasd programming, but nothing that I would consider 'deep' enough on ECKD programming. Some of the books I have are were good with CKD, but not ECKD. >>>> So, I am looking for suggestions for books that are designed to teach someone complex ECKD programming within the restrictions imposed by the OS. >>>> >>>> Tony Thigpen
Re: Looking for a good book on ECKD EXCP, CCWs, etc.
That requires downloading an extension. Do you have links to reference manuals for, e.g., 2105, 3990? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Ed Jaffe <17285f33d197-dmarc-requ...@listserv.uga.edu> Sent: Friday, July 19, 2024 2:24 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Looking for a good book on ECKD EXCP, CCWs, etc. You can download it yourself from: https://www.manualslib.com/manual/882015/Ibm-Multiprise-3000.html On 7/19/2024 11:00 AM, Michael Watkins wrote: > Thanks. I can find i SA22-1025-00 on OneLaunch, but my employer's security > policy does not allow me to install this. Do you happen to have a .PDF of > either SA22-1025-00 or SA22-1026-00 that you could email to > michael.watk...@cpa.texas.gov? > > > -Original Message- > From: IBM Mainframe Assembler List On > Behalf Of Tony Thigpen > Sent: Friday, July 19, 2024 12:46 PM > To: ASSEMBLER-LIST@LISTSERV.UGA.EDU > Subject: Re: Looking for a good book on ECKD EXCP, CCWs, etc. > > CAUTION: This email originated from outside of the Texas Comptroller's email > system. > DO NOT click links or open attachments unless you expect them from the sender > and know the content is safe. > > SA22-1025-00 > Internal Disk Subsystem: > Reference Guide > Multiprise 3000 Enterprise Server > > Tony Thigpen > > Michael Watkins wrote on 7/19/24 1:29 PM: >> What is the full title of the 'MP3k' book? Is it an IBM document? >> >> -Original Message- >> From: IBM Mainframe Assembler List >> On Behalf Of Tony Thigpen >> Sent: Thursday, July 18, 2024 5:57 PM >> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU >> Subject: Re: Looking for a good book on ECKD EXCP, CCWs, etc. >> >> CAUTION: This email originated from outside of the Texas Comptroller's email >> system. >> DO NOT click links or open attachments unless you expect them from the >> sender and know the content is safe. >> >> Thanks Ed. I do have that book. It's actually better indexed than the other >> book I was using as a reference even though the MP3K book was dated a few >> months earlier. >> >> Tony Thigpen >> >> Ed Jaffe wrote on 7/18/24 5:46 PM: >>> The reference I learned from was the MP3000 book describing the CCWs >>> available on its integrated SSD RAID DASD. >>> >>> On 7/18/2024 1:13 PM, Tony Thigpen wrote: >>>> I have several books that include basic EXCP/CCW dasd programming, >>>> but nothing that I would consider 'deep' enough on ECKD programming. >>>> Some of the books I have are were good with CKD, but not ECKD. >>>> >>>> So, I am looking for suggestions for books that are designed to >>>> teach someone complex ECKD programming within the restrictions >>>> imposed by the OS. >>>> >>>> Tony Thigpen This e-mail message, including any attachments, appended messages and the information contained therein, is for the sole use of the intended recipient(s). If you are not an intended recipient or have otherwise received this email message in error, any use, dissemination, distribution, review, storage or copying of this e-mail message and the information contained therein is strictly prohibited. If you are not an intended recipient, please contact the sender by reply e-mail and destroy all copies of this email message and do not otherwise utilize or retain this email message or any or all of the information contained therein. Although this email message and any attachments or appended messages are believed to be free of any virus or other defect that might affect any computer system into which it is received and opened, it is the responsibility of the recipient to ensure that it is virus free and no responsibility is accepted by the sender for any loss or damage arising in any way from its opening or use.
Re: Don't do this......
The last time I looked the CBT tape had a few OCO programs, but someone may have disassembled and commented all of them by now. I know that Gerhard Postpischil ז״ל, a departed friend and colleague, did so for at least one. IAC, I know of nothing on the CBT tape requires paying license fees, so no shareware, -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Tony Thigpen Sent: Friday, July 19, 2024 11:37 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Don't do this.. Are CBT files shareware or open source? Tony Thigpen Seymour J Metz wrote on 7/19/24 11:23 AM: > Mystery code is often clearer if you assemble it and look at the listing. > > BTW, shareware is not the same as open source. > > -- > Shmuel (Seymour J.) Metz > http://mason.gmu.edu/~smetz3 > עַם יִשְׂרָאֵל חַי > נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר > > > > > From: IBM Mainframe Assembler List on > behalf of Tony Thigpen > Sent: Friday, July 19, 2024 10:56 AM > To: ASSEMBLER-LIST@LISTSERV.UGA.EDU > Subject: Don't do this.. > > Found in some shareware code: > > >MVI RO,2 > > Please page down when you think you know what the program was doing. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > elsewhere > RO EQU SEEKO+7,1 > > I finally figured out what was happening when I copied the code from the > PC editor I was using to view the shareware code to a test program in > xedit so I could see what it was actually doing. The character after the > "R" was the letter 'OH', not a 'zero', but the pc editor does not > display a significantly different item for zero and the letter 'O'. > > > > Tony Thigpen
Re: Don't do this......
Mystery code is often clearer if you assemble it and look at the listing. BTW, shareware is not the same as open source. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Tony Thigpen Sent: Friday, July 19, 2024 10:56 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Don't do this.. Found in some shareware code: MVI RO,2 Please page down when you think you know what the program was doing. elsewhere RO EQU SEEKO+7,1 I finally figured out what was happening when I copied the code from the PC editor I was using to view the shareware code to a test program in xedit so I could see what it was actually doing. The character after the "R" was the letter 'OH', not a 'zero', but the pc editor does not display a significantly different item for zero and the letter 'O'. Tony Thigpen
Re: Looking for a good book on ECKD EXCP, CCWs, etc.
For starters, read up on Define Extent and Locate, but EXCP hangs a prefix on that limits what you can do, analogous to the old Set File Mask. If you're authorized, you can do what you want. For EXCPVR you'll want to write a few appendages. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Tony Thigpen Sent: Thursday, July 18, 2024 4:38 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Looking for a good book on ECKD EXCP, CCWs, etc. Eventually, both. I can play all I want, anytime, on the DR box. Tony Thigpen Seymour J Metz wrote on 7/18/24 4:19 PM: > I'd advise asking on ibmmain. > > Are you looking for authorized or unauthorized? > > -- > Shmuel (Seymour J.) Metz > http://mason.gmu.edu/~smetz3 > עַם יִשְׂרָאֵל חַי > נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר > > > > > From: IBM Mainframe Assembler List on > behalf of Tony Thigpen > Sent: Thursday, July 18, 2024 4:13 PM > To: ASSEMBLER-LIST@LISTSERV.UGA.EDU > Subject: Looking for a good book on ECKD EXCP, CCWs, etc. > > I have several books that include basic EXCP/CCW dasd programming, but > nothing that I would consider 'deep' enough on ECKD programming. Some of > the books I have are were good with CKD, but not ECKD. > > So, I am looking for suggestions for books that are designed to teach > someone complex ECKD programming within the restrictions imposed by the OS. > > Tony Thigpen
Re: Looking for a good book on ECKD EXCP, CCWs, etc.
I'd advise asking on ibmmain. Are you looking for authorized or unauthorized? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Tony Thigpen Sent: Thursday, July 18, 2024 4:13 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Looking for a good book on ECKD EXCP, CCWs, etc. I have several books that include basic EXCP/CCW dasd programming, but nothing that I would consider 'deep' enough on ECKD programming. Some of the books I have are were good with CKD, but not ECKD. So, I am looking for suggestions for books that are designed to teach someone complex ECKD programming within the restrictions imposed by the OS. Tony Thigpen
Re: Subpool 0 Usage
Unsound code in a controlled environment is still unsound. But it's not my dog. Key 1-7 can MODESET to whatever it wants. There are lots of ways things can go pearwise. Defensive programming is your friend. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Binyamin Dissen <1773bcccb823-dmarc-requ...@listserv.uga.edu> Sent: Friday, July 12, 2024 7:15 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Subpool 0 Usage AC=1 is in a controlled environment, so no issue there. Key 1-7 cannot use user subpools. On Fri, 12 Jul 2024 10:43:45 +0000 Seymour J Metz wrote: :>Supervisor state, system (0-7) key or AC(1), not just supervisor state. :> :>Even paranoids have real enemies. :> :>-- :>Shmuel (Seymour J.) Metz :>http://mason.gmu.edu/~smetz3 :>??? ?? ??? :>?? ??? ?? :> :> :> :> :>From: IBM Mainframe Assembler List on behalf of Binyamin Dissen <1773bcccb823-dmarc-requ...@listserv.uga.edu> :>Sent: Friday, July 12, 2024 1:00 AM :>To: ASSEMBLER-LIST@LISTSERV.UGA.EDU :>Subject: Re: Subpool 0 Usage :> :>Well, that is referring to supervisor state code. And, strangely enough, :>subpool zero is slightly better than the other user subpools, as getmain SP=0 :>in key0 goes to SP=252 (key 0). :> :>But, yes, user key storage should not be used as work areas for supervisor :>state code. :> :>On Thu, 11 Jul 2024 18:25:14 -0500 Janko Kalinic :>wrote: :> :>:>https://secure-web.cisco.com/1aoQblQ8e1xmWfLRvzUdMBruORlC6YGST5EU9g_cDGJe0X09PzcBRwuivd4RYxokh6WOhLViyOIwSLaPY36ukg6yiQwbdgomfXS1BvK15SgmLitto-McpqCxmvDt072zln36swF95J-w16CisI4G7GspiMpUaDDR4pLpzgEvpWtTdkoleerNp_5xmmh-qNBcU6o_xkGGEsmB9AJ2Pf5TuOl1gV4Y0pled6gXbZ3I4igctrVBy_yEyI3njQ62yqFK3pr3GN3Mxz2vEEo8cA_joI6_DPC5offQOQF0p7fMnB6b3n2bamhgza9wlLkObKxEinWg1l7_OgWrVovUxe2R7zQxMF7SdAMi_K3CDtPX0w-8dwxkVEP_jsOeNcR0C6ApYUSEfKpaNXfum5RrVp-f8nFr3hrl-zh923-8Qns9yhLBRoDIduxvSw4EXbw7e1sbX/https%3A%2F%2Fconferences.gse.org.uk%2F2019%2Fpresentations%2FFN.pdf :>:> :>:> :>:>On Thu, Jul 11, 2024 at 6:08 PM Steve Smith wrote: :>:> :>:>> Well if you want to discuss, it would be helpful if you'd offer up what the :>:>> source was, and what it said, and maybe what you thought of it, instead of :>:>> just teasing out five words at a time. :>:>> :>:>> sas :>:>> :>:>> On Thu, Jul 11, 2024 at 4:04?PM Janko Kalinic :>:>> wrote: :>:>> :>:>> > It was from a 2019 GSE conference presentation. :>:>> > :>:>> > On Thu, Jul 11, 2024 at 3:01 PM Binyamin Dissen < :>:>> > 1773bcccb823-dmarc-requ...@listserv.uga.edu> wrote: :>:>> > :>:>> > > On Thu, 11 Jul 2024 14:14:02 -0500 Janko Kalinic < :>:>> > > the.pds.comm...@gmail.com> :>:>> > > wrote: :>:>> > > :>:>> > > :>I just read that you should NOT use Subpool 0 for anything if :>:>> possible. :>:>> > > :>Thoughts? :>:>> > > :>:>> > > Where did you read this? :>:>> > > :>:>> > > -- :>:>> > > Binyamin Dissen :>:>> > > http://secure-web.cisco.com/1XY2eL64x4C2WpoLzEaXzAfQi8uZhNr2O1HO5JU51wOIyDIJ-cUlLHDaDghI86MP18ZdeAYUKD_J1-_a5lOum_u15dnjj0lwn5ib8oFo9DgCNslCz5lK9y03-SqAfipq9k2XlzPOWLLd_n2HbH1wPCINZVLCLOSnffXe2OopL-3r4LhwF4aV1_gtFEMObAaWJoImH0SDPrAbHtqYUrnThaKypOmh-tTEmwWudESRbkICcKh3Pxequ69AhP048DaUd-WbzGnmL2Ha8k6iJOhsUKaSIbrbnEY6lsPXInyo06GL_aXPri1Yqi39CHyNZ9pGHJs0d_ZsLZBXi2eKUgt0Tcshn-XGREFZD5es_rK0lPrQIdwJNxXTGSfhsgkDnzRBVXFLAUtMEjegqyJhr4HHKaTsJkD4EZGTO98Lw_1eC6BooAzqp3X66nqZObSWaYgKs/http%3A%2F%2Fwww.dissensoftware.com :>:>> > > :>:>> > > Director, Dissen Software, Bar & Grill - Israel :>:>> > > :>:>> > :>:>> -- Binyamin Dissen http://secure-web.cisco.com/1X3JZrPv7CCT09-ROA8Rwb8lkRvPmfBXxFHucaJLrZei31RcyYiqTq9svUqCbkQP6MG3koIo3VVnQPUsNRAPZD-l5ew__iNGzSbqaGocn4ViQcMKfMD8LSk-igD2U36euOd9WI7j_LClOcawCykVUFAhmJ7TjufYd94pP5sOpKrwp-Oobhpj6QxWzfk417CqFWhSMicZnvGxm9HKSXRmgikgC9hpEFuOhd8KqNhVQH8gPFYqy-_hpBqP3lA4JCDizRtEzP8oYOvqfKmxaYqFXdzSAXSVrVEyuOzvf8u5WToVI5yJEsrDCsGyi7lTpFT5vy6Xtt2bcyUAc6i1ZlTIKGKXvrXdTCOWOgRHZdKrJSKUQKdll8LdyGY722LZT15X8zfgj0u2Q8yvp7FWZRTITwJPUGsrFb9yum5LcQ4AeYV6-RFEqlEuqpCpTol5P_h7l/http%3A%2F%2Fwww.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel
Re: Subpool 0 Usage
Supervisor state, system (0-7) key or AC(1), not just supervisor state. Even paranoids have real enemies. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Binyamin Dissen <1773bcccb823-dmarc-requ...@listserv.uga.edu> Sent: Friday, July 12, 2024 1:00 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Subpool 0 Usage Well, that is referring to supervisor state code. And, strangely enough, subpool zero is slightly better than the other user subpools, as getmain SP=0 in key0 goes to SP=252 (key 0). But, yes, user key storage should not be used as work areas for supervisor state code. On Thu, 11 Jul 2024 18:25:14 -0500 Janko Kalinic wrote: :>https://secure-web.cisco.com/1aoQblQ8e1xmWfLRvzUdMBruORlC6YGST5EU9g_cDGJe0X09PzcBRwuivd4RYxokh6WOhLViyOIwSLaPY36ukg6yiQwbdgomfXS1BvK15SgmLitto-McpqCxmvDt072zln36swF95J-w16CisI4G7GspiMpUaDDR4pLpzgEvpWtTdkoleerNp_5xmmh-qNBcU6o_xkGGEsmB9AJ2Pf5TuOl1gV4Y0pled6gXbZ3I4igctrVBy_yEyI3njQ62yqFK3pr3GN3Mxz2vEEo8cA_joI6_DPC5offQOQF0p7fMnB6b3n2bamhgza9wlLkObKxEinWg1l7_OgWrVovUxe2R7zQxMF7SdAMi_K3CDtPX0w-8dwxkVEP_jsOeNcR0C6ApYUSEfKpaNXfum5RrVp-f8nFr3hrl-zh923-8Qns9yhLBRoDIduxvSw4EXbw7e1sbX/https%3A%2F%2Fconferences.gse.org.uk%2F2019%2Fpresentations%2FFN.pdf :> :> :>On Thu, Jul 11, 2024 at 6:08 PM Steve Smith wrote: :> :>> Well if you want to discuss, it would be helpful if you'd offer up what the :>> source was, and what it said, and maybe what you thought of it, instead of :>> just teasing out five words at a time. :>> :>> sas :>> :>> On Thu, Jul 11, 2024 at 4:04?PM Janko Kalinic :>> wrote: :>> :>> > It was from a 2019 GSE conference presentation. :>> > :>> > On Thu, Jul 11, 2024 at 3:01 PM Binyamin Dissen < :>> > 1773bcccb823-dmarc-requ...@listserv.uga.edu> wrote: :>> > :>> > > On Thu, 11 Jul 2024 14:14:02 -0500 Janko Kalinic < :>> > > the.pds.comm...@gmail.com> :>> > > wrote: :>> > > :>> > > :>I just read that you should NOT use Subpool 0 for anything if :>> possible. :>> > > :>Thoughts? :>> > > :>> > > Where did you read this? :>> > > :>> > > -- :>> > > Binyamin Dissen :>> > > http://secure-web.cisco.com/1XY2eL64x4C2WpoLzEaXzAfQi8uZhNr2O1HO5JU51wOIyDIJ-cUlLHDaDghI86MP18ZdeAYUKD_J1-_a5lOum_u15dnjj0lwn5ib8oFo9DgCNslCz5lK9y03-SqAfipq9k2XlzPOWLLd_n2HbH1wPCINZVLCLOSnffXe2OopL-3r4LhwF4aV1_gtFEMObAaWJoImH0SDPrAbHtqYUrnThaKypOmh-tTEmwWudESRbkICcKh3Pxequ69AhP048DaUd-WbzGnmL2Ha8k6iJOhsUKaSIbrbnEY6lsPXInyo06GL_aXPri1Yqi39CHyNZ9pGHJs0d_ZsLZBXi2eKUgt0Tcshn-XGREFZD5es_rK0lPrQIdwJNxXTGSfhsgkDnzRBVXFLAUtMEjegqyJhr4HHKaTsJkD4EZGTO98Lw_1eC6BooAzqp3X66nqZObSWaYgKs/http%3A%2F%2Fwww.dissensoftware.com :>> > > :>> > > Director, Dissen Software, Bar & Grill - Israel :>> > > :>> > :>> -- Binyamin Dissen http://secure-web.cisco.com/1XY2eL64x4C2WpoLzEaXzAfQi8uZhNr2O1HO5JU51wOIyDIJ-cUlLHDaDghI86MP18ZdeAYUKD_J1-_a5lOum_u15dnjj0lwn5ib8oFo9DgCNslCz5lK9y03-SqAfipq9k2XlzPOWLLd_n2HbH1wPCINZVLCLOSnffXe2OopL-3r4LhwF4aV1_gtFEMObAaWJoImH0SDPrAbHtqYUrnThaKypOmh-tTEmwWudESRbkICcKh3Pxequ69AhP048DaUd-WbzGnmL2Ha8k6iJOhsUKaSIbrbnEY6lsPXInyo06GL_aXPri1Yqi39CHyNZ9pGHJs0d_ZsLZBXi2eKUgt0Tcshn-XGREFZD5es_rK0lPrQIdwJNxXTGSfhsgkDnzRBVXFLAUtMEjegqyJhr4HHKaTsJkD4EZGTO98Lw_1eC6BooAzqp3X66nqZObSWaYgKs/http%3A%2F%2Fwww.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel
Re: Subpool 0 Usage
Well, SP0 is shared by default. Then there's that whole business of converting SP0 to SP252. Of course, it depends on the context. Authorized? Subtasks? Multi-user? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Janko Kalinic Sent: Thursday, July 11, 2024 3:14 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Subpool 0 Usage I just read that you should NOT use Subpool 0 for anything if possible. Thoughts? Regards, John K
Re: Moving beyond S/370
Oldest machine is a z15, and of course it's not a technical question - "exotic"
is very much a matter of perception.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
עַם יִשְׂרָאֵל חַי
נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
From: IBM Mainframe Assembler List on behalf
of Charles Mills
Sent: Thursday, July 11, 2024 4:08 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Moving beyond S/370
Pick an exact ARCH level rather than just "nothing exotic."
Set your HLASM options to that level.
If HLASM flags nothing then there is your proof. (Whether your folks will
accept it or not is a psychology question, not a technology question. )
Charles
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Seymour J Metz
Sent: Thursday, July 11, 2024 11:59 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Moving beyond S/370
I'm dealingusing these won't creat a maintena with some code that currently
uses nothing newer than BAS/BASR. I've made some changes using a few newer
instructions, plus the SP macros from the toolkit. Any advice on convincing
reviewers that there's nothing exotic in these:
CLIJx
ELSE
ENDIF
EXRL
IF
J
JAS
LARL
LAY
NILL
TMLL
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
עַם יִשְׂרָאֵל חַי
נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
Re: Moving beyond S/370
I should have clarified that it's a mix of z15 and z16; nothing older. But both
the code and the training are older.
Of course, even with modernized training they're not going to cover everything
in a 2K+ page PoOps and a 500+ HLASM reference manual.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
עַם יִשְׂרָאֵל חַי
נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
From: IBM Mainframe Assembler List on behalf
of Ngan, Robert (DXC Luxoft)
Sent: Thursday, July 11, 2024 4:13 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Moving beyond S/370
CLIJx
I coded a macro that emulated this with CHI/Jx, back in the days where
customers may have had machines that didn't support these instructions. Failed
assembly on a real CLIJx if immediate was not in 0:255 range, or -128:127 for
CIJx, That horrendous CHI instruction I posted previously does assembly time
bounds checking that I had to add to fix this.
EXRL
Before the existence of TRAP type instructions, we used EX n,* to generate S0C3
abends with n in the 0:15 range to distinguish the various S0C3 generated
within a specific module.
EXRL n,* where n is non-zero may alter the EXRL instruction to something other
than EXRL, which may not abend and then fall thru to the next instruction.
LARL
Same deal with CLIJx, coded a macro to generate BASR reg,0 followed by AHI (or
2 AHI's) to emulate LARL for up to 32K (or 64K with 2 AHI's). Real LARL failed
assembly if offset was not even, but emulated version happily generated odd
offsets. Had to add code to make BASR second operand the expression 0-(offset
// 2)**2 which resolves to zero if offset is even (good), and -1 if it is odd
(bad, fails assembly).
TMLL
There is a subtle difference between the condition codes set by TMxx vs. TM, I
always need to check the POPS whenever I use TMxx for testing conditions other
than Z or O.
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Seymour J Metz
Sent: Thursday, July 11, 2024 13:59
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Moving beyond S/370
I'm dealingusing these won't creat a maintena with some code that currently
uses nothing newer than BAS/BASR. I've made some changes using a few newer
instructions, plus the SP macros from the toolkit. Any advice on convincing
reviewers that there's nothing exotic in these:
CLIJx
ELSE
ENDIF
EXRL
IF
J
JAS
LARL
LAY
NILL
TMLL
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
עַם יִשְׂרָאֵל חַי
נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
Moving beyond S/370
I'm dealingusing these won't creat a maintena with some code that currently
uses nothing newer than BAS/BASR. I've made some changes using a few newer
instructions, plus the SP macros from the toolkit. Any advice on convincing
reviewers that there's nothing exotic in these:
CLIJx
ELSE
ENDIF
EXRL
IF
J
JAS
LARL
LAY
NILL
TMLL
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
עַם יִשְׂרָאֵל חַי
נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
Re: Getting to CVT with FLAG(PAGE0)
What I suggested is that 1. The combination of legacy mapping macros and legacy code using those macros causes lots of PAGE0 warning. 2. Getting rid of the warnings requires a mass update. 3. A mass update is disruptive. 4. There is no easy fix. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Jonathan Scott Sent: Thursday, July 11, 2024 11:52 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Getting to CVT with FLAG(PAGE0) What are you suggesting as a "fix"? If a symbol such as CVTPTR has been defined with an EQU (as it has since OS/360 in the 1960s) it obviously cannot be redefined to make it relocatable (for example as a field in a DSECT) without triggering compatibility problems in existing code. Shmuel (Seymour J.) Metz writes: > The problem isn't in the assembler, but in the IBM mapping macros that have > EQU to absolute addresses. FLAG(, PAGE0) is doing what it is supposed to > do. > > For new code, there's no issue: use, e.g., CVTPTR(,0), FLCCVT. Jonathan Scott, HLASM IBM Hursley, UK
Re: Getting to CVT with FLAG(PAGE0)
The problem isn't in the assembler, but in the IBM mapping macros that have EQU to absolute addresses. FLAG(, PAGE0) is doing what it is supposed to do. For new code, there's no issue: use, e.g., CVTPTR(,0), FLCCVT. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Jonathan Scott Sent: Thursday, July 11, 2024 9:46 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Getting to CVT with FLAG(PAGE0) The purpose of the FLAG(PAGE0) option, added for HLASM 1.3 in 1998, is to warn users that they have coded an absolute expression for an address expression without any base or index register, so they will be implicitly referencing low storage, which might be accidental. If you do not want this warning, you can either add an explicit zero base register, making it clear that it is intentional, or you can turn off the warning (temporarily if necessary). The option originally only checked for a base register (either specified explicitly or via a USING with 0) but the processing was subsequently modified so that specifying a zero index register is also accepted as an indication that the reference is intentional. There is nothing requiring a "fix" in that respect. This warning has proved very useful in detecting accidents, for example when MVC is coded instead of MVI. That is why IBM macros have been modified to specify a zero base register, allowing users to turn on this option to check their own code without triggering extra warnings from IBM macro expansions. Shmuel (Seymour J.) Metz writes: > FSVO "told what to do"; an explanation of how to change each of the many > places that got the warning is a messy circumvention, not a fix. Jonathan Scott, HLASM IBM Hursley, UK
Re: Getting to CVT with FLAG(PAGE0)
FSVO "told what to do"; an explanation of how to change each of the many places that got the warning is a messy circumvention, not a fix. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Peter Relson Sent: Thursday, July 11, 2024 9:01 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Getting to CVT with FLAG(PAGE0) John K wrote: I had to turn off FLAG(PAGE0) for SWAREQ and TRKCALC. SWAREQ addressed this almost 15 years ago. TRKCALC was changed over 15 years ago. Please avoid using ancient versions of macros. Shmuel wrote: The obvious example is CVTPTR, which currently is an absolute EQU. Changing that to a DS A would break compatibility. Any ideas on how to resolve the PAGE0 issue while remaing compatible? Does it require an HLASM enhancement? This was in response to my post that told what to do. So I don't know why the question is being asked. Jonathan's post (and any number of macros) show what to do. Michael S wrote Does this mean: A. Yeah, it is going to give that warning. You have to consider each case to determine if the warning is valid or not. B. I'm coding it wrong. C. I'm coding it right but there's a better way to code it that won't trigger the error. I like my compiles and assembles to be clean: no warnings. So I'm not a fan of option A. I suppose I could put in a compile option to set FLAG(NOPAGE0) in programs that are getting to the CVT. I'd have chosen choice D: "You're coding it in a syntactically correct way that you have asked to be flagged in case you have some other case that was not intended". And I'd choose the action that would logically go with your choice C. Now that you have found 2 errors and 2 cases of CVTPTR, you'll fix the errors and I'd think (least work, and most effective) change your uses of CVTPTR to specify a base reg of 0. . Peter
Re: Getting to CVT with FLAG(PAGE0)
The obvious example is CVTPTR, which currently is an absolute EQU. Changing that to a DS A would break compatibility. Any ideas on how to resolve the PAGE0 issue while remaing compatible? Does it require an HLASM enhancement? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Peter Relson Sent: Wednesday, July 10, 2024 7:41 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Getting to CVT with FLAG(PAGE0) Turning off FLAG(PAGE0) is never necessary within your own code. Adding explicit base reg of 0 (not an index reg of 0) is the technique to indicate you know what you are doing and thus override the flag. You will see that within many macro expansions the need to reference the CVT without requiring the invoker to include the CVT. Maybe there are some macros that don't do that. If you find any in z/OS, let me know and maybe we can get that improved. Peter Relson z/OS Core Technology Design
Re: Provenance of term "yonder"?
I was asking about the use of the word as part of an instruction name. As far as I know, the word itself is very much in use, at least in the US. It's even in some songs. Off we go -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Martin Ward Sent: Monday, July 1, 2024 7:03 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Provenance of term "yonder"? yonder 1,1,1: at, in, or to that relatively distant place; over there yonder 1,2,1: being at a distance, either within view or as if within view The earliest known use of the word yonder is in the Middle English period (1150—1500). OED's earliest evidence for yonder is from before 1300. Some dialects in various parts of the United States still use the word yonder, usually to specify something that's within sight, and often with accompanied by a gesture pointing toward it. -- Martin Dr Martin Ward | Email: mar...@gkc.org.uk | http://secure-web.cisco.com/1FVD5pyQXw6nYDq-8s8S76wlDglFy0GB4lvMZ1ViOR-gegXG5hP43X7V-ntYCBI7FyhhvogU5nh3cuW062E0dIhlFRNw5h6oGf-Ai7Y8lmO3QecTqfBUzv-fV3nFCNGrW-3xNBbdXgW7eiOABoErp61pMs5QHg6f_aQ8COKW1nczi_doMcL_Wg60xMkhdmstoxqqdVeyEs94__u4S7Nf9OQ3ZndN2_U1bf-Go3zN08xkNGXNDpjr4TbBfb9rXPeQ2xOsgA-_vYJELEx1TDGWwYrgrfZpv-9rDq97DLNFShZITBiTZjsvrw4wJIV4t_vpgeYnDAob1LErZNxezUeG5swZBtLKD6mNSZ6blCtXKpIfa9FkpSGp8YcYGV76OEKB_Psf_kN2ALPMXgnOurYOL-qzzPHAVbUXe9smjAJKocoM/http%3A%2F%2Fwww.gkc.org.uk G.K.Chesterton site: http://secure-web.cisco.com/1ZE5IAy2AyhFvVH0r_qnchK2rgmGGcZCArAxZYAn8Xu6rlJ4SLJxAau4cgC3SqgT0Pq7XOZGmUFFzKLWD9nsWotekrYiVm06eVbBQyJrMNlG3akHfGo-VGhwyDRgJx8A72k9FheZQpKtSmk0Yh1LmSHjkZTWGaY124EqI83EqgHsXd34YTTMUfmovDV2fjsbGc1djm61IiEZ-OVcPFjjT0JPm2aBBxbFfisr_fEEN_L8MZrrqusfrmVXdmSP0F5CdRzDojT-R4vo1seRhAP3a0ki7gXbF6ta0FgGO2eQ9CHo4YftWuRFz5Mb-ghFA_Xd4LML3c5ifX8rD1Y7atBJ8Rqbnnp4i1bBKunKGSbcWZ5eqNcBc6zoiFm1yju2ScpIeCMsHXqfW77-xNoTYvvkbvu-adwxfsOgts8Gai9-VbZU/http%3A%2F%2Fwww.gkc.org.uk%2Fgkc | Erdos number: 4
Re: Provenance of term "yonder"?
On yonder hill there stands a creature Who she is I do not know I'll go and court her for her beauty She must answer yes or no -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Colin Paice Sent: Monday, July 1, 2024 6:55 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Provenance of term "yonder"? Good King Wenceslas first looked out, on the feast of Stephens... *Yonder* peasant, who is he? Where and what' his dwelling?" "Sire, he lives *a good league hence* Underneath the mountain Right against the forest fence By Saint Agnes' fountain On Mon, 1 Jul 2024 at 11:37, Seymour J Metz wrote: > Is the use of "yonder" to designate instructions with long displacements > official IBM nomenclature? What is its provenance? > > -- > Shmuel (Seymour J.) Metz > http://mason.gmu.edu/~smetz3 > עַם יִשְׂרָאֵל חַי > נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
Provenance of term "yonder"?
Is the use of "yonder" to designate instructions with long displacements official IBM nomenclature? What is its provenance? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
Re: Current list of extended mnemonics?
> are the old names What I really want is a single alphabetical table that contains all of the mnemonics for instructions valid on Z. That's in addition to the current table, not in place of it. > CONCS and DISCS Now that's a blast from the past! -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Jonathan Scott Sent: Tuesday, June 11, 2024 7:26 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Current list of extended mnemonics? Shmuel (Seymour J.) Metz writes: > A lot but not all :-( As far as I can see (using a program to compare appendix J with the table that I recently added to the HLASM Programmer's Guide) the only extended mnemonics omitted from Appendix J are the old names for instructions that have been renamed or extended: ADTR AXTR CDFBRCDGBRCDGTRCEFBRCEGBR CFDBRCFEBRCFXBRCGDBRCGDTRCGEBRCGXBR CGXTRCUTFUCUUTFCXFBRCXGBRCXGTRDDTR DXTR FIDBRFIEBRFIXBRLDXBRLEDBRLEXBR LRDR LRER MDTR ME MER MXTR PPNO SDTR SXTR TMH TML I also note that my table has two spurious "extended mnemonic" indications, in that the program to generate it found that mnemonics CONCS and DISCS within OPTABLE(UNI) are marked not to be used during disassembly but they have the same hex opcodes as LBEAR and STBEAR, so it assumes they were extended mnemonics for them. When new instructions were created for the same opcodes, it seemed unnecessary to remove CONCS and DISCS from the UNI table as that could in theory still be useful for reassembling ancient 370 code, but it has caused that weird side-effect. I don't want to update the table manually to fix that, but I may modify the program in future to spot that the opcode is no longer current so it cannot be an extended mnemonic for a current instruction. Jonathan Scott, HLASM IBM Hursley, UK
Re: Current list of extended mnemonics?
Yes! Thanks. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Paul Gilmartin <0014e0e4a59b-dmarc-requ...@listserv.uga.edu> Sent: Monday, June 10, 2024 11:34 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Current list of extended mnemonics? On 6/10/24 16:17, Seymour J Metz wrote: > A lot but not all :-( > > I normally download new PoOps editions as soon as I have a working URL. > . Is there anything useful here?: <https://www.ibm.com/docs/en/systems-hardware/linuxone/3932-AGL?topic=related-publications> <https://www.ibm.com/docs/sk/zvm/7.2?topic=programming-zvm-esaxc-principles-operation> -- gil
Re: Current list of extended mnemonics?
A lot but not all :-( I normally download new PoOps editions as soon as I have a working URL. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Dan Greiner Sent: Monday, June 10, 2024 5:20 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Current list of extended mnemonics? A list of extended mnemonics was added to the z/Architecture Principles of Operation (SA22-7832-13) in Appendix J. I found a copy at https://linux.mainframe.blog/zarchitecture-principles-of-operation/
Current list of extended mnemonics?
What is a URL for the most recent list of extended mnemonics for branch relative and branch relative long instructions? Thanks. As a side issue, will they be added to the reference summary? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
Fw: BXLE instruction
I meant to repost this last year but it slipped through the cracks. If anyone can help Bill with his registration issue I'd appreciate it. Also, if anybody has a machine-readable copy of the TR I'd love to see it. The trick in question relies on the use of the same odd register as the R1 and R3 in BXH, BXHG, BXLE, BXLEG, JXH, JXHG, JXLE and JXLEG. You can only test 30 consecutive bits with the 32-bit version and 62 with the 64-bit version; the high and low bits should be zero. The code, arbitrarily picking GR 1 as the odd register, looks something like: L R1,STATUS IF(BXH,R15,r15) action 1 ENDIF ... IF(BXH,R15,r15) action 30 ENDIF ... STATUS DCA.1(0,flag1,...,flag31,0) Where the test is a BXH or BXLE depending on which way you want to test. If you have to work it out with pencil and paper in order to understand what's going on, welcome to the club. I thought that it was slick the first time I saw it, and I still think so. I think it would be a good example in PoOps. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: William Collier Sent: Wednesday, November 2, 2022 11:27 AM To: Seymour J Metz Subject: BXLE instruction To: Seymour J Metz mailto:sme...@gmu.edu>> Hi, Last night I enjoyed reading your comment on the IBM-MAIN listserv: The slickest thing that I saw in OS/360 was code testing successive bits using BXH and BXLE. I would like to respond with the note below. I have followed (I believe) all the directions for creating a password in order to be allowed to post a note responding to your note. It hasn't worked (yet). Would you, in the interest of timeliness, be willing to post the note below on my behalf? If not, that's OK. I will figure it out. Bill Collier == Re: End of several eras Back in 1965 IBM Poughkeepsie our job was to write an operating system for System/360 which would fit into 1K bytes (sic) of an 8k byte machine. I figured out how to use a BXLE instruction to both test and advance a bit string in a register. It saved us maybe 30-some bytes. I described this in IBM TR 00.1412-1, June 22, 1966. Thank you, Seymour Metz, for your note reminding us of the fun we had in those days. Bill Collier coll...@acm.org<mailto:coll...@acm.org>
Re: BXLE usage assistance
True; make that AL2 except where HW alignment is required. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of g...@altiboxmail.no Sent: Friday, June 7, 2024 12:48 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: BXLE usage assistance Note that an Y type without explicit length specified will have halfword alignment, so there may by a pad byte between an entry string and the next length field. That will make it more complicated (but not impossible) to advance to the next entry based on the length fields. Gunnar -Original Message- From: IBM Mainframe Assembler List On Behalf Of Seymour J Metz Sent: Friday, June 7, 2024 6:24 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Fw: BXLE usage assistance Metz's Law: You may be good at arithmetic but the assembler is better: let it do the calculations. LAR9,TEND ... TABLE1 DS0F DCY(TLEN) DCY(L'E1) E1 DCCL14'AA' DCY(L'E2) E2 DCCL15'BBB' ... TEND EQU *-1 TLEN EQU *-TABLE1 -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of g...@altiboxmail.no Sent: Friday, June 7, 2024 12:02 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: BXLE usage assistance Note that LAR9,TABLE1+2 ADDRESS OF BEGINNING OF TABLE AHR9,TABLE1 CALC ADDR OF END OF TABLE will not establish the end of table suitable for the BXLE instruction. The table coded in the example below has a wrong total length (XL2'008F'), you have forgotten to include the elements length fields. Also the calculated end of table must be at least 1 byte before the end, otherwise BXLE will not stop at the end (as BXL would have done, but that instruction doesn't exist). It is essential that a correct compare value for BXLE is established, otherwise it may not work as intended when the search is for an entry not present in the table. Gunnar -Original Message- From: IBM Mainframe Assembler List On Behalf Of Mark Young Sent: Tuesday, June 4, 2024 7:37 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: BXLE usage assistance Thanks for all the replies. See the code sample below. I'm getting stuck trying to get the length for the next table entry into R8 so the BXLE instruction loop the correct length. Let me know if I'm on the correct path, or I'm in never never land. Also, the --->>> <<<--- is where I think I'm getting stuck. TESTBXLE CSECT , TESTBXLE AMODE 31 TESTBXLE RMODE ANY SAVE (14,12),,TESTBXLE*&SYSDATE*&SYSTIME BALR R12,0 R12 - BASE REGISTER USING *,R12 ESTABLISH ADDRESSABILITY STR13,SAVEAREA+4 SAVEAREA LAR13,SAVEAREAPOINTERS * CHKOPTS1 LAR7,TABLE1+4 ADDRESS OF FIRST ELEMENT LHR8,TABLE1+2 LENGTH OF TABLE ENTRY LAR9,TABLE1+2 ADDRESS OF BEGINNING OF TABLE AHR9,TABLE1 CALC ADDR OF END OF TABLE LOOP1CLC 0(9,R7),=C'F' BEFOUND ENTRY FOUND = RC=0 --->>> LHR8,0(2,R7) <<<--- POINT TO LENGTH OF NEXT ENTRY BXLE R7,R8,LOOP1 LOOPING UNTIL OPT FOUND B NOTFND ENRTY NOT FOUND ? RC=8 * FOUNDL R13,SAVEAREA+4 RETURN (14,12),RC=0 * NOTFND L R13,SAVEAREA+4 RETURN (14,12),RC=8 * PRINT NOGEN YREGS SAVEAREA DS18F TABLE1 DS0F DCXL2'008F' DCXL2'000E',CL14'AA' DCXL2'000F',CL15'BBB' DCXL2'0011',CL17'C' DCXL2'000D',CL13'D' DCXL2'0017',CL23'EEE' DCXL2'0009',CL9'F' DCXL2'0013',CL19'GGG' DCXL2'0019',CL25'H' DCXL2'0008',CL8'' END TESTBXLE Thanks, Mark. 8c
Fw: BXLE usage assistance
Metz's Law: You may be good at arithmetic but the assembler is better: let it do the calculations. LAR9,TEND ... TABLE1 DS0F DCY(TLEN) DCY(L'E1) E1 DCCL14'AA' DCY(L'E2) E2 DCCL15'BBB' ... TEND EQU *-1 TLEN EQU *-TABLE1 -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of g...@altiboxmail.no Sent: Friday, June 7, 2024 12:02 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: BXLE usage assistance Note that LAR9,TABLE1+2 ADDRESS OF BEGINNING OF TABLE AHR9,TABLE1 CALC ADDR OF END OF TABLE will not establish the end of table suitable for the BXLE instruction. The table coded in the example below has a wrong total length (XL2'008F'), you have forgotten to include the elements length fields. Also the calculated end of table must be at least 1 byte before the end, otherwise BXLE will not stop at the end (as BXL would have done, but that instruction doesn't exist). It is essential that a correct compare value for BXLE is established, otherwise it may not work as intended when the search is for an entry not present in the table. Gunnar -Original Message- From: IBM Mainframe Assembler List On Behalf Of Mark Young Sent: Tuesday, June 4, 2024 7:37 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: BXLE usage assistance Thanks for all the replies. See the code sample below. I'm getting stuck trying to get the length for the next table entry into R8 so the BXLE instruction loop the correct length. Let me know if I'm on the correct path, or I'm in never never land. Also, the --->>> <<<--- is where I think I'm getting stuck. TESTBXLE CSECT , TESTBXLE AMODE 31 TESTBXLE RMODE ANY SAVE (14,12),,TESTBXLE*&SYSDATE*&SYSTIME BALR R12,0 R12 - BASE REGISTER USING *,R12 ESTABLISH ADDRESSABILITY STR13,SAVEAREA+4 SAVEAREA LAR13,SAVEAREAPOINTERS * CHKOPTS1 LAR7,TABLE1+4 ADDRESS OF FIRST ELEMENT LHR8,TABLE1+2 LENGTH OF TABLE ENTRY LAR9,TABLE1+2 ADDRESS OF BEGINNING OF TABLE AHR9,TABLE1 CALC ADDR OF END OF TABLE LOOP1CLC 0(9,R7),=C'F' BEFOUND ENTRY FOUND = RC=0 --->>> LHR8,0(2,R7) <<<--- POINT TO LENGTH OF NEXT ENTRY BXLE R7,R8,LOOP1 LOOPING UNTIL OPT FOUND B NOTFND ENRTY NOT FOUND ? RC=8 * FOUNDL R13,SAVEAREA+4 RETURN (14,12),RC=0 * NOTFND L R13,SAVEAREA+4 RETURN (14,12),RC=8 * PRINT NOGEN YREGS SAVEAREA DS18F TABLE1 DS0F DCXL2'008F' DCXL2'000E',CL14'AA' DCXL2'000F',CL15'BBB' DCXL2'0011',CL17'C' DCXL2'000D',CL13'D' DCXL2'0017',CL23'EEE' DCXL2'0009',CL9'F' DCXL2'0013',CL19'GGG' DCXL2'0019',CL25'H' DCXL2'0008',CL8'' END TESTBXLE Thanks, Mark. 8c
Re: Toolkit support for compare and jump?
I agree that the macros should be in the base, but even without them HLASM has features that, IMHO, justify the term high level. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Schmitt, Michael Sent: Friday, June 7, 2024 10:32 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Toolkit support for compare and jump? My opinion is that the structured programming macros should be included with HLASM, at no extra cost. For four reasons: 1. How can you call it High Level assembler without the macros? 2. The macro library is already a prerequisite for other IBM products, such as IMS. 3. Having the macros part of HLASM would standardize them. As it is now, there's the IBM macros and there's other versions from other sources, which may not be consistent in syntax and implementation. 4. We can't code using the macros as it is now, because while perhaps we have a license *today*, we can't know that we'll always have the license. I've already had to rewrite a large assembler program to remove the macros, because they were licensed when I wrote it but then the license was dropped. So I learned my lesson: never use the macros. -Original Message- From: IBM Mainframe Assembler List On Behalf Of Jonathan Scott Sent: Friday, June 7, 2024 8:23 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Toolkit support for compare and jump? Pieter Wiid writes: > Found a bug in this implementation: > ... 1686 DOEXIT CIJ,R15,NE,0 > ... 1696+ CIJ R15,0 > ** ASMA175S Delimiter error, expected comma - This example appears to be simply due to using an old level of the HLASM Toolkit Structured Programming Macro macro library which does not include the Compare-and-Branch support. However, the example included with the case does show a problem when DOEXIT specifies a compare-and-branch instruction followed by a logical OR condition, which is that an undefined label is used for the branch. > I raised case TS016361097, but IBM are being obstructive on entitlement. Unlike HLASM, which is included as standard with z/OS, the HLASM Toolkit, which includes the Structured Programming Macros and ASMIDF, is an optional priced feature, which must be licensed separately. So an appropriate license needs to be located. Personally, I've always felt that we should encourage customers to report bugs and also that there should be no charge to report a problem if you do not actually need a fix. I would even like some way to reward customers who provide helpful information about problems. However, that's not how IBM works. In this case, the team are now aware of the problem, and are quite likely to look into fixing it anyway, but it is always easier for us to prioritise work on a fix if it is associated with a valid customer case. Jonathan Scott, HLASM IBM Hursley, UK
Re: BXLE usage assistance
? Please show the code you mean. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Peter Sylvester Sent: Thursday, June 6, 2024 6:07 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: BXLE usage assistance Hi, before doing the CLC, I might have put the length of the C'' into reg 0, and then first make a CR 0,7 Best On 05/06/2024 23:17, Peter Vels wrote: > Hi Shmuel, > > Your code is much better than mine (thanks!), however, you still need > > LAR7,2(R7) > > to skip past the length field in the LOOP. R8 contains the correct length, > but doesn't cater for the length field itself. > > CHKOPTS1 LAR7,TABLE1+2 > LAR9,TABLE1+2 > AHR9,TABLE1 > > LOOP1LHR8,0(R7) > CLC 2(9,R7),=C'F' > JEFOUND > LAR7,2(R7) > BXLE R7,R8,LOOP1 > > Peter > > On Thu, 6 Jun 2024 at 03:23, Seymour J Metz wrote: > >> Yes, 2(9,R7) or a symbol in the DSECT following the length field. There's >> probably processing code that has to be adjusted as well. >> >> From: IBM Mainframe Assembler List on >> behalf of Gary Weinhold >> >> I believe the CLC would be CLC 2(9,R7) although in actual code it would >> probably be executed with Rn containing R8 - 1. >> >> On 2024-06-05 11:02 a.m., Seymour J Metz wrote: >>> What's wrong with >>> >>> CHKOPTS1 LAR7,TABLE1+2 ADDRESS OF FIRST ELEMENT >>>LAR9,TABLE1+2 ADDRESS OF BEGINNING OF TABLE >>>AHR9,TABLE1 CALC ADDR OF END OF TABLE >>> >>> LOOP1 LHR8,0(R7) entry length for BXLE >>>CLC 0(9,R7),=C'F' >>>JEFOUND ENTRY FOUND = RC=0 >>>BXLE R7,R8,LOOP1 LOOPING UNTIL OPT FOUND >>> >> >>
Re: BXLE usage assistance
Whoops! Thanks for catching that. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Peter Vels Sent: Wednesday, June 5, 2024 5:17 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: BXLE usage assistance Hi Shmuel, Your code is much better than mine (thanks!), however, you still need LAR7,2(R7) to skip past the length field in the LOOP. R8 contains the correct length, but doesn't cater for the length field itself. CHKOPTS1 LAR7,TABLE1+2 LAR9,TABLE1+2 AHR9,TABLE1 LOOP1LHR8,0(R7) CLC 2(9,R7),=C'F' JEFOUND LAR7,2(R7) BXLE R7,R8,LOOP1 Peter On Thu, 6 Jun 2024 at 03:23, Seymour J Metz wrote: > Yes, 2(9,R7) or a symbol in the DSECT following the length field. There's > probably processing code that has to be adjusted as well. > > From: IBM Mainframe Assembler List on > behalf of Gary Weinhold > > I believe the CLC would be CLC 2(9,R7) although in actual code it would > probably be executed with Rn containing R8 - 1. > > On 2024-06-05 11:02 a.m., Seymour J Metz wrote: > > > > What's wrong with > > > > CHKOPTS1 LAR7,TABLE1+2 ADDRESS OF FIRST ELEMENT > > LAR9,TABLE1+2 ADDRESS OF BEGINNING OF TABLE > > AHR9,TABLE1 CALC ADDR OF END OF TABLE > > > > LOOP1 LHR8,0(R7) entry length for BXLE > > CLC 0(9,R7),=C'F' > > JEFOUND ENTRY FOUND = RC=0 > > BXLE R7,R8,LOOP1 LOOPING UNTIL OPT FOUND > > > > >
Re: Toolkit CC codes NE and NEQ.
Thanks. The difficult we see quickly, the obvious takes longer :-( -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Jonathan Scott Sent: Wednesday, June 5, 2024 4:58 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Toolkit CC codes NE and NEQ. Try the correct order for a comparison: (CLIJ,FOO,NE,BAR) Shmuel (Seymour J.) Metz writes: > IF(CLIJ,FOO,BAR,NE) > > gets an undefined symbol error on NE. Jonathan Scott, HLASM IBM Hursley, UK
Toolkit CC codes NE and NEQ.
According to the Toolkit documentation, NE is a valid condition code for the IF macro. However, IF(CLIJ,FOO,BAR,NE) gets an undefined symbol error on NE. I tried NEQ, with the same result. I don't want to specify it as 7 or tack on a NOT. Is this a bug or a documentation error? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
Re: BXLE usage assistance
Yes, 2(9,R7) or a symbol in the DSECT following the length field. There's probably processing code that has to be adjusted as well. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Gary Weinhold Sent: Wednesday, June 5, 2024 11:35 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: BXLE usage assistance I believe the CLC would be CLC 2(9,R7) although in actual code it would probably be executed with Rn containing R8 - 1. On 2024-06-05 11:02 a.m., Seymour J Metz wrote: > EXTERNAL EMAIL ALERT This email originated from outside of DataKinetics. Do > not click links or open any attachments unless you both recognize the sender, > and know the content is safe. > > What's wrong with > > CHKOPTS1 LAR7,TABLE1+2 ADDRESS OF FIRST ELEMENT > LAR9,TABLE1+2 ADDRESS OF BEGINNING OF TABLE > AHR9,TABLE1 CALC ADDR OF END OF TABLE > > LOOP1 LHR8,0(R7) entry length for BXLE > CLC 0(9,R7),=C'F' > JEFOUND ENTRY FOUND = RC=0 > BXLE R7,R8,LOOP1 LOOPING UNTIL OPT FOUND > > Specifying the length field on your USING? > > -- > Shmuel (Seymour J.) Metz > http://mason.gmu.edu/~smetz3 > עַם יִשְׂרָאֵל חַי > נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר > > Gary Weinhold Senior Application Architect DATAKINETICS | Data Performance & Optimization Phone:+1.613.523.5500 x216 Email: weinh...@dkl.com Visit us online at http://secure-web.cisco.com/1JysorrktMfOHAt2bFtGWitJTNXOJwvUUFJtTct2kSfx5reORmUFO9dnlbA7iknRRK-N86Rmi-TYyRSIKmWH3dphjxeN8jtexggQah-kHgY0DjvlBSwJM8mBB4lTUoO3ZXDzvd0yPJpaNPrIIi18fK5DZWTHJbVfn-4IIRCH1F70ASjKDwWuLMGol2e-rJDZNvn1xnegmXMiyqfqXjf4TdiYAsthXRObMBk8skhdPS4DyLzZsKHwIgU24vMcDzYS5BPuNXnFLXhXNNuuorX3rkQvpZpW-bSdM5Uq-J4Rht6csVnbiQPXi1IZVEuh9zRzFdmRQL7ktQ65WhJ9UW0p_7gGXsRDCygTXa5ULfa3VPfTHBto4-2jZafWqwCn-lNHQ6dNXntMwIH_bBik4t3eP3HdtIaGMOC6LopmRMe3BQvc/http%3A%2F%2Fwww.DKL.com E-mail Notification: The information contained in this email and any attachments is confidential and may be subject to copyright or other intellectual property protection. If you are not the intended recipient, you are not authorized to use or disclose this information, and we request that you notify us by reply mail or telephone and delete the original message from your mail system.
Re: BXLE usage assistance
What's wrong with CHKOPTS1 LAR7,TABLE1+2 ADDRESS OF FIRST ELEMENT LAR9,TABLE1+2 ADDRESS OF BEGINNING OF TABLE AHR9,TABLE1 CALC ADDR OF END OF TABLE LOOP1 LHR8,0(R7) entry length for BXLE CLC 0(9,R7),=C'F' JEFOUND ENTRY FOUND = RC=0 BXLE R7,R8,LOOP1 LOOPING UNTIL OPT FOUND Specifying the length field on your USING? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Peter Vels Sent: Wednesday, June 5, 2024 3:42 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: BXLE usage assistance Hi Mark, Try this: CHKOPTS1 LAR7,TABLE1+4 ADDRESS OF FIRST ELEMENT LHR8,TABLE1+2 LENGTH OF TABLE ENTRY LRR6,R8 SAVE R8 FOR LATER LAR9,TABLE1+2 ADDRESS OF BEGINNING OF TABLE AHR9,TABLE1 CALC ADDR OF END OF TABLE LOOP1CLC 0(9,R7),=C'F' JEFOUND ENTRY FOUND = RC=0 * --->>> LHR8,0(2,R7) <<<--- POINT TO LENGTH OF NEXT ENTRY LRR8,R6 RESTORE R8 LHR6,0(R8,R7) PUT THE NEXT LENGTH INTO R6 LAR7,2(R7)SKIP OVER THE LENGTH FIELD BXLE R7,R8,LOOP1 LOOPING UNTIL OPT FOUND I don't like that I used an extra register, R6, so I'm hoping someone can improve it. Peter On Wed, 5 Jun 2024 at 03:58, Mike Shaw wrote: > Mark, > > You are coding a length (the 2) in the 2nd operand of your LH > instruction...that 2 is being used by the machine as register 2. LH always > loads two bytes. > > Mike Shaw > MVS/QuickRef Support > Chisoft > > > On Tue, Jun 4, 2024, 1:38 PM Mark Young wrote: > > > Thanks for all the replies. See the code sample below. I'm getting > stuck > > trying to get the length for the next table entry into R8 so the BXLE > > instruction loop the correct length. Let me know if I'm on the correct > > path, or I'm in never never land. Also, the --->>> <<<--- is > > where I think I'm getting stuck. > > > > TESTBXLE CSECT , > > TESTBXLE AMODE 31 > > TESTBXLE RMODE ANY > > SAVE (14,12),,TESTBXLE*&SYSDATE*&SYSTIME > > BALR R12,0 R12 - BASE REGISTER > > USING *,R12 ESTABLISH ADDRESSABILITY > > STR13,SAVEAREA+4 SAVEAREA > > LAR13,SAVEAREAPOINTERS > > * > > CHKOPTS1 LAR7,TABLE1+4 ADDRESS OF FIRST ELEMENT > > LHR8,TABLE1+2 LENGTH OF TABLE ENTRY > > LAR9,TABLE1+2 ADDRESS OF BEGINNING OF TABLE > > AHR9,TABLE1 CALC ADDR OF END OF TABLE > > LOOP1CLC 0(9,R7),=C'F' > > BEFOUND ENTRY FOUND = RC=0 > > --->>> LHR8,0(2,R7) <<<--- POINT TO LENGTH OF NEXT ENTRY > > BXLE R7,R8,LOOP1 LOOPING UNTIL OPT FOUND > > B NOTFND ENRTY NOT FOUND ? RC=8 > > * > > FOUNDL R13,SAVEAREA+4 > > RETURN (14,12),RC=0 > > * > > NOTFND L R13,SAVEAREA+4 > > RETURN (14,12),RC=8 > > * > > PRINT NOGEN > > YREGS > > SAVEAREA DS18F > > TABLE1 DS0F > > DCXL2'008F' > > DCXL2'000E',CL14'AA' > > DCXL2'000F',CL15'BBB' > > DCXL2'0011',CL17'C' > > DCXL2'000D',CL13'D' > > DCXL2'0017',CL23'EEE' > > DCXL2'0009',CL9'F' > > DCXL2'0013',CL19'GGG' > > DCXL2'0019',CL25'H' > > DCXL2'0008',CL8'' > > END TESTBXLE > > > > > > Thanks, > > Mark. > > >
Re: The best way to check any virtual address
The real problem is the time of check to time of use window, Putting your code in the scope of a recovery service and using, e.g., MVCK, resolves that issue. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Dan Greiner Sent: Monday, June 3, 2024 11:29 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: The best way to check any virtual address Virtual-storage accessibility is an issue about which the Systems Architecture team was often asked, by customers, ISVs, and IBM developers. At a SHARE presentation in 2009, I dragged out my FrameMaker instruction template and designed the IS IT SAFE (IIS) instruction in about 5 minutes. IIS was a simple RXY-format instruction where the second operand designated a storage location, and the first operand was ignored. The condition code was set as follows: CC0 Storage is accessible for both fetch and store. CC1 Storage is accessible for fetch only CC2 Storage is not accessible The most important part of the instruction description was the programming note: This instruction is absolutely useless! Why? Because the CPU is clueless as to whether a dynamic-address-translation (DAT) exception is due to the virtual address being paged out by the OS, or a DAT exception is due to the virtual address being totally bogus. Only the OS can tell you that correctly. I also recall that various OSes have service routines to provide such information, but I don't recall what they are. Part of the initial design criteria for transactional execution was to efficiently provide a means by which a program could speculatively touch a virtual address, and if the transaction aborted, then pretend you didn't mean it (... my bad ... do over). Regrettably, in their finite wisdom, IBM has put the coffin nail into nonconstrained TX.
Re: BXLE usage assistance
Not quite. Using array + total length in the odd register would give you an extra iteration with garbage. Normal practice is to point it at the last entry, but since the entries are variable length, just cut it back by 1 and all will be cool. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of g...@altiboxmail.no Sent: Wednesday, May 29, 2024 6:43 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: BXLE usage assistance The BXLE will work in this case, it is clearly explained in the Principles of Operation manual. End the loop with BXLE R1,R3,LOOP R3 must be an even register, then R3 shall hold the increment and R3+1 the compare value. Before the LOOP set R3+1 = array + total length, and R1 = start of first entry (the length field). Before the end of LOOP set R3 = the entry length The BXLE will then update R1 with the entry length and point to the next entry, and branch back to LOOP. It will fall thru when the content of R1 reaches the content of R3+1. Gunnar -Original Message- From: IBM Mainframe Assembler List On Behalf Of Mark Sent: Wednesday, May 29, 2024 9:03 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: BXLE usage assistance Hello, I'm writing an exit where I have to scan through an array of variable length entries in a table where the format is as below (all the entires are readable characters) First 2 bytes = total length of array in hex then 2 bytes for length of first entry in hex First Entry in table 2 bytes for length of 2nd entry in hex 2nd entry in table 2 bytes for length of 3rd entry in hex 3rd entry in table. repeats until end of array. I'm thinking a BXLE will work, but getting stuck on exactly how to code it. any help is greatly appriciated. Thanks, Mark. .
Re: BXLE usage assistance
And JAS, JCT, JXH. Just don't drop the latest PoOps on your foot. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Gary Weinhold Sent: Wednesday, May 29, 2024 5:26 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: BXLE usage assistance I believe there's a branch relative version too; JXLE. On 2024-05-29 4:57 p.m., Seymour J Metz wrote: > EXTERNAL EMAIL ALERT This email originated from outside of DataKinetics. Do > not click links or open any attachments unless you both recognize the sender, > and know the content is safe. > > LHRODD,ARRAYLEN > LARODD,ARRAYFIRST-1(RODD) > LARPTR,ARRAYFIRST > LOOP LHREVEN,0(,RPTR) > ... > BXLE RPTR,REVEN,LOOP > > where REVEN,RODD is a register pair. > > -- > Shmuel (Seymour J.) Metz > http://mason.gmu.edu/~smetz3 > עַם יִשְׂרָאֵל חַי > נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר > > > Gary Weinhold Senior Application Architect DATAKINETICS | Data Performance & Optimization Phone:+1.613.523.5500 x216 Email: weinh...@dkl.com Visit us online at http://secure-web.cisco.com/1xnLNEBq2i3Ufko0q16XEuWW-JzfLYUeV3c9d1bA6ZnGQ5dqFaInkhhvjy7jft4qhDf37gJT6BEGpjkjiVbBBs9NxcWQ0BzKxJn0ewFbH8QB-o5KB7nohE4m-5D0YNOdatYa3DdCk3vWvlWqt_s5hx7Dsm-n2Cuo4OV3BVsAXFZFzUnSsHvpPooMk5lM6hyWMOOxDABezbi08DD21ZEmgKbbb1H2t1Tr4an31nmift3hWE9oMbkvVpjblP0s2f73FP1hSMgp3k8VWI4QkW5o01j_xdkfWLmSsnNtpAisJGQ9YS_cqcQBoVk63zFb5_1Sw8dPx-d7TScGb_FgV230IgT1EpqKaLs3ThvvcUQutG1YC7zO3tPltfRI4AcJrGhjW5JWFgpYS5Asok5AL2d57z52Kc0iU8kIfDb7jSMjsFbA/http%3A%2F%2Fwww.DKL.com E-mail Notification: The information contained in this email and any attachments is confidential and may be subject to copyright or other intellectual property protection. If you are not the intended recipient, you are not authorized to use or disclose this information, and we request that you notify us by reply mail or telephone and delete the original message from your mail system. From: IBM Mainframe Assembler List on behalf of Mark<176dcd91c5b1-dmarc-requ...@listserv.uga.edu> > Sent: Wednesday, May 29, 2024 3:03 PM > To:ASSEMBLER-LIST@LISTSERV.UGA.EDU > Subject: BXLE usage assistance > > Hello, > > I'm writing an exit where I have to scan through an array of variable length > entries in a table where the format is as below (all the entires are readable > characters) > > First 2 bytes = total length of array in hex > then > 2 bytes for length of first entry in hex > First Entry in table > 2 bytes for length of 2nd entry in hex > 2nd entry in table > 2 bytes for length of 3rd entry in hex > 3rd entry in table. > repeats until end of array. > > I'm thinking a BXLE will work, but getting stuck on exactly how to code it. > any help is greatly appriciated. > > Thanks, > Mark. > .
Re: BXLE usage assistance
LHRODD,ARRAYLEN LARODD,ARRAYFIRST-1(RODD) LARPTR,ARRAYFIRST LOOP LHREVEN,0(,RPTR) ... BXLE RPTR,REVEN,LOOP where REVEN,RODD is a register pair. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Mark <176dcd91c5b1-dmarc-requ...@listserv.uga.edu> Sent: Wednesday, May 29, 2024 3:03 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: BXLE usage assistance Hello, I'm writing an exit where I have to scan through an array of variable length entries in a table where the format is as below (all the entires are readable characters) First 2 bytes = total length of array in hex then 2 bytes for length of first entry in hex First Entry in table 2 bytes for length of 2nd entry in hex 2nd entry in table 2 bytes for length of 3rd entry in hex 3rd entry in table. repeats until end of array. I'm thinking a BXLE will work, but getting stuck on exactly how to code it. any help is greatly appriciated. Thanks, Mark. .
Re: Toolkit support for compare and jump?
Thanks. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Jonathan Scott Sent: Wednesday, May 29, 2024 10:03 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Toolkit support for compare and jump? Shipped in 2020: https://www.ibm.com/support/pages/apar/PH31153 Jonathan Scott, HLASM IBM Hursley, UK
Toolkit support for compare and jump?
Are there any announced plans for the HLASM Toolkit to exploit the compare and branch (relative) instructions on a new form of IF et al? Something like: IF(CLIJ,R1,X'F00',E) IF(CLIJE,R1,X'F00') -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
Re: Changing BRANCH to JUMP...
I would assume that your BK is BC 3, in which case the appropriate translation in BRC 3. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Martin Trübner <1237eee49f7e-dmarc-requ...@listserv.uga.edu> Sent: Friday, May 24, 2024 11:34 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Changing BRANCH to JUMP... Dave, BK never existed- could this be an inhouse macro? What is the condition that is in the corresponding 47instruction? or- how would you code the nn in this: BC nn,label Martin On 24.05.24 17:16, David Clark wrote: > Some time back I changed my logical construct macro sets to use > the relative forms of branching. That has been working fine as I > reassemble things. But today I came across one that failed to resolve > successfully--but I can't find anything about it in the manuals I have. It > was a branch on carry (BK) mnemonic and, apparently, JK is not recognized > as such. I presume this is one of the exceptions to simply replacing B > with J? Help?!? ;-) > > Sincerely, > > Dave Clark > -- > int.ext: 91078 > direct: (937) 531-6378 > home: (937) 751-3300 > > Winsupply Group Services > 3110 Kettering Boulevard > Dayton, Ohio 45439 USA > (937) 294-5331
Re: WHERE in debugger?
Alas, the IRS dropped Z/XDC well before I arrived. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Robert Shimizu Sent: Friday, May 17, 2024 5:19 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: WHERE in debugger? Hello Shmuel: Good afternoon. I lurk on the Assembler list and watch your posts go by. z/XDC can do all you're looking for and much, much more. That said, it's a professional engineering tool and it costs money. Sincerely, Bob On 5/17/24 2:11 PM, Seymour J Metz wrote: > Do the IDF and z/OS Debugger have commands given an address will return > return a load module, csect and symbol for that address? What about storage > mapped by a dsect? > > -- > Shmuel (Seymour J.) Metz > http://mason.gmu.edu/~smetz3 > עַם יִשְׂרָאֵל חַי > נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר > -- Robert W. Shimizu Partner, Concierge ColeSoft Marketing, Inc. (800) 932-5150 (928) 771-2003 Check out our latest offering! dump/XDC is HERE! <https://www.colesoft.com/solutions/dumpxdc/overview-2> bshim...@colesoft.com <mailto:bshim...@colesoft.com> http://www.colesoft.com/ <http://www.colesoft.com/>
WHERE in debugger?
Do the IDF and z/OS Debugger have commands given an address will return return a load module, csect and symbol for that address? What about storage mapped by a dsect? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
Re: Relation between ASMLANGX and EQALANGX
That's a third option; TEST comes with z/OS and they are licensed for the other two. But is there a preference between z/OS Debugger and HLASM Interactive Debug Facility (IDF), which look very similar to each other and which are both available at the IRS? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Joseph Reichman Sent: Thursday, May 16, 2024 11:53 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Relation between ASMLANGX and EQALANGX Seymour when I was I. Development they encouraged me to stop using TSO TEST and use to debug tool let me look at my assembly JCL On Thu, May 16, 2024 at 11:51 AM Seymour J Metz wrote: > The HLASM Toolkit includes ASMLANGX and the z/OS debugger includes > EQALANGX; are their outputs interchangeable, that is, can ASMIDF, ASMIDFB > and EQANMDBG use the output from either, or does ASMIDF have to use the > output from ASMLANGX and EQANMDBG have to use the output of EQALANGX? > > -- > Shmuel (Seymour J.) Metz > http://mason.gmu.edu/~smetz3 > עַם יִשְׂרָאֵל חַי > נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
Relation between ASMLANGX and EQALANGX
The HLASM Toolkit includes ASMLANGX and the z/OS debugger includes EQALANGX; are their outputs interchangeable, that is, can ASMIDF, ASMIDFB and EQANMDBG use the output from either, or does ASMIDF have to use the output from ASMLANGX and EQANMDBG have to use the output of EQALANGX? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
HLASM IDF ddnames
Cross-posted to ASSEMBLER-LIST, IBM-MAIN. Is there a list of all the ddnames used by IDF and their functions? The manual has a section on optional files, but it is missing, e.g., the macro library ASM. I tried checking the index, with no luck. BTW, why did IBM drop the RCF e-mail address? It was an easy, robust way to submit comments. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
Re: Does the GET macro indicate EOF?
or MYEODAD XRR1,R1 BRR14 ... DOEXIT (LTR,R1,R1,Z) -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Ed Jaffe <17285f33d197-dmarc-requ...@listserv.uga.edu> Sent: Friday, May 10, 2024 3:04 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the GET macro indicate EOF? On 5/9/2024 5:41 AM, Binyamin Dissen wrote: > Have your EODAD do > >LFI R1,c'EODA' >BR R14 Or my favorite value: LFI R1,X'FE0D' Then you can DOEXIT CIJ,R1,LT,0 to exit the loop if negative... -- Phoenix Software International Edward E. Jaffe 831 Parkview Drive North El Segundo, CA 90245 https://secure-web.cisco.com/1QV9NJauLlUqZCVJgsyHivXqnU-xa6_5zKxojR_y1scMR7d4H3Urya21mUIZL5OeI13VMS19o_38tA4HNnhDsCiLnHm4U6HwIxbHJu32tZBnX_GKpsz-7F4mThAjqFrEwRi8U5RzJj1c2qebKn3T64GHnv5TL6t2h2x36Q5y3OeMWXtA0VuwlZoGGaazxl4Cd32LAUq60tQIpYNGHWmKPtTBWJTCcZHpHExTvXqkZqfxaiblEvl1uZuAAYsCc_LyBEf-nF7_qrDR_5Ljb0vXV0bsxywUTwItGUP6X-NvJqhYHUwLM2qN0Tc6LjpJsyAEc76llkMCumQ57S3xFgSKLvzf0cFRPXzux4-cEe5c0LlHq76HKV5FlTlwaqjCJ4sVF0Eu1pq_sKyCrRfQqAkyJtHOqhVfDlVrE60Ec49LLFVQ/https%3A%2F%2Fwww.phoenixsoftware.com%2F This e-mail message, including any attachments, appended messages and the information contained therein, is for the sole use of the intended recipient(s). If you are not an intended recipient or have otherwise received this email message in error, any use, dissemination, distribution, review, storage or copying of this e-mail message and the information contained therein is strictly prohibited. If you are not an intended recipient, please contact the sender by reply e-mail and destroy all copies of this email message and do not otherwise utilize or retain this email message or any or all of the information contained therein. Although this email message and any attachments or appended messages are believed to be free of any virus or other defect that might affect any computer system into which it is received and opened, it is the responsibility of the recipient to ensure that it is virus free and no responsibility is accepted by the sender for any loss or damage arising in any way from its opening or use.
Re: Does the GET macro indicate EOF?
Usually people set a switch in the EODAD routine. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of David Eisenberg Sent: Wednesday, May 8, 2024 6:35 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Does the GET macro indicate EOF? I hope someone can help me; my question pertains to the QSAM GET macro. Please consider this code snippet: OPEN SYSIN GETLOOP GET SYSIN,BUFFER MYEODAD DS0H B GETLOOP EOF CLOSE SYSIN * SYSINDCB DDNAME=SYSIN,MACRF=GM,DSORG=PS,RECFM=FB,EODAD=MYEODAD,LRECL=80 I've deliberately placed the EODAD address immediately after the GET. My question: is there anything I can test immediately after the GET to determine whether a) I successfully read a record, or b) I've reached the EOF? The IBM manual says that after a GET, R1 points to the record that was read; however, I don't see any indication in the manual of where R1 points when the EOF is encountered, nor do I see any return code setting in R15 at EOF. I have empirically observed that at EOF, R1 points to an area in storage containing the string 'EOV ', but I don't know if I can rely on that. Does GET tell me anything when the EOF is reached? Or is there something in the DCB that I can test to tell me that I'm at the EOF? (I know that it looks silly to have the EODAD in the middle of the GET loop. This is about my trying to overcome an IDF limitation regarding single-stepping.) Any help would be appreciated; thank you! David
Re: Relative branching instructions info
Titles, form codes and lynx? Thanks. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Bertus Bekker Sent: Friday, May 10, 2024 7:08 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Relative branching instructions info Although not fully related to this topic, and covering more implementation than pure architecture matters, the IBM z Functional Matrix Redpapers do give a summary of some of the evolution. On Fri, May 10, 2024 at 12:52 AM Farley, Peter < 0dc9d8785c29-dmarc-requ...@listserv.uga.edu> wrote: > I second (or is it fourth or fifth now . . .) that request! > > Peter > > From: IBM Mainframe Assembler List On > Behalf Of Martin Trübner > Sent: Thursday, May 9, 2024 3:35 PM > To: ASSEMBLER-LIST@LISTSERV.UGA.EDU > Subject: Re: Relative branching instructions info > > > Yes Sir, please !!! > > > > Martin > > > > On 09.05.24 18:04, Jonathan Scott wrote: > > > I have for some years had a comprehensive list of all opcodes > > > supported by HLASM showing the range of OPTABLEs for which each > > > one is valid, the instruction format, whether it is an extended > > > mnemonic, the instruction name and some other information. This > > > information is generated systematically by a tool from the HLASM > > > OPTABLE definitions. > > > > > > I will try to get it added as a new appendix to the HLASM > > > Programmer's Guide, if that is considered practical and > > > maintainable. > > > > > > Jonathan Scott, HLASM > > > IBM Hursley, UK > > -- > > This message and any attachments are intended only for the use of the > addressee and may contain information that is privileged and confidential. > If the reader of the message is not the intended recipient or an authorized > representative of the intended recipient, you are hereby notified that any > dissemination of this communication is strictly prohibited. If you have > received this communication in error, please notify us immediately by > e-mail and delete the message and any attachments from your system. >
Re: Relative branching instructions info
IMHO it would be useful. Thanks. Now all we need is a nodel to feature cross reference. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Jonathan Scott Sent: Thursday, May 9, 2024 12:04 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Relative branching instructions info I have for some years had a comprehensive list of all opcodes supported by HLASM showing the range of OPTABLEs for which each one is valid, the instruction format, whether it is an extended mnemonic, the instruction name and some other information. This information is generated systematically by a tool from the HLASM OPTABLE definitions. I will try to get it added as a new appendix to the HLASM Programmer's Guide, if that is considered practical and maintainable. Jonathan Scott, HLASM IBM Hursley, UK
Re: Relative branching instructions info
Another complication is that an alias may have been added to HLASM later than the instruction. It's happened, but I have no idea how often. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Charles Mills Sent: Thursday, May 9, 2024 11:21 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Relative branching instructions info Ah! That's a different question. It's always a research project. I know of no exhaustive "this instruction was introduced with this model" document. You can go through the various Principles of Operation versions and look for change bars. Not a quick task. You can look at the description for each instruction and look at the Program Exceptions paragraph and find something like "Operation (if the general-instructions-extension facility is not installed)." And then go through the various announcements looking for when the relevant facility was announced. Another trick is to look at the supported opcodes for each hardware level specification for HLASM. As I say, not simple. A research project. I once thought about doing a definitive spreadsheet but I gave up on the project before I had made much progress. Charles -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of João Reginato Sent: Thursday, May 9, 2024 8:07 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: RES: Relative branching instructions info Importance: Low I need to know in what hardware it was first implemented
Re: Relative branching instructions info
The OP wanted model-dependent information, which is not in PoOps. I suggested the redbooks, although they may not have as much detail as he wants. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Charles Mills Sent: Thursday, May 9, 2024 11:10 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Relative branching instructions info Principles of Operation is both the best source, and also about the only definitive source. https://publibz.boulder.ibm.com/epubs/pdf/dz9zr010.pdf Charles -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of João Reginato Sent: Thursday, May 9, 2024 5:50 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Relative branching instructions info Importance: Low Hi Do you know where can I find additional information about the hardware implementation of the relative branching instructions? (ie. CLIJ, CRJ, J, etc) TIA João
Re: Does the GET macro indicate EOF?
BR 14 will work as well as J RESUME and is shorter. Clearing R1 works as well as a separate flag, if you only need to test it in one place. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Martin Trübner <1237eee49f7e-dmarc-requ...@listserv.uga.edu> Sent: Thursday, May 9, 2024 8:37 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the GET macro indicate EOF? set the bit as suggested in a separate EOF routine if you use the BR 14 to end your EOF handling, you have a bit to test after the GET. so it looks like this GET_LOOP DS 0H GET DCB RESUME DS 0H TM FLAG,BIT JO REAL_EOF SET_FLAG DS 0H OI FLAG,BIT J RESUME DCB EODAD=SET_FLAG that way you should be able to work with just one break point at label RESUME . It comes there with FLAG set once EOF is reached, but also every time after GET On 09.05.24 14:18, David Eisenberg wrote: >> What are you trying to do?< > I'm trying to overcome a limitation in ASMIDF involving single-stepping > through code while debugging. That's the only reason I'm asking about this. > > As per the IBM documentation, ASMIDF's single-stepping process involves the > automatic placement and removal of breakpoints. To do accomplish that, ASMIDF > must predict the next executable instruction, so that it can set a breakpoint > on it. When the current instruction is a GET macro, ASMIDF doesn't have the > logic to dig out the EODAD and set a temporary breakpoint on that > instruction; it only sets the temporary breakpoint on the instruction > immediately following the GET. > > My GET code is in an external subroutine that is called by other > applications. Any developer who single-steps into that subroutine never gets > control back from ASMIDF, because the GET loop reads to EOF, and (because > there is no automatic breakpoint set on the EODAD) the program runs to > completion without stopping. > > The entire problem disappears if the EODAD is immediately after the GET, > because then the breakpoint will be set and honored in all cases. But if I do > it that way, then I have to know whether I reached that instruction because > it really is the EOF, or whether the GET returned a record. > > I just don't know how to dig what I need out of any control blocks, or > whether that information is available. Does the GET return anything I can > use? Maybe via R1? Or is there something in the DCB to tell me if I've > reached the EOF? > > David
Re: Does the GET macro indicate EOF?
That will work, at least in MVS. I'm not sure about CMS or z/VSE. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Steve Smith Sent: Wednesday, May 8, 2024 7:14 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the GET macro indicate EOF? You can set up an EODAD routine that clears R1, and BR 14. You can then just check for R1 being 0 after the GET. I think that will work; I only use GL for QSAM. sas
Re: Does the GET macro indicate EOF?
This is a general issue for any debugger; stepping only works for the main line, and does not handle exits. You can set a breakpoint on the exit, or use the code MYEODXR1,1 BR14 Is there an RFE for the debugger to trap Instruction Fetch PER events? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of David Eisenberg Sent: Thursday, May 9, 2024 8:18 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Does the GET macro indicate EOF? >What are you trying to do?< I'm trying to overcome a limitation in ASMIDF involving single-stepping through code while debugging. That's the only reason I'm asking about this. As per the IBM documentation, ASMIDF's single-stepping process involves the automatic placement and removal of breakpoints. To do accomplish that, ASMIDF must predict the next executable instruction, so that it can set a breakpoint on it. When the current instruction is a GET macro, ASMIDF doesn't have the logic to dig out the EODAD and set a temporary breakpoint on that instruction; it only sets the temporary breakpoint on the instruction immediately following the GET. My GET code is in an external subroutine that is called by other applications. Any developer who single-steps into that subroutine never gets control back from ASMIDF, because the GET loop reads to EOF, and (because there is no automatic breakpoint set on the EODAD) the program runs to completion without stopping. The entire problem disappears if the EODAD is immediately after the GET, because then the breakpoint will be set and honored in all cases. But if I do it that way, then I have to know whether I reached that instruction because it really is the EOF, or whether the GET returned a record. I just don't know how to dig what I need out of any control blocks, or whether that information is available. Does the GET return anything I can use? Maybe via R1? Or is there something in the DCB to tell me if I've reached the EOF? David
Re: SV: ASMA043E Previously defined symbol
> It worked but my co-workers were apoplectic to see definitions > appear in the midst of executable code. Why? I rely heavily on generating EQU, to say nothing of LOCTR-wrapped constants and code. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Paul Gilmartin <0014e0e4a59b-dmarc-requ...@listserv.uga.edu> Sent: Sunday, May 5, 2024 10:44 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: SV: ASMA043E Previously defined symbol On 5/4/24 22:36:27, Ed Jaffe wrote: >>... >> But we had a register equates macro that came to conflict with >> IATYREGS when we added JES3 support. Many JES3 headers used >> IATYREGS conditioned on setting ofa GBLB. > > All of the IATY macros have similar conditioning, thus allowing duplicate > (usually embedded) mapping macro invocations without assembler errors. > . By that time I was not an Assembler coder but a sympathetic spectator. The product was a couple years old before we added JES3 support. Our coding conventions required that each Assembler module COPY a standard module prologue containing register equates, branch around eyecatcher, etc. We could remove the register equates and substitute IATYREGS but we feared that might introduce conflicts with established non-JES3 Earlier, I had been assigned to create a functional macro which required some definitions: EQU, DSECT, ... I coded that to MEXIT immediately on repeated calls. Then I went a step further: I added a call to my definitions macro to my functional macro, avoiding explicit prerequisites. It worked but my co-workers were apoplectic to see definitions appear in the midst of executable code. That may have contributed to the brevity of my term a an Assembler programmer. -- gil
Re: IEABRC anomaly
That's how I changed it for testing, but I don't know whether they will allow the fix in production. Meanwhile, I've added comments on the IEABRCX hack just in case. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Ngan, Robert (DXC Luxoft) Sent: Friday, May 3, 2024 2:07 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: IEABRC anomaly I remember (a long time ago) we had "first time" code preceded by a NOP, which altered the NOP condition code to branch around the "first time" code on subsequent invocations. Robert Ngan DXC Luxoft -Original Message- From: IBM Mainframe Assembler List On Behalf Of Abe Kornelis Sent: Thursday, May 2, 2024 14:59 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: IEABRC anomaly [Some people who received this message don't often get email from a...@bixoft.nl. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] Shmuel, all, it's been a long time since I last saw code like that. Worst example was code that XOR-ed the opcode of an AH instruction to switch back and forth between AH and SH to print a report in two columns. If I still had code like that in my code base, I'd prioritize to make that code RENT. (if I had enough breathing room to make that decision) Kind regards, Abe === Op 02/05/2024 om 19:16 schreef Seymour J Metz: > Except that IEABRC is only necessary for old code. I've inherited code that > uses NOP as a switch, overlaying the mask with F. > > -- > Shmuel (Seymour J.) Metz > https://secure-web.cisco.com/1hq5TPW9p1rQ9PcYL1V69Y4MDh5ECPN79dsvNxzpDZNOLyKkXJkaX5k8nFSb_DDXsVQyrEciAZkbttxpkpd2W5ZDt9YExftC2pGJOxWylN7ZcENyuD-YmwHkTh6RjpYCQwNREyGx6RWJDKd_C_y8VlPdgbm2tYZrxLUMyE0qDqGnKl4-h4moEbbZoSCCQmx3aI8n5QB28Q9zmtjaTIGZs13NmST7LT--RpCOz07PMJ3AA08qP3TgstuIXRadzzBy77qBdbRqlZe9HgNQZpfBijiG95d8jlf4m1I0MGdlsQlOlWlye86hlCXH6MRIaVoUTeXU9izzFEffYFvjCG5tat5YvDx3t00NkFMIaQFBf-lorck60IoiPse3HuDHVt_2_4Enw3-i8OtCrhQYEf0zRVTgtV8t5-Gsmc0qhDHQq234/https%3A%2F%2Fnam12.safelinks.protection.outlook.com%2F%3Furl%3Dhttp%253A%252F%252Fmason > .gmu.edu%2F~smetz3&data=05%7C02%7Crobert.ngan%40dxc.com%7Cc9f10e081dd6 > 47cf875a08dc6ae2549e%7C93f33571550f43cfb09fcd331338d086%7C0%7C0%7C6385 > 02767524497151%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2l > uMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=1205muWAwyyeshC > OveMPL6ffrbRvqWVIgVKRulIjy%2BA%3D&reserved=0 > עַם יִשְׂרָאֵל חַי > נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר > > > From: IBM Mainframe Assembler List > on behalf of Peter Relson > Sent: Thursday, May 2, 2024 8:37 AM > To: ASSEMBLER-LIST@LISTSERV.UGA.EDU > Subject: Re: IEABRC anomaly > > I don't recall having thought about this when providing IEABRC. But the > conclusion that it's not going to get added is likely a correct one. > > Without a complex macro (which definitely is not going to happen), changing > NOP to JNOP for the cases Jonathan Scott mentioned will reject operands that > are fully valid (avoiding RC=4 if you suppress ASMA212W Branch address > alignment for unfavorable). I believe his case is a very common one of > using the operand of NOP for diagnostic purposes. > > While NOP perhaps isn't a branch (because it never goes anywhere), it is the > conditional branch opcode so could have been a candidate for conversion. But > functionally it is not necessary. Anyone who truly wants conversion of the > operand for some reason could avoid using NOP and code a conditional branch > with mask 0. That will get converted. > > Peter Relson > z/OS Core Technology Design
Re: IEABRC anomaly
In general, but not when there are addressability issues. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Tom Marchant <00a69b48f3bb-dmarc-requ...@listserv.uga.edu> Sent: Thursday, May 2, 2024 8:49 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: IEABRC anomaly Would it help to use IEABRCX and disable it around that macro? -- Tom Marchant On Thu, 2 May 2024 21:50:26 +, Seymour J Metz wrote: >It's not clear that the author ever heard of EX. Some of the code is decades >old, and a mass cleanup is not authorized. I'm not rven sure whether I can get >permission to fix a macro that IEABRC breaks (it uses the BDDD of a B as a >first-time switch. > >-- >Shmuel (Seymour J.) Metz >http://mason.gmu.edu/~smetz3 >עַם יִשְׂרָאֵל חַי >נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר > > >From: IBM Mainframe Assembler List on behalf >of Paul Gilmartin <0014e0e4a59b-dmarc-requ...@listserv.uga.edu> >Sent: Thursday, May 2, 2024 5:12 PM >To: ASSEMBLER-LIST@LISTSERV.UGA.EDU >Subject: Re: IEABRC anomaly > >On 5/2/24 11:16:13, Seymour J Metz wrote: >> Except that IEABRC is only necessary for old code. I've inherited code that >> uses NOP as a switch, overlaying the mask with F. >> . >Self-modifying or EX code!? > >-- >gil
Re: IEABRC anomaly
It's not clear that the author ever heard of EX. Some of the code is decades old, and a mass cleanup is not authorized. I'm not rven sure whether I can get permission to fix a macro that IEABRC breaks (it uses the BDDD of a B as a first-time switch. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Paul Gilmartin <0014e0e4a59b-dmarc-requ...@listserv.uga.edu> Sent: Thursday, May 2, 2024 5:12 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: IEABRC anomaly On 5/2/24 11:16:13, Seymour J Metz wrote: > Except that IEABRC is only necessary for old code. I've inherited code that > uses NOP as a switch, overlaying the mask with F. > . Self-modifying or EX code!? -- gil
Re: IEABRC anomaly
Except that IEABRC is only necessary for old code. I've inherited code that uses NOP as a switch, overlaying the mask with F. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Peter Relson Sent: Thursday, May 2, 2024 8:37 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: IEABRC anomaly I don't recall having thought about this when providing IEABRC. But the conclusion that it's not going to get added is likely a correct one. Without a complex macro (which definitely is not going to happen), changing NOP to JNOP for the cases Jonathan Scott mentioned will reject operands that are fully valid (avoiding RC=4 if you suppress ASMA212W Branch address alignment for unfavorable). I believe his case is a very common one of using the operand of NOP for diagnostic purposes. While NOP perhaps isn't a branch (because it never goes anywhere), it is the conditional branch opcode so could have been a candidate for conversion. But functionally it is not necessary. Anyone who truly wants conversion of the operand for some reason could avoid using NOP and code a conditional branch with mask 0. That will get converted. Peter Relson z/OS Core Technology Design
Re: ASMA043E Previously defined symbol
I just ran a test on OREXX: it catches syntax errors even in unexecuted code but does not catch duplicate labels. I'll have to test on ooRexx as well, but I'm out of round tuits. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Seymour J Metz Sent: Wednesday, May 1, 2024 5:53 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: ASMA043E Previously defined symbol No, it is a feature of *some* interpreters. Others translate into an internal code and interpret that. I don't know how it handles duplicate labels, but Object Rexx definitely catches some errors that others don't as the result of its initial tokenization prior to execution. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Charles Mills Sent: Wednesday, May 1, 2024 2:17 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: ASMA043E Previously defined symbol Well, and it is a feature of interpretive execution. When you branch to a label, it looks until it finds that label. It doesn't keep looking to see if there is another. (Yes, it could and might, but it would take time, and it doesn't.) It's an example of something I dislike about both Rexx and Python: errors that would be caught in compilation in other languages are not caught until you hit them, perhaps at oh-dark-thirty at a customer site. Charles -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Phil Smith III Sent: Wednesday, May 1, 2024 10:00 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: ASMA043E Previously defined symbol Paul Gilmartin wrote, re Rexx being fine with duplicate labels: >That's bad. That's WAD. Remember, the goal of Rexx was ease of use. Just sayin'.
Re: IEABRC anomaly
In my case it gets an addressability error. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Joseph Reichman Sent: Wednesday, May 1, 2024 11:25 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: IEABRC anomaly There is a B2D2 there just the mask is zero So it falls thru > On May 1, 2024, at 11:06 AM, Pieter Wiid wrote: > > NOP translates to BC 0 > > -Original Message- > From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] > On Behalf Of Paul Gilmartin > Sent: Wednesday, 01 May 2024 16:21 > To: ASSEMBLER-LIST@LISTSERV.UGA.EDU > Subject: Re: IEABRC anomaly > >> On 5/1/24 07:56:17, Seymour J Metz wrote: >> It turns out that IEABRC does not convert NOP to JNOP. Is that a bug or a >> feature? >> . > Does NOP depend on a base register? > > -- > gil > > > -- > This email has been checked for viruses by Avast antivirus software. > http://www.avast.com/
Re: ASMA043E Previously defined symbol
While WAD often means BAD, that is not always the case. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Steve Smith Sent: Wednesday, May 1, 2024 1:25 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: ASMA043E Previously defined symbol Ease of bizarre inscrutable errors is not the same as ease of use. Just sayin' ;-) WAD just means it was a bad design. sas On Wed, May 1, 2024 at 7:00 PM Phil Smith III wrote: > Paul Gilmartin wrote, re Rexx being fine with duplicate labels: > >That's bad. > > That's WAD. Remember, the goal of Rexx was ease of use. Just sayin'. >
Re: ASMA043E Previously defined symbol
No, it is a feature of *some* interpreters. Others translate into an internal code and interpret that. I don't know how it handles duplicate labels, but Object Rexx definitely catches some errors that others don't as the result of its initial tokenization prior to execution. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Charles Mills Sent: Wednesday, May 1, 2024 2:17 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: ASMA043E Previously defined symbol Well, and it is a feature of interpretive execution. When you branch to a label, it looks until it finds that label. It doesn't keep looking to see if there is another. (Yes, it could and might, but it would take time, and it doesn't.) It's an example of something I dislike about both Rexx and Python: errors that would be caught in compilation in other languages are not caught until you hit them, perhaps at oh-dark-thirty at a customer site. Charles -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Phil Smith III Sent: Wednesday, May 1, 2024 10:00 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: ASMA043E Previously defined symbol Paul Gilmartin wrote, re Rexx being fine with duplicate labels: >That's bad. That's WAD. Remember, the goal of Rexx was ease of use. Just sayin'.
IEABRC anomaly
It turns out that IEABRC does not convert NOP to JNOP. Is that a bug or a feature? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
Re: Complex immediate fields
Expect a performance hit if you modify instructions. I like to use LOCTR to keep data physically remote but visually near the instructions that use them. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Gary Weinhold Sent: Monday, April 15, 2024 2:06 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Complex immediate fields From a performance and sometimes readability point of view, having constants (whether instructions or operands), close in memory to the instructions using them is desirable. As Gil mentions, macroes are likely to do it. There ia a data cache and an intruction cache, but there is nothing inherent to prevent a program from modifying the instruction stream or the instruction stream from branching into an area of the program that's in the data cache. (There may be key exceptions that create errors). But any modification to the instruction cache requires the instruction cache line to be moved to the data cache, and any attempt to execute instructions in the data cache requires the cache line to be moved to the instruction cache. I don't think this affects page fault handling. Whether instructions are refreshable depends on external factors, including binder options and characteristics of the load library. I don't know about USS. Gary Weinhold Senior Application Architect DATAKINETICS | Data Performance & Optimization Phone:+1.613.523.5500 x216 Email: weinh...@dkl.com Visit us online at http://www.dkl.com/ E-mail Notification: The information contained in this email and any attachments is confidential and may be subject to copyright or other intellectual property protection. If you are not the intended recipient, you are not authorized to use or disclose this information, and we request that you notify us by reply mail or telephone and delete the original message from your mail system. From: IBM Mainframe Assembler List on behalf of Paul Gilmartin <0014e0e4a59b-dmarc-requ...@listserv.uga.edu> Sent: April 15, 2024 13:37 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Complex immediate fields On 4/15/24 10:09:06, Charles Mills wrote: > ... > And I would never, ever embed data in the instruction stream. > . I.e. no parameters following the CALL-type instruction? Don't some library macros (still) do this, bypassing with a relative (ugh!) branch instruction? Are instruction pages distinguished from data pages nowadays? Do page faults behave differently between the two? Are instruction pages REFReshable? -- gil
Re: Complex immediate fields
Business needs. The key questions are What is the oldest OS we have to support What is the oldest processor we have to support. Long ago in a galaxy far away I controlled dual passing with SYSPARM, tested by my private macros. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Tom Marchant <00a69b48f3bb-dmarc-requ...@listserv.uga.edu> Sent: Monday, April 15, 2024 2:49 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Complex immediate fields Charles is right. IILF was first documented in the -08 level of the POO, for the z114/z196. z/OS 2.2 was the last release to run on that hardware, and has been unsupported since 2020-09-30. The extended mnemonic LFI was added later, but that isn't relevant. I don't understand the reluctance to use newer instructions when they are included in the minimum requirement for the operating system. -- Tom Marchant On Mon, 15 Apr 2024 09:09:06 -0700, Charles Mills wrote: >If you are running "sometimes" on older hardware I think you have a greater >risk from unsupported z/OS than from unsupported instructions. > >I'm not sure, but I think that IILF came along no later than the zEC12. Any >machine older than the zEC12 only supports z/OS V2R2 and below. V2R2 went out >of service almost four years ago. If you are running a current z/OS it won't >run on older hardware. > >I also think you are at greater risk of encountering unsupported instructions >in optimized COBOL 6 code than in hand-built assembler. > >And I would never, ever embed data in the instruction stream. > >Charles > > >-Original Message- >From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On >Behalf Of Jon Perryman >Sent: Sunday, April 14, 2024 11:09 PM >To: ASSEMBLER-LIST@LISTSERV.UGA.EDU >Subject: Re: Complex immediate fields > >> On current hardware there is an IILF (LFI) instruction, and I would like to >>> use it instead of the XR/ICM sequence. > >Before using any modern instructions, ask yourself if they are worth the risk. >Does your disaster recovery site guarantee this as a minimum machine level. >Maybe your employer has older machines available in case of capacity problems. >How about company acquisition. You need to consider the impact. > >>Back in he Assembler XF era I would code something like >> LAR0,L'DEST >> LAR1,DEST >> XRR15,R15 >> ICM R15,8,=C' ' >> MVCL R0,R14 > >Why use LFI when better alternatives for ICM =C' ' have been around forever. >J bydata >data dc A(X'4000',0,L'dest) >bydata LM R15,R1,data > >Since the J instruction only updates the PSW, I'm guessing it will replace the >update PSW in the previous instruction thus making this a single instruction >on current hardware but still compatible with older hardware. > >Alternatively, there is the NILH instruction which has existed for a couple >decades.
Re: PUSH and POP USING question
Try PUSH USING DROP , USING *,R15 ... *DROP R15 Don't need POP USING -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Tony Thigpen Sent: Monday, April 15, 2024 10:04 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: PUSH and POP USING question All, I have some small routines that are contained in COPY members. They all contain USING *,R15. They are all used via BALR. Although I know it don't matter, but I would like to eliminate the 'MULTIPLE ADDRESS RESOLUTIONS' message. I first tried: PUSH USING USING *,R15 ... DROP R15 POP USING So, I need to drop the base registers, but since this code is used in programs that use different base registers, I would have to drop every register after the PUSH. Does anyone have a good 'method/trick' to handle this? Tony Thigpen
Re: Complex immediate fields
I'll have to try that once I get my userid back. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Charles Mills Sent: Friday, March 29, 2024 3:26 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Complex immediate fields What about (untested) ShiftLeft24 EQU x'100' LFI R15,X'40'*ShiftLeft24 Charles -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Seymour J Metz Sent: Friday, March 29, 2024 9:57 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Complex immediate fields Back in he Assembler XF era I would code something like LAR0,L'DEST LAR1,DEST XRR15,R15 ICM R15,8,=C' ' MVCL R0,R14 On current hardware there is an IILF (LFI) instruction, and I would like to use it instead of the XR/ICM sequence. I consider LFI R15,X'4000' to be ugly, and would like to be able to either use an immediate field combing CL1 and XL3 pieces or to refer to an EQU defining that combination. Is there any way to do that in HLASM? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
Re: Complex immediate fields
Good catch. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Dan Greiner Sent: Friday, March 29, 2024 1:09 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Complex immediate fields Seymour, You usage of the even/odd R0/R1 pair appears to be reversed (unless you intended to zero some memory at whatever location L'DEST resolves to ... not to worry, it happens to dyslexic programmers like me all the time). I don't know of any means by which you can split the definition of an immediate field such as you suggest, and I'm not sure I'd welcome that sort of complexity for what is otherwise a relatively simple concept: immediacy.
Re: Complex immediate fields
Back in the day the PDP-6 looked coll. MAP in IBSYS/IBJOB also had a feature that I would love to see in HLASM: the QUAL pseudo-op. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Paul Gilmartin <0014e0e4a59b-dmarc-requ...@listserv.uga.edu> Sent: Friday, March 29, 2024 1:15 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Complex immediate fields On 3/29/24 10:56:49, Seymour J Metz wrote: > Ba... I consider > > LFI R15,X'4000' > > to be ugly, and would like to be able to either use an immediate field > combing CL1 and XL3 pieces or to refer to an EQU defining that combination. > Is there any way to do that in HLASM? > Is LOCTR any help? (You would have loved the PDP-6 immediate facility. An immediate value could be any sequence of instructions and constants.) -- gil
Re: Complex immediate fields
That still uses hex notation for character data, which is what I'm trying to avoid. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Tom Harper <16c16a7381bc-dmarc-requ...@listserv.uga.edu> Sent: Friday, March 29, 2024 1:12 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Complex immediate fields Seymour, How about this: LLILH R15,X’4000’ Tom Harper Phoenix Software International Sent from my iPhone > On Mar 29, 2024, at 12:56 PM, Seymour J Metz wrote: > > Back in he Assembler XF era I would code something like > > LAR0,L'DEST > LAR1,DEST > XRR15,R15 > ICM R15,8,=C' ' > MVCL R0,R14 > > On current hardware there is an IILF (LFI) instruction, and I would like to > use it instead of the XR/ICM sequence. I consider > > LFI R15,X'4000' > > to be ugly, and would like to be able to either use an immediate field > combing CL1 and XL3 pieces or to refer to an EQU defining that combination. > Is there any way to do that in HLASM? > > > > -- > Shmuel (Seymour J.) Metz > http://mason.gmu.edu/~smetz3 > עַם יִשְׂרָאֵל חַי > נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר This e-mail message, including any attachments, appended messages and the information contained therein, is for the sole use of the intended recipient(s). If you are not an intended recipient or have otherwise received this email message in error, any use, dissemination, distribution, review, storage or copying of this e-mail message and the information contained therein is strictly prohibited. If you are not an intended recipient, please contact the sender by reply e-mail and destroy all copies of this email message and do not otherwise utilize or retain this email message or any or all of the information contained therein. Although this email message and any attachments or appended messages are believed to be free of any virus or other defect that might affect any computer system into which it is received and opened, it is the responsibility of the recipient to ensure that it is virus free and no responsibility is accepted by the sender for any loss or damage arising in any way from its opening or use.
Complex immediate fields
Back in he Assembler XF era I would code something like LAR0,L'DEST LAR1,DEST XRR15,R15 ICM R15,8,=C' ' MVCL R0,R14 On current hardware there is an IILF (LFI) instruction, and I would like to use it instead of the XR/ICM sequence. I consider LFI R15,X'4000' to be ugly, and would like to be able to either use an immediate field combing CL1 and XL3 pieces or to refer to an EQU defining that combination. Is there any way to do that in HLASM? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
Re: Don Higgins has retired from z390 development again
Congratulations on your clear scans. Please consider retaining an online presence after your retirement. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Don Higgins Sent: Tuesday, March 5, 2024 3:45 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Don Higgins has retired from z390 development again All I have retired again from z390 development after having survived esophageal cancer, kidney cancer, and thyroid cancer over the past 2 years. All my scans are now clear of cancer, and I feel well again. So at 79 I'm planning to spend more time with my wife Charlotte traveling and relaxing. I will miss working with the current z390 core development team: Abe Kornelis, John Ganci, and Anthony Delosa, and hope they will continue on. I also miss working with Melvyn Maltz and John Ehrman who supported z390. Melvyn developed the z390 CICS emulation, and John invited me to present z390 at several SHARE sessions. For those interested in learning more about z390, the current development site is here: https://github.com/z390development/z390 The original website I maintained from 2004 until 2012 when I turned it over to Abe is here: https://secure-web.cisco.com/1vVfXcURNkEeZJyQ_p8Su0cx1RxZlL1iT8Tnu961a0Xq1kAIo9W59J10NCK_nlJ0FEdj1noPCZVeTXIU7xjCsYyIGeIpYw-9jCli8r0LirA2qz3aoUldqYrzRM_O_NV2Zu6HvjLCCvLUNjwfuSqj0NqJnyekBqhdifPbBxRbQezonL_khkT6x8QPAWeYEdw3UmlCoaJTyOSzyt1czlCq_8wheA0hsYlYFwtmknsGmO-L9tVJOz10Fv_CZnYF2bQKcPqyHwHGDaHlKe4RnCIY2VstbI4eyc0N5tflNBW7gqqQJUzC6vEPCKM-Vi10azffJv4UffYIBrn64h6oHxE0MKwzFip4V_YByz0FnWKUc-a0tkGKC0ojJlzPQD8Q7nbUaEv0ZLQ8AmImvYhrlpXSm54Esr5EWjevVLcVSMQigLbY/https%3A%2F%2Fz390.org%2F All z390 code is written in J2SE Java and is open source. The purpose of z390 is to help those interested in learning, developing, and executing mainframe assembler programs on Windows and Linux. Don Higgins d...@higgins.net <mailto:d...@higgins.net> http://secure-web.cisco.com/1VxVxIlTBzu_hufaYusy6sDdTt_RAzLiExSqhz8RdaIHW1G9ADnbT_0esag0NXNMleueIZeCKVdkrOHGDuBx6SZ4NX2jb07OTg77ulVP0pQe5AEYWgHrZJCtE5_jzMcQftXSV-9fvLTYp3hyCLg0k20e1BZhlxidsrTLzOZ-AGwRGtgY3szkAWRvkTat8cfwBtIqNXQeZbCJnQMp-tAh23mfpJLgU9YZpXoXcfTnT3TghKhIGFrQzamGcZ_aiaqz_G7tuv35FqzEmX09w4PABPiUGEn__OJoKpPJLxZy3QkwAOVUOFJACmtf-hZEHRHeVXvG_E_eCiGtNKdCBvLwnXBRfTLio8yFl-bGNCVz-IpZPyAp68jpUrVTLIcxf1iHuI4I011JZQoxCjdbu5hEBcToIKXpRKZ5TKg5zjSg3MqA/http%3A%2F%2Fwww.donhiggins.org <http://secure-web.cisco.com/1VxVxIlTBzu_hufaYusy6sDdTt_RAzLiExSqhz8RdaIHW1G9ADnbT_0esag0NXNMleueIZeCKVdkrOHGDuBx6SZ4NX2jb07OTg77ulVP0pQe5AEYWgHrZJCtE5_jzMcQftXSV-9fvLTYp3hyCLg0k20e1BZhlxidsrTLzOZ-AGwRGtgY3szkAWRvkTat8cfwBtIqNXQeZbCJnQMp-tAh23mfpJLgU9YZpXoXcfTnT3TghKhIGFrQzamGcZ_aiaqz_G7tuv35FqzEmX09w4PABPiUGEn__OJoKpPJLxZy3QkwAOVUOFJACmtf-hZEHRHeVXvG_E_eCiGtNKdCBvLwnXBRfTLio8yFl-bGNCVz-IpZPyAp68jpUrVTLIcxf1iHuI4I011JZQoxCjdbu5hEBcToIKXpRKZ5TKg5zjSg3MqA/http%3A%2F%2Fwww.donhiggins.org>
Re: Why am I getting ASMA145E (was Re: Macro parameters: parsing a relocatable address)
The objective is not to parse the operand, but that doesn't mean that you can achieve the objective without doing so. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Binyamin Dissen Sent: Tuesday, February 27, 2024 9:40 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Why am I getting ASMA145E (was Re: Macro parameters: parsing a relocatable address) Yes, but the objective is not to parse the operand. On Tue, 27 Feb 2024 06:56:45 -0700 Paul Gilmartin <0014e0e4a59b-dmarc-requ...@listserv.uga.edu> wrote: :>On 2/27/24 05:21:41, Seymour J Metz wrote: :>> Because 24(R3) is not an expression. The second operand of the USING must be either a register number or a relocatable expression. :>> . :>Rather than :> USING MY0004,24(R3) :>would :> USING MY0004-24,R3 :>have the desired effect? -- Binyamin Dissen http://www.dissensoftware.com/ Director, Dissen Software, Bar & Grill - Israel
Re: Why am I getting ASMA145E (was Re: Macro parameters: parsing a
I don't have a dog in this fight; I was just trying to clarify what the issue was. It seems reasonable, but I haven't come up with a use case. If I were designing USING ab initio I would probably allow the base-displacement form only on a labelled USING, if at all. The only real way to determine the need is for someone to do an RFE with a good business case and see how many other customers concur. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Jonathan Scott Sent: Wednesday, February 28, 2024 7:42 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Why am I getting ASMA145E (was Re: Macro parameters: parsing a There are certainly cases where a base-displacement operand on USING would appear at first glance to make sense, as in the suggested case: USING SOMELABEL,24(R3) or with a symbolic offset expression USING SOMELABEL,TWENTY_FOUR(R3) However, even in concept some of the implications are not obvious. This would obviously be expected to work like a dependent USING, but it does not have a base USING giving the list of registers to be used, so it is not the same. One might expect it to act as if there was an implicit base USING for R3 pointing 24 bytes earlier, but without a label, which would be a new concept. But does that mean one could issue a DROP R3 and that R3 would be currently considered in use as a base so that a new USING for R3 would drop this use? At least since the language enhancement for PH42188 in 2021 to allow DROP for a relocatable symbol, one would be able to use DROP SOMELABEL. These are examples of the sorts of issues that arise when we investigate possible language enhancements. If there is a strong justification for some enhancement, it may be worth working through such issues and finding solutions. However, as far as I can see, the current suggestion would appear to require new concepts and raise complications which appear to be out of proportion to the potential benefits. Jonathan Scott, HLASM IBM Hursley, UK
Re: Why am I getting ASMA145E (was Re: Macro parameters: parsing a relocatable address)
If you mean BLAH DSECT DS 10C BLUEDS C that is *NOT* the same as 10(1); BLUE is a relocatable symbol offset 10 from dsect BLAH. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Binyamin Dissen Sent: Tuesday, February 27, 2024 11:55 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Why am I getting ASMA145E (was Re: Macro parameters: parsing a relocatable address) On Tue, 27 Feb 2024 15:13:02 + Seymour J Metz wrote: :>> BLUE is the same as 10(1) :>SHOW THE CODE! Look at the bottom of the previous email. spamassasian seems to be rejecting my posts with a lot of quoting. -- Binyamin Dissen http://secure-web.cisco.com/140hW0kVgu98LqZ9iiZPaWvVKjGYLQdUJww8mDKpSBfbXDgAEabDNFyElq8LJF5ADusJW91ylcaOFtbst0nC5H9wmM9DX6dJA4D9M7BtWuL1sxOv_RM2eEDVsWCOC4JoOPtIEqHwVzCqr6gC3gRnDLi16nKxrtUjApe_-cpfDKKF3ElSx3axsPF24yb_QgQRm98LCY-Ufb-SQ2djQfkYG0qTZHM-YP7CphzPXa4cqIBnR28cAAeUMOAzZpBH9suFtJ6neYRJfmPFkexjKv3vrubUh2ge8qa1jEfwtRG8Gv8iJF4Kyr4FtwRObi5Wu8cw7VjKsC4l9dPpI_eAWoaaOdyTD3_hPbtTKHfihsn7VeCh3icFO77N7RSe_f6FG9FTJlrZ14fjzJUJKCOGrtuigd4Ev3tNwkGO1hVuokStWmmM/http%3A%2F%2Fwww.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel
Re: Why am I getting ASMA145E (was Re: Macro parameters: parsing a relocatable address)
The problem is that 24(R3) really is not a relocatable expression. if you can
come up with a business case for accepting displacement9register) on a USING,
an RFE might bee accepted.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
עַם יִשְׂרָאֵל חַי
נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
From: IBM Mainframe Assembler List on behalf
of Jon Perryman
Sent: Tuesday, February 27, 2024 2:16 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Why am I getting ASMA145E (was Re: Macro parameters: parsing a
relocatable address)
On Tue, 27 Feb 2024 16:46:28 +0200, Binyamin Dissen
wrote:
>How is different than the case at the bottom?
>:>Because 24(R3) is not an expression. The second operand of the USING must be
>either a register number or a relocatable expression
Sadly, HLASM improvements barely keep the product alive otherwise we would see
REXX as an alternative to macro language. While USING SOMELABEL,MYLABEL may
generate 24(R3) internally, you cannot specify USING SOMELABEL,24(R3). You
could argue 24(R3) is a relocatable expression. I suspect that EQU will have
the same problem. You must accept HLASM with its blemishes and learn to work
around those blemishes. Some solutions to your problem as follows:
1. R3 is an EQU with type undefined. Maybe there is a type of "register" which
would allow 24(R3) to be considered a relocatable expression. R3 is ambiguous
because the assembler doesn't know if R3 represents a length, register or index
register.
2. Maybe EQU supports type S-CON that would allow it to be used as an arg in
the MVC. E.g. LBL EQU 24(R3),TYPE=SCON,LENGTH=2 used in MVC LBL,OTHER.
3. Force the user to code a length of 2 or omit the length. If var contains "("
then it must be "(2," or "(,".
4. If var contains "(" then replace it with "(2," and let it fail if the user
coded a length.
5. If you don't like using ORG then maybe EX is more to your liking. I'm not
saying I would use this method but different strokes for different folds.
Re: Why am I getting ASMA145E (was Re: Macro parameters: parsing a relocatable address)
> BLUE is the same as 10(1) SHOW THE CODE! > a label that translates to DDD(R) There is no such thing. A label has an absolute o relative value that remains constant throughout an assembly. A USING affects how the assembler generates object code from machine instructions ans S-cons. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Binyamin Dissen Sent: Tuesday, February 27, 2024 9:46 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Why am I getting ASMA145E (was Re: Macro parameters: parsing a relocatable address) I must be missing something quite obvious. How is different than the case at the bottom? BLUE is the same as 10(1) Some special rule where exactly DDD(R) is simply not allowed even though a label that translates to DDD(R) is allowed? On Tue, 27 Feb 2024 12:21:41 + Seymour J Metz wrote: :>Because 24(R3) is not an expression. The second operand of the USING must be either a register number or a relocatable expression. -- Binyamin Dissen http://secure-web.cisco.com/1K_cMuSTIBArNuzHYGbUwzs7QqGYDMlN9JV2mxyaM5utIjQAHX8L0UHrOP_1parujvKd0dEKBliQGkeLuShT9i2AgGCFMt2Pjsj8fbBA4EtjL97Oe79LACcRPPlM2iqlWWvPv5sUmeuR09eHSRu_XgB92FuTnuzdwnvpYsDbjvgzwZMwFSrLbCe3JrQcoeKolzGHLdO0-wNZ6-d4mgwGo30M_h8BFUmxV_c07AEcme4Jg1-HPOpDtPvfltiJ2bDFK4tlla4nBf3kEv1ODW34efFzCJejaG3MRv7PDpqVTgUBIw6PIwPLI2RTcvV9FQnayyIRIvxlsDCM753IPP38kK0n7fnDQ6TDAMZrym1_ULcYmeUvXpaiwdy9GfaFVELS0RmEG2a1UiMe8mdWi2WAu4_xsomONpW4CsBhzvjlb3DA/http%3A%2F%2Fwww.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel
Re: Why am I getting ASMA145E (was Re: Macro parameters: parsing a relocatable address)
It would certainly be valid. The effect of USING MY0004-24,R3 would be that MY0004+foo would get a displacement of foo=24 and an index of R3. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Paul Gilmartin <0014e0e4a59b-dmarc-requ...@listserv.uga.edu> Sent: Tuesday, February 27, 2024 8:56 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Why am I getting ASMA145E (was Re: Macro parameters: parsing a relocatable address) On 2/27/24 05:21:41, Seymour J Metz wrote: > Because 24(R3) is not an expression. The second operand of the USING must be > either a register number or a relocatable expression. > . Rather than USING MY0004,24(R3) would USING MY0004-24,R3 have the desired effect? -- gil
Re: Why am I getting ASMA145E (was Re: Macro parameters: parsing a relocatable address)
Because 24(R3) is not an expression. The second operand of the USING must be either a register number or a relocatable expression. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Binyamin Dissen Sent: Tuesday, February 27, 2024 7:01 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Why am I getting ASMA145E (was Re: Macro parameters: parsing a relocatable address) MACRO , MYCLC &P1,&P2 LCLC &C &C SETC '&SYSNDX' DSECT , MY&C DSCL2 &SYSECT CSECT , PUSH USING USING MY&C,&P1 CLC MY&C,&P2 POP USING MEND , Fails on 46 MYCLC 24(R3),ZERO 060 847+ DSECT , 06 48+MY0004 DSCL2 240 0003449+ CSECT , 50+ PUSH USING 51+ USING MY0004,24(R3) ** ASMA145E Operator, right parenthesis, or end-of-expression expected - (R3) Not sure why the assembler doesn't accept this relocatable expression. It will work if BLAH DSECT DS 10C BLUEDS C QWERT DSECT , BLIP DS F USING BLAH,1 USING QWERT,BLUE -- where BLUE is 10(1) -- Binyamin Dissen http://www.dissensoftware.com/ Director, Dissen Software, Bar & Grill - Israel
Re: Macro parameters: parsing a relocatable address
That will work if &P1 is a relocatable expression, but not if it's base(reg) or (reg). -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Binyamin Dissen Sent: Monday, February 26, 2024 2:14 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Macro parameters: parsing a relocatable address What I meant was: MACRO , MYCLC &P1,&P2 LCLC &C &C SETC '&SYSNDX' DSECT , MY&C DSCL2 &SYSECT CSECT , PUSH USING USING MY&C,&P1 CLC MY&C,&P2 POP USING MEND , However, it fails on 46 MYCLC 24(R3),ZERO 060 847+ DSECT , 06 48+MY0004 DSCL2 240 0003449+ CSECT , 50+ PUSH USING 51+ USING MY0004,24(R3) ** ASMA145E Operator, right parenthesis, or end-of-expression expected - (R3) Not sure why the assembler doesn't accept this relocatable expression. On Mon, 26 Feb 2024 10:55:31 -0500 David Eisenberg wrote: :>Benjamin, :> :>I'm really struggling to understand... how would I use a DSECT and USING to solve this? I can certainly generate those in the macro, but I don't see the technique in this case. :> :>David :> :>On Mon, 26 Feb 2024 17:14:19 +0200, Binyamin Dissen wrote: :> :>>Generate a DSECT and USING. :>> :>>On Mon, 26 Feb 2024 08:22:00 -0500 David Eisenberg :>>wrote: :>> :>>:>I?m seeking some guidance if anyone is able to help. I?d like to write a macro like this: :>>:> :>>:>&NAMEMYCLC &FIELD1,&FIELD2 :>>:> :>>:>in which both &FIELD1 and &FIELD2 are relocatable addresses. It?s &FIELD1 that is of particular interest to me. &FIELD1 might be expressed as a hard-coded displacement and base register, or a relocatable symbol? or it could be an absolute symbol equivalent to a displacement, followed by a base register? etc. I.e., it could be any valid relocatable address syntax. What &FIELD1 will *not* have is an *explicit length.* The macro parameters will specify valid relocatable addresses, and nothing more. :>>:> :>>:>My question: I?d like the MYCLC macro to generate a CLC instruction in which the two parameters are compared to each other for a constant length of 2. So far, the only ways I can think of to do this are: :>>:> :>>:>1. Parse &FIELD1 to figure out how the relocatable address is expressed, and insert an explicit length of 2 to generate a valid CLC first operand. I would do it that way, but (unless I'm missing something) it seems quite complex to code. :>>:>2. Generate this DC statement: DC X?D501?,S(&FIELD1,&FIELD2) . This seems to work, but it?s a bit unattractive in a PRINT GEN (and it looks a bit odd in the assembly listing, because the assembler doesn't treat it like a machine instruction in the object code on the left side of the listing). :>>:> :>>:>I?m wondering if anyone can suggest a reasonable way to code option 1 above. Can the macro assembler give me any help in parsing &FIELD1 so that I can transform that parameter to insert an explicit length, regardless of how &FIELD1 is expressed? Or is there some other approach that I haven?t considered at all? Or should I just go with option 2 above? :>>:> :>>:>Please note that I don?t want the macro to generate more than one machine instruction. One way or another, I just want the macro to generate a CLC for a length of 2. (And I really do want the CLC located in the macro as opposed to open code, because the macro does some analysis on the comparands prior to generating the CLC.) :>>:> :>>:>Any advice would be appreciated... thank you! :>>:> :>>:>David :>> :>>-- :>>Binyamin Dissen :>>http://secure-web.cisco.com/12D8uQ01ccp0utIHmjacXYXOu5jNYmttF4njp0GLIXLsq-2i6Es4u1iAr4UqCqWTDUSila2VZc28J1aqf-6n5Yv7TLe2ppeDlTlf_TomL8QrqkdJz4rN8WjjdSCh4PSjY-kALmBvtsFBP8NkMh-zVvN85q5bzVhCNO23vM3Gwg21DQnsaGlavs7u_9xS-KRjXKOKiTZiijOF0rnqKIFUGSCyNBKJHtav5Ag8Oq9zHIrbQMJalrvmYQN9pRew-3-zPGt45nCU1ZtDTNJ5bmyjf964mM4tpeWA8VLfFq8q1qE0nemML4RN07iat19zGpZd4DZ2qOmcQhggeOJIv0cZXKNL5XJvo8SY8gM67Ai0ler-eNZ4gcPChKyFauKCmJhBmH-jCgMvJVyZWmxAXEp9ddlrg1nTB9YHjsuHG0atiwBk/http%3A%2F%2Fwww.dissensoftware.com :>> :>>Director, Dissen Software, Bar & Grill - Israel -- Binyamin Dissen http://secure-web.cisco.com/12D8uQ01ccp0utIHmjacXYXOu5jNYmttF4njp0GLIXL
Re: Hiding COPY text
To clarify, I would like for COPY IEABRC to appear in the listing, but not any of the statements that IEABRC contains. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Jonathan Scott Sent: Monday, February 26, 2024 8:50 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Hiding COPY text I think we need some clarification of what is meant by a request for PRINT NOGEN for a copy book. What is the intended difference from using PRINT OFF? In the specific case of ASMMSP, that already contains PRINT OFF. If you want to see the source, you will have to look at the copy book or use PCONTROL to override that. To avoid showing a copy book, I would use a sequence such as the following: PUSH PRINT,NOPRINT PRINT OFFCOPY whatever COPY whatever POP PRINT,NOPRINT The comment on the PRINT OFF statement is intended to describe what is being hidden, but if that is not required, the statement can be changed to PRINT OFF,NOPRINT. Jonathan Scott, HLASM IBM Hursley, UK
Re: Macro parameters: parsing a relocatable address
Why? What are you trying to solve by wrappng the MVC in a macro? MVC 0(2),0 ORG *-4 DCS(&OP1) DCS(&OP2) but, again, why? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of David Eisenberg Sent: Monday, February 26, 2024 8:22 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Macro parameters: parsing a relocatable address I’m seeking some guidance if anyone is able to help. I’d like to write a macro like this: &NAMEMYCLC &FIELD1,&FIELD2 in which both &FIELD1 and &FIELD2 are relocatable addresses. It’s &FIELD1 that is of particular interest to me. &FIELD1 might be expressed as a hard-coded displacement and base register, or a relocatable symbol… or it could be an absolute symbol equivalent to a displacement, followed by a base register… etc. I.e., it could be any valid relocatable address syntax. What &FIELD1 will *not* have is an *explicit length.* The macro parameters will specify valid relocatable addresses, and nothing more. My question: I’d like the MYCLC macro to generate a CLC instruction in which the two parameters are compared to each other for a constant length of 2. So far, the only ways I can think of to do this are: 1. Parse &FIELD1 to figure out how the relocatable address is expressed, and insert an explicit length of 2 to generate a valid CLC first operand. I would do it that way, but (unless I'm missing something) it seems quite complex to code. 2. Generate this DC statement: DC X’D501’,S(&FIELD1,&FIELD2) . This seems to work, but it’s a bit unattractive in a PRINT GEN (and it looks a bit odd in the assembly listing, because the assembler doesn't treat it like a machine instruction in the object code on the left side of the listing). I’m wondering if anyone can suggest a reasonable way to code option 1 above. Can the macro assembler give me any help in parsing &FIELD1 so that I can transform that parameter to insert an explicit length, regardless of how &FIELD1 is expressed? Or is there some other approach that I haven’t considered at all? Or should I just go with option 2 above? Please note that I don’t want the macro to generate more than one machine instruction. One way or another, I just want the macro to generate a CLC for a length of 2. (And I really do want the CLC located in the macro as opposed to open code, because the macro does some analysis on the comparands prior to generating the CLC.) Any advice would be appreciated... thank you! David
Re: Hiding COPY text
That don't change anything. I don't have up.date access to those libraries and asking to change the CM process would be DOA.. For personal tools, of course, the exit approach is viable. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Martin Trübner <1237eee49f7e-dmarc-requ...@listserv.uga.edu> Sent: Monday, February 26, 2024 3:22 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Hiding COPY text Shmuel, they are just simple application programs. They need no special rules nor privileges. They must be reachable during HLASM execution, but not reside in a special lib, nor introduced to anyone or defined anywhere. Martin
Re: Hiding COPY text
I'd have to get the exits into the CM environment, which I believe to be politically impossible. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Martin Trübner <1237eee49f7e-dmarc-requ...@listserv.uga.edu> Sent: Sunday, February 25, 2024 11:19 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Hiding COPY text Shmuel, If you can get the parm (or a process)-stmt passed endavour, I can send you the source of the three-in-one-exit. It sits here on my machine. Right now it is coded to supporess copy or macro expansions, if they come from certain libraries, but changing the code to react only on certain copy/macros is a no-brainer. And of course the reaction to suppress everything but the first line regardless of print-stmts. That way someone can alsways have them printed (without the parm/process-stmt) or have the suppression working (with the stmt) Martin Am 23.02.24 um 15:34 schrieb Seymour J Metz: > I don't want to use PRINT OFF for the COPY of ASMMSP or IEABRC, but I don't > want to clutter up the listing. Is there an analog of PRINT NOGEN for code in > a COPY? > > -- > Shmuel (Seymour J.) Metz > http://mason.gmu.edu/~smetz3 > עַם יִשְׂרָאֵל חַי > נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
Re: Hiding COPY text
I'm not sure what Endevor allows but changing the build process is above my pay grade. It's the golden rule: he who has the gold makes the rule. And, yes, there are legitimate reasons for locking down the build process. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Paul Gilmartin <0014e0e4a59b-dmarc-requ...@listserv.uga.edu> Sent: Friday, February 23, 2024 3:32 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Hiding COPY text On 2/23/24 13:12:16, Seymour J Metz wrote: > Configuation Management using Endevor. > . Does Endevor let you define your own build processes as, for example, "make" does (but SMP/E doesn't.) Are you concerned with suppressing the listing of the IEABRC macro definition, or of its expansion? -- gil
Re: Hiding COPY text
Simply? In someone else's controlled environment? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Dave Clark Sent: Friday, February 23, 2024 3:36 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Hiding COPY text "IBM Mainframe Assembler List" wrote on 02/23/2024 12:52:42 PM: > That works for stand-alone assemblies, but I'm not sure whether the > CM process can accommodate it. It doesn't strictly need to. You could "simply" put the following statement (his) at the beginning of your assembler source program and -- voila! Naturally, you would need those exit program in place, too. PROCESS EXIT(INX(EXNAME),LBX(EXNAME),PRX(EXNAME)) Sincerely, Dave Clark -- int.ext: 91078 direct: (937) 531-6378 home: (937) 751-3300 Winsupply Group Services 3110 Kettering Boulevard Dayton, Ohio 45439 USA (937) 294-5331 * This email message and any attachments is for use only by the named addressee(s) and may contain confidential, privileged and/or proprietary information. If you have received this message in error, please immediately notify the sender and delete and destroy the message and all copies. All unauthorized direct or indirect use or disclosure of this message is strictly prohibited. No right to confidentiality or privilege is waived or lost by any error in transmission. *
Re: Hiding COPY text
Configuation Management using Endevor. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Martin Trübner <1237eee49f7e-dmarc-requ...@listserv.uga.edu> Sent: Friday, February 23, 2024 3:04 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Hiding COPY text Shmuel what is "the CM process" ? Martin Am 23.02.24 um 18:52 schrieb Seymour J Metz: > That works for stand-alone assemblies, but I'm not sure whether the CM > process can accommodate it. > > -- > Shmuel (Seymour J.) Metz > http://mason.gmu.edu/~smetz3 > עַם יִשְׂרָאֵל חַי > נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר > > > From: IBM Mainframe Assembler List on > behalf of Martin Trübner<1237eee49f7e-dmarc-requ...@listserv.uga.edu> > Sent: Friday, February 23, 2024 12:06 PM > To:ASSEMBLER-LIST@LISTSERV.UGA.EDU > Subject: Re: Hiding COPY text > > There are exits in HLASM that can be used to suppress printing according > to you own rules. > > > I wrote code to suppress printing of macros and copy-code, if they come > from certain libraries. > > > the PROCESS/PARM for the HLASM must contain > > EXIT(INX(EXNAME),LBX(EXNAME),PRX(EXNAME)) > > > As you can see I did it in three exit-points - all with the same exit > > > Martin > > Am 23.02.24 um 15:34 schrieb Seymour J Metz: >> I don't want to use PRINT OFF for the COPY of ASMMSP or IEABRC, but I don't >> want to clutter up the listing. Is there an analog of PRINT NOGEN for code >> in a COPY? >> >> -- >> Shmuel (Seymour J.) Metz >> http://mason.gmu.edu/~smetz3 >> עַם יִשְׂרָאֵל חַי >> נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
Re: Hiding COPY text
That works for stand-alone assemblies, but I'm not sure whether the CM process can accommodate it. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Martin Trübner <1237eee49f7e-dmarc-requ...@listserv.uga.edu> Sent: Friday, February 23, 2024 12:06 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Hiding COPY text There are exits in HLASM that can be used to suppress printing according to you own rules. I wrote code to suppress printing of macros and copy-code, if they come from certain libraries. the PROCESS/PARM for the HLASM must contain EXIT(INX(EXNAME),LBX(EXNAME),PRX(EXNAME)) As you can see I did it in three exit-points - all with the same exit Martin Am 23.02.24 um 15:34 schrieb Seymour J Metz: > I don't want to use PRINT OFF for the COPY of ASMMSP or IEABRC, but I don't > want to clutter up the listing. Is there an analog of PRINT NOGEN for code in > a COPY? > > -- > Shmuel (Seymour J.) Metz > http://mason.gmu.edu/~smetz3 > עַם יִשְׂרָאֵל חַי > נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
Re: Hiding COPY text
IEABRC is z/OS, but ASMMSP is part of the HLASM Toolkit. Or is the toolkit only for z/OS and z/VM? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Dave Clark Sent: Friday, February 23, 2024 11:31 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Hiding COPY text "IBM Mainframe Assembler List" wrote on 02/23/2024 11:27:00 AM: > Is there anything in ASMMSP or IEABRC that depends on being in open code? I don't have those copybooks (I'm on z/VSE) so someone else will have to answer that question. Sincerely, Dave Clark -- int.ext: 91078 direct: (937) 531-6378 home: (937) 751-3300 Winsupply Group Services 3110 Kettering Boulevard Dayton, Ohio 45439 USA (937) 294-5331 * This email message and any attachments is for use only by the named addressee(s) and may contain confidential, privileged and/or proprietary information. If you have received this message in error, please immediately notify the sender and delete and destroy the message and all copies. All unauthorized direct or indirect use or disclosure of this message is strictly prohibited. No right to confidentiality or privilege is waived or lost by any error in transmission. *
Re: Hiding COPY text
Is there anything in ASMMSP or IEABRC that depends on being in open code? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Dave Clark Sent: Friday, February 23, 2024 9:46 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Hiding COPY text "IBM Mainframe Assembler List" wrote on 02/23/2024 09:34:33 AM: > I don't want to use PRINT OFF for the COPY of ASMMSP or IEABRC, but > I don't want to clutter up the listing. Is there an analog of PRINT > NOGEN for code in a COPY? It sounds like you want the COPY statement to be seen but not heard, so to speak. So, barring a better solution, and just theorizing here... Create your own INCLUDE macro that generates a COPY statement for the macro parameter value. That way a PRINT NOGEN will hide the COPY and its results but the MACRO usage will document the copybook usage, too. Sincerely, Dave Clark -- int.ext: 91078 direct: (937) 531-6378 home: (937) 751-3300 Winsupply Group Services 3110 Kettering Boulevard Dayton, Ohio 45439 USA (937) 294-5331 * This email message and any attachments is for use only by the named addressee(s) and may contain confidential, privileged and/or proprietary information. If you have received this message in error, please immediately notify the sender and delete and destroy the message and all copies. All unauthorized direct or indirect use or disclosure of this message is strictly prohibited. No right to confidentiality or privilege is waived or lost by any error in transmission. *
Hiding COPY text
I don't want to use PRINT OFF for the COPY of ASMMSP or IEABRC, but I don't want to clutter up the listing. Is there an analog of PRINT NOGEN for code in a COPY? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר
Re: How to create a pdf file from Mainframe
I didn't see an equivalent to FCB. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of SHASHANK DEWANGAN Sent: Monday, January 8, 2024 11:31 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: How to create a pdf file from Mainframe If you interested in freeware then try TXT2PDF : TXT2PDF is a mainframe utility program commonly used to convert TEXT files to a PDF file. https://secure-web.cisco.com/19WPr3ySdE3QpqbqAu27VXo10_PAj5NKDuY5pUPPVKWBidSlq_CY5QJdO03-7Z0XjBhwn53_AMDqQEASzXffcFYFaPqq6UO9VKmSvCl0NondfEkK_vCe46ybKGjGFjoaNHb10Dv00F_kZlCxZeWyztZHM4pj_rWgAbuYHSgHl85jHVh1FSDwH1M1q1DRjdaIse-mDB0Fdvz3SDQS8AZ_Rhl0myjxfskvMwNlMMIfiZyHSVBqHDQjfIBe6s0-rg3C-sL3F934lcT7Pby2xpza-0IKrfRRQKJLzPLXkTEqs9oBkR_xpylj6GwAErEAXZRY66P7TxyEFYibgqLc2qW01K7kNX8okbaGWGrFcTKrF4AP25dnKrZsiUrisuIn2vGJM5dGB85em-LmjYAxnbuyfms-yqdBKOzfEPJL4yC1ZI9U/https%3A%2F%2Fwww.homerow.net%2Frexx%2Ftxt2pdf%2F Even AWS Mainframe modernization is utilizing this freeware to generate PDF. They have provided all the stuff like REXX, JCL, Guide etc in the link https://docs.aws.amazon.com/m2/latest/userguide/txt2pdf.html All the best. Regards, Shashank Dewangan On Mon, 8 Jan 2024 at 23:21, sudershan ravi wrote: > Hi Everyone, > > Could someone help me on creating a pdf file from the mainframe job. What > are the options we have? > > Thanks, > Sudershan >
Re: Setting &sysect as CSECT or on using
You're right, and I experimentally confirmed what the manual said. Thanks. So why not MACRO ... &SYSLOC LOCTR MEND which seems to cover everything? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Paul Gilmartin <0014e0e4a59b-dmarc-requ...@listserv.uga.edu> Sent: Wednesday, December 20, 2023 3:30 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Setting &sysect as CSECT or on using On 12/20/23 12:58:41, Seymour J Metz wrote: > Why not > > MACRO > ... > &SYSECT &SYSSTYP > &SYSLOC LOCTR > MEND > . Doesn't &SYSLOC LOCTR imply &SYSECT &SYSSTYP? I don't believe it creates a duplicate-named location counter in a different section. > Is there an RFE for PUSH CSECT, PUSH DSECT or PUSH LOCTR? > . I think Tony's suggestion covers the meager use case. > > From: Tony Harminc > Sent: Wednesday, December 20, 2023 2:46 PM> > MACRO > ... > &N SETC '&SYSECT' > &T SETC '&SYSSTYP' > BLAH DSECT > ... > &N &T > MEND > > is common enough in our code. I can't say I've tried it, but presumably it > would work with an unnamed xSECT. -- gil
Re: Setting &sysect as CSECT or on using
Why not MACRO ... &SYSECT &SYSSTYP &SYSLOC LOCTR MEND Is there an RFE for PUSH CSECT, PUSH DSECT or PUSH LOCTR? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Tony Harminc Sent: Wednesday, December 20, 2023 2:46 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Setting &sysect as CSECT or on using On Wed, 20 Dec 2023 at 13:46, Paul Gilmartin < 0014e0e4a59b-dmarc-requ...@listserv.uga.edu> wrote: > On 12/20/23 09:21:39, Joseph Reichman wrote: > > I understand if I want to make it work I’ll have to break up the macro > into parts finish the fest after I have a CSECT statement > > . > It works as intended as it is. I believe the design objective of > &SYSECT is to allow the coder of a data area DSECT to restore the > caller's environment before exit. > MACRO ... &N SETC '&SYSECT' &T SETC '&SYSSTYP' BLAH DSECT ... &N &T MEND is common enough in our code. I can't say I've tried it, but presumably it would work with an unnamed xSECT. Tony H.
Re: Setting &sysect as CSECT or on using
It doesn't matter where the macro definition is, only where the invocation is. Also, where and to what is &USING set? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Joe Reichman Sent: Tuesday, December 19, 2023 7:53 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Setting &sysect as CSECT or on using The macro was invoked in the context of unnamed csect However the Macro established CSECT would having a macro Whitin a macros solve this I guess the first macro would establish the CSECT allowing me to use &sysect in the second macro thanks -Original Message- From: IBM Mainframe Assembler List On Behalf Of Tony Harminc Sent: Tuesday, December 19, 2023 6:28 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Setting &sysect as CSECT or on using On Tue, 19 Dec 2023 at 18:12, Joseph Reichman wrote: > When I use the following > Using &sysect,12,10 > > &sysect comes up blank even though I know it had been set Thanks > Available only in a macro. Which makes some sense - what would be its use in open code? But you say it's blank? If you're in macro code and your macro was invoked in the context of an unnamed CSECT (or you used START, etc.), then blank would be legit. You say it had been set - by what? Only a label on a CSECT/DSECT/etc. type instruction can set it. Tony H.
Re: Setting &sysect as CSECT or on using
MNOTE *,'&&SYSECT="&SYSECT."; &&USING="&USING."' Also, what do you expect that LAE to do? Note; you can replace the LA, LA pair with a single LAY; shorter, faster and clearer. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Joe Reichman Sent: Tuesday, December 19, 2023 6:33 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Setting &sysect as CSECT or on using 2420+ PRINT ON 50 B240 00E0 2421+ BAKR 14,0 54 51CF 0 2422+ LAE 12,0(15,0) 58 41A0 CFFF00FFF 2423+ LA10,4095(,12) 5C 41A0 A0011 2424+ LA10,1(,10) 60 B247 2425+ MSTA 0 2426+ DROP 15 2427+ MHELP 16 2428+ USING ,12,10 ** ASMA074E Illegal syntax in expression - ,12 Here is the macro code DROP 15 DROP ADDRESSING ON ENTRY POINT MHELP 16 USING &SYSECT,&USING SET ADDRESSING ON BASE REGISTER(SJOER Here is the MHELP dump clearly you can see that &SYSECT is GRECOV THANKS //MHELP ENTRY TO STORAGE MODE SYSTEM PARAMETERS: //SYSVAR NAMELNTH VALUE (5 //SYSNDX 004 0005 //SYSECT 006 GRECOV //SYSLOC 006 GRECOV //SYSTIME 005 18.04 //SYSDATE 008 12/19/23 -Original Message- From: IBM Mainframe Assembler List On Behalf Of Binyamin Dissen Sent: Tuesday, December 19, 2023 6:27 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Setting &sysect as CSECT or on using You know what you failed to include in the post. 'nuff said. On Tue, 19 Dec 2023 18:12:37 -0500 Joseph Reichman wrote: :>Hi :> :>When I use the following :> Using &sysect,12,10 :> :>&sysect comes up blank even though I know it had been set :>Thanks -- Binyamin Dissen http://www.dissensoftware.com/ Director, Dissen Software, Bar & Grill - Israel
Re: Reseting RMODE
is there an RFE for an RMODE(MIN) option to accept multiple RMODE statements and use the most restrictive? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר From: IBM Mainframe Assembler List on behalf of Paul Gilmartin <0014e0e4a59b-dmarc-requ...@listserv.uga.edu> Sent: Monday, December 4, 2023 10:48 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Reseting RMODE (Don't be greedy; don't set personal "Reply-to:") On 12/4/23 07:28:51, João Reginato wrote: > As I've said before, I wasn't clear enough here. > My intent is to change the RMODE during the compilation phase only. > I have all CSECTS with RMODE ANY so, one of them, need to be RMODE 24, and I > cannot change it because the HLASM doesn't allow that. despite it hasn't > finished the compilation of all my csects, issuing the message reported > before. >. Ir would be marginally useful if HLASM, when the programmer codes conflicting RMODE instructions, chose the one most restrictive. But you can simulate this by setting a GBLA wherever any RMODE is needed and choosing the least one with AIF logic near the end of your assembly. -- gil
