date:20140904

[PATCH 4/5] ARM: phyCORE-AM335x: Add support for 2x512MB RAM

2014-09-04 Thread Teresa Gámez

Added settings for 1GB RAM option.

Signed-off-by: Teresa Gámez t.ga...@phytec.de
---
 arch/arm/boards/phytec-phycore-am335x/lowlevel.c |   25 ++
 images/Makefile.am33xx   |4 +++
 2 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c 
b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
index a15e151..66bae80 100644
--- a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
@@ -36,6 +36,7 @@ enum {
MT41J128M16125IT_256MB,
MT41J64M1615IT_128MB,
MT41J256M16HA15EIT_512MB,
+   MT41J512M8125IT_2x512MB,
 };
 
 struct pcm051_sdram_timings timings[] = {
@@ -95,6 +96,25 @@ struct pcm051_sdram_timings timings[] = {
.wr_slave_ratio0= 0x7b,
},
},
+
+   /* 1024MB */
+   [MT41J512M8125IT_2x512MB] = {
+   .regs = {
+   .emif_read_latency  = 0x7,
+   .emif_tim1  = 0x0AAAE4DB,
+   .emif_tim2  = 0x266B7FDA,
+   .emif_tim3  = 0x501F867F,
+   .sdram_config   = 0x61C053B2,
+   .zq_config  = 0x50074BE4,
+   .sdram_ref_ctrl = 0x0C30
+   },
+   .data = {
+   .rd_slave_ratio0= 0x32,
+   .wr_dqs_slave_ratio0= 0x48,
+   .fifo_we_slave_ratio0   = 0x99,
+   .wr_slave_ratio0= 0x80,
+   },
+   },
 };
 
 extern char __dtb_am335x_phytec_phycore_start[];
@@ -169,6 +189,11 @@ ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_512mb, 
bootinfo, r1, r2)
pcm051_board_entry(bootinfo, MT41J256M16HA15EIT_512MB);
 }
 
+ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_2x512mb, bootinfo, r1, r2)
+{
+   pcm051_board_entry(bootinfo, MT41J512M8125IT_2x512MB);
+}
+
 ENTRY_FUNCTION(start_am33xx_phytec_phycore_sdram, r0, r1, r2)
 {
void *fdt;
diff --git a/images/Makefile.am33xx b/images/Makefile.am33xx
index c1f19c1..d24338e 100644
--- a/images/Makefile.am33xx
+++ b/images/Makefile.am33xx
@@ -23,6 +23,10 @@ pblx-$(CONFIG_MACH_PCM051) += 
start_am33xx_phytec_phycore_sram_512mb
 FILE_barebox-am33xx-phytec-phycore-mlo-512mb.img = 
start_am33xx_phytec_phycore_sram_512mb.pblx.mlo
 am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-512mb.img
 
+pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_2x512mb
+FILE_barebox-am33xx-phytec-phycore-mlo-2x512mb.img = 
start_am33xx_phytec_phycore_sram_2x512mb.pblx.mlo
+am33xx-mlo-$(CONFIG_MACH_PCM051) += 
barebox-am33xx-phytec-phycore-mlo-2x512mb.img
+
 pblx-$(CONFIG_MACH_BEAGLEBONE) += start_am33xx_beaglebone_sdram
 FILE_barebox-am33xx-beaglebone.img = start_am33xx_beaglebone_sdram.pblx
 am33xx-barebox-$(CONFIG_MACH_BEAGLEBONE) += barebox-am33xx-beaglebone.img
-- 
1.7.0.4


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[PATCH 2/5] ARM: phyCORE-AM335x: Update RAM Timings

2014-09-04 Thread Teresa Gámez

Increased the RAM frequency to 400MHz.
Recalculation of the RAM timing values was needed.

Signed-off-by: Teresa Gámez t.ga...@phytec.de
---
 arch/arm/boards/phytec-phycore-am335x/lowlevel.c |   70 +++---
 1 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c 
b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
index ff1f04e..ff0b021 100644
--- a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
@@ -16,15 +16,15 @@
 #include debug_ll.h
 
 static const struct am33xx_cmd_control pcm051_cmd = {
-   .slave_ratio0 = 0x40,
+   .slave_ratio0 = 0x80,
.dll_lock_diff0 = 0x0,
-   .invert_clkout0 = 0x1,
-   .slave_ratio1 = 0x40,
+   .invert_clkout0 = 0x0,
+   .slave_ratio1 = 0x80,
.dll_lock_diff1 = 0x0,
-   .invert_clkout1 = 0x1,
-   .slave_ratio2 = 0x40,
+   .invert_clkout1 = 0x0,
+   .slave_ratio2 = 0x80,
.dll_lock_diff2 = 0x0,
-   .invert_clkout2 = 0x1,
+   .invert_clkout2 = 0x0,
 };
 
 struct pcm051_sdram_timings {
@@ -42,57 +42,57 @@ struct pcm051_sdram_timings timings[] = {
/* 1x256M16 */
[MT41J128M16125IT_1x256M16] = {
.regs = {
-   .emif_read_latency  = 0x6,
-   .emif_tim1  = 0x0888A39B,
-   .emif_tim2  = 0x26337FDA,
-   .emif_tim3  = 0x501F830F,
-   .sdram_config   = 0x61C04AB2,
+   .emif_read_latency  = 0x7,
+   .emif_tim1  = 0x0AAAD4DB,
+   .emif_tim2  = 0x26437FDA,
+   .emif_tim3  = 0x501F83FF,
+   .sdram_config   = 0x61C052B2,
.zq_config  = 0x50074BE4,
-   .sdram_ref_ctrl = 0x093B,
+   .sdram_ref_ctrl = 0x0C30,
},
.data = {
.rd_slave_ratio0= 0x3B,
-   .wr_dqs_slave_ratio0= 0x3B,
-   .fifo_we_slave_ratio0   = 0x97,
-   .wr_slave_ratio0= 0x76,
+   .wr_dqs_slave_ratio0= 0x33,
+   .fifo_we_slave_ratio0   = 0x9c,
+   .wr_slave_ratio0= 0x6f,
},
},
 
/* 1x128M16 */
[MT41J64M1615IT_1x128M16] = {
.regs =  {
-   .emif_read_latency  = 0x6,
-   .emif_tim1  = 0x0888A39B,
-   .emif_tim2  = 0x26247FDA,
-   .emif_tim3  = 0x501F821F,
-   .sdram_config   = 0x61C04A32,
+   .emif_read_latency  = 0x7,
+   .emif_tim1  = 0x0AAAE4DB,
+   .emif_tim2  = 0x262F7FDA,
+   .emif_tim3  = 0x501F82BF,
+   .sdram_config   = 0x61C05232,
.zq_config  = 0x50074BE4,
-   .sdram_ref_ctrl = 0x093B,
+   .sdram_ref_ctrl = 0x0C30,
},
.data = {
-   .rd_slave_ratio0= 0x3A,
-   .wr_dqs_slave_ratio0= 0x36,
+   .rd_slave_ratio0= 0x38,
+   .wr_dqs_slave_ratio0= 0x34,
.fifo_we_slave_ratio0   = 0xA2,
-   .wr_slave_ratio0= 0x74,
+   .wr_slave_ratio0= 0x72,
},
},
 
/* 1x512MB */
[MT41J256M16HA15EIT_1x512M16] = {
.regs = {
-   .emif_read_latency  = 0x6,
-   .emif_tim1  = 0x0888A39B,
-   .emif_tim2  = 0x26517FDA,
-   .emif_tim3  = 0x501F84EF,
-   .sdram_config   = 0x61C04B32,
+   .emif_read_latency  = 0x7,
+   .emif_tim1  = 0x0AAAE4DB,
+   .emif_tim2  = 0x266B7FDA,
+   .emif_tim3  = 0x501F867F,
+   .sdram_config   = 0x61C05332,
.zq_config  = 0x50074BE4,
-   .sdram_ref_ctrl = 0x093B,
+   .sdram_ref_ctrl = 0x0C30
},
.data = {
-   .rd_slave_ratio0= 0x3B,
-   .wr_dqs_slave_ratio0= 0x3B,
-   .fifo_we_slave_ratio0   = 0x96,
-

[PATCH 5/5] ARM: phyCORE-AM335x: Update partition table

2014-09-04 Thread Teresa Gámez

Added device tree partition and made rootfs partition
variable size depending on nand flash size.

Signed-off-by: Teresa Gámez t.ga...@phytec.de
---
 arch/arm/dts/am335x-phytec-phycore.dts |   22 ++
 1 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/am335x-phytec-phycore.dts 
b/arch/arm/dts/am335x-phytec-phycore.dts
index 16febd3..047dc15 100644
--- a/arch/arm/dts/am335x-phytec-phycore.dts
+++ b/arch/arm/dts/am335x-phytec-phycore.dts
@@ -194,8 +194,13 @@
};
 
partition@3 {
+   label = oftree;
+   reg = 0xc 0x2;
+   };
+
+   partition@4 {
label = kernel;
-   reg = 0xc 0x40;
+   reg = 0xe 0x40;
};
};
 };
@@ -305,13 +310,22 @@
};
 
partition@6 {
-   label = kernel;
-   reg = 0x12 0x80;
+   label = oftree;
+   reg = 0x12 0x2;
};
 
partition@7 {
+   label = kernel;
+   reg = 0x14 0x80;
+   };
+
+   partition@8 {
label = root;
-   reg = 0x92 0x1f6e;
+   /*
+* Size 0x0 extends partition to
+* end of nand flash.
+*/
+   reg = 0x92 0x0;
};
};
 };
-- 
1.7.0.4


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[PATCH 3/5] ARM: phyCORE-AM335x: Fixup RAM setting naming

2014-09-04 Thread Teresa Gámez

Naming is confusing and wrong. Fixed it up.

Signed-off-by: Teresa Gámez t.ga...@phytec.de
---
 arch/arm/boards/phytec-phycore-am335x/lowlevel.c |   30 +++---
 images/Makefile.am33xx   |   18 ++--
 2 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c 
b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
index ff0b021..a15e151 100644
--- a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c
@@ -33,14 +33,14 @@ struct pcm051_sdram_timings {
 };
 
 enum {
-   MT41J128M16125IT_1x256M16,
-   MT41J64M1615IT_1x128M16,
-   MT41J256M16HA15EIT_1x512M16,
+   MT41J128M16125IT_256MB,
+   MT41J64M1615IT_128MB,
+   MT41J256M16HA15EIT_512MB,
 };
 
 struct pcm051_sdram_timings timings[] = {
-   /* 1x256M16 */
-   [MT41J128M16125IT_1x256M16] = {
+   /* 256MB */
+   [MT41J128M16125IT_256MB] = {
.regs = {
.emif_read_latency  = 0x7,
.emif_tim1  = 0x0AAAD4DB,
@@ -58,8 +58,8 @@ struct pcm051_sdram_timings timings[] = {
},
},
 
-   /* 1x128M16 */
-   [MT41J64M1615IT_1x128M16] = {
+   /* 128MB */
+   [MT41J64M1615IT_128MB] = {
.regs =  {
.emif_read_latency  = 0x7,
.emif_tim1  = 0x0AAAE4DB,
@@ -77,8 +77,8 @@ struct pcm051_sdram_timings timings[] = {
},
},
 
-   /* 1x512MB */
-   [MT41J256M16HA15EIT_1x512M16] = {
+   /* 512MB */
+   [MT41J256M16HA15EIT_512MB] = {
.regs = {
.emif_read_latency  = 0x7,
.emif_tim1  = 0x0AAAE4DB,
@@ -154,19 +154,19 @@ static noinline void pcm051_board_entry(unsigned long 
bootinfo, int sdram)
pcm051_board_init(sdram);
 }
 
-ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_1x256m16, bootinfo, r1, r2)
+ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_256mb, bootinfo, r1, r2)
 {
-   pcm051_board_entry(bootinfo, MT41J128M16125IT_1x256M16);
+   pcm051_board_entry(bootinfo, MT41J128M16125IT_256MB);
 }
 
-ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_1x128m16, bootinfo, r1, r2)
+ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_128mb, bootinfo, r1, r2)
 {
-   pcm051_board_entry(bootinfo, MT41J64M1615IT_1x128M16);
+   pcm051_board_entry(bootinfo, MT41J64M1615IT_128MB);
 }
 
-ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_1x512m16, bootinfo, r1, r2)
+ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram_512mb, bootinfo, r1, r2)
 {
-   pcm051_board_entry(bootinfo, MT41J256M16HA15EIT_1x512M16);
+   pcm051_board_entry(bootinfo, MT41J256M16HA15EIT_512MB);
 }
 
 ENTRY_FUNCTION(start_am33xx_phytec_phycore_sdram, r0, r1, r2)
diff --git a/images/Makefile.am33xx b/images/Makefile.am33xx
index fa1f848..c1f19c1 100644
--- a/images/Makefile.am33xx
+++ b/images/Makefile.am33xx
@@ -11,17 +11,17 @@ pblx-$(CONFIG_MACH_PCM051) += 
start_am33xx_phytec_phycore_sdram
 FILE_barebox-am33xx-phytec-phycore.img = start_am33xx_phytec_phycore_sdram.pblx
 am33xx-barebox-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore.img
 
-pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_1x256m16
-FILE_barebox-am33xx-phytec-phycore-mlo-1x256m16.img = 
start_am33xx_phytec_phycore_sram_1x256m16.pblx.mlo
-am33xx-mlo-$(CONFIG_MACH_PCM051) += 
barebox-am33xx-phytec-phycore-mlo-1x256m16.img
+pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_256mb
+FILE_barebox-am33xx-phytec-phycore-mlo-256mb.img = 
start_am33xx_phytec_phycore_sram_256mb.pblx.mlo
+am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-256mb.img
 
-pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_1x128m16
-FILE_barebox-am33xx-phytec-phycore-mlo-1x128m16.img = 
start_am33xx_phytec_phycore_sram_1x128m16.pblx.mlo
-am33xx-mlo-$(CONFIG_MACH_PCM051) += 
barebox-am33xx-phytec-phycore-mlo-1x128m16.img
+pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_128mb
+FILE_barebox-am33xx-phytec-phycore-mlo-128mb.img = 
start_am33xx_phytec_phycore_sram_128mb.pblx.mlo
+am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-128mb.img
 
-pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_1x512m16
-FILE_barebox-am33xx-phytec-phycore-mlo-1x512m16.img = 
start_am33xx_phytec_phycore_sram_1x512m16.pblx.mlo
-am33xx-mlo-$(CONFIG_MACH_PCM051) += 
barebox-am33xx-phytec-phycore-mlo-1x512m16.img
+pblx-$(CONFIG_MACH_PCM051) += start_am33xx_phytec_phycore_sram_512mb
+FILE_barebox-am33xx-phytec-phycore-mlo-512mb.img = 
start_am33xx_phytec_phycore_sram_512mb.pblx.mlo
+am33xx-mlo-$(CONFIG_MACH_PCM051) += barebox-am33xx-phytec-phycore-mlo-512mb.img
 
 pblx-$(CONFIG_MACH_BEAGLEBONE) += start_am33xx_beaglebone_sdram
 FILE_barebox-am33xx-beaglebone.img = start_am33xx_beaglebone_sdram.pblx
-- 
1.7.0.4

[PATCH 1/5] ARM: phyCORE-AM335x: Updated SPI NOR dts entries

2014-09-04 Thread Teresa Gámez

Updated the SPI NOR flash entries. NOR flash got
detected but did not work.

- Updated muxing
- Fixed frequency
- Fixed CS
- Removed first compatible entry (the flashes used is changing frequently)

Signed-off-by: Teresa Gámez t.ga...@phytec.de
---
 arch/arm/dts/am335x-phytec-phycore.dts |   14 +++---
 1 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/dts/am335x-phytec-phycore.dts 
b/arch/arm/dts/am335x-phytec-phycore.dts
index 5678138..16febd3 100644
--- a/arch/arm/dts/am335x-phytec-phycore.dts
+++ b/arch/arm/dts/am335x-phytec-phycore.dts
@@ -50,10 +50,10 @@
 
spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins = 
-   0x150 (INPUT_EN | MUX_MODE0)
-   0x154 (PULL_UP | INPUT_EN | MUX_MODE0)
-   0x158 (INPUT_EN | MUX_MODE0)
-   0x15c (PULL_UP | INPUT_EN | MUX_MODE0)
+   0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* 
spi0_clk.spi0_clk */
+   0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* 
spi0_d0.spi0_d0 */
+   0x158 (PIN_INPUT_PULLUP | MUX_MODE0)/* 
spi0_d1.spi0_d1 */
+   0x15c (PIN_INPUT_PULLUP | MUX_MODE0)/* 
spi0_cs0.spi0_cs0 */
;
};
 
@@ -172,9 +172,9 @@
status = okay;
 
flash: m25p80 {
-   compatible = sst,sst25vf032b, m25p80;
-   spi-max-frequency = 1500;
-   reg = 1;
+   compatible = m25p80;
+   spi-max-frequency = 4800;
+   reg = 0;
#address-cells = 1;
#size-cells = 1;
 
-- 
1.7.0.4


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Re: [PATCH 5/5] ARM: phyCORE-AM335x: Update partition table

2014-09-04 Thread Alexander Aring

Hi Teresa,

On Thu, Sep 04, 2014 at 08:50:40AM +0200, Teresa Gámez wrote:
 Added device tree partition and made rootfs partition
 variable size depending on nand flash size.
 
 Signed-off-by: Teresa Gámez t.ga...@phytec.de
 ---
  arch/arm/dts/am335x-phytec-phycore.dts |   22 ++
  1 files changed, 18 insertions(+), 4 deletions(-)
 
 diff --git a/arch/arm/dts/am335x-phytec-phycore.dts 
 b/arch/arm/dts/am335x-phytec-phycore.dts
 index 16febd3..047dc15 100644
 --- a/arch/arm/dts/am335x-phytec-phycore.dts
 +++ b/arch/arm/dts/am335x-phytec-phycore.dts
 @@ -194,8 +194,13 @@
   };
  
   partition@3 {
 + label = oftree;
 + reg = 0xc 0x2;
 + };
 +
 + partition@4 {
   label = kernel;
 - reg = 0xc 0x40;
 + reg = 0xe 0x40;
   };
   };
  };
 @@ -305,13 +310,22 @@
   };
  
   partition@6 {
 - label = kernel;
 - reg = 0x12 0x80;
 + label = oftree;
 + reg = 0x12 0x2;
   };
  
   partition@7 {
 + label = kernel;
 + reg = 0x14 0x80;
 + };
 +
 + partition@8 {
   label = root;
 - reg = 0x92 0x1f6e;
 + /*
 +  * Size 0x0 extends partition to
 +  * end of nand flash.
 +  */
 + reg = 0x92 0x0;

I think this should be 0x94 insead 0x92.

From partition7 7 kernel you have 0x14 + 0x80 = 0x94.

I simple use the gnome-calculator in hex mode to check it.

- Alex

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Re: [PATCH 5/5] ARM: phyCORE-AM335x: Update partition table

2014-09-04 Thread Alexander Aring

On Thu, Sep 04, 2014 at 09:12:58AM +0200, Alexander Aring wrote:
 Hi Teresa,
 
 On Thu, Sep 04, 2014 at 08:50:40AM +0200, Teresa Gámez wrote:
  Added device tree partition and made rootfs partition
  variable size depending on nand flash size.
  
  Signed-off-by: Teresa Gámez t.ga...@phytec.de
  ---
   arch/arm/dts/am335x-phytec-phycore.dts |   22 ++
   1 files changed, 18 insertions(+), 4 deletions(-)
  
  diff --git a/arch/arm/dts/am335x-phytec-phycore.dts 
  b/arch/arm/dts/am335x-phytec-phycore.dts
  index 16febd3..047dc15 100644
  --- a/arch/arm/dts/am335x-phytec-phycore.dts
  +++ b/arch/arm/dts/am335x-phytec-phycore.dts
  @@ -194,8 +194,13 @@
  };
   
  partition@3 {
  +   label = oftree;
  +   reg = 0xc 0x2;
  +   };
  +
  +   partition@4 {
  label = kernel;
  -   reg = 0xc 0x40;
  +   reg = 0xe 0x40;
  };
  };
   };
  @@ -305,13 +310,22 @@
  };
   
  partition@6 {
  -   label = kernel;
  -   reg = 0x12 0x80;
  +   label = oftree;
  +   reg = 0x12 0x2;
  };
   
  partition@7 {
  +   label = kernel;
  +   reg = 0x14 0x80;
  +   };
  +
  +   partition@8 {
  label = root;
  -   reg = 0x92 0x1f6e;
  +   /*
  +* Size 0x0 extends partition to
  +* end of nand flash.
  +*/
  +   reg = 0x92 0x0;
 
 I think this should be 0x94 insead 0x92.
 
 From partition7 7 kernel you have 0x14 + 0x80 = 0x94.
 
 I simple use the gnome-calculator in hex mode to check it.
 

But in this case it was very obviously. Can't have a two in this
position. :-)

- Alex

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Re: [PATCH] Documentation: .gitignore: ignore 'commands/' generated directory

2014-09-04 Thread Sascha Hauer

On Wed, Sep 03, 2014 at 07:16:39PM +0400, Antony Pavlov wrote:
 Signed-off-by: Antony Pavlov antonynpav...@gmail.com

Applied, thanks

Sascha

 ---
  Documentation/.gitignore | 1 +
  1 file changed, 1 insertion(+)
 
 diff --git a/Documentation/.gitignore b/Documentation/.gitignore
 index 1454566..5c36dc3 100644
 --- a/Documentation/.gitignore
 +++ b/Documentation/.gitignore
 @@ -1,2 +1,3 @@
  build
 +commands
  html
 -- 
 2.1.0
 
 
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Re: [PATCH v3 2/3] pinctrl: at91: add pinctrl driver

2014-09-04 Thread Sascha Hauer

On Wed, Sep 03, 2014 at 05:10:33PM +0200, Raphaël Poggi wrote:
 This patch is perfect :-). You just miss to check the return value in
 at91_gpio_probe.
 
 Do I have to integrate this patch in mine ? or you will apply it yourself ?

I just added the return value check, squashed the patch into your
pinctrl driver patch and applied to -next.

Sascha


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[PATCH] Fix barebox metadata

2014-09-04 Thread Philipp Zabel

Patch 97e81f2d78f3 (Add support for metadata in barebox images)
writes the wrong length for the model tag in the barebox metadata.
Fix this to use the correct value.

Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
 scripts/gen-dtb-s | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/gen-dtb-s b/scripts/gen-dtb-s
index 434612f..a920495 100755
--- a/scripts/gen-dtb-s
+++ b/scripts/gen-dtb-s
@@ -36,7 +36,7 @@ if [ $imd = y ]; then
if [ $model != notfound ]; then
modellen=$($FDTGET -t s $dtb / model | wc -c)
le32 0x640c8004
-   le32 $compatlen
+   le32 $modellen
echo .byte  $model
echo .balign 4
fi
-- 
2.0.1


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Re: [PATCH v3 2/3] pinctrl: at91: add pinctrl driver

2014-09-04 Thread Raphaël Poggi

Perfect thank you, so I just have to send one patch for the gpio clock
registration.

2014-09-04 11:26 GMT+02:00 Sascha Hauer s.ha...@pengutronix.de:
 On Wed, Sep 03, 2014 at 05:10:33PM +0200, Raphaël Poggi wrote:
 This patch is perfect :-). You just miss to check the return value in
 at91_gpio_probe.

 Do I have to integrate this patch in mine ? or you will apply it yourself ?

 I just added the return value check, squashed the patch into your
 pinctrl driver patch and applied to -next.

 Sascha


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Re: [PATCH] Fix barebox metadata

2014-09-04 Thread Sascha Hauer

On Thu, Sep 04, 2014 at 11:28:20AM +0200, Philipp Zabel wrote:
 Patch 97e81f2d78f3 (Add support for metadata in barebox images)
 writes the wrong length for the model tag in the barebox metadata.
 Fix this to use the correct value.
 
 Signed-off-by: Philipp Zabel p.za...@pengutronix.de

Applied, thanks

Sascha

 ---
  scripts/gen-dtb-s | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/scripts/gen-dtb-s b/scripts/gen-dtb-s
 index 434612f..a920495 100755
 --- a/scripts/gen-dtb-s
 +++ b/scripts/gen-dtb-s
 @@ -36,7 +36,7 @@ if [ $imd = y ]; then
   if [ $model != notfound ]; then
   modellen=$($FDTGET -t s $dtb / model | wc -c)
   le32 0x640c8004
 - le32 $compatlen
 + le32 $modellen
   echo .byte  $model
   echo .balign 4
   fi
 -- 
 2.0.1
 
 

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v2014.09.0

2014-09-04 Thread Sascha Hauer

Hi All,

After a long long holiday we have a September release.

ome highlights for this release are:

- barebox now has RTC support
- Marvell MVEBU support has gained i2c and PCIe support
- Canon PowerShot A1100 IS support
- Freescale P1010 SoC support
- barebox now runs as EFI payload on X86-64 systems
- USB Host and device support has improved: Correct device hierarchy,
  detect USB devices multiple times, Android Fastboot support

Here comes the detailed list of patches that went into this release.

Sascha


Andreas Pretzsch (1):
  scripts: gitignore: update based on Makefile

Andrey Panov (1):
  ARM: i.MX6Q: Add support for Embedsky E9 board.

Antony Pavlov (40):
  i2c: import SMBus stuff from linux
  gpio: add driver for PCA95[357]x, PCA9698, TCA64xx, and MAX7310 SMBus I/O 
expanders
  Documentation: add virt2real barebox mini-howto
  commands: usb: add tree view capability
  usb: ehci: use linux-way ehci_readl and ehci_writel
  treewide: drop Doxygen stuff
  Makefile: clean barebox.zynq
  led: try to get LED's label from the 'label' property
  ARM: add ARM946E-S CPU type
  ARM: add very initial support for Canon DIGIC chips
  clocksource: add driver for Canon DIGIC timer
  serial: add driver for Canon DIGIC UART
  gpio: add driver for Canon DIGIC
  ARM: DIGIC: add Canon PowerShot A1100 IS support
  lib: import 'bcd' from linux-3.15
  Add a simple rtc framework
  i2c: add Marvell 64xxx driver
  i2c: busses/Makefile: fix indentation
  MIPS: dts: rzx50.dts: add LCD backlight
  MIPS: ritmix-rzx50_defconfig: enable LED-related stuff
  led: triggers: fix crash on disabling default-on trigger
  commands: trigger: check trigger disable return code too
  led: triggers: fix no previous prototype for 'trigger_init' warning
  watchdog: add minimal jz4740 driver
  watchdog: i.MX: check requested mem region in imx_wd_probe()
  ARM: add Canon A1100 ROM image generation
  ARM: DIGIC: add canon-a1100_defconfig
  Documentation: add QEMU Canon A1100 barebox mini-howto
  rtc: import ds1307 driver from linux-3.15
  commands: add hwclock
  ARM: versatilepb_defconfig: enable RTC support
  rtc-lib: import rtc_time_to_tm() from linux-3.15
  rtc: add jz4740 driver
  MIPS: dts: jz4755.dtsi: add jz4740-rtc
  MIPS: ritmix-rzx50_defconfig: enable RTC support
  MIPS: add support for metadata in barebox images
  MIPS: qemu-malta_defconfig: enable metadata in barebox image (IMD)
  openrisc: add barebox.lds to .gitignore
  scripts: add bareboximd{,-target} to .gitignore
  Documentation: .gitignore: ignore 'commands/' generated directory

Beniamino Galvani (2):
  mfd: syscon: add device tree support
  pinctrl: rockchip: add support for new DT bindings

Bo Shen (1):
  mci: core: the sd1.0 card can work in 4 bits mode

Ezequiel Garcia (5):
  net: phy: Add fallbacks for the obsoletes phy DT properties
  net: phy: mdio-mvebu: Make the clock property required
  net: phy: Add minimal support for QSGMII PHY
  trivial: Correct word spelling, s/miscelleanous/miscellaneous
  bus: mvebu: fix ranges fixup

Herve Codina (1):
  hush: Fix error code returned value

Holger Schurig (7):
  Documentation: remove all all in help's help text.
  Documentation: lowercase help short texts
  Documentation: only write changed *.rst files
  Documentation: change generated help lines
  Documentation: revamp dfu's help text
  sandbox: disable bareboxcrc32 in sandbox mode
  sandbox: allow make ARCH=sandbox allyesconfig

Jan Luebbe (1):
  Documentation: use command groups

Jean-Christophe PLAGNIOL-VILLARD (1):
  EFI: introduce efi_strguid to convert GUID to human readable names

Juergen Borleis (4):
  saveenv: make clear how to use the command's parameters
  envfs: provide an intentional way to ignore an existing external 
environment
  envfs: change API to be able to forward special flags into the envfs 
superblock
  saveenv: provide a zeroed/empty/ignore environment

Lucas Stach (4):
  Makefile.lib: imxcfg: fix include path
  scripts: imx-image: add input validation to mw
  arm: mach-imx: add MMDC and CCM register defines for use in DCD
  arm: nitrogen6x: new memory setup from BD u-boot

Markus Pargmann (2):
  mfd: mc34704: Add DT support
  include/bbu: Add missing include errno.h

Matteo Fortini (3):
  sama5d3x: fix HSMC MODE register offset and add TIMINGS register
  sama5d3x: HSMC NAND initialize TIMINGS and import values from U-Boot
  ARM: atmel: sama5d3_xplained: import smc timing from U-Boot

Michael Olbrich (2):
  EFI: fix error handling in efi_get_boot()
  EFI: add missing include

Philipp Zabel (1):
  Fix barebox metadata

Raphael Poggi (5):
  i2c: omap: fix typo in dt_ids
  mtd:

[PATCH v3 0/4] firmware programming interface

2014-09-04 Thread Steffen Trumtrar

Hi!

Changes since v2:

- don't forget to call the close hook
- change compatible to make it clear that passive-serial means a fpga 
programming mode
- minor cleanup

The interface was tested on a Socfpga SoCkit board with v2014.08.0.

Regards,
Steffen

Juergen Beisert (2):
  Add a Firmware programming framework
  Firmware: provide a handler to program Altera FPGAs

Sascha Hauer (2):
  DT: Add binding for Altera FPGAs in passive-serial mode
  Firmware: socfpga: Add SoCFPGA FPGA program support

 .../bindings/firmware/altr,passive-serial.txt  |  13 +
 arch/arm/dts/socfpga.dtsi  |   6 +
 arch/arm/mach-socfpga/Makefile |   1 +
 arch/arm/mach-socfpga/include/mach/socfpga-regs.h  |   2 +
 commands/Kconfig   |   9 +
 commands/Makefile  |   1 +
 commands/firmwareload.c|  66 
 common/Kconfig |   3 +
 common/Makefile|   1 +
 common/firmware.c  | 211 ++
 drivers/Kconfig|   1 +
 drivers/Makefile   |   1 +
 drivers/firmware/Kconfig   |  14 +
 drivers/firmware/Makefile  |   2 +
 drivers/firmware/altera_serial.c   | 315 +++
 drivers/firmware/socfpga.c | 440 +
 include/firmware.h |  42 ++
 17 files changed, 1128 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/firmware/altr,passive-serial.txt
 create mode 100644 commands/firmwareload.c
 create mode 100644 common/firmware.c
 create mode 100644 drivers/firmware/Kconfig
 create mode 100644 drivers/firmware/Makefile
 create mode 100644 drivers/firmware/altera_serial.c
 create mode 100644 drivers/firmware/socfpga.c
 create mode 100644 include/firmware.h

-- 
2.1.0


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[PATCH v3 1/4] Add a Firmware programming framework

2014-09-04 Thread Steffen Trumtrar

From: Juergen Beisert j...@pengutronix.de

This framework handles a list of registered Firmware programming handlers
to unify a firmware programming interface by hiding the details how
to program a specific Firmware in its handler. This is created with FPGAs
in mind but should be usable for other devices aswell.
A user has two possibilities to load a firmware. A device file is create
under /dev/ which can be used to copy a firmware to. Additionally a
firmwareload command is introduced which can list the registered firmware
handlers and also to upload a firmware.

Signed-off-by: Juergen Beisert j...@pengutronix.de
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
Changes since v2:
- actually call mgr-handler-close(mgr-handler) in the close hook

 commands/Kconfig|   9 +++
 commands/Makefile   |   1 +
 commands/firmwareload.c |  66 +++
 common/Kconfig  |   3 +
 common/Makefile |   1 +
 common/firmware.c   | 211 
 include/firmware.h  |  42 ++
 7 files changed, 333 insertions(+)
 create mode 100644 commands/firmwareload.c
 create mode 100644 common/firmware.c
 create mode 100644 include/firmware.h

diff --git a/commands/Kconfig b/commands/Kconfig
index 61816f51159b..a6ca2722f5f6 100644
--- a/commands/Kconfig
+++ b/commands/Kconfig
@@ -1883,6 +1883,15 @@ config CMD_BAREBOX_UPDATE
  -yautom. use 'yes' when asking confirmations
  -f LEVEL  set force level
 
+config CMD_FIRMWARELOAD
+   bool
+   select FIRMWARE
+   prompt firmwareload
+   help
+ Provides the firmwareload command which deals with devices which 
need
+ firmware to work. It is also used to upload firmware to FPGA devices.
+
+
 config CMD_LINUX_EXEC
bool linux exec
depends on LINUX
diff --git a/commands/Makefile b/commands/Makefile
index d42aca5c0c99..2897a796bd44 100644
--- a/commands/Makefile
+++ b/commands/Makefile
@@ -100,3 +100,4 @@ obj-$(CONFIG_CMD_MENUTREE)  += menutree.o
 obj-$(CONFIG_CMD_2048) += 2048.o
 obj-$(CONFIG_CMD_REGULATOR)+= regulator.o
 obj-$(CONFIG_CMD_LSPCI)+= lspci.o
+obj-$(CONFIG_CMD_FIRMWARELOAD) += firmwareload.o
diff --git a/commands/firmwareload.c b/commands/firmwareload.c
new file mode 100644
index ..a2596951a795
--- /dev/null
+++ b/commands/firmwareload.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2013 Juergen Beisert ker...@pengutronix.de, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include command.h
+#include getopt.h
+#include firmware.h
+
+static int do_firmwareload(int argc, char *argv[])
+{
+   int ret, opt;
+   const char *name = NULL, *firmware;
+   struct firmware_mgr *mgr;
+
+   while ((opt = getopt(argc, argv, t:l))  0) {
+   switch (opt) {
+   case 't':
+   name = optarg;
+   break;
+   case 'l':
+   firmwaremgr_list_handlers();
+   return 0;
+   default:
+   return COMMAND_ERROR_USAGE;
+   }
+   }
+
+   if (!(argc - optind))
+   return COMMAND_ERROR_USAGE;
+
+   firmware = argv[optind];
+
+   mgr = firmwaremgr_find(name);
+
+   if (!mgr) {
+   printf(No such programming handler found: %s\n,
+   name ? name : default);
+   return 1;
+   }
+
+   ret = firmwaremgr_load_file(mgr, firmware);
+
+   return ret;
+}
+
+BAREBOX_CMD_HELP_START(firmwareload)
+BAREBOX_CMD_HELP_TEXT(Options:)
+BAREBOX_CMD_HELP_OPT(-t target, define the firmware handler by name\n)
+BAREBOX_CMD_HELP_OPT(-l\t, list devices capable of firmware loading\n)
+BAREBOX_CMD_HELP_END
+
+BAREBOX_CMD_START(firmwareload)
+   .cmd = do_firmwareload,
+   BAREBOX_CMD_DESC(Program a firmware file into a device)
+   BAREBOX_CMD_HELP(cmd_firmwareload_help)
+BAREBOX_CMD_END
diff --git a/common/Kconfig b/common/Kconfig
index bba7f159c1da..b90237fb81fd 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -301,6 +301,9 @@ config CBSIZE
prompt Buffer size for input from the Console
default 1024
 
+config FIRMWARE
+   bool
+
 choice
prompt Select your shell
 
diff --git a/common/Makefile b/common/Makefile
index 204241c919cd..ed5f4fba23e0 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -44,6 +44,7 @@

[PATCH v3 4/4] Firmware: socfpga: Add SoCFPGA FPGA program support

2014-09-04 Thread Steffen Trumtrar

From: Sascha Hauer s.ha...@pengutronix.de

Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
---
Changes since v2:
- be sure to clear nce bit to allow HPS configuration

 arch/arm/dts/socfpga.dtsi |   6 +
 arch/arm/mach-socfpga/Makefile|   1 +
 arch/arm/mach-socfpga/include/mach/socfpga-regs.h |   2 +
 drivers/firmware/Kconfig  |   3 +
 drivers/firmware/Makefile |   1 +
 drivers/firmware/socfpga.c| 440 ++
 6 files changed, 453 insertions(+)
 create mode 100644 drivers/firmware/socfpga.c

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 3368b459d030..afac867c991d 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -465,6 +465,12 @@
status = disabled;
};
 
+   fpgamgr@ff706000 {
+   compatible = altr,socfpga-fpga-mgr;
+   reg = 0xff706000 0x1000,
+ 0xffb9 0x1000;
+   };
+
gpio0: gpio@ff708000 {
compatible = snps,dw-apb-gpio;
reg = 0xff708000 0x1000;
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index d8bf0674306e..12585c547673 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -2,3 +2,4 @@ obj-y += generic.o nic301.o bootsource.o reset-manager.o
 pbl-y += init.o freeze-controller.o scan-manager.o system-manager.o
 pbl-y += clock-manager.o iocsr-config-cyclone5.o
 obj-$(CONFIG_ARCH_SOCFPGA_XLOAD) += xload.o
+obj-$(CONFIG_ARCH_SOCFPGA_FPGA) += fpga.o
diff --git a/arch/arm/mach-socfpga/include/mach/socfpga-regs.h 
b/arch/arm/mach-socfpga/include/mach/socfpga-regs.h
index 9d1e677cb736..b124ed675cfc 100644
--- a/arch/arm/mach-socfpga/include/mach/socfpga-regs.h
+++ b/arch/arm/mach-socfpga/include/mach/socfpga-regs.h
@@ -2,10 +2,12 @@
 #define __MACH_SOCFPGA_REGS_H
 
 #define CYCLONE5_SDMMC_ADDRESS 0xff704000
+#define CYCLONE5_FPGAMGRREGS_ADDRESS   0xff706000
 #define CYCLONE5_GPIO0_BASE0xff708000
 #define CYCLONE5_GPIO1_BASE0xff709000
 #define CYCLONE5_GPIO2_BASE0xff70A000
 #define CYCLONE5_L3REGS_ADDRESS0xff80
+#define CYCLONE5_FPGAMGRDATA_ADDRESS   0xffb9
 #define CYCLONE5_UART0_ADDRESS 0xffc02000
 #define CYCLONE5_UART1_ADDRESS 0xffc03000
 #define CYCLONE5_SDR_ADDRESS   0xffc2
diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
index 28a173b63f2a..58660632519e 100644
--- a/drivers/firmware/Kconfig
+++ b/drivers/firmware/Kconfig
@@ -8,4 +8,7 @@ config FIRMWARE_ALTERA_SERIAL
  Programming an Altera FPGA via a few GPIOs for the control lines and
  MOSI, MISO and clock from an SPI interface for the data lines
 
+config FIRMWARE_ALTERA_SOCFPGA
+   bool Altera SoCFPGA fpga loader
+
 endmenu
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index ec6a5a17083d..c3a3c3400485 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_FIRMWARE_ALTERA_SERIAL) += altera_serial.o
+obj-$(CONFIG_FIRMWARE_ALTERA_SOCFPGA) += socfpga.o
diff --git a/drivers/firmware/socfpga.c b/drivers/firmware/socfpga.c
new file mode 100644
index ..a5dc6072aab4
--- /dev/null
+++ b/drivers/firmware/socfpga.c
@@ -0,0 +1,440 @@
+/*
+ *
+ * Copyright (C) 2012 Altera Corporation www.altera.com
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *  - Neither the name of the Altera Corporation nor the
+ *names of its contributors may be used to endorse or promote products
+ *derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY

[PATCH v3 2/4] Firmware: provide a handler to program Altera FPGAs

2014-09-04 Thread Steffen Trumtrar

From: Juergen Beisert j...@pengutronix.de

This handler uses a regular SPI master and a few GPIOs to program an
Altera FPGA in serial mode.

Signed-off-by: Juergen Beisert j...@pengutronix.de
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
Changes since v2:
- use udelay
- check gpio_set_* return values

 drivers/Kconfig  |   1 +
 drivers/Makefile |   1 +
 drivers/firmware/Kconfig |  11 ++
 drivers/firmware/Makefile|   1 +
 drivers/firmware/altera_serial.c | 315 +++
 5 files changed, 329 insertions(+)
 create mode 100644 drivers/firmware/Kconfig
 create mode 100644 drivers/firmware/Makefile
 create mode 100644 drivers/firmware/altera_serial.c

diff --git a/drivers/Kconfig b/drivers/Kconfig
index 12a9d8c7d853..ded980fb16ae 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -28,5 +28,6 @@ source drivers/bus/Kconfig
 source drivers/regulator/Kconfig
 source drivers/reset/Kconfig
 source drivers/pci/Kconfig
+source drivers/firmware/Kconfig
 
 endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index 1990e86bd9af..9b284c76f904 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -27,3 +27,4 @@ obj-y += bus/
 obj-$(CONFIG_REGULATOR) += regulator/
 obj-$(CONFIG_RESET_CONTROLLER) += reset/
 obj-$(CONFIG_PCI) += pci/
+obj-$(CONFIG_FIRMWARE) += firmware/
diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
new file mode 100644
index ..28a173b63f2a
--- /dev/null
+++ b/drivers/firmware/Kconfig
@@ -0,0 +1,11 @@
+menu Firmware Drivers
+
+config FIRMWARE_ALTERA_SERIAL
+   bool Altera SPI programming
+   depends on OFDEVICE
+   select FIRMWARE
+   help
+ Programming an Altera FPGA via a few GPIOs for the control lines and
+ MOSI, MISO and clock from an SPI interface for the data lines
+
+endmenu
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
new file mode 100644
index ..ec6a5a17083d
--- /dev/null
+++ b/drivers/firmware/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_FIRMWARE_ALTERA_SERIAL) += altera_serial.o
diff --git a/drivers/firmware/altera_serial.c b/drivers/firmware/altera_serial.c
new file mode 100644
index ..b2a1e6893f98
--- /dev/null
+++ b/drivers/firmware/altera_serial.c
@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2013 Juergen Beisert ker...@pengutronix.de, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include common.h
+#include init.h
+#include driver.h
+#include firmware.h
+#include of_gpio.h
+#include xfuncs.h
+#include malloc.h
+#include gpio.h
+#include clock.h
+#include spi/spi.h
+
+#include fcntl.h
+#include fs.h
+
+/*
+ * Physical requirements:
+ * - three free GPIOs for the signals nCONFIG, CONFIGURE_DONE, nSTATUS
+ * - 32 bit per word, LSB first capable SPI master (MOSI + clock)
+ *
+ * Example how to configure this driver via device tree
+ *
+ * fpga@0 {
+ * compatible = altr,fpga-passive-serial;
+ * nstat-gpio = gpio4 18 0;
+ * confd-gpio = gpio4 19 0;
+ * nconfig-gpio = gpio4 20 0;
+ * spi-max-frequency = 1000;
+ * reg = 0;
+ * };
+ */
+
+struct fpga_spi {
+   struct firmware_handler fh;
+   int nstat_gpio; /* input GPIO to read the status line */
+   int confd_gpio; /* input GPIO to read the config done line */
+   int nconfig_gpio; /* output GPIO to start the FPGA's config */
+   struct device_d *dev;
+   struct spi_device *spi;
+   bool padding_done;
+};
+
+static int altera_spi_open(struct firmware_handler *fh)
+{
+   struct fpga_spi *this = container_of(fh, struct fpga_spi, fh);
+   struct device_d *dev = this-dev;
+   int ret;
+
+   dev_dbg(dev, Initiating programming\n);
+
+   /* initiate an FPGA programming */
+   gpio_set_value(this-nconfig_gpio, 0);
+
+   /*
+* after about 2 µs the FPGA must acknowledge with
+* STATUS and CONFIG DONE lines at low level
+*/
+   ret = wait_on_timeout(2 * 1000,
+   (gpio_get_value(this-nstat_gpio) == 0) 
+   (gpio_get_value(this-confd_gpio) == 0));
+
+   if (ret != 0) {
+   dev_err(dev, FPGA does not acknowledge the programming 
initiation\n);
+   if (gpio_get_value(this-nstat_gpio))
+   dev_err(dev, STATUS is still high!\n);
+   if (gpio_get_value(this-confd_gpio))
+   dev_err(dev, CONFIG

[PATCH v3 3/4] DT: Add binding for Altera FPGAs in passive-serial mode

2014-09-04 Thread Steffen Trumtrar

From: Sascha Hauer s.ha...@pengutronix.de

Altera FPGAs that are programmed via SPI use the passive serial protocol.
Add a simple binding that describes the setup for this usecase.

Cc: devicet...@vger.kernel.org
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
Signed-off-by: Steffen Trumtrar s.trumt...@pengutronix.de
---
 .../devicetree/bindings/firmware/altr,passive-serial.txt| 13 +
 1 file changed, 13 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/firmware/altr,passive-serial.txt

diff --git a/Documentation/devicetree/bindings/firmware/altr,passive-serial.txt 
b/Documentation/devicetree/bindings/firmware/altr,passive-serial.txt
new file mode 100644
index ..1305901a4dd5
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/altr,passive-serial.txt
@@ -0,0 +1,13 @@
+Altera FPGAs in passive serial mode
+---
+
+This binding defines the control interface to Altera FPGAs in
+passive serial mode. This is used to upload the firmware and
+to start the FPGA.
+
+Required properties:
+- compatible: shall be altr,fpga-passive-serial
+- reg: SPI chip select
+- nstat-gpio: Specify GPIO for controlling the nstat pin
+- confd-gpio: Specify GPIO for controlling the confd pin
+- nconfig-gpio: Specify GPIO for controlling the nconfig pin
+
+Example:
+
+   fpga@0 {
+   compatible = altr,fpga-passive-serial;
+   nstat-gpios = gpio4 18 0;
+   confd-gpios = gpio4 19 0;
+   nconfig-gpios = gpio4 20 0;
+   spi-max-frequency = 1000;
+   reg = 0;
+   };
-- 
2.1.0


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[RFC] ARM: dts: i.MX53: voipac: Provide NAND flash partition table

2014-09-04 Thread Rostislav Lisovy

Signed-off-by: Rostislav Lisovy lis...@gmail.com
---
When compiled and loaded with the imx-usb-loader to RAM, the command
saveenv and loadenv do work properly (i.e. loading environment
from /dev/nand0.environment.bb). When I flash the barebox to the NAND
with the barebox_update command and reboot the device, the message
environment load /dev/env0: No such file or directory is provided
during boot. saveenv and loadenv do not know anything about
/dev/nand0.environment.bb anymore and try to access the /dev/env0.
What am I doing wrong?


 arch/arm/dts/imx53-voipac-bsb.dts  |  1 +
 arch/arm/dts/imx53-voipac-dmm-668.dtsi | 33 +
 2 files changed, 34 insertions(+)
 create mode 100644 arch/arm/dts/imx53-voipac-dmm-668.dtsi

diff --git a/arch/arm/dts/imx53-voipac-bsb.dts 
b/arch/arm/dts/imx53-voipac-bsb.dts
index 54c8bcd..12ce592 100644
--- a/arch/arm/dts/imx53-voipac-bsb.dts
+++ b/arch/arm/dts/imx53-voipac-bsb.dts
@@ -10,4 +10,5 @@
  */
 
 #include arm/imx53-voipac-bsb.dts
+#include imx53-voipac-dmm-668.dtsi
 #include imx53.dtsi
diff --git a/arch/arm/dts/imx53-voipac-dmm-668.dtsi 
b/arch/arm/dts/imx53-voipac-dmm-668.dtsi
new file mode 100644
index 000..dfff1c2
--- /dev/null
+++ b/arch/arm/dts/imx53-voipac-dmm-668.dtsi
@@ -0,0 +1,33 @@
+/ {
+   chosen {
+   linux,stdout-path = uart1;
+
+   environment@0 {
+   compatible = barebox,environment;
+   device-path = nfc, partname:environment;
+   };
+   };
+};
+
+nfc {
+   partition@0 {
+   label = barebox;
+   reg = 0x0 0x8;
+   };
+
+   partition@1 {
+   label = environment;
+   reg = 0x8 0x8;
+   };
+
+   partition@2 {
+   label = kernel;
+   reg = 0x10 0x40;
+   };
+
+   partition@3 {
+   label = rootfs;
+   reg = 0x50 0x07B0;
+   };
+};
+
-- 
2.0.0.rc4


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[PATCH] ARM: dts: i.MX53: voipac: Provide NAND flash partition table

2014-09-04 Thread Rostislav Lisovy

Signed-off-by: Rostislav Lisovy lis...@gmail.com
---
This is a bit embarrassing but please ignore my previous email.
Everything works just fine, I was constantly flashing the old binary
without the partition table :-)

 arch/arm/dts/imx53-voipac-bsb.dts  |  1 +
 arch/arm/dts/imx53-voipac-dmm-668.dtsi | 33 +
 2 files changed, 34 insertions(+)
 create mode 100644 arch/arm/dts/imx53-voipac-dmm-668.dtsi

diff --git a/arch/arm/dts/imx53-voipac-bsb.dts 
b/arch/arm/dts/imx53-voipac-bsb.dts
index 54c8bcd..12ce592 100644
--- a/arch/arm/dts/imx53-voipac-bsb.dts
+++ b/arch/arm/dts/imx53-voipac-bsb.dts
@@ -10,4 +10,5 @@
  */
 
 #include arm/imx53-voipac-bsb.dts
+#include imx53-voipac-dmm-668.dtsi
 #include imx53.dtsi
diff --git a/arch/arm/dts/imx53-voipac-dmm-668.dtsi 
b/arch/arm/dts/imx53-voipac-dmm-668.dtsi
new file mode 100644
index 000..dfff1c2
--- /dev/null
+++ b/arch/arm/dts/imx53-voipac-dmm-668.dtsi
@@ -0,0 +1,33 @@
+/ {
+   chosen {
+   linux,stdout-path = uart1;
+
+   environment@0 {
+   compatible = barebox,environment;
+   device-path = nfc, partname:environment;
+   };
+   };
+};
+
+nfc {
+   partition@0 {
+   label = barebox;
+   reg = 0x0 0x8;
+   };
+
+   partition@1 {
+   label = environment;
+   reg = 0x8 0x8;
+   };
+
+   partition@2 {
+   label = kernel;
+   reg = 0x10 0x40;
+   };
+
+   partition@3 {
+   label = rootfs;
+   reg = 0x50 0x07B0;
+   };
+};
+
-- 
2.0.0.rc4


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Re: picotcp tftp support [was Adding IPv4 multicast support]

2014-09-04 Thread Antony Pavlov

On Wed, 16 Jul 2014 08:48:18 +0200
Daniele Lacamera daniele.lacam...@tass.be wrote:

 On Wed, Jul 16, 2014 at 8:30 AM, Sascha Hauer s.ha...@pengutronix.de wrote:
  Right now the network users register to a udp port and provide a handler
  which is called whenever a packet to this port is received. The
  prototype for this function is:
 
  struct net_connection *net_udp_new(IPaddr_t dest, uint16_t dport,
  rx_handler_f *handler, void *ctx);
 
  Then network users can send packets on this connection:
 
  int net_udp_send(struct net_connection *con, int len);
 
  The function returns after the packet has been sent.
 
  The network user has to keep the ball rolling by calling
 
  void net_poll(void);
 
  in a loop. This function will call into the network drivers receive
  function and dispatch the received packets. ARP packets are handled
  internally, the UDP packets are passed to the registered handlers.
 
  The handlers usually will send answers to received packets (so a tftp
  client will send an ack here or request the next packet).
 
  Usually the loop calling net_poll() also has some functionality to
  detect progress and will send the last packet again if it was lost.
 
  Hope that explains the networking model in barebox.
 
 
 Hi Sascha,
 
 Thanks a lot for this clarification. The mechanism you described is
 the same as the native execution model of PicoTCP, and looking around
 in the code it seems that looping around net_poll() was in fact the
 way to go.
 
 to Antony: I will improve TFTP first, by allowing multiple sessions at
 the same time. I will keep you posted on the progress.

I see a barebox-related publication with nice pictures on the picotcp website  
:)

  http://www.picotcp.com/barebox-on-top-of-picotcp

We are awaiting improved TFTP...

-- 
Best regards,
  Antony Pavlov

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Re: [PATCH 1/5] ARM: phyCORE-AM335x: Updated SPI NOR dts entries

2014-09-04 Thread Sascha Hauer

Hi Teresa,

On Thu, Sep 04, 2014 at 08:50:36AM +0200, Teresa Gámez wrote:
 Updated the SPI NOR flash entries. NOR flash got
 detected but did not work.
 
 - Updated muxing
 - Fixed frequency
 - Fixed CS
 - Removed first compatible entry (the flashes used is changing frequently)
 
 Signed-off-by: Teresa Gámez t.ga...@phytec.de

Applied up to 4/5. The Root partition start seems indeed wrong.

Sascha

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Re: [PATCH] ARM: dts: i.MX53: voipac: Provide NAND flash partition table

2014-09-04 Thread Sascha Hauer

On Thu, Sep 04, 2014 at 05:44:11PM +0200, Rostislav Lisovy wrote:
 Signed-off-by: Rostislav Lisovy lis...@gmail.com
 ---
 This is a bit embarrassing but please ignore my previous email.
 Everything works just fine, I was constantly flashing the old binary
 without the partition table :-)

:-)

Applied, thanks

Sascha

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Re: [PATCH] serial: imx: Fix for non-devicetree boards

2014-09-04 Thread Sascha Hauer

On Fri, Aug 15, 2014 at 11:10:03AM +0200, Philipp Zabel wrote:
 Commit 3843bfd0ab77eaf125ca617922927b61fc8ded74
 serial: imx: Determine device name from device tree
 broke this driver for non-devicetree boards, since
 of_alias_get may not be called with a NULL pointer
 as first argument.
 
 Signed-off-by: Philipp Zabel p.za...@pengutronix.de

Applied, thanks.

Damn, I missed this patch in my inbox, otherwise it would have been in
the last release.

Now it's in the stable/2014.09 branch.

Sascha

 ---
  drivers/serial/serial_imx.c | 8 +---
  1 file changed, 5 insertions(+), 3 deletions(-)
 
 diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c
 index 474bfaf..e379f29 100644
 --- a/drivers/serial/serial_imx.c
 +++ b/drivers/serial/serial_imx.c
 @@ -338,9 +338,11 @@ static int imx_serial_probe(struct device_d *dev)
   cdev-flush = imx_serial_flush;
   cdev-setbrg = imx_serial_setbaudrate;
   cdev-linux_console_name = ttymxc;
 - devname = of_alias_get(dev-device_node);
 - if (devname)
 - cdev-devname = xstrdup(devname);
 + if (dev-device_node) {
 + devname = of_alias_get(dev-device_node);
 + if (devname)
 + cdev-devname = xstrdup(devname);
 + }
  
   imx_serial_init_port(cdev);
  
 -- 
 2.0.1
 
 

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[PATCH 4/5] ARM: phyCORE-AM335x: Add support for 2x512MB RAM

[PATCH 2/5] ARM: phyCORE-AM335x: Update RAM Timings

[PATCH 5/5] ARM: phyCORE-AM335x: Update partition table

[PATCH 3/5] ARM: phyCORE-AM335x: Fixup RAM setting naming

[PATCH 1/5] ARM: phyCORE-AM335x: Updated SPI NOR dts entries

Re: [PATCH 5/5] ARM: phyCORE-AM335x: Update partition table

Re: [PATCH 5/5] ARM: phyCORE-AM335x: Update partition table

Re: [PATCH] Documentation: .gitignore: ignore 'commands/' generated directory

Re: [PATCH v3 2/3] pinctrl: at91: add pinctrl driver

[PATCH] Fix barebox metadata

Re: [PATCH v3 2/3] pinctrl: at91: add pinctrl driver

Re: [PATCH] Fix barebox metadata

v2014.09.0

[PATCH v3 0/4] firmware programming interface

[PATCH v3 1/4] Add a Firmware programming framework

[PATCH v3 4/4] Firmware: socfpga: Add SoCFPGA FPGA program support

[PATCH v3 2/4] Firmware: provide a handler to program Altera FPGAs

[PATCH v3 3/4] DT: Add binding for Altera FPGAs in passive-serial mode

[RFC] ARM: dts: i.MX53: voipac: Provide NAND flash partition table

[PATCH] ARM: dts: i.MX53: voipac: Provide NAND flash partition table

Re: picotcp tftp support [was Adding IPv4 multicast support]

Re: [PATCH 1/5] ARM: phyCORE-AM335x: Updated SPI NOR dts entries

Re: [PATCH] ARM: dts: i.MX53: voipac: Provide NAND flash partition table

Re: [PATCH] serial: imx: Fix for non-devicetree boards

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