[casper] Question About The ADC Clock Frequency
Hi, All, In our model, We need ADC clock frequency up to 250Mhz. Our ADC boards are ADC16*250-8.We are using adc16*250-8 yellow block in our model modified based PAPER model .However when I changed the XSG core config/User IP Clock Rate(MHz) to 250 Mhz and System Generator/FPGA Clock Period(ns) to 4ns, it could not create bof file,something like the following: ERROR:LIT:667 - Block 'MMCM_ADV symbol "physical_group_roach2_tl8511_250port_adc1_adc16x250_8/roach2_tl8511_250port_ adc1_adc16x250_8/bufg_i<3>/roach2_tl8511_250port_adc1_adc16x250_8/roach2_tl85 11_250port_adc1_adc16x250_8/adc_mmcm_0/mmcm_adv_inst" (output signal=roach2_tl8511_250port_adc1_adc16x250_8/roach2_tl8511_250port_adc1_adc1 6x250_8/bufg_i<3>)' has its target frequency, FVCO, out of range. Valid FVCO range for speed grade "-1" is 600MHz - 1200MHz. The computed FCVO is a function of the input frequency CLKIN1_PERIOD, the division factor DIVCLK_DIVIDE, and the CLKFBOUT_MULT_F attribute (FVCO = 1000*CLKFBOUT_MULT_F/(CLKIN1_PERIOD*DIVCLK_DIVIDE)). The CLKIN_PERIOD attribute may have been set by ngdbuild based on the user specified PERIOD constraint. The current calculated FVCO is 1250.00 MHz. Reference the V6 architecture Users Guide or search the Xilinx Answer Records database for the error code. Now, The system work in 250Mhz clock rate while the model bof file is crearted in 200Mhz. It looks no problem in sending the correct data packets, but I am not sure whether it run normally.In theory , the input data rate is 250Mhz*8bits*32=64Gbits/s,after fft, EQ ,the data rate becomes 32Gbits/s,we have 4 10Gbe ports to send out data.Each ports will have32/4=8Gbits/s,(if we use 200MHz,this data rate is about 6.4Gbits/s )I don't know whether it is ok for the transition capability of the 10Gbe NICs(10Gbits/s). Could anyone help me please? Thanks! peter
[casper] High speed samplers (>10GS/s)
Hello everyone Does anybody know if there are any high speed (>10GS/s) samplers in development, aside from the 4-bit sampler listed on the wiki? This would ideally be >15GSps as we're looking to directly sample C-band. Is the ZDOK able to handle such speeds? Cheers Michael
Re: [casper] High speed samplers (>10GS/s)
How much BW from C-band do you actually want to use? Can you consider sampling in the second or third nyquist zone using a slower sampler? Jason Manley CBF Manager SKA-SA Cell: +27 82 662 7726 Work: +27 21 506 7300 On 12 Jan 2015, at 13:22, Michael D'Cruze wrote: > Hello everyone > > Does anybody know if there are any high speed (>10GS/s) samplers in > development, aside from the 4-bit sampler listed on the wiki? This would > ideally be >15GSps as we're looking to directly sample C-band. Is the ZDOK > able to handle such speeds? > > Cheers > Michael
Re: [casper] High speed samplers (>10GS/s)
That's pretty wide, yeah. The good news is that it's less than a 1:2 feed ratio, so you could definitely use this technique effectively. I think the 10b sampler that you mentioned would work for you, but last I checked, it wasn't available as a production, off-the-shelf part. Maybe Dan can offer a status update. The closest well-trodden path would be to use one of the ASIAA 5GSa/s parts. That'd give you over 2GHz usable BW. I also saw some test results from a prototype 20GSa/s part that looked promising... but I don't know if there was any plan to put it into production. Again, Dan might be able to offer more info. Jason Manley CBF Manager SKA-SA Cell: +27 82 662 7726 Work: +27 21 506 7300 On 12 Jan 2015, at 13:33, Michael D'Cruze wrote: > This is what we're considering at the moment, as it's our only option. The > Lovell's C-band receiver can see 4-7.5 GHz; ideally we'd see all of that > instantaneously. > > BW > Michael > > > From: Jason Manley > Sent: Monday, January 12, 2015 11:28 AM > To: Michael D'Cruze > Cc: Casper Lists > Subject: Re: [casper] High speed samplers (>10GS/s) > > How much BW from C-band do you actually want to use? Can you consider > sampling in the second or third nyquist zone using a slower sampler? > > Jason Manley > CBF Manager > SKA-SA > > Cell: +27 82 662 7726 > Work: +27 21 506 7300 > > On 12 Jan 2015, at 13:22, Michael D'Cruze > wrote: > >> Hello everyone >> >> Does anybody know if there are any high speed (>10GS/s) samplers in >> development, aside from the 4-bit sampler listed on the wiki? This would >> ideally be >15GSps as we're looking to directly sample C-band. Is the ZDOK >> able to handle such speeds? >> >> Cheers >> Michael >
Re: [casper] High speed samplers (>10GS/s)
This is what we're considering at the moment, as it's our only option. The Lovell's C-band receiver can see 4-7.5 GHz; ideally we'd see all of that instantaneously. BW Michael From: Jason Manley Sent: Monday, January 12, 2015 11:28 AM To: Michael D'Cruze Cc: Casper Lists Subject: Re: [casper] High speed samplers (>10GS/s) How much BW from C-band do you actually want to use? Can you consider sampling in the second or third nyquist zone using a slower sampler? Jason Manley CBF Manager SKA-SA Cell: +27 82 662 7726 Work: +27 21 506 7300 On 12 Jan 2015, at 13:22, Michael D'Cruze wrote: > Hello everyone > > Does anybody know if there are any high speed (>10GS/s) samplers in > development, aside from the 4-bit sampler listed on the wiki? This would > ideally be >15GSps as we're looking to directly sample C-band. Is the ZDOK > able to handle such speeds? > > Cheers > Michael
[casper] ADC 5g testing
Dear All, I am trying to test the ADC output for a simple sinusoid input signal (75 MHz, -6dBm) with the snapshot block. Many of the output values are not consistent with the expected results. Do I need to do any post-processing on data after reading from Bram ? Regards, Amit
Re: [casper] ADC 5g testing
Hi Amit, Could you please provide an example plot of what you mean by "not consistent with expect results"? Questions: 1. What is your clock rate? 2. Have you calibrated the MMCM? 3. The ADC output is offset binary, are you correctly interpreting it as such? 4. If you are using the adc5g python package the BRAM output needs to be converted to signed binary before capture (by subtracting 128). Have you done so? 5. Have you done any core-to-core mismatch corrections? 6. Less importantly, is your clock generator reference locked to your test tone synthesizer? Thanks, Rurik On Mon, Jan 12, 2015 at 9:58 AM, Amit Bansod wrote: > Dear All, > > I am trying to test the ADC output for a simple sinusoid input signal (75 > MHz, -6dBm) with the snapshot block. > > Many of the output values are not consistent with the expected results. Do > I need to do any post-processing on data after reading from Bram ? > > Regards, > Amit > >
Re: [casper] ADC1X26G
Hi Michael, I think is worthwhile to augment Rick’s response by noting that the premise of this project was a direct interface to SERDES transceivers, which required GTH generation transceiver—not available in Virtex 6 family (ROACH2). Hence the choice of VC709 platform with Virtex 7 as the back end, much more detail in the report. One could think of ways to do a ROACH2 interface with extreme demux factor, but honestly, given the data rates intrinsic to this conversion rate, we don’t think the V6 is well matched generally—also the high demux would make for a much more complicated ADC board. cc to CASPER list to follow up on your other thread. Jonathan > On Jan 13, 2015, at 12:35 AM, Rick Raffanti > wrote: > > Hello Michael, > No plans at this point to build a ROACH version. I am making a couple more > for the VC709, but that's it for the development at this point. > Rick > > On Mon, Jan 12, 2015 at 2:21 PM, Michael D'Cruze > wrote: > Dear Rick and Jonathan > > > > I’ve seen the test report for the 26GS/s sampler that you posted on the > Casper wiki. I wondered if you could estimate a timescale for the ADC going > to production? It looks like it’s still in the early stages of development. > Is this intended for ROACH2, do you know? > > > > Many thanks > > Michael > >
Re: [casper] Question About The ADC Clock Frequency
Hi, Peter, On Jan 12, 2015, at 1:11 AM, Peter Niu wrote: > In our model, We need ADC clock frequency up to 250Mhz. Our ADC boards are > ADC16*250-8.We are using adc16*250-8 yellow block in our model modified based > PAPER model .However when I changed the XSG core config/User IP Clock > Rate(MHz) to 250 Mhz and System Generator/FPGA Clock Period(ns) to 4ns, it > could not create bof file,something like the following: > > ERROR:LIT:667 - Block 'MMCM_ADV symbol [...] has its target frequency, FVCO, > out of range. I'm surprised that you did not get a DRC (design rule check) error earlier in the build process. The ADC chips on the ADC16 board can sample as high as 250 Msps when the ADC16 is running in 16 input mode, but MMCM limitations prevent using some sample rate ranges. In short, the ADC16 board is limited to a maximum of 240 Msps in 16 input mode. For details, see this new section of the CASPER wiki: https://casper.berkeley.edu/wiki/ADC16x250-8#ADC16_Sample_Rate_vs_Virtex-6_MMCM_Limitations > Now, The system work in 250Mhz clock rate while the model bof file is > crearted in 200Mhz. It looks no problem in sending the correct data packets, > but I am not sure whether it run normally.In theory , the input data rate is > 250Mhz*8bits*32=64Gbits/s,after fft, EQ ,the data rate becomes 32Gbits/s,we > have 4 10Gbe ports to send out data.Each ports will have32/4=8Gbits/s,(if we > use 200MHz,this data rate is about 6.4Gbits/s )I don't know whether it is ok > for the transition capability of the 10Gbe NICs(10Gbits/s). > Could anyone help me please? It may seem like it works at 250 MHz, but you are asking for problems if you clock the FPGA faster than the design was built for. You could rebuild the design for 240 Msps and it should work OK (assuming the build can meet timing at 240 MHz). Hope this helps, Dave
