Re: [casper] bitstream: command not found

[Mark Wagner]

Hi Katherine,

I think you're asking bash to execute the script and not python.  Try
calling it with python or put a python shebang in there (making sure
the path is correct).

Mark

On Sat, Apr 20, 2013 at 10:40 AM, katherine viviana cortes urbina
 wrote:
> Hi all,
>
> I have a new error when I ran the .bof to using ./tut3_2048.py 192.168.100.2
> -b tut3_1ghz_2013_Apr_09_1815.bof this is:
>
> \nAuthor: Jason Manley, November 2009.
> : File name too long
>
> ./tut3_2048.py: line 15: bitstream: command not found
> ./tut3_2048.py: line 18: syntax error near unexpected token `('
> ./tut3_2048.py: line 18: `def exit_fail():'
>
> In the tut3_2048.py I have definite the:
>
> bitstream = 'tut3_1ghz_2013_Apr_09_1815.bof'  and fpga.progdev(bitstream) in
> the script.
>
> any idea?
>
> Cheers
>
> katty
>

Re: [casper] Netbooting ROACH and ROACH2 from same server

[Mark Wagner]

Hi Dale,

I set this up in the dnsmasq configuration given the ROACH1 and 2 have
differing MAC address families.  For example, in my dnsmasq.conf file I
have the lines:

dhcp-mac=roach2,02:*:01:*:*:*
dhcp-mac=roach1,*:6D:*:*:*:*

dhcp-option=tag:roach2,17,192.168.40.1:/home/nfs/roach2/current
dhcp-option=tag:roach1,17,192.168.40.1:/home/nfs/roach1/current

I'm attaching my dnsmasq.conf file if it's any help.  In /etc/exports I
have:

/home/nfs/roach1
192.168.40.0/24(rw,subtree_check,no_root_squash,insecure)
/home/nfs/roach2
192.168.40.0/24(rw,subtree_check,no_root_squash,insecure)

It was awhile ago, but I don't think I needed to do anything else.

Mark


On Wed, Jun 19, 2013 at 5:21 PM, Tom Kuiper  wrote:

> **
> On 06/19/2013 05:16 PM, Gary, Dale E. wrote:
>
>  I would like to get a ROACH1 to netboot on the same network as our
> ROACH2s, but I am not sure how to specify two different directories from
> which to serve uImages to different machines.  Is it possible?  I am using
> the Ubuntu tftp server, whose config file (/etc/xinetd.d/tftp) specifies
> the boot directory as
> server_args = -s /srv/roach2_boot/boot
>  but I would need to specify /srv/roach_boot/boot for the ROACH1.
>
> On my ROACH controller I have /var/roach1_root and /var/roach2_root.  Each
> ROACH has the host and path to its NFS directory in EPROM.  The parameters
> were set after logging in via the ROACH serial port.  Melissa Soriano set
> it up but I'm sure I can dig up her notes if you need more information.
>
> Tom
>


dnsmasq.conf
Description: Binary data

Re: [casper] July 21 Deadline for Casper Workshop Registration

[Mark Wagner]

Hi All,

I've changed the link on casper.berkeley.edu to the one Jonathan
provided for now.

Mark

On Sun, Jul 21, 2013 at 4:28 AM, Jonathan Weintroub
 wrote:
> Dear all,
>
> For much of this weekend it appears the workshop web page hosted by U. 
> Manchester, linked from the casper.berkeley.edu, has not been responding.  
> This seems still to be the case this morning.
>
> Per our host, Ben Stappers, to register you can go directly to the 
> registration business page.
>
> http://estore.manchester.ac.uk/browse/product.asp?catid=282&modid=2&compid=1
>
> This page is up and running, which I demonstrated by registering at the last 
> possible minute myself.
>
> Please plan to submit your registration and pay the fee on time, which means 
> today.
>
> Regards,
>
> Jonathan Weintroub
>
>
> On Jul 19, 2013, at 11:30 AM, Dan Werthimer  wrote:
>
>>
>>
>> Dear Casperites,
>>
>>
>> We hope you can join us for the CASPER workshop in Manchester.
>>
>> PLEASE REGISTER SOON:
>>
>> The deadline for registration is in TWO DAYS (July 21).
>> Details Below from Ben Stappers:
>>
>>
>>
>>
>> Dear Colleagues,
>>
>> The CASPER collaboration workshop of 2013 to be held at Jodrell Bank
>> Observatory which will take place from September 2nd-6th 2013 is just
>> two months away and we are making excellent progress on putting
>> together an exciting and interesting week.
>>
>> Please find below a couple of important announcements:
>>
>> We have decided to extend the registration deadline, please register
>> before the 21st July 2013, after that date it will no longer be possible
>> to register for the meeting. Registration is possible by following the
>> links at http://www.jb.man.ac.uk/meetings/casper2013/
>>
>> Abstract Submission
>>
>> We are now happy to accept submission of titles and abstracts for
>> talks and posters. All submissions for talks will be considered,
>> however due to the relatively limited time available for talks it may
>> be that you will be offered a poster spot instead. Please submit your
>> abstracts for talks and posters before July 31st. Follow the links
>> that can be found at http://www.jb.man.ac.uk/meetings/casper2013/
>>
>> Abstract Submission
>>
>> Programme
>>
>> The full programme will be finalised once all the talks have been
>> decided. However we already have an exciting list of invited speakers
>> and will be adding more in the next couple of weeks.
>>
>> Phil Diamond ---The Square Kilometre Array
>> Wallace Turner   ---Signal Processing Challenges of the SKA
>> Roshene McCool   ---Data Transport Challenges of the SKA
>> NVIDIA Representative---The view from NVIDIA
>> XILINX Representative---The view from XILINX
>> Justin Kasper---Solar Physics and Low Frequency Radio Astronomy
>> Dan Thornton ---Searching for Extragalactic Fast Radio Bursts
>>
>> We also extrmely priviliged to have Jocelyn Bell-Burnell giving us an
>> evening lecture on Wednesday 4th September on the discovery of pulsars
>> and the associated technology.
>>
>> Please don't forget to book your accommodation as soon as possible to
>> get the best possible deal.
>>
>> Important dates:
>>
>> Registration Open:April 26th 2013
>> Deadline for Travel Assistance Requests:  June 26th 2013
>> Announcement of Travel Assistance Requests: July 10th 2013
>> Registration Closes:  July 21st 2013
>> Abstract Submission Closes:   July 31st 2013
>> Meeting dates:September 2nd - 6th 2013
>>
>>
>> We look forward to welcoming you to Jodrell Bank Observatory.
>>
>> - Ben Stappers for the LOC and SOC
>>
>>
>>
>>
>
>

Re: [casper] July 21 Deadline for Casper Workshop Registration

[Mark Wagner]

Hi Jonathan,

Thanks for the heads up -- I updated the link. See you in Manchester!

Mark


On Wed, Jul 31, 2013 at 8:42 AM, Jonathan Weintroub <
jweintr...@cfa.harvard.edu> wrote:

> Hi Mark,
>
> I think at this point it is best to revert the CASPER home page link for
> the workshop to what it was before.
>
> http://www.jb.man.ac.uk/meetings/casper2013/
>
> The registration page currently linked has been taken down.  Today is the
> deadline for abstract submission, I'll send a note to the mailing list.
>
> Cheers,
>
> Jonathan
>
>
>
> On Jul 21, 2013, at 1:16 PM, Mark Wagner  wrote:
>
> > Hi All,
> >
> > I've changed the link on casper.berkeley.edu to the one Jonathan
> > provided for now.
> >
> > Mark
> >
> > On Sun, Jul 21, 2013 at 4:28 AM, Jonathan Weintroub
> >  wrote:
> >> Dear all,
> >>
> >> For much of this weekend it appears the workshop web page hosted by U.
> Manchester, linked from the casper.berkeley.edu, has not been responding.
>  This seems still to be the case this morning.
> >>
> >> Per our host, Ben Stappers, to register you can go directly to the
> registration business page.
> >>
> >>
> http://estore.manchester.ac.uk/browse/product.asp?catid=282&modid=2&compid=1
> >>
> >> This page is up and running, which I demonstrated by registering at the
> last possible minute myself.
> >>
> >> Please plan to submit your registration and pay the fee on time, which
> means today.
> >>
> >> Regards,
> >>
> >> Jonathan Weintroub
> >>
> >>
> >> On Jul 19, 2013, at 11:30 AM, Dan Werthimer 
> wrote:
> >>
> >>>
> >>>
> >>> Dear Casperites,
> >>>
> >>>
> >>> We hope you can join us for the CASPER workshop in Manchester.
> >>>
> >>> PLEASE REGISTER SOON:
> >>>
> >>> The deadline for registration is in TWO DAYS (July 21).
> >>> Details Below from Ben Stappers:
> >>>
> >>>
> >>>
> >>>
> >>> Dear Colleagues,
> >>>
> >>> The CASPER collaboration workshop of 2013 to be held at Jodrell Bank
> >>> Observatory which will take place from September 2nd-6th 2013 is just
> >>> two months away and we are making excellent progress on putting
> >>> together an exciting and interesting week.
> >>>
> >>> Please find below a couple of important announcements:
> >>>
> >>> We have decided to extend the registration deadline, please register
> >>> before the 21st July 2013, after that date it will no longer be
> possible
> >>> to register for the meeting. Registration is possible by following the
> >>> links at http://www.jb.man.ac.uk/meetings/casper2013/
> >>>
> >>> Abstract Submission
> >>>
> >>> We are now happy to accept submission of titles and abstracts for
> >>> talks and posters. All submissions for talks will be considered,
> >>> however due to the relatively limited time available for talks it may
> >>> be that you will be offered a poster spot instead. Please submit your
> >>> abstracts for talks and posters before July 31st. Follow the links
> >>> that can be found at http://www.jb.man.ac.uk/meetings/casper2013/
> >>>
> >>> Abstract Submission
> >>>
> >>> Programme
> >>>
> >>> The full programme will be finalised once all the talks have been
> >>> decided. However we already have an exciting list of invited speakers
> >>> and will be adding more in the next couple of weeks.
> >>>
> >>> Phil Diamond ---The Square Kilometre Array
> >>> Wallace Turner   ---Signal Processing Challenges of the SKA
> >>> Roshene McCool   ---Data Transport Challenges of the SKA
> >>> NVIDIA Representative---The view from NVIDIA
> >>> XILINX Representative---The view from XILINX
> >>> Justin Kasper---Solar Physics and Low Frequency Radio Astronomy
> >>> Dan Thornton ---Searching for Extragalactic Fast Radio Bursts
> >>>
> >>> We also extrmely priviliged to have Jocelyn Bell-Burnell giving us an
> >>> evening lecture on Wednesday 4th September on the discovery of pulsars
> >>> and the associated technology.
> >>>
> >>> Please don't forget to book your accommodation as soon as possible to
> >>> get the best possible deal.
> >>>
> >>> Important dates:
> >>>
> >>> Registration Open:April 26th 2013
> >>> Deadline for Travel Assistance Requests:  June 26th 2013
> >>> Announcement of Travel Assistance Requests: July 10th 2013
> >>> Registration Closes:  July 21st 2013
> >>> Abstract Submission Closes:   July 31st 2013
> >>> Meeting dates:September 2nd - 6th 2013
> >>>
> >>>
> >>> We look forward to welcoming you to Jodrell Bank Observatory.
> >>>
> >>> - Ben Stappers for the LOC and SOC
> >>>
> >>>
> >>>
> >>>
> >>
> >>
>
>

Re: [casper] casper libraries

[Mark Wagner]

Hi Tim,

That page needs to be updated or removed.

The repository that is used with our tutorials can be found here:

https://github.com/casper-astro/mlib_devel

We generally update this once a year, coinciding with the CASPER workshop.

There are other more active forks (e.g.*
https://github.com/sma-wideband/mlib_devel  **
https://github.com/ska-sa/mlib_devel*) which have more bugfixes, features,
and hardware support, but may not be as stable.

Mark


On Fri, Aug 16, 2013 at 2:03 PM, Timothy Madden  wrote:

> Folks
>
> It seems that the libraries listed on
> https://casper.berkeley.edu/wiki/Repositories
>
> are all at least 2 years old.
>
> Is there REALLY no development on Casper libraries for 2 years?
>
> Where does one get something more recent?
>
> Tim Madden
>
>

Re: [casper] Setting up CASPER tools on a Windows machine

[Mark Wagner]

Hi Joseph,

I don't think Matlab 2013 is supported by Xilinx 14.5 or 14.6 yet:

http://www.xilinx.com/support/answers/56250.html

Mark


On Mon, Aug 19, 2013 at 1:17 PM, Wesley New  wrote:

> Hi Joe,
>
> That error should actually be a warning. It doesnt stop you from compiling
> designs. There is something else not right with your setup.
>
> Have a look at the startsg script in the root of the mlib_devel directory
> and check that you are setting all those environment variables correctly.
>
> Regards
>
> Wes
> On 19 Aug 2013 21:50, "Kujawski, Joseph"  wrote:
>
>> Does anyone have a setup guide for getting the CASPER tools running in a
>> Windows environment?
>>
>> My configuration is as follows:
>>
>> 1) Windows 7, 64bit
>> 2) Matlab 2013a
>> 3) Xilinx ISE version 14.6
>>
>> I followed the instructions at
>> https://casper.berkeley.edu/wiki/MSSGE_Setup_with_Xilinx_14.5_and_Matlab_2012b
>>  as
>> best I could for the Windows platform, but have not gotten to the point
>> that I can see the CASPER blocks in my Simulink library.
>>
>> Running casper_xps in Matlab produces the error 'Unsupported Xilinx
>> System Generator version 14.5.4652'
>>
>>
>> --
>> **
>> * Joe Kujawski
>> * Siena College
>> * Dept. of Physics and Astronomy, RB 113
>> * 515 Loudon Road
>> * Loudonville, NY 12211-1462
>> *
>> * Email: jkujaw...@siena.edu
>> * Phone: 518-782-6885
>> * Fax: 518-783-2986
>> **
>>
>>

Re: [casper] Compile error - Design Error "standard exception" and Block Error

[Mark Wagner]

Hi All,

I had a separate email with Michael about this -- it's an issue that comes
up when not using a supported OS (namely Debian/Ubuntu based systems).  I
think he may have found a workaround though.

Mark

On Thu, Sep 25, 2014 at 9:29 AM, David MacMahon 
wrote:

> Hi, Michael,
>
> On Sep 20, 2014, at 6:47 AM, Michael D'Cruze wrote:
>
> > com.xilinx.sysgen.netlist.NetlistInternal: couldn't open first pass text
> > file at /projects/t1/sysgen/sysgen/masterScript4416603519849447044.pl
> > line 544
>
> That's weird.  What's on/around line 544 of
> /projects/t1/sysgen/sysgen/masterScript4416603519849447044.pl?
>
> Dave
>
>
>

Re: [casper] about tutorial3 on roach board2

[Mark Wagner]

It seems github has some policies about binary files that may not show them
as you'd expect. But for tutorial 3, you should be able to go here:

https://github.com/casper-astro/tutorials_devel/commit/ab557d6192cec4aff49634f3a20a979e81ead69f

click on the view button for the file you want (e.g. tut3.mdl.gz) and then
click on 'view the full file'.  I think that should download it for you.

We might want to think about putting the binaries in official releases for
the tutorials:

https://help.github.com/articles/distributing-large-binaries/

Best,
Mark

On Wed, Oct 15, 2014 at 1:43 PM, Wang Jinqing  wrote:

>
> Hi,
>
> I want to run the tutorial3 wideband spectrometer on my roach2. So I want
> to download the model file from the web
> https://casper.berkeley.edu/wiki/Wideband_Spectrometer  on the setup line
> it writes like:"This tutorial comes with a com plete model".
>
> But It seems nothing connection if I click in this item. So I want to
> build the model by myself but the document about this tutorial3 is  detail
> enough  on the https://casper.berkeley.edu/wiki/Wideband_Spectrometer &nbs
> p; for a new man like me.
>
> So how I can download this model or build the tutorial3 model on roach2.
>
> Best Regards.
>
> Oliver Wang
>
>
>
>

Re: [casper] Compiler merging SRLs -- Timing performance

[Mark Wagner]

Hi Jack,

Not sure if this will help, but in Planahead I would try to click and drag
that LUT as close as possible to each of the outputs.  And if that doesn't
help or makes it worse, you could also try to duplicate the logic going to
each of those outputs, forcing separate LUTs to be used.

Cheers,
Mark


On Thu, Dec 4, 2014 at 10:48 AM, Jack Hickish  wrote:

> Hi all,
>
> This is something I've been fighting with for a while now, and I wonder if
> anyone on this maillist has any insight (because I'm pretty sure I may just
> be doing something wrong with the tools).
>
> The problem:
> I'm playing with a ROACH2 design that (sometimes) compiles at 312 MHz.
> However, every now and then I'll make a small change to the design and the
> compile will fail timing catastrophically, with paths failing sometimes
> with -2 ns (or worse) slack.
> When I look at the failing path(s), the delays are usually ~80% routing.
> I'll see a signal take a huge detour to use a shift register in some
> arbitrary location on the chip. Upon closer inspection of the relevant SRL,
> it appears that the LUT concerned is being used for two signal paths, one
> on the O5 output, one on the O6. The result seems to be that it is poorly
> placed for both it's roles.
>
> I'm only using ~50% of the slices and about 30% of the registers / luts on
> the FPGA, and there are plenty of sensibly located SLICEMs the placer could
> use if it so desired. I've switched lut combining off (with the -lt flag),
> in planahead which doesn't seem to have made any difference.
>
> Can anyone offer me any words of advice / wisdom which might reduce my
> confusion at what's going on (or, even better, help me solve the problem)?
>
> Despairingly yours,
> Jack
>
>
>

Re: [casper] System Compatibility

[Mark Wagner]

Hi Victor,

A list of supported operating systems is here on page 7:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/irn.pdf

If you need free, a much safer alternative to Ubuntu (but still
unsupported) is CentOS 6.5, which is built from RHEL6 source packages.

Mark



On Tue, Jun 23, 2015 at 12:48 PM, Victor Cardoso <
victorcardoso...@hotmail.com> wrote:

> Greetings,
>
> I am working with the ROACH 2 in order to implement the MUSIC project. I
> am having a lot of troubles to compile the Tutorial 1 (Introduction to
> Simulink) due to mismatch between Xilinx ISE 14.5 and my Operating System,
> Ubuntu 10.04.
> I would like to know if it's possible to run this example using Ubuntu.
> Otherwise, I can install Redhat Enterprise Linux 6.3, Matlab 12b and Xilinx
> 14.5 to run the codes.
>
> I look forward hearing from you.
>
> Best Regards,
> Victor Cardoso.
>

Re: [casper] System Compatibility

[Mark Wagner]

Hi Victor,

It looks like you don't have your matlab path setup correctly.  Have you
checked out this page:
https://casper.berkeley.edu/wiki/MSSGE_Setup_with_Xilinx_14.x_and_Matlab_2012b

Mark


On Tue, Jun 30, 2015 at 11:28 AM, Victor Cardoso <
victorcardoso...@hotmail.com> wrote:

> Thank you all for your support.
>
> After hearing from you, I decided to change my OS to Red Hat Workstation
> 6. Unfortunately, the bugs persisted.
> When I try to launch the System Generator on Simulink I receive this
> message:
> --> Error Evaluating 'OpenFcn' callback of Xilinx System Generator Block
> block (mask) 'untitled/ System Generator'. --Undefined variable "com" or
> class "com.xilinx.sysgen.util.StrategyUtil.loadAllStrategyNames".
>
> Additionally, when I type sysgen at the terminal, I get this message:
> [   INFO   ] XILINX_DSP environment variable does NOT coincide with
> $XILINX. Resetting...
> /opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util/sysgen: line 1176: matlab: command
> not found
>
> How should I proceed at this point?
>
> I appreciate your attention,
> Victor Cardoso.
>
> PS: I'm running matlab 2012b, Xilinx ISE 14.7 and Red Hat Workstation 6.6.
> --
> From: jsm...@ska.ac.za
> Date: Wed, 24 Jun 2015 07:11:47 +0200
> Subject: Re: [casper] System Compatibility
> To: mwag...@ssl.berkeley.edu
> CC: victorcardoso...@hotmail.com; casper@lists.berkeley.edu
>
>
> Hi Victor,
>
> We used to use Ubuntu 14.04, and it kind of worked, but it wasn't stable.
> Switched to the most recent version of CentOS about a month ago and haven't
> had problems since.
>
> Xilinx v14.7, Matlab 2012b.
>
> Regards,
> James
>
>
> On Wed, Jun 24, 2015 at 1:10 AM, Mark Wagner 
> wrote:
>
> Hi Victor,
>
> A list of supported operating systems is here on page 7:
>
> http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/irn.pdf
>
> If you need free, a much safer alternative to Ubuntu (but still
> unsupported) is CentOS 6.5, which is built from RHEL6 source packages.
>
> Mark
>
>
>
> On Tue, Jun 23, 2015 at 12:48 PM, Victor Cardoso <
> victorcardoso...@hotmail.com> wrote:
>
> Greetings,
>
> I am working with the ROACH 2 in order to implement the MUSIC project. I
> am having a lot of troubles to compile the Tutorial 1 (Introduction to
> Simulink) due to mismatch between Xilinx ISE 14.5 and my Operating System,
> Ubuntu 10.04.
> I would like to know if it's possible to run this example using Ubuntu.
> Otherwise, I can install Redhat Enterprise Linux 6.3, Matlab 12b and Xilinx
> 14.5 to run the codes.
>
> I look forward hearing from you.
>
> Best Regards,
> Victor Cardoso.
>
>
>
>

Re: [casper] ADC calibration issue

[Mark Wagner]

git rev-parse HEAD

On Thu, Mar 30, 2017 at 10:46 AM, Jack Hickish 
wrote:

> Someone better with git can tell you the "right" way, but I would just run
> "git log" in the repository directory, and note the most recent commit hash.
>
> Cheers
> Jack
>
> On Thu, 30 Mar 2017 at 10:31 vijay kumar 
> wrote:
>
>> I am using 200 MHz ADC clock frequency (demux-1). And I am not sure how
>> to check the adc repo and mlib_devel repo versions ? Could you please help
>> me in that ?
>> Thank you.
>>
>> On Wed, Mar 29, 2017 at 6:39 PM, Jack Hickish 
>> wrote:
>>
>> I like the triumphant "done!" at the end :)
>>
>> Next questions --
>> What version of the adc repo and mlib_devel repos are you using?
>> Do you have other hardware you can test on? (It's very unlikely to be a
>> hardware problem, IMO, but worth checking if you can).
>> What ADC clock rate are you using?
>>
>> Cheers
>> Jack
>>
>> On Wed, 29 Mar 2017 at 14:39 vijay kumar 
>> wrote:
>>
>> Yes ! I assume the clock has been clocked. For convenience, I have
>> included the output script i get after I run the initialization script.
>>
>>
>> Programming 192.168.10.2 with direct_mar_29_2017_Mar_29_1500.bof.gz...
>> Design built for ROACH2 rev2 with 4 ADCs (ZDOK rev2)
>> Gateware supports demux modes (using demux by 1)
>> Resetting ADC, power cycling ADC, and reprogramming FPGA...
>> ZDOK0 clock OK
>> Calibrating SERDES blocks...calibrating chips ["A", "B", "C", "D"]
>> chip A chan 1 lane 0 no good taps found
>> chip A chan 1 lane 1 no good taps found
>> chip A chan 2 lane 0 no good taps found
>> chip A chan 2 lane 1 no good taps found
>> chip A chan 3 lane 0 no good taps found
>> chip A chan 3 lane 1 no good taps found
>> chip A chan 4 lane 0 no good taps found
>> chip A chan 4 lane 1 no good taps found
>> chip B chan 1 lane 0 no good taps found
>> chip B chan 1 lane 1 no good taps found
>> chip B chan 2 lane 0 no good taps found
>> chip B chan 2 lane 1 no good taps found
>> chip B chan 3 lane 0 no good taps found
>> chip B chan 3 lane 1 no good taps found
>> chip B chan 4 lane 0 no good taps found
>> chip B chan 4 lane 1 no good taps found
>> chip C chan 1 lane 0 no good taps found
>> chip C chan 1 lane 1 no good taps found
>> chip C chan 2 lane 0 no good taps found
>> chip C chan 2 lane 1 no good taps found
>> chip C chan 3 lane 0 no good taps found
>> chip C chan 3 lane 1 no good taps found
>> chip C chan 4 lane 0 no good taps found
>> chip C chan 4 lane 1 no good taps found
>> chip D chan 1 lane 0 no good taps found
>> chip D chan 1 lane 1 no good taps found
>> chip D chan 2 lane 0 no good taps found
>> chip D chan 2 lane 1 no good taps found
>> chip D chan 3 lane 0 no good taps found
>> chip D chan 3 lane 1 no good taps found
>> chip D chan 4 lane 0 no good taps found
>> chip D chan 4 lane 1 no good taps found
>>
>> ERROR: SERDES calibration failed for ADC A.
>> ERROR: SERDES calibration failed for ADC B.
>> ERROR: SERDES calibration failed for ADC C.
>> ERROR: SERDES calibration failed for ADC D.
>> Selecting analog inputs...
>> Using default digital gain of 1...
>> Done!
>>
>>
>> On Wed, Mar 29, 2017 at 5:33 PM, Jack Hickish 
>> wrote:
>>
>> Further, is the board clocking OK? -- I believe the initialization script
>> should give feedback on whether of not the FPGA's PLL has successfully
>> locked to the ADC clock, and what the current measured board clock is.
>>
>> Cheers
>> Jack
>>
>> On Wed, 29 Mar 2017 at 14:28 Matt Dexter  wrote:
>>
>> Is the design and lab setup consistent with the limitations documented at
>> https://casper.berkeley.edu/wiki/ADC16x250-8#ADC16_Sample_
>> Rate_vs_Virtex-6_MMCM_Limitations
>> ?
>>
>> More information on the clock requirements may be found at
>> https://casper.berkeley.edu/wiki/ADC16x250-8_coax_rev_2#
>> ADC16x250-8_coax_rev_2_Inputs
>>
>> Matt
>>
>> On Wed, 29 Mar 2017, vijay kumar wrote:
>>
>> > Date: Wed, 29 Mar 2017 17:16:34 -0400
>> > From: vijay kumar 
>> > To: casper@lists.berkeley.edu
>> > Subject: [casper] ADC calibration issue
>> >
>> > Hello Casperites,
>> > I have been working on the ROACH-2 casper for the past few months. Now
>> i have started to capture values from the ADC
>> > 16x250-8 block. But, when I am trying to run the initialization script,
>> it gives me an error saying that "chip 'x'
>> > chan 'x' lane 'x' no good taps found  ". I am unable to figure out what
>> might be causing this error. I would be glad
>> > if I could get help from you guys.
>> >
>> > Thank you.
>> >
>> >
>> > With regards
>> > Vijay
>> >
>> > --
>> > You received this message because you are subscribed to the Google
>> Groups "casper@lists.berkeley.edu" group.
>> > To unsubscribe from this group and stop receiving emails from it, send
>> an email to
>> > casper+unsubscr...@lists.berkeley.edu.
>> > To post to this group, send email to casper@lists.berkeley.edu.
>> >
>> >
>>
>> --
>> You received this message because you are subscribed to the Google Groups
>> "casper@lists.berkeley.edu" group.
>> To unsubscribe from this group a

[casper] UDP Server for XPS iBOB base

[Mark Wagner]

Hi All,

Andrew and I have put together a memo for the XPS iBOB base UDP Server.  
It's on the casper wiki (casper.berkeley.edu/wiki) under 'memos.'  The 
new UDP version of XPS_iBOB_base.zip is also on the wiki under 
'downloads.'  The server should improve performance and decrease memory 
footprint of any IBOB lwip designs.  If there's any questions, please 
let me know.


Thanks,

Mark

Re: [casper] bit width setting of pbf filter and fft widtband

[Mark Wagner]

Hi Wan,

Jason says that he has been able to use 25 bitwidth in the past without 
issues, but there's been some changes to the FFT recently and i've had 
some troubles as well with other bitwidths.  I recommend using only 18 
bits right now.  If I find a fix, i'll let you know.


Thanks,
Mark

wan.ch...@csiro.au wrote:

Hi:
 
Is there any instructions to set the bit width of PFB and FFT?
 
When I set output bitwidth of PBF to 25, I get a wrong spectrum 
output. But it works well when the bitwidth is set to 18.
 
I guess something might be over flow in the FFT block.
 
Any idea on the bitwidth of PFB and FFT?
 
Thanks
 
Wan
 

Re: [casper] build error

[Mark Wagner]

Hi John,

I think this is a permissions error.  Did you check out the library or did
someone else?  The file may have gotten corrupted.  I would just try
checking out mlib_devel_10_1 from the repository again and see if that
helps.

Mark

On Mon, Nov 2, 2009 at 4:18 PM, John Ford  wrote:

> Hi all.  I'm installing a new incarnation of our build system on a new
> machine.  It's 10.1.03.  With a simple roach example, I get the following
> error:
> ...
> XSG generation complete.
> #
> ## Copying base system ##
> #
> 
> ## Copying custom IPs ##
> 
> ##
> ## Creating Simulink IP ##
> ##
> ##
> ## Creating EDK files   ##
> ##
> #
> ## Elaborating objects ##
> #
> ##
> ## Preparing software files ##
> ##
> #
> ## Running EDK backend ##
> #
>
> blah blah blah, it's happily using up my disk... then:
>
>
> Creating Script File ...
>
> #--#
> # Starting program ngdbuild
> # ngdbuild -p xc5vsx95tff1136-1 -nt timestamp -uc system.ucf
> "C:/work/roachtest/XPS_ROACH_base/implementation/system.ngc" system.ngd
> #--#
> Release 10.1.03 - ngdbuild K.39 (nt)
> Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
>
> Command Line: ngdbuild -p xc5vsx95tff1136-1 -nt timestamp -uc system.ucf
> C:/work/roachtest/XPS_ROACH_base/implementation/system.ngc system.ngd
>
> Reading NGO file
> "C:/work/roachtest/XPS_ROACH_base/implementation/system.ngc"
> ...
> ERROR:ConstraintSystem:8 - The file 'system.ucf' could not be opened for
>   reading.
>
> Loading design module
>
> "C:/work/roachtest/XPS_ROACH_base/implementation/infrastructure_inst_wrapper.ngc
> "...
> Loading design module
>
> "C:/work/roachtest/XPS_ROACH_base/implementation/reset_block_inst_wrapper.ngc"..
> .
> Loading design module
> "C:/work/roachtest/XPS_ROACH_base/implementation/opb0_wrapper.ngc"...
> Loading design module
>
> "C:/work/roachtest/XPS_ROACH_base/implementation/epb_opb_bridge_inst_wrapper.ngc
> "...
> Loading design module
>
> "C:/work/roachtest/XPS_ROACH_base/implementation/epb_infrastructure_inst_wrapper
> .ngc"...
> Loading design module
>
> "C:/work/roachtest/XPS_ROACH_base/implementation/sys_block_inst_wrapper.ngc"...
> Loading design module
>
> "C:/work/roachtest/XPS_ROACH_base/implementation/roachtest_xsg_core_config_wrapp
> er.ngc"...
> Loading design module
>
> "C:/work/roachtest/XPS_ROACH_base/implementation/roachtest_software_register_wra
> pper.ngc"...
> Loading design module
>
> "C:/work/roachtest/XPS_ROACH_base/implementation/roachtest_software_register1_wr
> apper.ngc"...
> Gathering constraint information from source properties...
> Done.
>
> Applying constraints in "system.ucf" to the design...
> ERROR:ConstraintSystem:8 - The file 'system.ucf' could not be opened for
>   reading.
>
> Resolving constraint associations...
> Checking Constraint Associations...
> Done...
> Checking Partitions ...
>
> Checking expanded design ...
> WARNING:NgdBuild:443 - SFF primitive
>
> 'roachtest_XSG_core_config/roachtest_XSG_core_config/default_clock_driver/xlc
>
> lockdriver_1/clr_reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_i
>   s_0.fdre_comp' has unconnected output pin
> WARNING:NgdBuild:452 - logical net 'N18' has no driver
> WARNING:NgdBuild:452 - logical net 'N19' has no driver
> WARNING:NgdBuild:452 - logical net 'N20' has no driver
> WARNING:NgdBuild:452 - logical net 'N21' has no driver
> WARNING:NgdBuild:452 - logical net 'N22' has no driver
> WARNING:NgdBuild:452 - logical net 'N23' has no driver
> WARNING:NgdBuild:452 - logical net 'N24' has no driver
> WARNING:NgdBuild:452 - logical net 'N25' has no driver
> WARNING:NgdBuild:452 - logical net 'N26' has no driver
> WARNING:NgdBuild:452 - logical net 'N27' has no driver
> WARNING:NgdBuild:452 - logical net 'N28' has no driver
> WARNING:NgdBuild:452 - logical net 'N29' has no driver
> WARNING:NgdBuild:452 - logical net 'N30' has no driver
> WARNING:NgdBuild:452 - logical net 'N31' has no driver
> WARNING:NgdBuild:452 - logical net 'N32' has no driver
> WARNING:NgdBuild:452 - logical net 'N33' has no driver
>
> Partition Implementation Status
> ---
>
>  No Partitions were found in this design.
>
> ---
>
> NGDBUILD Design Results Summary:
>  Number of errors: 2
>  Number of warnings:  17
>
>
> One or more errors were found during NGDBUILD.  No NGD file will be
> written.
>
> Any ideas?  I'm stumped.
>
> John
>
>
>
>
>

Re: [casper] over mapping

[Mark Wagner]

Hi Laura,

For FPGA utilization, I look at the file:
sysgen/synth_model/modelfilename_cw.syr

Mark


On Wed, Nov 18, 2009 at 2:26 PM, Laura Spitler wrote:

> Hi everyone,
>
> I have a general question about over mapping a design. What's the
> easiest way to determine by how much I've over utilized the chip?
> The log files don't seem to give a resource summary when mapping fails
> with an error.
>
> Thanks!
> Laura
>
>

Re: [casper] Writing to BRAM

[Mark Wagner]

Hi Ousseama,

I wrote the attached file awhile ago.  It should work if I remember
correctly.  After you compile it, execute it and it will tell you what the
arguments are.

Mark



On Mon, Nov 23, 2009 at 8:51 PM, Oussama Sekkat  wrote:

> Hi All,
>
> Does anyone happens to have C code already written that takes an input file
> and writes the content of that file into a shared BRAM in BORPH?
>
> Oussama.
>
>
>
#include 
#include 
#include 

/*

== INPUT ==
arg 1 is the tvg process number 
arg 2 is starting bram address to write
arg 3 is ending bram address to write
arg 4 is bram name
arg 5 is data file of values to be written 

== OUTPUT (stdout) ==
column 1 is the bram address 
column 2 is the value

*/

int main(int argc,char **argv)
{
if(argv[1] == NULL)
{
	printf("Usage: arite_bram \n");
}
else
{
	FILE *bram_file,*data_file;
	char bram[200];
	char file[100];
	char tmp[100];
	memset(file,0,100);
	memcpy(file,argv[5],strlen(argv[5]));

	int i;
	int buffer;
 
	sprintf(bram,"/proc/%s/hw/ioreg/%s",argv[1],argv[4]);
	sprintf(tmp,"%s",file);
	bram_file=fopen(bram,"wb");
	data_file=fopen(file,"r");
   
	if(bram_file == NULL)
	{
printf("Error: couldn't open file '%s'\n",bram); 
return 1;
	}

for(i=atoi(argv[2]);i<=atoi(argv[3]);i++)
{
	fscanf(data_file,"%s\n",tmp); 
	buffer=atof(tmp)*32767;
   
printf("%d %d\n",i,buffer);
fwrite(&buffer,sizeof(int),1,bram_file);
}

fclose(bram_file);
	fclose(data_file);
}
return 0;
}

Re: [casper] Silly NFS problem

[Mark Wagner]

Hi Glenn,

My /etc/exports file has the line:

/srv/roachfs192.168.1.0/24(rw,subtree_check,no_root_squash,insecure)

I think you should only have the one line that exports /srv/roach_boot,
without the etch.  If that doesn't work, I would try seeing if I could mount
/srv/roach_boot on a different computer.

Mark


On Fri, Dec 11, 2009 at 5:05 PM, G Jones  wrote:

> Hello,
> Sorry to bother you all with this, but I'm having trouble getting my
> ROACH to mount the network file system. I followed the guide, and the
> DHCP seems to work as well as the TFTP portion. However, when it's
> time to mount the root file system, I get:
>
> Sending DHCP requests ., OK
> IP-Config: Got DHCP answer from 192.168.0.1, my address is 192.168.0.8
> IP-Config: Complete:
> device=eth0, addr=192.168.0.8, mask=255.255.0.0, gw=255.255.255.255,
> host=192.168.0.8, domain=, nis-domain=(none),
> bootserver=192.168.0.1, rootserver=192.168.0.1,
> rootpath=/srv/roach_boot/etch
> Looking up port of RPC 13/2 on 192.168.0.1
> Looking up port of RPC 15/1 on 192.168.0.1
> Root-NFS: Server returned error -13 while mounting /srv/roach_boot/etch
> VFS: Unable to mount root fs via NFS, trying floppy.
> VFS: Cannot open root device "192.168.0.1:/srv/roach_boot/etch" or
> unknown-block(2,0)
> Please append a correct "root=" boot option; here are the available
> partitions:
> 0100   4096 ram0 (driver?)
> ...
>
> 1f05384 mtdblock5 (driver?)
> Kernel panic - not syncing: VFS: Unable to mount root fs on
> unknown-block(2,0)
> Rebooting in 180 seconds..System Hardware Reset
>
>
> I've tried googling a while on the "error -13" message and see that it
> means that my nfs server is saying access denied. However, I can't
> figure out why this is.
> I've tried doing chmod -R 777 /srv/roach_boot/etch but no change.
> My /etc/exports file is as follows:
> /srv/roach_boot/etch 192.168.0.0(rw,subtree_check,no_root_squash,insecure)
>
> I've also tried exporting /srv/roach_boot
>
> $sudo exportfs
> /srv/roach_boot/etch
>192.168.0.0
> /srv/roach_boot
>192.168.0.0
>
>
> I appreciate any help solving what I'm sure is a silly linux problem.
> My server is debian lenny if it matters.
>
> Thanks,
> Glenn
>
>

[casper] strange error

[Mark Wagner]

Has anyone seen this:

standard exception: XNetlistEngine: An exception was raised:
com.xilinx.sysgen.netlist.NetlistInternal: couldn't open first pass text
file at
/home/mwagner/workspace/roach_mspec/mdls/rmspec/sysgen/sysgen/masterScript7818408840409605852.pl
line 15370 Reported by: Unspecified

I've installed 11.4 and casper libraries with matlab2009a and get the above
error during generation using Dave's 1M channel spectrometer to test it.
 This design has compiled fine under 11.3.  The file that is being
referenced here does exist and is readable by 'all', so I don't see what the
issue is.  Any suggestions would be most appreciated.

Cheers,
Mark

Re: [casper] strange error

[Mark Wagner]

Thanks guys, unfortunately the delete and replace didn't work.  I'll try to
sift through that huge perl script to see what's going on.

Cheers,
Mark

On Thu, Dec 24, 2009 at 12:01 PM, Billy Mallard  wrote:

> Mark Wagner wrote:
> >Has anyone seen this:
> >
> >standard exception: XNetlistEngine: An exception was raised:
> >com.xilinx.sysgen.netlist.NetlistInternal: couldn't open first pass
> >text file at
> >/home/mwagner/workspace/roach_mspec/mdls/rmspec/sysgen/sysgen/
> >masterScript7818408840409605852.pl
> >line 15370 Reported by: Unspecified
> ...
> >The file that is being referenced here does exist and is readable
> >by 'all', so I don't see what the issue is.
>
> I encountered this problem just a few days ago.  It went away when i
> deleted the System Generator and XSG Core Config blocks and replaced
> them with fresh ones from the library.
>
> Billy
>

Re: [casper] strange error

[Mark Wagner]

HI John, thanks for the advice, I don't think this is the problem though.
 It seems the script is giving an error during core generation.  I'm using
11.4 and this perl script is also longer than the one I generated in 11.3.
 I think this is going to require an email to Xilinx support.

Mark

On Sat, Dec 26, 2009 at 6:08 AM, John Ford  wrote:

>
> Maybe the path is too long?  Try a directory closer to the root.
>
>
> > Mark Wagner wrote:
> >>Has anyone seen this:
> >>
> >>standard exception: XNetlistEngine: An exception was raised:
> >>com.xilinx.sysgen.netlist.NetlistInternal: couldn't open first pass
> >>text file at
> >>/home/mwagner/workspace/roach_mspec/mdls/rmspec/sysgen/sysgen/
> >>masterScript7818408840409605852.pl
> >>line 15370 Reported by: Unspecified
> > ...
> >>The file that is being referenced here does exist and is readable
> >>by 'all', so I don't see what the issue is.
> >
> > I encountered this problem just a few days ago.  It went away when i
> > deleted the System Generator and XSG Core Config blocks and replaced
> > them with fresh ones from the library.
> >
> > Billy
> >
>
>
>

Re: [casper] read-only file system

[Mark Wagner]

Hi Tom,

I needed to change root=/dev/sda1 rw to root='/dev/sda1 rw' (add qoutes) in
the command below to get the usb filesystem mounted read/write.

Mark



On Thu, Jan 14, 2010 at 2:39 PM, Tom Downes  wrote:

> Yes, it boots read-only even trying to set usbboot as below.  Though, as I
> said, I cannot set mtdparts=${partitions}, I have to remove the dollar
> sign.  If that is important then I'm not sure what to do because if I leave
> the dollar sign in it immediately boots and not to USB.
>
>
> setenv usbboot bootargs console=ttyS0,115200 mtdparts=${partitions}
> rootdelay=8 root=/dev/sda1 rw; bootm fc00
>
> I'll look into things more this afternoon.
>
> Tom
>
>
> On Tue, Jan 12, 2010 at 8:22 AM, Zhiwei Liu  wrote:
>
> Tom,
>>
>> Do you mean it still mounts the new filesystem read-only even if you
>> change the usbboot environment to "bootargs console=ttyS0,115200
>> mtdparts=${partitions}
>> rootdelay=8 root=/dev/sda1 rw; bootm fc00"?
>>
>> I wish I could play with the environment a little bit, but I made it to
>> boot off the USB stick automatically.
>> I can not interrupt the standard boot process at uboot. I'm still
>> struggling to bring it back to the standard
>> boot process, It seems like I have to reload the uboot to overwrite the
>> 'bootargs' environment.
>>
>> FYR, I also had some warnings when booting.
>> --
>> EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
>> VFS: Mounted root (ext2 filesystem).
>> Freeing unused kernel memory: 136k init
>> INIT: version 2.86 booting
>> warning: can't open /etc/mtab: No such file or directory
>> mount: wrong fs type, bad option, bad superblock on tmpfs,
>>missing codepage or other error
>>In some cases useful info is found in syslog - try
>>dmesg | tail  or so
>> ---
>> I don't know how to fix that.
>>
>> Zhiwei
>>
>>
>>
>>
>> On Tue, Jan 5, 2010 at 5:18 PM, Tom Downes  wrote:
>>
>>> Zhiwei (and others):
>>>
>>> We are having the same problem as you upon upgrading to the 20091006
>>> kernel and the 20091130 etch file system on USB.  We have an older
>>> filesystem (don't recall the date) on one USB stick and the new one on
>>> another.  Both USB sticks are formatted ext2 and are the same
>>> brand/model.
>>>
>>> For some reason, when booting by "run usbboot" it will mount the old
>>> filesystem read-write but the new filesystem read-only.  Doing a
>>> remount fixes the problem, but of course the boot process has had a
>>> number of failures along the way.
>>>
>>> This is after changing the usbboot environment variable to what you
>>> list, but when I try to do it with the dollar sign for partitions it
>>> immediately runs.  So if I remove that, it will work.  Is that really
>>> an environment variable?  In any case, it works for one system, but
>>> not the other so I'm not sure it's the issue precisely.
>>>
>>> setenv usbboot bootargs console=ttyS0,115200 mtdparts=${partitions}
>>> rootdelay=8 root=/dev/sda1 rw; bootm fc00
>>> saveenv
>>> run usbboot
>>>
>>> (minus the dollar sign for mtdparts)
>>>
>>> For both USB sticks it will complain about the file systems not having
>>> been checked.  I have gone through and run "tune2fs -c 0 -i 0" on the
>>> new stick and done a manual force check with "e2fsck -fp".  On the
>>> ROACH and on a true desktop.  Yet it still gives the error.  My
>>> impression is that sometimes the kernel will mount an ext2 fs
>>> read-only if it doesn't think that it has been checked.  I would think
>>> that this is the source of the problem were it not for the fact that
>>> the same kernel mounts one disk read-write and the other read-only.
>>>
>>> I usually get the date set correctly along the way and do soft reboots
>>> so that the clock doesn't get too far off.  Otherwise I would be
>>> concerned about automatic checks for a given number of days (despite
>>> my use of tune2fs).
>>>
>>> In both cases it also complains about the jffs2 filesystem not
>>> mounting properly at the very end of boot.
>>>
>>> I'm a bit baffled...
>>>
>>> Tom
>>>
>>>
>>
>

Re: [casper] read-only file system

[Mark Wagner]

Hi Tom,

Have any of these permutations worked for you?  I've gotten it to boot with
the command I sent you earlier, but Jason also mentioned to me awhile ago
that editing the fstab file would work too, but I haven't tried that yet.

Mark

On Thu, Jan 14, 2010 at 3:23 PM, Tom Downes  wrote:

> Mark:
>
> I think the problem might be more basic.  I have not found clear
> instructions on the precise command that one is supposed to run to change
> the usbboot environment variable.  It appears to be csh-like environment
> that one is greeted with when you break the automatic boot process.
>
> I think the problem that I was having before was that when I ran:
>
> setenv usbboot bootargs console=ttyS0,115200 mtdparts=${partitions}
> rootdelay=8 root=/dev/sda1 rw; bootm fc00
>
> it interpreted "bootm fc00" as a 2nd command rather than part of the
> setenv.  It also seems like there should be a second setenv after usbboot so
> that usbboot is not so much an environment variable itself as a shorthand
> for setting the bootargs environment variable to values appropriate for
> booting by USB.
>
> So... I have tried a number of permutations of the below code, putting in
> single/double quotes all around (to manipulate whether the $ is interpreted
> literally or whether its value is taken in), including where you suggest and
> around ${partitions}.  Putting single or double quotes around the whole
> thing allows the setenv commad to be interpreted as a single command rather
> than one setenv followed by a bootm.
>
> Variation of what I have tried:
>
> setenv usbboot 'setenv bootargs console=ttyS0,115200 mtdparts=${partitions}
> rootdelay=8 root=/dev/sda1 rw; bootm fc00'
>
> Sorry for being obtuse, but I'm not sure this booting environment is really
> csh/tcsh or just some extremely basic CLI.
>
> Tom
>
> On Thu, Jan 14, 2010 at 2:46 PM, Mark Wagner wrote:
>
>> Hi Tom,
>>
>> I needed to change root=/dev/sda1 rw to root='/dev/sda1 rw' (add qoutes)
>> in the command below to get the usb filesystem mounted read/write.
>>
>> Mark
>>
>>
>>
>> On Thu, Jan 14, 2010 at 2:39 PM, Tom Downes  wrote:
>>
>>> Yes, it boots read-only even trying to set usbboot as below.  Though, as
>>> I said, I cannot set mtdparts=${partitions}, I have to remove the dollar
>>> sign.  If that is important then I'm not sure what to do because if I leave
>>> the dollar sign in it immediately boots and not to USB.
>>>
>>>
>>> setenv usbboot bootargs console=ttyS0,115200 mtdparts=${partitions}
>>> rootdelay=8 root=/dev/sda1 rw; bootm fc00
>>>
>>> I'll look into things more this afternoon.
>>>
>>> Tom
>>>
>>>
>>> On Tue, Jan 12, 2010 at 8:22 AM, Zhiwei Liu wrote:
>>>
>>> Tom,
>>>>
>>>> Do you mean it still mounts the new filesystem read-only even if you
>>>> change the usbboot environment to "bootargs console=ttyS0,115200
>>>> mtdparts=${partitions}
>>>> rootdelay=8 root=/dev/sda1 rw; bootm fc00"?
>>>>
>>>> I wish I could play with the environment a little bit, but I made it to
>>>> boot off the USB stick automatically.
>>>> I can not interrupt the standard boot process at uboot. I'm still
>>>> struggling to bring it back to the standard
>>>> boot process, It seems like I have to reload the uboot to overwrite the
>>>> 'bootargs' environment.
>>>>
>>>> FYR, I also had some warnings when booting.
>>>> --
>>>> EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
>>>> VFS: Mounted root (ext2 filesystem).
>>>> Freeing unused kernel memory: 136k init
>>>> INIT: version 2.86 booting
>>>> warning: can't open /etc/mtab: No such file or directory
>>>> mount: wrong fs type, bad option, bad superblock on tmpfs,
>>>>missing codepage or other error
>>>>In some cases useful info is found in syslog - try
>>>>dmesg | tail  or so
>>>> ---
>>>> I don't know how to fix that.
>>>>
>>>> Zhiwei
>>>>
>>>>
>>>>
>>>>
>>>> On Tue, Jan 5, 2010 at 5:18 PM, Tom Downes wrote:
>>>>
>>>>> Zhiwei (and others):
>>>>>
>>>>> We are having the same problem as you upon upgrading t

Re: [casper] BEE2 hanging

[Mark Wagner]

Hi John,

Are you running this arm() command on the BEE2 or are you using a udp or tcp
server?  Does it write the value in ascii or binary mode?  BORPH has
occasionally acted strangely for us when we use ascii mode so we don't use
it anymore.

Mark

On Fri, Jan 29, 2010 at 1:23 PM, John Ford  wrote:

> Hi all.
>
> We're working hard on cleaning up our 800 MHz Coherent Dedispersion pulsar
> machine for production.  We have it working with 8 GPU machines, and from
> 64 to 2048 coarse channels.
>
> One problem we have is that with our output FPGA that rearranges the data
> and ships it off simultaneously over 4 10 GbE ports, sometimes sending an
> arm() command (which tells the system to start on the next 1 PPS) locks up
> the communication with that FPGA.
>
> The arm command (python) just does 2 writes to the same register, first
> sending a zero, then sending a one after sleeping for a second.
>
> If we kill the program that's trying to write to the fpga, we can unload
> the bof and reload it, it starts working again.  Then it will fail again
> with an arm() at some random number of times later.
>
> It seems to fail more often if we run the system at high speed.  Paul says
> it doesn't fail at all at 200 MHz, instead of our usual 800 MHz ADC clock
> rate.
>
> Our previous design that is for the regular guppi modes does not do this.
>
> Any ideas where to look for this?
>
> Does trying to read or write a non-existent register make borph unhappy
> enough to smite us?
>
> Thanks for any insight.
>
> John
>
>
>
>

[casper] filesystem update

[Mark Wagner]

I updated my usb stick to the filesystem:
http://casper.berkeley.edu/svn/trunk/roach/sw/binaries/filesystem/filesystem_etch_2009-11-30.tar.bz

when I 'run usbboot' I get to:

sd 1:0:0:0: [sda] 15794175 512-byte hardware sectors (8087 MB)
sd 1:0:0:0: [sda] Write Protect is off
sd 1:0:0:0: [sda] Assuming drive cache: write through
sd 1:0:0:0: [sda] 15794175 512-byte hardware sectors (8087 MB)
sd 1:0:0:0: [sda] Write Protect is off
sd 1:0:0:0: [sda] Assuming drive cache: write through
 sda: sda1
sd 1:0:0:0: [sda] Attached SCSI removable disk
EXT2-fs warning (device sda1): ext2_fill_super: mounting ext3 filesystem as
ext2

VFS: Mounted root (ext2 filesystem) readonly.
Freeing unused kernel memory: 136k init
Warning: unable to open an initial console.
warning: `ntpd' uses 32-bit capabilities (legacy support in use)

and then the boot process freezes.  I've repartitioned and rebuilt the
filesystem as ext3 and then simply copied (cp -rp) over the files as i've
done on other working usb sticks.  Any suggestions?

Thanks,
Mark

Re: [casper] filesystem update

[Mark Wagner]

Thanks guys, I tried that and it seems to work now.

Mark

On Mon, Feb 1, 2010 at 3:57 AM, Andy Lutomirski  wrote:

> cp -rp might not be enough -- the docs are vague on what it does to
> symlinks.  cp -a may be a better bet.
>
> Also, you can convert ext2 to ext3 directly using tune2fs -j.
>
>
> --Andy
>
>
> On Feb 1, 2010, at 2:40 AM, Mark Wagner  wrote:
>
> I updated my usb stick to the filesystem:
>
> <http://casper.berkeley.edu/svn/trunk/roach/sw/binaries/filesystem/filesystem_etch_2009-11-30.tar.bz>
> http://casper.berkeley.edu/svn/trunk/roach/sw/binaries/filesystem/filesystem_etch_2009-11-30.tar.bz
>
> when I 'run usbboot' I get to:
>
> sd 1:0:0:0: [sda] 15794175 512-byte hardware sectors (8087 MB)
> sd 1:0:0:0: [sda] Write Protect is off
> sd 1:0:0:0: [sda] Assuming drive cache: write through
> sd 1:0:0:0: [sda] 15794175 512-byte hardware sectors (8087 MB)
> sd 1:0:0:0: [sda] Write Protect is off
> sd 1:0:0:0: [sda] Assuming drive cache: write through
>  sda: sda1
> sd 1:0:0:0: [sda] Attached SCSI removable disk
> EXT2-fs warning (device sda1): ext2_fill_super: mounting ext3 filesystem as
> ext2
>
> VFS: Mounted root (ext2 filesystem) readonly.
> Freeing unused kernel memory: 136k init
> Warning: unable to open an initial console.
> warning: `ntpd' uses 32-bit capabilities (legacy support in use)
>
> and then the boot process freezes.  I've repartitioned and rebuilt the
> filesystem as ext3 and then simply copied (cp -rp) over the files as i've
> done on other working usb sticks.  Any suggestions?
>
> Thanks,
> Mark
>
>
>
>
>

[casper] 11.4 issues

[Mark Wagner]

I have recently tried to install Xilinx 11.4 and have run into a standard
exception error involving the System Generator generated perl script
MasterScriptXXX.pl.  This error has occurred on Ubuntu 8.04, 9.10 and Fedora
12.  Xilinx support would not answer questions until I installed a supported
OS (Red Hat Enterprise 5 or Suse Enterprise Linux 10).  I tried RHE5 and the
error went away and my design compiled. A possible free alternative is
CentOS and is supposed to follow the same distribution cycle and carry the
same packages and versions as RHE5, but I have not tried this and I doubt
Xilinx would support it.

The cost of a RHE5 license is zero compared to say, a switch, so I think
that's the option we're looking at here in Berkeley.

Mark

Re: [casper] 11.4 issues

[Mark Wagner]

HI Griffin,

I have not come up with a solution to this problem other than using a
supported OS (RHEL5).  I did try exporting the variables you mentioned and
then generating a simple design again in Ubuntu, but am still getting the
same MasterScriptxxx.pl error.

At this point our solution is to migrate over to RHEL5.  I wish we didn't
have to do this, but it's the only thing that seems to fix the problem and
will assure us Xilinx technical support for future issues.

Mark


On Tue, Feb 9, 2010 at 10:12 AM, Griffin Foster wrote:

> Well my coregen problem was a minor one(forgot to set my paths). But the
> next issue i have is I get an "NGC Netlisting Error". This comes up as a
> dialogue box in matlab, it is rather long but the short of it is:
>
> "NGC Netlisting Error"
>
> [: 21:
> /opt/Xilinx/11.1/ISE/lib/lin64: ... : unexpected operator
> [: 22:
> /opt/Xilinx/11.1/DSP_Tools/lin64/sysgen/lib: ... : unexpected operator
>
> on my last email:
> >> export PERL4LIB=/opt/Xilinx/11.1/DSP_Tools/lin64/sysgen/scripts;$PERLLIB
>
> should be:
> export PERLLIB=/opt/Xilinx/11.1/DSP_Tools/lin64/sysgen/scripts;$PERLLIB
>
> -Griffin
>
> On Feb 9, 2010, at 5:55 PM, John Ford wrote:
>
> >> Hey Mark, I get the same error with ubuntu 9.10, xilinx 11.4. At first I
> >> had a problem with perl looking for module with it's @INC variable, my
> fix
> >> was to add the following lines to my .bashrc file:
> >>
> >> export
> PERL5LIB=/opt/Xilinx/11.1/DSP_Tools/lin64/sysgen/scripts;$PERL5LIB
> >> export PERL4LIB=/opt/Xilinx/11.1/DSP_Tools/lin64/sysgen/scripts;$PERLLIB
> >>
> >> But that only got me down to line 329 of the masterscript.pl The
> >> output to script_results I am now getting is 'Could not find the
> >> "coregen" executable. at masterScript.pl line 329' . Did you find a
> >> solution or does anyone else have any ideas about this? Thanks.
> >
> > One thing we found with 11.3 on Linux was that somthing in the system
> does
> > not like symbolic links.  Maybe that's part of this problem, but worse.
> >
> > John
> >
> Yeah, I'm finding that they aren't working also.
>
> >>
> >> -Griffin
> >>
> >> On Feb 3, 2010, at 10:30 PM, Tom Kuiper wrote:
> >>
> >>> Mark Wagner wrote:
> >>>> I have recently tried to install Xilinx 11.4 and have run into a
> >>>> standard exception error involving the System Generator generated perl
> >>>> script MasterScriptXXX.pl.  This error has occurred on Ubuntu 8.04,
> >>>> 9.10 and Fedora 12.  Xilinx support would not answer questions until I
> >>>> installed a supported OS (Red Hat Enterprise 5 or Suse Enterprise
> Linux
> >>>> 10).  I tried RHE5 and the error went away and my design compiled. A
> >>>> possible free alternative is CentOS and is supposed to follow the same
> >>>> distribution cycle and carry the same packages and versions as RHE5,
> >>>> but I have not tried this and I doubt Xilinx would support it.
> >>>>
> >>>> The cost of a RHE5 license is zero compared to say, a switch, so I
> >>>> think that's the option we're looking at here in Berkeley.
> >>> I have a feeling that if you dig a little deeper you may find that Perl
> >>> is trying to use a relocatable library that it can't find.  You
> probably
> >>> have it and can find it with 'locate'.  A symlink may then solve the
> >>> problem.
> >>>
> >>> Changing OS to RH will cause a big headache if you have locally
> compiled
> >>> headaches.
> >>>
> >>> I suspect that, like Microsoft, this is a game RH plays to freeze out
> >>> the competition.  I imagine that vendors like RH because they can have
> a
> >>> commercial relationship with them, especially technical support,
> unlike,
> >>> say, Debian.
> >>>
> >>> Cheers
> >>>
> >>> Tom
> >>>
> >>
> >>
> >>
> >
> >
>
>
>

Re: [casper] ROACH updates

[Mark Wagner]

This works, i'm updating the wiki.

On Wed, Feb 17, 2010 at 6:35 AM, Jason Manley wrote:

> The new filesystem has an explicit remount read-only line in rcSimple. To
> quote zhiwei liu from an earlier email:
>
> To compare to the old filesystem, the /etc/rcSimple file in the new
> filesystem has a line like:
>
> mount -n -o remount, ro, noatime /
>
> I think that is the problem.  If you mark or delete this line, it will
> mount the filesystem writeable.
>
> Try this and let me know if you're still having trouble.
>
> Jason
>
>
> On 17 Feb 2010, at 06:15, Griffin Foster wrote:
>
>  I've been setting up ROACH boards using the new recommended linux kernel
>> and filesystem but I seem to be getting a problem about the NFS mount being
>> read only. My export file is set to rw and when I am using
>> filesystem_etch_2009_08_14.tar.bz2 with the same setting the mount works as
>> rw. I thought it might be some thing to do with the warning I get on the
>> serial, "warning: can't open /etc/mtab: No such file or directory" but both
>> of the filesystem have that same warning. The mtab for the etch_2009-11-30
>> has /dev/root / nfs ro,... while etch_2009_08_14 has /dev/root / nfs rw,...
>> . I don't know how this /proc/mount file is created, does anyone have an
>> idea about whats going on? Could this be caused by CPLD or uBoot not being
>> the latest versions?
>>
>> -Griffin
>>
>> On Dec 1, 2009, at 7:33 AM, Jason Manley wrote:
>>
>>  Hi CASPERites with ROACH boards...
>>>
>>> Firmware and Software:
>>> ==
>>> You might consider applying the following updates. These versions are
>>> considered "stable" and are currently in use by KAT. In order of priority:
>>>
>>> * Update your base-system Simulink SVN repository:
>>>  There have been numerous library fixes, including DRAM and 10GbE. Bus
>>> access also changed back in August and you will need the corresponding
>>> updated CPLD image to maintain compatibility. The open-source XAUI core has
>>> a problem and is disabled at the moment. If using 10GbEv2, it will need to
>>> use Xilinx's XAUI core for now. Likewise with the XAUI block itself.
>>>
>>> * CPLD:
>>> http://casper.berkeley.edu/svn/trunk/roach/gw/binaries/roach_cpld/roach_cpld_8_0_1588.jed
>>>  Major change fixed a bus contention issue. To work reliably, all bof
>>> files compiled with CASPER SVN libraries later than August 18th will require
>>> this update. Bof files generated prior to that date are incompatible and
>>> should be recompiled with an updated SVN checkout. This updated CPLD image
>>> is also needed to enable MMC/SD card support.
>>>
>>> * Uboot:
>>> http://casper.berkeley.edu/svn/trunk/roach/sw/binaries/uboot/uboot-clkfix-20091113.bin
>>>  Various bus fixes and clock speed corrections. Onboard FPU test
>>> disabled. If you're recompiling uboot from source, it may not work as
>>> expected (it hangs after unpacking the Linux kernel). A bug appears to have
>>> crept-in the Uboot source-code of SVN head revision. We're trying to track
>>> it down, but until then, use this provided binary.
>>>
>>> * Linux Kernel:
>>> http://casper.berkeley.edu/svn/trunk/roach/sw/binaries/linux/uImage-20091006-mmcfix
>>>  Various fixes, primarily:
>>>  *) SD/MMC support.
>>>  *) Fixes to system clock timekeeping.
>>>  *) Support for RTC and monitoring system health through lmsensors
>>> and /proc filesystem entries.
>>>  *) Shutdown support (when you press ROACH's power button, system
>>> will cleanly shutdown, just like your computer).
>>>
>>> * Linux Root filesystem:
>>> http://casper.berkeley.edu/svn/trunk/roach/sw/binaries/filesystem/filesystem_etch_2009-11-30.tar.bz
>>>  Various fixes, primarily:
>>>  *) added SD/MMC node;
>>>  *) added devicefile for RTC;
>>>  *) added support for monitoring system health through new lmsensors
>>> (libsensors 3 or 4) and /proc filesystem entries with included sensors.conf
>>>  *) and new tcpborphserver (KATCP server) with ability to open more
>>> than one instance of a tgtap driver. Please note that there is currently a
>>> bug in the 10GbE cores that is causing trouble with the CPU access to the
>>> 10GbE interfaces. Tcpborphserver also does not correctly shutdown tgtap
>>> instances when reprogramming the FPGA, so YMMV. Please note that the
>>> tcpborphserver source code in SVN is currently outdated. There is a rewrite,
>>> tcpborphserver2 on the way.
>>>
>>> * Roach monitor (Actel Fusion):
>>> http://casper.berkeley.edu/svn/trunk/roach/gw/binaries/roach_monitor/roach_monitor_8_3_1698.stp
>>>  and
>>>
>>> http://casper.berkeley.edu/svn/trunk/roach/gw/binaries/roach_monitor/roach_monitor_8_3_1698.ufc
>>>  Minor changes to LED flashing/signalling.
>>>
>>> Real Time Clock
>>> ===
>>> The hardware RTC is not very accurate. It uses the Actel Fusion to keep
>>> time while the PPC is powered-down. It doesn't work when AC is removed,
>>> because then the Fusion loses power and there is no battery backup. It's
>>> simply th

Re: [casper] Compilation errors with FFT block

[Mark Wagner]

Hi Nevada,

If all your casper libraries are linked and updated, the first thing I would
try is deleting the fft and replacing it with a new one from the library,
then recompiling.

Or try running the fft mask script from the matlab command line and see if
you get any other telling errors.

Mark


On Wed, Mar 3, 2010 at 11:10 PM, Nevada Sanchez  wrote:

> I have a rather simples model that takes a signal stored in ram and FFT's
> it. However, I'm having some problems getting it to compile. I get the
> following errors whenever I run 'Update Diagram':
>
> + Block error: twiddle: Simulink: The LinkStatus can be set only for a
> linked block.
> + Block error: twiddle: Simulink: Error in
> 'sysgen_scratch/fft/fft_biplex0/biplex_core/fft_stage_3/butterfly_direct/twiddle':
> Initialization commands cannot be evaluated.
>
> Could somebody help me out with this?
>
> -Nevada
>

Re: [casper] Where is sshd?

[Mark Wagner]

Hi Steve,

On Debian/Ubuntu 'sshd' is at /usr/sbin/sshd, but I would use the script
/etc/init.d/ssh, which should be started at boot.  If not you can try
restarting it yourself:

 /etc/init.d/ssh 

Mark


On Thu, Mar 4, 2010 at 1:48 PM, Steve Maher wrote:

> Hi,
>
> Excitement with our very first ROACH/CASPER experience today when we fired
> up our new roach board.
>
> However, all getting-started & tutorials I find indicate sshd should be
> running but I can't find it anywhere.   Port 22 doesn't answer, no sshd
> running, no results for "busybox find -name "*ssh*".
>
> Do I need a different linux image?
>
> Current:
> Linux version 2.6.25-svn2338 (d...@lappy) (gcc version 4.0.0 (DENX ELDK
> 4.0 4.0.
> 0)) #111 Tue Oct 6 14:24:10 SAST 2009
>
>
> Thanks,
>
> Steve
>
>

Re: [casper] Compilation errors with FFT block

[Mark Wagner]

Hi Nevada,

Have you tried running the mask script from the matlab command line?  This
may give some clues as to what the issue is.

Also, does the twiddle block show up in your casper library?

Mark

On Fri, Mar 12, 2010 at 11:52 AM, Nevada Sanchez  wrote:

> It seems that the problem with the bad links was caused by me not opening
> the libraries on startup. I updated my startup.m script and everything is
> fine, except that I still have to remove the link to the Casper library to
> get the FFT block to compile.
>
> -Nevada
>
> On Mar 12, 2010, at 4:44 AM, John Ford wrote:
>
> >> Is it still necessary in 11.x/RHEL to load/open the CASPER library
> >> before opening a model containing library blocks?
> >
> > Yes, Henry, it is.  We have a startup.m that opens/loads the user's
> > libraries and starts sysgen.
> >
> > Here it is.
> >
> > Yes, Master<1005> more startup.m
> > addpath('/export/home/tokra/scratch/casper/mlib_devel_10_1/xps_library');
> >
> addpath('/export/home/tokra/scratch/casper/mlib_devel_10_1/casper_library');
> >
> addpath('/export/home/tokra/scratch/casper/mlib_devel_10_1/gavrt_library');
> > sysgen_startup
> > system_dependent('RemoteCWDPolicy','reload')
> > system_dependent('RemotePathPolicy','reload')
> > load_system('casper_library');
> > load_system('gavrt_library');
> > Yes, Master<1006>
> >
> > Then of course there are all the environment variable to set.  We also
> > have a script for that:
> >
> > Yes, Master<1006> more Startsg.sh
> > #!/bin/bash
> > source /export/home/tokra/Xilinx/11.1/settings64.sh
> > export MATLAB=/opt/matlab
> > export XILINX=/export/home/tokra/Xilinx/11.1/ISE
> > export XILINX_EDK=/export/home/tokra/Xilinx/11.1/EDK
> > export PLATFORM=lin64
> > export XILINX_DSP=/export/home/tokra/Xilinx/11.1/DSP_Tools/${PLATFORM}
> > export
> > BEE2_XPS_LIB_PATH=/export/home/tokra/scratch/casper/mlib_devel_10_1/xps_l
> > ib
> > export MLIB_ROOT=/export/home/tokra/scratch/casper/mlib_devel_10_1
> > export
> PATH=${XILINX}/bin/${PLATFORM}:${XILINX_EDK}/bin/${PLATFORM}:${PATH}
> > export
> > LD_LIBRARY_PATH=${XILINX}/bin/${PLATFORM}:${XILINX}/lib/${PLATFORM}:${XIL
> > INX_DSP}/sysgen/lib:${LD_LIBRARY_PATH}
> > export LMC_HOME=${XILINX}/smartmodel/${PLATFORM}/installed_lin
> > export PATH=${LMC_HOME}/bin:${XILINX_DSP}/common/bin:${PATH}
> > export INSTALLMLLOC=/opt/matlab
> > export TEMP=/tmp/
> > export TMP=/tmp/
> > $MATLAB/bin/matlab
> >
> >
> > John
> >
> >
> >>
> >> Thanks,
> >> Henry
> >>
> >> On 3/11/2010 11:46 PM, Nevada Sanchez wrote:
> >>> I've tried deleting and replacing (even creating an entirely new model)
> >>> with no luck. I managed to fix it be destroying the link of the FFT
> >>> module back to the Casper library and all is well now. Except that I
> >>> don't think I should have to do that.
> >>>
> >>> Anyway, I've been having another annoyance that may be related to this
> >>> problem. Every time I open a model, all of the casper and xps blocks
> >>> have bad links until I drag one of the blocks from their respective
> >>> libraries into the file. The libraries are in the path and they show up
> >>> in the library browser. Any ideas on what might be going wrong here?
> >>>
> >>> If it helps, we're running Xilinx tools version 11.4, with the latest
> >>> snapshot of the casper repository on RHEL 5.
> >>>
> >>> -Nevada
> >>>
> >>> On Mar 4, 2010, at 2:18 AM, Mark Wagner wrote:
> >>>
> >>>> Hi Nevada,
> >>>>
> >>>> If all your casper libraries are linked and updated, the first thing I
> >>>> would try is deleting the fft and replacing it with a new one from the
> >>>> library, then recompiling.
> >>>>
> >>>> Or try running the fft mask script from the matlab command line and
> >>>> see if you get any other telling errors.
> >>>>
> >>>> Mark
> >>>>
> >>>>
> >>>> On Wed, Mar 3, 2010 at 11:10 PM, Nevada Sanchez  >>>> <mailto:nev...@mit.edu>> wrote:
> >>>>
> >>>>I have a rather simples model that takes a signal stored in ram
> >>>>and FFT's it. However, I'm having some problems getting it to
> >>>>compile. I get the following errors whenever I run 'Update
> >>>> Diagram':
> >>>>
> >>>>+ Block error: twiddle: Simulink: The LinkStatus can be set only
> >>>>for a linked block.
> >>>>+ Block error: twiddle: Simulink: Error in
> >>>>
>  
> 'sysgen_scratch/fft/fft_biplex0/biplex_core/fft_stage_3/butterfly_direct/twiddle':
> >>>>Initialization commands cannot be evaluated.
> >>>>
> >>>>Could somebody help me out with this?
> >>>>
> >>>>-Nevada
> >>>>
> >>>>
> >>>
> >>
> >
> >
> >
>
>
>

Re: [casper] Compilation errors with FFT block

[Mark Wagner]

Hi Nevada,

Right click on block -> View Mask, go to initialization tab, and run the
same command except replacing the variables for what you are actually using
as parameters:

fft_init(gcb,'FFTsiz', 10, ...

also, make sure that that the current block you have selected is the fft, or
replace gcb with the fft's path.

Mark



On Fri, Mar 12, 2010 at 12:14 PM, Nevada Sanchez  wrote:

> The twiddle block does show up in the Casper library. I'm not entirely sure
> how to correctly run the mask script from the MATLAB command line, but I
> tried the following (my model is called 'sysgen_scratch').
>
> 
> >> fft_init(sysgen_scratch/fft)
> ??? Error due to multiple causes.
>
> Caused by:
> The LinkStatus can be set only for a linked block.
> Error in
> 'sysgen_scratch/fft/fft_biplex0/biplex_core/fft_stage_3/butterfly_direct/twiddle':
> Initialization commands cannot be evaluated.
> >>
> >> sysgen_scratch/fft
> ??? Error due to multiple causes.
>
> Caused by:
> The LinkStatus can be set only for a linked block.
> Error in
> 'sysgen_scratch/fft/fft_biplex0/biplex_core/fft_stage_3/butterfly_direct/twiddle':
> Initialization commands cannot be evaluated.
> 
>
> I suspect this isn't what you meant.
>
> -Nevada
>
> On Mar 12, 2010, at 14:59 PM, Mark Wagner wrote:
>
> Hi Nevada,
>
> Have you tried running the mask script from the matlab command line?  This
> may give some clues as to what the issue is.
>
> Also, does the twiddle block show up in your casper library?
>
> Mark
>
> On Fri, Mar 12, 2010 at 11:52 AM, Nevada Sanchez  wrote:
>
>> It seems that the problem with the bad links was caused by me not opening
>> the libraries on startup. I updated my startup.m script and everything is
>> fine, except that I still have to remove the link to the Casper library to
>> get the FFT block to compile.
>>
>> -Nevada
>>
>> On Mar 12, 2010, at 4:44 AM, John Ford wrote:
>>
>> >> Is it still necessary in 11.x/RHEL to load/open the CASPER library
>> >> before opening a model containing library blocks?
>> >
>> > Yes, Henry, it is.  We have a startup.m that opens/loads the user's
>> > libraries and starts sysgen.
>> >
>> > Here it is.
>> >
>> > Yes, Master<1005> more startup.m
>> >
>> addpath('/export/home/tokra/scratch/casper/mlib_devel_10_1/xps_library');
>> >
>> addpath('/export/home/tokra/scratch/casper/mlib_devel_10_1/casper_library');
>> >
>> addpath('/export/home/tokra/scratch/casper/mlib_devel_10_1/gavrt_library');
>> > sysgen_startup
>> > system_dependent('RemoteCWDPolicy','reload')
>> > system_dependent('RemotePathPolicy','reload')
>> > load_system('casper_library');
>> > load_system('gavrt_library');
>> > Yes, Master<1006>
>> >
>> > Then of course there are all the environment variable to set.  We also
>> > have a script for that:
>> >
>> > Yes, Master<1006> more Startsg.sh
>> > #!/bin/bash
>> > source /export/home/tokra/Xilinx/11.1/settings64.sh
>> > export MATLAB=/opt/matlab
>> > export XILINX=/export/home/tokra/Xilinx/11.1/ISE
>> > export XILINX_EDK=/export/home/tokra/Xilinx/11.1/EDK
>> > export PLATFORM=lin64
>> > export XILINX_DSP=/export/home/tokra/Xilinx/11.1/DSP_Tools/${PLATFORM}
>> > export
>> >
>> BEE2_XPS_LIB_PATH=/export/home/tokra/scratch/casper/mlib_devel_10_1/xps_l
>> > ib
>> > export MLIB_ROOT=/export/home/tokra/scratch/casper/mlib_devel_10_1
>> > export
>> PATH=${XILINX}/bin/${PLATFORM}:${XILINX_EDK}/bin/${PLATFORM}:${PATH}
>> > export
>> >
>> LD_LIBRARY_PATH=${XILINX}/bin/${PLATFORM}:${XILINX}/lib/${PLATFORM}:${XIL
>> > INX_DSP}/sysgen/lib:${LD_LIBRARY_PATH}
>> > export LMC_HOME=${XILINX}/smartmodel/${PLATFORM}/installed_lin
>> > export PATH=${LMC_HOME}/bin:${XILINX_DSP}/common/bin:${PATH}
>> > export INSTALLMLLOC=/opt/matlab
>> > export TEMP=/tmp/
>> > export TMP=/tmp/
>> > $MATLAB/bin/matlab
>> >
>> >
>> > John
>> >
>> >
>> >>
>> >> Thanks,
>> >> Henry
>> >>
>> >> On 3/11/2010 11:46 PM, Nevada Sanchez wrote:
>> >>> I've tried deleting and replacing (even creating an entirely new
>> model)
>> >>> with no luck. I managed to fix it be destr

Re: [casper] Compilation errors with FFT block

[Mark Wagner]

Hi Nevada,

Changing a mask parameter forces the mask script to be run and hence the
subsystems to be redrawn using the casper library you've loaded.  If the
parameters are not changed, the mask script will not redraw the subsystems.
 This saves time, but may mean that some of your block subsystems may
conflict with your newer updates to the library.

Mark


On Fri, Mar 12, 2010 at 12:58 PM, Nevada Sanchez  wrote:

> Strangely, that seemed to work. In fact, all it seems to take is for me to
> open up the mask parameters dialog and change something (pretty much
> anything, it seems).
>
> -Nevada
>
> On Mar 12, 2010, at 15:21 PM, Mark Wagner wrote:
>
> Hi Nevada,
>
> Right click on block -> View Mask, go to initialization tab, and run the
> same command except replacing the variables for what you are actually using
> as parameters:
>
> fft_init(gcb,'FFTsiz', 10, ...
>
> also, make sure that that the current block you have selected is the fft,
> or replace gcb with the fft's path.
>
> Mark
>
>
>
> On Fri, Mar 12, 2010 at 12:14 PM, Nevada Sanchez  wrote:
>
>> The twiddle block does show up in the Casper library. I'm not entirely
>> sure how to correctly run the mask script from the MATLAB command line, but
>> I tried the following (my model is called 'sysgen_scratch').
>>
>> 
>> >> fft_init(sysgen_scratch/fft)
>> ??? Error due to multiple causes.
>>
>> Caused by:
>> The LinkStatus can be set only for a linked block.
>> Error in
>> 'sysgen_scratch/fft/fft_biplex0/biplex_core/fft_stage_3/butterfly_direct/twiddle':
>> Initialization commands cannot be evaluated.
>> >>
>>  >> sysgen_scratch/fft
>> ??? Error due to multiple causes.
>>
>> Caused by:
>> The LinkStatus can be set only for a linked block.
>>     Error in
>> 'sysgen_scratch/fft/fft_biplex0/biplex_core/fft_stage_3/butterfly_direct/twiddle':
>> Initialization commands cannot be evaluated.
>> 
>>
>> I suspect this isn't what you meant.
>>
>> -Nevada
>>
>> On Mar 12, 2010, at 14:59 PM, Mark Wagner wrote:
>>
>> Hi Nevada,
>>
>> Have you tried running the mask script from the matlab command line?  This
>> may give some clues as to what the issue is.
>>
>> Also, does the twiddle block show up in your casper library?
>>
>> Mark
>>
>> On Fri, Mar 12, 2010 at 11:52 AM, Nevada Sanchez  wrote:
>>
>>> It seems that the problem with the bad links was caused by me not opening
>>> the libraries on startup. I updated my startup.m script and everything is
>>> fine, except that I still have to remove the link to the Casper library to
>>> get the FFT block to compile.
>>>
>>> -Nevada
>>>
>>> On Mar 12, 2010, at 4:44 AM, John Ford wrote:
>>>
>>> >> Is it still necessary in 11.x/RHEL to load/open the CASPER library
>>> >> before opening a model containing library blocks?
>>> >
>>> > Yes, Henry, it is.  We have a startup.m that opens/loads the user's
>>> > libraries and starts sysgen.
>>> >
>>> > Here it is.
>>> >
>>> > Yes, Master<1005> more startup.m
>>> >
>>> addpath('/export/home/tokra/scratch/casper/mlib_devel_10_1/xps_library');
>>> >
>>> addpath('/export/home/tokra/scratch/casper/mlib_devel_10_1/casper_library');
>>> >
>>> addpath('/export/home/tokra/scratch/casper/mlib_devel_10_1/gavrt_library');
>>> > sysgen_startup
>>> > system_dependent('RemoteCWDPolicy','reload')
>>> > system_dependent('RemotePathPolicy','reload')
>>> > load_system('casper_library');
>>> > load_system('gavrt_library');
>>> > Yes, Master<1006>
>>> >
>>> > Then of course there are all the environment variable to set.  We also
>>> > have a script for that:
>>> >
>>> > Yes, Master<1006> more Startsg.sh
>>> > #!/bin/bash
>>> > source /export/home/tokra/Xilinx/11.1/settings64.sh
>>> > export MATLAB=/opt/matlab
>>> > export XILINX=/export/home/tokra/Xilinx/11.1/ISE
>>> > export XILINX_EDK=/export/home/tokra/Xilinx/11.1/EDK
>>> > export PLATFORM=lin64
>>> > export XILINX_DSP=/export/home/tokra/Xilinx/11.1/DSP_Tools/${PLATFORM}
>>> > export
>>> >
>>> BEE2_XPS_LIB_PATH=

Re: [casper] Simulink/Xilinx integration

[Mark Wagner]

Hi Steve,

Try opening up the System Generator block and entering in 'd7' in the 'clock
pin location' field.  Then, make sure the highest level in your model file
is selected and open bee_xps, click 'gcb' and make sure it still corresponds
to your model file name, not a subsystem.  Then try running bee xps.

Also, are you using 'Use explicit sample period' of 1 in your slice block?
 If not, this might explain the error you're getting with the Slice and
Counter.

Mark

On Sun, Mar 14, 2010 at 3:02 PM, Steve Maher wrote:

> Hi Jason,
>
> Thanks for the reply.
>
> On Sun, Mar 14, 2010 at 12:10 PM, Jason Manley wrote:
>
>> Hi Steve
>>
>> Are you preloading the libraries?
>>
>
> I am now =)
>
> I get a zillion warnings in the console (mostly about parameterized links)
>  but I can now run XSG/XPS ... thanks.
>
>
>
> However, XSG fails when building the following tutorial (my version
> attached)
>
> http://casper.berkeley.edu/wiki/Roach_Tutorial
>
> I've included *testborph_sysgen_error.log* below, but the main error seems
> to be the following:
>
> All Xilinx Blocks must be contained in a level of hierarchy with a
> System Generator Token
>
>
> Obviously I do have a System Generator Token.  Googling for the error
> produced
> http://www.xilinx.com/support/answers/24845.htm, but it's not applicable.
>
>
> Hmmm...
>
> Steve
>
> p.s. If I try running XPS a second time, Matlab/Simulink crashes.
>
>
>
>
>
>
>
> - Version Log
> --
> Version Path
> System Generator 11.5.2275  C:/Xilinx/11.1/DSP_Tools/nt/sysgen
> AccelDSP 11.5.2275
>  C:/Xilinx/11.1/DSP_Tools/nt/AccelDSP
> Matlab 7.9.0.529 (R2009b)   C:/Program Files/MATLAB/R2009b
> ISE 11.4.i  C:/Xilinx/11.1/ISE
>
> 
> Summary of Errors:
> Error 0001: All Xilinx Blocks must be contained in a level of hierarc...
>  Block: Unspecified
> Error 0002: A summary of Sysgen errors has been written to C:/roachmo...
>  Block:
> Error 0003: A summary of Sysgen errors has been written to C:/roachmo...
>  Block:
> Error 0004: A summary of Sysgen errors has been written to C:/roachmo...
>  Block: 'testborph/Counter'
> Error 0005: A summary of Sysgen errors has been written to C:/roachmo...
>  Block: 'testborph/Slice'
>
> 
>
> Error 0001:
>
> Reported by:
>   Unspecified
>
> Details:
> All Xilinx Blocks must be contained in a level of hierarchy with a
> System Generator Token
>
> 
>
> Error 0001:
>
> Reported by:
>
> Details:
> A summary of Sysgen errors has been written to
> C:/roachmodels/testborph_sysgen_error.log
>
> 
>
> Error 0001:
>
> Reported by:
>
> Details:
> A summary of Sysgen errors has been written to
> C:/roachmodels/testborph_sysgen_error.log
>
> 
>
> Error 0001:
>
> Reported by:
>   'testborph/Counter'
>
> Details:
> A summary of Sysgen errors has been written to
> C:/roachmodels/testborph_sysgen_error.log
>
> 
>
> Error 0001:
>
> Reported by:
>   'testborph/Slice'
>
> Details:
> A summary of Sysgen errors has been written to
> C:/roachmodels/testborph_sysgen_error.log
>
> 
>
>

Re: [casper] XAUI license

[Mark Wagner]

Hi Sean,

I haven't seen this problem before, but I might try checking 'Use KAT open
XAUI PHY' in the parameters box or using the v2 10gbe yellow block.

Mark


On Sun, Mar 21, 2010 at 3:15 AM, Sean  wrote:

> Hi all,
>
> Last week I compiled a simple design to test the 10Gbe port for the ROACH;
> no problem.  However, I just tried compiling it again and an error occurred
> complaining that I didn't have the XAUI v.7 license.  I looked in
> C:\Xilinx\10.1\ISE\coregen\core_licenses and found the license.  It is
> "permanent" so I figure it's not expired, but to be sure I requested a new
> one.  I still get the same problem.  Now I don't think it's actually a
> license issue since I tried compiling it on a collaborators machine at a
> different institution (with a different lisence) and got the same error.
>
> Has anyone else experienced anything like this and found their way clear?
>  Advice is greatly appreciated.
>
> Thanks,
>
> Sean
>
>

Re: [casper] Block/Mask Initialization problem

[Mark Wagner]

Hi Ian,

The parameters that are being set in the mask script are not for the
delay_bram per se, but for the counter blocks underneath the delay_bram.
 The delay_bram's parameters would be set by a mask above it, or by hand.

Could you attach the error message you're getting so we can have a crack at
it?

Thanks,
Mark




On Thu, Apr 8, 2010 at 3:38 PM, O'Dwyer, Ian J (382G) <
ian.j.o'dw...@jpl.nasa.gov > wrote:

> Hi All,
>
> I am getting an error with a couple of blocks when trying to simulate a new
> design.  This is using version 10.1.  It seems like there is some problem
> with the initialization commands/mask.  For example in one block delay_bram
> there appear to be only 3 variables that are in the mask,   delay_len,
> bram_latency and use_dsp48.
>
> However, the mask initialization looks like this
>
> if (DelayLen <= bram_latency)
> error('delay value must be greater than BRAM Latency');
> end
> BitWidth = max(ceil(log2(DelayLen)), 2);
> if strcmp(use_dsp48,'on'),
> set_param([gcb,'/Counter'], 'use_behavioral_HDL', 'off', ...
> 'use_rpm', 'on', 'implementation', 'DSP48');
> else, %default counter settings
> set_param([gcb,'/Counter'], 'use_behavioral_HDL', 'off', ...
> 'use_rpm', 'off', 'implementation', 'Fabric');
> end
>
>
> I am not an expert on masks at all,  but it seems like it is trying to set
> values for variables (use_behavioral_hdl, implementation and use_rpm) that
> do not exist in delay_bram's mask and I think that's what the simulator is
> trying to tell me with its error message.  Does this look familiar to
> anyone
> at all?  Any suggestions?
>
> Many thanks
>
> Ian O'Dwyer
>
>
>

[casper] papers request

[Mark Wagner]

Hi All,

The CASPER wiki has a lack of CASPER related papers (particularly science)
and *we* would like to remedy that.  If you have something you'd like to
contribute, please email me the paper/presentation/thesis, or a link, and I
will post it for you.  If you have wiki access, you can post it yourself
here .

Thanks,
Mark

Re: [casper] 6 GS/s Spectrometer

[Mark Wagner]

Hi John,

I don't think anyone has been able to get a spectrometer working at the full
3GS/s interleaved yet.  The best Suraj and I have been able to do is about
2.4Gs/s before we start running into serious timing issues.  We do have
plans to meet soon with a Xilinx timing expert in the hopes of resolving our
issues.

Mark


On Thu, Apr 22, 2010 at 2:12 PM, John Ford  wrote:

> Hi all.
>
> Has anyone done a 6 GS/s spectrometer using 2 interleaved 3 GS/s ADC
> boards on a ROACH?  I seem to recall someone doing something of the sort,
> but I don't recall any details.
>
> Thanks for any info!
>
> John
>
>
>
>
>

Re: [casper] casper Digest, Vol 30, Issue 1

[Mark Wagner]

Hi Chao-Te,

To answer you question, the xps executable should be in the EDK directory.
 For instance, ours is located here:

/opt/Xilinx/11.1/EDK/bin/lin64/xps

I haven't directly used xps on windows, but I think it should be something
like this:

C:\Xilinx\10.1\EDK\bin\nt\xps.exe

>From the XPS_ROACH_base directory on linux I run the command:

$xps -nw system.xmp

Although, before you try to remove this error, I would check to see what the
utilization report looks like and if you actually have the resources to
build the design.  You can find this report in:

/XPS_ROACH_base/implementation/system_map.mrp

The example spectrometer was designed for the sx95t and may not fit on the
lx110t (which doesn't have very many dsp48's).

Mark



On Sun, May 2, 2010 at 9:12 PM, Chao-Te Li  wrote:

> Hi,
>
> I was compiling the wideband spectrometer from the 2009 tutorials.
> http://casper.berkeley.edu/wiki/Tutorials
>
> It was compilted well with ROACH:sx95t. but when I chose
> ROACH:lx110t, I got the following error message and suggestion -
>
>
> xilperl D:/Xilinx/EDK/data/fpga_impl/observe_par.pl -error yes
> implementation/system.par
> Analyzing implementation/system.par
>
> *
> ***
> ERROR: 1 constraint not met.
>
> PAR could not meet all timing constraints. A bitstream will not be
> generated.
>
> To disable the PAR timing check:
>
> 1> Disable the "Treat timing closure failure as error" option from the
> Project Options dialog in XPS.
>
> OR
>
> 2> Type following at the XPS prompt:
> XPS% xset enable_par_timing_error 0
>
>
> 
>
>
> How do I do to bring up the XPS or its prompt?
> Thanks.
>
>
> --
> Open WebMail Project (http://openwebmail.org)
>
>
> -- Original Message ---
> From: casper-requ...@lists.berkeley.edu
> To: casper@lists.berkeley.edu
> Sent: Sat, 01 May 2010 12:55:16 -0700
> Subject: casper Digest, Vol 30, Issue 1
>
> > Send casper mailing list submissions to
> >   casper@lists.berkeley.edu
> >
> > To subscribe or unsubscribe via the World Wide Web, visit
> >
>
> https://calmail.berkeley.edu/manage/list/listinfo/cas...@lists.berkel
> ey.edu
> >
> > or, via email, send a message with subject or body 'help' to
> >   casper-requ...@lists.berkeley.edu
> >
> > You can reach the person managing the list at
> >   casper-ow...@lists.berkeley.edu
> >
> > When replying, please edit your Subject line so it is more specific
> > than "Re: Contents of casper digest..."
> >
> > Today's Topics:
> >
> >1. Re: 'The Great Debate: Are We Alone?' (Tonight) (dana whitlow)
> >
> > --
> >
> > Message: 1
> > Date: Fri, 30 Apr 2010 17:15:22 -0400
> > From: dana whitlow 
> > Subject: Re: [casper] 'The Great Debate: Are We Alone?' (Tonight)
> > To: melvyn wright 
> > Cc: casper@lists.berkeley.edu
> > Message-ID: <4bdb486a.2040...@naic.edu>
> > Content-Type: text/plain; charset=ISO-8859-1; format=flowed
> >
> > Good idea- we'll just hook that right up.  Let's see now- should it
> > be 430 MHz or 2380 MHz?
> >
> > Dana
> >
> > melvyn wright wrote:
> > > On Fri, Apr 30, 2010 at 12:13 PM, David Hawkins 
> wrote:
> > >
> > >>> will the debate be recorded, and available later for humans or for
> LGMs ?
> > >>>
> > >> Shouldn't we be blasting it out into space for the LGMs
> > >> to listen to live?
> > >>
> > >> :)
> > >>
> > >
> > > not according to
> > > http://www.csmonitor.com/USA/Politics/DC-Decoder/2010/0430/Stephen-
> Hawking-alien-warning-Could-we-talk-to-them
> > >
> > > :-(
> > >
> > > M.
> > >
> > >
> > >
> > >
> >
> > End of casper Digest, Vol 30, Issue 1
> > *
> --- End of Original Message ---
>
>
>

Re: [casper] casper Digest, Vol 30, Issue 1

[Mark Wagner]

Hi Chao-Te,

The 100% utilization of DSP48's seems to be your problem.  I would try using
slices instead.
In the fft and pfb paramater box, you can do this by checking 'specify
multiplier use' and then entering in a vector that specifies the multipliers
you want to use. I think you want 'behavioral,' so if you have a 2^7 fft,
you would enter in: [2 2 2 2 2 2 2].

Mark

On Sun, May 2, 2010 at 10:12 PM, Chao-Te Li  wrote:

> Hi Mark,
>
> Thanks for the help.
> I copy the utility summary from MATLAB as follows -
>
> Device Utilization Summary:
>
>   Number of BUFGs   3 out of 32  9%
>   Number of DCM_ADVs1 out of 12  8%
>   Number of DSP48Es64 out of 64100%
>   Number of ILOGICs65 out of 800 8%
>   Number of External IOBs  97 out of 64015%
>  Number of LOCed IOBs  97 out of 97100%
>
>   Number of External IOBMs  1 out of 320 1%
>  Number of LOCed IOBMs  1 out of 1 100%
>
>   Number of External IOBSs  1 out of 320 1%
>  Number of LOCed IOBSs  1 out of 1 100%
>
>   Number of OLOGICs 5 out of 800 1%
>   Number of RAMB18X2s  50 out of 14833%
>   Number of RAMB36_EXPs14 out of 148 9%
>   Number of Slice Registers 21382 out of 69120  30%
>  Number used as Flip Flops  21382
>  Number used as Latches 0
>  Number used as LatchThrus  0
>
>   Number of Slice LUTS  21127 out of 69120  30%
>   Number of Slice LUT-Flip Flop pairs   27717 out of 69120  40%
>
> --
>
> The model does use up all the DSP48Es (and some other devices).
> But they are at most 100%. So it's ok in terms of resources?
>
> Regards,
> Chao-Te
>
>
> --
> Open WebMail Project (http://openwebmail.org)
>
>
> -- Original Message ---
> From: Mark Wagner 
> To: Chao-Te Li 
> Cc: casper@lists.berkeley.edu
> Sent: Sun, 2 May 2010 21:48:48 -0700
> Subject: Re: [casper] casper Digest, Vol 30, Issue 1
>
> > Hi Chao-Te,
> >
> > To answer you question, the xps executable should be in the EDK
> directory.
> >  For instance, ours is located here:
> >
> > /opt/Xilinx/11.1/EDK/bin/lin64/xps
> >
> > I haven't directly used xps on windows, but I think it should be
> something
> > like this:
> >
> > C:\Xilinx\10.1\EDK\bin\nt\xps.exe
> >
> > >From the XPS_ROACH_base directory on linux I run the command:
> >
> > $xps -nw system.xmp
> >
> > Although, before you try to remove this error, I would check to see
> > what the utilization report looks like and if you actually have the
> > resources to build the design.  You can find this report in:
> >
> > /XPS_ROACH_base/implementation/system_map.mrp
> >
> > The example spectrometer was designed for the sx95t and may not fit
> > on the lx110t (which doesn't have very many dsp48's).
> >
> > Mark
> >
> > On Sun, May 2, 2010 at 9:12 PM, Chao-Te Li
> >  wrote:
> >
> > > Hi,
> > >
> > > I was compiling the wideband spectrometer from the 2009 tutorials.
> > > http://casper.berkeley.edu/wiki/Tutorials
> > >
> > > It was compilted well with ROACH:sx95t. but when I chose
> > > ROACH:lx110t, I got the following error message and suggestion -
> > >
> > >
> > > xilperl D:/Xilinx/EDK/data/fpga_impl/observe_par.pl -error yes
> > > implementation/system.par
> > > Analyzing implementation/system.par
> > >
> > >
>
> *
> > > ***
> > > ERROR: 1 constraint not met.
> > >
> > > PAR could not meet all timing constraints. A bitstream will not be
> > > generated.
> > >
> > > To disable the PAR timing check:
> > >
> > > 1> Disable the "Treat timing closure failure as error" option from the
> > > Project Options dialog in XPS.
> > >
> > > OR
> > >
> > > 2> Type following at the XPS prompt:
> > > XPS% xset enable_par_timing_error 0
> > >
> > >
> > > 
> > >
> > >
> > > How do I do to bring up the XPS or its prompt?
> > > Thanks.

Re: [casper] casper Digest, Vol 30, Issue 1

[Mark Wagner]

Hi Chao-Te,

Can you try replacing the fft and the pfb_fir blocks, making sure to set the
parameters the same?  Then try rerunning it.  Sometimes this resolves the
problem.  If you get the same error, try running the initialization scripts
by hand.  You can see how the script is called by right clicking on the
block -> view mask, then go to the 'initialization' tab.  From the matlab
prompt, just enter in the call, replacing the variables with the actual
values (ex. fft_init(gcb,'FFTSize',12,...etc.) ).  This should give you more
verbose output.

Mark


On Mon, May 3, 2010 at 4:17 AM, Chao-Te Li  wrote:

> Hi Mark,
>
> I got some errors as follows when I tried to specify the parameters
> for fft or pfb (although I have updated the ISE 10.1 to SP3) -
>
>
> #
> ##  System Update  ##
> #
> Error using ==> set_param
> Error in 'r_spec_2048_r103/pfb_fir_real': Initialization commands cannot be
> evaluated.  MATLAB error message: Error using ==> set_param
> Error in 'r_spec_2048_r103/pfb_fir_real/pol1_in1_last_tap': Initialization
> commands cannot be evaluated.  MATLAB error message: Error using ==>
> get_param
> Invalid Simulink object name:
> r_spec_2048_r103/pfb_fir_real/pol1_in1_last_tap/pfb_real_add_tree.
> #
> ##  System Update  ##
> #
> Error using ==> set_param
> Error in 'r_spec_2048_r103/pfb_fir_real': Initialization commands cannot be
> evaluated.  MATLAB error message: Error using ==> set_param
> Error in 'r_spec_2048_r103/pfb_fir_real/pol1_in1_last_tap': Initialization
> commands cannot be evaluated.  MATLAB error message: Error using ==>
> get_param
> Invalid Simulink object name:
> r_spec_2048_r103/pfb_fir_real/pol1_in1_last_tap/pfb_real_add_tree.
> Warning: Block diagram 'r_spec_2048_r103' contains one or more
> parameterized
> library links.  To find the
> parameterized links use the Model Advisor.  The diagram has been saved but
> may not behave as you intended.
> Warning: Block diagram 'r_spec_2048_r103' contains one or more disabled
> library links.  To find the disabled
> links use the Model Advisor.  The diagram has been saved but may not
> contain
> what you intended.
>
>
> ----
>
> any suggestion?
>
> Chao-Te
>
> --
> Open WebMail Project (http://openwebmail.org)
>
>
> -- Original Message ---
> From: Mark Wagner 
> To: Chao-Te Li 
> Cc: casper@lists.berkeley.edu
> Sent: Sun, 2 May 2010 22:59:34 -0700
> Subject: Re: [casper] casper Digest, Vol 30, Issue 1
>
> > Hi Chao-Te,
> >
> > The 100% utilization of DSP48's seems to be your problem.  I would
> > try using slices instead. In the fft and pfb paramater box, you can
> > do this by checking 'specify multiplier use' and then entering in a
> > vector that specifies the multipliers you want to use. I think you
> > want 'behavioral,' so if you have a 2^7 fft, you would enter in: [2
> > 2 2 2 2 2 2].
> >
> > Mark
> >
> > On Sun, May 2, 2010 at 10:12 PM, Chao-Te Li  > that unless you dig deep into the design, you're nota.edu.tw> wrote:
> >
> > > Hi Mark,
> > >
> > > Thanks for the help.
> > > I copy the utility summary from MATLAB as follows -
> > >
> > > Device Utilization Summary:
> > >
> > >   Number of BUFGs   3 out of 32  9%
> > >   Number of DCM_ADVs1 out of 12  8%
> > >   Number of DSP48Es64 out of 64100%
> > >   Number of ILOGICs65 out of 800 8%
> > >   Number of External IOBs  97 out of 64015%
> > >  Number of LOCed IOBs  97 out of 97100%
> > >
> > >   Number of External IOBMs  1 out of 320 1%
> > >  Number of LOCed IOBMs  1 out of 1 100%
> > >
> > >   Number of External IOBSs  1 out of 320 1%
> > >  Number of LOCed IOBSs  1 out of 1 100%
> > >
> > >   Number of OLOGICs 5 out of 800 1%
> > >   Number of RAMB18X2s  50 out of 14833%
> > >   Number of RAMB36_EXPs14 out of 148 9%
> > >   Number of Slice Registers 21382 out of 69120  30%
> > >  Number used as Flip Flops  21382
> > >

[casper] FYI: corrupted model file issue

[Mark Wagner]

FWIW, I recently encountered an issue where Matlab/Simulink crashed on me
and when I restarted my session and tried to re-open the model file I had
been working on, Matlab gave a Segmentation Violation.

I'm not sure if anyone else has encountered this, but the problem has
something to do with blocks that are interdependent on the CASPER DSP
(casper_library.mdl) and BEE_XPS System (xps_library.mdl) block sets, the
snap block in my case.  If I didn't load the BEE_XPS System blockset, then
started Matlab, I could open my file with links broken.  I was able to
file->open xps_library.mdl and have my design get drawn.  I needed to delete
the offending interdependent blocks and replace them with ones from the
library.  I could then save my design and close/open it and continue my
project.

Xilinx support has been helpful, and have been able to reproduce this
problem with my corrupted model file, but are not sure why this would happen
in the first place.  Either way, the above fix seems to work.

Mark

[casper] casper rss feed

[Mark Wagner]

For those of you that use an RSS news reader, I added a CASPER feed to our
website.  You can subscribe to it by clicking on the icon in your address
bar, or by entering the address http://casper.berkeley.edu/rssfeed.xml into
your preferred reader.

Also, NO ONE responded last time I made this request, but if you have any
CASPER related papers or information that you would like disseminated,
please let me know.  Many of you are doing world class research and it would
be great if we could put this up on our website.

Thanks,
Mark

Re: [casper] config issue with window() function?

[Mark Wagner]

Hi Steve,

I'm not sure if you've done this already, but the first thing I would do
would be to replace the block with a new one from the library.  If this
doesn't work, I would run the mask script from the matlab command prompt,
which, if it doesn't fix the problem, will give you a more verbose error.

Mark

On Mon, May 10, 2010 at 2:34 PM, Steve Maher wrote:

> Hi all,
>
> I am having an (basic configuration?) issue with *pfb_coeff_gen *and the *
> window()* function.
>
> I get the following error when compiling a pfb_coeff_gen block:
>
> Error in 'testHamming/pfb_coeff_gen/ROM1': Parameter 'pfb_coeff_gen_calc(6,
>> 4,'hamming',0, 0,1,1)' cannot be evaluated.  MATLAB error message: Undefined
>> function or method 'window' for input arguments of type 'char'.
>
>
> I seem to have the Signal Processing Library installed correctly as the
> test *window('hamming', 1024)* passes at line 62 of pfb_coeff_gen_init.m.
>
> Tips appreciated.
>
> Steve
>

Re: [casper] 64-bit toolflow computer?

[Mark Wagner]

Hi Bay,

We had to move to RHEL5 (64-bit ok) to get versions above 11.3 working.
 I've heard that CentOS works too.

Mark


On Thu, May 20, 2010 at 3:49 PM, Bay E. Grabowski wrote:

> We're setting up a new toolflow computer after Ubuntu stopped working.
> Should we be installing RHEL 64-bit install or 32-bit? The wiki mentions
> 64-bit in passing, but I remember there being some problems with 64-bit
> earlier...
>
> --
> Bay Grabowski
> b...@umail.ucsb.edu
>
>
>

Re: [casper] 64-bit toolflow computer?

[Mark Wagner]

Hi Andrew,

I did try Fedora 12, which didn't work either.  I really wasn't happy with
RHEL5 for the same reason you mention, but it was the only OS I was able to
get to work with the newest tools.  It also meant Xilinx would answer our
questions, or at least attempt to.

Mark



On Thu, May 20, 2010 at 6:39 PM, Andrew Lutomirski  wrote:

> On Thu, May 20, 2010 at 9:34 PM, John Ford  wrote:
> >> Hi Bay,
> >>
> >> We had to move to RHEL5 (64-bit ok) to get versions above 11.3 working.
> >>  I've heard that CentOS works too.
> >
> > And you really need 64 bit...
>
> We're in the process of setting up a Fedora 13 system, since it's
> annoying to have packages as old as RHEL's.  Has anyone had any
> trouble with that?
>
> (There's also RHEL6 Beta, but I haven't gotten that to install without
> crashing, so I don't think it's quite ready for prime time.)
>
> --Andy
>
> >
> > John
> >
> >
> >>
> >> Mark
> >>
> >>
> >> On Thu, May 20, 2010 at 3:49 PM, Bay E. Grabowski
> >> wrote:
> >>
> >>> We're setting up a new toolflow computer after Ubuntu stopped working.
> >>> Should we be installing RHEL 64-bit install or 32-bit? The wiki
> mentions
> >>> 64-bit in passing, but I remember there being some problems with 64-bit
> >>> earlier...
> >>>
> >>> --
> >>> Bay Grabowski
> >>> b...@umail.ucsb.edu
> >>>
> >>>
> >>>
> >>
> >
> >
> >
> >
>

[casper] There Will Be Branches

[Mark Wagner]

Casperians,

The global distribution of our collaboration has exposed limitations in the
centralized nature of our version control system (i.e. Subversion).  Our
proposed solution is to migrate the CASPER version control system from
Subversion to Git (http://git-scm.com).  Git is a "free & open source,
distributed version control system."

Moving to Git will make branching, merging, and having mirrors easier.  The
next step is to migrate our existing Subversion repository.  We've been
discussing this, would like to suggest some changes, and ask for your input.

Acronym definitions:

a. DNM - Do Not Migrate.  Leave in a read-only svn repository that will
eventually cease being relevant/interesting.

b. DVW - Distribute Via Wiki.  There seem to be quite a few binaries in the
repository and these may be better served through the wiki.

Proposed Repository Changes:

1. branches/  - DNM

2. tags/  - DNM

3. trunk/astro_library/ - DNM (superseded by casper_library?)

4. trunk/caltech/ - Migrate to "caltech" library or absorb into
mlib_devel_10_1 before migration?

5. trunk/mlib_devel_10_1/ - Migrate to "mlib_devel" repo.  For the
gavrt_library externals: see trunk/caltech/

6. trunk/mlib_devel_7_1/ - DNM

7. trunk/mlib_devel_8_2/ - DNM

8. trunk/mlib_devel_9_2/ - DNM

9. trunk/newfft_library/ - DNM

10. trunk/projects/* - Migrate each project to its own repo.  Make a bundled
"casper_projects" repo that uses Git submodules to include all (most?,
some?, any?) of these individual repos?

11. trunk/ref_designs_tutorials/workshop_2009/ - DNM

12. trunk/ref_designs_tutorials/workshop_2010/ - Migrate to
"casper_workshop" repo.

13. trunk/roach/demos/ - DNM?  Already in casper_workshop?  Migrate to
"roach_demos" repo?

14. trunk/roach/gw/binaries/ - DNM, DVW.

15. trunk/roach/production/roach2_run1/ - What is this and how is it used?

16. trunk/roach/production/test_software/ - Move to "roach_test_sw" repo?

17. trunk/roach/sw/ - Much of this is DNM, DVW.  Migrate to other repos that
link back to original repo (e,g, linux, u-boot, busybox)? migrate to
"roach_dev_sw" repo?  Build a bundled repo with all roach related software
development?

18. trunk/udp_framework/ - DNM (superseded by KATCP?)

Thanks,
Mark, Dave

Re: [casper] GCC error

[Mark Wagner]

Hi Matt,

Did you manage to fix your problem? This design simulates just fine for me
too under 11.4 and 12.1, but we don't have a 11.5 install.

What version of gcc are you using?  Have you tried contacting xilinx
support?

Mark

On Wed, Jun 2, 2010 at 3:42 PM, John Ford  wrote:

> > Hi John,
> >
> > The .mdl file is attached.
>
> Hi Matthew.
>
> This simulated fine for me on my 11.3 system, modulo the warnings about
> being created on a newer version...
>
> Of course, bee_xps complains bitterly about the lack of the MSSGE block if
> you try to build it.
>
> John
>
>
> >
> > Matthew
> >
> >
> >
> >>> Hi All,
> >>>
> >>> We're trying to get the version 11 tools running on RHEL5, and we've
> >>> run
> >>> into a problem.  When we try to simulate designs involving Xilinx
> >>> blocks
> >>> (without any Casper blocks), we get the following error:
> >>>
> >>> "Program "gcc" returned non-zero status (1).
> >>>
> >>> Error occurred during "Simulation Initialization"."
> >>
> >> Can you send the .mdl file?
> >>
> >> John
> >>
> >>
> >>>
> >>> The design consisted of a System Generator block, and a Xilinx sampled
> >>> constant sent through a gateway to a scope.  The error occurred for the
> >>> sampled constant.
> >>>
> >>> We're running:
> >>> RHEL 5.1.19.6
> >>> Matlab 2009b
> >>> Xilinx ISE 11.5
> >>>
> >>>
> >>> Has anybody ran into this issue?  Any suggestions?
> >>>
> >>> Thanks,
> >>> Matthew
> >>> __
> >>> Matthew Stevenson
> >>> Graduate Student of Astrophysics
> >>>
> >>> Ph: (626) 395-4095
> >>> Fax: (626) 568-9352
> >>> E-mail: m...@astro.caltech.edu
> >>>
> >>>
> >>>
> >>>
> >>>
> >>>
> >>>
> >>
> >>
> >
>
>
>
>

Re: [casper] Green FFT fixed

[Mark Wagner]

One could also use the complex() function to avoid ambiguity.

Mark


On Thu, Jun 17, 2010 at 11:06 AM, Jonathan Landon <
silicondiode2...@yahoo.com> wrote:

> Recent versions of Matlab encourage use of a modified variable name for
> sqrt(-1) -- i.e., 1i and 1j instead of i and j.  Using i,j as loop variables
> is fine as long as complex numbers everywhere else are 1i or 1j.  Users
> familiar with Matlab have learned never to use i,j as loop variables since
> it overwrites sqrt(-1).  I'm not sure that older versions of Matlab support
> the use of 1i/1j, so I think I'm with Jason in suggesting the use of loop
> variables with names other than i,j.
>
> Jonathan
>
>
>

[casper] New casper-scm mailing list

[Mark Wagner]

CASPER now has a 'casper-scm' mailing list.  We've decided to move all
Software Configuration Management (SCM) discussion over to this new
list and away from the general 'casper' mailing list.

 If you are involved with CASPER software and library development, please
sign up at lists.berkeley.edu.

Thanks,
Mark

Re: [casper] Multi-Clock domain design using CASPER

[Mark Wagner]

Hi Kauchal,

I think reading
this
thread
from our email archive may be helpful.

Basically, make sure no subsystems are open and/or selected when
running bee_xps, just the top level model file.  As well, try entering
some value like 'd7' into the clock pin location in the System Generator
parameter field.

Mark



On Sun, Jul 11, 2010 at 11:37 PM, Kaushal Buch wrote:

> Hi,
>
> I have developed a digital noise source which provides 4 outputs to
> provide stimulus to the CASPER based POCO design. The noise source is
> clocked at 4 times the system clock (so that the four outputs emulate
> the data from an iADC board). Hence, I have two subsystems in the
> Sysgen design - one containing noise source block and the other
> containing the CASPER based correlator design. Both these subsystems
> are connected using the multiple subsystem generator token at the top
> level, as recommended by Xilinx.
>
> 1. The design gives expected results in simulation mode.
>
> 2. However, when I try to run bee_xps command for compiling this
> design, it gives the following error:
>
>
> --
> Error using ==> gen_xps_files at 91
> XPS_xsg block must be on the same level as the Xilinx SysGen block.
> (Have you put a XSG block in you design, and is the current system the
> correct one ?)
>
> --
>
> 3. I tried putting the MSSGE (XSG Core Config) token on the top level
> along with the multiple subsystem generator token, but it still gives
> error.
>
> How to design multi-clock domain system using CASPER blocks ?
>
> Looking forward to some suggestions / help in sorting out this problem.
>
>
> Thanks & Regards,
>
> Kaushal Buch
>
> GMRT, India.
>
>

Re: [casper] Setting up CASPER toolflow from scratch -- Windows/Linux, and version numbers

[Mark Wagner]

Hi Mandana,

1. I think that the required licenses are on the "MSSGE toolflow setup,"
they're just a little farther down
the page and not as obvious:

http://casper.berkeley.edu/wiki/MSSGE_Toolflow_Setup#Licenses

People have had this issue in the past, i'm just not sure of a better place
to put them.

2. Getting the python stuff setup on RHEL5 IS a headache.  I would prefer
Ubuntu
as well,  but unfortunately Xilinx doesn't support that.

Mark


On Thu, Jul 15, 2010 at 11:07 AM, Mandana Amiri  wrote:

> Hi,
>
> I recently went through the toolflow setup with RHEL5/Matlab_2008b/Xilinx
> 11.5/mlib10_1 from svn as advised by this list in late May.
> ( http://www.mail-archive.com/casper@lists.berkeley.edu/msg01530.html )
>
> The setup went smoothly and I was able to simulate/run tut1 and iADC
> tutorial so far. I ran into couple of glitches:
>
> 1. It took me a while to realize that I need Matlab "Signal Processing
> Blockset" (different than toolbox)  license. This was not part of our
> presumably fully licensed Matlab. So it may worth adding the list of Matlab
> toolboxes to the "toolflow setup" wiki page.
>
> 2. I found setting up Python2.6 under RHEL5 quite frustrating. (RHEL5 only
> supports Python 2.4). I had to rebuild numpy and scipy from source which
> required installing many packages (python-devel, gtk++-devel, pygobject,
> pygtk, etc.) and I ran into incompatibility issues when getting those
> packages from RHEL5. In this regard, I would have much preferred to deal
> with Ubuntu than RHEL5.
>
> Regards,
> Mandana Amiri
>
>
> Jonathan Landon wrote:
>
>> In March there was some discussion about setting up the CASPER tools on
>> Windows vs. Linux, and at the time the answer seemed to be that Linux is the
>> way of the future but it hadn't been well-tested, so a new user should set
>> up the 10.1 tools on Windows.  Since then, the 11.x tools have had plenty of
>> testing, so the official CASPER wisdom is for users starting from scratch to
>> use the Xilinx 11.4 tools on RHEL5 with Matlab 2009b and mlib_devel_10_1
>> from the git repository -- is that right?
>> The related CASPER wiki pages were last updated 12 February 2010 (
>> http://casper.berkeley.edu/wiki/Linux_xps), (
>> http://casper.berkeley.edu/wiki/Xilinx_ISE_11.4_Setup) and there was
>> additional discussion March 2010 on this list (included below), so I just
>> want to make sure I have the latest info in case anything changed since
>> then.
>>
>> Thanks,
>> Jonathan Landon
>>
>>
>> [casper] Simulink/Xilinx integration
>>
>> Andrew Martens
>> Tue, 16 Mar 2010 06:43:51 -0700
>>
>> -- Forwarded message --
>> From: Andrew Martens 
>> Date: 16 March 2010 14:51
>> Subject: Re: [casper] Simulink/Xilinx integration
>> To: Steve Maher 
>>
>>
>> Hi Steve
>>
>> As Jason has mentioned, going with Linux is choosing the path less
>> traveled within the CASPER group. We are moving that way for various reasons
>> but are not there yet. If you are looking for an easy route into the tools,
>> Windows-XP combined with Matlab2007b and the Xilinx 10.x tools are the way
>> to go. (http://casper.berkeley.edu/wiki/MSSGE_Toolflow_Setup)
>>
>> If you need to go the Linux route, tread lightly. Firstly ensure that you
>> can get as close to the official Xilinx supported configuration as possible
>> (http://www.xilinx.com/ise/ossupport/index.htm). Red Hat and SUSE
>> enterprise Linux are officially supported. Centos is a freely available
>> Linux version
>> based on Red Hat source. Note that an email was sent out a few weeks ago
>> with a configuration that CASPER people at UC Berkeley have tried and
>> recommend (
>> http://www.mail-archive.com/casper@lists.berkeley.edu/msg01228.html).
>> http://casper.berkeley.edu/wiki/Xilinx_ISE_11.4_Setup gives a setup using
>> Centos 5. I have set up (independently and using slightly different steps)
>> using Centos 5 and have successfully compiled a small design.
>>
>> Please note that at the moment Xilinx does not officially support System
>> Generator on any 64-bit version of Windows. For large devices (e.g to be on
>> ROACH2) a 64 bit operating system will be crucial (
>> http://www.xilinx.com/ise/products/memory.htm).
>>
>> Regards
>> Andrew
>>
>>
>> On 16 March 2010 14:01, Steve Maher  wrote:
>>
>> On Mon, Mar 15, 2010 at 12:38 PM, Jason Manley > >wrote:
>> Actually, the most stable flow right now (at least I've found) is Windows
>> XP 32-bit with 10.1.3.1386 and Matlab R2007b. This is what I would
>> recommend.
>>
>> Well, since I have to wait to get the license for R2007b from Matlab
>> (since it requires different types of keys than current releases) AND I'm
>> losing our only Windows XP 32-bit machine at the end of this week (it's
>> moving to a telescope in Spain), I'm going to try things on Linux (Ubuntu).
>>  I think
>> I'll start with 11.x while I'm waiting for the license from Matlab.  If
>> that doesn't work I'll back down to 10.1.
>>
>> Simultaneously I guess I'll try to track down Windows XP 32 bi

Re: [casper] Multi-Clock domain design using CASPER

[Mark Wagner]

Hi Kaushal,

I haven't done this, but you should be able
to use upsample and downsample blocks
to run at different frequencies.

Mark


On Fri, Jul 16, 2010 at 4:48 AM, Kaushal Dipak Buch <
kdb...@gmrt.ncra.tifr.res.in> wrote:

> Hi Jack,
>
> The following is what I tried for implementing a multiple subsystem
> generator based sample module for understanding and later implementing the
> actual design
>
> 1. Generation of two subsystems and selection of Hybrid DCM-CE option using
> the Sysgen token. Synthesis results in a top level VHDL/Verilog file
> containing these two subsystems. According to Xilinx, these subsystems have
> to be seperated either by Shared RAM, From FIFO-To FIFO or shared
> register, which was implemented in this sample design. However, it is
> also mentioned in the Sysgen User Guide that this process only results
> in top level instance file in VHDL/ Verilog and respective netlists of
> FIFO/RAM and the actual design. One has to select the top level wrapper
> which stitches all these together and then follow the  normal ISE flow
> to generate the bit file. It instantiates the DCM. However, I have gone
> only upto generation of bit file and have not implemented this sample
> design
> on FPGA.
>
> 2. When I did the same thing for the noise source (Subsystem 1) and
> correlator blocks (Subsystem 2), and tried to run synthesis using bee_xps
> command, the tool flow terminated giving the error mentioned in the inital
> email. I believe the bee_xps flow does not seem to be compatible with this
> kind of multiple clock domain designs.(using Multiple Subysystem Generator
> token).(Can someone with knowledge of bee_xps flow clarify this ?)
>
> Thanks & Regards,
>
> Kaushal
>
> P.S. I am sorry for the earlier couple of duplicate emails from me on the
> same query, which were due to some email server problem at our end.
>
>
>
>
>
>
>
> On Fri, 16 Jul 2010, Jack Hickish wrote:
>
>  Regarding multirate support from the toolflow - the system generator token
>> seems to have various options for multirate implementation (the default of
>> which is clock enables).
>>
>> On reading the system generator help file, my take is that the "hybrid
>> DCM-CE" mode will instantiate a DCM that can drive up to three clock ports
>> at different rates on virtex 5.
>>
>> I'd be interested to know if anyone has ever actually used this option
>> (and
>> if it worked!).
>>
>>
>>
>> On Mon, Jul 12, 2010 at 10:34 AM, Jason Manley > >wrote:
>>
>>  AFAIK, the toolflow doesn't currently support multi-clock domains from
>>> within the Simulink environment. Simulink hides this from you by trying
>>> to
>>> run everything at the fastest rate and then using "enable" lines to blank
>>> the lower speed logic components.
>>>
>>> Perhaps you should consider constructing a block that allows for multiple
>>> simultaneous outputs by breaking your logic into parallel sections.
>>> Because
>>> most designs run around 200-250MHz, with your current scheme this'd mean
>>> trying to clock your section of gateware at 800MHz or even 1GHz. I don't
>>> think this'd work. So even if you did get multiple clock domains working,
>>> it'd only be useful for standalone testing at lower speeds (~50-100MHz)
>>> or a
>>> subset of designs where the FPGA runs very slowly (which wastes compute
>>> resources and most people don't do). I think a configurable noise
>>> generator
>>> that runs at the native rate of the design would be very useful for the
>>> greater CASPER community though. I would certainly compile it into all my
>>> F
>>> engines for online testing.
>>>
>>> Jason
>>>
>>>
>>> On 12 Jul 2010, at 11:19, Kaushal Buch wrote:
>>>
>>>  Hi Mark,
>>>
>>>>
>>>> I tried the options that you have suggested and also those given in
>>>> the email thread. However, it gives same error.
>>>>
>>>> I am attaching the snapshot of the design. In the subsystem where the
>>>> noise block is present, XSG Core Config token is not kept as no CASPER
>>>> blocks are being used. It seems that the error is due to the
>>>> unavailability of the XSG Core Config token in this subsystem or on
>>>> the top level.  I tried keeping the token in this subsystem, but that
>>>> also does not solve the problem.
>>>>
>>>> Thanks & Regards,
>>>>
>>>> Kaushal
>&g

Re: [casper] Simulink refuses to simulate/compile

[Mark Wagner]

Hi Jon,

Try opening up the System Generator token and entering 'd7' into the clock
pin location.

Mark

On Thu, Jul 29, 2010 at 10:27 AM, Jon Losh  wrote:

> This tutorial .mdl that I'm using doesn't have any subsystems. Deleting and
> replacing the token didn't work, nor did the old trick of copying the
> contents into a new .mdl.
>
>
> On Thu, Jul 29, 2010 at 1:18 PM, John Ford  wrote:
>
>> > So simulink keeps throwing the same error whenever I try to simulate or
>> > compile something: "All Xilinx blocks must be contained in the same
>> > hierarchy as a system generator block." Googling gives me solutions that
>> > don't apply to me; same for the casper archive. The truly mysterious
>> thing
>> > is that I went back to a design that I made for the roach tutorial 1,
>> > which
>> > I have not touched since, and even this now refuses to simulate or
>> > compile.
>> > Any hot ideas?
>>
>> Make sure all the subsystem windows are closed, and you have clicked in
>> the main window with the sysgen token.
>>
>> If that doesn't work, then delete the sysgen token and put it back.
>>
>> Otherwise, ???
>>
>> John
>>
>>
>> >
>>
>>
>>
>

Re: [casper] ADC block error

[Mark Wagner]

Suraj,

So from what I understand, anyone that wants to use the 3gsps adc, now needs
to add line

addpath('/mlib_devel/casper_library/simulink_drawing_fns')

to their startup.m script?

Mark


On Mon, Aug 9, 2010 at 2:43 PM,  wrote:

> Hi John,
>
> The 'reuse_line' function is located in
> casper_library/simulink_drawing_fns. MATLAB is missing it because the
> addpath function isn't recursive.
>
> -Suraj
>
> > Hi all.  We are trying to build models on 11.X for the roach, and they
> are
> > failing.  Here are the error messages:
> >
> > Yes, Master<752> cat /tmp/jmf.txt
> >
> > Undefined function or method 'reuse_line' for input arguments of type
> > 'char'.
> >
> > Error in 'test_jmf/adc083000x2/adc0_sim': Initialization commands cannot
> > be evaluated.
> >
> > Error due to multiple causes: --> Undefined function or method
> > 'reuse_line' for input arguments of type 'char'. --> Error in
> > 'test_jmf/adc083000x2/adc0_sim': Initialization commands cannot be
> > evaluated.
> >
> >
> > I've seen this error in the mail archives, but I don't see the
> solution...
> >
> > Thanks.
> >
> > John
> >
> >
> >
> >
>
>
>
>

Re: [casper] bee_xps fails when building tutorial 3 for Roach

[Mark Wagner]

Hi Mandana,

Thanks for trying this out.  I just looked at the design, and it appears I
didn't
update it with the newest fft and pfb.  I just now did this.  Can you

svn co
http://casper.berkeley.edu/svn/trunk/ref_designs_tutorials/workshop_2010/roach_tut3_wideband_spec/

and using the newest clone of mlib_dewel, try and compile the r105 model
file?
It just worked for me.

If you're still having issues, let me know.

Thanks,
Mark


On Mon, Aug 9, 2010 at 3:22 PM,  wrote:

> Hi,
>
> I am trying to build the wideband spectrometer mdl file for Roach and when
> I run bee_xps, it fails. Errors are listed below. I tried this with the
> latest mlib_devel10.1 from svn and also with mlib_devel cloned from git
> and they both fail the same way. (I can not locate 'ref_designs_tutorials'
> directory in git, but I assume the latest svn version is fine).
>
> I noticed that when I open the tut3 mdl file, there are broken links in
> the fft and pfb blocks, so I deleted these blocks and replaced them with
> new ones from the library. The PFB block has an additional parameter: Fold
> adders into DSPs and I leave it as checked!
>
> Any chance you have seen this error before? Please advise.
>
> Thanks
> Mandana
> ps I can successfully build tutorial 1 and iADC tutorial
> pss For Tutorial 3, if I just go to system Generator block and press
> generate, it finishes with comiled successfully. However, bee_xps fails
>
> - Version Log -
> Version Path
> System Generator 11.5.2275   /opt/Xilinx/11.1/DSP_Tools/lin64/sysgen
> AccelDSP 11.5.2275   /opt/Xilinx/11.1/DSP_Tools/lin64/AccelDSP
> Matlab 7.7.0.471 (R2008b)/usr/local/matlab_2008b
> ISE 11.5.i   /opt/Xilinx/11.1/ISE
>
> and in xflow.log I have:
> 
>
> ERROR:NgdBuild:604 - logical block
>
> 'r_spec_2048_r105_XSG_core_config/r_spec_2048_r105_XSG_core_config/r_spec_204
>
> 8_r105_x0/fft_wideband_real_b9aab9e8c9/fft_unscrambler_d7ee91cd7f/reorder_71b
>   a0a1129/map9/comp5.core_instance5/BU2' with type
>   'dmg_43_c2a1bee36c7e7174_dist_mem_gen_v4_3_xst_1' could not be resolved.
> A
>   pin name misspelling can cause this, a missing edif or ngc file, or the
>   misspelling of a type name. Symbol
>   'dmg_43_c2a1bee36c7e7174_dist_mem_gen_v4_3_xst_1' is not supported in
> target
>   'virtex5'.
> ERROR:NgdBuild:604 - logical block
>
> 'r_spec_2048_r105_XSG_core_config/r_spec_2048_r105_XSG_core_config/r_spec_204
>
> 8_r105_x0/fft_wideband_real_b9aab9e8c9/fft_unscrambler_d7ee91cd7f/reorder_71b
>   a0a1129/map8/comp5.core_instance5/BU2' with type
>   'dmg_43_c2a1bee36c7e7174_dist_mem_gen_v4_3_xst_1' could not be resolved.
> A
>   pin name misspelling can cause this, a missing edif or ngc file, or the
>   misspelling of a type name. Symbol
>   'dmg_43_c2a1bee36c7e7174_dist_mem_gen_v4_3_xst_1' is not supported in
> target
>   'virtex5'.
> ERROR:NgdBuild:604 - logical block
>
> 'r_spec_2048_r105_XSG_core_config/r_spec_2048_r105_XSG_core_config/r_spec_204
>
> 8_r105_x0/fft_wideband_real_b9aab9e8c9/fft_unscrambler_d7ee91cd7f/reorder_71b
>   a0a1129/map7/comp5.core_instance5/BU2' with type
>   'dmg_43_c2a1bee36c7e7174_dist_mem_gen_v4_3_xst_1' could not be resolved.
> A
>   pin name misspelling can cause this, a missing edif or ngc file, or the
>   misspelling of a type name. Symbol
>   'dmg_43_c2a1bee36c7e7174_dist_mem_gen_v4_3_xst_1' is not supported in
> target
>   'virtex5'.
> ERROR:NgdBuild:604 - logical block
>
> 'r_spec_2048_r105_XSG_core_config/r_spec_2048_r105_XSG_core_config/r_spec_204
>
> 8_r105_x0/fft_wideband_real_b9aab9e8c9/fft_unscrambler_d7ee91cd7f/reorder_71b
>   a0a1129/map6/comp5.core_instance5/BU2' with type
>   'dmg_43_c2a1bee36c7e7174_dist_mem_gen_v4_3_xst_1' could not be resolved.
> A
>   pin name misspelling can cause this, a missing edif or ngc file, or the
>   misspelling of a type name. Symbol
>   'dmg_43_c2a1bee36c7e7174_dist_mem_gen_v4_3_xst_1' is not supported in
> target
>   'virtex5'.
> ERROR:NgdBuild:604 - logical block
>
> 'r_spec_2048_r105_XSG_core_config/r_spec_2048_r105_XSG_core_config/r_spec_204
>
> 8_r105_x0/fft_wideband_real_b9aab9e8c9/fft_unscrambler_d7ee91cd7f/reorder_71b
>   a0a1129/map5/comp5.core_instance5/BU2' with type
>   'dmg_43_c2a1bee36c7e7174_dist_mem_gen_v4_3_xst_1' could not be resolved.
> A
>   pin name misspelling can cause this, a missing edif or ngc file, or the
>   misspelling of a type name. Symbol
>   'dmg_43_c2a1bee36c7e7174_dist_mem_gen_v4_3_xst_1' is not supported in
> target
>   'virtex5'.
> ERROR:NgdBuild:604 - logical block
>
> 'r_spec_2048_r105_XSG_core_config/r_spec_2048_r105_XSG_core_config/r_spec_204
>
> 8_r105_x0/fft_wideband_real_b9aab9e8c9/fft_unscrambler_d7ee91cd7f/reorder_71b
>   a0a1129/map4/comp5.core_instance5/BU2' with type
>   'dmg_43_c2a1bee36c7e7174_dist_mem_gen_v4_3_xst_1' could not be resolved.
> A
>   pin name misspelling can cause this, a missing edif or ngc file, or the
>   misspelling of a type name. Symbo

Re: [casper] FFT on ROACH

[Mark Wagner]

Hi Andrea,

The first thing I would do is delete the fft and replace it with one from
your updated library, using the same parameters of course.  If you're still
having the problem, I would try running the mask script from the matlab
command prompt to get a more verbose output.  To see how the mask script is
called, right click on the block and select 'view mask,' then select the
'initialization' tab.

Mark


On Mon, Aug 30, 2010 at 4:19 AM, Andrea Mattana
wrote:

> Hi All,
>
>  I'm a Medicina Radiotelescopes (Italy) team member, my name is Andrea
> Mattana, I'm working here since January to develop a new acquisition
> system for SETI based on the CASPER ROACH board.
>
>  I have started to work using the libraries available on the SVN
> repository and in June I have done the migration on GIT following your
> instractions and now I'm very up-to-date.
>
>  I have some problems in using the CASPER FFT libraries, the drawings
> seems to do not update after changing parameters. When I try to look
> under mask (i.e. on fft_biplex_real_2x) there are no connections at all
> between blocks, while many other casper blocks works nominally. I have
> seen on the GIT commit log an update done by David MacMahon on those
> blocks, I don't know if he is the right person that can help me anyway
> I'm very happy to hear any suggestion to fix the problem from you all.
>
>  The developing system I use it is a Linux Centos release 5.5 64 bit,
> Matlab R2009b, Xilinx 11.4.
>
>  Kind regards,
>
>Andrea Mattana
>
>
> ---
>
> Andrea Mattana
>
> Istituto Nazionale di Astrofisica
> Istituto di RadioAstronomia
>
> Stazione di Medicina
> Via Fiorentina 3508/B
> I-40059 Medicina (BO)
> Tel  +39-051-6965834
> Fax +39-051-6965810
>
>
>

Re: [casper] ROACH start-up issues.

[Mark Wagner]

Hi Ramesh,

Are you sure you're using a null modem cable?  (
http://casper.berkeley.edu/wiki/Equipment_Cables)

Also, I haven't tried ckermit, you may want to try using minicom or picocom.
 Power cycling
after you've tried to connect.

Mark



On Wed, Sep 8, 2010 at 2:19 PM, Ramesh Karuppusamy  wrote:

> Dear CASPERites,
>
> We received our ROACH board from Digicom, and I am trying to get the basic
> communication going.
>
> The Xport web interface shows up when I connect to 192.168.4.20, and I used
> that to configure the serial interface to talk at 115200 bauds, 8N1.
> However, when I connect a serial terminal (ckermit running on Ubuntu) and
> restart the ROACH system,  I see no activity on the serial port.
>
> I ruled out problems with the serial cable by short-circuiting pins 2/3 and
> 7/8 to create a loop-back - this should simply echoed back what I typed and
> it did.
>
> When I telnet to 192.168.2.40, port 10001, I do not see any uBoot prompt.
>
> Any clues on what is going wrong with this board? Do I have start all over
> again and use a usbWiggler as described in
> http://casper.berkeley.edu/wiki/ROACH_Bringup?
>
> cheers,
> Ramesh
>

Re: [casper] ROACH start-up issues.

[Mark Wagner]

Hi Ramesh,

Can you confirm that your terminal client is set to: BAUD = 115200, 8
Bits, no parity, stop bit, no flow control

If this is the case, then i'm not sure what the problem is.  Do you have the
same problem with a different client?
For instance, I use picocom:

$ sudo apt-get install picocom
$ picocom --baud 115200 /dev/ttyUSB0 (where /dev/ttyUSB0 is the serial
device)

Thanks,
Mark


On Wed, Sep 8, 2010 at 4:41 PM, Ramesh Karuppusamy  wrote:

>
> Hi Mark, hi Sean:
>
> Thank you very much for the quick response. Yes, a null-modem cable solved
> the issue partly. I see the messages from the roach unit in my C-Kermit
> terminal emulation software.
>
> But I am unable to interrupt the boot procedure at "Hit any key to stop
> autoboot: " point. Once booted, I am unable to type anything at the "roach
> login: " prompt too? Am I missing something obvious?
>
> I am attaching the serial console messages with this mail.
>
> Any ideas?
>
> Thanks again.
>
> Cheers,
> Ramesh
>
>
>
>
> On Sep 8, 2010, at 8:29 PM, Mark Wagner wrote:
>
> Hi Ramesh,
>
> Are you sure you're using a null modem cable?  (
> http://casper.berkeley.edu/wiki/Equipment_Cables)
>
> Also, I haven't tried ckermit, you may want to try using minicom or
> picocom.  Power cycling
> after you've tried to connect.
>
> Mark
>
>
>
> On Wed, Sep 8, 2010 at 2:19 PM, Ramesh Karuppusamy wrote:
>
>> Dear CASPERites,
>>
>> We received our ROACH board from Digicom, and I am trying to get the basic
>> communication going.
>>
>> The Xport web interface shows up when I connect to 192.168.4.20, and I
>> used that to configure the serial interface to talk at 115200 bauds, 8N1.
>> However, when I connect a serial terminal (ckermit running on Ubuntu) and
>> restart the ROACH system,  I see no activity on the serial port.
>>
>> I ruled out problems with the serial cable by short-circuiting pins 2/3
>> and 7/8 to create a loop-back - this should simply echoed back what I typed
>> and it did.
>>
>> When I telnet to 192.168.2.40, port 10001, I do not see any uBoot prompt.
>>
>> Any clues on what is going wrong with this board? Do I have start all over
>> again and use a usbWiggler as described in
>> http://casper.berkeley.edu/wiki/ROACH_Bringup?
>>
>> cheers,
>> Ramesh
>>
>
>
>
>

Re: [casper] ROACH usbboot

[Mark Wagner]

Hi Ramesh,

Did you make sure that the partition you created was bootable?

Also, di you copy the filesystem over to the usb drive as root using 'cp
-rp'?
This is to preserve permissions and ownerships.

Mark


On Thu, Sep 9, 2010 at 10:26 AM, Ramesh Karuppusamy  wrote:

> Hi All,
>
> I am trying to boot a ROACH system off a usb-stick. I followed instructions
> found at
> http://casper.berkeley.edu/wiki/Getting_Started_with_ROACH and tried both
>
> I tried both filesystem_etch_nfs_2009_07_07.tar.gz and
> filesystem_etch_2009-11-30.tar.bz from the SVN repository.
>
> I used a 2GB usb-stick, then parted'ed the device to create a primary
> parition and then ran
> "mkfs .-t ext2" command to create an ext2 file system.
>
> I stopped the normal roach boot procedure, and then typed "run usbboot" and
> I see
> the following error:
>
> Warning: unable to open an initial console.
> Kernel panic - not syncing: No init found.  Try passing init= option to
> kernel.
>
> Including  "init=3" parameter to bootargs doesn't help either.
>
> Any idea on what is going wrong here?
>
> Thanks in advance!
>
> Cheers,
> Ramesh
>

Re: [casper] ROACH software

[Mark Wagner]

Hi Daniel,

Currently our libraries do not work with 12.x as Xilinx has stopped support
for the OPB bus structure,
which our yellow blocks depend on.

I'm not sure what board you're planning to use, but the BEE2 and IBOB have
Virtex-2, which
isn't supported in 11.x, but is supported in 10.1 under windows.  Matlab
2010a will not work with
the 10.1 toolflow as far as I know.  For 10.1 we use Matlab r2007b. There
may be other versions
that work, i'm just not aware of them.

If you plan on using a ROACH, then you can either use 10.1 or 11.x.  We
generally use 11.x under
Linux, which is what I would recommend since we would be able to give you
the most support here.

Best,
Mark


On Thu, Oct 7, 2010 at 8:39 AM, Daniel Esteban Herrera Pena <
danherr...@udec.cl> wrote:

> Hi there!
>
> I started to look at the tutorials as you recommended, now I have software
> issues, I have Matlab 2010a (windows) and I'm having troubles installing
> System Generator 10.1 (for the lastest CASPER libraries), I've contacted
> Xilinx customer support for a evaluation license (do you guys had to do
> the same?).
>
> Does anyone tried to work with Xilinx lastest version (12.3)?, the ISE
> Design Suite includes a lot of stuff (System Generator as well) and I see
> that I wouldn't have problems getting a free license for that version.
>
> Another issue, I'm not pretty sure, but it seems I need to create a
> startup.m file for CASPER libraries integration, it is correct? what I
> need to write there?.
>
> Thanks!
>
> Daniel H.
>
>
>

Re: [casper] 10Gbe yellow block outside of subnet?

[Mark Wagner]

Hi Billy,

I'm not aware of the 10Gbe being specific to certain subnets.  Are you sure
it's a generating packets issue and not a receiving packets?

Have you tried looking for packets using something like wireshark or
tcpdump?

Also, if you run ifconfig, what is your subnet mask set to?

Mark


On Wed, Oct 13, 2010 at 6:23 PM, Barott, William Chauncey
wrote:

>  Hi all,
>
>
>
> I'm running version 7 of the toolflow compiling for BEE2s.  Have run into a
> difficulty with the 10Gbe yellow block.
>
> I can quite successfully generate packets within the same subnet - e.g. the
> BEE2 on 10.4.0.100 and a receiver computer on 10.4.0.101.  However, I've not
> been successful in trying to generate packets outside of the /24 subnet.
> With the same 10.4.0.100 BEE2 address, I cannot get packets delivered to
> 10.5.0.101, for example (note the 4 changed to 5).  I've not been able to
> find a subnet configuration for the BEE2 10gbe block - maybe I've missed it,
> nor have I found anything about such a limitation in the documentation.  It
> could also be a peculiarity of my network setup (though it's all quite out
> of the box), but difficult to diagnose at this stage.
>
>
>
> Has someone out there successfully done what I'm trying to do?  Or know
> that it's not possible?
>
> Any info is appreciated.  Thanks!
>
>
>
> Billy
>
>
>
>
>
>
>

Re: [casper] filesystem update

[Mark Wagner]

Hi Laura,

If I remember correctly, the other thing that can cause this is not opening
up the tarball
as root.  Are you doing this?

Mark


On Tue, Oct 26, 2010 at 5:29 PM, Laura Spitler wrote:

> Hi everyone,
>
> I know this thread is old, but I'm running into the same problem. I'm
> trying to boot my ROACH using a USB stick formatted with one partion
> as ext2. I copied the latest filesystem (2010_03_24) (sudo cp -a )
> onto the drive making sure the normal root directories are in the
> "root" of the usb stick. The /dev/ directories are there.
>
> It stalls on the same error as for Mark:
>
> VFS: Mounted root (ext2 filesystem) readonly.
> Freeing unused kernel memory: 132k init
> Warning: unable to open an initial console.
>
> Any ideas?
> Laura
>
>
>
> On Mon, Feb 1, 2010 at 5:31 PM, Mark Wagner 
> wrote:
> > Thanks guys, I tried that and it seems to work now.
> > Mark
> >
> > On Mon, Feb 1, 2010 at 3:57 AM, Andy Lutomirski 
> wrote:
> >>
> >> cp -rp might not be enough -- the docs are vague on what it does to
> >> symlinks.  cp -a may be a better bet.
> >> Also, you can convert ext2 to ext3 directly using tune2fs -j.
> >>
> >> --Andy
> >>
> >>
> >> On Feb 1, 2010, at 2:40 AM, Mark Wagner 
> wrote:
> >>
> >> I updated my usb stick to the filesystem:
> >>
> >>
> http://casper.berkeley.edu/svn/trunk/roach/sw/binaries/filesystem/filesystem_etch_2009-11-30.tar.bz
> >> when I 'run usbboot' I get to:
> >> sd 1:0:0:0: [sda] 15794175 512-byte hardware sectors (8087 MB)
> >> sd 1:0:0:0: [sda] Write Protect is off
> >> sd 1:0:0:0: [sda] Assuming drive cache: write through
> >> sd 1:0:0:0: [sda] 15794175 512-byte hardware sectors (8087 MB)
> >> sd 1:0:0:0: [sda] Write Protect is off
> >> sd 1:0:0:0: [sda] Assuming drive cache: write through
> >>  sda: sda1
> >> sd 1:0:0:0: [sda] Attached SCSI removable disk
> >> EXT2-fs warning (device sda1): ext2_fill_super: mounting ext3 filesystem
> >> as ext2
> >> VFS: Mounted root (ext2 filesystem) readonly.
> >> Freeing unused kernel memory: 136k init
> >> Warning: unable to open an initial console.
> >> warning: `ntpd' uses 32-bit capabilities (legacy support in use)
> >> and then the boot process freezes.  I've repartitioned and rebuilt the
> >> filesystem as ext3 and then simply copied (cp -rp) over the files as
> i've
> >> done on other working usb sticks.  Any suggestions?
> >> Thanks,
> >> Mark
> >>
> >>
> >>
> >
> >
>

Re: [casper] ROACH ZDOK numbering

[Mark Wagner]

Hi Laura,

This is indeed the case.

Mark

On Sat, Nov 6, 2010 at 12:03 PM, Laura Spitler wrote:

> Hi everyone,
>
> Can someone please verify for me that ZDOK0 on the ROACH board
> corresponds to ADC0 in Simulink and ZDOK1 corresponds to ADC1?
>
> Thanks,
> Laura
>
>

Re: [casper] PAR could not meet all timing constraints.

[Mark Wagner]

Hi Daniel,

How fast are you trying to clock you design?  Try opening the timing report
by typing dos('timingan') from the Matlab prompt and File-->Open
./XPS_ROACH_base/implementation/system.twx from inside the design directory.
 This should tell you where the offending paths are (i.e. negative slack).
 You could then add latency strategically to give the data some time to
propagate.

Mark


On Wed, Nov 24, 2010 at 1:51 PM, Daniel Esteban Herrera Pena <
danherr...@udec.cl> wrote:

> Hi CASPER team,
>
> I wanted to test the iADC tutorial on my ROACH but I can't.
>
> I followed the tutorial changing XSG core from iBOB to sx95t and removing
> ibop_lwip from original design. Simulation worked perfect but when I start
> bee_xps the following error appears after a while twice:
>
> ERROR: 2 constraints not met.
>
> PAR could not meet all timing constraints. A bitstream will not be
> generated.
>
> I saw what Mark Wagner recommended to see:
> /XPS_ROACH_base/implementation/system_map.mrp
>
> The thing I have here is a large file but I suspect that the problem is
> around this part:
>
> Asterisk (*) preceding a constraint indicates it was not met.
>   This may be due to a setup or hold violation.
>
>
> --
>  Constraint|Check| Worst Case |
> Best Case | Timing |   Timing
>| |Slack   |
> Achievable | Errors |Score
>
> --
> * NET "iadc_test_adc/iadc_test_adc/adc_clk_ | MAXPERIOD   |-1.666ns|
> |   1|1666
>  buf" PERIOD = 10 ns HIGH 50%  | MINLOWPULSE | 4.666ns|
>  5.334ns|   0|   0
>
> --
> * PERIOD analysis for net "iadc_test_adc/ia | SETUP   | 8.535ns|
>  1.465ns|   0|   0
>  dc_test_adc/adc_clk_dcm" derived from  NE | HOLD| 0.148ns|
> |   0|   0
>  T "iadc_test_adc/iadc_test_adc/adc_clk_bu | MINPERIOD   | 7.779ns|
>  2.221ns|   0|   0
>  f" PERIOD = 10 ns HIGH 50%  duty cycle co | MAXPERIOD   |-1.666ns|
> |   1|1666
>  rrected to 10 nS  HIGH 5 nS   | ||
> ||
>
> --
>
> Both constraints have a MAXPERIOD of -1.666ns, I don't know that a minus
> have to do here with time, but is what the report says.
>
> Do you have any insights of this?. Or I just disable the PAR timing check?
>
> Best!
>
> Daniel Herrera
>
>
>

Re: [casper] 10GbE vs XAUI

[Mark Wagner]

Hi Jonathan,

The XAUI sends data point to point using layer 2 (Data Link Layer) in the
OSI model; while 10GbE uses layer 4 (Transport Layer).  I think you'd want
to use XAUI for direct connections from board to board (less overhead),
while using 10GbE for data sent using a switch, router, or otherwise, from
an FPGA board to a server, or to other FPGA boards.

Mark


On Tue, Nov 30, 2010 at 8:53 PM, David MacMahon
wrote:

> Hi, Jonathan,
>
> Both the XAUI and the 10 GbE blocks provide high speed serial connectivity.
>  The main difference is that the XAUI block provides a (less complex)
> point-to-point streaming interface with another XAUI block, whereas the 10
> GbE block provides a (more complex) switchable (and I think even routable)
> datagram interface to any other 10 GbE enabled device.  If you want to send
> high speed data from a casper device (e.g. roach) to a non-casper device
> (e.g. "receive computer"), the 10 GbE core is the only one that is suitable.
>
> Hope this helps,
> Dave
>
> On Nov 30, 2010, at 2:56 PM, Jonathan Landon wrote:
>
> > When is it more appropriate to use the XAUI block instead of the
> ten_Gbe_v2 block?  Is it a matter of talking to a non-CASPER device -- i.e.,
> both blocks work equally well for talking between ROACHs but for streaming
> data to a receive computer it makes sense to create a UDP socket and use the
> ten_Gbe_v2 block that sends UDP packets?
> >
> > Thanks,
> > Jonathan Landon
> >
> >
>
>
>

Re: [casper] Writing binary to BRAMs on roach?

[Mark Wagner]

Hi Jon,

I think you may want to try using the struct.pack()
method to
format your data before the fpga.write() call.

Best,
Mark


On Thu, Jan 6, 2011 at 1:22 PM, Jon Losh  wrote:

> Hi,
>
> I'm using Corr in Python to write test data to BRAMs on a roach, but
> whenever I try to write something using the fpga.write() method, it writes
> the ASCII codes rather than the numbers themselves. The fpga.write() method
> also won't take anything but a string as its input, and I can't find any
> detailed documentation for Corr for how to fix this.
>
> I found some references to an "ioreg" variable that I can set to make the
> roach interpret things as binary rather than ASCII, but I can't figure out
> what process number my BORPH file is.
>
> Anyone have any hot ideas?
>

Re: [casper] Tut3 trouble - Error due to multiple causes

[Mark Wagner]

Hi Daniel,

This error occurs when the Simulink design is updated.  It's possible the
library you've loaded has blocks that are different than those used to
create the original design.  If you start a simulation (Simulation -->
Start), the error dialog box should pop up with more detailed information
about the offending block or connection.  If the issue is a block, try
deleting it and replacing it with one from your library.

Mark


2011/2/15 Daniel Esteban Herrera Peña 

> Hi everyone,
>
> I could get a 800MHz clock source to test the spectrometer in tut3 (using
> the pre-compiled file you provided) with successful results including
> changing the input frequency to 1GHz, now I want to change the adc input
> clock to 2GHz (I see that I must change to interleave mode), but first I
> tried to synthesize the r_spec_2048_r105 without making any change and I
> receive this error:
>
> Detected Linux OS
> #
> ##  System Update  ##
> #
> Error using ==> gen_xps_files at 199
> Error due to multiple causes.
>
> If I knew just one cause I will be happy trying to resolve it, but I have
> no clue at all. I saw in the forums some issue regarding the adc block, I
> tried to follow those steps (re-adding adc block, disabling link) but the
> problem persist. Does anyone knows how to inspect more deeply the error I'm
> having?.
>
> Thanks.
>
> Daniel H.
>
>

Re: [casper] Tut3 trouble - Error due to multiple causes

[Mark Wagner]

Hi Daniel,

The extra ports in your design may be due to not having the "Number of
Simultaneous inputs" set correctly in either the pfb or fft.  Can you check
this in the fft and pfb and verify they are the same?

Mark


2011/2/18 Daniel Esteban Herrera Peña 

> Hi team,
>
> Thank you Mark for your suggestion, I identify two blocks pfb_fir_real and
> fft_wideband_real (only green blocks) I read all the parameters and I insert
> the same blocks again (the fft block has two different parameters from the
> tutorial and the pfb only one) the pfb block now shows two extra ports
> related to an strange second signal (an input pol2_in1 and an output
> pol2_out1) so I replace this pfb block without making connections in those
> ports (except for a terminator on pol2_out1). After run simulation and wait
> for some minutes an error window pops up:
>
>  MessageSourceReported by   Summary
> Model Error  Unknown   Simulink  Error due to multiple causes.
> Block Error  pfb_fir_real  Simulink  Error in 'tut3/pfb_fir_real':
> Initialization commands cannot be evaluated.
>
> The first error still chasing me to hell, and the second I think it is
> related to this new strange ports (pol2), the parameter "coefficient
> bitwidth" is set to 18 bits according to the original design but the
> tutorial suggest to be less than or equal to the input bit width (8), it
> this alright?
>
> Any insights?
>
> thank you.
>
> Daniel H.
>
>
> On Tue, 15 Feb 2011 13:33:20 -0800, Mark Wagner 
> wrote:
>
>> Hi Daniel,
>>
>> This error occurs when the Simulink design is updated.  It's
>> possible the library you've loaded has blocks that are different than
>> those used to create the original design.  If you start a simulation
>> (Simulation --> Start), the error dialog box should pop up with more
>> detailed information about the offending block or connection.  If the
>> issue is a block, try deleting it and replacing it with one from your
>> library.
>>
>> Mark
>>
>> 2011/2/15 Daniel Esteban Herrera Peña
>>  Hi everyone,
>>
>>  I could get a 800MHz clock source to test the spectrometer in tut3
>> (using the pre-compiled file you provided) with successful results
>> including changing the input frequency to 1GHz, now I want to change
>> the adc input clock to 2GHz (I see that I must change to interleave
>> mode), but first I tried to synthesize the r_spec_2048_r105 without
>> making any change and I receive this error:
>>
>>  Detected Linux OS
>>  #
>>  ##  System Update  ##
>>  #
>>  Error using ==> gen_xps_files at 199
>>  Error due to multiple causes.
>>
>>  If I knew just one cause I will be happy trying to resolve it, but I
>> have no clue at all. I saw in the forums some issue regarding the adc
>> block, I tried to follow those steps (re-adding adc block, disabling
>> link) but the problem persist. Does anyone knows how to inspect more
>> deeply the error I'm having?.
>>
>>  Thanks.
>>
>>  Daniel H.
>>
>>
>>
>> Links:
>> --
>> [1] mailto:danherr...@udec.cl
>>
>
> --
> 
> Daniel Esteban Herrera Peña
> Ingeniero Civil Electrónico
> Universidad de Concepción, Chile.
> (41)236-0289 842-38325
> 
>
>

Re: [casper] Licensing dsp tools 10.1

[Mark Wagner]

Hi Daniel,

This is a CASPER archived email thread related to your question:

http://www.mail-archive.com/casper@lists.berkeley.edu/msg01228.html

Basically, you should
make sure you're running a supported OS (
http://www.xilinx.com/ise/ossupport/index.htm).  Here at Berkeley, we use
RHEL5, which works fine.  CentOS is free and based on Redhat is also know to
work.  If you choose either of these options, it will be much easier for us
to help you debug your issues.

Mark


2011/2/23 Daniel Esteban Herrera Peña 

> Dear Casperites,
>
> I'v been having troubles synthesizing the spectrometer, so I wanted to try
> a different version of every tool I'm using (Ubuntu Lynx/Matlab2009b/Xilinx
> 11.4 to WinXP/Matlab2007b/Xilinx 10.1) but I can't have dsp tools installed,
> I installed Xilinx Webpack 10.1 and I execute the dsp_tools installer, the
> program ask me for a registration ID (I use what xilinx gave me for webpack)
> but that is not the right one. I can't even have a 30 day trial, so my
> question is how did you guys can work with this old version for free?
>
> Kind regards,
>
> Daniel H.
>
>

Re: [casper] CentOS xilinx license manager

[Mark Wagner]

Hi Daniel,

I'm sorry you're having trouble with CentOS.  I prefer Ubuntu as well, but
as Dan said, we couldn't get the toolflow to reasonably work with it.

Have you run 'xilinxupdate?'  It should be at:

/opt/Xilinx/11.1/common/bin/lin64/xilinxupdate

Is there any error you're getting when you run this?  Can you send that
along?

Thanks,
Mark



2011/2/28 Daniel Esteban Herrera Peña 

> Dear Casper friends,
>
> I'm trying to have a functional setup with CentOS 5, I've already installed
> Matlab and Xilinx 11.1, the problem is that I can't update to 11.4 because
> for some reason nothing happens after executing xlcm (Xilinx License
> Manager), I'm ok with Ubuntu but with this OS I had some issues making
> things work, if some of you has passed for this before, I'd be happy to know
> how you resolve it.
>
> Regards,
>
> Daniel H.
>
>

Re: [casper] High clock freq timing error

[Mark Wagner]

Hi Daniel,

>From the Matlab command prompt, you can type dos('timingan') and then open
the timing report ./XPS_ROACH_base/implementation/system.twx from the
analyzer.  You'll see where the timing issues are occurring (i.e. negative
slack).  You can then go back to your design and add registers or delays
where appropriate to hopefully allow data to propagate in a reasonable time.
 This takes up resources though, and can sometimes make things worse.  If
you're unable to get the design to meet timing at this point, it may behoove
you to use the floor planner.

Mark


2011/3/1 Daniel Esteban Herrera Peña 

> Continuing with the frequency problem...
>
> Now from CentOS I checked the same design, it's the spectrometer from
> tutorial 3 which I change freq from 800 to 1000MHz and I also change the
> User IP Clock Rate from 200 to 250MHz, the synthesis stops in the same
> error, but now I see that the numbers are slight different:
>
>
>
> --
>  Constraint|Check| Worst Case |
>  Best Case | Timing |   Timing
>| |Slack   |
> Achievable | Errors |Score
>
> --
> * PERIOD analysis for net "tut3_adc/tut3_ad | SETUP   |-1.638ns|
>   5.638ns| 110|   45473
>  c/adc_clk_dcm" derived from  NET "tut3_ad | HOLD| 0.102ns|
>|   0|   0
>  c/tut3_adc/adc_clk_buf" PERIOD = 4 ns HIG | ||
>||
>  H 50% | ||
>||
>
> I don't know what else I need to do! any insight will be greatly
> appreciated!
>
> Cheers,
>
> Daniel.
>
>
> On Fri, 25 Feb 2011 16:46:45 -0300, Daniel Esteban Herrera Peña <
> danherr...@udec.cl> wrote:
>
>> Hi Henry,
>>
>> Thanks for your quick response, as you thought, I indeed enter
>> 2000... in the meantime I digest how ADC works, I tried to compile
>> changing freq 800 to 1000 in the original design (no interleaving),
>> and I receive this error:
>>
>>
>>
>> --
>>  Constraint|Check| Worst
>> Case |  Best Case | Timing |   Timing
>>| |Slack
>> | Achievable | Errors |Score
>>
>>
>> --
>> * PERIOD analysis for net "spec_1ghz_adc/sp | SETUP   |
>> -0.656ns| 4.656ns| 123|   31325
>>  ec_1ghz_adc/adc_clk_dcm" derived from  NE | HOLD|
>> 0.118ns||   0|   0
>>  T "spec_1ghz_adc/spec_1ghz_adc/adc_clk_bu | |
>> |||
>>  f" PERIOD = 4 ns HIGH 50% | |
>> |||
>>
>>
>> --
>>  TS_epb_clk = PERIOD TIMEGRP "epb_clk" 88  | SETUP   |
>> 0.134ns|11.229ns|   0|   0
>>  MHz HIGH 50%  | HOLD|
>> 0.360ns||   0|   0
>>
>>
>> --
>>  NET "spec_1ghz_adc/spec_1ghz_adc/adc_clk_ | MINLOWPULSE |
>> 1.000ns| 3.000ns|   0|   0
>>  buf" PERIOD = 4 ns HIGH 50%   | |
>> |||
>>
>>
>> --
>>  NET "epb_cs_n_IBUF" MAXDELAY = 4 ns   | MAXDELAY|
>> 2.366ns| 1.634ns|   0|   0
>>
>>
>> --
>>  NET "spec_1ghz_adc/spec_1ghz_adc/adc_clk_ | N/A |
>> N/A| N/A| N/A| N/A
>>  buf" PERIOD = 4 ns HIGH 50%   | |
>> |||
>>
>>
>> --
>>
>> I see with this that I won't even be able to compile an interleaved
>> design, what else I can try?
>>
>> Thank you,
>>
>> Daniel H.
>>
>> On Fri, 25 Feb 2011 10:58:47 -0800, Henry Chen
>>  wrote:
>>
>>> Hi Daniel,
>>>
>>> It looks like you might have put 2000 into the "ADC clock rate"
>>> setting in the ADC yellow block. This will try to run the FPGA at
>>> 500MHz, which explains the timing error (it's very difficult
>>> to run the FPGA beyond 350MHz for a complex DSP design).
>>>
>>> I'm guessing you want to sample at 2GS/s, in which case you would put
>>> 1000 into the "ADC clock rate" box, and che

Re: [casper] git connection

[Mark Wagner]

Hi Danial,

git://casper.berkeley.edu/mlib_devel.git is a public repository, so you
don't need any account.  You're probably behind a firewall.  I may be wrong,
but I don't think SELinux blocks git:// so you probably need to talk to your
sysadmin.

Also, if you don't want to deal with it, you can download the tarball from
here .

Mark




2011/3/8 Daniel Esteban Herrera Peña 

> Dear Casper fellows,
>
> I tried to clone git rep (git://casper.berkeley.edu/mlib_devel.git) from
> CentOS and Win7, both fails with the message:
>
> git 1.7.4 (in CentOS 5):
> casper.berkeley.edu[0: 128.32.18.176]: errno=No error
> fatal: unable to connect a socket (No error)
>
> Git GUI (Windows):
> casper.berkeley.edu[0: 128.32.18.176]: errno=Connection refused
> fatal: unable to connect a socket (Connection refused)
>
> do I need an account or there's issues with the repository?
>
> Thank you!
>
> Daniel.
>
>

Re: [casper] pfb sync_out

[Mark Wagner]

Hi Samuel,

This seems strange, if you are indeed sending a sync pulse into the pfb, it
should return out after some delay.  I would recommend the sync_out of the
pfb attached to the enable of a counter attached to a software register
and/or a 'To Workspace.'  This should tell you for certain.

Mark


On Thu, Mar 10, 2011 at 8:45 PM, Samuel Tun  wrote:

> Hi there,
>
> Thanks to the various recommendations on this archive I have been able
> to compile an f-engine design for a ROACH board running at 250 MHz for
> a 1 GHz signal off the ADC. In testing the actual calculations along
> the data flow I found that, although my sync generator logic emits a
> sync pulse regularly, as expected, the corresponding sync pulse never
> comes out of the pfb  sync_out pin. That is, the sync_gen signal is
> pretty regular in my scope's plot, but the data coming out of the pfb
> sync_out always remains at zero, even though I see the actual data
> coming out of the pfb with the appropriate delay.
>
> Am I wrong in thinking that I should be seeing the delayed syng_gen
> pulse out of the pfb?
>
> thanks,
> Sam Tun
>
>

Re: [casper] tut2 10gbe not configuring

[Mark Wagner]

Hi Jon,

You're right, if you've just run the script, tgtap should be running on the
roach.

Which version of the roach filesystem are you using?  There were some

changes to tgtap awhile back.  If you're using an older version of the
filesystem

tgtap may not be compatible with the latest version of tut2.

Mark

On Thu, Mar 17, 2011 at 11:38 AM, Jon Losh  wrote:

> Hi,
>
> So I've been trying to get 10gbe working for tutorial 2, and the script
> keeps failing when it tries to call fpga.tap_start(). I get the following
> error:
>
> Connecting to server 10.0.0.105...  ok
>
> 
> Programming FPGA... ok
> ---
> Port 0 linkup:  True
> Port 3 linkup:  True
> ---
> Configuring receiver core... FAILURE DETECTED. Log entries:
> 10.0.0.105: Starting thread Thread-1
> 10.0.0.105: #version poco-0.1
> 10.0.0.105: #build-state poco-0.1775
> 10.0.0.105: ?progdev tut2_2011_Mar_16_1608.bof
>
> 10.0.0.105: !progdev ok
> 10.0.0.105: ?read gbe0_linkup 0 4
>
> 10.0.0.105: !read ok \0\0\0
> 10.0.0.105: ?read gbe3_linkup 0 4
>
> 10.0.0.105: !read ok \0\0\0
> None
>
> My sysadmin tells me that we have the latest versions of of the ROACH
> kernel, tcpborphserver, and corr, so I'm not totally sure what's up. One of
> the threads in the mail archive said to try checking the processes running
> on the roach to see if tgtap was running; a "ps aux" gives:
>
> root@10:~# ps aux
> USER   PID %CPU %MEMVSZ   RSS TTY  STAT START   TIME COMMAND
> root 1  0.0  0.0   2428   744 ?Ss   Oct01   0:02 init [2]
> root 2  0.0  0.0  0 0 ?S<   Oct01   0:00 [kthreadd]
> root 3  0.0  0.0  0 0 ?S<   Oct01   0:00
> [ksoftirqd/0]
> root 4  0.0  0.0  0 0 ?S<   Oct01   0:03 [events/0]
> root 5  0.0  0.0  0 0 ?S<   Oct01   0:00 [khelper]
> root51  0.0  0.0  0 0 ?S<   Oct01   0:00
> [kblockd/0]
> root61  0.0  0.0  0 0 ?S<   Oct01   0:00 [khubd]
> root68  0.0  0.0  0 0 ?S<   Oct01   0:00 [kmmcd]
> root88  0.0  0.0  0 0 ?SOct01   0:01 [bkexecd]
> root89  0.0  0.0  0 0 ?SOct01   0:00 [pdflush]
> root90  0.0  0.0  0 0 ?SOct01   0:00 [pdflush]
> root91  0.0  0.0  0 0 ?S<   Oct01   0:00 [kswapd0]
> root92  0.0  0.0  0 0 ?S<   Oct01   0:00 [aio/0]
> root   150  0.0  0.0  0 0 ?S<   Oct01   0:00
> [mtdblockd]
> root   196  0.0  0.0  0 0 ?S<   Oct01   0:00 [krmond]
> root   203  0.0  0.0  0 0 ?S<   Oct01   0:00 [rpciod/0]
> root   208  0.0  0.0  0 0 ?S<   Oct01   0:00 [mmcqd]
> root   214  0.0  0.0  0 0 ?SN   Oct01   0:00
> [jffs2_gcd_mtd3]
> root   238  0.0  0.1   6700  1164 ?Ss   Oct01   0:00
> /usr/sbin/sshd
> ntp247  0.0  0.1   5432  1312 ?Ss   Oct01   0:03
> /usr/sbin/ntpd -p /var/run/ntpd.pid -u 101:103 -g -b -l /tmp/nt
> root   256  0.0  0.0   1908   648 ?SOct01   0:00
> tcpborphserver2
> root   264  0.0  0.0   1788   576 ttyS0Ss+  Oct01   0:00
> /sbin/getty -L ttyS0 115200 vt100
> root   292  0.0  0.0   1632   304 ?S02:32   0:00
> /boffiles/tut2_2011_Mar_16_1608.bof
> root   293  7.3  0.2  1  2668 ?Ss   02:38   0:00 sshd:
> root@pts/0
> root   296  1.0  0.1   3552  1792 pts/0Ss   02:38   0:00 -bash
> root   300  0.0  0.0   2780   996 pts/0R+   02:38   0:00 ps aux
>
> Should tgtap be one of the processes running under "command"? If so, it
> doesn't appear to be there. Any ideas on a good angle to attack this from?
>

Re: [casper] tut2 10gbe not configuring

[Mark Wagner]

Well, that depends.  Are you simply using the mmc card that came with your
roach?  If so,  how long ago did it arrive?  If you're using NFS or USB
stick, then you probably would have downloaded the tarball, in which case,
the version would be in the name. Maybe some else knows a better way to
tell.

You should be able to get the newest version here:

http://casper.berkeley.edu/svn/trunk/roach/sw/binaries/filesystem/

Also, have you tried running tgtap from the roach itself?  Once you've
already loaded the design?  Find the process ID, and the name you're using
for the device... for ex:

tgtap -b /proc/959/hw/ioreg/ten_GbE -a 10.0.0.31 -t ten_GbE -m
02:02:0A:00:00:1F -p 33107

Mark


On Thu, Mar 17, 2011 at 1:10 PM, Jon Losh  wrote:

> How do I check what version of the filesystem I have?
>
>
> On Thu, Mar 17, 2011 at 4:04 PM, Mark Wagner wrote:
>
>> Hi Jon,
>>
>> You're right, if you've just run the script, tgtap should be running on
>> the roach.
>>
>> Which version of the roach filesystem are you using?  There were some
>>
>> changes to tgtap awhile back.  If you're using an older version of the
>> filesystem
>>
>> tgtap may not be compatible with the latest version of tut2.
>>
>> Mark
>>
>> On Thu, Mar 17, 2011 at 11:38 AM, Jon Losh  wrote:
>>
>>> Hi,
>>>
>>> So I've been trying to get 10gbe working for tutorial 2, and the script
>>> keeps failing when it tries to call fpga.tap_start(). I get the following
>>> error:
>>>
>>> Connecting to server 10.0.0.105...  ok
>>>
>>> 
>>> Programming FPGA... ok
>>> ---
>>> Port 0 linkup:  True
>>> Port 3 linkup:  True
>>> ---
>>> Configuring receiver core... FAILURE DETECTED. Log entries:
>>> 10.0.0.105: Starting thread Thread-1
>>> 10.0.0.105: #version poco-0.1
>>> 10.0.0.105: #build-state poco-0.1775
>>> 10.0.0.105: ?progdev tut2_2011_Mar_16_1608.bof
>>>
>>> 10.0.0.105: !progdev ok
>>> 10.0.0.105: ?read gbe0_linkup 0 4
>>>
>>> 10.0.0.105: !read ok \0\0\0
>>> 10.0.0.105: ?read gbe3_linkup 0 4
>>>
>>> 10.0.0.105: !read ok \0\0\0
>>> None
>>>
>>> My sysadmin tells me that we have the latest versions of of the ROACH
>>> kernel, tcpborphserver, and corr, so I'm not totally sure what's up. One of
>>> the threads in the mail archive said to try checking the processes running
>>> on the roach to see if tgtap was running; a "ps aux" gives:
>>>
>>> root@10:~# ps aux
>>> USER   PID %CPU %MEMVSZ   RSS TTY  STAT START   TIME COMMAND
>>> root 1  0.0  0.0   2428   744 ?Ss   Oct01   0:02 init
>>> [2]
>>> root 2  0.0  0.0  0 0 ?S<   Oct01   0:00
>>> [kthreadd]
>>> root 3  0.0  0.0  0 0 ?S<   Oct01   0:00
>>> [ksoftirqd/0]
>>> root 4  0.0  0.0  0 0 ?S<   Oct01   0:03
>>> [events/0]
>>> root 5  0.0  0.0  0 0 ?S<   Oct01   0:00
>>> [khelper]
>>> root51  0.0  0.0  0 0 ?S<   Oct01   0:00
>>> [kblockd/0]
>>> root61  0.0  0.0  0 0 ?S<   Oct01   0:00 [khubd]
>>> root68  0.0  0.0  0 0 ?S<   Oct01   0:00 [kmmcd]
>>> root88  0.0  0.0  0 0 ?SOct01   0:01
>>> [bkexecd]
>>> root89  0.0  0.0  0 0 ?SOct01   0:00
>>> [pdflush]
>>> root90  0.0  0.0  0 0 ?SOct01   0:00
>>> [pdflush]
>>> root91  0.0  0.0  0 0 ?S<   Oct01   0:00
>>> [kswapd0]
>>> root92  0.0  0.0  0 0 ?S<   Oct01   0:00 [aio/0]
>>> root   150  0.0  0.0  0 0 ?S<   Oct01   0:00
>>> [mtdblockd]
>>> root   196  0.0  0.0  0 0 ?S<   Oct01   0:00 [krmond]
>>> root   203  0.0  0.0  0 0 ?S<   Oct01   0:00
>>> [rpciod/0]
>>> root   208  0.0  0.0  0 0 ?S<   Oct01   0:00 [mmcqd]
>>> root   214  0.0  0.0  0 0 ?SN   Oct01   0:00
>>> [jffs2_gcd_mtd3]
>>> root   238  0.0  0.1   6700  1164 ?Ss   Oct01   0:00
>>> /usr/sbin/sshd
>>> ntp247  0.0  0.1   5432  1312 ?Ss   Oct01   0:03
>>> /usr/sbin/ntpd -p /var/run/ntpd.pid -u 101:103 -g -b -l /tmp/nt
>>> root   256  0.0  0.0   1908   648 ?SOct01   0:00
>>> tcpborphserver2
>>> root   264  0.0  0.0   1788   576 ttyS0Ss+  Oct01   0:00
>>> /sbin/getty -L ttyS0 115200 vt100
>>> root   292  0.0  0.0   1632   304 ?S02:32   0:00
>>> /boffiles/tut2_2011_Mar_16_1608.bof
>>> root   293  7.3  0.2  1  2668 ?Ss   02:38   0:00 sshd:
>>> root@pts/0
>>> root   296  1.0  0.1   3552  1792 pts/0Ss   02:38   0:00 -bash
>>> root   300  0.0  0.0   2780   996 pts/0R+   02:38   0:00 ps aux
>>>
>>> Should tgtap be one of the processes running under "command"? If so, it
>>> doesn't appear to be there. Any ideas on a good angle to attack this from?
>>>
>>
>>
>

Re: [casper] Roach: Getting Started Enviroment 2011

[Mark Wagner]

Hi Miguel,

Sorry you're having so much trouble.

1. This is just a warning you're getting and doesn't hav any effect on the
functionality of the toolflow, but you can comment out:

Browser(2).Library = 'testbench_lib';
Browser(2).Name= 'Testbench Blockset';

in mlib_devel/gavrt_library/slblocks.m, and you should stop getting that
warning.

2.  I think this is because you are opening up the model file with a newer
library than what it was originally created with.  But I think you solved
this already by deleting the block and pulling from the library you're
opening the model file with.

3.  If you look at this posedge, I think it's not being loaded correctly.
 If you try deleteing and replacing the posedge (tut2/pkt_sim/posedge) like
you did in 2, it should fix the problem.

4. I'm not sure what the issue is here, but try ctrl-D, which will update
the design and propagate the data types and hopefully it will give a more
telling error.

Best,
Mark


On Tue, Apr 5, 2011 at 1:43 AM,  wrote:

>   Hi Griffin,
> Thank you so much!!
>
> About the first option
> centos 5.3 / Xilinx ISE 11.4 / Matlab 2009b
> Are  Casper Libraries compatibles with? I mean, don’t are they build for
> Ise 10.1?
>
>
> My problems?  Ok let’s go step by step:
>
> 1) Each time I open simulink:
> Warning: Could not find library ‘testbench_lib’ o speciefied in
> ‘C:\codigos\mlib_devel\gavrt_library\slblocks.m’
>
> 2) The first time i open a model all the yellow blocks are “bad link” and
> matlab welcomes me with a lot of warnigs like:
> “Warning: "tut1/counter_value" is a parameterized link. To view, discard,
> or propagate the changes for this link,
> use the "Link Options" menu item.”
> With the tutorial 2 I also get four warnings like,
> “Warning: casper_library_misc.mdl, line 5905: block_diagram does not have a
> parameter named 'BlockName'”.
> And others warning about a parameter "SID” (I can remember a discussion
> about SID in the casper list)
> Anyway, then I pick up an element from BEE_XPS System Blockset (i can see
> this library in the simulink library browser) , put it in the model and the
> yellow blocks became ok.
>
> 3) When I tried to run ‘bee_xps’ with ‘tut2.mdl’ i get the same warnings
> plus the following error:
> Error using ==> gen_xps_files at 199
> Failed to find 'Misc/pulse_ext/posedge' in library 'casper_library'
> referenced by 'tut2/pkt_sim/posedge'.
>
> 4) With tutorial3 after “bee_xps” the thing are getting worse... I received
> around fifty errors like (i only copy two of them but i have a .txt file if
> someone is interested in):
> “Error using ==> gen_xps_files at 199
> --> Error reported by S-function 'sysgen' in 'r_spec_2048_r105/Concat1':
> An internal error occurred in the Xilinx Blockset Library.
>
> Please report this error to Xilinx (http://support.xilinx.com), in as much
> detail as possible. You may also find immediate help in the Answers Database
> and other online resources at http://support.xilinx.com.
>
> Since it is possible that this internal error resulted from an unhandled
> usage error in your design, we advise you to carefully check the usage of
> the block reporting the internal error. If errors persist, we recommend that
> you restart MATLAB.”
>
> “--> Error in 'r_spec_2048_r105/sync_cnt': Initialization commands cannot
> be evaluated.  MATLAB error message: Error using ==> register_mask at 48
> Error evaluating 'MoveFcn' callback of Xilinx Gateway Out Block block
> (mask) 'r_spec_2048_r105/sync_cnt/r_spec_2048_r105_sync_cnt_user_data_in'.
> Error using ==> xlBlockMoveCallback at 53
> Error reported by S-function 'sysgen' in
> 'r_spec_2048_r105/sync_cnt/r_spec_2048_r105_sync_cnt_user_data_in':
> An internal error occurred in the Xilinx Blockset Library.
>
> Please report this error to Xilinx (http://support.xilinx.com), in as much
> detail as possible. You may also find immediate help in the Answers Database
> and other online resources at http://support.xilinx.com.
>
> Since it is possible that this internal error resulted from an unhandled
> usage error in your design, we advise you to carefully check the usage of
> the block reporting the internal error. If errors persist, we recommend that
> you restart MATLAB.”
>
>
>
> I download the models from Casper web so i assume they will be ok. This is
> the reason why i was wondering if i have the correct setup. I readed
> http://www.xilinx.com/support/answers/17966.htm  and chose, Windows XP 32
> bits, Matlab R2008a, ISE 10.1.3. Theoretically... it should be valid
> but
>
> Miguel.
>
>
>  **
> **
> *From:* Griffin Foster 
>  *Sent:* Monday, April 04, 2011 6:38 PM
> *To:* migu...@gmail.com
> *Cc:* casper@lists.berkeley.edu
> *Subject:* Re: [casper] Roach: Getting Started Enviroment 2011
>
> Hi Miguel,
>
> We are using a windows and linux setup which is:
>
> centos 5.3 / Xilinx ISE 11.4 / Matlab 2009b
> windows XP / Xilinx ISE 10.1 / Matlab 2007b
>
> the main git repo is at: git://casper.berkeley.edu/mlib_devel.git
>
> What kind of 

Re: [casper] Roach: Getting Started Enviroment 2011

[Mark Wagner]

Hi Miguel,

For 2, try opening a new model file and putting in the XSG_core_config and
System Generator blocks, pulling them from their libraries.  Then open up
tut1 and copy everything except the XSG_core_config and the SG blocks and
paste it into your new model file. Save and ctrl-D.  If that doesn't work,
you may have to redraw tut1 from scratch.

Mark


On Tue, Apr 5, 2011 at 3:54 AM, ---> Miguel A. S. G <---
wrote:

>  Hi Mark,
> Thank you for your quick reply. Following your instructions...
>
> 1.- It's solved.
>
> 2.- It's not solved. I mean, I swapped the blocks of tut1.mdl with blocks
> from my library. Save the model, close matlab, open matlab and same "bad
> links" appear.
>
> 3 and 4.- Im not at work now so.. tomorrow i will try it.
>
> Thank you anyway!
> Miguel.
>
>  *From:* Mark Wagner 
> *Sent:* Monday, April 04, 2011 9:05 PM
> *To:* migu...@gmail.com
> *Cc:* casper@lists.berkeley.edu
> *Subject:* Re: [casper] Roach: Getting Started Enviroment 2011
>
> Hi Miguel,
>
> Sorry you're having so much trouble.
>
> 1. This is just a warning you're getting and doesn't hav any effect on the
> functionality of the toolflow, but you can comment out:
>
>  Browser(2).Library = 'testbench_lib';
> Browser(2).Name= 'Testbench Blockset';
>
> in mlib_devel/gavrt_library/slblocks.m, and you should stop getting that
> warning.
>
> 2.  I think this is because you are opening up the model file with a newer
> library than what it was originally created with.  But I think you solved
> this already by deleting the block and pulling from the library you're
> opening the model file with.
>
> 3.  If you look at this posedge, I think it's not being loaded correctly.
>  If you try deleteing and replacing the posedge (tut2/pkt_sim/posedge) like
> you did in 2, it should fix the problem.
>
> 4. I'm not sure what the issue is here, but try ctrl-D, which will update
> the design and propagate the data types and hopefully it will give a more
> telling error.
>
> Best,
> Mark
>
>
> On Tue, Apr 5, 2011 at 1:43 AM,  wrote:
>
>>   Hi Griffin,
>> Thank you so much!!
>>
>> About the first option
>>  centos 5.3 / Xilinx ISE 11.4 / Matlab 2009b
>> Are  Casper Libraries compatibles with? I mean, don’t are they build for
>> Ise 10.1?
>>
>>
>> My problems?  Ok let’s go step by step:
>>
>> 1) Each time I open simulink:
>> Warning: Could not find library ‘testbench_lib’ o speciefied in
>> ‘C:\codigos\mlib_devel\gavrt_library\slblocks.m’
>>
>> 2) The first time i open a model all the yellow blocks are “bad link” and
>> matlab welcomes me with a lot of warnigs like:
>> “Warning: "tut1/counter_value" is a parameterized link. To view, discard,
>> or propagate the changes for this link,
>> use the "Link Options" menu item.”
>> With the tutorial 2 I also get four warnings like,
>> “Warning: casper_library_misc.mdl, line 5905: block_diagram does not have
>> a parameter named 'BlockName'”.
>> And others warning about a parameter "SID” (I can remember a discussion
>> about SID in the casper list)
>> Anyway, then I pick up an element from BEE_XPS System Blockset (i can see
>> this library in the simulink library browser) , put it in the model and the
>> yellow blocks became ok.
>>
>> 3) When I tried to run ‘bee_xps’ with ‘tut2.mdl’ i get the same warnings
>> plus the following error:
>> Error using ==> gen_xps_files at 199
>> Failed to find 'Misc/pulse_ext/posedge' in library 'casper_library'
>> referenced by 'tut2/pkt_sim/posedge'.
>>
>> 4) With tutorial3 after “bee_xps” the thing are getting worse... I
>> received around fifty errors like (i only copy two of them but i have a .txt
>> file if someone is interested in):
>> “Error using ==> gen_xps_files at 199
>> --> Error reported by S-function 'sysgen' in 'r_spec_2048_r105/Concat1':
>> An internal error occurred in the Xilinx Blockset Library.
>>
>> Please report this error to Xilinx (http://support.xilinx.com), in as
>> much detail as possible. You may also find immediate help in the Answers
>> Database and other online resources at http://support.xilinx.com.
>>
>> Since it is possible that this internal error resulted from an unhandled
>> usage error in your design, we advise you to carefully check the usage of
>> the block reporting the internal error. If errors persist, we recommend that
>> you restart MATLAB.”
>>
>> “--> Error in 'r_spec_2

Re: [casper] casper.berkeley.edu hacked

[Mark Wagner]

Hi all,

With a great deal of work by Jeff and Matt up at Space Science Lab,
casper.berkeley.edu has been re-imaged and most if not all services should
be fully functional.  Namely, the website, wiki, git, and svn.  We also now
require access to the website and wiki over HTTPS.  Currently, we have a
self signed certificate, but we've requested an official certificate through
UCB and hope to replace the existing one soon.

For those of you that have a wiki account, please change your password.

If anyone has any issues or notices something amiss, please let us know.

Thanks,
Mark


On Wed, May 11, 2011 at 3:14 PM, Andrew Siemion wrote:

> Hi all,
>
> We suspect that casper.berkeley.edu has been hacked and the perpetrator(s)
> escalated their access to root.  All passwords or ssh-keys of any variety
> used on or from casper.berkeley.edu should be considered compromised.
> Casper.berkeley.edu will be taken off the network and re-imaged.  If you
> had a shell account on the old system and still need one, please let us
> know.
>
> Thanks,
>
> Andrew
>
>

Re: [casper] casper.berkeley.edu hacked

[Mark Wagner]

Thanks Dave,

It was trying to use the old password -- should be fixed now.

Mark


On Mon, May 16, 2011 at 4:05 PM, David Hawkins  wrote:

> Hi Mark,
>
>
>
>  If anyone has any issues or notices something amiss, please let us know.
>>
>
> Clicking on the 'Documentation' link does not work. See the output
> below.
>
> Cheers,
> Dave
>
>
> Casper has a problem
> Sorry! This site is experiencing technical difficulties.
> Try waiting a few minutes and reloading.
> (Can't contact the database server: Access denied for user 'root'@'localhost'
> (using password: YES) (localhost))
>

Re: [casper] casper.berkeley.edu hacked

[Mark Wagner]

Not sure what caused that, but I upgraded Mediawiki and it seems to be
working now.  Let me know if there's anything else.

Mark


On Tue, May 17, 2011 at 12:18 PM, William Mallard  wrote:

> Hi Mark,
>
> Mark Wagner wrote:
> > If anyone has any issues or notices something amiss, please let us
> > know.
>
> When i log in on the wiki, pages that do not start with /wiki/Special:
> are blank. If i log out again, they're fine.
>
> Billy
>

Re: [casper] This Connection is Untrusted

[Mark Wagner]

Hi Tom,

Right now we have a self-signed certificate, hence the warning.  We've
recently requested a verified certificate from the University, so hopefully
we won't have this issue much longer.

Mark


On Tue, May 24, 2011 at 3:30 PM, Tom Kuiper  wrote:

> You have asked Iceweasel to connect securely to casper.berkeley.edu, but
> we can't confirm that your connection is secure.
>
> Because of the hacking incident, I thought I'd better ask about his.  If
> this is not due to an impersonation, how can I get the new certificate?
>
> Regards
>
> Tom
>
> --
> I or me? http://www.oxforddictionaries.com/page/145
>
>
>
>

Re: [casper] git and self-signed certificate

[Mark Wagner]

Hi Sam, Henry,

Sorry about the delay on this.  We've setup the git daemon so you can access
the repositories read only.  For instance,

git clone git://casper,berkeley.edu/git/mlib_devel/bwrc

should work.

Best,
Mark


On Thu, Jun 2, 2011 at 8:39 PM, Samuel Tun  wrote:

> Hi all,
>
> I want to set up my CASPER repository to update via git, but have an
> issue cloning the libraries, well, the BWRC branch. First, in order to
> ignore the self-signed certificate bailout i use
> # env GIT_SSL_NO_VERIFY=true git clone
> https://casper.berkeley.edu/git/mlib_devel/bwrc.git
>
> This ignores the ceritficate, but then I get
>
> Cloning into bwrc...
> error: Unable to find 6996e77bb969865a1ae2dc8067b6072848ff5a93 under
> https://casper.berkeley.edu/git/mlib_devel/bwrc.git
> Cannot obtain needed blob 6996e77bb969865a1ae2dc8067b6072848ff5a93
> while processing commit 00a1431c5a8e1b34fded93994eef9b3acfab6537.
> error: Fetch failed.
>
> I can't find a fix on the internet that fixes my problem, although I
> did find a few threads like
> http://support.github.com/discussions/repos/199-git-repo-missing-a-blob
> where it's not clear to me how to get git to work.
>
> thanks,
> Sam
>
>

Re: [casper] Trouble running tutorial 3

[Mark Wagner]

Hi Ricardo,

Generally what we refer to as the iADC is 1Gsps (or 2 interleaved):
https://casper.berkeley.edu/wiki/ADC2x1000-8

Is this what you're using, or is it our national ADC at 3Gsps?
https://casper.berkeley.edu/wiki/ADC1x3000-8

Have you tried loading the bof file in SVN without making any changes?

https://casper.berkeley.edu/svn/trunk/ref_designs_tutorials/workshop_2010/roach_tut3_wideband_spec/r_spec_2048_r105_2010_Jul_26_1205.bof

If you're using the National board, you'll need to switch out the ADC yellow
block as well.

Mark


On Tue, Jun 21, 2011 at 2:14 PM, Ricardo Finger  wrote:

> Hello All,
>
> I am trying to run the tutorial 3 spectrometer on a ROACH + 1x_3GSPS_iADC.
> I used the bof file provided by casper as well as our own bof file compiled
> here (on ubuntu) using the simulink model from casper after replacing the
> pfb and fft blocks from our 'local' library.
>
> In both cases I got a strange symmetric spectrum (
> http://www.das.uchile.cl/~**rfinger/ROACH/tut3_1.png)
>  which
> doesn't change to much when a test tone is applied.
> The iADC clock was 800MHz, 0dBm, provided by a valontech 5007 synthesizer,
> and the test tone was 100/200 MHz, 0dBm.
>
> After a few integration periods I get a 'timeout' error, and a blank window
> in the spectrometer.py application.
>
> Does anyone got the same problem?
>
> Thanks,
>
> Ricardo.
>
> --
> Ricardo Finger Camus
> Electrical Engineer
> Astronomy Department
> University of Chile
> Of: 56(2)9771119
> Casilla 36-D, Santiago.
> http://www.das.uchile.cl/lab_**mwl/ 
>
>
>

Re: [casper] Roach ethernet problem / damaged board?

[Mark Wagner]

Hi Ryan,

Are you able to connect over serial and access uboot?  If you can boot into
borph, can you see if the roach has and IP and tcpborphserver is running?

Also, you can access the Actel Fusion over the Xport which has information
about temperatures and voltages.  You can get the python script to run it
here:
https://casper.berkeley.edu/wiki/Roach_monitor_and_management_subsystem

Mark


On Wed, Jun 22, 2011 at 4:21 PM, Ryan%20Monroe wrote:

> Hey all,
> I was testing the GPIO pins on the roach with a wire connected to the gpio
> 3.3V line.  The other end of the wire brushed across the board very quickly,
> most likely touching (if anything) the IIC bus or one of the two coax
> ports.  The roach shut down and immediately restarted.
>
> I now receive the following error upon trying to program my roach:
> "KatcpClientError: Client not connected"
>
> Pinging 192.168.0.2 receives no response.
>
>
> Anyone dealt with something like this before?  What would be some good
> first steps towards repairing the roach?
>
> --Ryan Monroe
>

Re: [casper] Trouble running tutorial 3

[Mark Wagner]

Hi Ricardo,

Can you run ctrl-d to update the design which will propagate the data types
and give you a more verbose error in the matlab workspace.

Also, you should be aware that Ubuntu is not a supported OS.

Is there a reason why you're taking the first 4 time samples instead of
every other?

Mark


On Thu, Jun 23, 2011 at 3:23 PM, Ricardo Finger  wrote:

> Hello Mark,
>
> I realised that the ADC yellow block is for the 2x1GSPS ADC while the
> ADC0083000 is the one for the the 3GSPS board I have. That explains
> why the .bof you mentioned and the one I created didnt work, since
> when I replaced the ADC block was to fix a 'library reference'
> problem,and I use the same block of the tutorial.
>
> The question now is that my simulink library does not have a
> 'ADC0083000' block but a 'ADC0083000x2' which I guess can be used with
> a single board too.
>
> I replaced the ADC block by the ADC083000x2 and used the 4 LSBs to
> connect to the PFB block in the tutorial design.
> I terminated the rest of the block connectors and leaved everything
> else unchanged.
> Now I am getting 'error due to multiple causes' when trying to simulate.
>
> To see how I connect the block you can have a look this screenshoot:
>
> http://www.das.uchile.cl/~rfinger/ROACH/tut3_adc83000.png
>
> Am I in the right direction?, or this is not the block to run a single
> 083000 ADC board?
> is there a log to look the multiple causes errors of the simulation to
> start debugging?
>
> Thanks!
>
> Ricardo.
>
>
> On Tue, Jun 21, 2011 at 6:58 PM, Ricardo Finger 
> wrote:
> > Hello Mark,
> >
> > Thanks for your prompt answer.
> > We are using the ADC1x3000-8 in the ZDOK 0.
> > The first thing we did was to run the bof file you mentioned, just
> > after downloaded.
> > I just did it again with the same result:
> >
> > root@roach-laptop:~/Desktop/workspace# ./spectrometer.py 192.168.1.10
> > -b r_spec_2048_r105_2010_Jul_26_1205.bof
> > Connecting to server 192.168.1.10 on port 7147...  ok
> >
> > 
> > Programming FPGA with r_spec_2048_r105_2010_Jul_26_1205.bof... done
> > Configuring accumulation period... done
> > Resetting counters... done
> > Setting digital gain of all channels to 4294967295... done
> >
> > We got the same spectrum I mentioned in my last email and after a
> > while we got error:
> >
> >
> > Exception in Tkinter callback
> > Traceback (most recent call last):
> >  File "/usr/lib/python2.6/lib-tk/Tkinter.py", line 1413, in __call__
> >return self.func(*args)
> >  File "/usr/lib/python2.6/lib-tk/Tkinter.py", line 498, in callit
> >func(*args)
> >  File "./spectrometer.py", line 49, in plot_spectrum
> >acc_n, interleave_a = get_data()
> >  File "./spectrometer.py", line 37, in get_data
> >a_1=struct.unpack('>1024l',fpga.read('odd',1024*4,0))
> >  File
> "/usr/local/lib/python2.6/dist-packages/corr-0.6.5-py2.6.egg/corr/katcp_wrapper.py",
> > line 265, in read
> >str(size))
> >  File
> "/usr/local/lib/python2.6/dist-packages/corr-0.6.5-py2.6.egg/corr/katcp_wrapper.py",
> > line 61, in _request
> >reply, informs = self.blocking_request(request,keepalive=True)
> >  File
> "/usr/local/lib/python2.6/dist-packages/katcp-0.3.4-py2.6.egg/katcp/client.py",
> > line 623, in blocking_request
> >(msg.name, timeout))
> > RuntimeError: Request read timed out after 10 seconds.
> >
> > I am using the normal Ethernet port to connect to the ROACH (not the
> 10GBE).
> > A red led lights up on the roach when I run the script.
> > Also a green light blinks about two times per second.
> > After the script crashes with the 'runtime' error the leds on the
> > roach continue doing the same thing.
> >
> > Ricardo.
> >
> >
> > On Tue, Jun 21, 2011 at 6:24 PM, Mark Wagner 
> wrote:
> >> Hi Ricardo,
> >> Generally what we refer to as the iADC is 1Gsps (or 2 interleaved):
> >> https://casper.berkeley.edu/wiki/ADC2x1000-8
> >> Is this what you're using, or is it our national ADC at 3Gsps?
> >> https://casper.berkeley.edu/wiki/ADC1x3000-8
> >> Have you tried loading the bof file in SVN without making any changes?
> >>
> https://casper.berkeley.edu/svn/trunk/ref_designs_tutorials/workshop_2010/roach_tut3_wideband_spec/r_spec_2048_r105_2010_Jul_26_1205.bof
> >>
> >> If you're using the National board, you'll need to switch out the ADC
>

Re: [casper] Trouble running tutorial 3

[Mark Wagner]

Hi Ricardo,

It looks like the ADC mask script didn't run properly as it should only show
8 ports for ADC 0 when you only have ZDOK 0 selected.  Yours seems to be in
interleaved mode.  I would try deleting the yellow block, replacing it with
your parameters, and updating again.

Not sure, most likely you have the SX95T, otherwise I don't think the .bof
file would have run.

Using the even samples will give you half the bandwidth.

The size of the PFB and the number of simultaneous inputs from the ADC are
independent.

Mark




On Tue, Jun 28, 2011 at 3:11 PM, Ricardo Finger  wrote:

> Hello Mark,
>
> I tried ctrl-d and I got the same errors when I try to simulate.
>
> "Error due to multiple causes." and "Error in
> 'r_spec_2048_r105_b/adc083000x2': Initialization commands cannot be
> evaluated."
>
> There is no reason why I connected the first 4 time samples. I was
> just trying to make it compile with the least possible changes to the
> original design. At this moment I am just trying to go through the
> tutorials with the HW I have: a (sx95?) Roach and 1xADC83000.
>
> Is there a command to know the type of FPGA installed on the roach?
>
> Is it possible to use the ADC083000x2 with just one ADC board
> installed? or there is another block for this purpose?
>
> Should I modify the size of the PFB and FFT to connect all samples of ADC0?
>
> or may I try first to connect every even sample: s0,s2,s4,s6?
> Should the former run as an spectrometer with a quarter of the
> bandwidth of the ADC clock?
>
> Regards,
>
> Ricardo.
>
>
>
>
>
>
>
>
>
> On Thu, Jun 23, 2011 at 6:35 PM, Mark Wagner 
> wrote:
> > Hi Ricardo,
> > Can you run ctrl-d to update the design which will propagate the data
> types
> > and give you a more verbose error in the matlab workspace.
> > Also, you should be aware that Ubuntu is not a supported OS.
> > Is there a reason why you're taking the first 4 time samples instead of
> > every other?
> > Mark
> >
> > On Thu, Jun 23, 2011 at 3:23 PM, Ricardo Finger 
> wrote:
> >>
> >> Hello Mark,
> >>
> >> I realised that the ADC yellow block is for the 2x1GSPS ADC while the
> >> ADC0083000 is the one for the the 3GSPS board I have. That explains
> >> why the .bof you mentioned and the one I created didnt work, since
> >> when I replaced the ADC block was to fix a 'library reference'
> >> problem,and I use the same block of the tutorial.
> >>
> >> The question now is that my simulink library does not have a
> >> 'ADC0083000' block but a 'ADC0083000x2' which I guess can be used with
> >> a single board too.
> >>
> >> I replaced the ADC block by the ADC083000x2 and used the 4 LSBs to
> >> connect to the PFB block in the tutorial design.
> >> I terminated the rest of the block connectors and leaved everything
> >> else unchanged.
> >> Now I am getting 'error due to multiple causes' when trying to simulate.
> >>
> >> To see how I connect the block you can have a look this screenshoot:
> >>
> >> http://www.das.uchile.cl/~rfinger/ROACH/tut3_adc83000.png
> >>
> >> Am I in the right direction?, or this is not the block to run a single
> >> 083000 ADC board?
> >> is there a log to look the multiple causes errors of the simulation to
> >> start debugging?
> >>
> >> Thanks!
> >>
> >> Ricardo.
> >>
> >>
> >> On Tue, Jun 21, 2011 at 6:58 PM, Ricardo Finger 
> >> wrote:
> >> > Hello Mark,
> >> >
> >> > Thanks for your prompt answer.
> >> > We are using the ADC1x3000-8 in the ZDOK 0.
> >> > The first thing we did was to run the bof file you mentioned, just
> >> > after downloaded.
> >> > I just did it again with the same result:
> >> >
> >> > root@roach-laptop:~/Desktop/workspace# ./spectrometer.py 192.168.1.10
> >> > -b r_spec_2048_r105_2010_Jul_26_1205.bof
> >> > Connecting to server 192.168.1.10 on port 7147...  ok
> >> >
> >> > 
> >> > Programming FPGA with r_spec_2048_r105_2010_Jul_26_1205.bof... done
> >> > Configuring accumulation period... done
> >> > Resetting counters... done
> >> > Setting digital gain of all channels to 4294967295... done
> >> >
> >> > We got the same spectrum I mentioned in my last email and after a
> >> > while we got error:
> >> >

Re: [casper] Fwd: trouble compiling tutorial 1

[Mark Wagner]

Hi Louis,

Can you run control-D to update the design?  This will propagate the data
types
and may give you some idea where the issue lies.

Mark


On Fri, Jul 8, 2011 at 9:27 PM, Louis Dartez  wrote:

>
> Hello,
>
>  I've been trying to compile tutorial 1 using the bee_xps
> command on MATLAB. After waiting a while I get a dialogue box titled 'NGC
> Netlisting Error' with the following errors:
>
> [: 21:
> /opt/Xilinx/11.1/ISE/lib/lin64:/opt/Xilinx/11.1/DSP_Tools/lin64/sysgen/lib:
> /usr/local/MATLAB/R2009a/sys/os/glnxa64:/usr/local/MATLAB/R2009a/bin/glnxa64:/usr/local/MATLAB/R2009a/extern/lib/glnxa64:/usr/local/MATLAB/R2009a/sys/java/jre/glnxa64/jre/lib/amd64/native_threads:/usr/local/MATLAB/R2009a/sys/java/jre/glnxa64/jre/lib/amd64:/opt/Xilinx/11.1/ISE/bin/lin64:
> unexpected operator
>
> [: 22:
> /opt/Xilinx/11.1/DSP_Tools/lin64/sysgen/lib:/opt/Xilinx/11.1/ISE/lib/lin64:
> /opt/Xilinx/11.1/DSP_Tools/lin64/sysgen/lib:/usr/local/MATLAB/R2009a/sys/os/glnxa64:/usr/local/MATLAB/R2009a/bin/glnxa64:/usr/local/MATLAB/R2009a/extern/lib/glnxa64:/usr/local/MATLAB/R2009a/sys/java/jre/glnxa64/jre/lib/amd64/native_threads:/usr/local/MATLAB/R2009a/sys/java/jre/glnxa64/jre/lib/amd64/server:/usr/local/MATLAB/R2009a/sys/java/jre/glnxa64/jre/lib/amd64:/opt/Xilinx/11.1/ISE/bin/lin64:
> unexpected operator
>
> In addition to the dialogue box above, I'm getting the following output
> within the MATLAB prompt:
>
> > In
> /opt/Xilinx/11.1/DSP_Tools/lin64/sysgen/bin/xlCompileGenerateMdl.p>xlCompileGenerateMdl
> at 181
>   In
> /opt/Xilinx/11.1/DSP_Tools/lin64/sysgen/bin/xlGenerateButton.p>xlGenerateButton
> at 281
>   In gen_xps_files at 324
>   In bee_xps>run_Callback at 150
>   In bee_xps at 82
> Error using ==> gen_xps_files at 328
> XSG generation failed:
>
> Any Ideas as to what may be behind these errors? Any advice would be
> appreciated.
>
> Thanks,
>
> --
> -- Louis Dartez
> (956) 372-5812
> Arecibo Remote Command Center Scholar
> Center for Gravitational Wave Astronomy
> University of Texas at Brownsville
>

Re: [casper] fitting large numbers into the 10 Gbe

[Mark Wagner]

Hi Sam,

The packetizer block in the CASPER library buffers up data from a vector
accumulator and can send it out in bursts to the 10GbE block with the
appropriate data valid.  It sounds like this may be what you need.

Mark


On Thu, Aug 4, 2011 at 2:55 PM, Samuel Tun  wrote:

> Hello,
>
> I'm wondering if anyone has any examples or suggestions on how to get
> large numbers coming out of vector accumulators into the 10 Gbe block.
> This block takes 64 bits at a time, so I've tried to slice up whatever
> comes out fo the vacc into 64 bit slices, delaying subsequent ones so
> that mux selections lets me capture an entire spectral channel as it
> comes out of vacc. However, cycling through the mux means I miss all
> the channels in between count starts. Regardless, I may be going about
> it the wrong way, so any examples would be greatly appreciated. The
> ones I've seen concatenate up to 64 bits, so do not have this problem.
> If anyone wants to take a look, this is intended for getting out the
> data of a 3 antenna 500 MHz bandwidth correlator for the FASR Subsytem
> Testbed, FST.
>
> http://dl.dropbox.com/u/3531421/test1ghz10Gbe.mdl
>
> Thanks,
> Sam Tun
>
>

Re: [casper] Error: An error encountered whil running XST

[Mark Wagner]

Hi Vikas,

As John said, it's possible that it's a glibc error, but I would recommend
updating the design (CTRL-D) before running bee_xps.  This might give you
more telling errors.

Mark


On Fri, Dec 16, 2011 at 8:12 PM, John Ford  wrote:

> I think you missed some of the messages from the terminal, and I bet that
> the top message says something like
>
> "glibc detected a memory error: freeing memory that is already freed"  or
> some such.
>
> There has recently been an update to glibc on Red Hat that evidently traps
> when it encounters this error.  We saw this on our machine that had had
> patches applied recently.  We rolled back the glibc to an earlier version
> and all's well.
>
> It's a bug in the xilinx program and ought to be fixed, but this was
> quicker for us to fix.
>
> John
>
>
>
> > Hi,
> >
> > I am trying to compile a design on my server but its giving this error -
> >
> > An error encountered while running XST
> >
> > and lines in the terminal window. [See attached text file] .
> > I tried reinstalling Xilinx on the system, but still it give the same
> > error.
> >
> > Had anybody encountered this problem?
> > Is the Xilinx / Matlab got corrupt ?
> > Can somebody tell me the solution to this ?
> > Thanks.
> >
> > -Vikas Asthana.
> >
>
>
>
>

Re: [casper] Short Error Message from "gen_xps_files at 328"

[Mark Wagner]

Hi Ron,

I've tried to compile your design (and my own) and have been having the
same issue.  This seems to have started when our sysadmins performed the
Redhat update and now i'm unable to generate even the simplest designs.

I'll try to roll back one of our machines and see if that helps.   I'll
also be putting in a ticket with Xilinx.

Mark


On Sat, Dec 24, 2011 at 11:43 AM,  wrote:

> I need to check some logs, but I do
> think somebody did some  of the
> CentOS updates that were announced
> "available" by the CentOS system
> updater. I don't see the reference
> to the glibc problem in recent
> CASPER email.
>
> >> A new problem is preventing me from
> >> compiling even simple models with
> >> bee_xps. For example, when I compile
> >> a model containing only the system
> >> generator, XSB Core Config, Xilinx
> >> constants and CASPER software
> >> registers, I receive the following
> >> messages from bee_xps.
> >>
> >> Detected Linux OS
> >> #
> >> ##  System Update  ##
> >> #
> >> #
> >> ## Block objects creation  ##
> >> #
> >> ##
> >> ## Checking objects ##
> >> ##
> >> Running system generator ...
> >> Error using ==> gen_xps_files at 328
> >> XSG generation failed: ?
> >>
> >> I am using Xilinx 11.1 and Matlab
> >> R2009a on CentOS Linux with the
> >> mlib_devel_10_1 library. I was not
> >> having this trouble until recently.
> >> Other people use my computer, but
> >> they know to avoid changing my
> >> installations.
> >>
> >> I attached a simple MDL file that
> >> produces the error messages shown
> >> above. What is causing gen_xps_files
> >> to have trouble at 328?
> >>
> >>
> >
> > Hi Ron.  This sounds strangely like the glibc problem I mentioned last
> > week.  Did any messages from the OS come up in the window you started the
> > matlab session from?
> >
> > You might check to see if anyone updated your glibc lately.
> >
> > I'll try your mdl tomorrow and see what happens.  I don't have access to
> a
> > toolset right now.
> >
> > John
> >
> >
> >
>
>
>
>

Re: [casper] Short Error Message from "gen_xps_files at 328"

[Mark Wagner]

I tried rolling back glibc and that did fix the XST error issue, but other
issues are now surfacing so i've opened a 'Webcase' with Xilinx and will
hopefully hear back from them soon.

Mark


On Sun, Dec 25, 2011 at 7:58 PM, John Ford  wrote:

> > I need to check some logs, but I do
> > think somebody did some  of the
> > CentOS updates that were announced
> > "available" by the CentOS system
> > updater. I don't see the reference
> > to the glibc problem in recent
> > CASPER email.
>
> May mail seems to have bounced that I sent.  In any case, there is a bug
> in xst that double-frees some memory, triggering glibc to throw a memory
> exception and scream and die.  We rolled back our glibc and it fixed the
> problem.  Well, it masks the problem...
>
> Sorry about the lack of info!
>
> John
>
>
> >
> >>> A new problem is preventing me from
> >>> compiling even simple models with
> >>> bee_xps. For example, when I compile
> >>> a model containing only the system
> >>> generator, XSB Core Config, Xilinx
> >>> constants and CASPER software
> >>> registers, I receive the following
> >>> messages from bee_xps.
> >>>
> >>> Detected Linux OS
> >>> #
> >>> ##  System Update  ##
> >>> #
> >>> #
> >>> ## Block objects creation  ##
> >>> #
> >>> ##
> >>> ## Checking objects ##
> >>> ##
> >>> Running system generator ...
> >>> Error using ==> gen_xps_files at 328
> >>> XSG generation failed: ?
> >>>
> >>> I am using Xilinx 11.1 and Matlab
> >>> R2009a on CentOS Linux with the
> >>> mlib_devel_10_1 library. I was not
> >>> having this trouble until recently.
> >>> Other people use my computer, but
> >>> they know to avoid changing my
> >>> installations.
> >>>
> >>> I attached a simple MDL file that
> >>> produces the error messages shown
> >>> above. What is causing gen_xps_files
> >>> to have trouble at 328?
> >>>
> >>>
> >>
> >> Hi Ron.  This sounds strangely like the glibc problem I mentioned last
> >> week.  Did any messages from the OS come up in the window you started
> >> the
> >> matlab session from?
> >>
> >> You might check to see if anyone updated your glibc lately.
> >>
> >> I'll try your mdl tomorrow and see what happens.  I don't have access to
> >> a
> >> toolset right now.
> >>
> >> John
> >>
> >>
> >>
> >
> >
>
>
>
>

Re: [casper] Short Error Message from "gen_xps_files at 328"

[Mark Wagner]

Hi Ron,

I used yum's 'downgrade' command:

$sudo yum downgrade glibc glibc-common

This should downgrade to the next highest version.

Mark


On Mon, Dec 26, 2011 at 4:44 PM,  wrote:

> How do you safely roll back glibc? I
> would like to try your fix but also
> want to avoid breaking any system
> setups. I am using CentOS. Is there
> a way to have Xilinx and Matlab
> software use a rolled-back glibc but
> allow other software to continue
> using the current version?
>
> > I tried rolling back glibc and that did fix the XST error issue, but
> other
> > issues are now surfacing so i've opened a 'Webcase' with Xilinx and will
> > hopefully hear back from them soon.
> >
> > Mark
> >
> >
> > On Sun, Dec 25, 2011 at 7:58 PM, John Ford  wrote:
> >
> >> > I need to check some logs, but I do
> >> > think somebody did some  of the
> >> > CentOS updates that were announced
> >> > "available" by the CentOS system
> >> > updater. I don't see the reference
> >> > to the glibc problem in recent
> >> > CASPER email.
> >>
> >> May mail seems to have bounced that I sent.  In any case, there is a bug
> >> in xst that double-frees some memory, triggering glibc to throw a memory
> >> exception and scream and die.  We rolled back our glibc and it fixed the
> >> problem.  Well, it masks the problem...
> >>
> >> Sorry about the lack of info!
> >>
> >> John
> >>
> >>
> >> >
> >> >>> A new problem is preventing me from
> >> >>> compiling even simple models with
> >> >>> bee_xps. For example, when I compile
> >> >>> a model containing only the system
> >> >>> generator, XSB Core Config, Xilinx
> >> >>> constants and CASPER software
> >> >>> registers, I receive the following
> >> >>> messages from bee_xps.
> >> >>>
> >> >>> Detected Linux OS
> >> >>> #
> >> >>> ##  System Update  ##
> >> >>> #
> >> >>> #
> >> >>> ## Block objects creation  ##
> >> >>> #
> >> >>> ##
> >> >>> ## Checking objects ##
> >> >>> ##
> >> >>> Running system generator ...
> >> >>> Error using ==> gen_xps_files at 328
> >> >>> XSG generation failed: ?
> >> >>>
> >> >>> I am using Xilinx 11.1 and Matlab
> >> >>> R2009a on CentOS Linux with the
> >> >>> mlib_devel_10_1 library. I was not
> >> >>> having this trouble until recently.
> >> >>> Other people use my computer, but
> >> >>> they know to avoid changing my
> >> >>> installations.
> >> >>>
> >> >>> I attached a simple MDL file that
> >> >>> produces the error messages shown
> >> >>> above. What is causing gen_xps_files
> >> >>> to have trouble at 328?
> >> >>>
> >> >>>
> >> >>
> >> >> Hi Ron.  This sounds strangely like the glibc problem I mentioned
> >> last
> >> >> week.  Did any messages from the OS come up in the window you started
> >> >> the
> >> >> matlab session from?
> >> >>
> >> >> You might check to see if anyone updated your glibc lately.
> >> >>
> >> >> I'll try your mdl tomorrow and see what happens.  I don't have access
> >> to
> >> >> a
> >> >> toolset right now.
> >> >>
> >> >> John
> >> >>
> >> >>
> >> >>
> >> >
> >> >
> >>
> >>
> >>
> >>
> >
>
>
>
>

Re: [casper] Casper Tutorial error imformation

[Mark Wagner]

Hi Renjie,

Where did you check out you mlib_devel from?  It seems that the FFTs from
the tutorial you're using are different from the ones in the library you're
opening in Simulink.  The parameters that are being complained about are
additions to the FFTs that have been made to more recent versions of
mlib_devel and should coincide with the tutorials.

That said, to simply get the design to compile, I think the easiest thing
would be to drag in the fft_biplex_real_4x block from your library, make
sure the parameters are effectively the same, and then delete the ones that
are currently in there.

But first you probably want to make sure you have the most recent version
of the 'stable' repository here:

https://github.com/casper-astro/mlib_devel

Mark


2012/2/27 朱人杰 

> **
>
> Dear sir,
>
>I am trying to get familiar with the casper development environment.
>I have successfully compiled the tut1 and tut2.
>When I compile tut4, matlab give me somme errors, it shows:
>
> Error using ==> gen_xps_files at 199
> Error due to multiple causes:
> --> fft_biplex_real_4x block (mask) does not have a parameter named
> 'hardcode_shifts'.
> --> Error in 'poco_wide_10_r314/fft0': Initialization commands cannot be
> evaluated.
> --> fft_biplex_real_4x block (mask) does not have a parameter named
> 'hardcode_shifts'.
> --> Error in 'poco_wide_10_r314/fft1': Initialization commands cannot be
> evaluated.
> --> fft_biplex_real_4x block (mask) does not have a parameter named
> 'hardcode_shifts'.
> --> Error in 'poco_wide_10_r314/fft2': Initialization commands cannot be
> evaluated.
> --> fft_biplex_real_4x block (mask) does not have a parameter named
> 'hardcode_shifts'.
> --> Error in 'poco_wide_10_r314/fft3': Initialization commands cannot be
> evaluated.
> --> adder_tree block (mask) does not have a parameter named 'adder_imp'.
> --> Error in 'poco_wide_10_r314/pfb_fir_real0': Initialization commands
> cannot be evaluated.
> --> adder_tree block (mask) does not have a parameter named 'adder_imp'.
> --> Error in 'poco_wide_10_r314/pfb_fir_real1': Initialization commands
> cannot be evaluated.
> --> adder_tree block (mask) does not have a parameter named 'adder_imp'.
> --> Error in 'poco_wide_10_r314/pfb_fir_real2': Initialization commands
> cannot be evaluated.
> --> adder_tree block (mask) does not have a parameter named 'adder_imp'.
> --> Error in 'poco_wide_10_r314/pfb_fir_real3': Initialization commands
> cannot be evaluated.
>
>   Can you help me about the problem?
>   Thank you very much.
>
>
> Best Regards,
>
> Renjie Zhu
> VLBI Laboratory
> Shanhai Astronomical Obervatory, CAS
> Email: zh...@shao.ac.cn
> Tel  : +86-21-64386191-124/501
> Fax  : +86-21-54257169
> --
>  2012-02-28
>
>

Re: [casper] Tutorial 2 Compilation Problems

[Mark Wagner]

Hi Joe,

Is there any information or errors above this that might be a little more
telling?

Mark

On Thu, May 3, 2012 at 11:37 PM, John Ford  wrote:

> > When I try to compile Tutorial 2b I got the following errors.
> > Rich tried compiling Jason Ray's enhanced Tutorial 2 and got similar
> > platgen errors.
> > Does anyone have any inputs on the possible cause and cure for these
> > errors?
> > Thanks,
>
> What did you name your .mdl file?  You can't have any spaces or capital
> letters in it.
>
> There may have been an earlier error than the one you posted.  We need to
> see the ones that preceeded this one if there were any.
>
> You might also post your .mdl file so we can try it here.
>
> John
>
> > Joe Greenberg
> >
> > NGCBUILD done.
> >
> > Rebuilding cache ...
> > ERROR:EDK:440 - platgen failed with errors!
> > gmake: *** [implementation/system.bmm] Error 2
> > ERROR:EDK - Error while running "gmake -f system.make bits".
> > Return code = 2
> > No changes to be saved in MSS file
> > Saved project XMP file
> > cp: cannot stat `implementation/system.bit': No such file or directory
> > bit file open failed
> > chmod: cannot access `implementation/system.bof': No such file or
> > directory
> > cp: cannot stat `implementation/system.bof': No such file or directory
> >
> > Error using ==> gen_xps_files at 702
> > Programation files generation failed, EDK compilation probably also
> > failed.
> >
>
>
>
>

[casper] simulink issue "no blocks"

[Mark Wagner]

In case someone else runs into this... I just had this issue that after
'loading' all the blocksets into Simulink and selecting them in the
browser, it only showed 'No Blocks'.  I'm not sure of the cause, but it
turns out I simply needed to change the permissions on /tmp/LibraryBrowser
to a+rwx.

Mark

Re: [casper] casper website down?

[Mark Wagner]

Hi Melissa, CC all,

Space Science Lab is having a power outage for the next 2 days so the
website will be down.

Sorry for the late notice.

Mark
On May 29, 2012 5:00 PM, "Soriano, Melissa (335J)" <
melissa.a.sori...@jpl.nasa.gov> wrote:

>  Hi CASPER,
>
>  It looks like the website (casper.berkeley.edu) is down?  I was trying
> to read some documentation.
>
>  Regards,
> Melissa
>

Re: [casper] NFS server + Casper tutorials

[Mark Wagner]

Hi Fabien,

Thanks! This looks really good, and definitely covers issues that might
come up.  Scientific Linux is a variant of Enterprise Linux (RHEL, Suse,
etc.), which many of us use, so I think having instructions for both is
really helpful.  Would you be willing to update the ROACH NFS
guideon the wiki to
reflect what you've done?

Mark


On Sun, Jul 8, 2012 at 8:32 PM, fabien wrote:

> Dear all,
>
> Some months ago I have been installing a NFS server on a computer with
> Scientific Linux, in order to boot a ROACH. Then, I did some Casper's
> tutorials.
>
> I encountered some problems, solved them, and wrote a note about it
> (attached).
> A part of this note (NFS server) is based on the ROACH NFS guide.
>
> I hope it can be useful.
> If you find any mistakes or have any suggestions, please let me know.
>
> Regards,
>
> Fabien
>

Re: [casper] Problem using shared bram/snap blocks for Roach 2

[Mark Wagner]

Hi Nimish,

How are you clocking your design?

Mark


On Sat, Aug 11, 2012 at 6:48 AM, Nimish Sane  wrote:

> Hi all,
>
> I am trying to compile a design with few snap blocks, specifically snap64
> blocks for Roach 2 —  ska-sa software library, Xilinx 11.4 tools, Linux,
> Roach 2, KatADC, 150MHz FPGA clock. The compilation fails with platgen
> errors. I tried compiling a design with just a snap64 block in it. Please
> find the log attached to this email that shows these errors.
>
> I can confirm that the problem is with the shared bram yellow block. I
> have used this block previously. It never had any such problems before. Any
> suggestions?
>
> Thanks,
>
> Nimish
>
>