Re: [casper] QDR vs DDR3 for new board
Aspw On 21 Aug 2014 23:19, Matt Strader mstra...@physics.ucsb.edu wrote: Hi Casperites, We (UCSB and Fermilab) are currently designing a new DAC/ADC board (12bits x 2.0 Gsps ADC, 14bits x 2.5 Gsps DAC) to interface with the ROACH2 for readout of future, larger MKID instruments. The DAC/ADC board will have it's own FPGA and it's own memory. We're currently deciding between adding QDRII+ SRAMs or DDR3 SDRAM chips to the board. My very limited experience with QDR and DDR2 on ROACH1 suggests QDR is simpler to work with (because of the constant latency), but it would take up many more pins on the FPGA for the width of the data they provide. Does anyone have other ideas of why to choose one over the other? If you were to design a board from scratch, which would you choose? Thanks, Matt Strader UCSB Physics oDeptford a ad
[casper] QDR vs DDR3 for new board
Hi Casperites, We (UCSB and Fermilab) are currently designing a new DAC/ADC board (12bits x 2.0 Gsps ADC, 14bits x 2.5 Gsps DAC) to interface with the ROACH2 for readout of future, larger MKID instruments. The DAC/ADC board will have it's own FPGA and it's own memory. We're currently deciding between adding QDRII+ SRAMs or DDR3 SDRAM chips to the board. My very limited experience with QDR and DDR2 on ROACH1 suggests QDR is simpler to work with (because of the constant latency), but it would take up many more pins on the FPGA for the width of the data they provide. Does anyone have other ideas of why to choose one over the other? If you were to design a board from scratch, which would you choose? Thanks, Matt Strader UCSB Physics Dept.
Re: [casper] QDR vs DDR3 for new board
Hi Matt, We're currently deciding between adding QDRII+ SRAMs or DDR3 SDRAM chips to the board. My very limited experience with QDR and DDR2 on ROACH1 suggests QDR is simpler to work with (because of the constant latency), but it would take up many more pins on the FPGA for the width of the data they provide. Does anyone have other ideas of why to choose one over the other? If you were to design a board from scratch, which would you choose? QDRII+ is really expensive compared to DDR3. I'd create an example HDL design for your FPGA, and see if two banks of DDR3 can be used in ping-pong mode to implement what QDRII+ gives you with its separate write/read ports. Two banks of DDR3 will likely be cheaper and and order-of-magnitude denser than QDRII+. If you do not need simultaneous write and read, then DDR3 should be adequate. Keep in mind that you can still over-lap writes and reads if your DDR controller clock rate and its burst performance is faster than the data rate coming from your fabric. Cheers, Dave
Re: [casper] QDR vs DDR3 for new board
hi matt, qdr has excellent bandwidth for doing random accesses, jumping around in memory (eg: it's great for re-ordering data, corner turns, bit reversing, etc). qdr is easier to use - fixed, known latency, does reads and writes simultaneously, but it's more expensive. . if your address access is sequential, the DDR can also give you good bandwidth, but the latency and bandwidth are not predictable (it depends on how much hopping around you do, and refresh cycles). best wishes, dan' On Thu, Aug 21, 2014 at 2:12 PM, Matt Strader mstra...@physics.ucsb.edu wrote: Hi Casperites, We (UCSB and Fermilab) are currently designing a new DAC/ADC board (12bits x 2.0 Gsps ADC, 14bits x 2.5 Gsps DAC) to interface with the ROACH2 for readout of future, larger MKID instruments. The DAC/ADC board will have it's own FPGA and it's own memory. We're currently deciding between adding QDRII+ SRAMs or DDR3 SDRAM chips to the board. My very limited experience with QDR and DDR2 on ROACH1 suggests QDR is simpler to work with (because of the constant latency), but it would take up many more pins on the FPGA for the width of the data they provide. Does anyone have other ideas of why to choose one over the other? If you were to design a board from scratch, which would you choose? Thanks, Matt Strader UCSB Physics Dept.
