[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

2022-12-14 Thread Anton Afanasyev via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc86a878e8995: [RISCV] Add Syntacore SCR1 CPU model (authored 
by dnpetrov-sc, committed by anton-afanasyev).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139302/new/

https://reviews.llvm.org/D139302

Files:
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td

Index: llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
===
--- /dev/null
+++ llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
@@ -0,0 +1,207 @@
+//==- RISCVSchedSyntacoreSCR1.td - Syntacore SCR1 Scheduling Definitions *- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+
+// SCR1: https://github.com/syntacore/scr1
+
+// This model covers SYNTACORE_SCR1_CFG_RV32IMC_MAX configuration (syntacore-scr1-max).
+// SYNTACORE_SCR1_CFG_RV32IC_BASE (syntacore-scr1-base) configuration has essentially
+// same scheduling characteristics.
+
+// SCR1 is single-issue in-order processor
+def SyntacoreSCR1Model : SchedMachineModel {
+  let MicroOpBufferSize = 0;
+  let IssueWidth = 1;
+  let LoadLatency = 2;
+  let MispredictPenalty = 3;
+  let CompleteModel = 0;
+  let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
+ HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
+ HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
+ HasVInstructions];
+}
+
+let SchedModel = SyntacoreSCR1Model in {
+
+let BufferSize = 0 in {
+def SCR1_ALU : ProcResource<1>;
+def SCR1_LSU : ProcResource<1>;
+def SCR1_MUL : ProcResource<1>;
+def SCR1_DIV : ProcResource<1>;
+def SCR1_CFU : ProcResource<1>;
+}
+
+// Branching
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// Integer arithmetic and logic
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// Integer multiplication: single-cycle multiplier in SCR1_CFG_RV32IMC_MAX
+def : WriteRes;
+def : WriteRes;
+
+// Integer division: latency 33, inverse throughput 33
+let Latency = 33, ResourceCycles = [33] in {
+def : WriteRes;
+def : WriteRes;
+}
+
+// Load/store instructions on SCR1 have latency 2 and inverse throughput 2
+// (SCR1_CFG_RV32IMC_MAX includes TCM)
+let Latency = 2, ResourceCycles=[2] in {
+// Memory
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Unsupported = true in {
+// Atomic memory
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// FP load/store
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// FP instructions
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+}
+
+// Others
+def : WriteRes;
+def : WriteRes;
+
+def : InstRW<[WriteIALU], (instrs COPY)>;
+
+//===--===//
+// Bypasses (none)
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

2022-12-13 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

2022-12-13 Thread Dmitrii Petrov via Phabricator via cfe-commits 
dnpetrov-sc updated this revision to Diff 482455.
dnpetrov-sc added a comment.

- Fixes


Repository:
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Files:
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td

Index: llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
===
--- /dev/null
+++ llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
@@ -0,0 +1,207 @@
+//==- RISCVSchedSyntacoreSCR1.td - Syntacore SCR1 Scheduling Definitions *- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+
+// SCR1: https://github.com/syntacore/scr1
+
+// This model covers SYNTACORE_SCR1_CFG_RV32IMC_MAX configuration (syntacore-scr1-max).
+// SYNTACORE_SCR1_CFG_RV32IC_BASE (syntacore-scr1-base) configuration has essentially
+// same scheduling characteristics.
+
+// SCR1 is single-issue in-order processor
+def SyntacoreSCR1Model : SchedMachineModel {
+  let MicroOpBufferSize = 0;
+  let IssueWidth = 1;
+  let LoadLatency = 2;
+  let MispredictPenalty = 3;
+  let CompleteModel = 0;
+  let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
+ HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
+ HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
+ HasVInstructions];
+}
+
+let SchedModel = SyntacoreSCR1Model in {
+
+let BufferSize = 0 in {
+def SCR1_ALU : ProcResource<1>;
+def SCR1_LSU : ProcResource<1>;
+def SCR1_MUL : ProcResource<1>;
+def SCR1_DIV : ProcResource<1>;
+def SCR1_CFU : ProcResource<1>;
+}
+
+// Branching
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// Integer arithmetic and logic
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// Integer multiplication: single-cycle multiplier in SCR1_CFG_RV32IMC_MAX
+def : WriteRes;
+def : WriteRes;
+
+// Integer division: latency 33, inverse throughput 33
+let Latency = 33, ResourceCycles = [33] in {
+def : WriteRes;
+def : WriteRes;
+}
+
+// Load/store instructions on SCR1 have latency 2 and inverse throughput 2
+// (SCR1_CFG_RV32IMC_MAX includes TCM)
+let Latency = 2, ResourceCycles=[2] in {
+// Memory
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Unsupported = true in {
+// Atomic memory
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// FP load/store
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// FP instructions
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+}
+
+// Others
+def : WriteRes;
+def : WriteRes;
+
+def : InstRW<[WriteIALU], (instrs COPY)>;
+
+//===--===//
+// Bypasses (none)
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def :

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

2022-12-13 Thread Dmitrii Petrov via Phabricator via cfe-commits 
dnpetrov-sc updated this revision to Diff 482449.
dnpetrov-sc marked an inline comment as done.
dnpetrov-sc added a comment.

- Added syntacore prefix


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139302/new/

https://reviews.llvm.org/D139302

Files:
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td

Index: llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
===
--- /dev/null
+++ llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
@@ -0,0 +1,207 @@
+//==- RISCVSchedSyntacoreSCR1.td - Syntacore SCR1 Scheduling Definitions *- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+
+// SCR1: https://github.com/syntacore/scr1
+
+// This model covers SYNTACORE_SCR1_CFG_RV32IMC_MAX configuration (syntacore-scr1-max).
+// SYNTACORE_SCR1_CFG_RV32IC_BASE (syntacore-scr1-base) configuration have essentially
+// same scheduling characteristics.
+
+// SCR1 is single-issue in-order processor
+def SyntacoreSCR1Model : SchedMachineModel {
+  let MicroOpBufferSize = 0;
+  let IssueWidth = 1;
+  let LoadLatency = 2;
+  let MispredictPenalty = 3;
+  let CompleteModel = 0;
+  let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
+ HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
+ HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
+ HasVInstructions];
+}
+
+let SchedModel = SyntacoreSCR1Model in {
+
+let BufferSize = 0 in {
+def SCR1_ALU : ProcResource<1>;
+def SCR1_LSU : ProcResource<1>;
+def SCR1_MUL : ProcResource<1>;
+def SCR1_DIV : ProcResource<1>;
+def SCR1_CFU : ProcResource<1>;
+}
+
+// Branching
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// Integer arithmetic and logic
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// Integer multiplication: single-cycle multiplier in SCR1_CFG_RV32IMC_MAX
+def : WriteRes;
+def : WriteRes;
+
+// Integer division: latency 33, inverse throughput 33
+let Latency = 33, ResourceCycles = [33] in {
+def : WriteRes;
+def : WriteRes;
+}
+
+// Load/store instructions on SCR1 have latency 2 and inverse throughput 2
+// (SCR1_CFG_RV32IMC_MAX includes TCM)
+let Latency = 2, ResourceCycles=[2] in {
+// Memory
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Unsupported = true in {
+// Atomic memory
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// FP load/store
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// FP instructions
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+}
+
+// Others
+def : WriteRes;
+def : WriteRes;
+
+def : InstRW<[WriteIALU], (instrs COPY)>;
+
+//===--===//
+// Bypasses (none)
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def :

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

2022-12-08 Thread Anton Afanasyev via Phabricator via cfe-commits 
anton-afanasyev added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVSchedSCR1.td:14
+// This model covers SCR1_CFG_RV32IMC_MAX configuration (scr1-max).
+// SCR1_CFG_RV32EC_MIN (scr1-min) and SCR1_CFG_RV32IC_BASE (scr1-base)
+// configurations have essentially same scheduling characteristics.

`SCR1_CFG_RV32EC_MIN (scr1-min)` -- this should be removed from comment as well 
since patch doesn't cover `scr1-min`


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[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

2022-12-08 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added a comment.

Should the names be prefixed with "syntacore-". I assume there could be an 
SCR2, etc. in the future?


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[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

2022-12-08 Thread Jessica Clarke via Phabricator via cfe-commits 
jrtc27 added inline comments.



Comment at: llvm/include/llvm/Support/RISCVTargetParser.def:22
 PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
+PROC(SCR1_BASE, {"scr1-base"}, FK_NONE, {"rv32ic"})
+PROC(SCR1_MAX, {"scr1-max"}, FK_NONE, {"rv32imc"})

Alphabetise (with the exception of INVALID)?


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[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

2022-12-06 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCV.td:637
+def : ProcessorModel<"scr1-min", SCR1Model,
+ [FeatureRV32E, FeatureStdExtC],
+ [TuneNoDefaultUnroll]>;

dnpetrov-sc wrote:
> craig.topper wrote:
> > Shouldn't this also need Feature32Bit?
> Now, that's somewhat funny. Indeed, RISCVSubtarget has `HasRV32` field, but 
> it is never queried. `IsRV32` predicate in RISCV.td is mapped to 
> `!Subtarget->is64Bit()` in C++ code.
> 
> Code generation for RV32E is not implemented yet, though (and would error out 
> in `RISCVTargetLowering`). I'll drop scr1-min for now.
> 
It is queried from the MC layer using something like 
FeatureBits[RISCV::Feature32Bit].

It’s only there to distinquish mtune CPU names from real CPU names. The mtune 
CPU names don’t have 32Bit or 64Bit and generate an error if they are used with 
-mcpu


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[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

2022-12-06 Thread Dmitrii Petrov via Phabricator via cfe-commits 
dnpetrov-sc updated this revision to Diff 480352.
dnpetrov-sc edited the summary of this revision.
dnpetrov-sc added a comment.

- fixed new line at end-of-file in RISCVSchedSCR1.td;
- dropped scr1-min (RV32E unsupported).


Repository:
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  https://reviews.llvm.org/D139302/new/

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Files:
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSchedSCR1.td

Index: llvm/lib/Target/RISCV/RISCVSchedSCR1.td
===
--- /dev/null
+++ llvm/lib/Target/RISCV/RISCVSchedSCR1.td
@@ -0,0 +1,207 @@
+//==- RISCVSchedSCR1.td - SCR1 Scheduling Definitions *- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+
+// SCR1: https://github.com/syntacore/scr1
+
+// This model covers SCR1_CFG_RV32IMC_MAX configuration (scr1-max).
+// SCR1_CFG_RV32EC_MIN (scr1-min) and SCR1_CFG_RV32IC_BASE (scr1-base)
+// configurations have essentially same scheduling characteristics.
+
+// SCR1 is single-issue in-order processor
+def SCR1Model : SchedMachineModel {
+  let MicroOpBufferSize = 0;
+  let IssueWidth = 1;
+  let LoadLatency = 2;
+  let MispredictPenalty = 3;
+  let CompleteModel = 0;
+  let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
+ HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
+ HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
+ HasVInstructions];
+}
+
+let SchedModel = SCR1Model in {
+
+let BufferSize = 0 in {
+def SCR1_ALU : ProcResource<1>;
+def SCR1_LSU : ProcResource<1>;
+def SCR1_MUL : ProcResource<1>;
+def SCR1_DIV : ProcResource<1>;
+def SCR1_CFU : ProcResource<1>;
+}
+
+// Branching
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// Integer arithmetic and logic
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// Integer multiplication: single-cycle multiplier in SCR1_CFG_RV32IMC_MAX
+def : WriteRes;
+def : WriteRes;
+
+// Integer division: latency 33, inverse throughput 33
+let Latency = 33, ResourceCycles = [33] in {
+def : WriteRes;
+def : WriteRes;
+}
+
+// Load/store instructions on SCR1 have latency 2 and inverse throughput 2
+// (SCR1_CFG_RV32IMC_MAX includes TCM)
+let Latency = 2, ResourceCycles=[2] in {
+// Memory
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Unsupported = true in {
+// Atomic memory
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// FP load/store
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// FP instructions
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+}
+
+// Others
+def : WriteRes;
+def : WriteRes;
+
+def : InstRW<[WriteIALU], (instrs COPY)>;
+
+//===--===//
+// Bypasses (none)
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

2022-12-05 Thread Dmitrii Petrov via Phabricator via cfe-commits 
dnpetrov-sc added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCV.td:637
+def : ProcessorModel<"scr1-min", SCR1Model,
+ [FeatureRV32E, FeatureStdExtC],
+ [TuneNoDefaultUnroll]>;

craig.topper wrote:
> Shouldn't this also need Feature32Bit?
Now, that's somewhat funny. Indeed, RISCVSubtarget has `HasRV32` field, but it 
is never queried. `IsRV32` predicate in RISCV.td is mapped to 
`!Subtarget->is64Bit()` in C++ code.

Code generation for RV32E is not implemented yet, though (and would error out 
in `RISCVTargetLowering`). I'll drop scr1-min for now.



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[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

2022-12-05 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVSchedSCR1.td:208
+}
\ No newline at end of file


Add new line


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[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

2022-12-05 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCV.td:637
+def : ProcessorModel<"scr1-min", SCR1Model,
+ [FeatureRV32E, FeatureStdExtC],
+ [TuneNoDefaultUnroll]>;

Shouldn't this also need Feature32Bit?


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[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

2022-12-05 Thread Dmitrii Petrov via Phabricator via cfe-commits 
dnpetrov-sc created this revision.
dnpetrov-sc added reviewers: craig.topper, anton-afanasyev, asi-sc.
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rbar, asb, hiraditya, arichardson.
Herald added a project: All.
dnpetrov-sc requested review of this revision.
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[RISCV] Add Syntacore SCR1 CPU model

SCR1 is available at https://github.com/syntacore/scr1

'scr1-min' corresponds to SCR1_CFG_RV32EC_MIN,
'scr1-base' corresponds to SCR1_CFG_RV32IC_BASE,
'scr1-max' corresponds to SCR1_CFG_RV32IMC_MAX.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139302

Files:
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSchedSCR1.td

Index: llvm/lib/Target/RISCV/RISCVSchedSCR1.td
===
--- /dev/null
+++ llvm/lib/Target/RISCV/RISCVSchedSCR1.td
@@ -0,0 +1,207 @@
+//==- RISCVSchedSCR1.td - SCR1 Scheduling Definitions *- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+
+// SCR1: https://github.com/syntacore/scr1
+
+// This model covers SCR1_CFG_RV32IMC_MAX configuration (scr1-max).
+// SCR1_CFG_RV32EC_MIN (scr1-min) and SCR1_CFG_RV32IC_BASE (scr1-base)
+// configurations have essentially same scheduling characteristics.
+
+// SCR1 is single-issue in-order processor
+def SCR1Model : SchedMachineModel {
+  let MicroOpBufferSize = 0;
+  let IssueWidth = 1;
+  let LoadLatency = 2;
+  let MispredictPenalty = 3;
+  let CompleteModel = 0;
+  let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
+ HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
+ HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
+ HasVInstructions];
+}
+
+let SchedModel = SCR1Model in {
+
+let BufferSize = 0 in {
+def SCR1_ALU : ProcResource<1>;
+def SCR1_LSU : ProcResource<1>;
+def SCR1_MUL : ProcResource<1>;
+def SCR1_DIV : ProcResource<1>;
+def SCR1_CFU : ProcResource<1>;
+}
+
+// Branching
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// Integer arithmetic and logic
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// Integer multiplication: single-cycle multiplier in SCR1_CFG_RV32IMC_MAX
+def : WriteRes;
+def : WriteRes;
+
+// Integer division: latency 33, inverse throughput 33
+let Latency = 33, ResourceCycles = [33] in {
+def : WriteRes;
+def : WriteRes;
+}
+
+// Load/store instructions on SCR1 have latency 2 and inverse throughput 2
+// (SCR1_CFG_RV32IMC_MAX includes TCM)
+let Latency = 2, ResourceCycles=[2] in {
+// Memory
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Unsupported = true in {
+// Atomic memory
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// FP load/store
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// FP instructions
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+}
+
+// Others
+def : WriteRes;
+def : WriteRes;
+
+def : InstRW<[WriteIALU], (instrs COPY)>;
+
+//===--===//
+// Bypasses (none)
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def : ReadAdvance;
+def :