[PATCH] D154635: [7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer

2023-07-13 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5d18d43f26ad: [7/8][RISCV] Add rounding mode control variant 
for conversion intrinsics… (authored by eopXD).

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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/Sema/SemaChecking.cpp
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfcvt-out-of-range.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfncvt-out-of-range.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwcvt-out-of-range.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll

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[PATCH] D154635: [7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer

2023-07-12 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D154635: [7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer

2023-07-12 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD updated this revision to Diff 539473.
eopXD added a comment.

Change:

- Rebase upon latest main and updated parent revisions


Repository:
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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/Sema/SemaChecking.cpp
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfcvt-out-of-range.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfncvt-out-of-range.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwcvt-out-of-range.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll

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[PATCH] D154635: [7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer

2023-07-10 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll:24
 ; CHECK-NEXT:vfsgnj.vv v8, v9, v8, v0.t
+; CHECK-NEXT:fsrm a0
 ; CHECK-NEXT:ret

This is concerning. This means the `vfcvt.f.x.v` is getting the modified 
rounding mode from `fsrmi a0, 3`. I think its functionally ok due to the inputs 
involved, but it still shouldn't be happening. Is the vfcvt.f.x.v missing its 
FRM implicit dependency for DYN?


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[PATCH] D154635: [7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer

2023-07-07 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD updated this revision to Diff 538016.
eopXD added a comment.

Remove rounding mode variant of vfwcvt.f.x, vfwcvt.f.xu
Add out-of-range semantic check and its corresponding test cases for the 
intrinsics added.


Repository:
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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/Sema/SemaChecking.cpp
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfcvt-out-of-range.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfncvt-out-of-range.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwcvt-out-of-range.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
  llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-costrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
  llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fround-costrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
  llvm/test/CodeGen/RISCV/rvv/round-vp.ll
  llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
  llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll

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[PATCH] D154635: [7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer

2023-07-07 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD updated this revision to Diff 538012.
eopXD marked 3 inline comments as done.
eopXD added a comment.

Remove rounding mode variant of vfwcvt.f.f


Repository:
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Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
  llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-costrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
  llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fround-costrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
  llvm/test/CodeGen/RISCV/rvv/round-vp.ll
  llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
  llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll

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[PATCH] D154635: [7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer

2023-07-06 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:6769
+let hasSideEffects = 0 in {
+defm PseudoVFWCVT_F_XU : VPseudoVWCVTF_V_RM;
+defm PseudoVFWCVT_F_X  : VPseudoVWCVTF_V_RM;

craig.topper wrote:
> These don't need rounding mode. As the spec ssys "A double-width IEEE 
> floating-point value can always represent a single-width integer exactly." 
> Not sure why they had an FRM use before.
> 
> I'm also very unsure why PseudoVFWCVT_RM_F_XU and PseudoVFWCVT_RM_F_X exist.
Fixed by https://reviews.llvm.org/D154653


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[PATCH] D154635: [7/8][RISCV] Add rounding mode control variant for conversion intrinsics between floating-point and integer

2023-07-06 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:6769
+let hasSideEffects = 0 in {
+defm PseudoVFWCVT_F_XU : VPseudoVWCVTF_V_RM;
+defm PseudoVFWCVT_F_X  : VPseudoVWCVTF_V_RM;

These don't need rounding mode. As the spec ssys "A double-width IEEE 
floating-point value can always represent a single-width integer exactly." Not 
sure why they had an FRM use before.

I'm also very unsure why PseudoVFWCVT_RM_F_XU and PseudoVFWCVT_RM_F_X exist.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:6775
 
-defm PseudoVFWCVT_F_F  : VPseudoVWCVTD_V;
+defm PseudoVFWCVT_F_F  : VPseudoVWCVTD_V_RM;
 } // mayRaiseFPException = true

VFWCVT_F_F doesn't need rounding mode.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154635/new/

https://reviews.llvm.org/D154635

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