[coreboot] ITE IT8718F support status
Hi, I just want to verify has anyone tested the ITE IT8718F superio support? Over at: http://www.coreboot.org/Supported_Motherboards all motherboards mentioned are in the unknown status at the moment. I'm currently porting to motherboard with this specific superIO chip. There's nothing particularly stand out from reading the code at src/superio/ite/it8718f though. Kind Regards, Darmawan -= Знания людей принадлежат миру =- [-Human knowledge belongs to the world-] -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] ITE IT8718F support status
On 3/8/15, Kyösti Mälkki kyosti.mal...@gmail.com wrote: On Sun, 2015-03-08 at 20:26 +0700, Darmawan Salihun wrote: Hi, I just want to verify has anyone tested the ITE IT8718F superio support? Over at: http://www.coreboot.org/Supported_Motherboards all motherboards mentioned are in the unknown status at the moment. Hi, key features of this superio were tested around 2010 when the first boards with it got their coreboot port completed. By 2014, when our supported boards wikipage was changed to collect reports of working builds, this small selection of boards had already become obsolete enough so that nobody has bothered to test and report. I see. This is indeed an old development board. I dust it off because it has complete documentation. Therefore, theoretically should be easy enough to work with for Coreboot porting. To have a working superio depends on a couple of external parameters. One is to route all the required IO ranges (including 2e/4e) to LPC bus, second is to confirm superio has 24/48 MHz clock input. In some cases 48MHz clock requires GPIO programming on southbridge. OK. Thanks for the hint ;-) Kind Regards, Darmawan -= Знания людей принадлежат миру =- [-Human knowledge belongs to the world-] -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Intel Q45 chipset support
Hi, I have checked the list of supported chipset and board but it seems that Intel Q45 is not yet in the list. I recall, this chipset is the same family with Intel gm45. Anyway, the specific board I'm going to port into is Gigabyte GA-EQ45M-S2 Rev.1. This board has Intel Q45 northbridge and ICH10(DO) southbridge, SuperIO ITE8720F Questions: 1. Which part of the code that I need to read to add support for this Intel Q45 and i82801J-DO? I've been reading the coreboot/src/northbridge/intel/gm45/ section and coreboot/src/southbridge/intel/i82801ix so far. 2. The SuperIO (ITE 8720F) is also not in the source code it seems. I saw ITE 8721F in there but no ITE 8720F Thanks in advance. Kind Regards, Darmawan -= Знания людей принадлежат миру =- [-Human knowledge belongs to the world-] -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] AMD Geode LX800 - CS5536 with Coreboot v3?
Hi Kyosti, On 1/30/14, Kyösti Mälkki kyosti.mal...@gmail.com wrote: On 01/30/2014 09:41 AM, Darmawan Salihun wrote: Hi all, Is it still possible to use Coreboot v3 for an AMD Geode LX800-CS5536 board? Or do I have to resort to other Coreboot version? You might be very much on your own just with the v3 build environment. I think bachmann/ot200 board is one of the most recent boards with Geode LX + CS5536 and some testing on coreboot v4. OK. I'll have a look at Coreboot v4. Is this where to clone it from: http://review.coreboot.org/coreboot.git ?? I have all the required datasheet and circuit diagram to do the port. The board is a custom board, not from any of the usual motherboard manufacturers. Kind Regards, Darmawan BTW.. Thanks for your excellent articles at InfoSec on the topic of System Address map initialization on PCI. Sure. Nice to hear people benefited from it. Kind Regards, Darmawan -= Знания людей принадлежат миру =- [-Human knowledge belongs to the world-] -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] AMD Geode LX800 - CS5536 with Coreboot v3?
Hi Christian, On 1/30/14, Christian Gmeiner christian.gmei...@gmail.com wrote: Hi ... Is it still possible to use Coreboot v3 for an AMD Geode LX800-CS5536 board? Or do I have to resort to other Coreboot version? You might be very much on your own just with the v3 build environment. I think bachmann/ot200 board is one of the most recent boards with Geode LX + CS5536 and some testing on coreboot v4. I am the maintainer of the bachmann/ot200 mainboard and current git runs well on the device. OK. I'll have a look at Coreboot v4. Is this where to clone it from: http://review.coreboot.org/coreboot.git http://review.coreboot.org/gitweb?p=coreboot.git OK. Thanks a lot. Kind Regards, Darmawan -= Знания людей принадлежат миру =- [-Human knowledge belongs to the world-] -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] AMD Geode LX800 - CS5536 with Coreboot v3?
Hi all, Is it still possible to use Coreboot v3 for an AMD Geode LX800-CS5536 board? Or do I have to resort to other Coreboot version? I have all the required datasheet and circuit diagram to do the port. The board is a custom board, not from any of the usual motherboard manufacturers. Kind Regards, Darmawan -= Знания людей принадлежат миру =- [-Human knowledge belongs to the world-] -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Link at http://www.coreboot.org/Previous_GSoC_Projects
Thanks Marc :-) On 7/13/12, Marc Jones marcj...@gmail.com wrote: On Thu, Jul 12, 2012 at 2:01 PM, Darmawan Salihun darmawan.sali...@gmail.com wrote: Hi guys, The link to: Low Cost Embedded x86 Teaching Tool in the wiki: http://www.coreboot.org/Previous_GSoC_Projects#USB_Option_ROM_for_SeaBIOS Should point to https://sites.google.com/site/pinczakko/low-cost-embedded-x86-teaching-tool-2 The Geocities page has long been gone. I don't have access to edit the page. Thanks, Darmawan -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot Fixed. Thanks, Marc -- http://se-eng.com -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] BIOS Disassembly Ninjutsu PDF (part of giving back to the community)
I'm sorry if this is not really related to Coreboot. I have yet to make active contribution to the project. I have released the PDF version of my BIOS Disassembly Ninjutsu book. Direct link: hxxp://www.4shared.com/office/k6ooEak2/BIOS_Disassembly_Ninjutsu_Unco.html two errata have been found so far: hxxp://bioshacking.blogspot.com/2012/02/bios-disassembly-ninjutsu-uncovered-1st.html The development of the book back then was possible one way or another due to flashrom and of course LinuxBIOS/Coreboot. So, this is one of my way to give back. Feel free to host the book if you want. Anyway, I was looking for feedback actually because I'm not as knowledgeable as you guys here. Kind Regards, Darmawan -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Asus M2V-MX memory init
Hi guys, Does this have something to do with remapping the RAM shadowed by PCI devices to above 4GB? Anyway, I haven't know yet whether Coreboot remaps RAM shadowed by PCI devices. Regards, Darmawan On 2/22/12, Peter Stuge pe...@stuge.se wrote: David Hillman wrote: It looks like I am missing something to properly initialize memory to get correct SPD info. Maybe SMBUS isn't working properly? I think SMBUS is OK and memory init too. Here's the diff between your two logs with some comments, but there may be more relevant stuff than what I see. Next time when posting logs please make sure that they do not wrap. One good way is to send them as attachments, under all circumstances with text/plain mime type. --- m2v_mx-2g 2012-02-22 04:13:21.309138502 +0100 +++ m2v_mx-4g 2012-02-22 04:13:02.663139149 +0100 @@ -1,4 +1,4 @@ -coreboot-4.0-2000-g91be49b-dirty Mon Feb 20 22:44:53 EST 2012 starting... +coreboot-4.0-2000-g91be49b-dirty Wed Feb 15 22:11:37 EST 2012 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings @@ -47,16 +47,21 @@ sdram_set_spd_registers: paramx :000ceee8 Device error Device error -Device error +Enabling dual channel memory Unbuffered 400MHz 400MHz Interleaved -RAM end at 0x0020 kB +RAM end at 0x0040 kB Ram3 IN TEST WAKEUP 800Initializing memory: done Setting variable MTRR 2, base:0MB, range: 2048MB, type WB +Setting variable MTRR 3, base: 2048MB, range: 1024MB, type WB +Setting variable MTRR 4, base: 3072MB, range: 512MB, type WB +Setting variable MTRR 5, base: 3584MB, range: 256MB, type WB +Setting variable MTRR 6, base: 3840MB, range: 128MB, type WB +Setting variable MTRR 7, base: 3968MB, range: 64MB, type WB DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=1d done @@ -68,41 +73,45 @@ TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 done DQS Training:RcvrEn:Pass2: 00 - CTLRMaxDelay=43 + CTLRMaxDelay=34 done DQS SAVE NVRAM: c2000 Writing 113222 of size 4 to nvram pos: 0 -Writing 17161515 of size 4 to nvram pos: 4 +Writing 17151515 of size 4 to nvram pos: 4 Writing 17171615 of size 4 to nvram pos: 8 Writing 15 of size 1 to nvram pos: 12 Writing 202520 of size 4 to nvram pos: 13 -Writing 17171918 of size 4 to nvram pos: 17 -Writing 17191718 of size 4 to nvram pos: 21 +Writing 18171819 of size 4 to nvram pos: 17 +Writing 18181718 of size 4 to nvram pos: 21 Writing 17 of size 1 to nvram pos: 25 -Writing 33 of size 1 to nvram pos: 26 +Writing 32 of size 1 to nvram pos: 26 Writing 0 of size 1 to nvram pos: 27 Writing 0 of size 1 to nvram pos: 28 Writing 0 of size 1 to nvram pos: 29 -Writing 111222 of size 4 to nvram pos: 30 -Writing 0 of size 4 to nvram pos: 34 -Writing 0 of size 4 to nvram pos: 38 -Writing 0 of size 1 to nvram pos: 42 -Writing 0 of size 4 to nvram pos: 43 -Writing 2f2f2f2f of size 4 to nvram pos: 47 -Writing 2f2f2f2f of size 4 to nvram pos: 51 -Writing 0 of size 1 to nvram pos: 55 -Writing 43 of size 1 to nvram pos: 56 +Writing 113222 of size 4 to nvram pos: 30 +Writing 15141615 of size 4 to nvram pos: 34 +Writing 15141515 of size 4 to nvram pos: 38 +Writing 15 of size 1 to nvram pos: 42 +Writing 202520 of size 4 to nvram pos: 43 +Writing 17191818 of size 4 to nvram pos: 47 +Writing 18191716 of size 4 to nvram pos: 51 +Writing 16 of size 1 to nvram pos: 55 +Writing 34 of size 1 to nvram pos: 56 Writing 0 of size 1 to nvram pos: 57 Writing 0 of size 1 to nvram pos: 58 Writing 0 of size 1 to nvram pos: 59 -Writing 741080ab of size 4 to nvram pos: 60 -DQS Training:tsc[00]=5eac6acb -DQS Training:tsc[01]=6087914d -DQS Training:tsc[02]=60879156 -DQS Training:tsc[03]=df309c2e -DQS Training:tsc[04]=f2a194b3 +Writing 7410809b of size 4 to nvram pos: 60 +DQS Training:tsc[00]=8cbdd63c +DQS Training:tsc[01]=8f476e2e +DQS Training:tsc[02]=8f476e37 +DQS Training:tsc[03]=00015b152149 +DQS Training:tsc[04]=00016daed79e Ram4 v_esp=000cef28 testx = 5a5a5a5a @@ -121,7 +130,7 @@ 0x10 Stage: done loading. Jumping to image. -coreboot-4.0-2000-g91be49b-dirty Mon Feb 20 22:44:53 EST 2012 booting... +coreboot-4.0-2000-g91be49b-dirty Wed Feb 15 22:11:37 EST 2012 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 @@ -147,7 +156,7 @@ PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 -PCI: 00:12.0: enabled 0 +PCI: 00:12.0: enabled 1 Why is 12.0 enabled with 4G? What is 12.0? PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:18.1: enabled 1 @@ -177,7 +186,7 @@ PNP: 002e.8: enabled 0
Re: [coreboot] porting Coreboot to a new motherboard....
Hi Ron, I've been looking for DDR-SDRAM start-up tutorial. Is there any on the web outside of the JEDEC specs? Anyway, where are the codes located in the Coreboot source ? is it on the motherboard-specific codes? TIA, Darmawan On 2/15/12, ron minnich rminn...@gmail.com wrote: reading your note leads me to believe you are not familiar with how sdram startup works. It's a lot more than just setting one register. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] porting Coreboot to a new motherboard....
Well, sorry about the noise. I forgot to mention that most of the RAM init I found was in the raminit.c of each of the northbridge. Is there any other important file(s) that I missed? Thanks, Darmawan On 2/20/12, Darmawan Salihun darmawan.sali...@gmail.com wrote: Hi Ron, I've been looking for DDR-SDRAM start-up tutorial. Is there any on the web outside of the JEDEC specs? Anyway, where are the codes located in the Coreboot source ? is it on the motherboard-specific codes? TIA, Darmawan On 2/15/12, ron minnich rminn...@gmail.com wrote: reading your note leads me to believe you are not familiar with how sdram startup works. It's a lot more than just setting one register. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- -= Human knowledge belongs to the world =- -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] porting Coreboot to a new motherboard....
Thanks Ron. I'm looking into it. On 2/20/12, ron minnich rminn...@gmail.com wrote: you commented out a number of calls to critical functions. You can't just simply set a register and assume it all works. Maybe I misunderstood. I think stepan's i945 code is a great example of how to turn on dram. Or you can look at sdram_enable in the lx440 code for the basic sdram startup cycle. Don't look at the reset of that code, I am not sure it was ever tested on real hardware, there's a comment in there about qemu I don't understand. The lx440 was the second (or first) linuxbios mainboard, but that's not my code, so I'm just not sure about it. ron -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] PCI Option ROM debugging with Coreboot+SeaBIOS (detailed steps)
I made a blogpost detailing the steps to debug PCI Option ROM with Coreboot+SeaBIOS and a GDB-server-compatible debugger: http://bioshacking.blogspot.com/search/label/PCI%20Option%20ROM Hopefully would help those in need because it takes quite a while to get it right. Thanks to Kevin O'Connor for the helps :-) Regards, Darmawan -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] AMD Hudson FCH datasheet
Hi everyone, I'm looking for AMD Hudson datasheet. I've looked at the links in the Coreboot datasheet section but only AMD Family 14h links exists. Has the Hudson FCH datasheet made public? Thanks, Darmawan -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Testing PCI Option/Expansion ROM in SeaBIOS
Hi Guys, Does enabling CONFIG_PCI_ROM_RUN in SeaBIOS is enough to test a PCI expansion ROM ? I have a PCI Expansion ROM to test with SeaBIOS (running in QEMU). TIA, Darmawan -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] IDE interface support code for AMDLX800-CS5536
Hi Mark, On 1/5/11, Marc Jones marcj...@gmail.com wrote: On Sat, Jan 1, 2011 at 1:38 PM, Darmawan Salihun darmawan.sali...@gmail.com wrote: On 1/2/11, Darmawan Salihun darmawan.sali...@gmail.com wrote: Hi guys, I'm looking for the support code for the IDE controller in CS5536 southbridge. I checked-out Coreboot source code but only saw Flash interface support in there. I saw the IDE controller is switched to Flash interface support with the DEADBEEF magic number. The board I'm working with right now use the primary IDE channel for both HDD connectors and a CF connectors. I need to know how to initialize the chipset correctly for this setup. The CF connector is the primary master and the HDD connector is primary slave. I've checked with lspci and cat /proc/ioports and I found that the legacy I/O ports for IDE controller is working just fine. Also, the I/O ports for IDE bus mastering (SFF-8038i) registers are allocated correctly. I mean with the current code that I tested the I/O ports allocation is just fine. Thanks, Darmawan Hi Darmawan, The IDE should get setup by default if the flash switch path is not selected. I assume you have already read the registers in the databook.. http://support.amd.com/us/Embedded_TechDocs/33238G_cs5536_db.pdf Yes, I've been reading it several times over ;-). I have pin point the problem to be in setting the appropriate ATA mode for the attached drives. The motherboard I'm working with has a CF interface in the primary master. While the primary slave is a 44-pin IDE connector (currently connected to an 80GB HDD). I booted FreeBSD 8.0 installation disk in full debug (via USB DVD), but it failed when it tried to set the drive controller mode via SET FEATURE (ATA command). This renders the CF _and_ the HDD unusable. I also booted to backtrack 3 i386 Linux, but it also failed even earlier (via USB DVD), when it tried to check for drive presence via IDENTIFY (ATA command). I'm confused as to: What are the acceptable values for the IDE_DTC, IDE_CAST and IDE_ETC registers? I mean values which would enable the OS to use mass storage device(s) on the IDE primary channel. There may be more information on the embedded developer site. The embedded guys are coreboot friendly, so they should be able to point at the appropriate doc. http://wwwd.amd.com/amd/devsite.nsf/home/welcome.htm?opendocumentlogin I see. On to the site. Thanks, Darmawan -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] IDE interface support code for AMDLX800-CS5536
Hi guys, I'm looking for the support code for the IDE controller in CS5536 southbridge. I checked-out Coreboot source code but only saw Flash interface support in there. I saw the IDE controller is switched to Flash interface support with the DEADBEEF magic number. The board I'm working with right now use the primary IDE channel for both HDD connectors and a CF connectors. I need to know how to initialize the chipset correctly for this setup. The CF connector is the primary master and the HDD connector is primary slave. I've checked with lspci and cat /proc/ioports and I found that the legacy I/O ports for IDE controller is working just fine. Also, the I/O ports for IDE bus mastering (SFF-8038i) registers are allocated correctly. Thanks, Darmawan -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] IDE interface support code for AMDLX800-CS5536
On 1/2/11, Darmawan Salihun darmawan.sali...@gmail.com wrote: Hi guys, I'm looking for the support code for the IDE controller in CS5536 southbridge. I checked-out Coreboot source code but only saw Flash interface support in there. I saw the IDE controller is switched to Flash interface support with the DEADBEEF magic number. The board I'm working with right now use the primary IDE channel for both HDD connectors and a CF connectors. I need to know how to initialize the chipset correctly for this setup. The CF connector is the primary master and the HDD connector is primary slave. I've checked with lspci and cat /proc/ioports and I found that the legacy I/O ports for IDE controller is working just fine. Also, the I/O ports for IDE bus mastering (SFF-8038i) registers are allocated correctly. I mean with the current code that I tested the I/O ports allocation is just fine. Thanks, Darmawan -- -= Human knowledge belongs to the world =- -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] IDE and Compact Flash handling in AMD Geode LX800 and CS5536
Hi, The CF is the primary master and the IDE interface is the primare slave. I've tried to enable the PATA MSR but lspci -vvv displays the IDE controller as [disabled] (base at 1f0h and 170h in memory space). Is there any register in the pci-to-isa bridge that I should reprogram? Thanks, Darmawan On 10 Dec 2010 16:17, Darmawan Salihun darmawan.sali...@gmail.com wrote: Hello, Unfortunately, the board is a custom-build board. I'm currently waiting for information from the board vendor. Yes, I've tried using only the PATA interface (there's a PATA connector on the board). With the stock BIOS (AMI), devices on the PATA could be detected but couldn't be written into, MBR loading occasionally failed as well. I'm still on the process of porting coreboot to this particular board. As for the cs5536_pata.msr=1, haven't try that one. I'll test ASAP. Thanks for the hints. -Darmawan On 12/10/10, Peter Stuge pe...@stuge.se wrote: Darmawan Salihun wrote: There's a CF interf... -- -= Human knowledge belongs ... -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] IDE and Compact Flash handling in AMD Geode LX800 and CS5536
Hi, I'm working on an AMD LX800-CS5536 board. The IRQ is now working properly. However, it's impossible to install an operating system through the IDE interface or the Compact Flash (CF) interface. Booting to the OS installation works just fine (Ubuntu Hardy Heron Linux and FreeBSD 8.0 and 8.1). However, when the OS arrived at the HDD partitioning. it always failed. There's a CF interface and an IDE interface on the board. My question is: how those interfaces usually connected to CS5536 southbridge? Are they multiplexed? Thanks in advance, Darmawan -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] IDE and Compact Flash handling in AMD Geode LX800 and CS5536
Hello, Unfortunately, the board is a custom-build board. I'm currently waiting for information from the board vendor. Yes, I've tried using only the PATA interface (there's a PATA connector on the board). With the stock BIOS (AMI), devices on the PATA could be detected but couldn't be written into, MBR loading occasionally failed as well. I'm still on the process of porting coreboot to this particular board. As for the cs5536_pata.msr=1, haven't try that one. I'll test ASAP. Thanks for the hints. -Darmawan On 12/10/10, Peter Stuge pe...@stuge.se wrote: Darmawan Salihun wrote: There's a CF interface and an IDE interface on the board. My question is: how those interfaces usually connected to CS5536 southbridge? How can we know what that board does? You have to ask the board vendor. If you also mention what board it is here, then maybe someone here can help. Did you try e.g. using only the PATA interface, maybe with a CF2IDE adapter? Did you make sure to use the cs5536_pata driver and set cs5536_pata.msr=1 on the kernel command line? //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Chipset VIA Apollo Pro+?
I have the datasheet of this chipset. I'll send it to you later. I was one working with legacy BIOS on moatherboard with this chipset. -Darmawan On 8/27/10, Mats Erik Andersson mats.anders...@gisladisker.se wrote: Hello, is there now, or has there been, someone interested in the legacy chipset VIA Apollo Pro+? In the sense of investigating its use with Coreboot. The northbridge is VIA VT82C693, and the southbridge is VIA VT82C596A on a mainboard from ECS: PCI-bridge VT82C691, AGP-bridge VT82C598, ISA-bridge VT82C596A, IDE-interface VT82C571, USB-controller VT82C572, and Power-ctrl VT82C596. A search for datasheets has given nothing but trivial information. Regards, Mats Erik Andersson, fil. dr -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Winflashrom plans
Hello guys, Sorry, I haven't been able to update Winflashrom for more than 3 years now. I'm planning to add Windows 7 support next month. Therefore, I'm looking for suggestions. A bit of Winflashrom background of the currently available Winflashrom (at flashrom.org): The programming model: a. User mode application: - Mostly pure flashrom source code recompiled with MinGW. - libpci recompiled with MinGW (for PCI access logic). This is required because the PCI access functions in the Windows API is not guaranteed (marked as obsolete), in Windows XP SP2 and Windows 2003 server back then. b. Device driver: - Provides POSIX mmap() implementation in the kernel, i.e. provides an entrypoint for mmap() function to user mode application. - Provides direct I/O port access for libpci. Well, the reason for these programming model is to reduce the burden when moving to newer flash chip support because this programming model preserves the POSIX API in the user mode application (the device driver is generic enough). Therefore, only the user mode application need to be recompiled to support new flash chip. Any suggestions on what to change from the current programming model? Thanks, Darmawan -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Fwd: SIS630ET coreboot challenge
-- Forwarded message -- From: Darmawan Salihun darmawan.sali...@gmail.com Date: Mon, 7 Jun 2010 20:00:08 +0700 Subject: Re: [coreboot] SIS630ET coreboot challenge To: Tiago Marques tiago...@gmail.com I've sent a datasheet in my posession to Keith. Haven't heard back from him yet. Hopefully he can make use of it :-) On 6/6/10, Tiago Marques tiago...@gmail.com wrote: Me? I wasn't after that. Best regards On Sat, Jun 5, 2010 at 9:32 AM, Stefan Reinauer stefan.reina...@coresystems.de wrote: On 6/5/10 5:15 AM, Tiago Marques wrote: See the attachment, doesn't look like something from a company that's alive and kicking. I know them since the SiS 730. Last time I heard they had some design win for a Core 2 chipset that I haven't seen in any product and started selling SiS branded SO-DIMMS :| So you did contact them for data sheets? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- -= Human knowledge belongs to the world =- -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] password
I'm not sure if this will work and it's risky as well, but you might want to try it out: In most BIOS, shorting the address pins (or the equivalent of that act) upon boot will force the machine to boot from the bootblock BIOS. The bootblock routine usually searches for BIOS binary file to flash, because the assumption is the system BIOS a.k.a main BIOS module is corrupt and need replacement. I'm not sure how to provide this new BIOS binary file replacement for your case. However, most BIOS requires boot floppy (in recent days FAT16 formatted USB sticks) which contains an autoexec.bat file with the routine to flash the new BIOS binary and the BIOS binary file itself. On 4/9/10, Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net wrote: On 08.04.2010 20:45, ron minnich wrote: I have a lenovo x300 somebody set the password on and ... as you guess, forgot. BIOS password or boot password? So, question: anyone have any idea how deep into the machine the password is kept no new machines? Deep in TPM? in other words, were flashrom to work on this box, can the password be reset? It depends. I know that you can reset the password with flashrom on HP machines (got a success report about that a few weeks ago). Not sure about Lenovo. You can store a password (or a hash of it) in flash or NVRAM or a small SPI EEPROM or an I2C EEPROM or even the TPM or any combination thereof. How much time/money are you willing to invest? - The easiest and probably most expensive way (could be a few hundred dollars) is to send the laptop with a proof of ownership to Lenovo to have it unlocked. - A risky and fast (if you can recover from a misflashed ROM) way is to simply flash a new ROM image which is pretty much guaranteed to have no builtin protection, but it won't help at all if the protection is not dependent on flash contents. Messing with nvramtool might have other effects, but hey, you can try that as well. - If you have a good logic analyzer, you can watch the traffic to the TPM, NVRAM, flash, and all other EEPROMs around the time you enter the password. If you find a good way to get the password removed, there's always the option of selling that knowledge to non-Lenovo repair shops. Good luck! Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] How coreboot passes e820-style system memory map to the OS?
Hi, I wonder how coreboot passes the e820-style system memory map to the OS. I found the following data structure pointer in the coreboot source code: static struct parameters *faked_real_mode = (void *)REAL_MODE_DATA_LOC; and also this line: void append_command_line(struct parameters *real_mode, char *arg, int arg_bytes) Does the second line above means faked_real_mode is passed as an argument to the bootloader (or probably directly as kernel parameter for Linux)? Or does SeaBIOS perform the necessary e820-style function to OS other than Linux? Thanks, Darmawan -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] How coreboot passes e820-style system memory map to the OS?
Thanks, all clear now :) On 3/26/10, Stefan Reinauer ste...@coresystems.de wrote: On 3/25/10 5:39 PM, Darmawan Salihun wrote: Hi, I wonder how coreboot passes the e820-style system memory map to the OS. With SeaBIOS, the OS or bootloader just calls an e820 int call. With FILO or Grub2 the linux kernel takes a parameter structure that is filled with the memory map, kernel command line and other information. Stefan -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] How come it's so slow?
I think every UEFI/EFI implementation will boot to old school boot mode when it can't find any EFI/UEFI-compliant boot-device/boot-partition. It would take too long though but at least the fallback is there. -Darmawan On 3/9/10, Ed Swierk eswi...@aristanetworks.com wrote: On Fri, Mar 5, 2010 at 8:58 AM, ron minnich rminn...@gmail.com wrote: Just got a new nehalem box in for test yesterday. Experiences so far: 1. POST from power-on takes 45 seconds. *45 SECONDS*. Now, I had it said to me at SCALE7x last year from someone from Intel that all new BIOSes on Intel chips are really EFI underneath -- is this indicative of what we are to expect? If so, it's awful. It's 15 times slower than what we had ten years ago, and 50 times slower than what we can do today on coreboot. As far as I can tell the sole purpose of EFI is to make it easier for hardware vendors to shovel more junk into the BIOS by removing the hurdle of hand-coding 16-bit assembly. But while EFI might accelerate the trend, it's not the only villain. Someone noticed a 9x growth in boot time on qemu recently (http://lists.gnu.org/archive/html/qemu-devel/2010-03/msg00546.html ). Even on a virtual platform with no actual hardware to initialize, boot time will grow unless someone is actively pushing the other way. Ultimately the system board vendors are responsible for the BIOS in the boards we buy. They are the ones cutting deals with Intel and AMI and Phoenix, and can exert the necessary leverage. But they won't, until they see 1-second cold boot as a feature that will sell more boards. --Ed -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] How come it's so slow?
On 3/9/10, Ed Swierk eswi...@aristanetworks.com wrote: On Fri, Mar 5, 2010 at 8:58 AM, ron minnich rminn...@gmail.com wrote: Just got a new nehalem box in for test yesterday. Experiences so far: 1. POST from power-on takes 45 seconds. *45 SECONDS*. Now, I had it said to me at SCALE7x last year from someone from Intel that all new BIOSes on Intel chips are really EFI underneath -- is this indicative of what we are to expect? If so, it's awful. It's 15 times slower than what we had ten years ago, and 50 times slower than what we can do today on coreboot. As far as I can tell the sole purpose of EFI is to make it easier for hardware vendors to shovel more junk into the BIOS by removing the hurdle of hand-coding 16-bit assembly. But while EFI might accelerate the trend, it's not the only villain. Someone noticed a 9x growth in boot time on qemu recently (http://lists.gnu.org/archive/html/qemu-devel/2010-03/msg00546.html ). Even on a virtual platform with no actual hardware to initialize, boot time will grow unless someone is actively pushing the other way. Ultimately the system board vendors are responsible for the BIOS in the boards we buy. They are the ones cutting deals with Intel and AMI and Phoenix, and can exert the necessary leverage. But they won't, until they see 1-second cold boot as a feature that will sell more boards. --Ed Sorry about the double post. Something went wrong with my mail client. Anyway, perhaps these articles by vid is a nice addition: http://x86asm.net/articles/introduction-to-uefi/index.html http://x86asm.net/articles/uefi-programming-first-steps/index.html -Darmawan -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] GSoC 2010
Flashrom used to have Windows port that I worked on back in 2007 (Winflashrom). I'm willing to help if any student want to port to Windows 7. I'm not a student anymore ;-) Regards, Darmawan On 3/5/10, Marc Jones marcj...@gmail.com wrote: On Thu, Mar 4, 2010 at 8:55 AM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net wrote: Hi, Google Summer of Code 2010 is approaching quickly. I hope coreboot/flashrom are going to participate again, and to do that, we have to apply between 2010-03-08 and 2010-03-12 (March 8 - March 12). Do we want to participate? Who is willing to mentor? Any developers who want to apply as students? Who will serve as organization administrator? Are there any good ideas for GSoC (coreboot or flashrom)? I would like for coreboot to do GSoC again. I think it is great exposure for the project and I would be happy to be a mentor again. I'll put some thought into what prospective students might work on. Marc -- http://se-eng.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] The default value of TOM (MSRC001_001A) just after Power-On
Hi Mark, Thanks. I'll have a look. -Darmawan On 1/22/10, Marc Jones marcj...@gmail.com wrote: On Wed, Jan 20, 2010 at 2:13 AM, Darmawan Salihun darmawan.sali...@gmail.com wrote: The default value of MSRC001_001A (Top of Memory below the 4GB limit) according to BKDG for AMD Fam 10h rev. 3.06 is undefined (after Reset/power-on). However, AMD64 Architecture Programmer's Manual Volume 2: System Programming Rev. 3.14 states that the value of MSRC001_001A after Reset or power on is: __0400_h Which one of this information is correct? I need to know it because I want to know what is the default MMIO range after reset. Hi Darmawan, I think that the BKDG is correct. I get 000_0001F_7780_ on a K8. You can take a look at cpu/amd/car/cache_as_ram.inc for the initial setup. Marc -- http://se-eng.com -- Regards, Darmawan Salihun -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] The default value of TOM (MSRC001_001A) just after Power-On
The default value of MSRC001_001A (Top of Memory below the 4GB limit) according to BKDG for AMD Fam 10h rev. 3.06 is undefined (after Reset/power-on). However, AMD64 Architecture Programmer's Manual Volume 2: System Programming Rev. 3.14 states that the value of MSRC001_001A after Reset or power on is: __0400_h Which one of this information is correct? I need to know it because I want to know what is the default MMIO range after reset. Thanks. -- Regards, Darmawan Salihun -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot for AMD 780G
that's pretty quick. Looking forward to it. Thanks :-) On 12/9/09, Bao, Zheng zheng@amd.com wrote: Now the code is being reviewed by the law department to make sure there isn't anything breaking the rules. Zheng -Original Message- From: coreboot-bounces+zheng.bao=amd@coreboot.org [mailto:coreboot-bounces+zheng.bao=amd@coreboot.org] On Behalf Of Goderic Sent: Wednesday, December 09, 2009 6:14 AM To: coreboot@coreboot.org Subject: [coreboot] Coreboot for AMD 780G Hello, This summer AMD released the documentation for SB700/SB710/SB750 and RS780. I was very excited about that, I have and AMD 780G board and I'd realy like to use coreboot. But I didn't hear anymore about it so I wonder how the work on is going. Thanks, -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- Regards, Darmawan Salihun -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Looking for AMD AGESA GPL-ed source code
Yes, the ported AGESA code is even more convenient for me because the abstraction is quite higher than asm code. Should be easier to understand. Thanks :). On 11/19/09, Bao, Zheng zheng@amd.com wrote: Currently the ported AGESA is mostly about HT link and memory controller. They are located in src/northbridge/amd/amdht and amdmct. I believe that would give you enough information. Zheng -Original Message- From: coreboot-bounces+zheng.bao=amd@coreboot.org [mailto:coreboot-bounces+zheng.bao=amd@coreboot.org] On Behalf Of Marc Jones Sent: Thursday, November 19, 2009 5:10 AM To: Stefan Reinauer Cc: darmawan.sali...@gmail.com; Tom Sylla; coreboot@coreboot.org Subject: Re: [coreboot] Looking for AMD AGESA GPL-ed source code On Wed, Nov 18, 2009 at 11:33 AM, Stefan Reinauer ste...@coresystems.de wrote: On 11/18/09 6:21 PM, Tom Sylla wrote: Sorry, I don't understand this mail. AMD VSA is for Geode PCI configuration space emulation and AGESA is for FamF and Fam10 initialization. They are unrelated. Oh! ... You are right, completely my fault. I confused the funny abbreviations. There is GPLed VSA but there never was and probably never will be GPLed AGESA. AMD planned to do this in 2006, but changed minds later again. Correct, it wasn't released as AGESA, but the coreboot code for fam10 is a port of AGESA. At the time, AGESA was mostly asm and didn't fit exactly into coreboot. Marc -- http://marcjonesconsulting.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- Regards, Darmawan Salihun -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Looking for AMD AGESA GPL-ed source code
Hello, OK. Thanks. On 11/18/09, Bao, Zheng zheng@amd.com wrote: Actually, most part of the agesa code has already been ported to coreboot. You can just look into the coreboot to get what you want. Zheng -Original Message- From: coreboot-bounces+zheng.bao=amd@coreboot.org [mailto:coreboot-bounces+zheng.bao=amd@coreboot.org] On Behalf Of Darmawan Salihun Sent: Wednesday, November 18, 2009 2:51 PM To: coreboot@coreboot.org Subject: [coreboot] Looking for AMD AGESA GPL-ed source code Hello all, Sorry if this sounds like a rather stupid question. Is the GPL-ed AGESA source code already becomes part of the coreboot svn? or I have to download it somewhere else? Thanks. -- Regards, Darmawan Salihun -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- Regards, Darmawan Salihun -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Looking for AMD AGESA GPL-ed source code
OK. Thanks for the links. On 11/18/09, Stefan Reinauer ste...@coresystems.de wrote: On 11/18/09 7:50 AM, Darmawan Salihun wrote: Hello all, Sorry if this sounds like a rather stupid question. Is the GPL-ed AGESA source code already becomes part of the coreboot svn? or I have to download it somewhere else? Thanks. svn://coreboot.org/vsa Additionally there's OpenVSA which compiles with a GNU toolchain but does not work completely, yet: svn://coreboot.org/openvsa Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- Regards, Darmawan Salihun -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Looking for AMD AGESA GPL-ed source code
Hello all, Sorry if this sounds like a rather stupid question. Is the GPL-ed AGESA source code already becomes part of the coreboot svn? or I have to download it somewhere else? Thanks. -- Regards, Darmawan Salihun -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] BIOS RAM in AMD SB7XX southbridges ?
What is the BIOS RAM in AMD SB7XX used for? Is it to buffer the BIOS contents from SPI flash chip prior to execution of the very first instruction? I recall that it's impossible to execute code directly in an SPI chip. or am I missing something? -- Regards, Darmawan Salihun -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] ECS AMD690GM-M2 AM2 AMD 690G Micro ATX AMD Motherboard
On Mon, Oct 13, 2008 at 5:17 AM, Peter Stuge [EMAIL PROTECTED] wrote: ron minnich wrote: I'm still puzzled as to what's going on with the dbm690t serial but it doesn't work with any combination of things I normally do to get rs232 to work. So it goes. Set bit 6 in PCI register 44h of device 20, f3 (1002:438d) and it might come alive. The SB600 LPC ISA bridge doesn't decode any io by default. See page 252 and forward in document 46155. (SB600 RRG) //Peter I got this board at home as well. This is Coreboot v3, right? Too bad it's used as an svn server now. I got to replace it with other board ASAP :-(. Anyway, how to set the baudrate? -- Kind Regards, Darmawan Salihun -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] AMD690GM-M2
Hello, On Thu, Oct 9, 2008 at 9:13 AM, Josh [EMAIL PROTECTED] wrote: Hi Uwe! On Tue, 07 Oct 2008, Uwe Hermann wrote: On Tue, Oct 07, 2008 at 02:44:32AM -0400, Josh wrote: ... I think there _is_ a serial port, see below. Doh, you're right. I thought it was supposed to have a serial port, but didn't think of looking for the header on the board. The board didn't come with a connector cable, but at least that's cheap to buy. ... Good, the chip is supported by flashrom. I'm having troubling finding a place to buy a W39V040B chip in the US. Looks like avnet.com is a good place to buy an alternative chip, but I can't to find any information on how to pick a chip that is compatible. What criteria do I need to look at when picking out a different chip. While I'm at it, I'd like to go with a bigger chip unless there is a reason not to. You need a chip with the same capacity and same electrical characteristics, i.e. __access time and voltage level__. You can look for this information in the W39V040B datasheet. I think Winbond also provides a cross-reference documentation that list the compatibilities of their flash ROMs with flash ROM produced by other manufacturers. I'm not sure if SB600 can decode the R/W access to Flash ROM bigger than your current flash ROM. Maybe others can clarify? superiotool r3511 Found ITE IT8726F (id=0x8726, rev=0x1) at 0x2e No dump available for this Super I/O Nice, first board with ITE IT8726F we've seen so far. Adding support for this Super I/O should be trivial, there's a datasheet and it's similar to most other ITE ones, of course. The Super I/O itself _does_ support serial though. And, luckily, the website says there's a serial header _on_ the board (no serial port per se, but you can attach one there). The board should come with a serial connector cable, I guess. The header is right below the PCI slots. I think we can make this work, but we'll need your help. cool. Next step would be to get a second ROM chip, so that you can make a backup of your BIOS using flashrom, and a PLCC extractor (optional). If you're sure you have a backup chip stored somewhere safe, the fun can begin :) We might need some more info, e.g. the output of 'getpir' (a file called irq_table.c) and 'mptable' output. Later, also 'superiotool -dV' but we need to add IT8726F support to superiotool first... It didn't look too difficult, so I'm in the process of adding dump support for IT8726F. At first glance it seemed pretty similar to IT8718F. If I have any questions, I'll let you know. Thanks, Josh -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- Regards, Darmawan Salihun -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] flashrom and list of computers
On Sat, Jun 7, 2008 at 2:08 AM, Stefan Reinauer [EMAIL PROTECTED] wrote: Carl-Daniel Hailfinger wrote: Hi, does anybody have an idea what to do if ICH6 BIOS Lock is enabled and BIOS Write is disabled? Removing the lock bit seems to fail according to flashrom. Yes, put a magic signature somewhere, go to S3 and wake up again. I read about this method somewhere in Phoenix BIOS Windows flash utility documentation a few years ago. But, not sure yet whether it's reliable enough. Have you test it? or is it already integrated in current flashrom? Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: [EMAIL PROTECTED] • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- Regards, Darmawan Salihun -= Human knowledge belongs to the world =- -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [LinuxBIOS] [Fwd: Re: AMD 690G chipset support in LinuxBIOS v2]
Hi Marc, On Jan 22, 2008 1:21 AM, Marc Jones [EMAIL PROTECTED] wrote: The 690/600 support should be available in the first half of this year. We moved it out a few months to bring in the Barcelona support. I don't have specific dates but we will announce the code to the list as soon as it is available. The support would be on coreboot v2?linuxbios v2 right? Marc bari wrote: Any news on AMD M690 Coreboot support now that it is part of the AMD Embedded Solutions group? -Bari Marc Jones wrote: Currently there is no support in LinuxBIOS for any ATI(now AMD) chipsets. We do plan to work on this in the next six months but I don't have a specific release date. == Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:[EMAIL PROTECTED] http://www.amd.com/embeddedprocessors Marc Regards, Darmawan --- -= Human knowledge belongs to the world =- -- coreboot mailing list coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
