Re: [coreboot] coreboot Digest, Vol 102, Issue 5
When I tried using flashrom and the file downloaded off John's site, I get a failure result. If I flash back to the backup.bios it says sucess. Why would this be happened on the Samsung 550? On Tue, Aug 6, 2013 at 3:00 AM, wrote: > Send coreboot mailing list submissions to > coreboot@coreboot.org > > To subscribe or unsubscribe via the World Wide Web, visit > http://www.coreboot.org/mailman/listinfo/coreboot > or, via email, send a message with subject or body 'help' to > coreboot-requ...@coreboot.org > > You can reach the person managing the list at > coreboot-ow...@coreboot.org > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of coreboot digest..." > > > Today's Topics: > >1. haswell firmware graphics support (ron minnich) > > > -- > > Message: 1 > Date: Mon, 5 Aug 2013 20:29:07 -0700 > From: ron minnich > To: coreboot > Subject: [coreboot] haswell firmware graphics support > Message-ID: > arv3jwbuq-jtrrb_q0gh...@mail.gmail.com> > Content-Type: text/plain; charset=ISO-8859-1 > > is now there in coreboot. > > If you have a board, such as a wtm2, and would like to work to get > this set up on your board, please let me know. > > All the heavy lifting in the final phase of this work was done by > Furquan Shaikh, in his summer internship here at Google. He's done a > very fine job. The code is IMHO really good. What we've learned can > also be applied to older chipsets, so let me know if you have interest > along those lines. > > We're finally breaking open the video bios situation; with luck, it > will soon be as open as ARM platforms ;-) > > thanks > > ron > > > > -- > > ___ > coreboot mailing list > coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > > End of coreboot Digest, Vol 102, Issue 5 > > -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] hi every one...
On 21.06.2011 03:54, ali hagigat wrote: I have a motherboard, Pentium III, 815/ICH2. How the CPU can be put into the deep sleep state? Is it possible to do it while not having the board schematic? Sure read the sleep states in ICH2 datasheet. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Svn works
On 22.05.2011 11:50, Gregg Levine wrote: Hello! I just ran the commands to update a previously checked out release. And without any complaints or anything else repeatable it just worked. Well that is a good thing :-) Thank god for SVN :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Is there searchable version of this mail list?
On 04/28/2011 10:55 AM, Boris Shpoungin wrote: Is there searchable version of this mail list which allows to search posts by keywords? Thanks http://www.mail-archive.com/linuxbios@clustermatic.org/ http://blog.gmane.org/gmane.linux.bios/ -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Welcome coreboot 2011 GSoC students
On 04/26/2011 10:16 AM, Marc Jones wrote: Say hi to the four GSoC students working with coreboot this summer. Hamo, Leandro, Stefan, and Tadas. You should be seeing more from them on the mail list and in IRC. Please make them welcome. They will also be keeping us all up to date on their progress on http://blogs.coreboot.org. Hello Hamo, Leandro, Stefan, and Tadas! Welcome to coreboot, glad to have you :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Happy Bunny Day!
Happy Bunny Day Everyone! -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] romcc segfault
On 04/12/2011 05:10 PM, Stefan Reinauer wrote: Hi, just a heads up, I got romcc to segfault with the following sample program: D'oh! -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] ask for ideas and suggestions about CBFS support on ARM
On 04/10/2011 12:25 PM, Patrick Georgi wrote: Am 10.04.2011 18:10, schrieb Joseph Smith: How about spitting up the code using pre-processing directives? One for arm and one for IA32? Just a thought. AH please. not. more. compile. time. options. sorry I guess that is not a good idea then... -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] ask for ideas and suggestions about CBFS support on ARM
On 04/10/2011 08:49 AM, Hamo wrote: Dear lists, I have be studying CBFS filesystem these days. Since coreboot only supports IA32 architecture now, the CBFS has hard-coded boot address and all the boot-related code and master header are located at around 0xFFF0. But as ARM read their first instruction at 0x0, we need change the CBFS filesystem but not destroy IA32 support. When porting to ARM, how should the rom be organized? I have 2 ideas: 1. Totally rewrite the CBFS structure on ARM according to that one on IA32 to meet the requirement of ARM architecture, including move the reset code and bootblock to the start of ROM(at address 0x0) and put all the other components follow them. In this way, we should rewrite the CBFStool and add a new option to CBFStool to tell it the architecture we are using. 2. Use the same structure on IA32 architecture but set the master header's offset to other value than 0x0 so that we can put boot code at the start of rom. Which one should I take or Do we have any better choice? Hope for your help. How about spitting up the code using pre-processing directives? One for arm and one for IA32? Just a thought. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [RFC][PATCHv2]add WIP_ARM config entry
On 04/06/2011 10:46 AM, Alex G. wrote: On 04/06/2011 05:25 PM, Paul Menzel wrote: PPS: Is this a good time to move to Git altogether? A mirror already exists. ;-) Since I am not doing any development, I am not the one to make that call. It's nice to have a git mirror, but contributors shouldn't be forced to use git, especially since subversion has been used for aeons with coreboot. Personally, I would be very unhappy to be forced to use git. -1 to gitification Yes Alex, I prefer svn over git 10 to 1. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] I865 memory controller status
On 04/05/2011 12:25 PM, Corey Osgood wrote: On Tue, Apr 5, 2011 at 10:38 AM, James Wall wrote: On Apr 5, 2011 9:02 AM, "Idwer Vollering" wrote: 2011/4/5 James Wall: Hello all, What is the status of the i865 memory controller? That chipset as a whole is (currently) unsupported, however plans to support it are there. RAM init is work in progress, another developer and I have a total of three i865 boards. Since RAM init is the hardest part, and we don't work on it full time, support can be expected anything but soon. All I have at this moment is nonworking code, it dies/stops in the beginning of RAM init. I expect to be working on this somewhat more frequent/intensive in two or three weeks. Idwer I am willing to test but I have very little coding knowledge, mostly bash scripts and hello world c programming skills. Well most of coreboot coding is pci_write_configX(whatever the datasheet tells you). The hard part is figuring out all the stuff the datasheet doesn't tell you :( Yeah and Intel is great at only giving you half the picture ;-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [RFC][PATCH]add EXPERIMENTAL config entry
On Tue, 5 Apr 2011 17:30:00 +0800, Hamo wrote: > Add EXPERIMENTAL config entry so that we can make all ARM-related > entries depend on this now. > We need to make all the ARM-related code available to ALL so that we > can attract those interested in ARM to join us. During this process, > some of the code may not be usable, so we need this to ensure that > those normal users will not be upset with it. > > Signed-off-by: Yang Hamo Bai > > Index: src/Kconfig > === > --- src/Kconfig (revision 6479) > +++ src/Kconfig (working copy) > @@ -21,6 +21,12 @@ > > menu "General setup" > > +config EXPERIMENTAL > +bool "Prompt for developement and/or incomplete code" > +default n > +help > + Some of the various things that Coreboot supports can be in a > state of development where the functionality, stability, or the level > of testing is not yet high enough fro general use. > + > config EXPERT > bool "Expert mode" > help > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot It is nice for everyone to have access to work in progress code but I am going to have to nak this only because config EXPERIMENTAL is way to broad and it opens the door for everyone to submit their half backed code arm or not. Then we end up with a tree full of unfinished code. I would consider acking something like config WIP_ARM or EXPERIMENTAL_ARM only because I would be really happy to see arm support. Sorry. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] FILO: USB_DISK by default should be disabled (trivial)
On 04/03/2011 02:49 PM, Tadas Slotkus wrote: Hello, This is my first patch, so please don't throw stones to me :) "config USB_DISK" should somehow depend on libpayload's "config USB" at least, but I don't know how to hardcode it, so I make USB disk to be disabled, since USB is disabled by default. It would be great if you could suggest how to link that dependency. Maybe instead libpayloads USB options should be enabled by default? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Where is the source code of Coreboot for PPC?
On 04/02/2011 08:14 AM, Hamo wrote: Hi lists, As I want to port Coreboot to ARM, I need to study the structure of Coreboot. Since Coreboot supported PPC once, I want to study the structure of the source code. But I can't find it. Can someone help me? Thanks. Doxygen gives a pretty good visual of the logical flow of coreboot in general. http://qa.coreboot.org/docs/doxygen/ I believe PPC was purged from the tree a little while ago so if you go back some revisions you will be able to find it. Hope that helps. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Board Incompatible but chipset is?
On Tue, 29 Mar 2011 18:20:45 -0400, Brandon wrote: > Hello. I have a Tyan Trinity S1857 board and according to your > compatible chipset list, it's chipset (Intel 440BX) is compatible. Is > there anyway I can get a port of some kind? I'm really not good with C > at all and I'd really like use Coreboot. Any reply will be greatly > appreciated. > Sorry Brandon, If you want coreboot on your board you will have to do the port yourself. You can do some research and find one of the many 440BX boards already supported that is close to yours and use that as a starting point. Good Luck :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [SerialICE] Serial output on Winbond W83627HG
On 03/29/2011 05:34 PM, Stefan Reinauer wrote: * Joseph Smith [110329 23:00]: Oh for reference: "To enable configuration registers programming, entry key must output twice to index port continuously. The entry key is decided by power on setting pins RTS2#/PS_CONF_KEY1 and RTS3#/PS_CONF_KEY0 as following: RTS2#/PS_CONF_KEY1 RTS3#/PS_CONF_KEY0 Entry key 0 0 0x77 ( default ) 0 1 0xA0 1 0 0x87 1 1 0x67 0x67 was the winner for me :-) Please supply a patch that adds this entry key to the fintec code in superiotool. Yes on my todo list. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Microcode CPU writeup
On 02/28/2011 02:16 AM, Rudolf Marek wrote: Hi all, Would someone be interrested if I write something about microcoded CPUs controllers? Like the classic uCode ROM + ALU + Regs + IO unit? Thanks, Rudolf Yeah sure :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot meeting @ Google, Sunday Mar. 13
Hello I am in the new england area so NYC is not to far for me :-) -- Sent from my Android phone with K-9 Mail. Please excuse my brevity. Gregg Levine wrote: On Fri, Mar 11, 2011 at 9:29 PM, David Hendricks wrote: > Hey everyone, > Stefan and I are going to be @ Google in Mountain View hacking on Coreboot > this weekend, so we figured this would be a good time to host another users > group meeting for those interested. This time we'll be hacking on our shiny > new AMD Persimmons (Fam 14h / Fusion) dev boards which I have been assured > by AMD are non-confidential so anyone curious can come in and poke at 'em. > Or you can swing by Fry's before coming and pick up a generic E350 board, > like the one Scott Duplichan recently > ported: http://www.coreboot.org/pipermail/coreboot/2011-February/063737.html > When: Sunday Mar. 13, noon to 8pm > Where: 1950 Charleston Rd. in Mountain View [ Link ], Alamitos conference > room (1st floor, adjacent to lobby) > Contact #: 408-512-3445 > (last meeting's participants bcc'd since this is pretty short notice) > -- > David Hendricks (dhendrix) > Systems Software Engineer, Google Inc. > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > Hello! I imagine it would not practical to throw a Coreboot based event here in NYC? I've been to the Google NYC Offices before, and it looks, well good to me. Although off list I can relate some issues I can't make public. - Gregg C Levine gregg.drw...@gmail.com "This signature fought the Time Wars, time and again." -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Support for Core i3 and better
On Fri, 11 Mar 2011 14:50:32 +0300, Oleg Gvozdev wrote: > 2011/3/11 Alex G. > >> On 03/11/2011 12:19 PM, Oleg Gvozdev wrote: >> > Hello >> > Could you, please, advise what motherboard I should use with coreboot > to >> > support Core i3, i5 or i7 CPU ? >> Yes. >> >> > And if any of these CPUs is not supported for now, where they will be >> > supported? >> In their momma's gusset. >> >> > As an alternative: do you support Core 2 Duo and with what motheboard ? >> > >> A little word of advice. Coming and asking us about what hardware to buy >> from a vendor that is more evil and uncooperative than Satan, is not >> going to bring you happy respondents. We're getting tired of having to >> tell people that Intel does not provide the documentation needed to >> support their hardware. >> >> So, suck it up, and look at AMD's offering instead. >> >> Alex >> >> -- >> coreboot mailing list: coreboot@coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > > > Thanks, > > I look now at Gygabyte GA-MA785GMT-UD2H and AM3 socket. > > > And my final questions are the next: > > 1. Does Coreboot work with Phenom II Thuban CPU ? I want 6-core CPU of > Phenom2 > > 2. If it does not, what do you suggest from quadcores Phenom2 AM3 or AM+.. > (i wrote your sentence about Satan,but i dont want to spend money on > unworking system) > > I just need as much powerfull CPU as it can be to use with Coreboot. Did you look here? http://www.coreboot.org/Supported_Motherboards -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Support for Core i3 and better
On Fri, 11 Mar 2011 12:53:50 +0200, "Alex G." wrote: > On 03/11/2011 12:19 PM, Oleg Gvozdev wrote: >> Hello >> Could you, please, advise what motherboard I should use with coreboot to >> support Core i3, i5 or i7 CPU ? > Yes. > >> And if any of these CPUs is not supported for now, where they will be >> supported? > In their momma's gusset. > >> As an alternative: do you support Core 2 Duo and with what motheboard ? >> > A little word of advice. Coming and asking us about what hardware to buy > from a vendor that is more evil and uncooperative than Satan, is not > going to bring you happy respondents. We're getting tired of having to > tell people that Intel does not provide the documentation needed to > support their hardware. > > So, suck it up, and look at AMD's offering instead. > Wow! -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Trying to port Intel Truxton to CAR
On 03/10/2011 07:55 PM, zxy__1127 wrote: > hi > check smbus DEVID. Would be early smbus at that point. > Thanks! > 2011-03-11 > > zxy__1127 > > *发件人：* Noé_Rubinstein > *发送时间：* 2011-03-11 03:03:50 > *收件人：* coreboot@coreboot.org > *抄送：* > *主题：* [coreboot] Trying to port Intel Truxton to CAR > NOT TO MERGE > Signed-off-by: Noé Rubinstein > I'm trying to port Intel Truxton to CAR. So far, serial output works and > Coreboot fails during SPD dump. If I remove the SPD dump, serial output > doesn't work anymore (??). > I have been told on the chan to post my current progress here. The patch > is not meant to be used as-is, and contains a lot of unrelated code, as > I was explicitly requested to leave things as they are. > -- > Noé Rubinstein > Proformatique (groupe Avencall) - XiVO IPBX OpenHardware > 10 bis, rue Lucien VOILIN - 92800 Puteaux > Tél. : +33 (0)1 41 38 99 60 ext 123 > Fax. : +33 (0)1 41 38 99 70 > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > Could also be something is funky with your memory controller not initializing correctly, this would cause bad SPD reads. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Support fot UMC UM8670 Super IO
On Thu, 10 Mar 2011 11:12:29 +0530, Anup Rao wrote: > Hi Everyone, > > I want to install Coreboot on an old Cyrix 6x86 machine. It comes > equipped with a M558 motherboard. > The AMI BIOS string ID is > 51-0830-001437-0011-071595-UT801X-001_10_UTRON-F > Further details can be found on this webpage: > http://motherboards.mbarron.net/models/pcchips/m558.htm > > The Super IO chip on it is a UMC UM8670. The Superiotool currently > does not detect/dump this chip (exactly as mentioned on the supported > HW page). > Also, It is currently not listed on the supported chipsets page for > Coreboot. I am unable to find any further information on the web for > this chip. > I am hoping that this chip is in someway a clone or identical to other > SuperIO chips. > > Can anyone confirm if it is supported by Coreboot? If not can anyone > point me to a location where information on this chip could be > available ? > Good luck to you, no part of that board is currently supported by coreboot it is simply way too old. Also good luck trying to find any datasheets for something that old. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] [3/4] [The 604 CAR crusades] Episode III - Revenge of the Abuild
On 03/09/2011 08:04 PM, Alex G. wrote: On 03/10/2011 02:30 AM, Joseph Smith wrote: Yes I am a little confused. Alex did you actually test CAR on a Socket 604 board? Or is this all just abuilded? I researched the matter, found that those CPUs support it, and I even found that a board already implemented CAR for 604 CPUs. Please the Preludium read if the chance yet got you not you have. No I do not have a 604 board, and did not test this on a 604 board. Sorry to say Alex, unless someone can with the hardware (at least one board can confirm) I will have to sit this one out. I know from developing CAR for both i830 and i810 that things can got wrong very easily, and if they do you will not even get serial output Sorry. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] [3/4] [The 604 CAR crusades] Episode III - Revenge of the Abuild
On 03/09/2011 04:19 PM, Stefan Reinauer wrote: * Alex G. [110309 21:59]: While the previous two patches were innocently trivial and abuild tested, this one _will_ break the build for several Socket 604 boards. We want the build to be broken until we can port those to CAR. Please provide a patch that does that. Actually we don't want the build to be broken. ;-) See patch for verbosity. The Tyan s2735 is a Socket 604 board that uses CAR. Did you verify that all CPUs that can be plugged into a Socket 604 can actually do CAR? Yes I am a little confused. Alex did you actually test CAR on a Socket 604 board? Or is this all just abuilded? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] self modifying code in intel vga bios?
O.T. - Is there i915 development going on? On Tue, 8 Mar 2011 11:01:57 +0100, "Georgi, Patrick" wrote: > Am Dienstag, den 08.03.2011, 10:28 +0100 schrieb cinap_len...@gmx.de: >> i know that the rom area is usualy cached in ram but to catch mistakes >> i disallow writing to the rom area... fish will make full traces >> later this day... it could be just a screwup on my side... >> just curious :) > I saw Intel VGABIOSes write to that area, and it was required for proper > operation of the device later. See r6251 of coreboot where I changed > YABEL's behaviour to account for that. > -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Add target for ASUS K8V-X SE motherboard
On 03/02/2011 05:03 PM, Alex G. wrote: On 03/02/2011 11:41 PM, Joseph Smith wrote: On 03/02/2011 04:38 PM, Peter Stuge wrote: Alex G. wrote: Add support for ASUS K8X-X SE motherboard. .. Linux cannot complete booting. Also not with acpi=off so that it uses the mptable? Yes. It fails to work with acpi, mptable, and pirq table. That means [no option], "acpi=off", and "acpi=off noapic" respectively. Basically the code isn't ready yet. I explained the issue in more detail in my first email qith this patch, that I had sent a while back. Maybe we should have a CONFIG_EXPERIMENTAL ? Alright, but don't mind my asking, how exactly do we do this? Alex why don't you leave acpi out for now, Linux doesn't need it to boot. I would concentrate on your IRQ routing issue. I haven't even touched the ACPI in over month. I'm testing with "acpi=off". The problem doesn't seem to be IRQ routing, as in routing, but the IOAPIC refusing to work the way it should work. I've explained this in more detail in my initial posting. I'm waiting for the friend who owns this board to pick it up any day now, so I doubt I will be able to finish it. I've been spinning in circles for a very long time now. If I can't get it ready, I'd like the next person who tries to port this board to already have my work as a starting point. Alex have you tried adding irqpoll to your command line? It may give you some clues? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Add target for ASUS K8V-X SE motherboard
On 03/02/2011 04:38 PM, Peter Stuge wrote: Alex G. wrote: Add support for ASUS K8X-X SE motherboard. .. Linux cannot complete booting. Also not with acpi=off so that it uses the mptable? Basically the code isn't ready yet. Maybe we should have a CONFIG_EXPERIMENTAL ? //Peter Alex why don't you leave acpi out for now, Linux doesn't need it to boot. I would concentrate on your IRQ routing issue. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Hello
On 03/02/2011 12:03 PM, Andy wrote: How to use the coreboot-5917 software?? $ svn co svn://coreboot.org/coreboot/trunk coreboot -r 5917 -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Add K8T800, K8T800Pro*, and K8M800* support
On 03/01/2011 04:14 PM, Stefan Reinauer wrote: * Peter Stuge [110216 14:43]: Alex G. wrote: Extended K8T890 driver to include the K8T800 and K8M800 northbridges. The K8T800 is almost identical to the K8T800Pro, also added to this patch. The K8T800_OLD is also defined, which is an older version of the K8T800, but which has no driver and early HT code yet. Also extended the K8M890 VGA driver to work for the K8M800 (not tested). According to the datasheet, the K8T890 and K8T800 are similar enough to be able to use the same initialization code. At least for the K8T800, this is sufficient to have a working HT link with the CPU, and to initialise the V-Link to the southbridge. Signed-off-by Alexandru Gagniuc Acked-by: Peter Stuge r6367 Sorry, we have to back this out again since the license of some of the files are not compatible with the coreboot license. Unfortunately at this point we can not allow GPLv3 code in the repository, as the resulting image will be GPLv2. Can you please back this out, Peter? (Or Alexandru, send a license update if licensing your files under GPLv2 is ok for you) Stefan Wow! That is a big no, no. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] #178: Life Insurance - How To Buy Life Insurance Policies
On 03/01/2011 02:24 PM, coreboot wrote: #178: Life Insurance - How To Buy Life Insurance Policies -+- Reporter: anonymous | Owner: Type: enhancement | c-d.hailfinger.devel.2006@… Priority: major |Status: new Component: flashrom (please use | Milestone: flashrom v1.1 trac on flashrom.org) | Keywords: life insurance Dependencies:| Patch Status: patch needs review -+- [[Image(http://www.johnkatsouris.co.uk/images/family_park.jpg)]] Buying such services like '''[http://www.lifeinsurance.net.au/ life insurance]''' in making things better for those people to have its best ways that will be better for them during this days. It can make things better for those people to have its best ways to satisfy their needs in life living in this world. This '''insurances''' people can have the things they need in life living in this world. Having such services that will make things better for them having the best services that will make them have a '''Life Insurance''' in making things better for them during this days. [[Image(http://onlinearnings.com/wp-content/uploads/2009/07/happy-life- insurance.jpg)]] It can make things better for those people having such '''[http://www.lifeinsurance.net.au/ life insurance]''' in a certain period of time. It is best for those people to have such ways that can be better for those people on having the things that will make them have such '''Living Insurance''' in a certain period of time that will make those people have its best ways in living. coreboot is selling life insurance now? Is this in case of electro static discharge? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Google Summer of Code 2011
On Mon, 28 Feb 2011 18:17:34 -0700, Marc Jones wrote: > GSoC mentoring org signup starts this week and is due by March 11. I > can take the lead this year, unless someone else would like to do it. > > If we are accepted (I expect we will be), Student applications are > March 28 - April 8. > > Please add your project ideas to the wiki : http://www.coreboot.org/GSoC > > Who would like to be a mentor this year? > > Marc > Hmm, even though I am getting old I am going to go back to school in the fall 2011 to further my education (and hopefully take some x86 assembly courses, cause I know some of you get sick of my assembly questions :-)). Could I be considered a student candidate for GSoC? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Intel's BIOS Implementation Test Suite
On 02/26/2011 11:23 AM, Scott Duplichan wrote: AMD recently contributed full processor and chipset reference code to the coreboot project, along with two working coreboot ports to demonstrate its use. FYI, AMD has been contributing code to coreboot for many years now, My fedora is off to them, many thanks, you know who you are :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Intel's BIOS Implementation Test Suite
On 02/26/2011 11:27 AM, Alex G. wrote: On 02/26/2011 06:23 PM, Scott Duplichan wrote: code is included, as far as I can tell. AMD recently contributed full processor and chipset reference code to the coreboot project, along with two working coreboot ports to demonstrate its use. You cannot really compare AMD to Intel, the same way you cannot compare an athlete to an old fart. :) The day Intel directly contributes code to coreboot will be the day monkeys land on mars. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Code organization question Re: Next target: ASUS TUSI-M
necessary at that point, otherwise the CBFS code > might not find the necessary data (because it's not mapped properly). > > I think the best approach would be to setup a simple mainboard / northbridge / southbridge dir with just the bare minimum and get raminit working. After that you can worry about things like cmos, vga, etc. No need to make things to complicated right off the bat, your just end up with a headache :-) Well I hope this helps. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Seeing the output messages
On 02/16/2011 05:15 AM, ali hagigat wrote: Joe, I wonder if you can answer my questions if you really know about them. I do not have any mother board with Coreboot support now. I am reviewing the code statically. Regards On Wed, Feb 16, 2011 at 1:35 PM, Joseph Smith wrote: On Wed, 16 Feb 2011 12:37:15 +0330, ali hagigat wrote: How a program is traced in Coreboot? by serial port? or initialization of internal graphics cards? What about those boards with external graphics cards? When it does printk, to what device the message is actually sent? Why don't you try it and find out! Of course I do. I have written code for several of boards in the coreboot tree. And several more I am working on. printk output goes to the serial console until vga starts and then it goes to both until the OS takes over. Maybe you should get a coreboot running on a board no way better to learn than to get your hands dirty, then maybe you will stop asking all these silly newbie questions. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Seeing the output messages
On Wed, 16 Feb 2011 12:37:15 +0330, ali hagigat wrote: > How a program is traced in Coreboot? by serial port? or initialization > of internal graphics cards? What about those boards with external > graphics cards? When it does printk, to what device the message is > actually sent? > Why don't you try it and find out! -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] QA contribution
On Tue, 01 Feb 2011 13:05:24 +0200, Juhana Helovuo wrote: > 30.1.2011 13:16, Peter Stuge kirjoitti: > >> Personally I believe that development is what is missing to get >> corebot testing going to a greater extent. As you will see in the >> documentation there are fairly many requirements for an individual >> mainboard to actually be hooked up to the test system. It's fully >> automated once it runs, but it's too complicated to get there. >> >> I think this needs to be optimized and to some degree productized, >> into an easy to buy and fairly affordable (<100$) unit that can >> administer testing of one or even better several mainboards. I have >> plenty of design and implementation ideas if you'd like to go into >> that. > > Hello all, > > I started building a tester device to hook up a mainboard into an > automated test host. > > The basic plan is as follows: The host computer is connected to tester > device via USB. The tester is connected to the target mainboard so that > it can take control of the BIOS ROM and reprogram it regardless of the > state of the target mainbaord. > > The tester device can also connect to the serial port of the target > mainboard, so it can act as a serial-over-USB-device. This is because > otherwise controlling the test of N mainboards would require N serial > ports in the host. > > The tester also has two FET switches for controlling the reset and ATX > power buttons on the target mainboard. > > The actual AC power control of the target mainboard is not included and > should be done by another device, such as this: > http://www.gembird.nl/default.aspx?op=products&op2=item&id=3234 > > So far there is support only for SPI ROMs, but the design could be > modified to support LPC and FWH also. > > The tester device is basically an Atmel Atmega microcontroller, which > can talk USB, RS232, SPI, and generic digital I/O. > > Here are some images of my first (incomplete) prototype: > > http://alpskari.asiantuntijat.org/~juhe/spi-flasher-piirilevyt/ > > The images were originally taken just to illustrate the PCB making > experiment via the toner transfer method, but you can also see what the > device looks like. The smaller board is specific to SPI ROMs and > attaches to the SPI ROM socket on the mainbaord. The larger PCB is a > microcontroller, which connects all the parts together. > > Both the software and hardware are incomplete. Hardware is missing some > parts and work. > > The software is not yet done, except a prototype microcontroller program > that can read and program SPI ROMs. It is controlled by "flashrom" from > Linux host. It can communicate via serial port using the "serial > programmer" protocol. Flashrom program was modified by adding a > "serprog-spi"-module, which is modified from "serprog", mainly by > adapting it to suit SPI. > > > Best regards, > Juhana Helovuo Wow! that is really cool! I hope it works out as planned :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] missing read_resources for CK804
On 01/27/2011 10:26 AM, Joseph Smith wrote: On Thu, 27 Jan 2011 07:02:04 -0700, Myles Watson wrote: On Thu, Jan 27, 2011 at 6:38 AM, Joseph Smith wrote: On Thu, 27 Jan 2011 06:15:34 -0700, Myles Watson wrote: On Thu, Jan 27, 2011 at 5:29 AM, Joseph Smith wrote: Hello, Working on a new CK804 board Which board did you base it on? What are the differences? I based it on the Asus A8N-E. The only differences are: 1. A8N-E supports 1 Athlon64 dualcore CPU, My board (Asus K8N-DRE) supports 2 Opteron dualcore CPU's 2. SuperIO's are different. I would think that there is a board that's more similar, then, but I'm not sure. But besides that, all the rest of the hardware is the same as far as I can tell. and I have it almost booting but it seems the resource allocator does not like / or want to enumerate the CK804. It fails before resource allocation, at device enumeration. It's hard to tell from the log why it went south, but are you sure that the Southbridge is on HT link 1? I have no idea how can I tell? Is there a way to tell what HT link it is on with the factory bios? There are a couple of ways. lspci from the factory BIOS is probably the easiest. There are a couple of registers that would tell you. Try: sudo lspci -xxx -s 18.0 Then look at the line that starts with e0: mine is: e0: 03 00 00 03 03 01 40 40 ... From the BKDG: Configuration Base and Limit 0–3 Registers Function 1: Offset E0h, E4h, E8h, ECh Remember that the byte order is little endian, and my registers are: e0 0303 - bus 0-3 on node 0 link 0 rw enabled e4 40400103 - bus 40-40 on node 0 link 1 rw enabled It is acually device 18.1. Factory bios 0xe0=0x5000103, 0xe4=0,0xe8=0,0xec=0. So that means I have - bus 0-5 on node 0 link 1 rw enabled And that is it. So now do we tell coreboot about it? maybe a custom resourcemap.c??? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] missing read_resources for CK804
On Thu, 27 Jan 2011 07:02:04 -0700, Myles Watson wrote: > On Thu, Jan 27, 2011 at 6:38 AM, Joseph Smith wrote: >> >> >> On Thu, 27 Jan 2011 06:15:34 -0700, Myles Watson > wrote: >>> On Thu, Jan 27, 2011 at 5:29 AM, Joseph Smith >> wrote: >>>> Hello, >>>> Working on a new CK804 board >>> Which board did you base it on? What are the differences? >>> >> I based it on the Asus A8N-E. The only differences are: >> >> 1. A8N-E supports 1 Athlon64 dualcore CPU, My board (Asus K8N-DRE) > supports >> 2 Opteron dualcore CPU's >> 2. SuperIO's are different. > I would think that there is a board that's more similar, then, but I'm not > sure. > >> But besides that, all the rest of the hardware is the same as far as I > can >> tell. >> >>>> and I have it almost booting but it seems the >>>> resource allocator does not like / or want to enumerate the CK804. >>> >>> It fails before resource allocation, at device enumeration. It's hard >>> to tell from the log why it went south, but are you sure that the >>> Southbridge is on HT link 1? >> >> I have no idea how can I tell? >> Is there a way to tell what HT link it is on with the factory bios? > There are a couple of ways. lspci from the factory BIOS is probably > the easiest. There are a couple of registers that would tell you. > > Try: > sudo lspci -xxx -s 18.0 > > Then look at the line that starts with e0: > > mine is: > e0: 03 00 00 03 03 01 40 40 ... > > From the BKDG: > > Configuration Base and Limit 0–3 Registers Function 1: Offset E0h, E4h, > E8h, ECh > > Remember that the byte order is little endian, and my registers are: > > e0 03000003 - bus 0-3 on node 0 link 0 rw enabled > e4 40400103 - bus 40-40 on node 0 link 1 rw enabled > It is acually device 18.1. Factory bios 0xe0=0x5000103, 0xe4=0,0xe8=0,0xec=0. So that means I have - bus 0-5 on node 0 link 1 rw enabled And that is it. So now do we tell coreboot about it? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] missing read_resources for CK804
On Thu, 27 Jan 2011 06:15:34 -0700, Myles Watson wrote: > On Thu, Jan 27, 2011 at 5:29 AM, Joseph Smith wrote: >> Hello, >> Working on a new CK804 board > Which board did you base it on? What are the differences? > I based it on the Asus A8N-E. The only differences are: 1. A8N-E supports 1 Athlon64 dualcore CPU, My board (Asus K8N-DRE) supports 2 Opteron dualcore CPU's 2. SuperIO's are different. But besides that, all the rest of the hardware is the same as far as I can tell. >> and I have it almost booting but it seems the >> resource allocator does not like / or want to enumerate the CK804. > > It fails before resource allocation, at device enumeration. It's hard > to tell from the log why it went south, but are you sure that the > Southbridge is on HT link 1? I have no idea how can I tell? Is there a way to tell what HT link it is on with the factory bios? > Here's a snippet from my log showing the > CK804 being found. > > PCI: Using configuration type 1 > PCI: 00:00.0 [10de/005e] ops > PCI: 00:00.0 [10de/005e] enabled > Capability: type 0x08 @ 0x44 > flags: 0x01e0 > PCI: 00:00.0 count: 000f static_count: 000f > PCI: 00:00.0 [10de/005e] enabled next_unitid: 000f > PCI: pci_scan_bus for bus 00 > PCI: 00:00.0 [10de/005e] enabled > PCI: 00:01.0 [10de/0051] bus ops > PCI: 00:01.0 [10de/0051] enabled > PCI: 00:01.1 [10de/0052] bus ops > PCI: 00:01.1 [10de/0052] enabled > PCI: 00:02.0 [10de/005a] ops > > Here's roughly the same point in your log: > > PCI: 00:18.3 [1022/1103] ops > PCI: 00:18.3 [1022/1103] enabled > PCI: pci_scan_bus returning with max=000 > PCI_DOMAIN: passpw: enabled > scan_static_bus for Root Device done > done > Wow mine looks very wrong If you would like to take alook at the code I have so far, let me know I can email it to you. Thanks for help Myles. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Question about CK804 boards
Hello, I am looking at adding a new target for the Asus K8N-DRE Nvidia CK804 board (http://www.asus.com/product.aspx?P_ID=qF4qMu1w9HDZjIvt). Most of the CK804 boards code is pretty much the same. How much of it is mainboard independent? Looks like all components are already supported by coreboot (CPU's, CK804, and SuperIO). This being my first AMD board any key tips would be great... like how to find gpios...etc. Too bad there is no public datasheet for CK804 Also is PCIE-1x and PCIE-16x both working on the CK804? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]Set display type to CRT on kontron 986lcd-m
On Thu, 13 Jan 2011 11:16:45 +0100, Patrick Georgi wrote: > Hi, > > attached patch changes the display type to CRT on kontron/986lcd-m as > the VGABIOS doesn't reliably pick a useful default (in some versions). > > > Signed-off-by: Patrick Georgi This is more of a trivial thing but Acked-by: Joseph Smith It would be really nice to be able to choose Kconfig options for the INT15 Handler ;-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]Improve YABEL compatibility
On Thu, 13 Jan 2011 11:05:55 +0100, Patrick Georgi wrote: > Hi, > > attached patch improves compatibility of YABEL with realmode execution > of the VGA BIOS by passing through access to IVT, BDA and option ROM > area directly, instead of copying them from the emulated memory to real > memory after initialization is done. > > Some VGA BIOSes seem to map hardware registers into the option ROM area, > so routing accesses to these into emulated RAM will lead to all kinds of > unexpected behaviour. > > The intent of YABEL in coreboot is to provide improved security by > isolating hardware access - this patch doesn't improve or degrade > security as the memory regions in question were already copied back > after emulation before this patch. > > > Signed-off-by: Patrick Georgi Nice work! Acked-by: Joseph Smith -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Restarting at "Jumping to image"
Hello, I am working on a new mainboard/northbridge and have got it all the way to "Jumping to image" and then it immediately restarts and loops at that point over and over. I even did a ram_check() on the whole memory (accept vga range) and it passes just fine. Has anyone seen this before? Is there a simple way to verify/read the raw data after coreboot is copied to memory? Help? Here is my bootlog: http://coreboot.pastebin.com/KNyMM9xZ -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Next target: ASUS TUSI-M
On Wed, 5 Jan 2011 00:06:29 -0500, Keith Hui wrote: > This is the next board I want to port coreboot to. And the three logs > are attached. "Sissy" is what I name the machine the board is in, > after SiS. :D > > The flash chip i know for sure is SST 39SF020A. It needs a board > enable, for which I have figured out 3 of the 5 operations involved, > thanks to Luc's slides up at Phoronix. > > It used a soldered PLCC32 flash chip. I soldered a socket on myself, > and the chip miraclously survived. But I have not been able to get > another of the same chip for backup. All my 3 spares are DIP32. > > Super I/O is IT8705F, already supported. So it looks like all that's > needed is porting SiS630 from coreboot v1. I think I would also be the > first to port a single chip chipset to v4. > > Thanks to a previous thread on this list, I got the '630 datasheet, > but I don't know for sure what is different between it (the 630) and > my chip (630ET). > > Appreciate all the help I can get for this one. Sweet! I have a bunch of SIS 630 boards laying around, anything I can do to help just let me know :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] .cb files
LMFAO !!! "Patrick Georgi" wrote: >Am 03.01.2011 13:14, schrieb ali hagigat: >> How .cb files are created? >Creative work of human beings. > >> and what they are used for? >All kinds of things. > >In case you're wondering (which might qualify you for the creative work >mentioned above at least): Yes, these answers are mostly useless - I'm >a >proponent of the garbage-in-garbage-out principle. > > >Patrick > >-- >coreboot mailing list: coreboot@coreboot.org >http://www.coreboot.org/mailman/listinfo/coreboot -- Sent from my Android phone with K-9 Mail. Please excuse my brevity. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] incomplete documentation
On Sun, 2 Jan 2011 12:30:11 +0330, ali hagigat wrote: > Coreboot declares a complete documentation of some chips by: > http://www.coreboot.org/Datasheets > and particularly 82815E by: > http://www.coreboot.org/Datasheets#Intel_82801BA.2FBAM_.28ICH2.29 > > Where is the documentation for integrated graphics controller of this > chip? Only the explanation of some configuration registers are > available. > It is publicly available, try googling "82815 PRM" or "Intel 815 programmers reference manual" > Why Coreboot site maintainers do not clearly express that the > necessary documentation for BIOS developing is not available? Even the > open documents you have added in Data-sheet section are not complete. > Watch your tongue, there is a huge difference "open documents" and public documents. The "coreboot site maintainers" which includes many people with wiki access, don't have the time to run around collecting 50 million documents floating around the web, especially chipsets that are not even supported by coreboot yet. Google is your friend. FYI: You refer to the i815E Northbridge and link to the i82801BA ICH2 southbridge... two completely different things... are you sure you know what your doing??? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] CONFIG_DEBUG_RAM_SETUP bre aks build on i82810, i440bx and maybe more
On Mon, 20 Dec 2010 22:53:13 -0500, Keith Hui wrote: > > Joseph, now go fix i810. ;-) > Sorry, It will not be for a while I am to busy working on other things at the moment. Maybe Uwe, Anders, or anyone else contributing to i810? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] CONFIG_DEBUG_RAM_SETUP breaks build on i82810, i440bx and maybe more
On Sun, 19 Dec 2010 21:56:58 -0500, Keith Hui wrote: > As title. Log from a locally modified abuild attached. > > I think this is something we did some time ago with simplifying > debugging facility - trying to use printk() everywhere. > Well, that is not good. Not good at all... -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]Allow components to add files to CBFS
On 12/15/2010 05:23 PM, Stefan Reinauer wrote: * Scott Duplichan [101215 22:33]: -Original Message- From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On Behalf Of Patrick Georgi Sent: Wednesday, December 15, 2010 03:08 PM To: coreboot@coreboot.org Subject: Re: [coreboot] [PATCH]Allow components to add files to CBFS ]That there aren't any binary components in the tree is simply for the fact ]that they're not redistributable: We usually scrap them from vendor BIOSes, ]and they're not separately available. Thanks for explaining. I always wondered why uma video option roms were not included with coreboot. Microcode patches should be put into this same category. The supplied AMD patches are not the latest, if I am not mistaken. It wouldn't be hard to automate the process of extracting AMD patches from a BIOS binary. Actually we can redistribute Intel and VIA option ROMs. I asked ATI and then AMD a lot of times, but I never got a definite written answer on whether they're no-lawyer-involved happy with us putting up copies of their oproms. If they were, I'd gladly add their images to our oprom repository on coreboot.org. Scott, can you (or Marc?) get anyone at AMD to make a binding statement? It would help the coreboot user experience a lot. Also, where do we officially get amd microcode files? I don't think extracting them from some UEFI image is the way to go. Again, for Intel it's fairly easy. Can we get AMD to catch up here? Yes most of the Intel oproms (vga bios blobs) are publicly downloadable from the Intel website (just look for the developer drivers). I think we should have a section in the tree for the blobs. I think the only discrepancy Intel has is they do not want hacked/cracked copy's of their blobs re-distributable... -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]Allow components to add files to CBFS
On 12/15/2010 11:04 AM, Peter Stuge wrote: Great idea in general. Patrick Georgi wrote: filename-position This one is tricky. Blobs may need to have alignment, a negative offset (ie. start at end of flash - $amount) rather than a positive, etc. How could we handle those cases? //Peter Ah, great point Peter! The MBI binary bolb modules ***-have-*** to be aligned in order for the VGA Bios to read them, other wise they are useless blobs of crap, and the VGA Bios is smart enough to know that and reject them. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]Allow components to add files to CBFS
On 12/15/2010 09:10 AM, Patrick Georgi wrote: Am Mittwoch, 15. Dezember 2010, um 14:36:51 schrieb Joseph Smith: Hmm, still a little confused what you mean here. So your patch just reworks the code to handle all binary blobs the same??? It provides an easier way to add binary components. Right now we add them to Kconfig and have common code that switches based on these Kconfig flags in src/arch/x86/Makefile.inc. With this patch, if a chipset component requires some binary, it can add that binary to the build easily without having to touch global code. Ok, so does it just search for the file names and if found adds them to the build? src/arch/x86/Makefile.inc contains code for MBI, which is (as far as I can see) specific to a single chipset. That simply doesn't belong in there, but so far there is no other way to do it. Oh no, the MBI code can work with all Intel chipsets with tv-out and lvds capabilities (whether internal or external). Currently only i945/ICH7 and i830/ICH4 use it...and another one is coming soon :-) Future chipsets will require more of that rather than less. The growing use of embedded controllers, even in desktop chipsets, also plays a part in this. Agreed. What this patch doesn't do is to rewire our existing binary component handling to use the new framework. Ok good. Acked-by: Joseph Smith That's a separate step. Hmm, I think the "separate step" will require some major testing I really do not want MBI to get broken. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]Allow components to add files to CBFS
On 12/15/2010 06:51 AM, Patrick Georgi wrote: Hi, We have a couple of chipsets in the tree that require external data in CBFS, sometimes with placement requirements (eg. for embedded controllers), and there will be more of that kind to come. Right now, we're adding Kconfig options for each and every of these new files, but that's not a sustainable model. The patch provides a way for each Makefile.inc to add such files by setting up a couple of variables: # -y can, as usual be used for conditional inclusion cbfs-files-y += filename filename-name := CBFS filename filename-type := CBFS type filename-position := location in CBFS (eg. 0xfff8) filename can either be a filename in the current directory (or a relative path from there) or, if that doesn't match a file, a path starting from the tree root. filename in filename-name etc. means the actual filename, for example: cbfs-files-y += mbi.bin mbi.bin-name := mbi.bin mbi.bin-type := 0x80 filename-position is an optional argument. If it doesn't exist, CBFS is free in its placement of the file. The files are added immediately after creation of the CBFS image to make sure that they'll have the space. Even the romstage is added only afterwards. mbi.bin-* (in the example above) are cleaned after processing to avoid option conflicts if two files of the same name (with different CBFS names) are added. To avoid code duplication, I moved CBFS image creation from two locations into src/arch/x86/Makefile.inc. That's also part of the patch. The patch doesn't yet rework MBI, VGABIOS and bootsplash handling into the new method of adding generic files. I'm reasonably sure that MBI and VGABIOS can be moved out of Kconfig without much effect to users (as they're pretty much a binary decision, if the file is used at all, but the file is the same everywhere), but the bootsplash is probably a more individualistic matter, so should be kept in Kconfig. Opinions? Hmm, still a little confused what you mean here. So your patch just reworks the code to handle all binary blobs the same??? - Joe -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] build service results for r6173
On 12/13/2010 03:55 PM, repository service wrote: Dear coreboot readers! This is the automatic build system of coreboot. The developer "ruik" checked in revision 6173 to the coreboot repository. This caused the following changes: Change Log: Following patch adds support for suspend/resume functions. I had to change the get_cbmem_toc because macro magic did not work well. The writes to NVRAM are not used in asrock board (k8 pre rev f) but they should work when used with am2 boards. In fact maybe the suspend will work on mahogany or others ;) - with some simple patch which follows for asrock. Signed-off-by: Rudolf Marek Acked-by: Peter Stuge Build Log: Compilation of amd:mahogany has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=mahogany&vendor=amd&num=2 Compilation of amd:mahogany_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=mahogany_fam10&vendor=amd&num=2 Compilation of amd:tilapia_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=tilapia_fam10&vendor=amd&num=2 Compilation of asrock:939a785gmh has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=939a785gmh&vendor=asrock&num=2 Compilation of asus:a8v-e_deluxe has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=a8v-e_deluxe&vendor=asus&num=2 Compilation of asus:a8v-e_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=a8v-e_se&vendor=asus&num=2 Compilation of asus:m2v has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=m2v&vendor=asus&num=2 Compilation of asus:m2v-mx_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=m2v-mx_se&vendor=asus&num=2 Compilation of asus:m4a78-em has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=m4a78-em&vendor=asus&num=2 Compilation of asus:m4a785-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=m4a785-m&vendor=asus&num=2 Compilation of getac:p470 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=p470&vendor=getac&num=2 Compilation of gigabyte:ma785gmt has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=ma785gmt&vendor=gigabyte&num=2 Compilation of gigabyte:ma78gm has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=ma78gm&vendor=gigabyte&num=2 Compilation of ibase:mb899 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=mb899&vendor=ibase&num=2 Compilation of iei:kino-780am2-fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=kino-780am2-fam10&vendor=iei&num=2 Compilation of intel:d945gclf has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=d945gclf&vendor=intel&num=2 Compilation of jetway:pa78vm5 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=pa78vm5&vendor=jetway&num=2 Compilation of kontron:986lcd-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=986lcd-m&vendor=kontron&num=2 Compilation of roda:rk886ex has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=rk886ex&vendor=roda&num=2 If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system Oh, no... -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] SerialICE
On 12/09/2010 05:41 PM, Stefan Reinauer wrote: * Jonas Bülow [101209 22:36]: SerialICE sounds interesting. Is the project still alive? Yes, it is. Alive and waiting for contributions. :-) Stefan It is as alive as you want to it to be Jonas :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] FYI IWILL DK8S2's CHEAP
On 12/03/2010 10:32 AM, Joseph Smith wrote: On Fri, 03 Dec 2010 10:02:57 -0500, Joseph Smith wrote: Hello, Just an FYI for anyone interested in a cheap powerful server board to develop coreboot on: IWILL DK8S2, comes with two 2.2GHz dual core Opterons for a steal at $29.99 and there is 248 of them available :-) http://cgi.ebay.com/IWILL-DK8S2-eATX-Quad-Core-2-2GHz-Opteron-Motherboard-/230548264166?pt=Motherboards&hash=item35adbf54e6 Only 247 now I just purchased one for myself as an early B-day present :-) Well I got my board today, looks good :-) Little disappointed though that these boards do not have the on-board sata raid controlleroh well I could always use a pci card I guess. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] FYI IWILL DK8S2's CHEAP
On Fri, 03 Dec 2010 10:02:57 -0500, Joseph Smith wrote: > Hello, > Just an FYI for anyone interested in a cheap powerful server board to > develop coreboot on: > > IWILL DK8S2, comes with two 2.2GHz dual core Opterons for a steal at $29.99 > and there is 248 of them available :-) > > http://cgi.ebay.com/IWILL-DK8S2-eATX-Quad-Core-2-2GHz-Opteron-Motherboard-/230548264166?pt=Motherboards&hash=item35adbf54e6 > > Only 247 now I just purchased one for myself as an early B-day present :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] FYI IWILL DK8S2's CHEAP
Hello, Just an FYI for anyone interested in a cheap powerful sever board to develop coreboot on: IWILL DK8S2, comes with two 2.2GHz dual core Opterons for a steal at $29.99 and there is 248 of them available :-) http://cgi.ebay.com/IWILL-DK8S2-eATX-Quad-Core-2-2GHz-Opteron-Motherboard-/230548264166?pt=Motherboards&hash=item35adbf54e6 -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] iWill mainboards???
Hello, I was just looking a iWill DK8S2 Opteron board but can not find the iWill website on the web. Anyone know what happened to them? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Add ICH5/i865 chipset detection, dumping s upport for model_f2x MSRs, ICH5 GPIOs and PM registers and add BAR reading support for i865
On Sun, 28 Nov 2010 01:19:18 +0100, Idwer Vollering wrote: > Add support for dumping the MSRs on model_f2x and dumping GPIOs and PM > registers on ICH5. > Add ICH5 and i865 to the supported chips list. > Enable the dumping of BAR6 on i865. > > Signed-off-by: Idwer Vollering > > --- > Nice! Acked-by: Joseph Smith -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Request for i852 -> i855 ACPI dump, please
Hello, I am in desperate need of a full (all tables) ACPI dump from somone with a i852 or i855 chipset. You can send it to me offlist if you like. Thanks in advance. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Avoid hang when 4GB or more DRAM is installed on AMD RS780 UMA systems
On Wed, 10 Nov 2010 19:29:45 -0800, Stefan Reinauer wrote: > > > Sent from my mobile phone > > On 10.11.2010, at 17:36, Joseph Smith wrote: >> Not so sure about AMD chips but I know Intel chips reserve memory just > below 4Gb for vga buffer. As for resource ranges Intel chips reserve a low > memory range for VESA IO registers and a high memory range for GMCH MMIO > registers. Hope that helps. >> > > Actually the intel chipsets reserve memory at the top of ram for graphics, > not below 4G Ah your right, my bad. It is just below TOM. ex: [rest of memory][vga memory area][tom]. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Avoid hang when 4GB or more DRAM is installed on AMD RS780 UMA systems
On 11/10/2010 07:30 PM, Scott Duplichan wrote: -Original Message- From: Joseph Smith [mailto:j...@settoplinux.org] Sent: Wednesday, November 10, 2010 05:42 PM To: Scott Duplichan Cc: 'Patrick Georgi'; coreboot@coreboot.org Subject: Re: [coreboot] [PATCH] Avoid hang when 4GB or more DRAM is installed on AMD RS780 UMA systems ]On 11/10/2010 06:18 PM, Scott Duplichan wrote: ]> ] On i945, UMA is done by providing a fixed resource. I don't think any ]> ] other changes were necessary (see src/northbridge/intel/i945/northbridge.c) ]> ]> I took a look at the i945 code and found the AMD code also adds the exact ]> same fixed resource for the UMA area. What I cannot figure out is how this ]> can reduce the WB DRAM range so that the UMA memory ix excluded. ]> ]> If I test with 2GB installed and a 256 MB frame buffer, function add_uma_resource ]> is called with the expected arguments: Adding UMA memory area, base=7000 size=1000 ]> ]> Later, set_var_mtrr_resource is passed a range of c-7fff. The existing ]> coreboot code assumes this range has already had the UMA part removed, and ]> adds it back: ]> ]> // Increase the base range and set up UMA as an UC hole instead ]> var_state.range_sizek += (uma_memory_size>> 10); ]> ]> What logic should deduct the reserved range from the DRAM range before ]> this code runs? ]> ]Hmm. The UMA resource should be in high memory. And code should say if ]UMA high memory resource is used do not allocate c. Interesting. I think I can explain this part. The message "Adding UMA memory area, base=7000 size=1000" refers to the physical address of the DRAM that becomes unavailable due to UMA. This DRAM is never accessed using this physical address. It is accessed through the frame buffer bar, which gets assigned an address between top of memory and 4GB, such as E800. Not so sure about AMD chips but I know Intel chips reserve memory just below 4Gb for vga buffer. As for resource ranges Intel chips reserve a low memory range for VESA IO registers and a high memory range for GMCH MMIO registers. Hope that helps. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Avoid hang when 4GB or more DRAM is installed on AMD RS780 UMA systems
On 11/10/2010 06:18 PM, Scott Duplichan wrote: ] On i945, UMA is done by providing a fixed resource. I don't think any ] other changes were necessary (see src/northbridge/intel/i945/northbridge.c) I took a look at the i945 code and found the AMD code also adds the exact same fixed resource for the UMA area. What I cannot figure out is how this can reduce the WB DRAM range so that the UMA memory ix excluded. If I test with 2GB installed and a 256 MB frame buffer, function add_uma_resource is called with the expected arguments: Adding UMA memory area, base=7000 size=1000 Later, set_var_mtrr_resource is passed a range of c-7fff. The existing coreboot code assumes this range has already had the UMA part removed, and adds it back: // Increase the base range and set up UMA as an UC hole instead var_state.range_sizek += (uma_memory_size>> 10); What logic should deduct the reserved range from the DRAM range before this code runs? Hmm. The UMA resource should be in high memory. And code should say if UMA high memory resource is used do not allocate c. Interesting. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Trouble converting Truxton to CAR
On Tue, 02 Nov 2010 08:43:50 +0100, Patrick Georgi wrote: > Am 02.11.2010 02:17, schrieb Dustin Harrison: >> valid for an Intel EP80579. Is there a way I can validate that this CPU >> will work with the existing CAR code? >> >> I've gone so far as doing a code-n-pray conversion, but my linux boot >> hangs at "Jumping to Entry" and running memtest causes it to bork on >> Test #2 with an unhandled interrupt. > That's already _very_ far as much as CAR is concerned. Usually, if CAR > fails, you either see nothing but a couple of post codes, or have the > system fail when decompressing ramstage at the latest (because RAM init > failed for some reason). > > Yes, sounds to me more like a raminit issue more than a CAR issue. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] motherboards support SMM
On 10/23/2010 05:16 PM, Keith Hui wrote: Why are you so interested in SMM? As I mentioned above, coreboot will avoid using SMM unless it is a requirement for a particular platform. If you want to add SMM to a platform where it is not used currently (and thus not required for coreboot) then it seems that you you have a lot of research and development ahead of you. Is it possible to have ACPI support for a board without SMM? Sure can, it may have some limits though without a SMI Handler (SMM). -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] motherboards support SMM
On 10/22/2010 06:40 PM, fengwei zhang wrote: Hi guys, I just went through most of the motherboards on coreboot webpage http://www.coreboot.org/Supported_Motherboards I found only motherboard with Intel® ICH7 southbridge supports SMM. For these motherboards, they will set the CONFIG_HAVE_SMI_HANDLER=y the motherboards with Intel® 82801 series don't support SMM, because the CONFIG_HAVE_SMI_HANDLER was not setted after configuration and it will have compile errors if you set that flag manually. In addition, most of motherboard with Intel ICH7 will have compile errors, there is only one mainboard will successfully compile and generate the coreboot.rom It is Intel D945GCLF motherboard. The source code I used is coreboot v4 lastest version. It would be great if someone could confirm this, thank you very much! Best, Fengwei Ahh ICH4 also supports SMM :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot doesn't compile smihandler.c smmhandler.S, even smm.h file, am I supposed to use other ways to compile SMM mode code?
On 10/21/2010 11:01 AM, fengwei zhang wrote: On Thu, Oct 21, 2010 at 10:52 AM, Joseph Smith mailto:j...@settoplinux.org>> wrote: On Thu, 21 Oct 2010 09:50:44 -0400, fengwei zhang mailto:namedy...@gmail.com>> wrote: > Hi, > > It seems like coreboot doesn't compile smihandler.c, smmhandler.S, even > smm.h file. I tried to put some junk into these files, and then make the > coreboot source code. it could still build the coreboot.rom image. In other > words, coreboot BIOS doesn't use any code under src/cpu/x86/smm/. > Since SMM is a special mode, am I supposed to use other ways to compile SMM > mode code? > Thank you very much! > > Well that is really not good! What kind of board are you trying to compile it for? I am trying to compile it on ASUS M2V-MS SE. My coreboot image works, but it seem like it doesn't include any SMM code. Am I supposed to use other ways to compile the coreboot(not just do "Make"), then I could compile SMM code into my BIOS? Ahh, I am pretty sure the smm code was writen for Intel chipsets It would be interesting to see it run with both Intel and AMD though -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot doesn't compile smihandler.c sm mhandler.S, even smm.h file, am I supposed to use other ways to compile SMM mode code?
On Thu, 21 Oct 2010 09:50:44 -0400, fengwei zhang wrote: > Hi, > > It seems like coreboot doesn't compile smihandler.c, smmhandler.S, even > smm.h file. I tried to put some junk into these files, and then make the > coreboot source code. it could still build the coreboot.rom image. In other > words, coreboot BIOS doesn't use any code under src/cpu/x86/smm/. > Since SMM is a special mode, am I supposed to use other ways to compile SMM > mode code? > Thank you very much! > > Well that is really not good! What kind of board are you trying to compile it for? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Convert all Intel i810 boards to CAR
On 10/14/2010 06:27 PM, Uwe Hermann wrote: On Thu, Oct 14, 2010 at 08:58:35AM -0700, Stefan Reinauer wrote: On 14.10.2010, at 05:38, Joseph Smith wrote: Anyways why can't cpu specific features be implemented at the model level and not at the socket level??? Because SSE, SSE2 and MMX are not CPU specific features in this context. SSE and MMX determine how many registrers are available for romcc. It describes the lowest common denominator between all CPUs in a socket. If one model selects SSE and another one does not, it will still be enabled, thus breaking every other CPU you can put in that socket. Yep. Maybe we should drop those flags from Kconfig completely and just set the right ROMCCFLAGS in the socket's makefile to remove any confusion about the meaning of thos flags. It's worth considering IMHO, yes. Or, actually, since sooner or later many chipsets will convert to TINYBOOTBLOCK and CAR (at least that's the plan I think), romcc will only ever be used for the bootblock, right? And that's pretty tiny hopefully and should work just fine with 386 as romcc option? Do we actually really have any measurable advantages from using romcc options other than 386 in that case? Same for RAM test -- it's not a memtest86 replacement, just a quick "Did I screw up RAM init" test, which doesn't get run very often after the RAM init code is finished / working. Does the RAM test speed really matter much here? Shall we just use 386 for ROMCC everywhere (and not use SSE2 for ramtest) and get rid of the MMX/SSE/SSE2 config options? Good point Uwe, I like how you think :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Convert all Intel i810 boards to CAR
On 10/14/2010 08:35 AM, Joseph Smith wrote: On 10/13/2010 03:00 PM, Uwe Hermann wrote: Hi, patch is committed with Peter's ack in r5949 as it's not really directly related to this discussion and also boot-tested by me on MSI MS-6178 as mentioned in the patch description. On Wed, Oct 13, 2010 at 09:50:52AM -0400, Joseph Smith wrote: On 10/13/2010 01:24 AM, Warren Turkal wrote: On Tuesday 12 October 2010 19:22:43 Joseph Smith wrote: FC-PGA's support SSE2 while the PGA's do not. that is the difference. I created FC_PGA370 to make the CAR coversion simpler. Hope that helps. I must be misunderstanding this entirely. First, you say there is a difference in that the FC version support SSE2. Then, you say that the FC_PGA370 socket is simply a mechanism to make conversion to CAR easier. Hm, this stuff may need some clarification and/or fixing in coreboot indeed. As far as I can see, e.g. from http://www.cpu-world.com/Sockets/Socket%20370%20%28PGA370%29.html there were 3 different sockets named socket370, all of which were physically compatible, but not electrically. I'm not so sure about the naming, but these seem to be the different packages / form factors of the sockets: - Plastic pin grid array (PPGA) - Flip-chip pin grid array (FC-PGA) - Flip-chip pin grid array (FC-PGA2) (http://en.wikipedia.org/wiki/Socket_370) Now, whether or not we need or want different socket_* directories for these I'm not sure yet, probably needs some investigation. However, as we're switchting all CPUs/boards to CAR sooner or later, having an extra dir just for the CAR (vs. ROMCC) version of the socket will not be required. As for SSE/SSE2, that seems to be a mess in coreboot too right now. Yes. I would like to see a common socket for all three maybe just socket_370 (Socket 370 is all that is in most mainboard vendor descriptions)?. There must be some way to probe and detect what features the cpu has and include the features based in that? Maybe a simple table with the model numbers? Anyways why can't cpu specific features be implemented at the model level and not at the socket level??? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Convert all Intel i810 boards to CAR
On 10/13/2010 03:00 PM, Uwe Hermann wrote: Hi, patch is committed with Peter's ack in r5949 as it's not really directly related to this discussion and also boot-tested by me on MSI MS-6178 as mentioned in the patch description. On Wed, Oct 13, 2010 at 09:50:52AM -0400, Joseph Smith wrote: On 10/13/2010 01:24 AM, Warren Turkal wrote: On Tuesday 12 October 2010 19:22:43 Joseph Smith wrote: FC-PGA's support SSE2 while the PGA's do not. that is the difference. I created FC_PGA370 to make the CAR coversion simpler. Hope that helps. I must be misunderstanding this entirely. First, you say there is a difference in that the FC version support SSE2. Then, you say that the FC_PGA370 socket is simply a mechanism to make conversion to CAR easier. Hm, this stuff may need some clarification and/or fixing in coreboot indeed. As far as I can see, e.g. from http://www.cpu-world.com/Sockets/Socket%20370%20%28PGA370%29.html there were 3 different sockets named socket370, all of which were physically compatible, but not electrically. I'm not so sure about the naming, but these seem to be the different packages / form factors of the sockets: - Plastic pin grid array (PPGA) - Flip-chip pin grid array (FC-PGA) - Flip-chip pin grid array (FC-PGA2) (http://en.wikipedia.org/wiki/Socket_370) Now, whether or not we need or want different socket_* directories for these I'm not sure yet, probably needs some investigation. However, as we're switchting all CPUs/boards to CAR sooner or later, having an extra dir just for the CAR (vs. ROMCC) version of the socket will not be required. As for SSE/SSE2, that seems to be a mess in coreboot too right now. Yes. I would like to see a common socket for all three maybe just socket_370 (Socket 370 is all that is in most mainboard vendor descriptions)?. There must be some way to probe and detect what features the cpu has and include the features based in that? Maybe a simple table with the model numbers? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Convert all Intel i810 boards to CAR
On 10/13/2010 01:24 AM, Warren Turkal wrote: On Tuesday 12 October 2010 19:22:43 Joseph Smith wrote: FC-PGA's support SSE2 while the PGA's do not. that is the difference. I created FC_PGA370 to make the CAR coversion simpler. Hope that helps. I must be misunderstanding this entirely. First, you say there is a difference in that the FC version support SSE2. Then, you say that the FC_PGA370 socket is simply a mechanism to make conversion to CAR easier. Does that mean that FC_PGA370 is simply PGA370 + CAR, or do PGA370 sockets really not support SSE2 chips? Researching it a little bit, I see that FC-PGA370 is a mechanically compatible socket, so I guess that the FC-PGA370 supports chips that the PGA370 does not. Is that correct? So FC-PGA is more than just an upgrade CAR? Yes, socket wise they are backwars compatable in 99% of boards. The PGA's were 66MHz FSB Celerons with 128k L2 cache. So I guess I would be satisfied if I knew that the minimum size l2 cache for a chip that fits in the PGA370 was 4K since that's what the patch says and since that's really what matters for the DCACHE_RAM_SIZE. Also, are we sure that the DCACHE_RAM_BASE used will work? I.e. has it been tested on real hardware? Also, if we have real hardware running that works with this. Would if be possible to get a the register output for a cpuid 0x8006 call? I'd just like to know if it would work on that processor since that call can be used to dynamically determine the amount of l2 cache. I've been thinking about adding that to the intel/amd/via CAR implementations so that DCACHE_RAM_SIZE doesn't need to be set. I'm sure CAR will work on the PGA's, although they may need Keith's L2 patch. More or less it was decided a while ago to split the model_6xx romcc clump-o-crap out into their own CAR model directories (starting with model_68x). I have a bunch of Socket 370 processors (FC-PGA and PGA) I plan on testing on my i810 board... I just have alot on my plate at this time. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Convert all Intel i810 boards to CAR
On 10/12/2010 09:51 PM, Warren Turkal wrote: Nack for the time being. I think this needs a little discussion. Is the FC_PGA370 socket different than the PGA370 socket? If they are different, do they take the same processors? I ask because the DCACHE_* config options in your patch are different than the options in the FC_PGA370 socket. Thanks, wt On Tuesday 12 October 2010 15:08:22 Uwe Hermann wrote: See patch. Uwe. FC-PGA's support SSE2 while the PGA's do not. that is the difference. I created FC_PGA370 to make the CAR coversion simpler. Hope that helps. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Move d810e2cb to tiny boot block.
On 10/08/2010 05:18 AM, Warren Turkal wrote: I just tried building the d810e2cb board with a tiny boot block. It builds! Ship it! :) Joseph, I see that you did the work on romstage.c on that board. Would you be able to test this patch to make sure it works? If anyone else has this board, I'd appreciate the testing. Thanks, wt 8<- Signed-off-by: Warren Turkal --- src/mainboard/intel/d810e2cb/Kconfig |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/mainboard/intel/d810e2cb/Kconfig b/src/mainboard/intel/d810e2cb/Kconfig index 8c6c76b..6d407d2 100644 --- a/src/mainboard/intel/d810e2cb/Kconfig +++ b/src/mainboard/intel/d810e2cb/Kconfig @@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_512 select HAVE_MAINBOARD_RESOURCES select GFXUMA + select TINY_BOOTBLOCK config MAINBOARD_DIR string Hello Warren, Unfortunately I do not have alot of coreboot time right now, but I will try to test it this next week sometime. Yes I am the one who wrote the code for this board; it is my freenas box at the moment :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Unsupported software interrupt #0x42
On 09/15/2010 03:24 PM, Tadas S wrote: Hello, 02.238: Calling Option ROM... 03.227: Unsupported software interrupt #0x42 eax 0x7 03.232: int42 call returned error. 04.804: ... Option ROM returned. It's coreboot serial output with timestamps. Since I don't know much here, I would like to ask if int0x42 is the same as int0x10 and if we could assume the same handler for both of them to avoid such error? Thanks, Tadas S. Yes int42 is the alternate of int10 -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Top Makefile
On Wed, 4 Aug 2010 19:07:38 +0430, ali hagigat
wrote:
> When we execute the command:
> make
> What rule will be executed?
>
> We know that compiling and linking c/assembly files by GNU gcc tool
produce
> object files with specific formats like elf, COFF,How the final
> Coreboot
> image is not in those formats, means it is not in elf, COFF formats? It
is
> an executable file.
Can you please explain why you are so interested in coreboot's
build("make") process?
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] cleanup CAR code
On Tue, 03 Aug 2010 19:14:51 +0200, Stefan Reinauer wrote: > New version, also drop unused CAR descriptors from romstage GDT. Yeah, I really like the macros, it makes it easier to read. I would like to test it first before I ack it. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] error in FILO configuration
On Tue, 3 Aug 2010 18:46:59 +0430, ali hagigat wrote: > I have FILO source code in: /root/build/coreboot/filo > and COREBOOT source code is in: /root/build/coreboot/coreboot-v4 > > When i execute the instruction below, it is followed by an error: > /root/build/coreboot/filo> make menuconfig > Libpayload config for FILO. > can't find file /root/build/coreboot/filo/../libpayload/Config.in > make: *** [menuconfig] Error 1 > > How can i correct it? > You need libpayload first. Please follow instructions on the wiki: http://www.coreboot.org/FILO -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [commit] r5680 - in trunk/src: northbr idge/intel/i82830 northbridge/via/cn400 northbridge/via/cn700 northbridge/via/cx700 northbridge/via/vt8623 northbridge/via /vx800 southbridge/amd
On Tue, 03 Aug 2010 11:34:27 +0200, Stefan Reinauer wrote: > On 8/2/10 5:14 PM, repository service wrote: >> Author: myles >> Date: Mon Aug 2 17:14:13 2010 >> New Revision: 5680 >> URL: https://tracker.coreboot.org/trac/coreboot/changeset/5680 >> >> Log: >> Build VGA code conditionally to avoid errors when using SeaBIOS. >> >> Signed-off-by: Myles Watson >> Acked-by: Kevin O'Connor >> >> Modified: >>trunk/src/northbridge/intel/i82830/Makefile.inc >>trunk/src/northbridge/via/cn400/Makefile.inc >>trunk/src/northbridge/via/cn700/Makefile.inc >>trunk/src/northbridge/via/cx700/Makefile.inc >>trunk/src/northbridge/via/vt8623/Makefile.inc >>trunk/src/northbridge/via/vx800/Makefile.inc >>trunk/src/southbridge/amd/cs5530/Makefile.inc > > I'm not too happy with this change. > > - the change definitely breaks the i82830 MBI code OOhh, we can't have this happening. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] drop CONFIG_USE_PRINTK_IN _CAR and CONFIG_USE_INIT
On Sun, 01 Aug 2010 20:01:19 +0200, Stefan Reinauer wrote: > See patch. As far as the CONFIG_USE_INIT, if nothing is using it and we have no tester for the ASROCK...I say drop it and the associated code. Acked by: Joseph Smith -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] fix potential smm security hole
On Thu, 29 Jul 2010 17:47:12 +0200, Stefan Reinauer wrote: > This patch resulted from a security review of coreboot's SMM handler. > Feedback appreciated. > > Regards, > Stefan Hello Stefan, I thought the SMM Handler already lived at 0xa instead of TSEG or HSEG. I don't really understand where the security hole is? Can you explain a little more in depth? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] #167: Support for new ION2 (Intel NM10 chipset)
On Mon, 26 Jul 2010 17:37:27 -0700, Corey Osgood wrote: > Anyways, here's a > link to the board I'm working on: > > http://www.zotacusa.com/zotac-nm10-b-e-atom-d510-1-66-ghz-dual-core-mini-itx-wifi-intel-motherboard-283.html > > The package I bought (from Newegg) has the built-in NM-10 video > onboard, and also includes a PCI-E 1x ION graphics card. I will try to > get both working. > Sweet! Good Luck Corey :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Convert Geode GX2 boards to CAR
On 07/21/2010 05:20 PM, Nils wrote: This patch converts the Geode GX2 boards to CAR. It reduces the boot time with ~35 seconds in "Stage: loading fallback/coreboot_ram". After the conversion GCC gave a lot of build warnings in the old ROMCC code (especially in the southbridge CS5535 code used by the Lippert Frontrunner board) which i had to fix. It is ABUILD tested and boot tested on my Wyse S50. Signed-off-by: Nils Jacobs Acked-by: Joseph Smith V2: Add newline at end of file src/cpu/amd/model_gx2/Makefile.inc.(thanks to Peter for spotting this) Remove unused code in src/southbridge/amd/cs5535/ . Thanks Nils, r5669. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] CentraLUG meeting, 2 August
On 07/24/2010 08:30 PM, ron minnich wrote: I like to give a demo of a build, just so people can see the Kconfig interface and how quickly it goes. I'm been told EFI takes *hours* to build, for example. Coreboot is a nice contrast. Ok, good idea. I am also bringing some boards for a live demo :-) By the way Ron, is there a page on the wiki or somewhere that gives a little history I can use? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] CentraLUG meeting, 2 August
On 07/24/2010 01:12 AM, ali hagigat wrote: You can talk about the Makefile too. How Coreboot is built in a typical scenario and by what tools. You mean Kconfig and crossgcc? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] CentraLUG meeting, 2 August
Brief summary about the presentation: 1. I plan on speaking a litle about myself, and how I got involved in coreboot (elaborate on above). 2. Give a brief history on coreboot and how it started. 3. Go over some of the features of coreboot. 4. Go over some of the great tools that have sprouted off of the coreboot tree. 5. Talk about how the code process flows and how you(audiance) can start to develop coreboot. 6. Open for Question and Answer time. -- Do you guys think there is anything else I should touch on? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Roda RK886EX troubles
On 07/22/2010 02:47 AM, Vitaly Chertovskih wrote: >>On 7/20/10 8:17 AM, Vitaly Chertovskih wrote: >> Hi! >> >> I'm experiencing some troubles in installing coreboot on Roda RK886EX. >> Please, help me. > >> Is there some manual about installation coreboot on Roda? >> >> I build coreboot, choosing Roda motherboard, adding compiled SeaBIOS >> image (I download it from coreboot.org <http://coreboot.org/> <http://coreboot.org <http://coreboot.org/>>), and >> including VGA onboard rom, grabbed from /dev/mem as described in >> howtos on coreboot.org <http://coreboot.org/> <http://coreboot.org <http://coreboot.org/>>. But, after flashing >> using flashrom, nothing happens. Screen blinks once, and nothing >> happens at all. >> >> I include my .config file, maybe it helps... >> >> Please, help me. What am I doing wrong? >Can you please send a serial console log along? >Stefan Attaching serial port log. Thanks! At first glance, it looks like there is something wrong with your mtrr setup. Maybe something weird about memory region allocations. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Convert Geode GX2 boards to CAR
On 07/16/2010 03:35 PM, Nils wrote: Hi Joseph, Op vrijdag 16 juli 2010 14:41:47 schreef u: On Tue, 6 Jul 2010 20:27:12 +0200, Nils wrote: Ping!? Could anybody tell me how to proceed? Peter:did i gave the wrong answers? :) Thanks,Nils. Nils, I really would hate to see your great work go to the way side. It has been a few revisions since your original patch. As long as you can send a working/tested updated patch to the list: Acked-by: Joseph Smith Thanks for the heads up! At the moment i have no time to update/test the patch, maybe in a few days. I will delete the unused code if til then nobody speaks up/ objects. And add the new line in Makefile.inc . Maybe until then Peter finds some time to give some professional advice. Thanks again for the ack. No problem, I have a few GX2's myself that have coreboot writen on them but way to many other things going on now to study code vs datasheets to get familiar with the GX2. Like I said I would hate for you code to go to the way side. P.s. How is your paraflasher project doing? Do you have some programming results already? No programming yet; still working on hardware design, I decided to make my own pcb's for it, something I have wanted to do for a long time. I have designed it with the gEDA tools (gschem, gsch2pcb, and PCB) which I have come to Love. Anyways the final harware should be kick ass. I have the programming for it in my head, just nothing on paper yet. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Convert Geode GX2 boards to CAR
On Tue, 6 Jul 2010 20:27:12 +0200, Nils wrote: > Ping!? > Could anybody tell me how to proceed? > Peter:did i gave the wrong answers? :) > > Thanks,Nils. > Nils, I really would hate to see your great work go to the way side. It has been a few revisions since your original patch. As long as you can send a working/tested updated patch to the list: Acked-by: Joseph Smith -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] What have I missed?
On Fri, 16 Jul 2010 06:02:32 -0400, Corey Osgood wrote: > It's been a while since I've read the list, and I've got a new project > going on and I'm trying to get back up to speed. I see there's now a > v4, currently checking it out but it looks a lot like the v2 code with > the v3 build system, is that about right? If so, sorry I wasn't around > to help out with the merge. What's the current state of CAR on > non-AMD64 CPUs, is the C7 implementation working reliably now? Does it > work on Nano? How about Atom? Anything else I should know about before > diving in? > Welcome back Corey :-) Good to hear from you. We now have CAR running on the Intel CPU's. Not all of the 440bx's and Socket 370's have been converted yet. I am currectly working on the 370's. We have a pending patch for CAR on Geode GX2. Yes v3 is kind of abandone, and we jumped to v4. v4 has same basic structure as v2 but we are now using Kconfig for our build system, don't get me wrong though... alot has changed sinse v2 so dive in:-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Uncommitted GPIOs
On 07/14/2010 05:00 PM, Peter Stuge wrote: Gregg C Levine wrote: Would anyone be able to confirm this line of reasoning? For anything based on the X86 design styles, only the GEODE families have these uncommitted GPIO points that are documented. I think there's more to the story. But do the Intel designed chipsets contain undocumented GPIO points? Yes, and many if not all superio chips have documented GPIO pins. Intel northbridges have GPIO lines in the integrated graphics display (IGD). Not usually documented in datasheets. Intel southbridges also have GPIO lines. And every SuperIO has many GPIO lines. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] warnings
On 07/07/2010 11:10 AM, Myles Watson wrote: Kill a few more warnings. Signed-off-by: Myles Watson Thanks, Myles Acked-by: Stefan Reinauer Rev 5656. Ah, thanks Myles, I actually had alot of those changes already in my ICH2 Overhaul coming soon. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] The firmware traps in SIS6xx/7xx/96x type chipsets
On Tue, 6 Jul 2010 16:50:21 +0300, "r. ozgur doruk" wrote: > Hello, > > I have Pentium4 laptop motherboard of which BIOS chip is soldered out by > some guys and it doesn't read newly programmed bios chip (a SST49lf080a) as > far as I understand since it even does not beep. And no harddisk signal, no > video and so on. In order to diagnose I have written a VHDL code (citing > Andy Green's Milksop experiment) and then program my code on a Xilinx CPLD > and connect it to the LPC debug board connector on the motherboard which > has > the signals LAD0 - 3, LRST, LFRAME, LCLK. The job of my VHDL code is to > convert the LPC protocol to a parallel address and data combination so that > I can at least trace what the motherboard responds. When I do that, if I > give a long sync to the motherboard after the first address is received by > the PLD I understand that the motherboard starts to fetch the flash codes > from the adress 0xFFD0. In fact this conforms to the script written by > the current coreboot developer as the SIS 966 has a firmware trap in the > memory region starting from 0xFFD0. When I operate the system giving a > ready sync after each address reception to the PLD the system runs until > showing 0xFFDF and the value stays in the CPLD address output busses. > The same thing is observed when the board is operated without the CPU in > its > socket. > > I operate the mainboard without the CPU using a small hack connecting one > of > the VID pins to the ground, thermal diode output to the vcc core, sckocc to > the ground and thermtrip to the vcc core. By that board thinks that CPU is > connected. > > The interesting thing is that, when I measure the powergood and the reset > inputs to the processor (by plugging the wires to the wholes as no > processor > is there). After the PLD address output is 0xFFDF both RESET and > POWERGOOD inputs become active so I think that the southbridge/northbridge > mechanism is alive. I also measured all of the processor socket holes one > by > one and found no problematic conditions on the socket contacts. > > The processor is heating up when operated without the heat sink and I also > noticed that thermtrip mechanism is also working as it shutdown after a > high > value of temperature. Because of that I think that the processor is > defective but again I can not be sure about that because of this firmware > trap feature of the chipsets I mention. So are those firmware traps in the > SIS chipsets are effective on the boot process of the processor? Or any > other reasons? > > Can I hear about your ideas? > > Thanks for all considerations > Very cool idea. I think SerialICE debugging may be alot easier, give you better results, and alot more information. http://www.serialice.com -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot on Dell c600
On Wed, 30 Jun 2010 09:30:20 +0200, CybFr wrote: > Hello, > > I tried to port coreboot to c610 but stopped at desoldering flash step... > So I > have a board, it boots with dell bios (I tried yesterday) and I can give it > to > the cause (I have another c610 on wich I will love to run coreboot). > > Any ideas to minimize send costs ?? (I'm in France) > Hello, I would love to port the C610. I am particularly interested because I would love to see AGP support for the Intel 830M, plus of course coreboot running on a laptop :-) Let me know if this works for you, I am located in the US. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Error creating thumbnail: libgomp: Thread creation failed: Resource temporarily unavailable
On Mon, 28 Jun 2010 11:17:34 +0200, Stefan Reinauer wrote: > On 6/28/10 5:08 AM, Joseph Smith wrote: >> I am getting this error on the wiki: >> >> http://www.coreboot.org/File:Paraflashersch.jpg >> >> any ideas? >> > > http://www.coreboot.org/pipermail/coreboot/2009-March/046030.html > > fixed, again, by increasing memory further. > Oh yeah, thanks again Stefan :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Error creating thumbnail: libgomp: Thread creation failed: Resource temporarily unavailable
I am getting this error on the wiki: http://www.coreboot.org/File:Paraflashersch.jpg any ideas? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Convert Geode GX2 boards to CAR
On 06/27/2010 06:06 PM, Nils wrote: This patch converts the Geode GX2 boards to CAR. It reduces the boot time with ~35 seconds in "Stage: loading fallback/coreboot_ram". After the conversion GCC gave a lot of build warnings in the old ROMCC code (especially in the southbridge CS5535 code used by the Lippert Frontrunner board) which i had to fix. It is ABUILD tested and boot tested on my Wyse S50. Signed-off-by: Nils Jacobs Patch and bootlog attached. I hope someone will find some time to review this rather large patch. Thanks,Nils. Sweet! -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] How to change the device id of a VBIOS
On Fri, 25 Jun 2010 09:06:23 +0200, Peter Stuge wrote: > Bao, Zheng wrote: >> I am wondering, if I got a Vgabios for graphics card A, can I just >> change the device ID in the binary file to fit the graphics B? > > If the code is the same, sure. > > >> Is there any checksum in the vgabios.bin? > > Yes. Option ROMs follow a well defined standard. > Hello, I had to do this to get my i810 vbios running on i810e because they have different device id's but use the same vbios. So what I did is just use a hex editor and change the device id to the correct one. But then SeaBIOS would complain about the incorrect checksum. I used Kevin's buildrom.py utility which basicly clears the lower 4 bits of the checksum which should be a 16 bit register at 0x07. This worked great for me, hope it helps you. > >> Is there a tool to handle it? > > Try tools/buildrom.py in the SeaBIOS repository at > git://git.linuxtogo.org/home/kevin/seabios.git > > http://git.linuxtogo.org/?p=kevin/seabios.git;a=blob;f=tools/buildrom.py > > -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [RFC] Network console for coreboot
On 06/22/2010 04:49 AM, Rudolf Marek wrote: Hi, I have done a ROMCC version too. Stay tuned. Btw this means that SerialICE over Ethernet is closer too. YAHOO! This is great news for serialice Rudolf :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
