Re: [edk2-devel] [Patch V3] MdeModulePkg: Retrive boot manager menu from any fv

[Ni, Ray]

Reviewed-by: Ray Ni 


> -Original Message-
> From: Liu, Zhiguang 
> Sent: Tuesday, May 11, 2021 10:32 AM
> To: devel@edk2.groups.io
> Cc: Wang, Jian J ; Wu, Hao A ;
> Gao, Zhichao ; Ni, Ray 
> Subject: [Patch V3] MdeModulePkg: Retrive boot manager menu from any fv
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3384
> 
> Currently, UefiBootManagerLib has the below assumption:
>   Assume the BootManagerMenuFile is in the same FV as the module links to
> this library.
> It has some limitation now, so remove the assumption.
> 
> Cc: Jian J Wang 
> Cc: Hao A Wu 
> Cc: Zhichao Gao 
> Cc: Ray Ni 
> Reviewed-by: Hao A Wu 
> Signed-off-by: Zhiguang Liu 
> ---
>  MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c | 9 +
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c
> b/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c
> index 6cc34d29c0..bef41ae102 100644
> --- a/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c
> +++ b/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c
> @@ -2,7 +2,7 @@
>Library functions which relates with booting.
> 
> 
> 
>  Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
> 
> -Copyright (c) 2011 - 2020, Intel Corporation. All rights reserved.
> 
> +Copyright (c) 2011 - 2021, Intel Corporation. All rights reserved.
> 
>  (C) Copyright 2015-2021 Hewlett Packard Enterprise Development LP
> 
>  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> 
> 
> @@ -2385,7 +2385,8 @@ EfiBootManagerRefreshAllBootOption (
>This function is called to get or create the boot option for the Boot 
> Manager
> Menu.
> 
> 
> 
>The Boot Manager Menu is shown after successfully booting a boot option.
> 
> -  Assume the BootManagerMenuFile is in the same FV as the module links to
> this library.
> 
> +  This function will first try to search the BootManagerMenuFile is in the
> same FV as
> 
> +  the module links to this library. If fails, it will search in all FVs.
> 
> 
> 
>@param  BootOptionReturn the boot option of the Boot Manager Menu
> 
> 
> 
> @@ -2437,7 +2438,7 @@ BmRegisterBootManagerMenu (
> 
> 
>if (DevicePath == NULL) {
> 
>  Data = NULL;
> 
> -Status = GetSectionFromFv (
> 
> +Status = GetSectionFromAnyFv (
> 
> PcdGetPtr (PcdBootManagerMenuFile),
> 
> EFI_SECTION_PE32,
> 
> 0,
> 
> @@ -2455,7 +2456,7 @@ BmRegisterBootManagerMenu (
>  //
> 
>  // Get BootManagerMenu application's description from EFI User
> Interface Section.
> 
>  //
> 
> -Status = GetSectionFromFv (
> 
> +Status = GetSectionFromAnyFv (
> 
> PcdGetPtr (PcdBootManagerMenuFile),
> 
> EFI_SECTION_USER_INTERFACE,
> 
> 0,
> 
> --
> 2.30.0.windows.2



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[edk2-devel] [PATCH] UefiCpuPkg/PiSmmCpu: Remove hardcode 48 address size limitation

[Ni, Ray]

5-level paging can be enabled on CPU which supports up to 52 physical
address size. But when the feature was enabled, the 48 address size
limit was not removed and the 5-level paging testing didn't access
address >= 2^48. So the issue wasn't detected until recently an
address >= 2^48 is accessed.

Change-Id: Iaedc73be318d4b4122071efc3ba6e967a4b58fc3
Signed-off-by: Ray Ni 
Cc: Eric Dong 
Cc: Laszlo Ersek 
Cc: Rahul Kumar 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 26 ++
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index fd6583f9d1..89143810b6 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -1887,11 +1887,13 @@ InitializeMpServiceData (
   IN UINTN   ShadowStackSize
   )
 {
-  UINT32Cr3;
-  UINTN Index;
-  UINT8 *GdtTssTables;
-  UINTN GdtTableStepSize;
-  CPUID_VERSION_INFO_EDXRegEdx;
+  UINT32  Cr3;
+  UINTN   Index;
+  UINT8   *GdtTssTables;
+  UINTN   GdtTableStepSize;
+  CPUID_VERSION_INFO_EDX  RegEdx;
+  UINT32  MaxExtendedFunction;
+  CPUID_VIR_PHY_ADDRESS_SIZE_EAX  VirPhyAddressSize;
 
   //
   // Determine if this CPU supports machine check
@@ -1918,9 +1920,17 @@ InitializeMpServiceData (
   // Initialize physical address mask
   // NOTE: Physical memory above virtual address limit is not supported !!!
   //
-  AsmCpuid (0x8008, (UINT32*), NULL, NULL, NULL);
-  gPhyMask = LShiftU64 (1, (UINT8)Index) - 1;
-  gPhyMask &= (1ull << 48) - EFI_PAGE_SIZE;
+  AsmCpuid (CPUID_EXTENDED_FUNCTION, , NULL, NULL, NULL);
+  if (MaxExtendedFunction >= CPUID_VIR_PHY_ADDRESS_SIZE) {
+AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, , NULL, 
NULL, NULL);
+  } else {
+VirPhyAddressSize.Bits.PhysicalAddressBits = 36;
+  }
+  gPhyMask  = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;
+  //
+  // Clear the low 12 bits
+  //
+  gPhyMask &= 0xf000ULL;
 
   //
   // Create page tables
-- 
2.31.1.windows.1



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Re: [edk2-devel][PATCH v5 1/7] IntelSiliconPkg/ReportCpuHobLib: Add ReportCpuHobLib

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty 

-Original Message-
From: Chuang, SofiaX  
Sent: Monday, May 10, 2021 12:54 PM
To: devel@edk2.groups.io
Cc: Chuang, SofiaX ; Ni, Ray ; 
Chaganty, Rangasai V 
Subject: [edk2-devel][PATCH v5 1/7] IntelSiliconPkg/ReportCpuHobLib: Add 
ReportCpuHobLib

From: SofiaX Chuang 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298

Add ReportCpuHobLib

Signed-off-by: SofiaX Chuang 
Cc: Ray Ni 
Cc: Rangasai V Chaganty 
---
 .../Include/Library/ReportCpuHobLib.h | 27 +
 .../Intel/IntelSiliconPkg/IntelSiliconPkg.dec |  6 ++-  
.../Intel/IntelSiliconPkg/IntelSiliconPkg.dsc |  1 +  
.../Library/ReportCpuHobLib/ReportCpuHobLib.c | 39 +++
 .../ReportCpuHobLib/ReportCpuHobLib.inf   | 26 +
 5 files changed, 98 insertions(+), 1 deletion(-)  create mode 100644 
Silicon/Intel/IntelSiliconPkg/Include/Library/ReportCpuHobLib.h
 create mode 100644 
Silicon/Intel/IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.c
 create mode 100644 
Silicon/Intel/IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf

diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Library/ReportCpuHobLib.h 
b/Silicon/Intel/IntelSiliconPkg/Include/Library/ReportCpuHobLib.h
new file mode 100644
index 00..106ab3d436
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/ReportCpuHobLib.h
@@ -0,0 +1,27 @@
+/** @file++  Report CPU HOB library++  This library report the CPU HOB 
+with Physical Address bits.++Copyright (c) 2021, Intel Corporation. All 
+rights reserved.+SPDX-License-Identifier: 
+BSD-2-Clause-Patent++**/++#ifndef _REPORT_CPU_HOB_LIB_H_+#define 
+_REPORT_CPU_HOB_LIB_H_++#include ++/**+  Build a HOB for 
+the CPU.+**/+VOID+EFIAPI+ReportCpuHob (+  VOID+  );++#endif+diff --git 
+a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec 
+b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index 4a2cbca5c1..2461ab8e06 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -3,7 +3,7 @@
 # # This package provides common open source Intel silicon modules. #-# 
Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.+# 
Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved. # 
SPDX-License-Identifier: BSD-2-Clause-Patent # ##@@ -42,6 +42,10 @@
   #   AslUpdateLib|Include/Library/AslUpdateLib.h +  ## @libraryclass Provides 
services to report CPU hob+  #+  
ReportCpuHobLib|Include/Library/ReportCpuHobLib.h+ [Guids]   ## GUID for 
Package token space   # {A9F8D54E-1107-4F0A-ADD0-4587E7A4A735}diff --git 
a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc 
b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
index 5e0de7e19a..1092371d84 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
@@ -93,6 +93,7 @@
   IntelSiliconPkg/Library/PeiDxeSmmBootMediaLib/PeiFirmwareBootMediaLib.inf   
IntelSiliconPkg/Library/PeiDxeSmmBootMediaLib/DxeSmmFirmwareBootMediaLib.inf   
IntelSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf+  
IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf  [BuildOptions]   
*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACESdiff --git 
a/Silicon/Intel/IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.c 
b/Silicon/Intel/IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.c
new file mode 100644
index 00..3f67b477d2
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHob
+++ Lib.c
@@ -0,0 +1,39 @@
+/** @file+  Source code file for Report CPU HOB library.++Copyright (c) 2021, 
Intel Corporation. All rights reserved.+SPDX-License-Identifier: 
BSD-2-Clause-Patent++**/++#include +#include 
+#include +#include 
+++/**+  Build a HOB for the 
CPU.+**/+VOID+EFIAPI+ReportCpuHob (+  VOID+  )+{+  UINT8
   PhysicalAddressBits;+  CPUID_VIR_PHY_ADDRESS_SIZE_EAX  AddressSizeEax;++  
AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, , NULL, NULL, 
NULL);+  if (AddressSizeEax.Uint32 >= CPUID_VIR_PHY_ADDRESS_SIZE) {+
AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, , NULL, NULL, 
NULL);+PhysicalAddressBits = AddressSizeEax.Bits.PhysicalAddressBits;+  } 
else {+PhysicalAddressBits = 36;+  }++  ///+  /// Create a CPU hand-off 
information+  ///+  BuildCpuHob (PhysicalAddressBits, 16);+}diff --git 
a/Silicon/Intel/IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf 
b/Silicon/Intel/IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf
new file mode 100644
index 00..1d2d6b4151
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHob
+++ Lib.inf
@@ -0,0 +1,26 @@
+### @file+# Component information file for the Report CPU HOB library.+#+# 
Copyright (c) 2021, Intel Corporation. All rights reserved.+#+# 
SPDX-License-Identifier: BSD-2-Clause-Patent+#+###++[Defines]+  INF_VERSION 
   = 0x00010005+  BASE_NAME  = ReportCpuHobLib+ 
 FILE_GUID 

Re: [edk2-devel][PATCH v5 1/7] IntelSiliconPkg/ReportCpuHobLib: Add ReportCpuHobLib

[Ni, Ray]

Reviewed-by: Ray Ni 
> -Original Message-
> From: Chuang, SofiaX 
> Sent: Tuesday, May 11, 2021 3:54 AM
> To: devel@edk2.groups.io
> Cc: Chuang, SofiaX ; Ni, Ray ; 
> Chaganty, Rangasai V
> 
> Subject: [edk2-devel][PATCH v5 1/7] IntelSiliconPkg/ReportCpuHobLib: Add 
> ReportCpuHobLib
> 
> From: SofiaX Chuang 
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298
> 
> Add ReportCpuHobLib
> 
> Signed-off-by: SofiaX Chuang 
> Cc: Ray Ni 
> Cc: Rangasai V Chaganty 
> ---
>  .../Include/Library/ReportCpuHobLib.h | 27 +
>  .../Intel/IntelSiliconPkg/IntelSiliconPkg.dec |  6 ++-
>  .../Intel/IntelSiliconPkg/IntelSiliconPkg.dsc |  1 +
>  .../Library/ReportCpuHobLib/ReportCpuHobLib.c | 39 +++
>  .../ReportCpuHobLib/ReportCpuHobLib.inf   | 26 +
>  5 files changed, 98 insertions(+), 1 deletion(-)
>  create mode 100644 
> Silicon/Intel/IntelSiliconPkg/Include/Library/ReportCpuHobLib.h
>  create mode 100644 
> Silicon/Intel/IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.c
>  create mode 100644 
> Silicon/Intel/IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf
> 
> diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Library/ReportCpuHobLib.h
> b/Silicon/Intel/IntelSiliconPkg/Include/Library/ReportCpuHobLib.h
> new file mode 100644
> index 00..106ab3d436
> --- /dev/null
> +++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/ReportCpuHobLib.h
> @@ -0,0 +1,27 @@
> +/** @file
> 
> +
> 
> +  Report CPU HOB library
> 
> +
> 
> +  This library report the CPU HOB with Physical Address bits.
> 
> +
> 
> +Copyright (c) 2021, Intel Corporation. All rights reserved.
> 
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +
> 
> +**/
> 
> +
> 
> +#ifndef _REPORT_CPU_HOB_LIB_H_
> 
> +#define _REPORT_CPU_HOB_LIB_H_
> 
> +
> 
> +#include 
> 
> +
> 
> +/**
> 
> +  Build a HOB for the CPU.
> 
> +**/
> 
> +VOID
> 
> +EFIAPI
> 
> +ReportCpuHob (
> 
> +  VOID
> 
> +  );
> 
> +
> 
> +#endif
> 
> +
> 
> diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec 
> b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
> index 4a2cbca5c1..2461ab8e06 100644
> --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
> +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
> @@ -3,7 +3,7 @@
>  #
> 
>  # This package provides common open source Intel silicon modules.
> 
>  #
> 
> -# Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
> 
> +# Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
> 
>  # SPDX-License-Identifier: BSD-2-Clause-Patent
> 
>  #
> 
>  ##
> 
> @@ -42,6 +42,10 @@
>#
> 
>AslUpdateLib|Include/Library/AslUpdateLib.h
> 
> 
> 
> +  ## @libraryclass Provides services to report CPU hob
> 
> +  #
> 
> +  ReportCpuHobLib|Include/Library/ReportCpuHobLib.h
> 
> +
> 
>  [Guids]
> 
>## GUID for Package token space
> 
># {A9F8D54E-1107-4F0A-ADD0-4587E7A4A735}
> 
> diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc 
> b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
> index 5e0de7e19a..1092371d84 100644
> --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
> +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
> @@ -93,6 +93,7 @@
>IntelSiliconPkg/Library/PeiDxeSmmBootMediaLib/PeiFirmwareBootMediaLib.inf
> 
>
> IntelSiliconPkg/Library/PeiDxeSmmBootMediaLib/DxeSmmFirmwareBootMediaLib.inf
> 
>IntelSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf
> 
> +  IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf
> 
> 
> 
>  [BuildOptions]
> 
>*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
> 
> diff --git 
> a/Silicon/Intel/IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.c
> b/Silicon/Intel/IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.c
> new file mode 100644
> index 00..3f67b477d2
> --- /dev/null
> +++ b/Silicon/Intel/IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.c
> @@ -0,0 +1,39 @@
> +/** @file
> 
> +  Source code file for Report CPU HOB library.
> 
> +
> 
> +Copyright (c) 2021, Intel Corporation. All rights reserved.
> 
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> +
> 
> +**/
> 
> +
> 
> +#include 
> 
> +#include 
> 
> +#include 
> 
> +#include 
> 
> +
> 
> +
> 
> +/**
> 
> +  Build a HOB for the CPU.
> 
> +**/
> 
> +VOID
> 
> +EFIAPI
> 
> +ReportCpuHob (
> 
> +  VOID
> 
> +  )
> 
> +{
> 
> +  UINT8   PhysicalAddressBits;
> 
> +  CPUID_VIR_PHY_ADDRESS_SIZE_EAX  AddressSizeEax;
> 
> +
> 
> +  AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, , NULL, NULL, 
> NULL);
> 
> +  if (AddressSizeEax.Uint32 >= CPUID_VIR_PHY_ADDRESS_SIZE) {
> 
> +AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, , NULL, 
> NULL, NULL);
> 
> +PhysicalAddressBits = AddressSizeEax.Bits.PhysicalAddressBits;
> 
> +  } else {
> 
> +PhysicalAddressBits = 36;
> 
> +  }
> 
> +
> 
> +  ///
> 
> +  /// Create a CPU hand-off information
> 
> +  ///
> 
> +  BuildCpuHob (PhysicalAddressBits, 16);
> 
> +}
> 
> diff --git 
> 

[edk2-devel] TianoCore Bug Triage - APAC / NAMO - Tue, 05/11/2021 6:30pm-7:30pm #cal-reminder

[devel@edk2.groups.io Calendar]

*Reminder:* TianoCore Bug Triage - APAC / NAMO

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Re: [edk2-devel][PATCH v5 7/7] CometlakeOpenBoard: Move ReportCpuHob library path

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty 

-Original Message-
From: Chuang, SofiaX  
Sent: Monday, May 10, 2021 12:55 PM
To: devel@edk2.groups.io
Cc: Chuang, SofiaX ; Chiu, Chasel 
; Desimone, Nathaniel L 
; Chaganty, Rangasai V 
; Kethi Reddy, Deepika 
; Esakkithevar, Kathappan 

Subject: [edk2-devel][PATCH v5 7/7] CometlakeOpenBoard: Move ReportCpuHob 
library path

From: SofiaX Chuang 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298

Move ReportCpuHob library from MinPlatformPkg to IntelSiliconPkg.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Rangasai V Chaganty 
Cc: Deepika Kethi Reddy 
Cc: Kathappan Esakkithevar 
---
 .../CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc  | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git 
a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc 
b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc
index 6de834565a..44a1bd54d6 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc
@@ -1,7 +1,7 @@
 ## @file

 #  The main build description file for the CometlakeURvp board.

 #

-#  Copyright (c) 2020, Intel Corporation. All rights reserved.

+#  Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.

 #

 #  SPDX-License-Identifier: BSD-2-Clause-Patent

 #

@@ -161,6 +161,7 @@
   # Silicon Initialization Package

   ###

   
SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf

+  ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf

 

   ###

   # Platform Package

@@ -173,7 +174,6 @@
   
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf

 !endif

   
SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf

-  
ReportCpuHobLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf

 

   ###

   # Board Package

-- 
2.27.0



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Re: [edk2-devel][PATCH v5 2/7] TigerlakeOpenBoard: Move ReportCpuHob library path

[Chaganty, Rangasai V]

Reviewed-by: Sai Chaganty   

-Original Message-
From: Chuang, SofiaX  
Sent: Monday, May 10, 2021 12:54 PM
To: devel@edk2.groups.io
Cc: Chuang, SofiaX ; Chaganty, Rangasai V 
; Desimone, Nathaniel L 
; Luo, Heng 
Subject: [edk2-devel][PATCH v5 2/7] TigerlakeOpenBoard: Move ReportCpuHob 
library path

From: SofiaX Chuang 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298

Move ReportCpuHob library from MinPlatformPkg to IntelSiliconPkg.

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Heng Luo 
---
 .../Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc  | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc 
b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc
index a4265a839c..1adf634034 100644
--- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc
@@ -89,7 +89,6 @@
 

   
PciSegmentLib|$(PLATFORM_SI_PACKAGE)/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.inf

   PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf

-  
ReportCpuHobLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf

 

   #

   # Silicon Init Package

@@ -115,6 +114,7 @@
   #

   # Silicon Init Package

   #

+  ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf

   !include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc

 

   #

-- 
2.27.0



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Re: [edk2-devel] [PATCH v2] BaseTools: Add support for version 3 of FMP Image Header structure

[Bob Feng]

I created the PR https://github.com/tianocore/edk2/pull/1637 for merge.

Thanks,
Bob

From: Kinney, Michael D 
Sent: Tuesday, May 11, 2021 11:09 PM
To: Sughosh Ganu ; Feng, Bob C ; 
Liming Gao ; Chen, Christine ; 
Kinney, Michael D 
Cc: devel@edk2.groups.io
Subject: RE: [edk2-devel] [PATCH v2] BaseTools: Add support for version 3 of 
FMP Image Header structure

Hi Sughosh,

Thanks for the reminder.

We need to wait for one of the BaseTools maintainers to provide an Rb for the 
V2 version of this patch, then we will be able to merge.

Thanks,

Mike

From: Sughosh Ganu mailto:sughosh.g...@linaro.org>>
Sent: Tuesday, May 11, 2021 3:21 AM
To: Kinney, Michael D 
mailto:michael.d.kin...@intel.com>>; Feng, Bob C 
mailto:bob.c.f...@intel.com>>; Liming Gao 
mailto:gaolim...@byosoft.com.cn>>; Chen, Christine 
mailto:yuwei.c...@intel.com>>
Cc: devel@edk2.groups.io
Subject: Re: [edk2-devel] [PATCH v2] BaseTools: Add support for version 3 of 
FMP Image Header structure

hi,
Can this patch be merged. Thanks.

-sughosh

On Mon, 26 Apr 2021 at 21:27, Kinney, Michael D 
mailto:michael.d.kin...@intel.com>> wrote:
Reviewed-by: Michael D Kinney 
mailto:michael.d.kin...@intel.com>>

Mike

> -Original Message-
> From: devel@edk2.groups.io 
> mailto:devel@edk2.groups.io>> On Behalf Of Sughosh Ganu
> Sent: Friday, April 23, 2021 4:29 AM
> To: devel@edk2.groups.io
> Cc: Michal Simek mailto:michal.si...@xilinx.com>>; 
> Sughosh Ganu mailto:sughosh.g...@linaro.org>>
> Subject: [edk2-devel] [PATCH v2] BaseTools: Add support for version 3 of FMP 
> Image Header structure
>
> Add support for the ImageCapsuleSupport field, introduced in version 3
> of the EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER structure. This
> structure member is used to indicate if the corresponding payload has
> support for authentication and dependency.
>
> Signed-off-by: Sughosh Ganu 
> mailto:sughosh.g...@linaro.org>>
> ---
>
> Changes since v1:
> - Reword the patch header to get rid of the PatchCheck warning
> - Make passing of ImageCapsuleSupport parameter to the AddPayload
>   function as an optional parameter to maintain backward compatibility
> - Declare the values of CAPSULE_SUPPORT_DEPENDENCY and
>   CAPSULE_SUPPORT_AUTHENTICATION in the FmpCapsuleHeaderClass and use
>   those in the GenerateCapsule script
>
>  .../Source/Python/Capsule/GenerateCapsule.py  |  5 +++-
>  .../Common/Uefi/Capsule/FmpCapsuleHeader.py   | 28 +--
>  2 files changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/BaseTools/Source/Python/Capsule/GenerateCapsule.py 
> b/BaseTools/Source/Python/Capsule/GenerateCapsule.py
> index a8de988253..b8039db878 100644
> --- a/BaseTools/Source/Python/Capsule/GenerateCapsule.py
> +++ b/BaseTools/Source/Python/Capsule/GenerateCapsule.py
> @@ -561,6 +561,7 @@ if __name__ == '__main__':
>  print ('GenerateCapsule: error:' + str(Msg))
>  sys.exit (1)
>  for SinglePayloadDescriptor in PayloadDescriptorList:
> +ImageCapsuleSupport = 0x
>  Result = SinglePayloadDescriptor.Payload
>  try:
>  FmpPayloadHeader.FwVersion  = 
> SinglePayloadDescriptor.FwVersion
> @@ -575,6 +576,7 @@ if __name__ == '__main__':
>  if SinglePayloadDescriptor.UseDependency:
>  CapsuleDependency.Payload = Result
>  CapsuleDependency.DepexExp = SinglePayloadDescriptor.DepexExp
> +ImageCapsuleSupport|= 
> FmpCapsuleHeader.CAPSULE_SUPPORT_DEPENDENCY
>  Result = CapsuleDependency.Encode ()
>  if args.Verbose:
>  CapsuleDependency.DumpInfo ()
> @@ -607,13 +609,14 @@ if __name__ == '__main__':
>  FmpAuthHeader.MonotonicCount = 
> SinglePayloadDescriptor.MonotonicCount
>  FmpAuthHeader.CertData   = CertData
>  FmpAuthHeader.Payload= Result
> +ImageCapsuleSupport  |= 
> FmpCapsuleHeader.CAPSULE_SUPPORT_AUTHENTICATION
>  Result = FmpAuthHeader.Encode ()
>  if args.Verbose:
>  FmpAuthHeader.DumpInfo ()
>  except:
>  print ('GenerateCapsule: error: can not encode FMP Auth 
> Header')
>  sys.exit (1)
> -FmpCapsuleHeader.AddPayload (SinglePayloadDescriptor.Guid, 
> Result, HardwareInstance =
> SinglePayloadDescriptor.HardwareInstance, UpdateImageIndex = 
> SinglePayloadDescriptor.UpdateImageIndex)
> +FmpCapsuleHeader.AddPayload (SinglePayloadDescriptor.Guid, 
> Result, HardwareInstance =
> SinglePayloadDescriptor.HardwareInstance, UpdateImageIndex = 
> SinglePayloadDescriptor.UpdateImageIndex, CapsuleSupport =
> ImageCapsuleSupport)
>  try:
>  for EmbeddedDriver in 

Re: [edk2-devel] [PATCH v2] BaseTools: Add support for version 3 of FMP Image Header structure

[Bob Feng]

This patch is good to me.
Reviewed-by: Bob Feng 


Thanks,
Bob

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Sughosh Ganu
Sent: Thursday, April 22, 2021 3:51 PM
To: devel@edk2.groups.io
Cc: Kinney, Michael D ; Feng, Bob C 
; Liming Gao ; Chen, Christine 
; Sughosh Ganu 
Subject: [edk2-devel] [PATCH v2] BaseTools: Add support for version 3 of FMP 
Image Header structure

Add support for the ImageCapsuleSupport field, introduced in version 3 of the 
EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER structure. This structure member 
is used to indicate if the corresponding payload has support for authentication 
and dependency.

Signed-off-by: Sughosh Ganu 
---

Changes since v1:
- Reword the patch header to get rid of the PatchCheck warning
- Make passing of ImageCapsuleSupport parameter to the AddPayload
  function as an optional parameter to maintain backward compatibility
- Declare the values of CAPSULE_SUPPORT_DEPENDENCY and
  CAPSULE_SUPPORT_AUTHENTICATION in the FmpCapsuleHeaderClass and use
  those in the GenerateCapsule script

 .../Source/Python/Capsule/GenerateCapsule.py  |  5 +++-
 .../Common/Uefi/Capsule/FmpCapsuleHeader.py   | 28 +--
 2 files changed, 24 insertions(+), 9 deletions(-)

diff --git a/BaseTools/Source/Python/Capsule/GenerateCapsule.py 
b/BaseTools/Source/Python/Capsule/GenerateCapsule.py
index a8de988253..b8039db878 100644
--- a/BaseTools/Source/Python/Capsule/GenerateCapsule.py
+++ b/BaseTools/Source/Python/Capsule/GenerateCapsule.py
@@ -561,6 +561,7 @@ if __name__ == '__main__':
 print ('GenerateCapsule: error:' + str(Msg))
 sys.exit (1)
 for SinglePayloadDescriptor in PayloadDescriptorList:
+ImageCapsuleSupport = 0x
 Result = SinglePayloadDescriptor.Payload
 try:
 FmpPayloadHeader.FwVersion  = 
SinglePayloadDescriptor.FwVersion
@@ -575,6 +576,7 @@ if __name__ == '__main__':
 if SinglePayloadDescriptor.UseDependency:
 CapsuleDependency.Payload = Result
 CapsuleDependency.DepexExp = SinglePayloadDescriptor.DepexExp
+ImageCapsuleSupport|= 
FmpCapsuleHeader.CAPSULE_SUPPORT_DEPENDENCY
 Result = CapsuleDependency.Encode ()
 if args.Verbose:
 CapsuleDependency.DumpInfo () @@ -607,13 +609,14 @@ if 
__name__ == '__main__':
 FmpAuthHeader.MonotonicCount = 
SinglePayloadDescriptor.MonotonicCount
 FmpAuthHeader.CertData   = CertData
 FmpAuthHeader.Payload= Result
+ImageCapsuleSupport  |= 
FmpCapsuleHeader.CAPSULE_SUPPORT_AUTHENTICATION
 Result = FmpAuthHeader.Encode ()
 if args.Verbose:
 FmpAuthHeader.DumpInfo ()
 except:
 print ('GenerateCapsule: error: can not encode FMP Auth 
Header')
 sys.exit (1)
-FmpCapsuleHeader.AddPayload (SinglePayloadDescriptor.Guid, Result, 
HardwareInstance = SinglePayloadDescriptor.HardwareInstance, UpdateImageIndex = 
SinglePayloadDescriptor.UpdateImageIndex)
+FmpCapsuleHeader.AddPayload (SinglePayloadDescriptor.Guid, 
+ Result, HardwareInstance = SinglePayloadDescriptor.HardwareInstance, 
+ UpdateImageIndex = SinglePayloadDescriptor.UpdateImageIndex, 
+ CapsuleSupport = ImageCapsuleSupport)
 try:
 for EmbeddedDriver in EmbeddedDriverDescriptorList:
 FmpCapsuleHeader.AddEmbeddedDriver(EmbeddedDriver)
diff --git a/BaseTools/Source/Python/Common/Uefi/Capsule/FmpCapsuleHeader.py 
b/BaseTools/Source/Python/Common/Uefi/Capsule/FmpCapsuleHeader.py
index 91d24919c4..8abb449c6f 100644
--- a/BaseTools/Source/Python/Common/Uefi/Capsule/FmpCapsuleHeader.py
+++ b/BaseTools/Source/Python/Common/Uefi/Capsule/FmpCapsuleHeader.py
@@ -47,14 +47,19 @@ class FmpCapsuleImageHeaderClass (object):
 #   /// therefore can be modified without changing the Auth data.
 #   ///
 #   UINT64   UpdateHardwareInstance;
+#
+#   ///
+#   /// Bits which indicate authentication and depex information for the 
image that follows this structure
+#   ///
+#   UINT64   ImageCapsuleSupport
 # } EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER;
 #
-#  #define EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER_INIT_VERSION 
0x0002
+#  #define 
+ EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER_INIT_VERSION 0x0003
 
-_StructFormat = '= len (self._FmpCapsuleImageHeaderList):
@@ -198,13 +209,14 @@ class FmpCapsuleHeaderClass (object):
 self._ItemOffsetList.append (Offset)
 Offset = Offset + len (EmbeddedDriver)
 Index = 1
-for (UpdateImageTypeId, Payload, VendorCodeBytes, HardwareInstance, 
UpdateImageIndex) in self._PayloadList:
+for (UpdateImageTypeId, Payload, 

Re: [edk2-devel] Build fails with VS2012

[Andrew Fish via groups.io]

I’m always happy to resolve any Xcode issues. 

Thanks,

Andrew Fish

> On May 11, 2021, at 7:41 AM, Laszlo Ersek  wrote:
> 
> On 05/11/21 02:14, Rebecca Cran wrote:
>> Thanks. The obvious toolchains that are missing from ReadMe.rst are any
>> versions of XCODE and CLANG.
>> Also, it might be nice to specify _which_ GCC5 versions are supported,
>> since that covers gcc 5 through 11 and gcc 5.x currently causes a build
>> error. We maybe only care about gcc 7 and newer these days?
>> 
>> I just tried building with VS2015 and VS2013, and there was a build
>> error because it seems the location of rc.exe has changed. After fixing
>> that they successfully built OVMF. But it sounds like we possibly only
>> want to make sure that VS2017 and VS2019 are kept working now.
>> 
>> I've cc'd Bret and Sean because I'm wondering if there are plans to add
>> more toolchain/OS combinations into the GitHub/Azure solution? For
>> example adding macOS with XCODE5? Also, how about post-commit or nightly
>> builds that run more extensive tests, possibly generating binaries for
>> OVMF that people can try without building it themselves? Or would that
>> be something that might be useful for me to implement as a third-party
>> solution?
>> 
> 
> Too many good questions!
> 
> Personally, I care for gcc-8, and later.
> 
> Thanks
> Laszlo
> 
> 
> 
> 



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[edk2-devel] [PATCH v1 2/2] OvmfPkg/VirtioFsDxe: suppress incorrect gcc warnings

[Sergei Dmitrouk]

`CreateDirectoryIfCreating` is used only if `PermitCreation` is set.

`NewNodeIsDirectory` might not set in case of error, but that would lead
to leaving the function before invalid use.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3228
Cc: Laszlo Ersek 
Cc: Ard Biesheuvel 
Cc: Jordan Justen 
Signed-off-by: Sergei Dmitrouk 
---
 OvmfPkg/VirtioFsDxe/SimpleFsOpen.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/OvmfPkg/VirtioFsDxe/SimpleFsOpen.c 
b/OvmfPkg/VirtioFsDxe/SimpleFsOpen.c
index d73d23fe8665..9e46e8ab8385 100644
--- a/OvmfPkg/VirtioFsDxe/SimpleFsOpen.c
+++ b/OvmfPkg/VirtioFsDxe/SimpleFsOpen.c
@@ -332,6 +332,12 @@ VirtioFsSimpleFileOpen (
 return EFI_INVALID_PARAMETER;
   }
 
+  //
+  // Set CreateDirectoryIfCreating to suppress incorrect compiler/analyzer
+  // warnings.
+  //
+  CreateDirectoryIfCreating = FALSE;
+
   //
   // Validate the Attributes requested for the case when the file ends up being
   // created, provided creation is permitted.
@@ -426,6 +432,11 @@ VirtioFsSimpleFileOpen (
 goto FreeNewCanonicalPath;
   }
 
+  //
+  // Set NewNodeIsDirectory to suppress incorrect compiler/analyzer warnings.
+  //
+  NewNodeIsDirectory = FALSE;
+
   //
   // Try to open LastComponent directly under DirNodeId, as an existent regular
   // file or directory.
-- 
2.17.6



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[edk2-devel] [PATCH v1 0/2] "maybe-uninitialized" warnings emitted by

[Sergei Dmitrouk]

Compiling for IA32 target with gcc-5.5.0 emits "maybe-uninitialized" warnings.
Compilation command: build -a IA32 -p OvmfPkg/OvmfPkgIa32.dsc -t GCC49

Sergei Dmitrouk (2):
  ShellPkg/UefiShellCommandLib: suppress incorrect gcc warning
  OvmfPkg/VirtioFsDxe: suppress incorrect gcc warnings

 OvmfPkg/VirtioFsDxe/SimpleFsOpen.c| 11 +++
 .../Library/UefiShellCommandLib/UefiShellCommandLib.c |  5 +
 2 files changed, 16 insertions(+)

-- 
2.17.6



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[edk2-devel] [PATCH v1 1/2] ShellPkg/UefiShellCommandLib: suppress incorrect gcc warning

[Sergei Dmitrouk]

`Dupes` is used only if `Duplicates != NULL` and function is left if
allocation of memory for `Dupes` fails, so it can't be used
uninitialized.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3228
Cc: Ray Ni 
Cc: Zhichao Gao 
Signed-off-by: Sergei Dmitrouk 
---
 ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.c 
b/ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.c
index b06d22592d33..81923c8ae737 100644
--- a/ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.c
+++ b/ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.c
@@ -2128,6 +2128,11 @@ ShellSortFileList (
 }
   }
 
+  //
+  // Set Dupes to suppress incorrect compiler/analyzer warnings.
+  //
+  Dupes = NULL;
+
   //
   // If separation of duplicates has been requested, allocate the list for
   // them.
-- 
2.17.6



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Re: [edk2-devel] [edk2-platforms] [PATCH V1 00/18] Reinstate Purley MinPlatform

[Nate DeSimone]

Thanks Isaac. I'll make those changes at submission time.

-Original Message-
From: Oram, Isaac W  
Sent: Tuesday, May 11, 2021 3:13 PM
To: Desimone, Nathaniel L ; devel@edk2.groups.io
Cc: Chiu, Chasel ; Kinney, Michael D 
; Abbas, Mohamed ; Michael 
Kubacki ; Bobroff, Zachary ; 
DOPPALAPUDI, HARIKRISHNA 
Subject: RE: [edk2-platforms] [PATCH V1 00/18] Reinstate Purley MinPlatform

Series Reviewed-by: Isaac Oram 

Some nit observations.  Not critical, but nice to update.
  Patch 05/18:  
Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf
 would be better if it included MdePkg/MdePkg.dec in [Packages] section.
  Patch 16/18:  
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPreMemLib.c
 has some commented out code between lines 143 and 160 that should be removed.

Regards,
Isaac

-Original Message-
From: Desimone, Nathaniel L  
Sent: Tuesday, May 11, 2021 2:48 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Kinney, Michael D 
; Oram, Isaac W ; Abbas, 
Mohamed ; Michael Kubacki 
; Bobroff, Zachary ; 
DOPPALAPUDI, HARIKRISHNA 
Subject: [edk2-platforms] [PATCH V1 00/18] Reinstate Purley MinPlatform

This patch series revives the PurleyOpenBoardPkg. The package has been
upgraded to support the newest MinPlatformPkg and the new advanced
feature architecture. Build issues with the newest EDK II have been
fixed. Finally, I believe most (if not all) MinPlatform Architecture
violations have been fixed. The build system has been converted from
the legacy .bat scripts to the new Python build infrastructure.

For silicon code, I have consolidated PurleyRcPkg, PurleySktPkg,
and LewisburgPkg into a single PurleyRefreshSiliconPkg for consistency
with the other MinPlatform board port's silicon packages. In addition,
the silicon code has been upgraded to a newer version with support
for the 2nd Generation Xeon Scalable "Cascade Lake" processors.

Cc: Chasel Chiu 
Cc: Mike Kinney 
Cc: Isaac Oram 
Cc: Mohamed Abbas 
Cc: Michael Kubacki 
Cc: Zachary Bobroff 
Cc: Harikrishna Doppalapudi 
Signed-off-by: Nate DeSimone 

Nate DeSimone (18):
  PurleyRefreshSiliconPkg: Add DEC and DSC files.
  PurleyRefreshSiliconPkg/Pch: Add Register Header Files
  PurleyRefreshSiliconPkg/Pch: Add Public Header Files
  PurleyRefreshSiliconPkg/Pch: Add Private Header Files
  PurleyRefreshSiliconPkg/Pch: Add libraries
  PurleyRefreshSiliconPkg/Pch: Add ACPI tables
  PurleyRefreshSiliconPkg: Add Uncore files
  PurleyOpenBoardPkg: Add includes and libraries
  PurleyOpenBoardPkg: Add modules
  PurleyOpenBoardPkg/Acpi/BoardAcpiDxe: Add PlatformPciTree_WFP.asi
  PurleyOpenBoardPkg/Acpi/BoardAcpiDxe: Add PCxx.asi files
  PurleyOpenBoardPkg/Acpi/BoardAcpiDxe: Add ASL files
  PurleyOpenBoardPkg/Acpi: Add BoardAcpiDxe
  PurleyOpenBoardPkg: Add MtOlympus build files
  PurleyOpenBoardPkg: Add StructureConfig.dsc
  PurleyOpenBoardPkg: Add BoardMtOlympus
  Readme.md: Add PurleyOpenBoardPkg
  Maintainers.txt: Add PurleyOpenBoardPkg and PurleyRefreshSiliconPkg

 Maintainers.txt   |   10 +
 .../Acpi/BoardAcpiDxe/AmlOffsetTable.c|  290 +
 .../Acpi/BoardAcpiDxe/BoardAcpiDxe.c  |  547 ++
 .../Acpi/BoardAcpiDxe/BoardAcpiDxe.h  |   82 +
 .../Acpi/BoardAcpiDxe/BoardAcpiDxe.inf|   71 +
 .../Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c  |  516 ++
 .../Acpi/BoardAcpiDxe/Dsdt.inf|   29 +
 .../Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl |   19 +
 .../Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi |  227 +
 .../Acpi/BoardAcpiDxe/Dsdt/DSDT.asl   |   77 +
 .../Acpi/BoardAcpiDxe/Dsdt/Gpe.asl|  134 +
 .../Acpi/BoardAcpiDxe/Dsdt/HostBus.asl|  256 +
 .../Dsdt/IioPcieHotPlugGpeHandler.asl |  842 ++
 .../Dsdt/IioPcieRootPortHotPlug.asl   |  686 ++
 .../Acpi/BoardAcpiDxe/Dsdt/Itss.asl   |   32 +
 .../Acpi/BoardAcpiDxe/Dsdt/Mother.asi |  202 +
 .../Acpi/BoardAcpiDxe/Dsdt/Os.asi |  145 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC00.asi   |  385 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC01.asi   |  255 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC02.asi   |  255 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC03.asi   |  260 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC04.asi   |  232 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC05.asi   |  233 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC06.asi   |  328 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC06Ejd.asi|9 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC07.asi   |  259 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC08.asi   |  262 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC09.asi   |  260 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC10.asi   |  232 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC11.asi   |  231 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC12.asi   |  324 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC12Ejd.asi|9 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC13.asi   |  256 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC14.asi   |  259 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC15.asi   

[edk2-devel] [PATCH 1/2] Platform/Raspberrypi: Update DMA constants based on SOC revision

[Jeremy Linton]

The newer BCM2711 SoC's don't have a DMA constraint on the emmc2
controller. So we don't need to do the 1G translation. Lets
allow the AML to detect the SoC revision and return a different
_DMA resource.

Signed-off-by: Jeremy Linton 
---
 Platform/RaspberryPi/AcpiTables/Emmc.asl   | 39 +-
 .../Bcm27xx/Include/IndustryStandard/Bcm2711.h |  2 ++
 2 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/Platform/RaspberryPi/AcpiTables/Emmc.asl 
b/Platform/RaspberryPi/AcpiTables/Emmc.asl
index 23febe37b4..c6691e81dc 100644
--- a/Platform/RaspberryPi/AcpiTables/Emmc.asl
+++ b/Platform/RaspberryPi/AcpiTables/Emmc.asl
@@ -8,6 +8,7 @@
 
 #include 
 #include 
+#include 
 
 #include "AcpiTables.h"
 
@@ -31,7 +32,8 @@ DefinitionBlock (__FILE__, "SSDT", 2, "RPIFDN", "RPI4EMMC", 2)
 Return (^RBUF)
   }
 
-  Name (_DMA, ResourceTemplate() {
+  // Translated DMA region for < C0
+  Name (DMTR, ResourceTemplate() {
 QWordMemory (ResourceProducer,
   ,
   MinFixed,
@@ -48,6 +50,41 @@ DefinitionBlock (__FILE__, "SSDT", 2, "RPIFDN", "RPI4EMMC", 
2)
 )
   })
 
+  // Non translated DMA region for >= C0
+  Name (DMNT, ResourceTemplate() {
+QWordMemory (ResourceProducer,
+  ,
+  MinFixed,
+  MaxFixed,
+  NonCacheable,
+  ReadWrite,
+  0x0,
+  0x, // MIN
+  0x00FF, // MAX
+  0x, // TRA
+  0x0100, // LEN
+  ,
+  ,
+)
+  })
+
+  Method (_DMA, 0x0, Serialized)
+  {
+OperationRegion (CHPR, SystemMemory, ID_CHIPREV, 0x4)
+  Field (CHPR, DWordAcc, NoLock, Preserve) {
+SOCI, 32
+}
+
+if ((SOCI & 0xFF) >= 0x20)
+{
+  return (^DMNT);
+}
+else
+{
+  return (^DMTR);
+}
+  }
+
   // emmc2 Host Controller. (brcm,bcm2711-emmc2)
   Device (SDC3)
   {
diff --git a/Silicon/Broadcom/Bcm27xx/Include/IndustryStandard/Bcm2711.h 
b/Silicon/Broadcom/Bcm27xx/Include/IndustryStandard/Bcm2711.h
index 86906b2438..8a69128d11 100644
--- a/Silicon/Broadcom/Bcm27xx/Include/IndustryStandard/Bcm2711.h
+++ b/Silicon/Broadcom/Bcm27xx/Include/IndustryStandard/Bcm2711.h
@@ -88,4 +88,6 @@
 
 #define THERM_SENSOR   0xfd5d2200
 
+#define ID_CHIPREV 0xfc404000
+
 #endif /* BCM2711_H__ */
-- 
2.13.7



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[edk2-devel] [PATCH 2/2] Platform/RaspberryPi: Invert emmc PIO/DMA selection

[Jeremy Linton]

Now that we are doing SoC detection and adjusting the DMA
window it should be safe to turn DMA on by default.

Signed-off-by: Jeremy Linton 
---
 Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr | 4 ++--
 Platform/RaspberryPi/RPi4/RPi4.dsc  | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr 
b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
index aa124e4e31..759db6212f 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
@@ -300,8 +300,8 @@ formset
 prompt  = STRING_TOKEN(STR_MMC_EMMC_PROMPT),
 help= STRING_TOKEN(STR_MMC_EMMC_HELP),
 flags   = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED,
-option text = STRING_TOKEN(STR_MMC_EMMC_PIO), value = 0, flags = 
DEFAULT;
-option text = STRING_TOKEN(STR_MMC_EMMC_DMA), value = 1, flags = 0;
+option text = STRING_TOKEN(STR_MMC_EMMC_PIO), value = 0, flags = 0;
+option text = STRING_TOKEN(STR_MMC_EMMC_DMA), value = 1, flags = 
DEFAULT;
 endoneof;
 endif;
 #endif
diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc 
b/Platform/RaspberryPi/RPi4/RPi4.dsc
index cf796acf6a..b3acc04e07 100644
--- a/Platform/RaspberryPi/RPi4/RPi4.dsc
+++ b/Platform/RaspberryPi/RPi4/RPi4.dsc
@@ -486,7 +486,7 @@
   
gRaspberryPiTokenSpaceGuid.PcdMmcSdDefaultSpeedMHz|L"MmcSdDefaultSpeedMHz"|gConfigDxeFormSetGuid|0x0|25
   
gRaspberryPiTokenSpaceGuid.PcdMmcSdHighSpeedMHz|L"MmcSdHighSpeedMHz"|gConfigDxeFormSetGuid|0x0|50
   
gRaspberryPiTokenSpaceGuid.PcdMmcDisableMulti|L"MmcDisableMulti"|gConfigDxeFormSetGuid|0x0|0
-  
gRaspberryPiTokenSpaceGuid.PcdMmcEnableDma|L"MmcEnableDma"|gConfigDxeFormSetGuid|0x0|0
+  
gRaspberryPiTokenSpaceGuid.PcdMmcEnableDma|L"MmcEnableDma"|gConfigDxeFormSetGuid|0x0|1
 
   #
   # Debug-related.
-- 
2.13.7



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[edk2-devel] [PATCH 0/2] EMMC2 fix _DMA for newer SOC

[Jeremy Linton]

The _DMA range needs to change depending on the SOC in use, this
was part of the problem with enabling DMA by default because there
wasn't a clear way to determine the SOC revision in use.

Now that we have an id register for that, we can pick the correct
_DMA at runtime. Lets also flip DMA on by default.

Jeremy Linton (2):
  Platform/Raspberrypi: Update DMA constants based on SOC revision
  Platform/RaspberryPi: Invert emmc PIO/DMA selection

 Platform/RaspberryPi/AcpiTables/Emmc.asl   | 39 +-
 .../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr |  4 +--
 Platform/RaspberryPi/RPi4/RPi4.dsc |  2 +-
 .../Bcm27xx/Include/IndustryStandard/Bcm2711.h |  2 ++
 4 files changed, 43 insertions(+), 4 deletions(-)

-- 
2.13.7



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[edk2-devel] [PATCH v2 1/2] Silicon/Broadcom/BcmGenetDxe: Delay for linkup in transmit

[Jeremy Linton]

Under normal circumstances GenetSimpleNetworkTransmit won't be
called unless the rest of the network stack detects the link is
up. So, during normal operation when the adapter is initialized
the link naturally transitions to link up, and then is ready for
activity later in the boot sequence. If that hasn't happened by
the time PXE runs then it will itself wait for the link.

OTOH, the normal distro PXE sequence involves PXE loading shim
which in turn loads grub, which tries to read machine specific
configs, modules, and grub.cfg in order to prepare the boot menu.
Then, once a grub selection is picked, it might try to load the
kernel+initrd.

In this sequence the network stack is shutdown and restarted
multiple times. Grub though, starts up, notices its been network
booted, reads saved network parameters and immediately tries to
transmit data assuming the link is still up.

When that happens grub will print "couldn't send network packet"
and if that lasts long enough it fails to load grub.cfg and the
user gets dropped to the grub prompt because no one in the path
bothers to assure the link state has transitioned back up.

For reference: https://github.com/pftf/RPi4/issues/113

This patch fixes that by polling the link state via
GenericPhyUpdateConfig() for ten seconds in the transmit path
when the link is down. If the link recovers within this timeout
the state machine is transitioned and we continue data
transmission. If the 10 seconds expires without the link
resuming we will fail as before. While full link negotiation
can be fast, it frequently can take a second or two, or longer
depending on the remote peer on the other end of the
Ethernet cable. It seems auto MDX can slow this down,
and certain vendors products seem to be slower than the
norm. Ten seconds may not cover some of these possibilities,
but the user should validate cabling and the switch/peer's
port configuration if resuming the link is taking > 10
seconds. Picking a longer timeout is a tradeoff between the
machine appearing to hang for extended periods of time
(due to grub retries) if the link is actually down vs
generally providing enough time for most endpoints to
complete the negotiation.

Signed-off-by: Jeremy Linton 
Reviewed-by: Jared McNeill 
Reviewed-by: Andrei Warkentin 
---
 .../Drivers/Net/BcmGenetDxe/SimpleNetwork.c| 24 --
 1 file changed, 22 insertions(+), 2 deletions(-)

diff --git a/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/SimpleNetwork.c 
b/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/SimpleNetwork.c
index 1bda18f157..29c76d8495 100644
--- a/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/SimpleNetwork.c
+++ b/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/SimpleNetwork.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "BcmGenetDxe.h"
@@ -590,9 +591,28 @@ GenetSimpleNetworkTransmit (
 
   if (!Genet->SnpMode.MediaPresent) {
 //
-// Don't bother transmitting if there's no link.
+// We should only really get here if the link was up
+// and is now down due to a stop/shutdown sequence, and
+// the app (grub) doesn't bother to check link state
+// because it was up a moment before.
+// Lets wait a bit for the link to resume, rather than
+// failing to send. In the case of grub it works either way
+// but we can't be sure that is universally true, and
+// hanging for a couple seconds is nicer than a screen of
+// grub send failure messages.
 //
-return EFI_NOT_READY;
+int retries = 1000;
+DEBUG ((DEBUG_INFO, "%a: Waiting 10s for link\n", __FUNCTION__));
+do {
+  gBS->Stall (1);
+  Status = GenericPhyUpdateConfig (>Phy);
+} while (EFI_ERROR (Status) && retries--);
+if (EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_ERROR, "%a: no link\n", __FUNCTION__));
+  return EFI_NOT_READY;
+} else {
+  Genet->SnpMode.MediaPresent = TRUE;
+}
   }
 
   if (HeaderSize != 0) {
-- 
2.13.7



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[edk2-devel] [PATCH v2 0/2] rpi: Fix PXE issues with grub

[Jeremy Linton]

When PXE booting with grub the network link
isn't given a chance to resume so grub's transmit
calls fail. This results in failed boots. Similarly
the DMA range for the adapter isn't right since it
doesn't have a 32-bit restriction. Again this keeps
grub from failing on 8G devices,

v1-v2:
Update commit message to note solution
Add Review-by's

Jeremy Linton (2):
  Silicon/Broadcom/BcmGenetDxe: Delay for linkup in transmit
  Platform/RaspberryPi: Increase genet dma window

 Platform/RaspberryPi/RPi4/RPi4.dsc |  2 +-
 .../Drivers/Net/BcmGenetDxe/SimpleNetwork.c| 24 --
 2 files changed, 23 insertions(+), 3 deletions(-)

-- 
2.13.7



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[edk2-devel] [PATCH v2 2/2] Platform/RaspberryPi: Increase genet dma window

[Jeremy Linton]

The genet is capable of addressing the entire memory space
on the RPI4. Lets allow it to dma into those regions.
This solves intermittent issues with grub/etc being able
to communicate when the 3G limit is lifted on 8G boards.

Signed-off-by: Jeremy Linton 
Reviewed-by: Jared McNeill 
---
 Platform/RaspberryPi/RPi4/RPi4.dsc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc 
b/Platform/RaspberryPi/RPi4/RPi4.dsc
index 5c6783eae7..cf796acf6a 100644
--- a/Platform/RaspberryPi/RPi4/RPi4.dsc
+++ b/Platform/RaspberryPi/RPi4/RPi4.dsc
@@ -717,7 +717,7 @@
   Silicon/Broadcom/Drivers/Net/BcmGenetDxe/BcmGenetDxe.inf {
 
   gEmbeddedTokenSpaceGuid.PcdDmaDeviceOffset|0x
-  gEmbeddedTokenSpaceGuid.PcdDmaDeviceLimit|0x
+  gEmbeddedTokenSpaceGuid.PcdDmaDeviceLimit|0xff
   }
 
   #
-- 
2.13.7



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[edk2-devel] [PATCH v2 0/2] rpi: Fix PXE issues with grub

[Jeremy Linton]

When PXE booting with grub the network link
isn't given a chance to resume so grub's transmit
calls fail. This results in failed boots. Similarly
the DMA range for the adapter isn't right since it
doesn't have a 32-bit restriction. Again this keeps
grub from failing on 8G devices,

v1-v2:
Update commit message to note solution
Add Review-by's

Jeremy Linton (2):
  Silicon/Broadcom/BcmGenetDxe: Delay for linkup in transmit
  Platform/RaspberryPi: Increase genet dma window

 Platform/RaspberryPi/RPi4/RPi4.dsc |  2 +-
 .../Drivers/Net/BcmGenetDxe/SimpleNetwork.c| 24 --
 2 files changed, 23 insertions(+), 3 deletions(-)

-- 
2.13.7



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Re: [edk2-devel] [edk2-non-osi] [PATCH V1 0/9] PurleySiliconBinPkg: Restore Silicon FVs

[Oram, Isaac W]

Series Reviewed-by: Isaac Oram 

-Original Message-
From: Desimone, Nathaniel L  
Sent: Tuesday, May 11, 2021 2:54 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Kinney, Michael D 
; Oram, Isaac W ; Abbas, 
Mohamed ; Michael Kubacki 
; Bobroff, Zachary ; 
DOPPALAPUDI, HARIKRISHNA 
Subject: [edk2-non-osi] [PATCH V1 0/9] PurleySiliconBinPkg: Restore Silicon FVs

This patch series adds silicon firmware volumes back into the 
PurleySiliconBinPkg. Note that actual binaries provided by this patch series 
are the original binaries from 2018, which are unlikely to boot with the new 
PurleyRefreshSiliconPkg. The purpose of this patch series is to reinstate the 
directory structure so that it is possible to compile Purley MinPlatform. New 
binaries will be provided as part of an upcoming patch series.

Cc: Chasel Chiu 
Cc: Mike Kinney 
Cc: Isaac Oram 
Cc: Mohamed Abbas 
Cc: Michael Kubacki 
Cc: Zachary Bobroff 
Cc: Harikrishna Doppalapudi 
Signed-off-by: Nate DeSimone 

Nate DeSimone (9):
  PurleySiliconBinPkg/FV: Add License.txt
  PurleySiliconBinPkg/FV: Add RELEASE FvLateSilicon
  PurleySiliconBinPkg/FV: Remove DEBUG FvLateSilicon
  PurleySiliconBinPkg/FV: Add RELEASE FvPostMemorySilicon
  PurleySiliconBinPkg/FV: Add DEBUG FvPostMemorySilicon
  PurleySiliconBinPkg/FV: Add RELEASE FvPreMemorySilicon
  PurleySiliconBinPkg/FV: Add DEBUG FvPreMemorySilicon
  PurleySiliconBinPkg/FV: Add RELEASE FvTempMemorySilicon
  PurleySiliconBinPkg/FV: Add DEBUG FvTempMemorySilicon

 .../FV/FvLateSilicon/DEBUG/FVLATESILICON.Fv   |  Bin 0 -> 663512 bytes
 .../FvLateSilicon/DEBUG/FVLATESILICON.Fv.txt  |   17 +
 .../FV/FvLateSilicon/DEBUG/FvLateSilicon.inf  | 4009 +  
.../FV/FvLateSilicon/RELEASE/FVLATESILICON.Fv |  Bin 0 -> 429688 bytes
 .../RELEASE/FVLATESILICON.Fv.txt  |   17 +
 .../FvLateSilicon/RELEASE/FvLateSilicon.inf   | 3811 
 .../DEBUG/FVPOSTMEMORYSILICON.Fv  |  Bin 0 -> 196608 bytes
 .../DEBUG/FVPOSTMEMORYSILICON.Fv.txt  |3 +
 .../DEBUG/FvPostMemorySilicon.inf |  279 ++
 .../RELEASE/FVPOSTMEMORYSILICON.Fv|  Bin 0 -> 196608 bytes
 .../RELEASE/FVPOSTMEMORYSILICON.Fv.txt|3 +
 .../RELEASE/FvPostMemorySilicon.inf   |  267 ++
 .../DEBUG/FVPREMEMORYSILICON.Fv   |  Bin 0 -> 1245184 bytes
 .../DEBUG/FVPREMEMORYSILICON.Fv.txt   |7 +
 .../DEBUG/FvPreMemorySilicon.inf  | 1096 +
 .../RELEASE/FVPREMEMORYSILICON.Fv |  Bin 0 -> 1245184 bytes
 .../RELEASE/FVPREMEMORYSILICON.Fv.txt |7 +
 .../RELEASE/FvPreMemorySilicon.inf| 1051 +
 .../DEBUG/FVTEMPMEMORYSILICON.Fv  |  Bin 0 -> 131072 bytes
 .../DEBUG/FVTEMPMEMORYSILICON.Fv.txt  |4 +
 .../DEBUG/FvTempMemorySilicon.inf |  267 ++
 .../RELEASE/FVTEMPMEMORYSILICON.Fv|  Bin 0 -> 131072 bytes
 .../RELEASE/FVTEMPMEMORYSILICON.Fv.txt|4 +
 .../RELEASE/FvTempMemorySilicon.inf   |  263 ++
 .../Intel/PurleySiliconBinPkg/FV/License.txt  |   37 +
 25 files changed, 11142 insertions(+)
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvLateSilicon/DEBUG/FVLATESILICON.Fv
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvLateSilicon/DEBUG/FVLATESILICON.Fv.txt
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvLateSilicon/DEBUG/FvLateSilicon.inf
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvLateSilicon/RELEASE/FVLATESILICON.Fv
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvLateSilicon/RELEASE/FVLATESILICON.Fv.txt
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvLateSilicon/RELEASE/FvLateSilicon.inf
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/DEBUG/FVPOSTMEMORYSILICON.Fv
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/DEBUG/FVPOSTMEMORYSILICON.Fv.txt
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/DEBUG/FvPostMemorySilicon.inf
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/RELEASE/FVPOSTMEMORYSILICON.Fv
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/RELEASE/FVPOSTMEMORYSILICON.Fv.txt
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/RELEASE/FvPostMemorySilicon.inf
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPreMemorySilicon/DEBUG/FVPREMEMORYSILICON.Fv
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPreMemorySilicon/DEBUG/FVPREMEMORYSILICON.Fv.txt
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPreMemorySilicon/DEBUG/FvPreMemorySilicon.inf
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPreMemorySilicon/RELEASE/FVPREMEMORYSILICON.Fv
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPreMemorySilicon/RELEASE/FVPREMEMORYSILICON.Fv.txt
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPreMemorySilicon/RELEASE/FvPreMemorySilicon.inf
 

Re: [edk2-devel] [edk2-platforms] [PATCH V1 00/18] Reinstate Purley MinPlatform

[Oram, Isaac W]

Series Reviewed-by: Isaac Oram 

Some nit observations.  Not critical, but nice to update.
  Patch 05/18:  
Silicon/Intel/PurleyRefreshSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf
 would be better if it included MdePkg/MdePkg.dec in [Packages] section.
  Patch 16/18:  
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPreMemLib.c
 has some commented out code between lines 143 and 160 that should be removed.

Regards,
Isaac

-Original Message-
From: Desimone, Nathaniel L  
Sent: Tuesday, May 11, 2021 2:48 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Kinney, Michael D 
; Oram, Isaac W ; Abbas, 
Mohamed ; Michael Kubacki 
; Bobroff, Zachary ; 
DOPPALAPUDI, HARIKRISHNA 
Subject: [edk2-platforms] [PATCH V1 00/18] Reinstate Purley MinPlatform

This patch series revives the PurleyOpenBoardPkg. The package has been
upgraded to support the newest MinPlatformPkg and the new advanced
feature architecture. Build issues with the newest EDK II have been
fixed. Finally, I believe most (if not all) MinPlatform Architecture
violations have been fixed. The build system has been converted from
the legacy .bat scripts to the new Python build infrastructure.

For silicon code, I have consolidated PurleyRcPkg, PurleySktPkg,
and LewisburgPkg into a single PurleyRefreshSiliconPkg for consistency
with the other MinPlatform board port's silicon packages. In addition,
the silicon code has been upgraded to a newer version with support
for the 2nd Generation Xeon Scalable "Cascade Lake" processors.

Cc: Chasel Chiu 
Cc: Mike Kinney 
Cc: Isaac Oram 
Cc: Mohamed Abbas 
Cc: Michael Kubacki 
Cc: Zachary Bobroff 
Cc: Harikrishna Doppalapudi 
Signed-off-by: Nate DeSimone 

Nate DeSimone (18):
  PurleyRefreshSiliconPkg: Add DEC and DSC files.
  PurleyRefreshSiliconPkg/Pch: Add Register Header Files
  PurleyRefreshSiliconPkg/Pch: Add Public Header Files
  PurleyRefreshSiliconPkg/Pch: Add Private Header Files
  PurleyRefreshSiliconPkg/Pch: Add libraries
  PurleyRefreshSiliconPkg/Pch: Add ACPI tables
  PurleyRefreshSiliconPkg: Add Uncore files
  PurleyOpenBoardPkg: Add includes and libraries
  PurleyOpenBoardPkg: Add modules
  PurleyOpenBoardPkg/Acpi/BoardAcpiDxe: Add PlatformPciTree_WFP.asi
  PurleyOpenBoardPkg/Acpi/BoardAcpiDxe: Add PCxx.asi files
  PurleyOpenBoardPkg/Acpi/BoardAcpiDxe: Add ASL files
  PurleyOpenBoardPkg/Acpi: Add BoardAcpiDxe
  PurleyOpenBoardPkg: Add MtOlympus build files
  PurleyOpenBoardPkg: Add StructureConfig.dsc
  PurleyOpenBoardPkg: Add BoardMtOlympus
  Readme.md: Add PurleyOpenBoardPkg
  Maintainers.txt: Add PurleyOpenBoardPkg and PurleyRefreshSiliconPkg

 Maintainers.txt   |   10 +
 .../Acpi/BoardAcpiDxe/AmlOffsetTable.c|  290 +
 .../Acpi/BoardAcpiDxe/BoardAcpiDxe.c  |  547 ++
 .../Acpi/BoardAcpiDxe/BoardAcpiDxe.h  |   82 +
 .../Acpi/BoardAcpiDxe/BoardAcpiDxe.inf|   71 +
 .../Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c  |  516 ++
 .../Acpi/BoardAcpiDxe/Dsdt.inf|   29 +
 .../Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl |   19 +
 .../Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi |  227 +
 .../Acpi/BoardAcpiDxe/Dsdt/DSDT.asl   |   77 +
 .../Acpi/BoardAcpiDxe/Dsdt/Gpe.asl|  134 +
 .../Acpi/BoardAcpiDxe/Dsdt/HostBus.asl|  256 +
 .../Dsdt/IioPcieHotPlugGpeHandler.asl |  842 ++
 .../Dsdt/IioPcieRootPortHotPlug.asl   |  686 ++
 .../Acpi/BoardAcpiDxe/Dsdt/Itss.asl   |   32 +
 .../Acpi/BoardAcpiDxe/Dsdt/Mother.asi |  202 +
 .../Acpi/BoardAcpiDxe/Dsdt/Os.asi |  145 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC00.asi   |  385 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC01.asi   |  255 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC02.asi   |  255 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC03.asi   |  260 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC04.asi   |  232 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC05.asi   |  233 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC06.asi   |  328 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC06Ejd.asi|9 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC07.asi   |  259 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC08.asi   |  262 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC09.asi   |  260 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC10.asi   |  232 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC11.asi   |  231 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC12.asi   |  324 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC12Ejd.asi|9 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC13.asi   |  256 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC14.asi   |  259 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC15.asi   |  259 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC16.asi   |  231 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC17.asi   |  231 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC18.asi   |  342 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC18Ejd.asi|9 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC19.asi   |  259 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC20.asi   |  260 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC21.asi   

Re: [edk2-devel] [PATCH edk2-test 1/1] uefi-sct/SctPkg: correct print code for EFI_MEMORY_TYPE

[Samer El-Haj-Mahmoud]

Thanks!!

Reviewed-by: Samer El-Haj-Mahmoud 


> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Heinrich
> Schuchardt via groups.io
> Sent: Friday, April 30, 2021 3:40 PM
> To: EDK II Development 
> Cc: Eric Jin ; G Edhaya Chandran
> ; Barton Gao ; Arvin
> Chen ; Samer El-Haj-Mahmoud  mahm...@arm.com>; Heinrich Schuchardt 
> Subject: [edk2-devel] [PATCH edk2-test 1/1] uefi-sct/SctPkg: correct print
> code for EFI_MEMORY_TYPE
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2284
>
> EFI_MEMORY_TYPE is an enum. SctPrint expects an UINTN when printing
> with %d. Add missing conversions in
> MemoryAllocationServicesBBTestFunction.
>
> Signed-off-by: Heinrich Schuchardt 
> ---
>  .../MemoryAllocationServicesBBTestFunction.c  | 98 +--
>  1 file changed, 49 insertions(+), 49 deletions(-)
>
> diff --git a/uefi-
> sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/Blac
> kBoxTest/MemoryAllocationServicesBBTestFunction.c b/uefi-
> sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/Blac
> kBoxTest/MemoryAllocationServicesBBTestFunction.c
> index bf8cd3b3afa4..e545b3cfc5b8 100644
> --- a/uefi-
> sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/Blac
> kBoxTest/MemoryAllocationServicesBBTestFunction.c
> +++ b/uefi-
> sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationSer
> +++ vices/BlackBoxTest/MemoryAllocationServicesBBTestFunction.c
> @@ -417,7 +417,7 @@ BBTestAllocatePagesInterfaceTest (
>   (UINTN)__LINE__,
>   Status,
>   TplArray[Index],
> - AllocatePagesMemoryType[TypeIndex]
> + (UINTN)AllocatePagesMemoryType[TypeIndex]
>   );
>if (!(Memory & EFI_PAGE_MASK)) {
>  AssertionType = EFI_TEST_ASSERTION_PASSED; @@ -437,7 +437,7 @@
> BBTestAllocatePagesInterfaceTest (
>   __FILE__,
>   (UINTN)__LINE__,
>   TplArray[Index],
> - AllocatePagesMemoryType[TypeIndex]
> + (UINTN)AllocatePagesMemoryType[TypeIndex]
>   );
>if (Memory != 0) {
>  Status = gtBS->FreePages (
> @@ -455,7 +455,7 @@ BBTestAllocatePagesInterfaceTest (
>   (UINTN)__LINE__,
>   Status,
>   TplArray[Index],
> - AllocatePagesMemoryType[TypeIndex]
> + (UINTN)AllocatePagesMemoryType[TypeIndex]
>   );
>  }
>}
> @@ -478,7 +478,7 @@ BBTestAllocatePagesInterfaceTest (
> (UINTN)__LINE__,
> Status,
> TplArray[Index],
> -   AllocatePagesMemoryType[TypeIndex]
> +   (UINTN)AllocatePagesMemoryType[TypeIndex]
> );
>} else {
>  PageNum = (UINTN)Descriptor.NumberOfPages; @@ -512,7 +512,7 @@
> BBTestAllocatePagesInterfaceTest (
> (UINTN)__LINE__,
> Status,
> TplArray[Index],
> -   AllocatePagesMemoryType[TypeIndex]
> +   (UINTN)AllocatePagesMemoryType[TypeIndex]
> );
>  if (!(Memory & EFI_PAGE_MASK)) {
>AssertionType = EFI_TEST_ASSERTION_PASSED; @@ -532,7 +532,7 @@
> BBTestAllocatePagesInterfaceTest (
> __FILE__,
> (UINTN)__LINE__,
> TplArray[Index],
> -   AllocatePagesMemoryType[TypeIndex]
> +   (UINTN)AllocatePagesMemoryType[TypeIndex]
> );
>  if (Memory <= Descriptor.PhysicalStart +
>   SctLShiftU64 (Descriptor.NumberOfPages, EFI_PAGE_SHIFT) - @@ -
> 554,7 +554,7 @@ BBTestAllocatePagesInterfaceTest (
> __FILE__,
> (UINTN)__LINE__,
> TplArray[Index],
> -   AllocatePagesMemoryType[TypeIndex],
> +   (UINTN)AllocatePagesMemoryType[TypeIndex],
> Descriptor.PhysicalStart,
> Descriptor.NumberOfPages,
> Memory
> @@ -589,7 +589,7 @@ BBTestAllocatePagesInterfaceTest (
> (UINTN)__LINE__,
> Status,
> TplArray[Index],
> -   AllocatePagesMemoryType[TypeIndex]
> +   (UINTN)AllocatePagesMemoryType[TypeIndex]
> );
>  if (!(Memory2 & EFI_PAGE_MASK)) {
>AssertionType = EFI_TEST_ASSERTION_PASSED; @@ -609,7 +609,7 @@
> BBTestAllocatePagesInterfaceTest (
> __FILE__,
> (UINTN)__LINE__,
> TplArray[Index],
> 

[edk2-devel] [PATCH] UefiCpuPkg/MpInitLib: Allocate a separate SEV-ES AP reset stack area

[Lendacky, Thomas]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3324

The SEV-ES stacks currently share a page with the reset code and data.
Separate the SEV-ES stacks from the reset vector code and data to avoid
possible stack overflows from overwriting the code and/or data.

When SEV-ES is enabled, invoke the GetWakeupBuffer() routine a second time
to allocate a new area, below the reset vector and data.

Both the PEI and DXE versions of GetWakeupBuffer() are changed to track
the previous reset buffer allocation in order to ensure that the new
buffer allocation is below the previous allocation.

Fixes: 7b7508ad784d16a5208c8d12dff43aef6df0835b
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Laszlo Ersek 
Cc: Rahul Kumar 
Signed-off-by: Tom Lendacky 
---
 UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 12 -
 UefiCpuPkg/Library/MpInitLib/MpLib.c| 48 +---
 UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 14 --
 3 files changed, 54 insertions(+), 20 deletions(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c 
b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
index 7839c249760e..fdfa0755d37a 100644
--- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
@@ -29,6 +29,11 @@ VOID *mReservedApLoopFunc = NULL;
 UINTNmReservedTopOfApStack;
 volatile UINT32  mNumberToFinish = 0;
 
+//
+// Begin wakeup buffer allocation below 0x88000
+//
+STATIC EFI_PHYSICAL_ADDRESS mWakeupBuffer = 0x88000;
+
 /**
   Enable Debug Agent to support source debugging on AP function.
 
@@ -102,7 +107,7 @@ GetWakeupBuffer (
   // LagacyBios driver depends on CPU Arch protocol which guarantees below
   // allocation runs earlier than LegacyBios driver.
   //
-  StartAddress = 0x88000;
+  StartAddress = mWakeupBuffer;
   Status = gBS->AllocatePages (
   AllocateMaxAddress,
   MemoryType,
@@ -112,6 +117,11 @@ GetWakeupBuffer (
   ASSERT_EFI_ERROR (Status);
   if (EFI_ERROR (Status)) {
 StartAddress = (EFI_PHYSICAL_ADDRESS) -1;
+  } else {
+//
+// Next wakeup buffer allocation must be below this allocation
+//
+mWakeupBuffer = StartAddress;
   }
 
   DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n",
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c 
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index dc2a54aa31e8..a76dae437606 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -1164,20 +1164,6 @@ GetApResetVectorSize (
AddressMap->SwitchToRealSize +
sizeof (MP_CPU_EXCHANGE_INFO);
 
-  //
-  // The AP reset stack is only used by SEV-ES guests. Do not add to the
-  // allocation if SEV-ES is not enabled.
-  //
-  if (PcdGetBool (PcdSevEsIsEnabled)) {
-//
-// Stack location is based on APIC ID, so use the total number of
-// processors for calculating the total stack area.
-//
-Size += AP_RESET_STACK_SIZE * PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
-
-Size = ALIGN_VALUE (Size, CPU_STACK_ALIGNMENT);
-  }
-
   return Size;
 }
 
@@ -1207,9 +1193,39 @@ AllocateResetVector (
 CpuMpData->AddressMap.ModeTransitionOffset
 );
 //
-// The reset stack starts at the end of the buffer.
+// The AP reset stack is only used by SEV-ES guests. Do not allocate it
+// if SEV-ES is not enabled.
 //
-CpuMpData->SevEsAPResetStackStart = CpuMpData->WakeupBuffer + 
ApResetVectorSize;
+if (PcdGetBool (PcdSevEsIsEnabled)) {
+  UINTN  ApResetStackSize;
+
+  //
+  // Stack location is based on ProcessorNumber, so use the total number
+  // of processors for calculating the total stack area.
+  //
+  ApResetStackSize = AP_RESET_STACK_SIZE *
+   PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
+
+  //
+  // Invoke GetWakeupBuffer a second time to allocate the stack area
+  // below 1MB. The returned buffer will be page aligned and sized and
+  // below the previously allocated buffer.
+  //
+  CpuMpData->SevEsAPResetStackStart = GetWakeupBuffer (ApResetStackSize);
+
+  //
+  // Check to be sure that the "allocate below" behavior hasn't changed.
+  // This will also catch a failed allocation, as "-1" is returned on
+  // failure.
+  //
+  if (CpuMpData->SevEsAPResetStackStart >= CpuMpData->WakeupBuffer) {
+DEBUG ((DEBUG_ERROR,
+  "SEV-ES AP reset stack is not below wakeup buffer\n"));
+
+ASSERT (FALSE);
+CpuDeadLoop ();
+  }
+}
   }
   BackupAndPrepareWakeupBuffer (CpuMpData);
 }
diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c 
b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
index 3989bd6a7a9f..4d09e89b4128 100644
--- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
@@ -11,6 +11,8 @@
 #include 
 #include 
 
+STATIC UINT64 mWakeupBuffer = BASE_1MB;
+
 /**
   S3 SMM Init Done notification function.
 
@@ -220,11 

Re: [edk2-devel] [PATCH 5/5] StandaloneMmPkg: build for 32bit arm machines

[Sami Mujawar]

Hi Etienne,

Thank you for this patch.

I am getting build errors in VariableMmDependency.inf when building for 
ARM. Not sure if you are getting these or it is my development 
environment (I am building on a Windows Host PC). Can you let me know 
which AArch32 GCC compiler you are using, please?


Apart from this, there are some minor comments that I have marked inline 
as [SAMI].


With those addressed.

Reviewed-by: Sami Mujawar 

Regards,

Sami Mujawar

On 04/05/2021 04:20 PM, Etienne Carriere wrote:

This change allows to build StandaloneMmPkg components for 32bit Arm
StandaloneMm firmware.

This change mainly moves AArch64/ source files to Arm/ side directory
for several components:  StandaloneMmCpu, StandaloneMmCoreEntryPoint
and StandaloneMmMemLib. The source file is built for both 32b and 64b
Arm targets.

Cc: Achin Gupta 
Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Leif Lindholm 
Cc: Sami Mujawar 
Cc: Sughosh Ganu 
Signed-off-by: Etienne Carriere 
---
  StandaloneMmPkg/Core/StandaloneMmCore.inf 
   |  2 +-
  StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/EventHandle.c   
   | 12 ++--
  StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/StandaloneMmCpu.c   
   |  2 +-
  StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/StandaloneMmCpu.h   
   |  0
  StandaloneMmPkg/Drivers/StandaloneMmCpu/{AArch64 => }/StandaloneMmCpu.inf 
   |  0
  StandaloneMmPkg/Include/Library/{AArch64 => Arm}/StandaloneMmCoreEntryPoint.h 
   |  0
  StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64 => 
Arm}/CreateHobList.c  |  2 +-
  StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64 => 
Arm}/SetPermissions.c |  2 +-
  StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/{AArch64 => 
Arm}/StandaloneMmCoreEntryPoint.c | 16 
  
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/StandaloneMmCoreEntryPoint.inf
| 14 +++---
  StandaloneMmPkg/Library/StandaloneMmCoreHobLib/{AArch64 => 
Arm}/StandaloneMmCoreHobLib.c |  0
  StandaloneMmPkg/Library/StandaloneMmCoreHobLib/{AArch64 => 
Arm}/StandaloneMmCoreHobLibInternal.c |  0
  StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreHobLib.inf 
   |  8 
  StandaloneMmPkg/Library/StandaloneMmMemLib/{AArch64/StandaloneMmMemLibInternal.c 
=> ArmStandaloneMmMemLibInternal.c} |  9 -
  StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf 
   |  6 +++---
  StandaloneMmPkg/Library/VariableMmDependency/VariableMmDependency.inf 
   |  2 +-
  StandaloneMmPkg/StandaloneMmPkg.dsc   
   |  8 
  17 files changed, 49 insertions(+), 34 deletions(-)

diff --git a/StandaloneMmPkg/Core/StandaloneMmCore.inf 
b/StandaloneMmPkg/Core/StandaloneMmCore.inf
index 87bf6e9440..56042b7b39 100644
--- a/StandaloneMmPkg/Core/StandaloneMmCore.inf
+++ b/StandaloneMmPkg/Core/StandaloneMmCore.inf
@@ -17,7 +17,7 @@
PI_SPECIFICATION_VERSION   = 0x00010032
ENTRY_POINT= StandaloneMmMain
  
-#  VALID_ARCHITECTURES   = IA32 X64 AARCH64

+#  VALID_ARCHITECTURES   = IA32 X64 AARCH64 ARM
  
  [Sources]

StandaloneMmCore.c
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c 
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
similarity index 92%
rename from StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c
rename to StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
index 63fbe26642..2d7fd81133 100644
--- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/EventHandle.c
+++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
@@ -2,6 +2,7 @@
  
Copyright (c) 2016 HP Development Company, L.P.

Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.
+  Copyright (c) 2021, Linaro Limited
  
SPDX-License-Identifier: BSD-2-Clause-Patent
  
@@ -27,6 +28,13 @@
  
  #include "StandaloneMmCpu.h"
  
+#ifdef MDE_CPU_AARCH64

+#define ARM_SMC_ID_MM_COMMUNICATE  ARM_SMC_ID_MM_COMMUNICATE_AARCH64
+#endif
+#ifdef MDE_CPU_ARM
+#define ARM_SMC_ID_MM_COMMUNICATE  ARM_SMC_ID_MM_COMMUNICATE_AARCH32
+#endif
[SAMI] Should this definition be in 
ArmPkg\Include\IndustryStandard\ArmStdSmc.h?
I can see Patch 2/5 uses the above define in 
ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c.

[/SAMI]

+
  EFI_STATUS
  EFIAPI
  MmFoundationEntryRegister (
@@ -92,8 +100,8 @@ 

Re: [edk2-devel] [PATCH 4/5] StandaloneMmPkg: fix pointer/int casts against 32bit architectures

[Sami Mujawar]

Hi Etienne,

Thank you for this patch.

A space should not be there between a unary operator add its operand.
See
https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/5_source_files/52_spacing#5-2-2-3-do-not-put-space-between-unary-operators-and-their-object

However, the existing code does not follow this anyways.

Reviewed-by: Sami Mujawar 

Regards,

Sami Mujawar


On 04/05/2021 04:20 PM, Etienne Carriere wrote:

Use intermediate (UINTN) cast when casting int from/to pointer. This
is needed as UINT64 values cast from/to 32bit pointer for 32bit
architectures.

Cc: Achin Gupta 
Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Leif Lindholm 
Cc: Sami Mujawar 
Cc: Sughosh Ganu 
Signed-off-by: Etienne Carriere 
---
  StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c 
  |  8 
  StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c
  | 14 +++---
  
StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c
 |  2 +-
  3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c 
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c
index 6884095c49..d4590bcd19 100644
--- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c
+++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.c
@@ -164,8 +164,8 @@ StandaloneMmCpuInitialize (

// Share the entry point of the CPU driver
DEBUG ((DEBUG_INFO, "Sharing Cpu Driver EP *0x%lx = 0x%lx\n",
-  (UINT64) CpuDriverEntryPointDesc->ArmTfCpuDriverEpPtr,
-  (UINT64) PiMmStandaloneArmTfCpuDriverEntry));
+  (UINTN) CpuDriverEntryPointDesc->ArmTfCpuDriverEpPtr,
+  (UINTN) PiMmStandaloneArmTfCpuDriverEntry));
*(CpuDriverEntryPointDesc->ArmTfCpuDriverEpPtr) = 
PiMmStandaloneArmTfCpuDriverEntry;

// Find the descriptor that contains the whereabouts of the buffer for
@@ -180,8 +180,8 @@ StandaloneMmCpuInitialize (
  return Status;
}

-  DEBUG ((DEBUG_INFO, "mNsCommBuffer.PhysicalStart - 0x%lx\n", (UINT64) 
NsCommBufMmramRange->PhysicalStart));
-  DEBUG ((DEBUG_INFO, "mNsCommBuffer.PhysicalSize - 0x%lx\n", (UINT64) 
NsCommBufMmramRange->PhysicalSize));
+  DEBUG ((DEBUG_INFO, "mNsCommBuffer.PhysicalStart - 0x%lx\n", (UINTN) 
NsCommBufMmramRange->PhysicalStart));
+  DEBUG ((DEBUG_INFO, "mNsCommBuffer.PhysicalSize - 0x%lx\n", (UINTN) 
NsCommBufMmramRange->PhysicalSize));

CopyMem (, NsCommBufMmramRange, sizeof(EFI_MMRAM_DESCRIPTOR));
DEBUG ((DEBUG_INFO, "mNsCommBuffer: 0x%016lx - 0x%lx\n", 
mNsCommBuffer.CpuStart, mNsCommBuffer.PhysicalSize));
diff --git 
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c 
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c
index e8fb96bd6e..4d4cf3d5ff 100644
--- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c
+++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/CreateHobList.c
@@ -72,14 +72,14 @@ CreateHobListFromBootInfo (

// Create a hoblist with a PHIT and EOH
HobStart = HobConstructor (
-   (VOID *) PayloadBootInfo->SpMemBase,
+   (VOID *) (UINTN) PayloadBootInfo->SpMemBase,
 (UINTN)  PayloadBootInfo->SpMemLimit - 
PayloadBootInfo->SpMemBase,
-   (VOID *) PayloadBootInfo->SpHeapBase,
-   (VOID *) (PayloadBootInfo->SpHeapBase + 
PayloadBootInfo->SpHeapSize)
+   (VOID *) (UINTN) PayloadBootInfo->SpHeapBase,
+   (VOID *) (UINTN) (PayloadBootInfo->SpHeapBase + 
PayloadBootInfo->SpHeapSize)
 );

// Check that the Hoblist starts at the bottom of the Heap
-  ASSERT (HobStart == (VOID *) PayloadBootInfo->SpHeapBase);
+  ASSERT (HobStart == (VOID *) (UINTN) PayloadBootInfo->SpHeapBase);

// Build a Boot Firmware Volume HOB
BuildFvHob (PayloadBootInfo->SpImageBase, PayloadBootInfo->SpImageSize);
@@ -190,9 +190,9 @@ CreateHobListFromBootInfo (
MmramRanges[3].RegionState   = EFI_CACHEABLE | EFI_ALLOCATED;

// Base and size of heap memory shared by all cpus
-  MmramRanges[4].PhysicalStart = (EFI_PHYSICAL_ADDRESS) HobStart;
-  MmramRanges[4].CpuStart  = (EFI_PHYSICAL_ADDRESS) HobStart;
-  MmramRanges[4].PhysicalSize  = HobStart->EfiFreeMemoryBottom - 
(EFI_PHYSICAL_ADDRESS) HobStart;
+  MmramRanges[4].PhysicalStart = (EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;
+  MmramRanges[4].CpuStart  = (EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;
+  MmramRanges[4].PhysicalSize  = HobStart->EfiFreeMemoryBottom - 
(EFI_PHYSICAL_ADDRESS) (UINTN) HobStart;
MmramRanges[4].RegionState   = EFI_CACHEABLE | EFI_ALLOCATED;

// Base and size of heap memory shared by all cpus
diff --git 
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/AArch64/StandaloneMmCoreEntryPoint.c
 

Re: [edk2-devel] [PATCH 3/5] GenGv: Arm: support images entered in Thumb mode

[Sami Mujawar]

Hi Etienne,

Thank you for this patch.

Please find my comments below marked [SAMI].

Regards,

Sami Mujawar
On 04/05/2021 04:20 PM, Etienne Carriere wrote:

Change GenFv for Arm architecture to generate a specific jump
instruction as image entry instruction, when the target entry label
is assembled with Thumb instruction set. This is possible since
SecCoreEntryAddress value fetched from the PE32 as its LSBit set when
the entry instruction executes in Thumb mode.

Cc: Bob Feng 
Cc: Liming Gao 
Cc: Achin Gupta 
Cc: Ard Biesheuvel 
Cc: Leif Lindholm 
Cc: Sughosh Ganu 
Signed-off-by: Etienne Carriere 
---
  BaseTools/Source/C/GenFv/GenFvInternalLib.c | 38 +++-
  1 file changed, 29 insertions(+), 9 deletions(-)

diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c 
b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
index 6e296b8ad6..3af65146f6 100644
--- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
+++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
@@ -34,9 +34,27 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
  #include "FvLib.h"
  #include "PeCoffLib.h"
  
-#define ARMT_UNCONDITIONAL_JUMP_INSTRUCTION   0xEB00

  #define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION  0x1400
  
+/*

+ * Arm instruction to jump to Fv enry instruction in Arm or Thumb mode.
+ * From ARM Arch Ref Manual versions b/c/d, section A8.8.25 BL, BLX (immediate)
+ * BLX (encoding A2) branches to offset in Thumb instruction set mode.
+ * BL (encoding A1) branches to offset in Arm instruction set mode.
+ */
+#define ARM_JUMP_OFFSET_MAX0xff
+#define ARM_JUMP_TO_ARM(Offset)(0xeb00 | ((Offset - 8) >> 2))
+
+#define _ARM_JUMP_TO_THUMB(Imm32)  (0xfa00 | \
+(((Imm32) & (1 << 1)) << (24 - 1)) | \
+(((Imm32) >> 2) & 0x7f))
+#define ARM_JUMP_TO_THUMB(Offset)  _ARM_JUMP_TO_THUMB((Offset) - 8)
+
+/*
+ * Arm instruction to retrun from exception (MOVS PC, LR)
+ */
+#define ARM_RETURN_FROM_EXCEPTION  0xE1B0F07E
+
  BOOLEAN mArm = FALSE;
  BOOLEAN mRiscV = FALSE;
  STATIC UINT32   MaxFfsAlignment = 0;
@@ -2203,23 +2221,25 @@ Returns:
  // if we found an SEC core entry point then generate a branch instruction
  // to it and populate a debugger SWI entry as well
  if (UpdateVectorSec) {
+  UINT32EntryOffset;
  
VerboseMsg("UpdateArmResetVectorIfNeeded updating ARM SEC vector");
  
-  // B SecEntryPoint - signed_immed_24 part +/-32MB offset

-  // on ARM, the PC is always 8 ahead, so we're not really jumping from 
the base address, but from base address + 8
-  ResetVector[0] = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress - 8) 
>> 2;
+  EntryOffset = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress);
  
-  if (ResetVector[0] > 0x00FF) {

-Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 32MB of the 
start of the FV");
+  if (EntryOffset > ARM_JUMP_OFFSET_MAX) {
+  Error(NULL, 0, 3000, "Invalid", "SEC Entry point offset above 1MB of the 
start of the FV");
  return EFI_ABORTED;
}
  
-  // Add opcode for an unconditional branch with no link. i.e.: " B SecEntryPoint"

-  ResetVector[0] |= ARMT_UNCONDITIONAL_JUMP_INSTRUCTION;
+  if (SecCoreEntryAddress & 1) {
[SAMI] if condition should evaluate a Boolean value. See 
https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/5_source_files/57_c_programming#5-7-2-1-boolean-values-variable-type-boolean-do-not-require-explicit-comparisons-to-true-or-false

With that changed.
[/SAMI]

+ResetVector[0] = ARM_JUMP_TO_THUMB(EntryOffset);
+  } else {
+ResetVector[0] = ARM_JUMP_TO_ARM(EntryOffset);
+  }
  
// SWI handler movs   pc,lr. Just in case a debugger uses SWI

-  ResetVector[2] = 0xE1B0F07E;
+  ResetVector[2] = ARM_RETURN_FROM_EXCEPTION;
  
// Place holder to support a common interrupt handler from ROM.

// Currently not supported. For this to be used the reset vector would 
not be in this FV




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Re: [edk2-devel] [PATCH 2/5] ArmPkg: prepare 32bit ARM build of StandaloneMmPkg

[Sami Mujawar]

Hi Etienne,

Thank you for this patch.

Reviewed-by: Sami Mujawar 

Regards,

Sami Mujawar


On 04/05/2021 04:20 PM, Etienne Carriere wrote:

Changes in ArmPkg to prepare building StandaloneMm firmware for
32bit Arm architectures.

Adds MmCommunicationDxe driver and ArmMmuPeiLib and
ArmmmuStandaloneMmLib libraries to the list of the standard
components build for ArmPkg on when ARM architectures.

Changes path of source file AArch64/ArmMmuStandaloneMmLib.c
and compile it for both 32bit and 64bit architectures.

Cc: Achin Gupta 
Cc: Ard Biesheuvel 
Cc: Leif Lindholm 
Cc: Sughosh Ganu 
Signed-off-by: Etienne Carriere 
---
  ArmPkg/ArmPkg.dec   |  2 
+-
  ArmPkg/ArmPkg.dsc   |  2 
+-
  ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c |  2 
+-
  ArmPkg/Library/StandaloneMmMmuLib/{AArch64 => }/ArmMmuStandaloneMmLib.c | 15 
---
  ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf |  6 
+++---
  5 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index 214b2f5892..6ed51edd03 100644
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -137,7 +137,7 @@
# hardware coherency (i.e., no virtualization or cache coherent DMA)

gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x0043
  
-[PcdsFeatureFlag.AARCH64]

+[PcdsFeatureFlag.AARCH64, PcdsFeatureFlag.ARM]
## Used to select method for requesting services from S-EL1.
#   TRUE  - Selects FF-A calls for communication between S-EL0 and SPMC.
#   FALSE - Selects SVC calls for communication between S-EL0 and SPMC.
diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc
index 926986cf7f..4c79dadf9e 100644
--- a/ArmPkg/ArmPkg.dsc
+++ b/ArmPkg/ArmPkg.dsc
@@ -158,7 +158,7 @@
ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLibNull.inf
  
-[Components.AARCH64]

+[Components.AARCH64, Components.ARM]
ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf
ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf
ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf
diff --git a/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c 
b/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c
index b1e3095809..4ae38a9f22 100644
--- a/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c
+++ b/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c
@@ -125,7 +125,7 @@ MmCommunication2Communicate (
}
  
// SMC Function ID

-  CommunicateSmcArgs.Arg0 = ARM_SMC_ID_MM_COMMUNICATE_AARCH64;
+  CommunicateSmcArgs.Arg0 = ARM_SMC_ID_MM_COMMUNICATE;
  
// Cookie

CommunicateSmcArgs.Arg1 = 0;
diff --git a/ArmPkg/Library/StandaloneMmMmuLib/AArch64/ArmMmuStandaloneMmLib.c 
b/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c
similarity index 92%
rename from ArmPkg/Library/StandaloneMmMmuLib/AArch64/ArmMmuStandaloneMmLib.c
rename to ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c
index dd014beec8..20f873e680 100644
--- a/ArmPkg/Library/StandaloneMmMmuLib/AArch64/ArmMmuStandaloneMmLib.c
+++ b/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c
@@ -2,6 +2,7 @@
File managing the MMU for ARMv8 architecture in S-EL0
  
Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.

+  Copyright (c) 2021, Linaro Limited
SPDX-License-Identifier: BSD-2-Clause-Patent
  
@par Reference(s):

@@ -62,7 +63,7 @@ SendMemoryPermissionRequest (
  // for other Direct Request calls which are not atomic
  // We therefore check only for Direct Response by the
  // callee.
-if (SvcArgs->Arg0 == ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64) {
+if (SvcArgs->Arg0 == ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP) {
// A Direct Response means FF-A success
// Now check the payload for errors
// The callee sends back the return value
@@ -164,13 +165,13 @@ GetMemoryPermissions (
ZeroMem (, sizeof (ARM_SVC_ARGS));
if (FeaturePcdGet (PcdFfaEnable)) {
  // See [2], Section 10.2 FFA_MSG_SEND_DIRECT_REQ.
-SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64;
+SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ;
  SvcArgs.Arg1 = ARM_FFA_DESTINATION_ENDPOINT_ID;
  SvcArgs.Arg2 = 0;
-SvcArgs.Arg3 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64;
+SvcArgs.Arg3 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES;
  SvcArgs.Arg4 = BaseAddress;
} else {
-SvcArgs.Arg0 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64;
+SvcArgs.Arg0 = ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES;
  SvcArgs.Arg1 = BaseAddress;
  SvcArgs.Arg2 = 0;
  SvcArgs.Arg3 = 0;
@@ -219,15 +220,15 @@ RequestMemoryPermissionChange (
ZeroMem (, sizeof (ARM_SVC_ARGS));
if (FeaturePcdGet (PcdFfaEnable)) {
  // See [2], Section 10.2 FFA_MSG_SEND_DIRECT_REQ.
-SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64;
+SvcArgs.Arg0 = 

Re: [edk2-devel] [PATCH 1/5] ArmPkg/IndustryStandard: 32b/64b agnostic FF-A and Mm SVC IDs

[Sami Mujawar]

Hi Etienn,

This patch looks good to me.

Reviewed-by: Sami Mujawar 

Regards,

Sami Mujawar


On 04/05/2021 04:20 PM, Etienne Carriere wrote:

Defines ARM_SVC_ID_FFA_* and ARM_SVC_ID_SP_* identifiers for 32bit
function IDs as per SMCCC specification. Defines also generic ARM
SVC identifier macros to wrap 32bit or 64bit identifiers upon target
built architecture.

Cc: Achin Gupta 
Cc: Ard Biesheuvel 
Cc: Leif Lindholm 
Cc: Sughosh Ganu 
Signed-off-by: Etienne Carriere 
---
  ArmPkg/Include/IndustryStandard/ArmFfaSvc.h | 12 
  ArmPkg/Include/IndustryStandard/ArmMmSvc.h  | 15 +++
  2 files changed, 27 insertions(+)

diff --git a/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h 
b/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h
index 65b8343ade..ebcb54b28b 100644
--- a/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h
+++ b/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h
@@ -17,9 +17,21 @@
  #define ARM_FFA_SVC_H_
  
  #define ARM_SVC_ID_FFA_VERSION_AARCH32  0x8463

+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32  0x846F
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x8470
  #define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64  0xC46F
  #define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC470
  
+/* Generic IDs when using AArch32 or AArch64 execution state */

+#ifdef MDE_CPU_AARCH64
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ 
ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP
ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64
+#endif
+#ifdef MDE_CPU_ARM
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ 
ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP
ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32
+#endif
+
  #define SPM_MAJOR_VERSION_FFA   1
  #define SPM_MINOR_VERSION_FFA   0
  
diff --git a/ArmPkg/Include/IndustryStandard/ArmMmSvc.h b/ArmPkg/Include/IndustryStandard/ArmMmSvc.h

index 33d60ccf17..deb3bc99d2 100644
--- a/ArmPkg/Include/IndustryStandard/ArmMmSvc.h
+++ b/ArmPkg/Include/IndustryStandard/ArmMmSvc.h
@@ -15,10 +15,25 @@
   * privileged operations on its behalf.
   */
  #define ARM_SVC_ID_SPM_VERSION_AARCH32 0x8460
+#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32   0x8461
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32   0x8464
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32   0x8465
  #define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64   0xC461
  #define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64   0xC464
  #define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64   0xC465
  
+/* Generic IDs when using AArch32 or AArch64 execution state */

+#ifdef MDE_CPU_AARCH64
+#define ARM_SVC_ID_SP_EVENT_COMPLETE   
ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES   
ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES   
ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64
+#endif
+#ifdef MDE_CPU_ARM
+#define ARM_SVC_ID_SP_EVENT_COMPLETE   
ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES   
ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES   
ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32
+#endif
+
  #define SET_MEM_ATTR_DATA_PERM_MASK   0x3
  #define SET_MEM_ATTR_DATA_PERM_SHIFT0
  #define SET_MEM_ATTR_DATA_PERM_NO_ACCESS0




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Re: [edk2-devel] [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform

[Sami Mujawar]

Pushed as 8549b1739183..e1efa61c33f7

Thanks,

Regards,

Sami Mujawar

On 11/05/2021, 08:47, "Pranav Madhu"  wrote:

Changes since V1:
- Remove patches that add CPU container object into DSDT
- Addressed comments from Sami

Low Power Idle (LPI) and Collaborative Processor Performance Control
(CPPC) are two power management mechanisms described in ACPI 6.4
specification. OSPM uses the _LPI object to select a local power state
for each level of processor hierarchy in the system. Collaborative
processor performance control (CPPC) defines an abstracted and flexible
mechanism for OSPM to collaborate with an entity in the platform to
manage the performance of a processor. In this patch series, CPPC
support depends on the availability of Activity Monitor Unit (AMU)
extension for CPU performance monitoring as defined in the Arm v8.4
architecture reference manuals. So CPPC is supported for RD-V1 and
RD-N2 platforms.

This patch series adds LPI support for all the Neoverse reference
design platforms. CPPC support is added for RD-V1, RD-V1-MC and
RD-N2 platforms.

This patch series should be applied on top of the patch series
https://edk2.groups.io/g/devel/message/74924

Link to github branch with the patches in this series -

https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rd_power_management


Pranav Madhu (11):
  Platform/Sgi: Macro definitions for ACPI _OSC
  Platform/Sgi: Low Power Idle states for SGI-575
  Platform/Sgi: Low Power Idle states for RD-N1-Edge
  Platform/Sgi: Low Power Idle States for RD-N1-Edge dual-chip
  Platform/Sgi: Low Power Idle states for RD-V1 platform
  Platform/Sgi: Macro definitions for ACPI CPPC
  Platform/Sgi: ACPI CPPC support for RD-V1
  Platform/Sgi: Low Power Idle States for RD-V1 quad-chip platform
  Platform/Sgi: ACPI CPPC support for RD-V1 quad-chip platform
  Platform/Sgi: Low Power Idle States for RD-N2
  Platform/Sgi: ACPI CPPC support for RD-N2

 Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h   |  90 +
 .../ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl   | 132 +++
 .../ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 162 
 Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl  | 364 ++
 Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl  | 294 ++
 .../ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 306 +++
 .../ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 132 +++
 7 files changed, 1480 insertions(+)

-- 
2.17.1




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Re: [edk2-devel] [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform

[Sami Mujawar]

For this series.

Reviewed-by: Sami Mujawar 

Regards,

Sami Mujawar

On 11/05/2021, 08:47, "Pranav Madhu"  wrote:

Changes since V1:
- Remove patches that add CPU container object into DSDT
- Addressed comments from Sami

Low Power Idle (LPI) and Collaborative Processor Performance Control
(CPPC) are two power management mechanisms described in ACPI 6.4
specification. OSPM uses the _LPI object to select a local power state
for each level of processor hierarchy in the system. Collaborative
processor performance control (CPPC) defines an abstracted and flexible
mechanism for OSPM to collaborate with an entity in the platform to
manage the performance of a processor. In this patch series, CPPC
support depends on the availability of Activity Monitor Unit (AMU)
extension for CPU performance monitoring as defined in the Arm v8.4
architecture reference manuals. So CPPC is supported for RD-V1 and
RD-N2 platforms.

This patch series adds LPI support for all the Neoverse reference
design platforms. CPPC support is added for RD-V1, RD-V1-MC and
RD-N2 platforms.

This patch series should be applied on top of the patch series
https://edk2.groups.io/g/devel/message/74924

Link to github branch with the patches in this series -

https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rd_power_management


Pranav Madhu (11):
  Platform/Sgi: Macro definitions for ACPI _OSC
  Platform/Sgi: Low Power Idle states for SGI-575
  Platform/Sgi: Low Power Idle states for RD-N1-Edge
  Platform/Sgi: Low Power Idle States for RD-N1-Edge dual-chip
  Platform/Sgi: Low Power Idle states for RD-V1 platform
  Platform/Sgi: Macro definitions for ACPI CPPC
  Platform/Sgi: ACPI CPPC support for RD-V1
  Platform/Sgi: Low Power Idle States for RD-V1 quad-chip platform
  Platform/Sgi: ACPI CPPC support for RD-V1 quad-chip platform
  Platform/Sgi: Low Power Idle States for RD-N2
  Platform/Sgi: ACPI CPPC support for RD-N2

 Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h   |  90 +
 .../ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl   | 132 +++
 .../ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 162 
 Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl  | 364 ++
 Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl  | 294 ++
 .../ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 306 +++
 .../ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 132 +++
 7 files changed, 1480 insertions(+)

-- 
2.17.1




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Re: [edk2-devel] [PATCH] UefiCpuPkg/MpInitLib: Properly cast from PCD to SEV-ES jump table pointer

[Laszlo Ersek]

On 05/10/21 16:24, Lendacky, Thomas wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3385
> 
> A VS2012 build fails with a cast conversion warning when the SEV-ES work
> area PCD is cast as a pointer to the SEV_ES_AP_JMP_FAR type.
> 
> When casting from a PCD value to a pointer, the cast should first be done
> to a UINTN and then to the pointer. Update the code to perform a cast to
> a UINTN before casting to a pointer to the SEV_ES_AP_JMP_FAR type.
> 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Laszlo Ersek 
> Cc: Rahul Kumar 
> Signed-off-by: Tom Lendacky 
> ---
>  UefiCpuPkg/Library/MpInitLib/MpLib.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c 
> b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> index 3d945972a025..dc2a54aa31e8 100644
> --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> @@ -1265,7 +1265,7 @@ SetSevEsJumpTable (
>UINT32Offset, InsnByte;
>UINT8 LoNib, HiNib;
>  
> -  JmpFar = (SEV_ES_AP_JMP_FAR *) FixedPcdGet32 (PcdSevEsWorkAreaBase);
> +  JmpFar = (SEV_ES_AP_JMP_FAR *) (UINTN) FixedPcdGet32 
> (PcdSevEsWorkAreaBase);
>ASSERT (JmpFar != NULL);
>  
>//
> 

Merged as commit 6933c78e4dc2, via
.

Thanks
Laszlo



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Re: [edk2-devel] [PATCH 13/13] OvmfPkg/BaseMemEncryptSevLib: remove Flush parameter

[Brijesh Singh]

On 5/11/21 6:55 AM, Laszlo Ersek wrote:
> I don't fully understand the updates in this patch:
>
> On 05/07/21 22:38, Brijesh Singh wrote:
>> BZ: 
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D3275data=04%7C01%7Cbrijesh.singh%40amd.com%7Cc383d8fdc1264644760508d91473b003%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637563309382960811%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=M3xHM2yU0m3VtPn1xGe1k5Wq0d6Vbdf9gMqDX1NxpgA%3Dreserved=0
>>
>> The Flush parameter is used to provide a hint whether the specified range
>> is Mmio address. Now that we have a dedicated helper to clear the
>> memory encryption mask for the Mmio address range, its safe to remove the
>> Flush parameter from MemEncryptSev{Set,Clear}PageEncMask().
> This looks good; it matches my request (1) from:
>
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flistman.redhat.com%2Farchives%2Fedk2-devel-archive%2F2021-May%2Fmsg00109.htmldata=04%7C01%7Cbrijesh.singh%40amd.com%7Cc383d8fdc1264644760508d91473b003%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637563309382960811%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=3TQrliMABDaa%2FtCN%2FvKewTmLfVRKIou2La5yRGGyzJY%3Dreserved=0
>
>> Cc: James Bottomley 
>> Cc: Min Xu 
>> Cc: Jiewen Yao 
>> Cc: Tom Lendacky 
>> Cc: Jordan Justen 
>> Cc: Ard Biesheuvel 
>> Cc: Laszlo Ersek 
>> Cc: Erdem Aktas 
>> Signed-off-by: Brijesh Singh 
>> ---
>>  OvmfPkg/Include/Library/MemEncryptSevLib.h| 10 ++
>>  .../BaseMemEncryptSevLib/X64/VirtualMemory.h  | 10 ++
>>  OvmfPkg/AmdSevDxe/AmdSevDxe.c |  3 +-
>>  OvmfPkg/IoMmuDxe/AmdSevIoMmu.c|  6 ++--
>>  .../Ia32/MemEncryptSevLib.c   | 10 ++
>>  .../X64/MemEncryptSevLib.c| 16 +++---
>>  .../X64/PeiDxeVirtualMemory.c | 32 +++
>>  .../X64/SecVirtualMemory.c|  8 ++---
>>  .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.c |  3 +-
>>  OvmfPkg/PlatformPei/AmdSev.c  |  3 +-
>>  10 files changed, 35 insertions(+), 66 deletions(-)
>>
>> diff --git a/OvmfPkg/Include/Library/MemEncryptSevLib.h 
>> b/OvmfPkg/Include/Library/MemEncryptSevLib.h
>> index b91490d5d44d..76d06c206c8b 100644
>> --- a/OvmfPkg/Include/Library/MemEncryptSevLib.h
>> +++ b/OvmfPkg/Include/Library/MemEncryptSevLib.h
>> @@ -100,8 +100,6 @@ MemEncryptSevIsEnabled (
>>address of a memory region.
>>@param[in]  NumPagesThe number of pages from start memory
>>region.
>> -  @param[in]  Flush   Flush the caches before clearing the 
>> bit
>> -  (mostly TRUE except MMIO addresses)
>>
>>@retval RETURN_SUCCESS  The attributes were cleared for the
>>memory region.
>> @@ -114,8 +112,7 @@ EFIAPI
>>  MemEncryptSevClearPageEncMask (
>>IN PHYSICAL_ADDRESS Cr3BaseAddress,
>>IN PHYSICAL_ADDRESS BaseAddress,
>> -  IN UINTNNumPages,
>> -  IN BOOLEAN  Flush
>> +  IN UINTNNumPages
>>);
>>
>>  /**
>> @@ -128,8 +125,6 @@ MemEncryptSevClearPageEncMask (
>>address of a memory region.
>>@param[in]  NumPagesThe number of pages from start memory
>>region.
>> -  @param[in]  Flush   Flush the caches before setting the 
>> bit
>> -  (mostly TRUE except MMIO addresses)
>>
>>@retval RETURN_SUCCESS  The attributes were set for the memory
>>region.
>> @@ -142,8 +137,7 @@ EFIAPI
>>  MemEncryptSevSetPageEncMask (
>>IN PHYSICAL_ADDRESS Cr3BaseAddress,
>>IN PHYSICAL_ADDRESS BaseAddress,
>> -  IN UINTNNumPages,
>> -  IN BOOLEAN  Flush
>> +  IN UINTNNumPages
>>);
>>
>>
>> diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h 
>> b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h
>> index 8dc39e647b90..21bbbd1c4f9c 100644
>> --- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h
>> +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h
>> @@ -58,8 +58,6 @@ InternalGetMemEncryptionAddressMask (
>>@param[in]  PhysicalAddress The physical address that is the start
>>address of a memory region.
>>@param[in]  Length  The length of memory region
>> -  @param[in]  Flush   Flush the caches before applying the
>> -  encryption mask
>>
>>@retval RETURN_SUCCESS  The 

Re: [edk2-devel] [PATCH] UefiCpuPkg/MpInitLib: Properly cast from PCD to SEV-ES jump table pointer

[Laszlo Ersek]

On 05/10/21 21:33, Lendacky, Thomas wrote:
> On 5/10/21 9:24 AM, Lendacky, Thomas via groups.io wrote:
>> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3385
>>
>> A VS2012 build fails with a cast conversion warning when the SEV-ES work
>> area PCD is cast as a pointer to the SEV_ES_AP_JMP_FAR type.
>>
>> When casting from a PCD value to a pointer, the cast should first be done
>> to a UINTN and then to the pointer. Update the code to perform a cast to
>> a UINTN before casting to a pointer to the SEV_ES_AP_JMP_FAR type.
>>
> 
> I should have included a Fixes: 7b7508ad784d16a5208c8d12dff43aef6df0835b tag.
> 

Thanks for the note, I'm picking that up.
Laszlo

> Tom
> 
>> Cc: Eric Dong 
>> Cc: Ray Ni 
>> Cc: Laszlo Ersek 
>> Cc: Rahul Kumar 
>> Signed-off-by: Tom Lendacky 
>> ---
>>  UefiCpuPkg/Library/MpInitLib/MpLib.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c 
>> b/UefiCpuPkg/Library/MpInitLib/MpLib.c
>> index 3d945972a025..dc2a54aa31e8 100644
>> --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
>> +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
>> @@ -1265,7 +1265,7 @@ SetSevEsJumpTable (
>>UINT32Offset, InsnByte;
>>UINT8 LoNib, HiNib;
>>  
>> -  JmpFar = (SEV_ES_AP_JMP_FAR *) FixedPcdGet32 (PcdSevEsWorkAreaBase);
>> +  JmpFar = (SEV_ES_AP_JMP_FAR *) (UINTN) FixedPcdGet32 
>> (PcdSevEsWorkAreaBase);
>>ASSERT (JmpFar != NULL);
>>  
>>//
>>
> 
> 
> 
> 
> 



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Re: [edk2-devel] [PATCH 07/13] MdePkg/BaseLib: add support for PVALIDATE instruction

[Brijesh Singh]

On 5/11/21 5:29 AM, Laszlo Ersek wrote:
> On 05/07/21 22:38, Brijesh Singh wrote:
>> BZ: 
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D3275data=04%7C01%7Cbrijesh.singh%40amd.com%7Cc5e03d8f093c430d01b608d91467bc91%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637563258060234952%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=QFATwHj5Jtoughp2bLTtFChUuKCWzQBSOGcZb2I%2B534%3Dreserved=0
>>
>> The PVALIDATE instruction validates or rescinds validation of a guest
>> page RMP entry. Upon completion, a return code is stored in EAX, rFLAGS
>> bits OF, ZF, AF, PF and SF are set based on this return code. If the
>> instruction completed succesfully, the rFLAGS bit CF indicates if the
>> contents of the RMP entry were changed or not.
>>
>> For more information about the instruction see AMD APM volume 3.
>>
>> Cc: James Bottomley 
>> Cc: Min Xu 
>> Cc: Jiewen Yao 
>> Cc: Tom Lendacky 
>> Cc: Jordan Justen 
>> Cc: Ard Biesheuvel 
>> Cc: Laszlo Ersek 
>> Cc: Erdem Aktas 
>> Cc: Michael D Kinney 
>> Cc: Liming Gao 
>> Cc: Zhiguang Liu 
>> Signed-off-by: Brijesh Singh 
>> ---
>>  MdePkg/Library/BaseLib/BaseLib.inf|  1 +
>>  MdePkg/Include/Library/BaseLib.h  | 46 +++
>>  MdePkg/Include/X64/Nasm.inc   |  8 
>>  MdePkg/Library/BaseLib/X64/Pvalidate.nasm | 42 +
>>  4 files changed, 97 insertions(+)
>>  create mode 100644 MdePkg/Library/BaseLib/X64/Pvalidate.nasm
>>
>> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
>> b/MdePkg/Library/BaseLib/BaseLib.inf
>> index b76f3af380ea..89a52f72c08a 100644
>> --- a/MdePkg/Library/BaseLib/BaseLib.inf
>> +++ b/MdePkg/Library/BaseLib/BaseLib.inf
>> @@ -317,6 +317,7 @@ [Sources.X64]
>>X64/GccInlinePriv.c | GCC
>>X64/EnableDisableInterrupts.nasm
>>X64/DisablePaging64.nasm
>> +  X64/Pvalidate.nasm
>>X64/RdRand.nasm
>>X64/XGetBv.nasm
>>X64/XSetBv.nasm
>> diff --git a/MdePkg/Include/Library/BaseLib.h 
>> b/MdePkg/Include/Library/BaseLib.h
>> index 7253997a6f8c..f177034af6a1 100644
>> --- a/MdePkg/Include/Library/BaseLib.h
>> +++ b/MdePkg/Include/Library/BaseLib.h
>> @@ -4813,6 +4813,52 @@ SpeculationBarrier (
>>VOID
>>);
>>  
>> +#if defined (MDE_CPU_X64)
>> +//
>> +// The page size for the PVALIDATE instruction
>> +//
>> +typedef enum {
>> +  PvalidatePageSize4K = 0,
>> +  PvalidatePageSize2MB,
>> +} PVALIDATE_PAGE_SIZE;
>> +
>> +//
>> +// PVALIDATE Return Code.
>> +//
>> +#define PVALIDATE_RET_SUCCESS 0
>> +#define PVALIDATE_RET_FAIL_INPUT  1
>> +#define PVALIDATE_RET_SIZE_MISMATCH   6
>> +
>> +//
>> +// The PVALIDATE instruction did not made any changes to the RMP entry.
> (1) Typo: should be "did not make".
Noted.
>
>> +//
>> +#define PVALIDATE_RET_NO_RMPUPDATE255
>> +
>> +/**
>> + Execute a PVALIDATE instruction to validate or rescinds validation of a 
>> guest
> (2) should be "to validate or to rescind validation" (infinitive form).
Noted.
>
>> + page's RMP entry.
>> +
>> + The instruction is available only when CPUID Fn8000_001F_EAX[SNP]=1.
>> +
>> + The function is available on X64.
>> +
>> + @param[in]PageSize The page size to use.
>> + @param[in]Validate Validate or rescinds.
> (3) If you use the imperative for "validate", then "rescinds"
> (indicative) reads strangely.
I will use validate or invalidate in future patches.
>
>> + @param[in]Address  The guest virtual address to validate.
>> +
>> + @retval   The return value from the PVALIDATE instruction, and
>> +   PVALIDATE_RET_NO_RMPUPDATE when there was no change in
>> +   the RMP entry.
> (4) @retval is only usable with actual return values (constants). If you
> provide a natural language explanation, then @return is the proper
> doxygen directive.
>
> You can combine these BTW, for example:
>
>   @retval PVALIDATE_RET_SUCCESS   The PVALIDATE instruction
>   succeeded, and updated the RMP
>   entry.
>   @retval PVALIDATE_RET_NO_RMPUPDATE  The PVALIDATE instruction
>   succeeded, but did not update the
>   RMP entry.
>   @return Failure codes from the PVALIDATE
>   instruction.

Will do.


>> +**/
>> +UINTN
>> +EFIAPI
>> +AsmPvalidate (
>> +  IN   PVALIDATE_PAGE_SIZE PageSize,
>> +  IN   BOOLEAN Validate,
>> +  IN   PHYSICAL_ADDRESSAddress
>> +  );
>> +#endif
>> +
>>  
>>  #if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
>>  ///
>> diff --git a/MdePkg/Include/X64/Nasm.inc b/MdePkg/Include/X64/Nasm.inc
>> index 527f71e9eb4d..528bb3385609 100644
>> --- a/MdePkg/Include/X64/Nasm.inc
>> +++ b/MdePkg/Include/X64/Nasm.inc
>> @@ -33,6 +33,14 @@
>>  DB 0xF3, 0x48, 0x0F, 0xAE, 0xE8
>>  %endmacro

Re: [edk2-devel] [PATCH] UefiCpuPkg/MpInitLib: Properly cast from PCD to SEV-ES jump table pointer

[Laszlo Ersek]

On 05/10/21 16:24, Lendacky, Thomas wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3385
> 
> A VS2012 build fails with a cast conversion warning when the SEV-ES work
> area PCD is cast as a pointer to the SEV_ES_AP_JMP_FAR type.
> 
> When casting from a PCD value to a pointer, the cast should first be done
> to a UINTN and then to the pointer. Update the code to perform a cast to
> a UINTN before casting to a pointer to the SEV_ES_AP_JMP_FAR type.
> 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Laszlo Ersek 
> Cc: Rahul Kumar 
> Signed-off-by: Tom Lendacky 
> ---
>  UefiCpuPkg/Library/MpInitLib/MpLib.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c 
> b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> index 3d945972a025..dc2a54aa31e8 100644
> --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> @@ -1265,7 +1265,7 @@ SetSevEsJumpTable (
>UINT32Offset, InsnByte;
>UINT8 LoNib, HiNib;
>  
> -  JmpFar = (SEV_ES_AP_JMP_FAR *) FixedPcdGet32 (PcdSevEsWorkAreaBase);
> +  JmpFar = (SEV_ES_AP_JMP_FAR *) (UINTN) FixedPcdGet32 
> (PcdSevEsWorkAreaBase);
>ASSERT (JmpFar != NULL);
>  
>//
> 

Reviewed-by: Laszlo Ersek 



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Re: [edk2-devel] 回复: [PATCH v3 0/2] MdePkg,SecurityPkg: Add support to RngDxe and BaseRngLib for AARCH64 RNDR

[Ard Biesheuvel]

On Tue, 11 May 2021 at 05:03, gaoliming  wrote:
>
> Thanks for your update. This version patches are good to me.
>
> Reviewed-by: Liming Gao 
>

Merged as #1633

Thanks all,

> > -邮件原件-
> > 发件人: Rebecca Cran 
> > 发送时间: 2021年5月11日 5:53
> > 收件人: devel@edk2.groups.io; Jiewen Yao ; Jian J
> > Wang ; Michael D Kinney
> > ; Liming Gao ;
> > Zhiguang Liu ; Ard Biesheuvel
> > ; Sami Mujawar 
> > 抄送: Rebecca Cran 
> > 主题: [PATCH v3 0/2] MdePkg,SecurityPkg: Add support to RngDxe and
> > BaseRngLib for AARCH64 RNDR
> >
> > Update MdePkg BaseRngLib and SecurityPkg RngDxe to add support for
> > the AARCH64 RNDR instruction.
> >
> > Changes from v2 to v3:
> >
> > o Fixed the default value of
> > gEfiSecurityPkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm
> >   to be an empty GUID.
> > o Removed RNDRRS since it wasn't being used.
> > o Fixed the commit message to remove mention of BaseLib.
> >
> > Rebecca Cran (2):
> >   MdePkg/BaseRngLib: Add support for ARMv8.5 RNG instructions
> >   SecurityPkg: Add support for RngDxe on AARCH64
> >
> >  MdePkg/MdePkg.dec
> > |   9 +-
> >  SecurityPkg/SecurityPkg.dec   |
> > 2 +
> >  MdePkg/MdePkg.dsc
> > |   4 +-
> >  SecurityPkg/SecurityPkg.dsc   |
> > 11 +-
> >  MdePkg/Library/BaseRngLib/BaseRngLib.inf  |
> > 23 ++-
> >  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf   |
> > 24 ++-
> >  MdePkg/Library/BaseRngLib/AArch64/ArmRng.h|
> > 43 +
> >  MdePkg/Library/BaseRngLib/BaseRngLibInternals.h   |
> > 78 +
> >  SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/AesCore.h |
> > 0
> >  SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/RdRand.h  |
> > 17 --
> >  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxeInternals.h|
> > 117 ++
> >  MdePkg/Library/BaseRngLib/AArch64/Rndr.c  |
> > 139 
> >  MdePkg/Library/BaseRngLib/BaseRng.c   |
> > 87 +-
> >  MdePkg/Library/BaseRngLib/Rand/RdRand.c   |
> > 131 +++
> >  SecurityPkg/RandomNumberGenerator/RngDxe/AArch64/RngDxe.c |
> > 127 +++
> >  SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/AesCore.c |
> > 0
> >  SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/RdRand.c  |
> > 45 +-
> >  SecurityPkg/RandomNumberGenerator/RngDxe/Rand/RngDxe.c|
> > 146 +
> >  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.c |
> > 170 
> >  MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.S|
> > 31 
> >  MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.asm  |
> > 30 
> >  MdePkg/Library/BaseRngLib/AArch64/ArmRng.S|
> > 37 +
> >  MdePkg/Library/BaseRngLib/AArch64/ArmRng.asm  |
> > 39 +
> >  MdePkg/Library/BaseRngLib/BaseRngLib.uni  |
> > 6 +-
> >  24 files changed, 1086 insertions(+), 230 deletions(-)
> >  create mode 100644 MdePkg/Library/BaseRngLib/AArch64/ArmRng.h
> >  create mode 100644 MdePkg/Library/BaseRngLib/BaseRngLibInternals.h
> >  rename SecurityPkg/RandomNumberGenerator/RngDxe/{ =>
> > Rand}/AesCore.h (100%)
> >  rename SecurityPkg/RandomNumberGenerator/RngDxe/{ =>
> > Rand}/RdRand.h (72%)
> >  create mode 100644
> > SecurityPkg/RandomNumberGenerator/RngDxe/RngDxeInternals.h
> >  create mode 100644 MdePkg/Library/BaseRngLib/AArch64/Rndr.c
> >  create mode 100644 MdePkg/Library/BaseRngLib/Rand/RdRand.c
> >  create mode 100644
> > SecurityPkg/RandomNumberGenerator/RngDxe/AArch64/RngDxe.c
> >  rename SecurityPkg/RandomNumberGenerator/RngDxe/{ =>
> > Rand}/AesCore.c (100%)
> >  rename SecurityPkg/RandomNumberGenerator/RngDxe/{ =>
> > Rand}/RdRand.c (71%)
> >  create mode 100644
> > SecurityPkg/RandomNumberGenerator/RngDxe/Rand/RngDxe.c
> >  create mode 100644
> > MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.S
> >  create mode 100644
> > MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.asm
> >  create mode 100644 MdePkg/Library/BaseRngLib/AArch64/ArmRng.S
> >  create mode 100644 MdePkg/Library/BaseRngLib/AArch64/ArmRng.asm
> >
> > --
> > 2.26.2
>
>
>
>
>
> 
>
>


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Re: [edk2-devel] [PATCH] IntelSiliconPkg/VTd: Support queued invalidation interface

[Huang, Jenny]

Reviewed by Jenny Huang.

-Original Message-
From: Sheng, W  
Sent: Thursday, April 29, 2021 11:55 PM
To: devel@edk2.groups.io
Cc: Huang, Jenny ; Yao, Jiewen ; 
Ni, Ray ; Chaganty, Rangasai V 
Subject: [PATCH] IntelSiliconPkg/VTd: Support queued invalidation interface

Add queued invalidation interface support for VTd core driver.
For software to invalidate the various caching structures, the architecture  
supports the following two types of invalidation interfaces.
1. Register-based invalidation interface 2. Queued invalidation interface.
BIOS shall check VER_REG to determine if register based invalidation can  be 
used. Only for Major Version 6 or lower can support register based  
invalidation. For any version newer than that should use queue  invalidation 
interface instead.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3366

Signed-off-by: Sheng Wei 
Cc: Jenny Huang 
Cc: Jiewen Yao 
Cc: Ray Ni 
Cc: Rangasai V Chaganty 
---
 .../Feature/VTd/IntelVTdDmarPei/DmarTable.c|   2 +
 .../Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c | 443 +++--
 .../Feature/VTd/IntelVTdDmarPei/IntelVTdDmarPei.c  |  15 +  
.../Feature/VTd/IntelVTdDmarPei/IntelVTdDmarPei.h  |  19 +
 .../Feature/VTd/IntelVTdDmarPei/TranslationTable.c |   2 -
 .../Feature/VTd/IntelVTdDxe/DmaProtection.h|  29 ++
 .../Feature/VTd/IntelVTdDxe/VtdReg.c   | 313 +--
 .../IntelSiliconPkg/Include/IndustryStandard/Vtd.h |  57 +++
 8 files changed, 813 insertions(+), 67 deletions(-)

diff --git 
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/DmarTable.c 
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/DmarTable.c
index d188f917..2154690d 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/DmarTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/DmarTabl
+++ e.c
@@ -561,6 +561,8 @@ ProcessDhrd (
   DEBUG ((DEBUG_INFO,"  VTD BaseAddress -  0x%016lx\n", 
DmarDrhd->RegisterBaseAddress));
   VTdUnitInfo->VtdUnitBaseAddress = (UINT32) DmarDrhd->RegisterBaseAddress;
 
+  VTdUnitInfo->EnableQueuedInvalidation = 0;
+
   DEBUG ((DEBUG_INFO,"  VTD Segment - %d\n", DmarDrhd->SegmentNumber));
   VTdUnitInfo->Segment = DmarDrhd->SegmentNumber;
 
diff --git 
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c 
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c
index 9ad2a494..f0bd7dc6 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTd
+++ Dmar.c
@@ -66,30 +66,269 @@ FlushWriteBuffer (
 }
 
 /**
-  Invalidate VTd context cache.
+  Perpare cache invalidation interface.
 
-  @param[in]  VtdUnitBaseAddressThe base address of the VTd engine.
+  @param[in]  VTdUnitInfo   The VTd engine unit information.
+
+  @retval EFI_SUCCESS   The operation was successful.
+  @retval EFI_UNSUPPORTED   Invalidation method is not supported.
+  @retval EFI_OUT_OF_RESOURCES  A memory allocation failed.
 **/
 EFI_STATUS
-InvalidateContextCache (
-  IN UINTN  VtdUnitBaseAddress
+PerpareCacheInvalidationInterface (
+  IN VTD_UNIT_INFO *VTdUnitInfo
   )
 {
-  UINT64Reg64;
+  UINT16 QueueSize;
+  UINT64 Reg64;
+  UINT32 Reg32;
+  VTD_ECAP_REG   ECapReg;
+
+
+  if (VTdUnitInfo->VerReg.Bits.Major <= 6) {
+VTdUnitInfo->EnableQueuedInvalidation = 0;
+DEBUG ((DEBUG_INFO, "Use Register-based Invalidation Interface for engine 
[0x%x]\n", VTdUnitInfo->VtdUnitBaseAddress));
+return EFI_SUCCESS;
+  }
+
+  ECapReg.Uint64 = MmioRead64 ((UINTN)VTdUnitInfo->VtdUnitBaseAddress + 
+ R_ECAP_REG);  if (ECapReg.Bits.QI == 0) {
+DEBUG ((DEBUG_ERROR, "Hardware does not support queued invalidations 
interface for engine [0x%x]\n", VTdUnitInfo->VtdUnitBaseAddress));
+return EFI_UNSUPPORTED;
+  }
+
+  VTdUnitInfo->EnableQueuedInvalidation = 1;  DEBUG ((DEBUG_INFO, "Use 
+ Queued Invalidation Interface for engine [0x%x]\n", 
+ VTdUnitInfo->VtdUnitBaseAddress));
+
+  Reg32 = MmioRead32 ((UINTN)VTdUnitInfo->VtdUnitBaseAddress + 
+ R_GSTS_REG);  if ((Reg32 & B_GSTS_REG_QIES) != 0) {
+DEBUG ((DEBUG_INFO,"Queued Invalidation Interface was enabled.\n"));
+Reg32 &= (~B_GSTS_REG_QIES);
+MmioWrite32 ((UINTN)VTdUnitInfo->VtdUnitBaseAddress + R_GCMD_REG, Reg32);
+do {
+  Reg32 = MmioRead32 ((UINTN)VTdUnitInfo->VtdUnitBaseAddress + R_GSTS_REG);
+} while ((Reg32 & B_GSTS_REG_QIES) != 0);
+MmioWrite64 ((UINTN)VTdUnitInfo->VtdUnitBaseAddress + R_IQA_REG, 
+ 0);
+
+if (VTdUnitInfo->QiDesc != NULL) {
+  FreePages(VTdUnitInfo->QiDesc, EFI_SIZE_TO_PAGES(sizeof(QI_DESC) * 
VTdUnitInfo->QiDescLength));
+  VTdUnitInfo->QiDesc = NULL;
+  VTdUnitInfo->QiDescLength = 0;
+}
+  }
+
+  //
+  // Initialize the Invalidation Queue Tail Register to zero.
+  //
+  MmioWrite64 

Re: [edk2-devel] [PATCH v1 0/2] Add GIC ITS entry to MADT

[Shashi Mallela]

Gentle reminder for ITS changes review.

The accompanying qemu git branch with ITS changes is available at
https://github.com/shashi-j/qemu.git


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Re: [edk2-devel] [PATCH v3 2/2] SecurityPkg: Add support for RngDxe on AARCH64

[Sami Mujawar]

This patch looks good to me.

Reviewed-by: Sami Mujawar 

Regards,

Sami Mujawar


On 10/05/2021 10:53 PM, Rebecca Cran wrote:

AARCH64 support has been added to BaseRngLib via the optional
ARMv8.5 FEAT_RNG.

Refactor RngDxe to support AARCH64, note support for it in the
VALID_ARCHITECTURES line of RngDxe.inf and enable it in SecurityPkg.dsc.

Signed-off-by: Rebecca Cran 
---
  SecurityPkg/SecurityPkg.dec   |   2 +
  SecurityPkg/SecurityPkg.dsc   |  11 +-
  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf   |  24 ++-
  SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/AesCore.h |   0
  SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/RdRand.h  |  17 --
  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxeInternals.h| 117 
++
  SecurityPkg/RandomNumberGenerator/RngDxe/AArch64/RngDxe.c | 127 
+++
  SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/AesCore.c |   0
  SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/RdRand.c  |  45 +-
  SecurityPkg/RandomNumberGenerator/RngDxe/Rand/RngDxe.c| 146 
+
  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.c | 170 

  11 files changed, 483 insertions(+), 176 deletions(-)

diff --git a/SecurityPkg/SecurityPkg.dec b/SecurityPkg/SecurityPkg.dec
index dfbbb0365a2b..4001650fa28e 100644
--- a/SecurityPkg/SecurityPkg.dec
+++ b/SecurityPkg/SecurityPkg.dec
@@ -297,6 +297,8 @@ [PcdsFixedAtBuild, PcdsPatchableInModule]

gEfiSecurityPkgTokenSpaceGuid.PcdStatusCodeFvVerificationPass|0x0303100A|UINT32|0x00010030

gEfiSecurityPkgTokenSpaceGuid.PcdStatusCodeFvVerificationFail|0x0303100B|UINT32|0x00010031

+  
gEfiSecurityPkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x00010032
+
  [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
## Image verification policy for OptionRom. Only following values are 
valid:
#  NOTE: Do NOT use 0x5 and 0x2 since it violates the UEFI specification and has 
been removed.
diff --git a/SecurityPkg/SecurityPkg.dsc b/SecurityPkg/SecurityPkg.dsc
index 12ccd1634941..bd4b810bce61 100644
--- a/SecurityPkg/SecurityPkg.dsc
+++ b/SecurityPkg/SecurityPkg.dsc
@@ -259,6 +259,12 @@ [Components]
  [Components.IA32, Components.X64, Components.ARM, Components.AARCH64]
SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf

+[Components.IA32, Components.X64, Components.AARCH64]
+  #
+  # Random Number Generator
+  #
+  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
+
  [Components.IA32, Components.X64]

SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf

@@ -334,11 +340,6 @@ [Components.IA32, Components.X64]

SecurityPkg/Library/SmmTcg2PhysicalPresenceLib/SmmTcg2PhysicalPresenceLib.inf

SecurityPkg/Library/SmmTcg2PhysicalPresenceLib/StandaloneMmTcg2PhysicalPresenceLib.inf

-  #
-  # Random Number Generator
-  #
-  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
-
#
# Opal Password solution
#
diff --git a/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf 
b/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
index 99d6f6b35fc2..f3300971993f 100644
--- a/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
+++ b/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
@@ -26,15 +26,22 @@ [Defines]
  #
  # The following information is for reference only and not required by the 
build tools.
  #
-#  VALID_ARCHITECTURES   = IA32 X64
+#  VALID_ARCHITECTURES   = IA32 X64 AARCH64
  #

  [Sources.common]
RngDxe.c
-  RdRand.c
-  RdRand.h
-  AesCore.c
-  AesCore.h
+  RngDxeInternals.h
+
+[Sources.IA32, Sources.X64]
+  Rand/RngDxe.c
+  Rand/RdRand.c
+  Rand/RdRand.h
+  Rand/AesCore.c
+  Rand/AesCore.h
+
+[Sources.AARCH64]
+  AArch64/RngDxe.c

  [Packages]
MdePkg/MdePkg.dec
@@ -50,12 +57,19 @@ [LibraryClasses]
RngLib

  [Guids]
+  gEfiRngAlgorithmSp80090Hash256Guid  ## SOMETIMES_PRODUCES## GUID
# Unique ID of the algorithm for RNG
+  gEfiRngAlgorithmSp80090Hmac256Guid  ## SOMETIMES_PRODUCES## GUID
# Unique ID of the algorithm for RNG
gEfiRngAlgorithmSp80090Ctr256Guid   ## SOMETIMES_PRODUCES## GUID
# Unique ID of the algorithm for RNG
+  gEfiRngAlgorithmX9313DesGuid## SOMETIMES_PRODUCES## GUID
# Unique ID of the algorithm for RNG
+  gEfiRngAlgorithmX931AesGuid ## SOMETIMES_PRODUCES## GUID
# Unique ID of the algorithm for RNG
gEfiRngAlgorithmRaw ## SOMETIMES_PRODUCES## GUID
# Unique ID of the algorithm for RNG

  [Protocols]
gEfiRngProtocolGuid## PRODUCES

+[Pcd]
+  gEfiSecurityPkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm  ## CONSUMES
+
  [Depex]
TRUE

diff --git a/SecurityPkg/RandomNumberGenerator/RngDxe/AesCore.h 

Re: [edk2-devel] [PATCH 06/13] MdePkg/Register/Amd: define GHCB macros for SNP AP creation

[Lendacky, Thomas]

On 5/11/21 4:59 AM, Laszlo Ersek wrote:
> On 05/07/21 22:38, Brijesh Singh wrote:
>> From: Tom Lendacky 
>>
>> BZ: 
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D3275data=04%7C01%7Cthomas.lendacky%40amd.com%7C92c1323bd1e84a2a38e208d914636ddf%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637563239563579592%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=DMDhcseilROSsL6EISUoT9p0pI%2BmXtEC3rLHIQS4NmI%3Dreserved=0
>>
>> Version 2 of GHCB introduces NAE for creating AP when SEV-SNP is
>> enabled in the guest VM. See the GHCB spec section for additional
>> details.
> 
> (1) The actual section reference is missing. I'll fix it up: from where
> the spec introduces exit code 0x8000_0013, the sections appear to be
> 4.1.9 and 4.3.2. Also, Table 5. "List of Supported Non-Automatic Events"
> is relevant for the SVM_VMGEXIT_SNP_AP_* macros.

There are some needed changes to this patch, so I can fix that up. I just
avoided putting actual section numbers in there because it is possible
that they can change in future versions.

> 
>>
>> While at it, define the VMSA state save area that are required for
> 
> (2) I think "area" (singular) is correct here, so we should say "is".
> I'll update it.

I can fix that up.

> 
>> creating the AP. The save area format is defined in AMD APM volume
>> 2 (Table B-4).
>>
>> Cc: James Bottomley 
>> Cc: Min Xu 
>> Cc: Jiewen Yao 
>> Cc: Tom Lendacky 
>> Cc: Jordan Justen 
>> Cc: Ard Biesheuvel 
>> Cc: Laszlo Ersek 
>> Cc: Erdem Aktas 
>> Cc: Michael D Kinney 
>> Cc: Liming Gao 
>> Cc: Zhiguang Liu 
>> Signed-off-by: Tom Lendacky 
>> Signed-off-by: Brijesh Singh 
>> ---
>>  MdePkg/Include/Register/Amd/Ghcb.h | 70 ++
>>  1 file changed, 70 insertions(+)
>>
>> diff --git a/MdePkg/Include/Register/Amd/Ghcb.h 
>> b/MdePkg/Include/Register/Amd/Ghcb.h
>> index a15b4b7e2760..956cefbc003c 100644
>> --- a/MdePkg/Include/Register/Amd/Ghcb.h
>> +++ b/MdePkg/Include/Register/Amd/Ghcb.h
>> @@ -55,6 +55,7 @@
>>  #define SVM_EXIT_AP_RESET_HOLD  0x8004ULL
>>  #define SVM_EXIT_AP_JUMP_TABLE  0x8005ULL
>>  #define SVM_EXIT_SNP_PAGE_STATE_CHANGE  0x8010ULL
>> +#define SVM_EXIT_SNP_AP_CREATION0x8013ULL
>>  #define SVM_EXIT_HYPERVISOR_FEATURES0x8000FFFDULL
>>  #define SVM_EXIT_UNSUPPORTED0x8000ULL
>>  
>> @@ -83,6 +84,12 @@
>>  #define IOIO_SEG_ES 0
>>  #define IOIO_SEG_DS (BIT11 | BIT10)
>>  
>> +//
>> +// AP Creation Information
>> +//
>> +#define SVM_VMGEXIT_SNP_AP_CREATE_ON_INIT  0
>> +#define SVM_VMGEXIT_SNP_AP_CREATE  1
>> +#define SVM_VMGEXIT_SNP_AP_DESTROY 2
>>  
>>  typedef PACKED struct {
>>UINT8  Reserved1[203];
>> @@ -195,4 +202,67 @@ typedef struct {
>>SNP_PAGE_STATE_ENTRY   Entry[SNP_PAGE_STATE_MAX_ENTRY];
>>  } SNP_PAGE_STATE_CHANGE_INFO;
>>  
>> +//
>> +// SEV-ES save area mapping structures used for SEV-SNP AP Creation.
>> +// Only the fields required to be set to a non-zero value are defined.
>> +//
>> +#pragma pack(1)
>> +typedef struct {
>> +  UINT16  Selector;
>> +  UINT16  Attributes;
>> +  UINT32  Limit;
>> +  UINT64  Base;
>> +} SEV_ES_SEGMENT_REGISTER;
>> +#pragma pack()
> 
> (3) there should be a space character between "pack" and "(" -- two
> instances.

Will do.

> 
>> +
>> +#define SEV_ES_RESET_CS_ATTRIBUTES(BIT7 | BIT4 | BIT3 | BIT1)
>> +#define SEV_ES_RESET_DS_ATTRIBUTES(BIT7 | BIT4 | BIT1)
>> +#define SEV_ES_RESET_ES_ATTRIBUTESSEV_ES_RESET_DS_ATTRIBUTES
>> +#define SEV_ES_RESET_FS_ATTRIBUTESSEV_ES_RESET_DS_ATTRIBUTES
>> +#define SEV_ES_RESET_GS_ATTRIBUTESSEV_ES_RESET_DS_ATTRIBUTES
>> +#define SEV_ES_RESET_SS_ATTRIBUTESSEV_ES_RESET_DS_ATTRIBUTES
>> +
>> +#define SEV_ES_RESET_GDTR_ATTRIBUTES  0
>> +#define SEV_ES_RESET_LDTR_ATTRIBUTES  (BIT7 | 2)
>> +#define SEV_ES_RESET_IDTR_ATTRIBUTES  0
>> +#define SEV_ES_RESET_TR_ATTRIBUTES(BIT7 | 3)
> 
> (4) ... I guess I can't go ahead merging this myself, after all (Liming
> may of course still merge the MdePkg patches, if he wants to).
> 
> My problem here is that the bit positions are cryptic.
> 
> I've found the *normal* (not SEV-ES) segment descriptor attributes in
> the AMD APM (publication #24593, revision 3.37, date March 2021, volume
> 2, sections sections 4.7 and 4.8).
> 
> However, the bit positions SEV-ES descriptors are surely different. For
> the "normal" segment descriptors, we already have the
> IA32_SEGMENT_DESCRIPTOR type in edk2, with the nicely broken-out
> attribute bits. The bit meanings within
> "SEV_ES_SEGMENT_REGISTER.Attributes" remain unclear to me.
> 
> Please at least provide a *specific* documentation reference in the
> commit message where I can verify (or at least "decode") the attribute bits.

Yeah, it is a strange format. The format is documented in sections 15.5
(VMRUN 

Re: [edk2-devel] [PATCH v3 1/2] MdePkg/BaseRngLib: Add support for ARMv8.5 RNG instructions

[Sami Mujawar]

This patch looks good to me.

Reviewed-by: Sami Mujawar 

Regards,

Sami Mujawar


On 10/05/2021 10:53 PM, Rebecca Cran wrote:

Make BaseRngLib more generic by moving x86-specific functionality into
'Rand' and adding files under 'AArch64' to support the optional ARMv8.5
RNG instruction RNDR that is a part of FEAT_RNG.

Signed-off-by: Rebecca Cran 
---
  MdePkg/MdePkg.dec|   9 +-
  MdePkg/MdePkg.dsc|   4 +-
  MdePkg/Library/BaseRngLib/BaseRngLib.inf |  23 +++-
  MdePkg/Library/BaseRngLib/AArch64/ArmRng.h   |  43 ++
  MdePkg/Library/BaseRngLib/BaseRngLibInternals.h  |  78 +++
  MdePkg/Library/BaseRngLib/AArch64/Rndr.c | 139 

  MdePkg/Library/BaseRngLib/BaseRng.c  |  87 ++--
  MdePkg/Library/BaseRngLib/Rand/RdRand.c  | 131 ++
  MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.S   |  31 +
  MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.asm |  30 +
  MdePkg/Library/BaseRngLib/AArch64/ArmRng.S   |  37 ++
  MdePkg/Library/BaseRngLib/AArch64/ArmRng.asm |  39 ++
  MdePkg/Library/BaseRngLib/BaseRngLib.uni |   6 +-
  13 files changed, 603 insertions(+), 54 deletions(-)

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index 8965e903e093..b49f88d8e18f 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -267,6 +267,11 @@ [LibraryClasses]
#
RegisterFilterLib|Include/Library/RegisterFilterLib.h

+[LibraryClasses.IA32, LibraryClasses.X64, LibraryClasses.AARCH64]
+  ##  @libraryclass  Provides services to generate random number.
+  #
+  RngLib|Include/Library/RngLib.h
+
  [LibraryClasses.IA32, LibraryClasses.X64]
##  @libraryclass  Abstracts both S/W SMI generation and detection.
##
@@ -288,10 +293,6 @@ [LibraryClasses.IA32, LibraryClasses.X64]
#
SmmPeriodicSmiLib|Include/Library/SmmPeriodicSmiLib.h

-  ##  @libraryclass  Provides services to generate random number.
-  #
-  RngLib|Include/Library/RngLib.h
-
##  @libraryclass  Provides services to log the SMI handler registration.
SmiHandlerProfileLib|Include/Library/SmiHandlerProfileLib.h

diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
index d363419006ea..a94959169b2f 100644
--- a/MdePkg/MdePkg.dsc
+++ b/MdePkg/MdePkg.dsc
@@ -145,6 +145,9 @@ [Components.IA32, Components.X64, Components.ARM, 
Components.AARCH64]
MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibSmm.inf
MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibUefiShell.inf

+[Components.IA32, Components.X64, Components.AARCH64]
+  MdePkg/Library/BaseRngLib/BaseRngLib.inf
+
  [Components.IA32, Components.X64]
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf
@@ -168,7 +171,6 @@ [Components.IA32, Components.X64]
MdePkg/Library/BaseS3StallLib/BaseS3StallLib.inf
MdePkg/Library/SmmMemLib/SmmMemLib.inf
MdePkg/Library/SmmIoLib/SmmIoLib.inf
-  MdePkg/Library/BaseRngLib/BaseRngLib.inf
MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf
MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.inf
MdePkg/Library/MmServicesTableLib/MmServicesTableLib.inf
diff --git a/MdePkg/Library/BaseRngLib/BaseRngLib.inf 
b/MdePkg/Library/BaseRngLib/BaseRngLib.inf
index 31740751c69c..1fcceb941495 100644
--- a/MdePkg/Library/BaseRngLib/BaseRngLib.inf
+++ b/MdePkg/Library/BaseRngLib/BaseRngLib.inf
@@ -1,9 +1,10 @@
  ## @file
  #  Instance of RNG (Random Number Generator) Library.
  #
-#  BaseRng Library that uses CPU RdRand instruction access to provide
-#  high-quality random numbers.
+#  BaseRng Library that uses CPU RNG instructions (e.g. RdRand) to
+#  provide random numbers.
  #
+#  Copyright (c) 2021, NUVIA Inc. All rights reserved.
  #  Copyright (c) 2015, Intel Corporation. All rights reserved.
  #
  #  SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -22,11 +23,25 @@ [Defines]
CONSTRUCTOR= BaseRngLibConstructor

  #
-#  VALID_ARCHITECTURES   = IA32 X64
+#  VALID_ARCHITECTURES   = IA32 X64 AARCH64
  #

-[Sources.Ia32, Sources.X64]
+[Sources]
BaseRng.c
+  BaseRngLibInternals.h
+
+[Sources.Ia32, Sources.X64]
+  Rand/RdRand.c
+
+[Sources.AARCH64]
+  AArch64/Rndr.c
+  AArch64/ArmRng.h
+
+  AArch64/ArmReadIdIsar0.S   | GCC
+  AArch64/ArmRng.S   | GCC
+
+  AArch64/ArmReadIdIsar0.asm | MSFT
+  AArch64/ArmRng.asm | MSFT

  [Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseRngLib/AArch64/ArmRng.h 
b/MdePkg/Library/BaseRngLib/AArch64/ArmRng.h
new file mode 100644
index ..a597e98bf0d5
--- /dev/null
+++ b/MdePkg/Library/BaseRngLib/AArch64/ArmRng.h
@@ -0,0 +1,43 @@
+/** @file
+  Random number generator service that uses the RNDR instruction
+  to provide pseudorandom numbers.
+
+  Copyright (c) 2021, NUVIA Inc. All rights reserved.
+
+  

Re: [edk2-devel] [PATCH v2] BaseTools: Add support for version 3 of FMP Image Header structure

[Michael D Kinney]

Hi Sughosh,

Thanks for the reminder.

We need to wait for one of the BaseTools maintainers to provide an Rb for the 
V2 version of this patch, then we will be able to merge.

Thanks,

Mike

From: Sughosh Ganu 
Sent: Tuesday, May 11, 2021 3:21 AM
To: Kinney, Michael D ; Feng, Bob C 
; Liming Gao ; Chen, Christine 

Cc: devel@edk2.groups.io
Subject: Re: [edk2-devel] [PATCH v2] BaseTools: Add support for version 3 of 
FMP Image Header structure

hi,
Can this patch be merged. Thanks.

-sughosh

On Mon, 26 Apr 2021 at 21:27, Kinney, Michael D 
mailto:michael.d.kin...@intel.com>> wrote:
Reviewed-by: Michael D Kinney 
mailto:michael.d.kin...@intel.com>>

Mike

> -Original Message-
> From: devel@edk2.groups.io 
> mailto:devel@edk2.groups.io>> On Behalf Of Sughosh Ganu
> Sent: Friday, April 23, 2021 4:29 AM
> To: devel@edk2.groups.io
> Cc: Michal Simek mailto:michal.si...@xilinx.com>>; 
> Sughosh Ganu mailto:sughosh.g...@linaro.org>>
> Subject: [edk2-devel] [PATCH v2] BaseTools: Add support for version 3 of FMP 
> Image Header structure
>
> Add support for the ImageCapsuleSupport field, introduced in version 3
> of the EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER structure. This
> structure member is used to indicate if the corresponding payload has
> support for authentication and dependency.
>
> Signed-off-by: Sughosh Ganu 
> mailto:sughosh.g...@linaro.org>>
> ---
>
> Changes since v1:
> - Reword the patch header to get rid of the PatchCheck warning
> - Make passing of ImageCapsuleSupport parameter to the AddPayload
>   function as an optional parameter to maintain backward compatibility
> - Declare the values of CAPSULE_SUPPORT_DEPENDENCY and
>   CAPSULE_SUPPORT_AUTHENTICATION in the FmpCapsuleHeaderClass and use
>   those in the GenerateCapsule script
>
>  .../Source/Python/Capsule/GenerateCapsule.py  |  5 +++-
>  .../Common/Uefi/Capsule/FmpCapsuleHeader.py   | 28 +--
>  2 files changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/BaseTools/Source/Python/Capsule/GenerateCapsule.py 
> b/BaseTools/Source/Python/Capsule/GenerateCapsule.py
> index a8de988253..b8039db878 100644
> --- a/BaseTools/Source/Python/Capsule/GenerateCapsule.py
> +++ b/BaseTools/Source/Python/Capsule/GenerateCapsule.py
> @@ -561,6 +561,7 @@ if __name__ == '__main__':
>  print ('GenerateCapsule: error:' + str(Msg))
>  sys.exit (1)
>  for SinglePayloadDescriptor in PayloadDescriptorList:
> +ImageCapsuleSupport = 0x
>  Result = SinglePayloadDescriptor.Payload
>  try:
>  FmpPayloadHeader.FwVersion  = 
> SinglePayloadDescriptor.FwVersion
> @@ -575,6 +576,7 @@ if __name__ == '__main__':
>  if SinglePayloadDescriptor.UseDependency:
>  CapsuleDependency.Payload = Result
>  CapsuleDependency.DepexExp = SinglePayloadDescriptor.DepexExp
> +ImageCapsuleSupport|= 
> FmpCapsuleHeader.CAPSULE_SUPPORT_DEPENDENCY
>  Result = CapsuleDependency.Encode ()
>  if args.Verbose:
>  CapsuleDependency.DumpInfo ()
> @@ -607,13 +609,14 @@ if __name__ == '__main__':
>  FmpAuthHeader.MonotonicCount = 
> SinglePayloadDescriptor.MonotonicCount
>  FmpAuthHeader.CertData   = CertData
>  FmpAuthHeader.Payload= Result
> +ImageCapsuleSupport  |= 
> FmpCapsuleHeader.CAPSULE_SUPPORT_AUTHENTICATION
>  Result = FmpAuthHeader.Encode ()
>  if args.Verbose:
>  FmpAuthHeader.DumpInfo ()
>  except:
>  print ('GenerateCapsule: error: can not encode FMP Auth 
> Header')
>  sys.exit (1)
> -FmpCapsuleHeader.AddPayload (SinglePayloadDescriptor.Guid, 
> Result, HardwareInstance =
> SinglePayloadDescriptor.HardwareInstance, UpdateImageIndex = 
> SinglePayloadDescriptor.UpdateImageIndex)
> +FmpCapsuleHeader.AddPayload (SinglePayloadDescriptor.Guid, 
> Result, HardwareInstance =
> SinglePayloadDescriptor.HardwareInstance, UpdateImageIndex = 
> SinglePayloadDescriptor.UpdateImageIndex, CapsuleSupport =
> ImageCapsuleSupport)
>  try:
>  for EmbeddedDriver in EmbeddedDriverDescriptorList:
>  FmpCapsuleHeader.AddEmbeddedDriver(EmbeddedDriver)
> diff --git a/BaseTools/Source/Python/Common/Uefi/Capsule/FmpCapsuleHeader.py
> b/BaseTools/Source/Python/Common/Uefi/Capsule/FmpCapsuleHeader.py
> index 91d24919c4..8abb449c6f 100644
> --- a/BaseTools/Source/Python/Common/Uefi/Capsule/FmpCapsuleHeader.py
> +++ b/BaseTools/Source/Python/Common/Uefi/Capsule/FmpCapsuleHeader.py
> @@ -47,14 +47,19 @@ class FmpCapsuleImageHeaderClass (object):
>  #   /// therefore can be modified without changing the Auth data.

Re: [edk2-devel] [PATCH v3 2/2] SecurityPkg: Add support for RngDxe on AARCH64

[Yao, Jiewen]

Acked-by: Jiewen Yao 

Need ARM expert to double confirm.

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Ard
> Biesheuvel
> Sent: Tuesday, May 11, 2021 10:44 PM
> To: Rebecca Cran ; Yao, Jiewen
> ; Wang, Jian J 
> Cc: edk2-devel-groups-io ; Kinney, Michael D
> ; Liming Gao ; Liu,
> Zhiguang ; Ard Biesheuvel
> ; Sami Mujawar 
> Subject: Re: [edk2-devel] [PATCH v3 2/2] SecurityPkg: Add support for RngDxe
> on AARCH64
> 
> On Mon, 10 May 2021 at 23:53, Rebecca Cran  wrote:
> >
> > AARCH64 support has been added to BaseRngLib via the optional
> > ARMv8.5 FEAT_RNG.
> >
> > Refactor RngDxe to support AARCH64, note support for it in the
> > VALID_ARCHITECTURES line of RngDxe.inf and enable it in SecurityPkg.dsc.
> >
> > Signed-off-by: Rebecca Cran 
> 
> I'm happy to take these and merge them if I can get an ack from a
> SecurityPkg maintainer.
> 
> 
> > ---
> >  SecurityPkg/SecurityPkg.dec   |   2 +
> >  SecurityPkg/SecurityPkg.dsc   |  11 +-
> >  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf   |  24 ++-
> >  SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/AesCore.h |   0
> >  SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/RdRand.h  |  17 --
> >  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxeInternals.h| 117
> ++
> >  SecurityPkg/RandomNumberGenerator/RngDxe/AArch64/RngDxe.c | 127
> +++
> >  SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/AesCore.c |   0
> >  SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/RdRand.c  |  45 +-
> 
> >  SecurityPkg/RandomNumberGenerator/RngDxe/Rand/RngDxe.c| 146
> +
> >  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.c | 170
> 
> >  11 files changed, 483 insertions(+), 176 deletions(-)
> >
> > diff --git a/SecurityPkg/SecurityPkg.dec b/SecurityPkg/SecurityPkg.dec
> > index dfbbb0365a2b..4001650fa28e 100644
> > --- a/SecurityPkg/SecurityPkg.dec
> > +++ b/SecurityPkg/SecurityPkg.dec
> > @@ -297,6 +297,8 @@ [PcdsFixedAtBuild, PcdsPatchableInModule]
> >
> gEfiSecurityPkgTokenSpaceGuid.PcdStatusCodeFvVerificationPass|0x0303100A|
> UINT32|0x00010030
> >
> gEfiSecurityPkgTokenSpaceGuid.PcdStatusCodeFvVerificationFail|0x0303100B|
> UINT32|0x00010031
> >
> > +
> gEfiSecurityPkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x0
> 0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID
> *|0x00010032
> > +
> >  [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
> >## Image verification policy for OptionRom. Only following values are
> valid:
> >#  NOTE: Do NOT use 0x5 and 0x2 since it violates the UEFI specification 
> > and
> has been removed.
> > diff --git a/SecurityPkg/SecurityPkg.dsc b/SecurityPkg/SecurityPkg.dsc
> > index 12ccd1634941..bd4b810bce61 100644
> > --- a/SecurityPkg/SecurityPkg.dsc
> > +++ b/SecurityPkg/SecurityPkg.dsc
> > @@ -259,6 +259,12 @@ [Components]
> >  [Components.IA32, Components.X64, Components.ARM,
> Components.AARCH64]
> >SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
> >
> > +[Components.IA32, Components.X64, Components.AARCH64]
> > +  #
> > +  # Random Number Generator
> > +  #
> > +  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
> > +
> >  [Components.IA32, Components.X64]
> >
> SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx
> e.inf
> >
> > @@ -334,11 +340,6 @@ [Components.IA32, Components.X64]
> >
> SecurityPkg/Library/SmmTcg2PhysicalPresenceLib/SmmTcg2PhysicalPresenceLib
> .inf
> >
> SecurityPkg/Library/SmmTcg2PhysicalPresenceLib/StandaloneMmTcg2PhysicalP
> resenceLib.inf
> >
> > -  #
> > -  # Random Number Generator
> > -  #
> > -  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
> > -
> >#
> ># Opal Password solution
> >#
> > diff --git a/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
> b/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
> > index 99d6f6b35fc2..f3300971993f 100644
> > --- a/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
> > +++ b/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
> > @@ -26,15 +26,22 @@ [Defines]
> >  #
> >  # The following information is for reference only and not required by the 
> > build
> tools.
> >  #
> > -#  VALID_ARCHITECTURES   = IA32 X64
> > +#  VALID_ARCHITECTURES   = IA32 X64 AARCH64
> >  #
> >
> >  [Sources.common]
> >RngDxe.c
> > -  RdRand.c
> > -  RdRand.h
> > -  AesCore.c
> > -  AesCore.h
> > +  RngDxeInternals.h
> > +
> > +[Sources.IA32, Sources.X64]
> > +  Rand/RngDxe.c
> > +  Rand/RdRand.c
> > +  Rand/RdRand.h
> > +  Rand/AesCore.c
> > +  Rand/AesCore.h
> > +
> > +[Sources.AARCH64]
> > +  AArch64/RngDxe.c
> >
> >  [Packages]
> >MdePkg/MdePkg.dec
> > @@ -50,12 +57,19 @@ [LibraryClasses]
> >RngLib
> >
> >  [Guids]
> > +  gEfiRngAlgorithmSp80090Hash256Guid  ## SOMETIMES_PRODUCES##
> GUID# Unique ID of the algorithm for RNG
> > +  

Re: [edk2-devel] [PATCH v3 2/2] SecurityPkg: Add support for RngDxe on AARCH64

[Ard Biesheuvel]

On Mon, 10 May 2021 at 23:53, Rebecca Cran  wrote:
>
> AARCH64 support has been added to BaseRngLib via the optional
> ARMv8.5 FEAT_RNG.
>
> Refactor RngDxe to support AARCH64, note support for it in the
> VALID_ARCHITECTURES line of RngDxe.inf and enable it in SecurityPkg.dsc.
>
> Signed-off-by: Rebecca Cran 

I'm happy to take these and merge them if I can get an ack from a
SecurityPkg maintainer.


> ---
>  SecurityPkg/SecurityPkg.dec   |   2 +
>  SecurityPkg/SecurityPkg.dsc   |  11 +-
>  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf   |  24 ++-
>  SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/AesCore.h |   0
>  SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/RdRand.h  |  17 --
>  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxeInternals.h| 117 
> ++
>  SecurityPkg/RandomNumberGenerator/RngDxe/AArch64/RngDxe.c | 127 
> +++
>  SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/AesCore.c |   0
>  SecurityPkg/RandomNumberGenerator/RngDxe/{ => Rand}/RdRand.c  |  45 +-
>  SecurityPkg/RandomNumberGenerator/RngDxe/Rand/RngDxe.c| 146 
> +
>  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.c | 170 
> 
>  11 files changed, 483 insertions(+), 176 deletions(-)
>
> diff --git a/SecurityPkg/SecurityPkg.dec b/SecurityPkg/SecurityPkg.dec
> index dfbbb0365a2b..4001650fa28e 100644
> --- a/SecurityPkg/SecurityPkg.dec
> +++ b/SecurityPkg/SecurityPkg.dec
> @@ -297,6 +297,8 @@ [PcdsFixedAtBuild, PcdsPatchableInModule]
>
> gEfiSecurityPkgTokenSpaceGuid.PcdStatusCodeFvVerificationPass|0x0303100A|UINT32|0x00010030
>
> gEfiSecurityPkgTokenSpaceGuid.PcdStatusCodeFvVerificationFail|0x0303100B|UINT32|0x00010031
>
> +  
> gEfiSecurityPkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x00010032
> +
>  [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
>## Image verification policy for OptionRom. Only following values are 
> valid:
>#  NOTE: Do NOT use 0x5 and 0x2 since it violates the UEFI specification 
> and has been removed.
> diff --git a/SecurityPkg/SecurityPkg.dsc b/SecurityPkg/SecurityPkg.dsc
> index 12ccd1634941..bd4b810bce61 100644
> --- a/SecurityPkg/SecurityPkg.dsc
> +++ b/SecurityPkg/SecurityPkg.dsc
> @@ -259,6 +259,12 @@ [Components]
>  [Components.IA32, Components.X64, Components.ARM, Components.AARCH64]
>SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
>
> +[Components.IA32, Components.X64, Components.AARCH64]
> +  #
> +  # Random Number Generator
> +  #
> +  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
> +
>  [Components.IA32, Components.X64]
>
> SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
>
> @@ -334,11 +340,6 @@ [Components.IA32, Components.X64]
>
> SecurityPkg/Library/SmmTcg2PhysicalPresenceLib/SmmTcg2PhysicalPresenceLib.inf
>
> SecurityPkg/Library/SmmTcg2PhysicalPresenceLib/StandaloneMmTcg2PhysicalPresenceLib.inf
>
> -  #
> -  # Random Number Generator
> -  #
> -  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
> -
>#
># Opal Password solution
>#
> diff --git a/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf 
> b/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
> index 99d6f6b35fc2..f3300971993f 100644
> --- a/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
> +++ b/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
> @@ -26,15 +26,22 @@ [Defines]
>  #
>  # The following information is for reference only and not required by the 
> build tools.
>  #
> -#  VALID_ARCHITECTURES   = IA32 X64
> +#  VALID_ARCHITECTURES   = IA32 X64 AARCH64
>  #
>
>  [Sources.common]
>RngDxe.c
> -  RdRand.c
> -  RdRand.h
> -  AesCore.c
> -  AesCore.h
> +  RngDxeInternals.h
> +
> +[Sources.IA32, Sources.X64]
> +  Rand/RngDxe.c
> +  Rand/RdRand.c
> +  Rand/RdRand.h
> +  Rand/AesCore.c
> +  Rand/AesCore.h
> +
> +[Sources.AARCH64]
> +  AArch64/RngDxe.c
>
>  [Packages]
>MdePkg/MdePkg.dec
> @@ -50,12 +57,19 @@ [LibraryClasses]
>RngLib
>
>  [Guids]
> +  gEfiRngAlgorithmSp80090Hash256Guid  ## SOMETIMES_PRODUCES## GUID   
>  # Unique ID of the algorithm for RNG
> +  gEfiRngAlgorithmSp80090Hmac256Guid  ## SOMETIMES_PRODUCES## GUID   
>  # Unique ID of the algorithm for RNG
>gEfiRngAlgorithmSp80090Ctr256Guid   ## SOMETIMES_PRODUCES## GUID   
>  # Unique ID of the algorithm for RNG
> +  gEfiRngAlgorithmX9313DesGuid## SOMETIMES_PRODUCES## GUID   
>  # Unique ID of the algorithm for RNG
> +  gEfiRngAlgorithmX931AesGuid ## SOMETIMES_PRODUCES## GUID   
>  # Unique ID of the algorithm for RNG
>gEfiRngAlgorithmRaw ## SOMETIMES_PRODUCES## GUID   
>  # Unique ID of the algorithm for RNG
>
>  [Protocols]
>gEfiRngProtocolGuid## PRODUCES
>
> 

Re: [edk2-devel] Build fails with VS2012

[Laszlo Ersek]

On 05/11/21 02:14, Rebecca Cran wrote:
> Thanks. The obvious toolchains that are missing from ReadMe.rst are any
> versions of XCODE and CLANG.
> Also, it might be nice to specify _which_ GCC5 versions are supported,
> since that covers gcc 5 through 11 and gcc 5.x currently causes a build
> error. We maybe only care about gcc 7 and newer these days?
> 
> I just tried building with VS2015 and VS2013, and there was a build
> error because it seems the location of rc.exe has changed. After fixing
> that they successfully built OVMF. But it sounds like we possibly only
> want to make sure that VS2017 and VS2019 are kept working now.
> 
> I've cc'd Bret and Sean because I'm wondering if there are plans to add
> more toolchain/OS combinations into the GitHub/Azure solution? For
> example adding macOS with XCODE5? Also, how about post-commit or nightly
> builds that run more extensive tests, possibly generating binaries for
> OVMF that people can try without building it themselves? Or would that
> be something that might be useful for me to implement as a third-party
> solution?
> 

Too many good questions!

Personally, I care for gcc-8, and later.

Thanks
Laszlo



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Re: [edk2-devel] [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms

[Sami Mujawar]

Pushed as 67988fb53dbc..8549b1739183 with minor edits to doxygen comment 
style.


Thanks.

Regards,

Sami Mujawar

On 10/05/2021 09:06 PM, Pranav Madhu wrote:

Changes since V2:
- Introduced CPU container object into DSDT
- Addressed comments from Sami

Changes since V1:
- Rebase the patches on top of latest master branch
- Addressed comments from Pierre

Processor Properties Topology Table (PPTT) describes the topological
structure of processors, and their shared resources such as caches.
This patch series adds PPTT table for Arm's Neoverse Reference Design
platforms.

The first patch in this series adds helper macros for PPTT table, and
the subsequent patches in this series adds PPTT table for Neoverse
Reference Design platforms which is mandatory as per Arm SystemReady SR
specification.

Link to github branch with the patches in this series -
https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rd_pptt

Pranav Madhu (14):
   Platform/Sgi: Helper macros for PPTT Table
   Platform/Sgi: Add CPU container for SGI-575
   Platform/Sgi: ACPI PPTT table for SGI-575 platform
   Platform/Sgi: Add CPU container for RD-N1-Edge
   Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform
   Platform/Sgi: Add DSDT ACPI table for RD-N1-Edge dual-chip platform
   Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip
   Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform
   Platform/Sgi: Add CPU container for RD-V1 platform
   Platform/Sgi: ACPI PPTT Table for RD-V1 platform
   Platform/Sgi: Add CPU container for RD-V1 quad-chip platform
   Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform
   Platform/Sgi: Add CPU container for RD-N2 platform
   Platform/Sgi: ACPI PPTT table for RD-N2 platform

  .../SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf  |   3 +-
  .../SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf  |   3 +-
  .../AcpiTables/RdN1EdgeX2AcpiTables.inf   |   3 +-
  .../ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf  |   3 +-
  .../ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf  |   3 +-
  .../SgiPkg/AcpiTables/RdV1McAcpiTables.inf|   1 +
  .../SgiPkg/AcpiTables/Sgi575AcpiTables.inf|   3 +-
  Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h   | 170 
  .../ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc  | 252 ++
  .../ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl   |  88 +++---
  .../ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc  | 186 +
  .../ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 136 ++
  .../SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc| 207 ++
  Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl  | 176 
  Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 175 
  Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl  | 176 
  Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 175 
  .../ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 177 
  .../ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc| 184 +
  .../ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl |  99 +++
  .../ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc| 172 
  21 files changed, 2156 insertions(+), 236 deletions(-)
  create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
  create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
  create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
  create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
  create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
  create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
  create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
  create mode 100644 Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc





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Re: [edk2-devel] [PATCH 13/13] OvmfPkg/BaseMemEncryptSevLib: remove Flush parameter

[Laszlo Ersek]

I don't fully understand the updates in this patch:

On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
> 
> The Flush parameter is used to provide a hint whether the specified range
> is Mmio address. Now that we have a dedicated helper to clear the
> memory encryption mask for the Mmio address range, its safe to remove the
> Flush parameter from MemEncryptSev{Set,Clear}PageEncMask().

This looks good; it matches my request (1) from:

https://listman.redhat.com/archives/edk2-devel-archive/2021-May/msg00109.html

> 
> Cc: James Bottomley 
> Cc: Min Xu 
> Cc: Jiewen Yao 
> Cc: Tom Lendacky 
> Cc: Jordan Justen 
> Cc: Ard Biesheuvel 
> Cc: Laszlo Ersek 
> Cc: Erdem Aktas 
> Signed-off-by: Brijesh Singh 
> ---
>  OvmfPkg/Include/Library/MemEncryptSevLib.h| 10 ++
>  .../BaseMemEncryptSevLib/X64/VirtualMemory.h  | 10 ++
>  OvmfPkg/AmdSevDxe/AmdSevDxe.c |  3 +-
>  OvmfPkg/IoMmuDxe/AmdSevIoMmu.c|  6 ++--
>  .../Ia32/MemEncryptSevLib.c   | 10 ++
>  .../X64/MemEncryptSevLib.c| 16 +++---
>  .../X64/PeiDxeVirtualMemory.c | 32 +++
>  .../X64/SecVirtualMemory.c|  8 ++---
>  .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.c |  3 +-
>  OvmfPkg/PlatformPei/AmdSev.c  |  3 +-
>  10 files changed, 35 insertions(+), 66 deletions(-)
> 
> diff --git a/OvmfPkg/Include/Library/MemEncryptSevLib.h 
> b/OvmfPkg/Include/Library/MemEncryptSevLib.h
> index b91490d5d44d..76d06c206c8b 100644
> --- a/OvmfPkg/Include/Library/MemEncryptSevLib.h
> +++ b/OvmfPkg/Include/Library/MemEncryptSevLib.h
> @@ -100,8 +100,6 @@ MemEncryptSevIsEnabled (
>address of a memory region.
>@param[in]  NumPagesThe number of pages from start memory
>region.
> -  @param[in]  Flush   Flush the caches before clearing the 
> bit
> -  (mostly TRUE except MMIO addresses)
>  
>@retval RETURN_SUCCESS  The attributes were cleared for the
>memory region.
> @@ -114,8 +112,7 @@ EFIAPI
>  MemEncryptSevClearPageEncMask (
>IN PHYSICAL_ADDRESS Cr3BaseAddress,
>IN PHYSICAL_ADDRESS BaseAddress,
> -  IN UINTNNumPages,
> -  IN BOOLEAN  Flush
> +  IN UINTNNumPages
>);
>  
>  /**
> @@ -128,8 +125,6 @@ MemEncryptSevClearPageEncMask (
>address of a memory region.
>@param[in]  NumPagesThe number of pages from start memory
>region.
> -  @param[in]  Flush   Flush the caches before setting the bit
> -  (mostly TRUE except MMIO addresses)
>  
>@retval RETURN_SUCCESS  The attributes were set for the memory
>region.
> @@ -142,8 +137,7 @@ EFIAPI
>  MemEncryptSevSetPageEncMask (
>IN PHYSICAL_ADDRESS Cr3BaseAddress,
>IN PHYSICAL_ADDRESS BaseAddress,
> -  IN UINTNNumPages,
> -  IN BOOLEAN  Flush
> +  IN UINTNNumPages
>);
>  
>  
> diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h 
> b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h
> index 8dc39e647b90..21bbbd1c4f9c 100644
> --- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h
> +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h
> @@ -58,8 +58,6 @@ InternalGetMemEncryptionAddressMask (
>@param[in]  PhysicalAddress The physical address that is the start
>address of a memory region.
>@param[in]  Length  The length of memory region
> -  @param[in]  Flush   Flush the caches before applying the
> -  encryption mask
>  
>@retval RETURN_SUCCESS  The attributes were cleared for the
>memory region.
> @@ -72,8 +70,7 @@ EFIAPI
>  InternalMemEncryptSevSetMemoryDecrypted (
>IN  PHYSICAL_ADDRESSCr3BaseAddress,
>IN  PHYSICAL_ADDRESSPhysicalAddress,
> -  IN  UINTN   Length,
> -  IN  BOOLEAN Flush
> +  IN  UINTN   Length
>);
>  
>  /**
> @@ -85,8 +82,6 @@ InternalMemEncryptSevSetMemoryDecrypted (
>@param[in]  PhysicalAddress The physical address that is the start
>address of a memory region.
>@param[in]  Length  The length of memory region
> -  @param[in]  Flush   Flush the caches before applying the
> -  encryption mask
>  
>@retval RETURN_SUCCESS  The 

Re: [edk2-devel] [edk2-platforms][PATCH V3 08/14] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform

[Pranav Madhu]

Hi Sami,

Please find my response:

>
> Hi Pranav,
>
> Please find my response inline marked [SAMI].
>
> Regards,
>
> Sami Mujawar
>
>
> On 10/05/2021 09:06 PM, Pranav Madhu wrote:
> > The RD-E1-Edge platform includes two clusters with eight multi-thread
> > CPUs. Each of the CPUs include 32KB L1 Data cache, 32KB L1 Instruction
> > cache and 256KB L2 cache. Each cluster includes a 2MB L3 cache. The
> > platform also includes a system level cache of 8MB. Add PPTT table for
> > RD-E1-Edge platform with this information.
> >

<...>

> \
> > +  PPTT_PROCESSOR_CLUSTER_THREADED_FLAGS,   /* Flag */
> \
> [SAMI] I see that PPTT_PROCESSOR_CLUSTER_THREADED_FLAGS sets the
> ACPI ID flag to invalid. Is there a reason for doing this?
> Also, it looks like the DSDT for RD-E1-Edge platform does not have the
> clusters definitions. Am I missing something here?
> Can you take a look, please?
> [/SAMI]

ACPI CPU container (ACPI0010) is introduced to support combined idles state for 
CPU core and container. Idle states are not supported for RDE1, and hence 
container is not added.

> > +  OFFSET_OF
> (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \

<...>

Regards,
Pranav
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Re: [edk2-devel] [PATCH 12/13] OvmfPkg/TpmMmioSevDecryptPei: use MemEncryptSevClearMmioPageEncMask()

[Laszlo Ersek]

On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
> 
> Use the MemEncryptSevClearMmioPageEncMask() to clear memory encryption mask
> for the Mmio address range.
> 
> Cc: James Bottomley 
> Cc: Min Xu 
> Cc: Jiewen Yao 
> Cc: Tom Lendacky 
> Cc: Jordan Justen 
> Cc: Ard Biesheuvel 
> Cc: Laszlo Ersek 
> Cc: Erdem Aktas 
> Signed-off-by: Brijesh Singh 
> ---
>  OvmfPkg/Tcg/TpmMmioSevDecryptPei/TpmMmioSevDecryptPeim.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/OvmfPkg/Tcg/TpmMmioSevDecryptPei/TpmMmioSevDecryptPeim.c 
> b/OvmfPkg/Tcg/TpmMmioSevDecryptPei/TpmMmioSevDecryptPeim.c
> index df2ad623308d..570c8467a673 100644
> --- a/OvmfPkg/Tcg/TpmMmioSevDecryptPei/TpmMmioSevDecryptPeim.c
> +++ b/OvmfPkg/Tcg/TpmMmioSevDecryptPei/TpmMmioSevDecryptPeim.c
> @@ -62,11 +62,10 @@ TpmMmioSevDecryptPeimEntryPoint (
>"%a: mapping TPM MMIO address range unencrypted\n",
>__FUNCTION__));
>  
> -DecryptStatus = MemEncryptSevClearPageEncMask (
> +DecryptStatus = MemEncryptSevClearMmioPageEncMask (
>0,
>FixedPcdGet64 (PcdTpmBaseAddress),
> -  EFI_SIZE_TO_PAGES ((UINTN) 0x5000),
> -  FALSE
> +  EFI_SIZE_TO_PAGES ((UINTN) 0x5000)
>);
>  
>  if (RETURN_ERROR (DecryptStatus)) {
> 

Reviewed-by: Laszlo Ersek 



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Re: [edk2-devel] [PATCH 11/13] OvmfPkg/QemuFlashFvbServicesRuntimeDxe: use Mmio helper to clear enc mask

[Laszlo Ersek]

On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
> 
> Use the MemEncryptSevClearMmioPageEncMask() to clear memory encryption mask
> for the Mmio address range.
> 
> Cc: James Bottomley 
> Cc: Min Xu 
> Cc: Jiewen Yao 
> Cc: Tom Lendacky 
> Cc: Jordan Justen 
> Cc: Ard Biesheuvel 
> Cc: Laszlo Ersek 
> Cc: Erdem Aktas 
> Signed-off-by: Brijesh Singh 
> ---
>  OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FwBlockServiceDxe.c | 5 ++---
>  OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashSmm.c  | 5 ++---
>  2 files changed, 4 insertions(+), 6 deletions(-)
> 
> diff --git a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FwBlockServiceDxe.c 
> b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FwBlockServiceDxe.c
> index 1f285e008372..ab40087a8408 100644
> --- a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FwBlockServiceDxe.c
> +++ b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FwBlockServiceDxe.c
> @@ -205,11 +205,10 @@ MarkIoMemoryRangeForRuntimeAccess (
>// memory range.
>//
>if (MemEncryptSevIsEnabled ()) {
> -Status = MemEncryptSevClearPageEncMask (
> +Status = MemEncryptSevClearMmioPageEncMask (
> 0,
> BaseAddress,
> -   EFI_SIZE_TO_PAGES (Length),
> -   FALSE
> +   EFI_SIZE_TO_PAGES (Length)
> );
>  ASSERT_EFI_ERROR (Status);
>}
> diff --git a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashSmm.c 
> b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashSmm.c
> index 7eb80bfeffae..ea75b489c7fd 100644
> --- a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashSmm.c
> +++ b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashSmm.c
> @@ -38,11 +38,10 @@ QemuFlashBeforeProbe (
>// C-bit on flash ranges from SMM page table.
>//
>  
> -  Status = MemEncryptSevClearPageEncMask (
> +  Status = MemEncryptSevClearMmioPageEncMask (
>   0,
>   BaseAddress,
> - EFI_SIZE_TO_PAGES (FdBlockSize * FdBlockCount),
> - FALSE
> + EFI_SIZE_TO_PAGES (FdBlockSize * FdBlockCount)
>   );
>ASSERT_EFI_ERROR (Status);
>  }
> 

Reviewed-by: Laszlo Ersek 



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Re: [edk2-devel] [PATCH 10/13] OvmfPkg/AmdSevDxe: use MemEncryptSevClearMmioPageEncMask() to clear EncMask

[Laszlo Ersek]

On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
> 
> Use the MemEncryptSevClearMmioPageEncMask() to clear memory encryption mask
> for the Mmio and NonExistent address range.
> 
> Cc: James Bottomley 
> Cc: Min Xu 
> Cc: Jiewen Yao 
> Cc: Tom Lendacky 
> Cc: Jordan Justen 
> Cc: Ard Biesheuvel 
> Cc: Laszlo Ersek 
> Cc: Erdem Aktas 
> Signed-off-by: Brijesh Singh 
> ---
>  OvmfPkg/AmdSevDxe/AmdSevDxe.c | 10 --
>  1 file changed, 4 insertions(+), 6 deletions(-)
> 
> diff --git a/OvmfPkg/AmdSevDxe/AmdSevDxe.c b/OvmfPkg/AmdSevDxe/AmdSevDxe.c
> index 689bfb376d03..80831b81facf 100644
> --- a/OvmfPkg/AmdSevDxe/AmdSevDxe.c
> +++ b/OvmfPkg/AmdSevDxe/AmdSevDxe.c
> @@ -53,11 +53,10 @@ AmdSevDxeEntryPoint (
>Desc = [Index];
>if (Desc->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo ||
>Desc->GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
> -Status = MemEncryptSevClearPageEncMask (
> +Status = MemEncryptSevClearMmioPageEncMask (
> 0,
> Desc->BaseAddress,
> -   EFI_SIZE_TO_PAGES (Desc->Length),
> -   FALSE
> +   EFI_SIZE_TO_PAGES (Desc->Length)
> );
>  ASSERT_EFI_ERROR (Status);
>}
> @@ -73,11 +72,10 @@ AmdSevDxeEntryPoint (
>// the range.
>//
>if (PcdGet16 (PcdOvmfHostBridgePciDevId) == INTEL_Q35_MCH_DEVICE_ID) {
> -Status = MemEncryptSevClearPageEncMask (
> +Status = MemEncryptSevClearMmioPageEncMask (
> 0,
> FixedPcdGet64 (PcdPciExpressBaseAddress),
> -   EFI_SIZE_TO_PAGES (SIZE_256MB),
> -   FALSE
> +   EFI_SIZE_TO_PAGES (SIZE_256MB)
> );
>  
>  ASSERT_EFI_ERROR (Status);
> 

Reviewed-by: Laszlo Ersek 



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Re: [edk2-devel] [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms

[Pranav Madhu]

Hi Sami,

Please find my comments inline:

> 
> Hi Pranav,
> 
> Comparing with the V2 series, I see that updates to the following files or
> corresponding patches are missing in this series.
> 
> -  RdV1Mc/Pptt.aslc
> -  RdN2/Pptt.aslc
> 
> Is this intentional?

No
RdN2: https://edk2.groups.io/g/devel/message/74924
RdV1Mc: https://edk2.groups.io/g/devel/message/74922

> 
> Regards,
> 
> Sami Mujawar
> 
> On 10/05/2021 09:06 PM, Pranav Madhu wrote:
> > Changes since V2:
> > - Introduced CPU container object into DSDT
> > - Addressed comments from Sami

<...>

Regards,
Pranav.


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Re: [edk2-devel] [PATCH 09/13] OvmfPkg/BaseMemEncryptSevLib: introduce MemEncryptSevClearMmioPageEncMask()

[Laszlo Ersek]

On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
> 
> The MemEncryptSevClearMmioPageEncMask() helper can be used for clearing
> the memory encryption mask for the Mmio region.
> 
> The MemEncryptSevClearMmioPageEncMask() is a simplifies version of

(1) s/simplifies/simplified/

Reviewed-by: Laszlo Ersek 

Thanks
Laszlo

> MemEncryptSevClearPageEncMask() -- it does not flush the caches after
> clearing the page encryption mask.
> 
> Cc: James Bottomley 
> Cc: Min Xu 
> Cc: Jiewen Yao 
> Cc: Tom Lendacky 
> Cc: Jordan Justen 
> Cc: Ard Biesheuvel 
> Cc: Laszlo Ersek 
> Cc: Erdem Aktas 
> Signed-off-by: Brijesh Singh 
> ---
>  OvmfPkg/Include/Library/MemEncryptSevLib.h| 25 ++
>  .../BaseMemEncryptSevLib/X64/VirtualMemory.h  | 23 +
>  .../Ia32/MemEncryptSevLib.c   | 31 +
>  .../X64/MemEncryptSevLib.c| 33 +++
>  .../X64/PeiDxeVirtualMemory.c | 33 +++
>  5 files changed, 145 insertions(+)
> 
> diff --git a/OvmfPkg/Include/Library/MemEncryptSevLib.h 
> b/OvmfPkg/Include/Library/MemEncryptSevLib.h
> index 99f15a7d1271..b91490d5d44d 100644
> --- a/OvmfPkg/Include/Library/MemEncryptSevLib.h
> +++ b/OvmfPkg/Include/Library/MemEncryptSevLib.h
> @@ -203,4 +203,29 @@ MemEncryptSevGetAddressRangeState (
>IN UINTNLength
>);
>  
> +/**
> +  This function clears memory encryption bit for the MMIO region specified by
> +  BaseAddress and NumPages.
> +
> +  @param[in]  Cr3BaseAddress  Cr3 Base Address (if zero then use
> +  current CR3)
> +  @param[in]  BaseAddress The physical address that is the start
> +  address of a MMIO region.
> +  @param[in]  NumPagesThe number of pages from start memory
> +  region.
> +
> +  @retval RETURN_SUCCESS  The attributes were cleared for the
> +  memory region.
> +  @retval RETURN_INVALID_PARAMETERNumber of pages is zero.
> +  @retval RETURN_UNSUPPORTED  Clearing the memory encryption 
> attribute
> +  is not supported
> +**/
> +RETURN_STATUS
> +EFIAPI
> +MemEncryptSevClearMmioPageEncMask (
> +  IN PHYSICAL_ADDRESS Cr3BaseAddress,
> +  IN PHYSICAL_ADDRESS BaseAddress,
> +  IN UINTNNumPages
> +  );
> +
>  #endif // _MEM_ENCRYPT_SEV_LIB_H_
> diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h 
> b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h
> index fe2a0b2826cd..8dc39e647b90 100644
> --- a/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h
> +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/X64/VirtualMemory.h
> @@ -126,4 +126,27 @@ InternalMemEncryptSevGetAddressRangeState (
>IN UINTNLength
>);
>  
> +/**
> +  This function clears memory encryption bit for the MMIO region specified by
> +  PhysicalAddress and Length.
> +
> +  @param[in]  Cr3BaseAddress  Cr3 Base Address (if zero then use
> +  current CR3)
> +  @param[in]  PhysicalAddress The physical address that is the start
> +  address of a MMIO region.
> +  @param[in]  Length  The length of memory region
> +
> +  @retval RETURN_SUCCESS  The attributes were cleared for the
> +  memory region.
> +  @retval RETURN_INVALID_PARAMETERLength is zero.
> +  @retval RETURN_UNSUPPORTED  Clearing the memory encyrption 
> attribute
> +  is not supported
> +**/
> +RETURN_STATUS
> +EFIAPI
> +InternalMemEncryptSevClearMmioPageEncMask (
> +  IN  PHYSICAL_ADDRESSCr3BaseAddress,
> +  IN  PHYSICAL_ADDRESSPhysicalAddress,
> +  IN  UINTN   Length
> +  );
>  #endif
> diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c 
> b/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c
> index 12a5bf495bd7..169d3118e44f 100644
> --- a/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c
> +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/Ia32/MemEncryptSevLib.c
> @@ -111,3 +111,34 @@ MemEncryptSevGetAddressRangeState (
>//
>return MemEncryptSevAddressRangeEncrypted;
>  }
> +
> +/**
> +  This function clears memory encryption bit for the MMIO region specified by
> +  BaseAddress and NumPages.
> +
> +  @param[in]  Cr3BaseAddress  Cr3 Base Address (if zero then use
> +  current CR3)
> +  @param[in]  BaseAddress The physical address that is the start
> +  address of a MMIO region.
> +  @param[in]  NumPagesThe number of pages from start memory
> +  

Re: [edk2-devel] [edk2-platforms][PATCH V3 00/14] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms

[Sami Mujawar]

Hi Pranav,

Comparing with the V2 series, I see that updates to the following files 
or corresponding patches are missing in this series.


-  RdV1Mc/Pptt.aslc
-  RdN2/Pptt.aslc

Is this intentional?

Regards,

Sami Mujawar

On 10/05/2021 09:06 PM, Pranav Madhu wrote:

Changes since V2:
- Introduced CPU container object into DSDT
- Addressed comments from Sami

Changes since V1:
- Rebase the patches on top of latest master branch
- Addressed comments from Pierre

Processor Properties Topology Table (PPTT) describes the topological
structure of processors, and their shared resources such as caches.
This patch series adds PPTT table for Arm's Neoverse Reference Design
platforms.

The first patch in this series adds helper macros for PPTT table, and
the subsequent patches in this series adds PPTT table for Neoverse
Reference Design platforms which is mandatory as per Arm SystemReady SR
specification.

Link to github branch with the patches in this series -
https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rd_pptt

Pranav Madhu (14):
   Platform/Sgi: Helper macros for PPTT Table
   Platform/Sgi: Add CPU container for SGI-575
   Platform/Sgi: ACPI PPTT table for SGI-575 platform
   Platform/Sgi: Add CPU container for RD-N1-Edge
   Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform
   Platform/Sgi: Add DSDT ACPI table for RD-N1-Edge dual-chip platform
   Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip
   Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform
   Platform/Sgi: Add CPU container for RD-V1 platform
   Platform/Sgi: ACPI PPTT Table for RD-V1 platform
   Platform/Sgi: Add CPU container for RD-V1 quad-chip platform
   Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform
   Platform/Sgi: Add CPU container for RD-N2 platform
   Platform/Sgi: ACPI PPTT table for RD-N2 platform

  .../SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf  |   3 +-
  .../SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf  |   3 +-
  .../AcpiTables/RdN1EdgeX2AcpiTables.inf   |   3 +-
  .../ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf  |   3 +-
  .../ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf  |   3 +-
  .../SgiPkg/AcpiTables/RdV1McAcpiTables.inf|   1 +
  .../SgiPkg/AcpiTables/Sgi575AcpiTables.inf|   3 +-
  Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h   | 170 
  .../ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc  | 252 ++
  .../ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl   |  88 +++---
  .../ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc  | 186 +
  .../ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 136 ++
  .../SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc| 207 ++
  Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl  | 176 
  Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 175 
  Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl  | 176 
  Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 175 
  .../ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 177 
  .../ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc| 184 +
  .../ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl |  99 +++
  .../ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc| 172 
  21 files changed, 2156 insertions(+), 236 deletions(-)
  create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
  create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
  create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
  create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
  create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
  create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
  create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
  create mode 100644 Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc





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Re: [edk2-devel] [edk2-platforms][PATCH V3 08/14] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform

[Sami Mujawar]

Hi Pranav,

Please find my response inline marked [SAMI].

Regards,

Sami Mujawar


On 10/05/2021 09:06 PM, Pranav Madhu wrote:

The RD-E1-Edge platform includes two clusters with eight multi-thread
CPUs. Each of the CPUs include 32KB L1 Data cache, 32KB L1 Instruction
cache and 256KB L2 cache. Each cluster includes a 2MB L3 cache. The
platform also includes a system level cache of 8MB. Add PPTT table for
RD-E1-Edge platform with this information.

Signed-off-by: Pranav Madhu 
---
  Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf |   3 +-
  Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 252 

  2 files changed, 254 insertions(+), 1 deletion(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf 
b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
index 2dd2275665a2..04ef2bfcaa26 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
@@ -1,7 +1,7 @@
  ## @file
  #  ACPI table data and ASL sources required to boot the platform.
  #
-#  Copyright (c) 2018-2020, ARM Ltd. All rights reserved.
+#  Copyright (c) 2018-2021, ARM Ltd. All rights reserved.
  #
  #  SPDX-License-Identifier: BSD-2-Clause-Patent
  #
@@ -23,6 +23,7 @@
Mcfg.aslc
RdE1Edge/Dsdt.asl
RdE1Edge/Madt.aslc
+  RdE1Edge/Pptt.aslc
Spcr.aslc
Ssdt.asl

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc 
b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
new file mode 100644
index ..91baab73d108
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
@@ -0,0 +1,252 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-E1-Edge platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-E1-Edge platform in the form as defined by ACPI PPTT table. The RD-E1-Edge
+* platform includes two clusters with eight dual-thread CPUS. Each of the CPUs
+* include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cache.
+* Each cluster includes a 2MB L3 cache. The platform also includes a system
+* level cache of 8MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+*   - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include 
+#include 
+#include 
+#include 
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define THREAD_PER_CORE_E1   2
+
+/*!
+   \brief Define helper macro for populating processor thread information.
+   \param PackageId Package instance number.
+   \param ClusterId Cluster instance number.
+   \param CpuId CPU instance number.
+   \param ThreadId  CPU thread number.
+*/
+#define PPTT_THREAD_INIT(PackageId, ClusterId, CpuId, ThreadId)
\
+  {
\
+EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (   
\
+  sizeof (RDE1EDGE_PPTT_THREAD),/* Length */   
\
+  PPTT_PROCESSOR_THREAD_FLAGS,  /* Flag */ 
\
+  OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, 
\
+Package.Cluster[ClusterId].Core[CpuId]),  /* Parent */ 
\
+  ((PackageId << 5) | (ClusterId << 4) | (CpuId << 1) | ThreadId), 
\
+/* ACPI Id */  
\
+  0 /* Num of private resource */  
\
+)  
\
+  }
+
+/*!
+   \brief Define helper macro for populating processor core information.
+   \param PackageId Package instance number.
+   \param ClusterId Cluster instance number.
+   \param CpuId CPU instance number.
+*/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId)
\
+  {
\
+/* Parameters for CPU Core */  
\
+EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (   
\
+  OFFSET_OF (RDE1EDGE_PPTT_CORE, DCache),   /* Length */   
\
+  PPTT_PROCESSOR_CORE_THREADED_FLAGS,   /* Flag */ 
\
+  OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, 
\
+Package.Cluster[ClusterId]),/* Parent */   
\
+  0,/* ACPI Id */  
\
+  2 /* Num of private resource */  
\
+), 
\
+   
\
+/* Offsets of the private resources */ 
\
+{  

Re: [edk2-devel] [PATCH 08/13] MdePkg/BaseLib: add support for RMPADJUST instruction

[Laszlo Ersek]

On 05/07/21 22:38, Brijesh Singh wrote:
> From: Tom Lendacky 
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
> 
> The RMPADJUST instruction will be used by the SEV-SNP guest to modify the
> RMP permissions for a guest page. See AMD APM volume 3 for further
> details.
> 
> Cc: James Bottomley 
> Cc: Min Xu 
> Cc: Jiewen Yao 
> Cc: Tom Lendacky 
> Cc: Jordan Justen 
> Cc: Ard Biesheuvel 
> Cc: Laszlo Ersek 
> Cc: Erdem Aktas 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Signed-off-by: Tom Lendacky 
> Signed-off-by: Brijesh Singh 
> ---
>  MdePkg/Library/BaseLib/BaseLib.inf|  1 +
>  MdePkg/Include/Library/BaseLib.h  | 36 +++-
>  MdePkg/Include/X64/Nasm.inc   |  8 +
>  MdePkg/Library/BaseLib/X64/RmpAdjust.nasm | 40 +++
>  4 files changed, 84 insertions(+), 1 deletion(-)
>  create mode 100644 MdePkg/Library/BaseLib/X64/RmpAdjust.nasm
> 
> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
> b/MdePkg/Library/BaseLib/BaseLib.inf
> index 89a52f72c08a..6ccb8997b7e8 100644
> --- a/MdePkg/Library/BaseLib/BaseLib.inf
> +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> @@ -319,6 +319,7 @@ [Sources.X64]
>X64/DisablePaging64.nasm
>X64/Pvalidate.nasm
>X64/RdRand.nasm
> +  X64/RmpAdjust.nasm
>X64/XGetBv.nasm
>X64/XSetBv.nasm
>X64/VmgExit.nasm
> diff --git a/MdePkg/Include/Library/BaseLib.h 
> b/MdePkg/Include/Library/BaseLib.h
> index f177034af6a1..04e58f995b9a 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -4857,9 +4857,43 @@ AsmPvalidate (
>IN   BOOLEAN Validate,
>IN   PHYSICAL_ADDRESSAddress
>);
> +
> +//
> +// RDX settings for RMPADJUST
> +//
> +#define RMPADJUST_VMPL_MAX   3
> +#define RMPADJUST_VMPL_MASK  0xFF
> +#define RMPADJUST_VMPL_SHIFT 0
> +#define RMPADJUST_PERMISSION_MASK_MASK   0xFF
> +#define RMPADJUST_PERMISSION_MASK_SHIFT  8
> +#define RMPADJUST_VMSA_PAGE_BIT  BIT16
> +
> +/**
> +  Adjusts the permissions of an SEV-SNP guest page.
> +
> +  Executes a RMPADJUST instruction with the register state specified by Rax,
> +  Rcx and Rdx. Returns Eax. This function is only available x64.

(1) trivial typo: IMO it should be "on X64" (preposition missing, and
X64 should be upper case).

> +
> +  The instruction is available only when CPUID Fn8000_001F_EAX[SNP]=1.
> +
> +  @param[in]  Rax   The value to load into RAX before executing the RMPADJUST
> +instruction.
> +  @param[in]  Rcx   The value to load into RCX before executing the RMPADJUST
> +instruction.
> +  @param[in]  Rdx   The value to load into RDX before executing the RMPADJUST
> +instruction.
> +
> +  @return Eax
> +**/
> +UINTN

(2) Not a "hard requirement", just something I thought I'd raise: both
the spec, and the leading comment (twice), say that the return code is
in EAX (not RAX). Would it make sense to use UINT32 for the return type
of the function?

(3) Since we are talking return codes... For PVALIDATE, the previous
patch introduces macros for the return codes. I haven't looked at
RMPADJUST before, but now it seems like SEV-ES-related machine
instructions come with a "global" status code table: 0 for SUCCESS, 1
for FAIL_INPUT, 6 for FAIL_SIZEMISMATCH (<-- all of these are shared by
PVALIDATE and RMPADJUST), and now FAIL_PERMISSION (2) for RMPADJUST only.

So now I wonder if these macros belong in an AMD-specific header file...
Anyway, I definitely defer to Liming and Mike on this MdePkg content.

> +EFIAPI
> +AsmRmpAdjust (
> +  IN  UINTN Rax,
> +  IN  UINTN Rcx,
> +  IN  UINTN Rdx
> +  );

(4) Given that we really call these R*x, shouldn't we make them
explicitly UINT64? I don't think there's an interpretation for RAX that
is *not* 64-bit.

>  #endif
>  
> -

(5) Indeed, this newline is superfluous, I just didn't want to obsess
about it under patch #7. If you agree it's unneeded, then please drop it
from patch#7.

>  #if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
>  ///
>  /// IA32 and x64 Specific Functions.
> diff --git a/MdePkg/Include/X64/Nasm.inc b/MdePkg/Include/X64/Nasm.inc
> index 528bb3385609..cfb14edc9449 100644
> --- a/MdePkg/Include/X64/Nasm.inc
> +++ b/MdePkg/Include/X64/Nasm.inc
> @@ -41,6 +41,14 @@
>  DB 0xF2, 0x0F, 0x01, 0xFF
>  %endmacro
>  
> +;
> +; Macro for the RMPADJUST instruction, defined in AMD APM volume 3.
> +; NASM feature request URL: https://bugzilla.nasm.us/show_bug.cgi?id=3392754
> +;
> +%macro RMPADJUST   0
> +DB 0xF3, 0x0F, 0x01, 0xFE
> +%endmacro
> +
>  ; NASM provides built-in macros STRUC and ENDSTRUC for structure definition.
>  ; For example, to define a structure called mytype containing a longword,
>  ; a word, a byte and a string of bytes, you might code
> diff --git a/MdePkg/Library/BaseLib/X64/RmpAdjust.nasm 
> 

Re: [edk2-devel] [PATCH 07/13] MdePkg/BaseLib: add support for PVALIDATE instruction

[Laszlo Ersek]

On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
> 
> The PVALIDATE instruction validates or rescinds validation of a guest
> page RMP entry. Upon completion, a return code is stored in EAX, rFLAGS
> bits OF, ZF, AF, PF and SF are set based on this return code. If the
> instruction completed succesfully, the rFLAGS bit CF indicates if the
> contents of the RMP entry were changed or not.
> 
> For more information about the instruction see AMD APM volume 3.
> 
> Cc: James Bottomley 
> Cc: Min Xu 
> Cc: Jiewen Yao 
> Cc: Tom Lendacky 
> Cc: Jordan Justen 
> Cc: Ard Biesheuvel 
> Cc: Laszlo Ersek 
> Cc: Erdem Aktas 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Signed-off-by: Brijesh Singh 
> ---
>  MdePkg/Library/BaseLib/BaseLib.inf|  1 +
>  MdePkg/Include/Library/BaseLib.h  | 46 +++
>  MdePkg/Include/X64/Nasm.inc   |  8 
>  MdePkg/Library/BaseLib/X64/Pvalidate.nasm | 42 +
>  4 files changed, 97 insertions(+)
>  create mode 100644 MdePkg/Library/BaseLib/X64/Pvalidate.nasm
> 
> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
> b/MdePkg/Library/BaseLib/BaseLib.inf
> index b76f3af380ea..89a52f72c08a 100644
> --- a/MdePkg/Library/BaseLib/BaseLib.inf
> +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> @@ -317,6 +317,7 @@ [Sources.X64]
>X64/GccInlinePriv.c | GCC
>X64/EnableDisableInterrupts.nasm
>X64/DisablePaging64.nasm
> +  X64/Pvalidate.nasm
>X64/RdRand.nasm
>X64/XGetBv.nasm
>X64/XSetBv.nasm
> diff --git a/MdePkg/Include/Library/BaseLib.h 
> b/MdePkg/Include/Library/BaseLib.h
> index 7253997a6f8c..f177034af6a1 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -4813,6 +4813,52 @@ SpeculationBarrier (
>VOID
>);
>  
> +#if defined (MDE_CPU_X64)
> +//
> +// The page size for the PVALIDATE instruction
> +//
> +typedef enum {
> +  PvalidatePageSize4K = 0,
> +  PvalidatePageSize2MB,
> +} PVALIDATE_PAGE_SIZE;
> +
> +//
> +// PVALIDATE Return Code.
> +//
> +#define PVALIDATE_RET_SUCCESS 0
> +#define PVALIDATE_RET_FAIL_INPUT  1
> +#define PVALIDATE_RET_SIZE_MISMATCH   6
> +
> +//
> +// The PVALIDATE instruction did not made any changes to the RMP entry.

(1) Typo: should be "did not make".

> +//
> +#define PVALIDATE_RET_NO_RMPUPDATE255
> +
> +/**
> + Execute a PVALIDATE instruction to validate or rescinds validation of a 
> guest

(2) should be "to validate or to rescind validation" (infinitive form).

> + page's RMP entry.
> +
> + The instruction is available only when CPUID Fn8000_001F_EAX[SNP]=1.
> +
> + The function is available on X64.
> +
> + @param[in]PageSize The page size to use.
> + @param[in]Validate Validate or rescinds.

(3) If you use the imperative for "validate", then "rescinds"
(indicative) reads strangely.

> + @param[in]Address  The guest virtual address to validate.
> +
> + @retval   The return value from the PVALIDATE instruction, and
> +   PVALIDATE_RET_NO_RMPUPDATE when there was no change in
> +   the RMP entry.

(4) @retval is only usable with actual return values (constants). If you
provide a natural language explanation, then @return is the proper
doxygen directive.

You can combine these BTW, for example:

  @retval PVALIDATE_RET_SUCCESS   The PVALIDATE instruction
  succeeded, and updated the RMP
  entry.
  @retval PVALIDATE_RET_NO_RMPUPDATE  The PVALIDATE instruction
  succeeded, but did not update the
  RMP entry.
  @return Failure codes from the PVALIDATE
  instruction.

> +**/
> +UINTN
> +EFIAPI
> +AsmPvalidate (
> +  IN   PVALIDATE_PAGE_SIZE PageSize,
> +  IN   BOOLEAN Validate,
> +  IN   PHYSICAL_ADDRESSAddress
> +  );
> +#endif
> +
>  
>  #if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
>  ///
> diff --git a/MdePkg/Include/X64/Nasm.inc b/MdePkg/Include/X64/Nasm.inc
> index 527f71e9eb4d..528bb3385609 100644
> --- a/MdePkg/Include/X64/Nasm.inc
> +++ b/MdePkg/Include/X64/Nasm.inc
> @@ -33,6 +33,14 @@
>  DB 0xF3, 0x48, 0x0F, 0xAE, 0xE8
>  %endmacro
>  
> +;
> +; Macro for the PVALIDATE instruction, defined in AMD APM volume 3.
> +; NASM feature request URL: https://bugzilla.nasm.us/show_bug.cgi?id=3392753
> +;
> +%macro PVALIDATE   0
> +DB 0xF2, 0x0F, 0x01, 0xFF
> +%endmacro
> +
>  ; NASM provides built-in macros STRUC and ENDSTRUC for structure definition.
>  ; For example, to define a structure called mytype containing a longword,
>  ; a word, a byte and a string of bytes, you might code

Thanks for filing the NASM BZ!

> diff --git a/MdePkg/Library/BaseLib/X64/Pvalidate.nasm 
> b/MdePkg/Library/BaseLib/X64/Pvalidate.nasm
> new file mode 100644
> index 

Re: [edk2-devel] [PATCH v2] BaseTools: Add support for version 3 of FMP Image Header structure

[Sughosh Ganu]

hi,
Can this patch be merged. Thanks.

-sughosh

On Mon, 26 Apr 2021 at 21:27, Kinney, Michael D 
wrote:

> Reviewed-by: Michael D Kinney 
>
> Mike
>
> > -Original Message-
> > From: devel@edk2.groups.io  On Behalf Of Sughosh
> Ganu
> > Sent: Friday, April 23, 2021 4:29 AM
> > To: devel@edk2.groups.io
> > Cc: Michal Simek ; Sughosh Ganu <
> sughosh.g...@linaro.org>
> > Subject: [edk2-devel] [PATCH v2] BaseTools: Add support for version 3 of
> FMP Image Header structure
> >
> > Add support for the ImageCapsuleSupport field, introduced in version 3
> > of the EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER structure. This
> > structure member is used to indicate if the corresponding payload has
> > support for authentication and dependency.
> >
> > Signed-off-by: Sughosh Ganu 
> > ---
> >
> > Changes since v1:
> > - Reword the patch header to get rid of the PatchCheck warning
> > - Make passing of ImageCapsuleSupport parameter to the AddPayload
> >   function as an optional parameter to maintain backward compatibility
> > - Declare the values of CAPSULE_SUPPORT_DEPENDENCY and
> >   CAPSULE_SUPPORT_AUTHENTICATION in the FmpCapsuleHeaderClass and use
> >   those in the GenerateCapsule script
> >
> >  .../Source/Python/Capsule/GenerateCapsule.py  |  5 +++-
> >  .../Common/Uefi/Capsule/FmpCapsuleHeader.py   | 28 +--
> >  2 files changed, 24 insertions(+), 9 deletions(-)
> >
> > diff --git a/BaseTools/Source/Python/Capsule/GenerateCapsule.py
> b/BaseTools/Source/Python/Capsule/GenerateCapsule.py
> > index a8de988253..b8039db878 100644
> > --- a/BaseTools/Source/Python/Capsule/GenerateCapsule.py
> > +++ b/BaseTools/Source/Python/Capsule/GenerateCapsule.py
> > @@ -561,6 +561,7 @@ if __name__ == '__main__':
> >  print ('GenerateCapsule: error:' + str(Msg))
> >  sys.exit (1)
> >  for SinglePayloadDescriptor in PayloadDescriptorList:
> > +ImageCapsuleSupport = 0x
> >  Result = SinglePayloadDescriptor.Payload
> >  try:
> >  FmpPayloadHeader.FwVersion  =
> SinglePayloadDescriptor.FwVersion
> > @@ -575,6 +576,7 @@ if __name__ == '__main__':
> >  if SinglePayloadDescriptor.UseDependency:
> >  CapsuleDependency.Payload = Result
> >  CapsuleDependency.DepexExp =
> SinglePayloadDescriptor.DepexExp
> > +ImageCapsuleSupport|=
> FmpCapsuleHeader.CAPSULE_SUPPORT_DEPENDENCY
> >  Result = CapsuleDependency.Encode ()
> >  if args.Verbose:
> >  CapsuleDependency.DumpInfo ()
> > @@ -607,13 +609,14 @@ if __name__ == '__main__':
> >  FmpAuthHeader.MonotonicCount =
> SinglePayloadDescriptor.MonotonicCount
> >  FmpAuthHeader.CertData   = CertData
> >  FmpAuthHeader.Payload= Result
> > +ImageCapsuleSupport  |=
> FmpCapsuleHeader.CAPSULE_SUPPORT_AUTHENTICATION
> >  Result = FmpAuthHeader.Encode ()
> >  if args.Verbose:
> >  FmpAuthHeader.DumpInfo ()
> >  except:
> >  print ('GenerateCapsule: error: can not encode FMP
> Auth Header')
> >  sys.exit (1)
> > -FmpCapsuleHeader.AddPayload (SinglePayloadDescriptor.Guid,
> Result, HardwareInstance =
> > SinglePayloadDescriptor.HardwareInstance, UpdateImageIndex =
> SinglePayloadDescriptor.UpdateImageIndex)
> > +FmpCapsuleHeader.AddPayload (SinglePayloadDescriptor.Guid,
> Result, HardwareInstance =
> > SinglePayloadDescriptor.HardwareInstance, UpdateImageIndex =
> SinglePayloadDescriptor.UpdateImageIndex, CapsuleSupport =
> > ImageCapsuleSupport)
> >  try:
> >  for EmbeddedDriver in EmbeddedDriverDescriptorList:
> >  FmpCapsuleHeader.AddEmbeddedDriver(EmbeddedDriver)
> > diff --git
> a/BaseTools/Source/Python/Common/Uefi/Capsule/FmpCapsuleHeader.py
> > b/BaseTools/Source/Python/Common/Uefi/Capsule/FmpCapsuleHeader.py
> > index 91d24919c4..8abb449c6f 100644
> > --- a/BaseTools/Source/Python/Common/Uefi/Capsule/FmpCapsuleHeader.py
> > +++ b/BaseTools/Source/Python/Common/Uefi/Capsule/FmpCapsuleHeader.py
> > @@ -47,14 +47,19 @@ class FmpCapsuleImageHeaderClass (object):
> >  #   /// therefore can be modified without changing the Auth data.
> >  #   ///
> >  #   UINT64   UpdateHardwareInstance;
> > +#
> > +#   ///
> > +#   /// Bits which indicate authentication and depex information
> for the image that follows this structure
> > +#   ///
> > +#   UINT64   ImageCapsuleSupport
> >  # } EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER;
> >  #
> > -#  #define
> EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER_INIT_VERSION 0x0002
> > +#  #define
> EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER_INIT_VERSION 0x0003
> >
> > -

Re: [edk2-devel] [PATCH 06/13] MdePkg/Register/Amd: define GHCB macros for SNP AP creation

[Laszlo Ersek]

On 05/07/21 22:38, Brijesh Singh wrote:
> From: Tom Lendacky 
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
> 
> Version 2 of GHCB introduces NAE for creating AP when SEV-SNP is
> enabled in the guest VM. See the GHCB spec section for additional
> details.

(1) The actual section reference is missing. I'll fix it up: from where
the spec introduces exit code 0x8000_0013, the sections appear to be
4.1.9 and 4.3.2. Also, Table 5. "List of Supported Non-Automatic Events"
is relevant for the SVM_VMGEXIT_SNP_AP_* macros.

> 
> While at it, define the VMSA state save area that are required for

(2) I think "area" (singular) is correct here, so we should say "is".
I'll update it.

> creating the AP. The save area format is defined in AMD APM volume
> 2 (Table B-4).
> 
> Cc: James Bottomley 
> Cc: Min Xu 
> Cc: Jiewen Yao 
> Cc: Tom Lendacky 
> Cc: Jordan Justen 
> Cc: Ard Biesheuvel 
> Cc: Laszlo Ersek 
> Cc: Erdem Aktas 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Signed-off-by: Tom Lendacky 
> Signed-off-by: Brijesh Singh 
> ---
>  MdePkg/Include/Register/Amd/Ghcb.h | 70 ++
>  1 file changed, 70 insertions(+)
> 
> diff --git a/MdePkg/Include/Register/Amd/Ghcb.h 
> b/MdePkg/Include/Register/Amd/Ghcb.h
> index a15b4b7e2760..956cefbc003c 100644
> --- a/MdePkg/Include/Register/Amd/Ghcb.h
> +++ b/MdePkg/Include/Register/Amd/Ghcb.h
> @@ -55,6 +55,7 @@
>  #define SVM_EXIT_AP_RESET_HOLD  0x8004ULL
>  #define SVM_EXIT_AP_JUMP_TABLE  0x8005ULL
>  #define SVM_EXIT_SNP_PAGE_STATE_CHANGE  0x8010ULL
> +#define SVM_EXIT_SNP_AP_CREATION0x8013ULL
>  #define SVM_EXIT_HYPERVISOR_FEATURES0x8000FFFDULL
>  #define SVM_EXIT_UNSUPPORTED0x8000ULL
>  
> @@ -83,6 +84,12 @@
>  #define IOIO_SEG_ES 0
>  #define IOIO_SEG_DS (BIT11 | BIT10)
>  
> +//
> +// AP Creation Information
> +//
> +#define SVM_VMGEXIT_SNP_AP_CREATE_ON_INIT  0
> +#define SVM_VMGEXIT_SNP_AP_CREATE  1
> +#define SVM_VMGEXIT_SNP_AP_DESTROY 2
>  
>  typedef PACKED struct {
>UINT8  Reserved1[203];
> @@ -195,4 +202,67 @@ typedef struct {
>SNP_PAGE_STATE_ENTRY   Entry[SNP_PAGE_STATE_MAX_ENTRY];
>  } SNP_PAGE_STATE_CHANGE_INFO;
>  
> +//
> +// SEV-ES save area mapping structures used for SEV-SNP AP Creation.
> +// Only the fields required to be set to a non-zero value are defined.
> +//
> +#pragma pack(1)
> +typedef struct {
> +  UINT16  Selector;
> +  UINT16  Attributes;
> +  UINT32  Limit;
> +  UINT64  Base;
> +} SEV_ES_SEGMENT_REGISTER;
> +#pragma pack()

(3) there should be a space character between "pack" and "(" -- two
instances.

> +
> +#define SEV_ES_RESET_CS_ATTRIBUTES(BIT7 | BIT4 | BIT3 | BIT1)
> +#define SEV_ES_RESET_DS_ATTRIBUTES(BIT7 | BIT4 | BIT1)
> +#define SEV_ES_RESET_ES_ATTRIBUTESSEV_ES_RESET_DS_ATTRIBUTES
> +#define SEV_ES_RESET_FS_ATTRIBUTESSEV_ES_RESET_DS_ATTRIBUTES
> +#define SEV_ES_RESET_GS_ATTRIBUTESSEV_ES_RESET_DS_ATTRIBUTES
> +#define SEV_ES_RESET_SS_ATTRIBUTESSEV_ES_RESET_DS_ATTRIBUTES
> +
> +#define SEV_ES_RESET_GDTR_ATTRIBUTES  0
> +#define SEV_ES_RESET_LDTR_ATTRIBUTES  (BIT7 | 2)
> +#define SEV_ES_RESET_IDTR_ATTRIBUTES  0
> +#define SEV_ES_RESET_TR_ATTRIBUTES(BIT7 | 3)

(4) ... I guess I can't go ahead merging this myself, after all (Liming
may of course still merge the MdePkg patches, if he wants to).

My problem here is that the bit positions are cryptic.

I've found the *normal* (not SEV-ES) segment descriptor attributes in
the AMD APM (publication #24593, revision 3.37, date March 2021, volume
2, sections sections 4.7 and 4.8).

However, the bit positions SEV-ES descriptors are surely different. For
the "normal" segment descriptors, we already have the
IA32_SEGMENT_DESCRIPTOR type in edk2, with the nicely broken-out
attribute bits. The bit meanings within
"SEV_ES_SEGMENT_REGISTER.Attributes" remain unclear to me.

Please at least provide a *specific* documentation reference in the
commit message where I can verify (or at least "decode") the attribute bits.

> +
> +#pragma pack(1)
> +typedef struct {
> +  SEV_ES_SEGMENT_REGISTER  Es;
> +  SEV_ES_SEGMENT_REGISTER  Cs;
> +  SEV_ES_SEGMENT_REGISTER  Ss;
> +  SEV_ES_SEGMENT_REGISTER  Ds;
> +  SEV_ES_SEGMENT_REGISTER  Fs;
> +  SEV_ES_SEGMENT_REGISTER  Gs;
> +  SEV_ES_SEGMENT_REGISTER  Gdtr;
> +  SEV_ES_SEGMENT_REGISTER  Ldtr;
> +  SEV_ES_SEGMENT_REGISTER  Idtr;
> +  SEV_ES_SEGMENT_REGISTER  Tr;
> +  UINT8Reserved1[42];

(5) This doesn't seem right. The comment higher up says that "Only the
fields required to be set to a non-zero value are defined", which is
fine. But in Table B-4, between fields "Tr" and "Vmpl", we have 5 qword
fields (PL0_SSP through PL3_SSP, plus U_CET), and a reserved dword
field. That makes for 5*8+4 =  44 bytes, not 42.

Hmmm. If I look at the table differently, I get a different result.
Namely, the first 

[edk2-devel] [edk2-non-osi] [PATCH V1 9/9] PurleySiliconBinPkg/FV: Add DEBUG FvTempMemorySilicon

[Nate DeSimone]

Cc: Chasel Chiu 
Cc: Mike Kinney 
Cc: Isaac Oram 
Cc: Mohamed Abbas 
Cc: Michael Kubacki 
Cc: Zachary Bobroff 
Cc: Harikrishna Doppalapudi 
Signed-off-by: Nate DeSimone 
---
 .../DEBUG/FVTEMPMEMORYSILICON.Fv  | Bin 0 -> 131072 bytes
 .../DEBUG/FVTEMPMEMORYSILICON.Fv.txt  |   4 +
 .../DEBUG/FvTempMemorySilicon.inf | 267 ++
 3 files changed, 271 insertions(+)
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvTempMemorySilicon/DEBUG/FVTEMPMEMORYSILICON.Fv
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvTempMemorySilicon/DEBUG/FVTEMPMEMORYSILICON.Fv.txt
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvTempMemorySilicon/DEBUG/FvTempMemorySilicon.inf

diff --git 
a/Silicon/Intel/PurleySiliconBinPkg/FV/FvTempMemorySilicon/DEBUG/FVTEMPMEMORYSILICON.Fv
 
b/Silicon/Intel/PurleySiliconBinPkg/FV/FvTempMemorySilicon/DEBUG/FVTEMPMEMORYSILICON.Fv
new file mode 100644
index 
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[edk2-devel] [edk2-non-osi] [PATCH V1 8/9] PurleySiliconBinPkg/FV: Add RELEASE FvTempMemorySilicon

[Nate DeSimone]

Cc: Chasel Chiu 
Cc: Mike Kinney 
Cc: Isaac Oram 
Cc: Mohamed Abbas 
Cc: Michael Kubacki 
Cc: Zachary Bobroff 
Cc: Harikrishna Doppalapudi 
Signed-off-by: Nate DeSimone 
---
 .../RELEASE/FVTEMPMEMORYSILICON.Fv| Bin 0 -> 131072 bytes
 .../RELEASE/FVTEMPMEMORYSILICON.Fv.txt|   4 +
 .../RELEASE/FvTempMemorySilicon.inf   | 263 ++
 3 files changed, 267 insertions(+)
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvTempMemorySilicon/RELEASE/FVTEMPMEMORYSILICON.Fv
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvTempMemorySilicon/RELEASE/FVTEMPMEMORYSILICON.Fv.txt
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvTempMemorySilicon/RELEASE/FvTempMemorySilicon.inf

diff --git 
a/Silicon/Intel/PurleySiliconBinPkg/FV/FvTempMemorySilicon/RELEASE/FVTEMPMEMORYSILICON.Fv
 
b/Silicon/Intel/PurleySiliconBinPkg/FV/FvTempMemorySilicon/RELEASE/FVTEMPMEMORYSILICON.Fv
new file mode 100644
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[edk2-devel] [edk2-non-osi] [PATCH V1 5/9] PurleySiliconBinPkg/FV: Add DEBUG FvPostMemorySilicon

[Nate DeSimone]

Cc: Chasel Chiu 
Cc: Mike Kinney 
Cc: Isaac Oram 
Cc: Mohamed Abbas 
Cc: Michael Kubacki 
Cc: Zachary Bobroff 
Cc: Harikrishna Doppalapudi 
Signed-off-by: Nate DeSimone 
---
 .../DEBUG/FVPOSTMEMORYSILICON.Fv  | Bin 0 -> 196608 bytes
 .../DEBUG/FVPOSTMEMORYSILICON.Fv.txt  |   3 +
 .../DEBUG/FvPostMemorySilicon.inf | 279 ++
 3 files changed, 282 insertions(+)
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/DEBUG/FVPOSTMEMORYSILICON.Fv
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/DEBUG/FVPOSTMEMORYSILICON.Fv.txt
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/DEBUG/FvPostMemorySilicon.inf

diff --git 
a/Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/DEBUG/FVPOSTMEMORYSILICON.Fv
 
b/Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/DEBUG/FVPOSTMEMORYSILICON.Fv
new file mode 100644
index 
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[edk2-devel] [edk2-non-osi] [PATCH V1 4/9] PurleySiliconBinPkg/FV: Add RELEASE FvPostMemorySilicon

[Nate DeSimone]

Cc: Chasel Chiu 
Cc: Mike Kinney 
Cc: Isaac Oram 
Cc: Mohamed Abbas 
Cc: Michael Kubacki 
Cc: Zachary Bobroff 
Cc: Harikrishna Doppalapudi 
Signed-off-by: Nate DeSimone 
---
 .../RELEASE/FVPOSTMEMORYSILICON.Fv| Bin 0 -> 196608 bytes
 .../RELEASE/FVPOSTMEMORYSILICON.Fv.txt|   3 +
 .../RELEASE/FvPostMemorySilicon.inf   | 267 ++
 3 files changed, 270 insertions(+)
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/RELEASE/FVPOSTMEMORYSILICON.Fv
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/RELEASE/FVPOSTMEMORYSILICON.Fv.txt
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/RELEASE/FvPostMemorySilicon.inf

diff --git 
a/Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/RELEASE/FVPOSTMEMORYSILICON.Fv
 
b/Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/RELEASE/FVPOSTMEMORYSILICON.Fv
new file mode 100644
index 
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GIT binary patch
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zuWIfu?jGtvO$d;gVTQLjqzCY*?W8YJrJtk#=sOxIO_#q=xQh@ZTcb-EpLA%3!

[edk2-devel] [edk2-non-osi] [PATCH V1 0/9] PurleySiliconBinPkg: Restore Silicon FVs

[Nate DeSimone]

This patch series adds silicon firmware volumes back
into the PurleySiliconBinPkg. Note that actual
binaries provided by this patch series are the original
binaries from 2018, which are unlikely to boot with the
new PurleyRefreshSiliconPkg. The purpose of this patch
series is to reinstate the directory structure so that
it is possible to compile Purley MinPlatform. New
binaries will be provided as part of an upcoming
patch series.

Cc: Chasel Chiu 
Cc: Mike Kinney 
Cc: Isaac Oram 
Cc: Mohamed Abbas 
Cc: Michael Kubacki 
Cc: Zachary Bobroff 
Cc: Harikrishna Doppalapudi 
Signed-off-by: Nate DeSimone 

Nate DeSimone (9):
  PurleySiliconBinPkg/FV: Add License.txt
  PurleySiliconBinPkg/FV: Add RELEASE FvLateSilicon
  PurleySiliconBinPkg/FV: Remove DEBUG FvLateSilicon
  PurleySiliconBinPkg/FV: Add RELEASE FvPostMemorySilicon
  PurleySiliconBinPkg/FV: Add DEBUG FvPostMemorySilicon
  PurleySiliconBinPkg/FV: Add RELEASE FvPreMemorySilicon
  PurleySiliconBinPkg/FV: Add DEBUG FvPreMemorySilicon
  PurleySiliconBinPkg/FV: Add RELEASE FvTempMemorySilicon
  PurleySiliconBinPkg/FV: Add DEBUG FvTempMemorySilicon

 .../FV/FvLateSilicon/DEBUG/FVLATESILICON.Fv   |  Bin 0 -> 663512 bytes
 .../FvLateSilicon/DEBUG/FVLATESILICON.Fv.txt  |   17 +
 .../FV/FvLateSilicon/DEBUG/FvLateSilicon.inf  | 4009 +
 .../FV/FvLateSilicon/RELEASE/FVLATESILICON.Fv |  Bin 0 -> 429688 bytes
 .../RELEASE/FVLATESILICON.Fv.txt  |   17 +
 .../FvLateSilicon/RELEASE/FvLateSilicon.inf   | 3811 
 .../DEBUG/FVPOSTMEMORYSILICON.Fv  |  Bin 0 -> 196608 bytes
 .../DEBUG/FVPOSTMEMORYSILICON.Fv.txt  |3 +
 .../DEBUG/FvPostMemorySilicon.inf |  279 ++
 .../RELEASE/FVPOSTMEMORYSILICON.Fv|  Bin 0 -> 196608 bytes
 .../RELEASE/FVPOSTMEMORYSILICON.Fv.txt|3 +
 .../RELEASE/FvPostMemorySilicon.inf   |  267 ++
 .../DEBUG/FVPREMEMORYSILICON.Fv   |  Bin 0 -> 1245184 bytes
 .../DEBUG/FVPREMEMORYSILICON.Fv.txt   |7 +
 .../DEBUG/FvPreMemorySilicon.inf  | 1096 +
 .../RELEASE/FVPREMEMORYSILICON.Fv |  Bin 0 -> 1245184 bytes
 .../RELEASE/FVPREMEMORYSILICON.Fv.txt |7 +
 .../RELEASE/FvPreMemorySilicon.inf| 1051 +
 .../DEBUG/FVTEMPMEMORYSILICON.Fv  |  Bin 0 -> 131072 bytes
 .../DEBUG/FVTEMPMEMORYSILICON.Fv.txt  |4 +
 .../DEBUG/FvTempMemorySilicon.inf |  267 ++
 .../RELEASE/FVTEMPMEMORYSILICON.Fv|  Bin 0 -> 131072 bytes
 .../RELEASE/FVTEMPMEMORYSILICON.Fv.txt|4 +
 .../RELEASE/FvTempMemorySilicon.inf   |  263 ++
 .../Intel/PurleySiliconBinPkg/FV/License.txt  |   37 +
 25 files changed, 11142 insertions(+)
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvLateSilicon/DEBUG/FVLATESILICON.Fv
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvLateSilicon/DEBUG/FVLATESILICON.Fv.txt
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvLateSilicon/DEBUG/FvLateSilicon.inf
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvLateSilicon/RELEASE/FVLATESILICON.Fv
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvLateSilicon/RELEASE/FVLATESILICON.Fv.txt
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvLateSilicon/RELEASE/FvLateSilicon.inf
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/DEBUG/FVPOSTMEMORYSILICON.Fv
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/DEBUG/FVPOSTMEMORYSILICON.Fv.txt
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/DEBUG/FvPostMemorySilicon.inf
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/RELEASE/FVPOSTMEMORYSILICON.Fv
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/RELEASE/FVPOSTMEMORYSILICON.Fv.txt
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPostMemorySilicon/RELEASE/FvPostMemorySilicon.inf
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPreMemorySilicon/DEBUG/FVPREMEMORYSILICON.Fv
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPreMemorySilicon/DEBUG/FVPREMEMORYSILICON.Fv.txt
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPreMemorySilicon/DEBUG/FvPreMemorySilicon.inf
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPreMemorySilicon/RELEASE/FVPREMEMORYSILICON.Fv
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPreMemorySilicon/RELEASE/FVPREMEMORYSILICON.Fv.txt
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvPreMemorySilicon/RELEASE/FvPreMemorySilicon.inf
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvTempMemorySilicon/DEBUG/FVTEMPMEMORYSILICON.Fv
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvTempMemorySilicon/DEBUG/FVTEMPMEMORYSILICON.Fv.txt
 create mode 100644 
Silicon/Intel/PurleySiliconBinPkg/FV/FvTempMemorySilicon/DEBUG/FvTempMemorySilicon.inf
 create mode 100644 

[edk2-devel] [edk2-non-osi] [PATCH V1 1/9] PurleySiliconBinPkg/FV: Add License.txt

[Nate DeSimone]

Cc: Chasel Chiu 
Cc: Mike Kinney 
Cc: Isaac Oram 
Cc: Mohamed Abbas 
Cc: Michael Kubacki 
Cc: Zachary Bobroff 
Cc: Harikrishna Doppalapudi 
Signed-off-by: Nate DeSimone 
---
 .../Intel/PurleySiliconBinPkg/FV/License.txt  | 37 +++
 1 file changed, 37 insertions(+)
 create mode 100644 Silicon/Intel/PurleySiliconBinPkg/FV/License.txt

diff --git a/Silicon/Intel/PurleySiliconBinPkg/FV/License.txt 
b/Silicon/Intel/PurleySiliconBinPkg/FV/License.txt
new file mode 100644
index 000..73830d0
--- /dev/null
+++ b/Silicon/Intel/PurleySiliconBinPkg/FV/License.txt
@@ -0,0 +1,37 @@
+Copyright (c) 2021 Intel Corporation.
+All rights reserved.
+
+Redistribution.
+
+Redistribution and use in binary form, without modification, are permitted,
+provided that the following conditions are met:
+
+1.  Redistributions must reproduce the above copyright notice and the
+following disclaimer in the documentation and/or other materials provided
+with the distribution.
+
+2.  Neither the name of Intel Corporation nor the names of its suppliers may
+be used to endorse or promote products derived from this software without
+specific prior written permission.
+
+3.  No reverse engineering, decompilation, or disassembly of this software
+is permitted.
+
+
+"Binary form" includes any format that is commonly used for electronic
+conveyance that is a reversible, bit-exact translation of binary
+representation to ASCII or ISO text, for example "uuencode".
+
+DISCLAIMER.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
-- 
2.27.0.windows.1



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[edk2-devel] [edk2-platforms] [PATCH V1 14/18] PurleyOpenBoardPkg: Add MtOlympus build files

[Nate DeSimone]

Cc: Chasel Chiu 
Cc: Mike Kinney 
Cc: Isaac Oram 
Cc: Mohamed Abbas 
Cc: Michael Kubacki 
Cc: Zachary Bobroff 
Cc: Harikrishna Doppalapudi 
Signed-off-by: Nate DeSimone 
---
 .../BoardMtOlympus/GitEdk2MinMtOlympus.bat|  74 +++
 .../BoardMtOlympus/OpenBoardPkg.dsc   | 221 +++
 .../BoardMtOlympus/OpenBoardPkg.fdf   | 589 ++
 .../BoardMtOlympus/PlatformPkgBuildOption.dsc |  81 +++
 .../BoardMtOlympus/PlatformPkgConfig.dsc  |  58 ++
 .../BoardMtOlympus/PlatformPkgPcd.dsc | 389 
 .../PurleyOpenBoardPkg/BoardMtOlympus/bld.bat | 138 
 .../BoardMtOlympus/build_board.py | 177 ++
 .../BoardMtOlympus/build_config.cfg   |  32 +
 .../BoardMtOlympus/logo.txt   |  11 +
 .../BoardMtOlympus/postbuild.bat  |  95 +++
 .../BoardMtOlympus/prebuild.bat   | 197 ++
 Platform/Intel/build.cfg  |   1 +
 13 files changed, 2063 insertions(+)
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/GitEdk2MinMtOlympus.bat
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.dsc
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.fdf
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgBuildOption.dsc
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgConfig.dsc
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgPcd.dsc
 create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/bld.bat
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/build_board.py
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/build_config.cfg
 create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/logo.txt
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/postbuild.bat
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/prebuild.bat

diff --git 
a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/GitEdk2MinMtOlympus.bat 
b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/GitEdk2MinMtOlympus.bat
new file mode 100644
index 00..85ce5beaf8
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/GitEdk2MinMtOlympus.bat
@@ -0,0 +1,74 @@
+@REM @file
+@REM
+@REM Copyright (c) 2018, Intel Corporation. All rights reserved.
+@REM SPDX-License-Identifier: BSD-2-Clause-Patent
+@REM
+
+@echo off
+
+pushd ..\..\..\..\..\
+
+@REM Set WORKSPACE environment.
+set WORKSPACE=%cd%
+echo.
+echo Set WORKSPACE as: %WORKSPACE%
+echo.
+
+@REM Check whether Git has been installed and been added to system path.
+git --help >nul 2>nul
+if %ERRORLEVEL% NEQ 0 (
+  echo.
+  echo The 'git' command is not recognized.
+  echo Please make sure that Git is installed and has been added to system 
path.
+  echo.
+  goto :EOF
+)
+
+@REM Create the Conf directory under WORKSPACE
+if not exist %WORKSPACE%\Conf (
+  mkdir Conf
+)
+
+@REM Set other environments.
+@REM Basic Rule:
+@REM   Platform override Silicon override Core
+@REM   Source override Binary
+
+set 
PACKAGES_PATH=%WORKSPACE%\edk2-platforms\Platform\Intel;%WORKSPACE%\edk2-platforms\Silicon\Intel;%WORKSPACE%\edk2-platforms\Features\Intel;%WORKSPACE%\edk2-platforms\Features\Intel\Debugging;%WORKSPACE%\edk2-platforms\Features\Intel\Network;%WORKSPACE%\edk2-platforms\Features\Intel\OutOfBandManagement;%WORKSPACE%\edk2-platforms\Features\Intel\PowerManagement;%WORKSPACE%\edk2-platforms\Features\Intel\SystemInformation;%WORKSPACE%\edk2-platforms\Features\Intel\UserInterface;%WORKSPACE%\edk2-non-osi\Silicon\Intel;%WORKSPACE%\edk2;%WORKSPACE%
+
+set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32
+
+@if not defined PYTHON_HOME (
+  @if exist C:\Python27 (
+set PYTHON_HOME=C:\Python27
+  )
+)
+
+set EDK_SETUP_OPTION=
+@rem if python is installed, disable the binary base tools.
+if defined PYTHON_HOME (
+  set EDK_TOOLS_BIN=
+  set EDK_SETUP_OPTION=Rebuild
+)
+pushd %WORKSPACE%\edk2
+call edksetup.bat %EDK_SETUP_OPTION%
+popd
+
+set openssl_path=%WORKSPACE%
+
+popd
+
+goto :EOF
+
+:Help
+echo.
+echo Usage:
+echo GitEdk2.bat [-w Workspace_Directory] (optional) [-b Branch_Name] 
(optional)
+echo.
+echo -wA absolute/relative path to be the workspace.
+echo   Default value is the current directory.
+echo.
+echo -bThe branch name of the repository. Currently, only master, udk2015,
+echo   trunk (same as master) and bp13 (same as udk2015) are supported.
+echo   Default value is master.
+echo.
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.dsc 
b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.dsc
new file mode 100644
index 00..98e02f35e7
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/OpenBoardPkg.dsc
@@ -0,0 +1,221 @@
+## @file
+#  The main build description file for the MtOlympus board.
+#
+# Copyright (c) 2018 - 2021, Intel 

[edk2-devel] [edk2-platforms] [PATCH V1 17/18] Readme.md: Add PurleyOpenBoardPkg

[Nate DeSimone]

Cc: Chasel Chiu 
Cc: Mike Kinney 
Cc: Isaac Oram 
Cc: Mohamed Abbas 
Cc: Michael Kubacki 
Cc: Zachary Bobroff 
Cc: Harikrishna Doppalapudi 
Signed-off-by: Nate DeSimone 
---
 Platform/Intel/Readme.md | 34 ++
 Readme.md|  1 +
 2 files changed, 35 insertions(+)

diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md
index 41d39c8582..06c5f32b1e 100644
--- a/Platform/Intel/Readme.md
+++ b/Platform/Intel/Readme.md
@@ -54,6 +54,7 @@ A UEFI firmware implementation using MinPlatformPkg is 
constructed using the fol
 
 ## Board Support
 * The `KabylakeOpenBoardPkg` contains board implementations for KabyLake 
systems.
+* The `PurleyOpenBoardPkg` contains board implementations for Purley systems.
 * The `SimicsOpenBoardPkg` contains board implementations for the Simics 
hardware simulator.
 * The `WhiskeylakeOpenBoardPkg` contains board implementations for WhiskeyLake 
systems.
 * The `CometlakeOpenBoardPkg` contains board implementations for CometLake 
systems.
@@ -80,6 +81,12 @@ A UEFI firmware implementation using MinPlatformPkg is 
constructed using the fol
 
 *Note: RVP = Reference and Validation Platform*
 
+ Microsoft
+
+| Machine Name  | Supported Chipsets   
  | BoardPkg | Board Name |
+||--||
+| Mt. Olympus   | Purley   
  | PurleyOpenBoardPkg   | BoardMtOlympus |
+
  Simics
 
 | Machine Name  | Supported Chipsets   
  | BoardPkg | Board Name |
@@ -237,6 +244,13 @@ return back to the minimum platform caller.
   |   ||   |---build_board.py: Optional 
board-specific pre-build, build
   |   ||   and clean 
post-build functions.
   |   ||
+  |   ||--PurleyOpenBoardPkg
+  |   ||   |--BoardMtOlympus
+  |   ||   |---build_config.cfg: 
BoardMtOlympus specific
+  |   ||   | build 
settings, environment variables.
+  |   ||   |---build_board.py: Optional 
board-specific pre-build,
+  |   ||   build, 
post-build and clean functions.
+  |   ||
   |   ||--SimicsOpenBoardPkg
   |   ||   |--BoardX58Ich10
   |   ||   |---build_config.cfg: BoardX58Ich10 
specific
@@ -263,6 +277,21 @@ return back to the minimum platform caller.
   |--FSP
   
 
+**Building with the batch scripts**
+
+Only PurleyOpenBoardPkg still supports batch script build (in addition to 
Python build). Batch scripts are deprecated
+and will be removed from PurleyOpenBoardPkg in the future. All other board 
packages must only use the Python build
+infrastructure.
+
+For PurleyOpenBoardPkg
+1. Open command window, go to the workspace directory, e.g. c:\Edk2Workspace.
+2. Type "cd edk2-platforms\Platform\Intel\PurleyOpenBoardPkg\BoardMtOlympus".
+3. Type "GitEdk2MinMtOlympus.bat" to setup GIT environment.
+4. Type "bld" to build Purley Mt Olympus board UEFI firmware image, "bld 
release" for release build, "bld clean" to
+   remove intermediate files."bld cache-produce" Generate a cache of binary 
files in the specified directory,
+   "bld cache-consume" Consume a cache of binary files from the specified 
directory, BINARY_CACHE_PATH is empty,
+   used "BinCache" as default path.
+
 ### **Known limitations**
 
 **KabylakeOpenBoardPkg**
@@ -273,6 +302,11 @@ return back to the minimum platform caller.
 1. This firmware project has only been tested for Microsoft Windows 10 x64 
boot with AHCI mode and Integrated Graphic
Device.
 
+**PurleyOpenBoardPkg**
+1. This firmware project has only been tested booting to Microsoft Windows 
Server 2016 with NVME on M.2 slot.
+2. This firmware project does not build with the GCC compiler.
+3. The validated version of iASL compiler that can build MinPurley is 
20180629. Older versions may generate ACPI build errors.
+
 **SimicsOpenBoardPkg**
 1. This firmware project has only been tested booting to Microsoft Windows 10 
x64 and Ubuntu 17.10 with AHCI mode.
 
diff --git a/Readme.md b/Readme.md
index d00600d350..aba26e29a6 100644
--- a/Readme.md
+++ b/Readme.md
@@ -243,6 +243,7 @@ they will be documented with the platform.
 ## Intel
 ### [Minimum Platforms](Platform/Intel/Readme.md)
 * [Kaby Lake](Platform/Intel/KabylakeOpenBoardPkg)
+* [Purley](Platform/Intel/PurleyOpenBoardPkg)
 * [Simics](Platform/Intel/SimicsOpenBoardPkg)
 * [Whiskey Lake](Platform/Intel/WhiskeylakeOpenBoardPkg)
 * 

[edk2-devel] [edk2-platforms] [PATCH V1 08/18] PurleyOpenBoardPkg: Add includes and libraries

[Nate DeSimone]

Cc: Chasel Chiu 
Cc: Mike Kinney 
Cc: Isaac Oram 
Cc: Mohamed Abbas 
Cc: Michael Kubacki 
Cc: Zachary Bobroff 
Cc: Harikrishna Doppalapudi 
Signed-off-by: Nate DeSimone 
---
 .../Ipmi/Library/IpmiLibKcs/IpmiLibKcs.c  | 362 ++
 .../Ipmi/Library/IpmiLibKcs/IpmiLibKcs.inf|  40 ++
 .../Features/Ipmi/Library/IpmiLibKcs/KcsBmc.c | 485 +
 .../Features/Ipmi/Library/IpmiLibKcs/KcsBmc.h | 208 ++
 .../IpmiPlatformHookLib/IpmiPlatformHookLib.c |  39 ++
 .../IpmiPlatformHookLib.inf   |  28 +
 .../Include/Acpi/GlobalNvs.asi| 282 
 .../Include/Acpi/GlobalNvsAreaDef.h   | 128 
 .../Include/Guid/PchRcVariable.h  | 414 +++
 .../Include/Guid/SetupVariable.h  | 539 ++
 .../Include/IioBifurcationSlotTable.h | 100 +++
 .../PurleyOpenBoardPkg/Include/Platform.h |  92 +++
 .../Include/Ppi/SystemBoard.h |  63 ++
 .../Include/Protocol/PciIovPlatform.h |  70 ++
 .../PurleyOpenBoardPkg/Include/SetupTable.h   |  21 +
 .../PurleyOpenBoardPkg/Include/SioRegs.h  |  35 +
 .../Intel/PurleyOpenBoardPkg/OpenBoardPkg.dec | 141 
 .../SiliconPolicyInitLib.c| 130 
 .../SiliconPolicyInitLib.inf  |  39 ++
 .../PchPolicyUpdateUsb.c  |  99 +++
 .../SiliconPolicyUpdateLib.c  | 659 ++
 .../SiliconPolicyUpdateLib.inf|  54 ++
 22 files changed, 4028 insertions(+)
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/IpmiLibKcs.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/IpmiLibKcs.inf
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/KcsBmc.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/KcsBmc.h
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf
 create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/Acpi/GlobalNvs.asi
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Include/Guid/PchRcVariable.h
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Include/Guid/SetupVariable.h
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Include/IioBifurcationSlotTable.h
 create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/Platform.h
 create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/Ppi/SystemBoard.h
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Include/Protocol/PciIovPlatform.h
 create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/SetupTable.h
 create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/SioRegs.h
 create mode 100644 Platform/Intel/PurleyOpenBoardPkg/OpenBoardPkg.dec
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyInitLib/SiliconPolicyInitLib.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyInitLib/SiliconPolicyInitLib.inf
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyUpdateLib/PchPolicyUpdateUsb.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.inf

diff --git 
a/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/IpmiLibKcs.c
 
b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/IpmiLibKcs.c
new file mode 100644
index 00..700e413aa6
--- /dev/null
+++ 
b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/IpmiLibKcs.c
@@ -0,0 +1,362 @@
+/** @file
+  IPMI library - KCS.
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "KcsBmc.h"
+
+#define MAX_TEMP_DATA 160
+
+//
+// Structure of IPMI Command buffer
+//
+#define EFI_IPMI_COMMAND_HEADER_SIZE  2
+
+typedef struct {
+  UINT8 Lun : 2;
+  UINT8 NetFunction : 6;
+  UINT8 Command;
+  UINT8 CommandData[MAX_TEMP_DATA - EFI_IPMI_COMMAND_HEADER_SIZE];
+} EFI_IPMI_COMMAND;
+
+//
+// Structure of IPMI Command response buffer
+//
+#define EFI_IPMI_RESPONSE_HEADER_SIZE 2
+
+typedef struct {
+  UINT8 Lun : 2;
+  UINT8 NetFunction : 6;
+  UINT8 Command;
+  UINT8 ResponseData[MAX_TEMP_DATA - EFI_IPMI_RESPONSE_HEADER_SIZE];
+} EFI_IPMI_RESPONSE;
+
+
+#define IPMI_INSTANCE_INFO_HOB_GUID { \
+  0x38ee71f, 0x1c78, 0x4874, { 0xba, 0xe3, 0xf8, 0xa2, 0x57, 0x75, 0x28, 0x52 
} \
+  }
+
+EFI_GUID mIpmiInstanceGuid = IPMI_INSTANCE_INFO_HOB_GUID;
+

[edk2-devel] [edk2-platforms] [PATCH V1 16/18] PurleyOpenBoardPkg: Add BoardMtOlympus

[Nate DeSimone]

Cc: Chasel Chiu 
Cc: Mike Kinney 
Cc: Isaac Oram 
Cc: Mohamed Abbas 
Cc: Michael Kubacki 
Cc: Zachary Bobroff 
Cc: Harikrishna Doppalapudi 
Signed-off-by: Nate DeSimone 
---
 .../BasePlatformHookLib/BasePlatformHookLib.c | 292 +
 .../BasePlatformHookLib.inf   |  36 +
 .../BoardAcpiLib/DxeBoardAcpiTableLib.c   |  35 +
 .../BoardAcpiLib/DxeBoardAcpiTableLib.inf |  40 ++
 .../BoardAcpiLib/DxeMtOlympusAcpiTableLib.c   |  52 ++
 .../BoardAcpiLib/SmmBoardAcpiEnableLib.c  |  61 ++
 .../BoardAcpiLib/SmmBoardAcpiEnableLib.inf|  41 ++
 .../BoardAcpiLib/SmmMtOlympusAcpiEnableLib.c  |  36 +
 .../BoardAcpiLib/SmmSiliconAcpiEnableLib.c| 119 
 .../Library/BoardInitLib/AllLanesEparam.c |  43 ++
 .../Library/BoardInitLib/GpioTable.c  | 296 +
 .../Library/BoardInitLib/IioBifur.c   |  88 +++
 .../BoardInitLib/PeiBoardInitPostMemLib.c |  45 ++
 .../BoardInitLib/PeiBoardInitPostMemLib.inf   |  37 ++
 .../BoardInitLib/PeiBoardInitPreMemLib.c  | 111 
 .../BoardInitLib/PeiBoardInitPreMemLib.inf|  69 ++
 .../Library/BoardInitLib/PeiMtOlympusDetect.c |  27 +
 .../BoardInitLib/PeiMtOlympusInitLib.h|  17 +
 .../BoardInitLib/PeiMtOlympusInitPostMemLib.c |  85 +++
 .../BoardInitLib/PeiMtOlympusInitPreMemLib.c  | 614 ++
 .../Library/BoardInitLib/UsbOC.c  |  45 ++
 21 files changed, 2189 insertions(+)
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.inf
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeMtOlympusAcpiTableLib.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmMtOlympusAcpiEnableLib.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/AllLanesEparam.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/GpioTable.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/IioBifur.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusDetect.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitLib.h
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPostMemLib.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPreMemLib.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/UsbOC.c

diff --git 
a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.c
 
b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.c
new file mode 100644
index 00..4c539de755
--- /dev/null
+++ 
b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.c
@@ -0,0 +1,292 @@
+/** @file
+
+Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define R_ICH_IOPORT_PCI_INDEX  0xCF8
+#define R_ICH_IOPORT_PCI_DATA   0xCFC
+#define R_ICH_LPC_IO_DEC 0x80
+
+#define PCI_DEVICE_NUMBER_ICH_LPC  31
+#define PCI_FUNCTION_NUMBER_ICH_LPC0
+
+#define PCI_CF8_ADDR(Bus, Dev, Func, Off) \
+  (((Off) & 0xFF) | (((Func) & 0x07) << 8) | (((Dev) & 0x1F) << 11) | 
(((Bus) & 0xFF) << 16) | (1 << 31))
+#define ICH_LPC_CF8_ADDR(Offset)PCI_CF8_ADDR(0, PCI_DEVICE_NUMBER_ICH_LPC, 
PCI_FUNCTION_NUMBER_ICH_LPC, Offset)
+

[edk2-devel] [edk2-platforms] [PATCH V1 13/18] PurleyOpenBoardPkg/Acpi: Add BoardAcpiDxe

[Nate DeSimone]

Cc: Chasel Chiu 
Cc: Mike Kinney 
Cc: Isaac Oram 
Cc: Mohamed Abbas 
Cc: Michael Kubacki 
Cc: Zachary Bobroff 
Cc: Harikrishna Doppalapudi 
Signed-off-by: Nate DeSimone 
---
 .../Acpi/BoardAcpiDxe/AmlOffsetTable.c| 290 ++
 .../Acpi/BoardAcpiDxe/BoardAcpiDxe.c  | 547 ++
 .../Acpi/BoardAcpiDxe/BoardAcpiDxe.h  |  82 +++
 .../Acpi/BoardAcpiDxe/BoardAcpiDxe.inf|  71 +++
 .../Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c  | 516 +
 .../Acpi/BoardAcpiDxe/Dsdt.inf|  29 +
 6 files changed, 1535 insertions(+)
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.h
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
 create mode 100644 
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c
 create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt.inf

diff --git 
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c 
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c
new file mode 100644
index 00..abb484172e
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c
@@ -0,0 +1,290 @@
+/** @file
+  Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/*
+ * 
+ * Intel ACPI Component Architecture
+ * 
+ * 
+ */
+#ifndef __AML_OFFSET_TABLE_H
+#define __AML_OFFSET_TABLE_H
+
+typedef struct {
+char   *Pathname;  /* Full pathname (from root) to the 
object */
+unsigned short ParentOpcode;   /* AML opcode for the parent object 
*/
+unsigned long  NamesegOffset;  /* Offset of last nameseg in the 
parent namepath */
+unsigned char  Opcode; /* AML opcode for the data */
+unsigned long  Offset; /* Offset for the data */
+unsigned long long Value;  /* Original value of the data (as 
applicable) */
+} AML_OFFSET_TABLE_ENTRY;
+
+#endif /* __AML_OFFSET_TABLE_H */
+
+/*
+ * Information specific to the supported object types:
+ *
+ * Integers:
+ *Opcode is the integer prefix, indicates length of the data
+ *(One of: BYTE, WORD, DWORD, QWORD, ZERO, ONE, ONES)
+ *Offset points to the actual integer data
+ *Value is the existing value in the AML
+ *
+ * Packages:
+ *Opcode is the package or var_package opcode
+ *Offset points to the package opcode
+ *Value is the package element count
+ *
+ * Operation Regions:
+ *Opcode is the address integer prefix, indicates length of the data
+ *Offset points to the region address
+ *Value is the existing address value in the AML
+ *
+ * Control Methods:
+ *Offset points to the method flags byte
+ *Value is the existing flags value in the AML
+ *
+ * Processors:
+ *Offset points to the first byte of the PBlock Address
+ *
+ * Resource Descriptors:
+ *Opcode is the descriptor type
+ *Offset points to the start of the descriptor
+ *
+ * Scopes/Devices/ThermalZones:
+ *Nameseg offset only
+ */
+AML_OFFSET_TABLE_ENTRY   DSDT_PLATWFP__OffsetTable[] =
+{
+{"PSYS",   0x5B80, 0x038B, 0x0C, 0x0391, 
0x30584946}, /* OPERATIONREGION */
+{"_SB_.PC00.FIX1", 0x0011, 0x, 0x88, 0xD187, 
0x}, /* WORDBUSNUMBER */
+{"_SB_.PC00.FIX2", 0x0011, 0x, 0x88, 0xD1AF, 
0x}, /* WORDIO */
+{"_SB_.PC00.FIX5", 0x0011, 0x, 0x87, 0xD1BF, 
0x}, /* DWORDMEMORY */
+{"_SB_.PC00.FIX3", 0x0011, 0x, 0x87, 0xD20D, 
0x}, /* DWORDMEMORY */
+{"_SB_.PC00.FIX4", 0x0011, 0x, 0x8A, 0xD227, 
0x}, /* QWORDMEMORY */
+{"_SB_.PC01.FIX1", 0x0011, 0x, 0x88, 0xEA9B, 
0x}, /* WORDBUSNUMBER */
+{"_SB_.PC01.FIX5", 0x0011, 0x, 0x87, 0xEAAB, 
0x}, /* DWORDMEMORY */
+{"_SB_.PC01.FIX2", 0x0011, 0x, 0x88, 0xEAC5, 
0x}, /* WORDIO */
+{"_SB_.PC01.FIX6", 0x0011, 0x, 0x88, 0xEAD5, 
0x}, /* WORDIO */
+{"_SB_.PC01.FIX7", 0x0011, 0x, 0x88, 0xEAE5, 
0x}, /* WORDIO */
+{"_SB_.PC01.FIX3", 0x0011, 0x, 0x87, 0xEAF5, 
0x}, /* DWORDMEMORY */
+{"_SB_.PC01.FIX4", 0x0011, 0x, 0x8A, 0xEB0F, 
0x}, /* QWORDMEMORY */
+{"_SB_.PC01.BR1A.MCTL",0x5B80, 0xEB91, 0x0C, 0xEB97, 
0x38584946}, /* OPERATIONREGION */
+

[edk2-devel] [edk2-platforms] [PATCH V1 18/18] Maintainers.txt: Add PurleyOpenBoardPkg and PurleyRefreshSiliconPkg

[Nate DeSimone]

Cc: Chasel Chiu 
Cc: Mike Kinney 
Cc: Isaac Oram 
Cc: Mohamed Abbas 
Cc: Michael Kubacki 
Cc: Zachary Bobroff 
Cc: Harikrishna Doppalapudi 
Signed-off-by: Nate DeSimone 
---
 Maintainers.txt | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/Maintainers.txt b/Maintainers.txt
index f6313b430c..10a9521ec3 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -195,6 +195,11 @@ M: Nate DeSimone 
 R: Liming Gao 
 R: Eric Dong 
 
+Platform/Intel/PurleyOpenBoardPkg
+F: Platform/Intel/PurleyOpenBoardPkg/
+M: Nate DeSimone 
+M: Chasel Chiu 
+
 Platform/Intel/WhiskeylakeOpenBoardPkg
 F: Platform/Intel/WhiskeylakeOpenBoardPkg/
 M: Chasel Chiu 
@@ -263,6 +268,11 @@ F: Silicon/Intel/KabylakeSiliconPkg/
 M: Chasel Chiu 
 M: Sai Chaganty 
 
+Silicon/Intel/PurleyRefreshSiliconPkg
+F: Silicon/Intel/PurleyRefreshSiliconPkg/
+M: Chasel Chiu 
+M: Nate DeSimone 
+
 Silicon/Intel/TigerlakeSiliconPkg
 F: Silicon/Intel/TigerlakeSiliconPkg/
 M: Sai Chaganty 
-- 
2.27.0.windows.1



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[edk2-devel] [edk2-platforms] [PATCH V1 04/18] PurleyRefreshSiliconPkg/Pch: Add Private Header Files

[Nate DeSimone]

Cc: Chasel Chiu 
Cc: Mike Kinney 
Cc: Isaac Oram 
Cc: Mohamed Abbas 
Cc: Michael Kubacki 
Cc: Zachary Bobroff 
Cc: Harikrishna Doppalapudi 
Signed-off-by: Nate DeSimone 
---
 .../Library/PchResetCommonLib.h   |  59 +++
 .../Pch/IncludePrivate/PchHHsioAx.h   |  16 ++
 .../Pch/IncludePrivate/PchHHsioBx.h   |  16 ++
 .../Pch/IncludePrivate/PchHHsioDx.h   |  16 ++
 .../Pch/IncludePrivate/PchHsio.h  | 147 ++
 .../Pch/IncludePrivate/PchLbgHsioAx.h |  16 ++
 .../Pch/IncludePrivate/PchLbgHsioBx.h |  17 ++
 .../Pch/IncludePrivate/PchLbgHsioBxD.h|  19 +++
 .../Pch/IncludePrivate/PchLbgHsioBxD_Ext.h|  19 +++
 .../Pch/IncludePrivate/PchLbgHsioBx_Ext.h |  17 ++
 .../Pch/IncludePrivate/PchLbgHsioSx.h |  17 ++
 .../Pch/IncludePrivate/PchLbgHsioSx_Ext.h |  17 ++
 .../Pch/IncludePrivate/PchLpHsioBx.h  |  16 ++
 .../Pch/IncludePrivate/PchLpHsioCx.h  |  16 ++
 .../Pch/IncludePrivate/PchPolicyHob.h |  18 +++
 15 files changed, 426 insertions(+)
 create mode 100644 
Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/Library/PchResetCommonLib.h
 create mode 100644 
Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioAx.h
 create mode 100644 
Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioBx.h
 create mode 100644 
Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioDx.h
 create mode 100644 
Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHsio.h
 create mode 100644 
Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioAx.h
 create mode 100644 
Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBx.h
 create mode 100644 
Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBxD.h
 create mode 100644 
Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBxD_Ext.h
 create mode 100644 
Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioBx_Ext.h
 create mode 100644 
Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioSx.h
 create mode 100644 
Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLbgHsioSx_Ext.h
 create mode 100644 
Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLpHsioBx.h
 create mode 100644 
Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchLpHsioCx.h
 create mode 100644 
Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchPolicyHob.h

diff --git 
a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/Library/PchResetCommonLib.h
 
b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/Library/PchResetCommonLib.h
new file mode 100644
index 00..a1d076c06c
--- /dev/null
+++ 
b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/Library/PchResetCommonLib.h
@@ -0,0 +1,59 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCH_RESET_COMMON_LIB_H_
+#define _PCH_RESET_COMMON_LIB_H_
+#include 
+#include 
+///
+/// Private data structure definitions for the driver
+///
+#define PCH_RESET_SIGNATURE SIGNATURE_32 ('I', 'E', 'R', 'S')
+
+typedef struct {
+  UINT32  Signature;
+  EFI_HANDLE  Handle;
+  union {
+PCH_RESET_PPI   PchResetPpi;
+PCH_RESET_PROTOCOL  PchResetProtocol;
+  }PchResetInterface;
+  UINT32  PchPwrmBase;
+  UINT16  PchAcpiBase;
+  UINTN   PchPmcBase;
+} PCH_RESET_INSTANCE;
+
+//
+// Function prototypes used by the Pch Reset ppi/protocol.
+//
+/**
+  Initialize an Pch Reset ppi/protocol instance.
+
+  @param[in] PchResetInstance Pointer to PchResetInstance to initialize
+
+  @retval EFI_SUCCESS The protocol instance was properly 
initialized
+  @exception EFI_UNSUPPORTED  The PCH is not supported by this module
+**/
+EFI_STATUS
+PchResetConstructor (
+  PCH_RESET_INSTANCE  *PchResetInstance
+  );
+
+/**
+  Execute Pch Reset from the host controller.
+  @param[in] PchResetInstance Pointer to PchResetInstance to initialize
+  @param[in] PchResetType Pch Reset Types which includes ColdReset, 
WarmReset, ShutdownReset,
+  PowerCycleReset, GlobalReset, 
GlobalResetWithEc
+
+  @retval EFI_SUCCESS Successfully completed.
+  @retval EFI_INVALID_PARAMETER   If ResetType is invalid.
+**/
+EFI_STATUS
+PchReset (
+  IN PCH_RESET_INSTANCE *PchResetInstance,
+  IN PCH_RESET_TYPE PchResetType
+  );
+#endif
diff --git 
a/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioAx.h 
b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioAx.h
new file mode 100644
index 00..37adb642c6
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/Pch/IncludePrivate/PchHHsioAx.h
@@ -0,0 +1,16 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef 

[edk2-devel] [edk2-platforms] [PATCH V1 00/18] Reinstate Purley MinPlatform

[Nate DeSimone]

This patch series revives the PurleyOpenBoardPkg. The package has been
upgraded to support the newest MinPlatformPkg and the new advanced
feature architecture. Build issues with the newest EDK II have been
fixed. Finally, I believe most (if not all) MinPlatform Architecture
violations have been fixed. The build system has been converted from
the legacy .bat scripts to the new Python build infrastructure.

For silicon code, I have consolidated PurleyRcPkg, PurleySktPkg,
and LewisburgPkg into a single PurleyRefreshSiliconPkg for consistency
with the other MinPlatform board port's silicon packages. In addition,
the silicon code has been upgraded to a newer version with support
for the 2nd Generation Xeon Scalable "Cascade Lake" processors.

Cc: Chasel Chiu 
Cc: Mike Kinney 
Cc: Isaac Oram 
Cc: Mohamed Abbas 
Cc: Michael Kubacki 
Cc: Zachary Bobroff 
Cc: Harikrishna Doppalapudi 
Signed-off-by: Nate DeSimone 

Nate DeSimone (18):
  PurleyRefreshSiliconPkg: Add DEC and DSC files.
  PurleyRefreshSiliconPkg/Pch: Add Register Header Files
  PurleyRefreshSiliconPkg/Pch: Add Public Header Files
  PurleyRefreshSiliconPkg/Pch: Add Private Header Files
  PurleyRefreshSiliconPkg/Pch: Add libraries
  PurleyRefreshSiliconPkg/Pch: Add ACPI tables
  PurleyRefreshSiliconPkg: Add Uncore files
  PurleyOpenBoardPkg: Add includes and libraries
  PurleyOpenBoardPkg: Add modules
  PurleyOpenBoardPkg/Acpi/BoardAcpiDxe: Add PlatformPciTree_WFP.asi
  PurleyOpenBoardPkg/Acpi/BoardAcpiDxe: Add PCxx.asi files
  PurleyOpenBoardPkg/Acpi/BoardAcpiDxe: Add ASL files
  PurleyOpenBoardPkg/Acpi: Add BoardAcpiDxe
  PurleyOpenBoardPkg: Add MtOlympus build files
  PurleyOpenBoardPkg: Add StructureConfig.dsc
  PurleyOpenBoardPkg: Add BoardMtOlympus
  Readme.md: Add PurleyOpenBoardPkg
  Maintainers.txt: Add PurleyOpenBoardPkg and PurleyRefreshSiliconPkg

 Maintainers.txt   |   10 +
 .../Acpi/BoardAcpiDxe/AmlOffsetTable.c|  290 +
 .../Acpi/BoardAcpiDxe/BoardAcpiDxe.c  |  547 ++
 .../Acpi/BoardAcpiDxe/BoardAcpiDxe.h  |   82 +
 .../Acpi/BoardAcpiDxe/BoardAcpiDxe.inf|   71 +
 .../Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c  |  516 ++
 .../Acpi/BoardAcpiDxe/Dsdt.inf|   29 +
 .../Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl |   19 +
 .../Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi |  227 +
 .../Acpi/BoardAcpiDxe/Dsdt/DSDT.asl   |   77 +
 .../Acpi/BoardAcpiDxe/Dsdt/Gpe.asl|  134 +
 .../Acpi/BoardAcpiDxe/Dsdt/HostBus.asl|  256 +
 .../Dsdt/IioPcieHotPlugGpeHandler.asl |  842 ++
 .../Dsdt/IioPcieRootPortHotPlug.asl   |  686 ++
 .../Acpi/BoardAcpiDxe/Dsdt/Itss.asl   |   32 +
 .../Acpi/BoardAcpiDxe/Dsdt/Mother.asi |  202 +
 .../Acpi/BoardAcpiDxe/Dsdt/Os.asi |  145 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC00.asi   |  385 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC01.asi   |  255 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC02.asi   |  255 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC03.asi   |  260 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC04.asi   |  232 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC05.asi   |  233 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC06.asi   |  328 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC06Ejd.asi|9 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC07.asi   |  259 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC08.asi   |  262 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC09.asi   |  260 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC10.asi   |  232 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC11.asi   |  231 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC12.asi   |  324 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC12Ejd.asi|9 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC13.asi   |  256 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC14.asi   |  259 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC15.asi   |  259 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC16.asi   |  231 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC17.asi   |  231 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC18.asi   |  342 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC18Ejd.asi|9 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC19.asi   |  259 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC20.asi   |  260 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC21.asi   |  260 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC22.asi   |  232 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC23.asi   |  232 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC24.asi   |  231 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC25.asi   |  259 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC26.asi   |  259 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC27.asi   |  259 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC28.asi   |  232 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC29.asi   |  232 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC30.asi   |  256 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC31.asi   |  259 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC32.asi   |  260 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC33.asi   |  260 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC34.asi   |  232 +
 .../Acpi/BoardAcpiDxe/Dsdt/PC35.asi   |  232 +
 

[edk2-devel] [edk2-platforms] [PATCH V1 01/18] PurleyRefreshSiliconPkg: Add DEC and DSC files.

[Nate DeSimone]

Cc: Chasel Chiu 
Cc: Mike Kinney 
Cc: Isaac Oram 
Cc: Mohamed Abbas 
Cc: Michael Kubacki 
Cc: Zachary Bobroff 
Cc: Harikrishna Doppalapudi 
Signed-off-by: Nate DeSimone 
---
 .../Intel/PurleyRefreshSiliconPkg/SiPkg.dec   | 390 ++
 .../SiPkgCommonLib.dsc|  33 ++
 .../PurleyRefreshSiliconPkg/SiPkgDxeLib.dsc   |  22 +
 .../PurleyRefreshSiliconPkg/SiPkgPeiLib.dsc   |  12 +
 4 files changed, 457 insertions(+)
 create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/SiPkg.dec
 create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgCommonLib.dsc
 create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgDxeLib.dsc
 create mode 100644 Silicon/Intel/PurleyRefreshSiliconPkg/SiPkgPeiLib.dsc

diff --git a/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkg.dec 
b/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkg.dec
new file mode 100644
index 00..1ec91ee25a
--- /dev/null
+++ b/Silicon/Intel/PurleyRefreshSiliconPkg/SiPkg.dec
@@ -0,0 +1,390 @@
+## @file
+# Component description file for the Purley Refresh Silicon Reference Code.
+#
+# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  DEC_SPECIFICATION  = 0x00010005
+  PACKAGE_NAME   = PurleyRefreshSiliconPkg
+  PACKAGE_GUID   = 0BF28B71-A81D-4029-BEC2-A4BE58A0D0D5
+  PACKAGE_VERSION= 0.1
+
+[Includes]
+  Include
+  Include/Library
+  Include/Guid
+
+  Library/BaseMemoryCoreLib/Core
+  Library/BaseMemoryCoreLib/Core/Include
+  Library/BaseMemoryCoreLib/Platform/Purley/Include
+
+  Library/BaseMemoryCoreLib/Chip/Skx
+  Library/BaseMemoryCoreLib/Chip/Skx/Include
+  Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio
+  Library/BaseMemoryCoreLib/Chip/Skx/Include/Protocol
+  Library/BaseMemoryCoreLib/Chip/Skx/Include/Setup
+
+  Library/ProcMemInit/Chip/Include
+  Override/IA32FamilyCpuPkg
+  Override/IA32FamilyCpuPkg/Include
+
+  Iio/Include
+  Iio/Include/Protocol
+
+  Pch
+  Pch/Include
+  Pch/IncludePrivate
+  Pch/AcpiTables/Dsdt
+
+[LibraryClasses]
+
+  ##  @libraryclass  Provides services to get the silicon access library.
+  SiliconAccessLib|Include/Library/UsraAccessApi.h
+
+  ##  @libraryclass  Provides services to convert CSR to PCIE address library.
+  CsrToPcieLib|PurleyRefreshSiliconPkg/Include/Library/CsrToPcieAddress.h
+
+  ##  @libraryclass  Provides services to PCIE address library.
+  PcieAddrLib|PurleyRefreshSiliconPkg/Include/Library/PcieAddress.h
+
+  ##  @libraryclass  Provides services to get PCI Express Address Base library.
+  MmPciLib|PurleyRefreshSiliconPkg/Include/Library/MmPciBaseLib.h
+
+  ##  @libraryclass  Provides services to get the silicon access library.
+  UsraLib|PurleyRefreshSiliconPkg/Include/Protocol/SiliconRegAccess.h
+
+[Guids]
+
+  ## Include/Guid/CpRcPkgTokenSpace.h
+  gEfiCpRcPkgTokenSpaceGuid   = { 0xfcdd2efc, 0x6ca8, 
0x4d0b, { 0x9d, 0x00, 0x6f, 0x9c, 0xfa, 0x57, 0x8f, 0x98 }}
+  gRcPkgTokenSpaceGuid= { 0x86cf2b1a, 0xb3da, 
0x4642, { 0x95, 0xf5, 0xd0, 0x1c, 0x6c, 0x1c, 0x60, 0xb8 }}
+  gEfiPchTokenSpaceGuid   = { 0x89a1b278, 0xa1a1, 
0x4df7, { 0xb1, 0x37, 0xde, 0x5a, 0xd7, 0xc4, 0x79, 0x13 }}
+  gEfiCommonPkgTokenSpaceGuid = { 0x86cf2b1a, 0xb3da, 
0x4642, { 0x95, 0xf5, 0xd0, 0x1c, 0x6c, 0x1c, 0x60, 0xb8 }}
+  gEfiPchTokenSpaceGuid   = { 0x977c97c1, 0x47e1, 
0x4b6b, { 0x96, 0x69, 0x43, 0x66, 0x99, 0xcb, 0xe4, 0x5b }}
+  gCpuUncoreTokenSpaceGuid= { 0x9044434c, 0x40e8, 
0x47a1, { 0xa3, 0xba, 0x85, 0x07, 0xf3, 0xc0, 0xe2, 0x56 }}
+  gPlatformTokenSpaceGuid = { 0x07dfa0d2, 0x2ac5, 
0x4cab, { 0xac, 0x14, 0x30, 0x5c, 0x62, 0x48, 0x87, 0xe4 }}
+
+  #
+  # Uncore
+  #
+  gProcessorProducerGuid  = { 0x1bf06aea, 0x5bec, 
0x4a8d, { 0x95, 0x76, 0x74, 0x9b, 0x09, 0x56, 0x2d, 0x30 }}
+  gEfiCpuHtCapableGuid= { 0x0d1b9c8e, 0xf77b, 
0x4632, { 0x83, 0x43, 0x91, 0xf4, 0x3d, 0x9a, 0x85, 0x60 }}
+  gEfiMemoryConfigDataGuid= { 0x80dbd530, 0xb74c, 
0x4f11, { 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 }}
+  gEfiMemoryConfigDataHobGuid = { 0x1de25879, 0x6e2a, 
0x4d72, { 0xa7, 0x68, 0x28, 0x8c, 0xcb, 0x9f, 0xa7, 0x19 }}
+  gEfiMemorySetupGuid = { 0x3eeff35f, 0x147c, 
0x4cd1, { 0xa2, 0x34, 0x92, 0xa0, 0x69, 0x70, 0x0d, 0xb6 }}
+  gEfiMemoryMapGuid   = { 0xf8870015, 0x6994, 
0x4b98, { 0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f }}
+  gEfiMemoryMapDataHobBdatGuid= { 0x3417b225, 0x916a, 
0x49f5, { 0x9a, 0xf5, 0xc9, 0xc7, 0xbf, 0x93, 0x7e, 0xa2 }}
+  gEfiMpstNodeDataGuid= { 0x418bc604, 0xf15e, 
0x4843, { 0x85, 0xd0, 0x2d, 0x24, 0x80, 0xb7, 0xe4, 

Re: [edk2-devel][PATCH v5 6/7] MiniPlatformPkg: Move ReportCpuHob library path

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 

> -Original Message-
> From: Chuang, SofiaX 
> Sent: Tuesday, May 11, 2021 3:54 AM
> To: devel@edk2.groups.io
> Cc: Chuang, SofiaX ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Liming Gao ;
> Dong, Eric 
> Subject: [edk2-devel][PATCH v5 6/7]
> MiniPlatformPkg: Move ReportCpuHob library path
> 
> From: SofiaX Chuang 
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298
> 
> Move ReportCpuHob library from MinPlatformPkg to IntelSiliconPkg.
> 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Cc: Eric Dong 
> ---
>  Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc   | 2 +-
>  .../PlatformInit/PlatformInitPei/PlatformInitPreMem.inf| 3 ++-
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
> b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
> index 707686055c..35cbd40abb 100644
> --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
> +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dsc
> @@ -94,7 +94,7 @@
>#
> 
> 
> FspWrapperPlatformLib|MinPlatformPkg/FspWrapper/Library/PeiFspWrapperPl
> atformLib/PeiFspWrapperPlatformLib.inf
> 
> 
> ReportFvLib|MinPlatformPkg/PlatformInit/Library/PeiReportFvLib/PeiReportFvLi
> b.inf
> 
> -
> ReportCpuHobLib|MinPlatformPkg/PlatformInit/Library/ReportCpuHobLib/Repo
> rtCpuHobLib.inf
> 
> +
> ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.i
> nf
> 
> 
> TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestPoin
> tCheckLib.inf
> 
>TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf
> 
> 
> SetCacheMtrrLib|MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNul
> l.inf
> 
> diff --git
> a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPre
> Mem.inf
> b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPre
> Mem.inf
> index e37bcba560..fb997838ef 100644
> ---
> a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPre
> Mem.inf
> +++
> b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPre
> Mem.inf
> @@ -1,7 +1,7 @@
>  ### @file
> 
>  # Component information file for the Platform Init Pre-Memory PEI module.
> 
>  #
> 
> -# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
> 
> +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
> 
>  #
> 
>  # SPDX-License-Identifier: BSD-2-Clause-Patent
> 
>  #
> 
> @@ -33,6 +33,7 @@
>MinPlatformPkg/MinPlatformPkg.dec
> 
>MdeModulePkg/MdeModulePkg.dec
> 
>MdePkg/MdePkg.dec
> 
> +  IntelSiliconPkg/IntelSiliconPkg.dec
> 
> 
> 
>  [Pcd]
> 
>gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode  ##
> CONSUMES
> 
> --
> 2.27.0



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Re: [edk2-devel][PATCH v5 5/7] WhiskeylakeOpenBoard: Move library path

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 

> -Original Message-
> From: Chuang, SofiaX 
> Sent: Tuesday, May 11, 2021 3:54 AM
> To: devel@edk2.groups.io
> Cc: Chuang, SofiaX ; Chiu, Chasel
> ; Desimone, Nathaniel L
> 
> Subject: [edk2-devel][PATCH v5 5/7] WhiskeylakeOpenBoard: Move library path
> 
> From: SofiaX Chuang 
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298
> 
> Move ReportCpuHob library from MinPlatformPkg to IntelSiliconPkg.
> 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> ---
>  .../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc  | 7 ---
>  .../WhiskeylakeURvp/OpenBoardPkg.dsc   | 7 ---
>  2 files changed, 8 insertions(+), 6 deletions(-)
> 
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc
> index fb493973e2..ee2aedd978 100644
> --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc
> +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc
> @@ -1,7 +1,7 @@
>  ## @file
> 
>  #  The main build description file for the UpXtreme board.
> 
>  #
> 
> -#  Copyright (c) 2020, Intel Corporation. All rights reserved.
> 
> +#  Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
> 
>  #
> 
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
>  #
> 
> @@ -39,7 +39,8 @@
>#
> 
># Include PCD configuration for this board.
> 
>#
> 
> -  !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
> 
> 
> +  !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
> 
> +
> 
>!include OpenBoardPkgPcd.dsc
> 
>!include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc
> 
> 
> 
> @@ -160,6 +161,7 @@
># Silicon Initialization Package
> 
>###
> 
> 
> SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSiliconInitL
> ib.inf
> 
> +
> ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.i
> nf
> 
> 
> 
>###
> 
># Platform Package
> 
> @@ -172,7 +174,6 @@
> 
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pei
> TestPointCheckLib.inf
> 
>  !endif
> 
> 
> SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheM
> trrLibNull.inf
> 
> -
> ReportCpuHobLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/ReportCpuHob
> Lib/ReportCpuHobLib.inf
> 
> 
> 
>###
> 
># Board Package
> 
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.
> dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.
> dsc
> index 9a1f107faf..b69cc8deb0 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.
> dsc
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.
> dsc
> @@ -1,7 +1,7 @@
>  ## @file
> 
>  #  The main build description file for the WhiskeylakeURvp board.
> 
>  #
> 
> -#  Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
> 
> +#  Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
> 
>  #
> 
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
>  #
> 
> @@ -39,7 +39,8 @@
>#
> 
># Include PCD configuration for this board.
> 
>#
> 
> -  !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
> 
> 
> +  !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
> 
> +
> 
>!include OpenBoardPkgPcd.dsc
> 
>!include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc
> 
> 
> 
> @@ -160,6 +161,7 @@
># Silicon Initialization Package
> 
>###
> 
> 
> SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSiliconInitL
> ib.inf
> 
> +
> ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.i
> nf
> 
> 
> 
>###
> 
># Platform Package
> 
> @@ -172,7 +174,6 @@
> 
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pei
> TestPointCheckLib.inf
> 
>  !endif
> 
> 
> SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheM
> trrLibNull.inf
> 
> -
> ReportCpuHobLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/ReportCpuHob
> Lib/ReportCpuHobLib.inf
> 
> 
> 
>###
> 
># Board Package
> 
> --
> 2.27.0



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Re: [edk2-devel][PATCH v5 4/7] KabylakeOpenBoard: Move ReportCpuHob library path

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 

> -Original Message-
> From: Chuang, SofiaX 
> Sent: Tuesday, May 11, 2021 3:54 AM
> To: devel@edk2.groups.io
> Cc: Chuang, SofiaX ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Jeremy Soller 
> Subject: [edk2-devel][PATCH v5 4/7]
> KabylakeOpenBoard: Move ReportCpuHob library path
> 
> From: SofiaX Chuang 
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298
> 
> Move ReportCpuHob library from MinPlatformPkg to IntelSiliconPkg.
> 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Jeremy Soller 
> ---
>  .../KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc  | 11 ---
>  .../KabylakeRvp3/OpenBoardPkg.dsc | 11 ---
>  2 files changed, 16 insertions(+), 6 deletions(-)
> 
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> index 862e6a6655..302cb679b5 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> @@ -1,7 +1,7 @@
>  ## @file
> 
>  #  The main build description file for the GalagoPro3 board.
> 
>  #
> 
> -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
> 
> +# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
> 
>  #
> 
>  # SPDX-License-Identifier: BSD-2-Clause-Patent
> 
>  #
> 
> @@ -38,7 +38,8 @@
>#
> 
># Include PCD configuration for this board.
> 
>#
> 
> -  !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
> 
> 
> +  !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
> 
> +
> 
>!include OpenBoardPkgPcd.dsc
> 
>!include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc
> 
> 
> 
> @@ -160,7 +161,11 @@
> 
> DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe
> bugLibReportStatusCode.inf
> 
>
> SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
> 
> 
> SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheM
> trrLibNull.inf
> 
> -
> ReportCpuHobLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/ReportCpuHob
> Lib/ReportCpuHobLib.inf
> 
> +
> 
> +  ###
> 
> +  # Silicon Package
> 
> +  ###
> 
> +
> ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.i
> nf
> 
> 
> 
>###
> 
># Platform Package
> 
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> index 0b30da8f96..8523ab3f4f 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> @@ -1,7 +1,7 @@
>  ## @file
> 
>  #  The main build description file for the KabylakeRvp3 board.
> 
>  #
> 
> -# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
> 
> +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
> 
>  #
> 
>  # SPDX-License-Identifier: BSD-2-Clause-Patent
> 
>  #
> 
> @@ -37,7 +37,8 @@
>#
> 
># Include PCD configuration for this board.
> 
>#
> 
> -  !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
> 
> 
> +  !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
> 
> +
> 
>!include OpenBoardPkgPcd.dsc
> 
>!include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc
> 
> 
> 
> @@ -201,6 +202,11 @@
> 
> SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLibN
> ull/SecBoardInitLibNull.inf
> 
> 
> 
>  [LibraryClasses.common.PEIM]
> 
> +  ###
> 
> +  # Silicon Package
> 
> +  ###
> 
> +
> ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.i
> nf
> 
> +
> 
>###
> 
># Platform Package
> 
>###
> 
> @@ -212,7 +218,6 @@
> 
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pei
> TestPointCheckLib.inf
> 
>  !endif
> 
> 
> SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheM
> trrLibNull.inf
> 
> -
> ReportCpuHobLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/ReportCpuHob
> Lib/ReportCpuHobLib.inf
> 
> 
> 
>###
> 
># Board Package
> 
> --
> 2.27.0



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Re: [edk2-devel][PATCH v5 3/7] SimicsOpenBoard: Move ReportCpuHob library path

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 

> -Original Message-
> From: Chuang, SofiaX 
> Sent: Tuesday, May 11, 2021 3:54 AM
> To: devel@edk2.groups.io
> Cc: Chuang, SofiaX ; Agyeman, Prince
> ; Chiu, Chasel 
> Subject: [edk2-devel][PATCH v5 3/7]
> SimicsOpenBoard: Move ReportCpuHob library path
> 
> From: SofiaX Chuang 
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298
> 
> Move ReportCpuHob library from MinPlatformPkg to IntelSiliconPkg.
> 
> Cc: Agyeman Prince 
> Cc: Chasel Chiu 
> ---
>  .../SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc | 11 ---
>  1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git
> a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
> index 77c408a326..93a7d1df55 100644
> --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
> +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
> @@ -1,7 +1,7 @@
>  ## @file
> 
>  #  The main build description file for the X58Ich10 board.
> 
>  #
> 
> -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
> 
> +# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
> 
>  #
> 
>  # SPDX-License-Identifier: BSD-2-Clause-Patent
> 
>  #
> 
> @@ -42,7 +42,8 @@
>DEFINE NETWORK_ISCSI_ENABLE   = FALSE
> 
>DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS = TRUE
> 
> 
> 
> -  !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
> 
> 
> +  !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
> 
> +
> 
>!include $(PROJECT)/OpenBoardPkgPcd.dsc
> 
>!include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc
> 
> 
> 
> @@ -137,6 +138,11 @@
>MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
> 
>VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf
> 
> 
> 
> +  #
> 
> +  # Silicon Package
> 
> +  #
> 
> +
> ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.i
> nf
> 
> +
> 
>#
> 
># Platform Package
> 
>#
> 
> @@ -145,7 +151,6 @@
>  !endif
> 
> 
> TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointLib
> .inf
> 
> 
> SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheM
> trrLib.inf
> 
> -
> ReportCpuHobLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/ReportCpuHob
> Lib/ReportCpuHobLib.inf
> 
> 
> 
>  [LibraryClasses.common.DXE_DRIVER]
> 
> 
> 
> --
> 2.27.0



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Re: [edk2-devel] [PATCH 05/13] MdePkg/Register/Amd: define GHCB macro for the Page State Change

[Laszlo Ersek]

On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
> 
> The Page State Change NAE exit will be used by the SEV-SNP guest to
> request a page state change using the GHCB protocol. See the GHCB
> spec section 4.1.6 and 2.3.1 for more detail on the structure
> definitions.
> 
> Cc: James Bottomley 
> Cc: Min Xu 
> Cc: Jiewen Yao 
> Cc: Tom Lendacky 
> Cc: Jordan Justen 
> Cc: Ard Biesheuvel 
> Cc: Laszlo Ersek 
> Cc: Erdem Aktas 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Signed-off-by: Brijesh Singh 
> ---
>  MdePkg/Include/Register/Amd/Fam17Msr.h | 15 
>  MdePkg/Include/Register/Amd/Ghcb.h | 33 ++
>  2 files changed, 48 insertions(+)
> 
> diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h 
> b/MdePkg/Include/Register/Amd/Fam17Msr.h
> index 542e4cdf4782..62014854d9b7 100644
> --- a/MdePkg/Include/Register/Amd/Fam17Msr.h
> +++ b/MdePkg/Include/Register/Amd/Fam17Msr.h
> @@ -58,6 +58,19 @@ typedef union {
>  UINT64  GuestFrameNumber:52;
>} GhcbGpaRegister;
>  
> +  struct {
> +UINT64 Function:12;
> +UINT64 GuestFrameNumber:40;
> +UINT64 Operation:4;
> +UINT64 Reserved:8;
> +  } SnpPageStateChangeRequest;
> +
> +  struct {
> +UINT32 Function:12;
> +UINT32 Reserved:20;
> +UINT32 ErrorCode;
> +  } SnpPageStateChangeResponse;
> +
>VOID*Ghcb;
>  
>UINT64  GhcbPhysicalAddress;
> @@ -69,6 +82,8 @@ typedef union {
>  #define GHCB_INFO_CPUID_RESPONSE5
>  #define GHCB_INFO_GHCB_GPA_REGISTER_REQUEST 18
>  #define GHCB_INFO_GHCB_GPA_REGISTER_RESPONSE19
> +#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_REQUEST 20
> +#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_RESPONSE21
>  #define GHCB_HYPERVISOR_FEATURES_REQUEST128
>  #define GHCB_HYPERVISOR_FEATURES_RESPONSE   129
>  #define GHCB_INFO_TERMINATE_REQUEST 256
> diff --git a/MdePkg/Include/Register/Amd/Ghcb.h 
> b/MdePkg/Include/Register/Amd/Ghcb.h
> index 326b11479779..a15b4b7e2760 100644
> --- a/MdePkg/Include/Register/Amd/Ghcb.h
> +++ b/MdePkg/Include/Register/Amd/Ghcb.h
> @@ -54,6 +54,7 @@
>  #define SVM_EXIT_NMI_COMPLETE   0x8003ULL
>  #define SVM_EXIT_AP_RESET_HOLD  0x8004ULL
>  #define SVM_EXIT_AP_JUMP_TABLE  0x8005ULL
> +#define SVM_EXIT_SNP_PAGE_STATE_CHANGE  0x8010ULL
>  #define SVM_EXIT_HYPERVISOR_FEATURES0x8000FFFDULL
>  #define SVM_EXIT_UNSUPPORTED0x8000ULL
>  
> @@ -162,4 +163,36 @@ typedef union {
>  #define GHCB_HV_FEATURES_SNP_AP_CREATE
> (GHCB_HV_FEATURES_SNP | BIT1)
>  #define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION 
> (GHCB_HV_FEATURES_SNP_AP_CREATE | BIT2)
>  #define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION_TIMER   
> (GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION | BIT3)
> +
> +//
> +// SNP Page State Change.
> +//
> +// Note that the PSMASH and UNSMASH operations are not supported when using 
> the MSR protocol.
> +//
> +#define SNP_PAGE_STATE_PRIVATE  1
> +#define SNP_PAGE_STATE_SHARED   2
> +#define SNP_PAGE_STATE_PSMASH   3
> +#define SNP_PAGE_STATE_UNSMASH  4
> +
> +typedef struct {
> +  UINT64  CurrentPage:12;
> +  UINT64  GuestFrameNumber:40;
> +  UINT64  Operation:4;
> +  UINT64  PageSize:1;
> +  UINT64  Reserved: 7;

(1) You didn't remove the stray space: my point (6) in
.

I'll fix it up.

Reviewed-by: Laszlo Ersek 

Thanks,
Laszlo

> +} SNP_PAGE_STATE_ENTRY;
> +
> +typedef struct {
> +  UINT16 CurrentEntry;
> +  UINT16 EndEntry;
> +  UINT32 Reserved;
> +} SNP_PAGE_STATE_HEADER;
> +
> +#define SNP_PAGE_STATE_MAX_ENTRY253
> +
> +typedef struct {
> +  SNP_PAGE_STATE_HEADER  Header;
> +  SNP_PAGE_STATE_ENTRY   Entry[SNP_PAGE_STATE_MAX_ENTRY];
> +} SNP_PAGE_STATE_CHANGE_INFO;
> +
>  #endif
> 



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Re: [edk2-devel] [PATCH 04/13] MdePkg/Register/Amd: define GHCB macro for Register GPA structure

[Laszlo Ersek]

On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
> 
> An SEV-SNP guest is required to perform the GHCB GPA registration. See
> the GHCB specification for further details.
> 
> Cc: James Bottomley 
> Cc: Min Xu 
> Cc: Jiewen Yao 
> Cc: Tom Lendacky 
> Cc: Jordan Justen 
> Cc: Ard Biesheuvel 
> Cc: Laszlo Ersek 
> Cc: Erdem Aktas 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Reviewed-by: Laszlo Ersek 
> Signed-off-by: Brijesh Singh 
> ---
>  MdePkg/Include/Register/Amd/Fam17Msr.h | 7 +++
>  1 file changed, 7 insertions(+)

Looks OK, thanks!
Laszlo

> 
> diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h 
> b/MdePkg/Include/Register/Amd/Fam17Msr.h
> index cdb8f588ccf8..542e4cdf4782 100644
> --- a/MdePkg/Include/Register/Amd/Fam17Msr.h
> +++ b/MdePkg/Include/Register/Amd/Fam17Msr.h
> @@ -53,6 +53,11 @@ typedef union {
>  UINT64  Features:52;
>} GhcbHypervisorFeatures;
>  
> +  struct {
> +UINT64  Function:12;
> +UINT64  GuestFrameNumber:52;
> +  } GhcbGpaRegister;
> +
>VOID*Ghcb;
>  
>UINT64  GhcbPhysicalAddress;
> @@ -62,6 +67,8 @@ typedef union {
>  #define GHCB_INFO_SEV_INFO_GET  2
>  #define GHCB_INFO_CPUID_REQUEST 4
>  #define GHCB_INFO_CPUID_RESPONSE5
> +#define GHCB_INFO_GHCB_GPA_REGISTER_REQUEST 18
> +#define GHCB_INFO_GHCB_GPA_REGISTER_RESPONSE19
>  #define GHCB_HYPERVISOR_FEATURES_REQUEST128
>  #define GHCB_HYPERVISOR_FEATURES_RESPONSE   129
>  #define GHCB_INFO_TERMINATE_REQUEST 256
> 



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Re: [edk2-devel] [PATCH 03/13] MdePkg/Register/Amd: define GHCB macros for hypervisor feature detection

[Laszlo Ersek]

On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
> 
> Version 2 of GHCB introduces advertisement of features that are supported
> by the hypervisor. See the GHCB spec section 2.2 for an additional details.
> 
> Cc: James Bottomley 
> Cc: Min Xu 
> Cc: Jiewen Yao 
> Cc: Tom Lendacky 
> Cc: Jordan Justen 
> Cc: Ard Biesheuvel 
> Cc: Laszlo Ersek 
> Cc: Erdem Aktas 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Reviewd-by: Laszlo Ersek 

(1) It's best to use the clipboard for picking up feedback tags -- I
didn't mistype my R-b. (I've checked, plus I use keyboard shortcuts to
insert them; I don't type them out individually).

Anyway I can fix this up upon merge.

> Signed-off-by: Brijesh Singh 
> ---
>  MdePkg/Include/Register/Amd/Fam17Msr.h | 7 +++
>  MdePkg/Include/Register/Amd/Ghcb.h | 8 
>  2 files changed, 15 insertions(+)
> 
> diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h 
> b/MdePkg/Include/Register/Amd/Fam17Msr.h
> index 7368ce7af02a..cdb8f588ccf8 100644
> --- a/MdePkg/Include/Register/Amd/Fam17Msr.h
> +++ b/MdePkg/Include/Register/Amd/Fam17Msr.h
> @@ -48,6 +48,11 @@ typedef union {
>  UINT32  Reserved2:32;
>} GhcbTerminate;
>  
> +  struct {
> +UINT64  Function:12;
> +UINT64  Features:52;
> +  } GhcbHypervisorFeatures;
> +
>VOID*Ghcb;
>  
>UINT64  GhcbPhysicalAddress;
> @@ -57,6 +62,8 @@ typedef union {
>  #define GHCB_INFO_SEV_INFO_GET  2
>  #define GHCB_INFO_CPUID_REQUEST 4
>  #define GHCB_INFO_CPUID_RESPONSE5
> +#define GHCB_HYPERVISOR_FEATURES_REQUEST128
> +#define GHCB_HYPERVISOR_FEATURES_RESPONSE   129
>  #define GHCB_INFO_TERMINATE_REQUEST 256
>  
>  #define GHCB_TERMINATE_GHCB0
> diff --git a/MdePkg/Include/Register/Amd/Ghcb.h 
> b/MdePkg/Include/Register/Amd/Ghcb.h
> index 712dc8e769c0..326b11479779 100644
> --- a/MdePkg/Include/Register/Amd/Ghcb.h
> +++ b/MdePkg/Include/Register/Amd/Ghcb.h
> @@ -54,6 +54,7 @@
>  #define SVM_EXIT_NMI_COMPLETE   0x8003ULL
>  #define SVM_EXIT_AP_RESET_HOLD  0x8004ULL
>  #define SVM_EXIT_AP_JUMP_TABLE  0x8005ULL
> +#define SVM_EXIT_HYPERVISOR_FEATURES0x8000FFFDULL
>  #define SVM_EXIT_UNSUPPORTED0x8000ULL
>  
>  //
> @@ -154,4 +155,11 @@ typedef union {
>  #define GHCB_EVENT_INJECTION_TYPE_EXCEPTION  3
>  #define GHCB_EVENT_INJECTION_TYPE_SOFT_INT   4
>  
> +//
> +// Hypervisor features dections
> +//

(2) The comment style is OK now, but the comment itself has some kind of
typo. I can't really guess what "dections" was supposed to be. I guess I
can replace the comment with "Hypervisor feature sets".

Reviewed-by: Laszlo Ersek 

Thanks
Laszlo

> +#define GHCB_HV_FEATURES_SNP  BIT0
> +#define GHCB_HV_FEATURES_SNP_AP_CREATE
> (GHCB_HV_FEATURES_SNP | BIT1)
> +#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION 
> (GHCB_HV_FEATURES_SNP_AP_CREATE | BIT2)
> +#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION_TIMER   
> (GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION | BIT3)
>  #endif
> 



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Re: [edk2-devel][PATCH v5 2/7] TigerlakeOpenBoard: Move ReportCpuHob library path

[Heng Luo]

Reviewed-by: Heng Luo 

> -Original Message-
> From: Chuang, SofiaX 
> Sent: Tuesday, May 11, 2021 3:54 AM
> To: devel@edk2.groups.io
> Cc: Chuang, SofiaX ; Chaganty, Rangasai V
> ; Desimone, Nathaniel L
> ; Luo, Heng 
> Subject: [edk2-devel][PATCH v5 2/7]
> TigerlakeOpenBoard: Move ReportCpuHob library path
> 
> From: SofiaX Chuang 
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298
> 
> Move ReportCpuHob library from MinPlatformPkg to IntelSiliconPkg.
> 
> Cc: Sai Chaganty 
> Cc: Nate DeSimone 
> Cc: Heng Luo 
> ---
>  .../Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc  | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git
> a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc
> b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc
> index a4265a839c..1adf634034 100644
> --- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc
> +++
> b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc
> @@ -89,7 +89,6 @@
> 
> 
> 
> PciSegmentLib|$(PLATFORM_SI_PACKAGE)/Library/BasePciSegmentMultiSegLib
> Pci/BasePciSegmentMultiSegLibPci.inf
> 
>PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
> 
> -
> ReportCpuHobLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/ReportCpuHob
> Lib/ReportCpuHobLib.inf
> 
> 
> 
>#
> 
># Silicon Init Package
> 
> @@ -115,6 +114,7 @@
>#
> 
># Silicon Init Package
> 
>#
> 
> +
> ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.i
> nf
> 
>!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc
> 
> 
> 
>#
> 
> --
> 2.27.0



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Re: [edk2-devel] [PATCH 02/13] MdePkg/Amd: add white spaces to retain alignment for future expansion

[Laszlo Ersek]

On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
> 
> Version 2 of the GHCB spec introduces several new SNP-specific NAEs.
> Unfortunately, the names for those NAEs break the alignment. Add some
> white spaces so that the SNP support patches do not break the alignment.
> 
> Cc: James Bottomley 
> Cc: Min Xu 
> Cc: Jiewen Yao 
> Cc: Tom Lendacky 
> Cc: Jordan Justen 
> Cc: Ard Biesheuvel 
> Cc: Laszlo Ersek 
> Cc: Erdem Aktas 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Signed-off-by: Brijesh Singh 
> ---
>  MdePkg/Include/Register/Amd/Fam17Msr.h | 10 +-
>  MdePkg/Include/Register/Amd/Ghcb.h | 12 ++--
>  2 files changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h 
> b/MdePkg/Include/Register/Amd/Fam17Msr.h
> index 716d52fd508d..7368ce7af02a 100644
> --- a/MdePkg/Include/Register/Amd/Fam17Msr.h
> +++ b/MdePkg/Include/Register/Amd/Fam17Msr.h
> @@ -53,11 +53,11 @@ typedef union {
>UINT64  GhcbPhysicalAddress;
>  } MSR_SEV_ES_GHCB_REGISTER;
>  
> -#define GHCB_INFO_SEV_INFO 1
> -#define GHCB_INFO_SEV_INFO_GET 2
> -#define GHCB_INFO_CPUID_REQUEST4
> -#define GHCB_INFO_CPUID_RESPONSE   5
> -#define GHCB_INFO_TERMINATE_REQUEST256
> +#define GHCB_INFO_SEV_INFO  1
> +#define GHCB_INFO_SEV_INFO_GET  2
> +#define GHCB_INFO_CPUID_REQUEST 4
> +#define GHCB_INFO_CPUID_RESPONSE5
> +#define GHCB_INFO_TERMINATE_REQUEST 256
>  
>  #define GHCB_TERMINATE_GHCB0
>  #define GHCB_TERMINATE_GHCB_GENERAL0
> diff --git a/MdePkg/Include/Register/Amd/Ghcb.h 
> b/MdePkg/Include/Register/Amd/Ghcb.h
> index ccdb662af7a7..712dc8e769c0 100644
> --- a/MdePkg/Include/Register/Amd/Ghcb.h
> +++ b/MdePkg/Include/Register/Amd/Ghcb.h
> @@ -49,12 +49,12 @@
>  //
>  // VMG Special Exit Codes
>  //
> -#define SVM_EXIT_MMIO_READ  0x8001ULL
> -#define SVM_EXIT_MMIO_WRITE 0x8002ULL
> -#define SVM_EXIT_NMI_COMPLETE   0x8003ULL
> -#define SVM_EXIT_AP_RESET_HOLD  0x8004ULL
> -#define SVM_EXIT_AP_JUMP_TABLE  0x8005ULL
> -#define SVM_EXIT_UNSUPPORTED0x8000ULL
> +#define SVM_EXIT_MMIO_READ  0x8001ULL
> +#define SVM_EXIT_MMIO_WRITE 0x8002ULL
> +#define SVM_EXIT_NMI_COMPLETE   0x8003ULL
> +#define SVM_EXIT_AP_RESET_HOLD  0x8004ULL
> +#define SVM_EXIT_AP_JUMP_TABLE  0x8005ULL
> +#define SVM_EXIT_UNSUPPORTED0x8000ULL
>  
>  //
>  // IOIO Exit Information
> 

Based on Liming's feedback at
,
I'll change the subject of this patch to:

MdePkg/Register/Amd: realign macros with more space for future expansion

(72 chars)

Reviewed-by: Laszlo Ersek 

Thanks,
Laszlo



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Re: [edk2-devel] [PATCH 01/13] MdePkg/Register/Amd: expand the SEV MSR to include the SNP definition

[Laszlo Ersek]

On 05/07/21 22:38, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
> 
> Define the SEV-SNP MSR bits.
> 
> Cc: James Bottomley 
> Cc: Min Xu 
> Cc: Jiewen Yao 
> Cc: Tom Lendacky 
> Cc: Jordan Justen 
> Cc: Ard Biesheuvel 
> Cc: Laszlo Ersek 
> Cc: Erdem Aktas 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Signed-off-by: Brijesh Singh 
> ---
>  MdePkg/Include/Register/Amd/Fam17Msr.h | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h 
> b/MdePkg/Include/Register/Amd/Fam17Msr.h
> index e4db09c5184c..716d52fd508d 100644
> --- a/MdePkg/Include/Register/Amd/Fam17Msr.h
> +++ b/MdePkg/Include/Register/Amd/Fam17Msr.h
> @@ -87,7 +87,12 @@ typedef union {
>  ///
>  UINT32  SevEsBit:1;
>  
> -UINT32  Reserved:30;
> +///
> +/// [Bit 2] Secure Nested Paging (SevSnp) is enabled
> +///
> +UINT32  SevSnpBit:1;
> +
> +UINT32  Reserved2:29;
>} Bits;
>///
>/// All bit fields as a 32-bit value
> 

Reviewed-by: Laszlo Ersek 



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[edk2-devel] [edk2-platforms][PATCH V2 11/11] Platform/Sgi: ACPI CPPC support for RD-N2

[Pranav Madhu]

Enable ACPI CPPC mechanism for RD-N2 as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with SCP to set
the desired performance. RD-N2 platform does not support CPPC revision
1 and below. So update the _OSC method to let OSPM know about this fact.

Signed-off-by: Pranav Madhu 
---
 Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 150 
 1 file changed, 150 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
index 125b20b64cee..a318ef48ded9 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
@@ -29,6 +29,12 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
 Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
   }
+
+  If (And (CAP0, OSC_CAP_CPPC_SUPPORT)) {
+/* CPPC revision 1 and below not supported */
+And (CAP0, Not (OSC_CAP_CPPC_SUPPORT), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+  }
 } Else {
   And (STS0, Not (OSC_STS_MASK), STS0)
   Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
@@ -127,6 +133,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 0)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000500, 0x06000504, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (0)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -145,6 +160,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 1)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000518, 0x0600051C, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (1)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -163,6 +187,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 2)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000530, 0x06000534, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (2)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -181,6 +214,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 3)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000548, 0x0600054C, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (3)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -199,6 +241,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 4)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000560, 0x06000564, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (4)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -217,6 +268,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 5)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000578, 0x0600057C, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (5)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -235,6 +295,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 6)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000590, 0x06000594, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (6)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -253,6 +322,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 7)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x060005A8, 0x060005AC, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (7)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -271,6 +349,15 @@ DefinitionBlock 

[edk2-devel] [edk2-platforms][PATCH V2 10/11] Platform/Sgi: Low Power Idle States for RD-N2

[Pranav Madhu]

RD-N2 platform supports two LPI states, LPI1 (Standby WFI) and LPI3
(Power-down). The cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.

Signed-off-by: Pranav Madhu 
---
 Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 214 
 1 file changed, 214 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
index c5d6f44b3e44..125b20b64cee 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
@@ -13,179 +13,393 @@
 DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
  EFI_ACPI_ARM_OEM_REVISION) {
   Scope (_SB) {
+/* _OSC: Operating System Capabilities */
+Method (_OSC, 4, Serialized) {
+  CreateDWordField (Arg3, 0x00, STS0)
+  CreateDWordField (Arg3, 0x04, CAP0)
+
+  /* Platform-wide Capabilities */
+  If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+/* OSC rev 1 supported, for other version, return failure */
+If (LEqual (Arg1, One)) {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+
+  If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+/* OS initiated LPI not supported */
+And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+  }
+} Else {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+  Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+}
+  } Else {
+And (STS0, Not (OSC_STS_MASK), STS0)
+Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+  }
+
+  Return (Arg3)
+}
+
+Name (CLPI, Package () {  /* LPI for Cluster, support 1 LPI state */
+  0,  // Version
+  0,  // Level Index
+  1,  // Count
+  Package () {// Power Gating state for Cluster
+2500, // Min residency (uS)
+1150, // Wake latency (uS)
+1,// Flags
+1,// Arch Context Flags
+100,  // Residency Counter Frequency
+0,// No Parent State
+0x0020,   // Integer Entry method
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI2-Cluster"
+  },
+})
+
+Name (PLPI, Package () {  /* LPI for Processor, support 2 LPI states */
+  0,  // Version
+  1,  // Level Index
+  2,  // Count
+  Package () {// WFI for CPU
+1,// Min residency (uS)
+1,// Wake latency (uS)
+1,// Flags
+0,// Arch Context lost Flags (no loss)
+100,  // Residency Counter Frequency
+0,// No parent state
+ResourceTemplate () { // Register Entry method
+  Register (FFixedHW,
+32,   // Bit Width
+0,// Bit Offset
+0x,   // Address
+3,// Access Size
+  )
+},
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI1-Core"
+  },
+  Package () {// Power Gating state for CPU
+150,  // Min residency (uS)
+350,  // Wake latency (uS)
+1,// Flags
+1,// Arch Context lost Flags (Core context lost)
+100,  // Residency Counter Frequency
+1,// Parent node can be in any shallower state
+ResourceTemplate () { // Register Entry method
+  Register (FFixedHW,
+32,   // Bit Width
+0,// Bit Offset
+0x4002,   // Address (PwrLvl:core, StateTyp:PwrDn)
+3,// Access Size
+  )
+},
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI3-Core"
+  },
+})
+
 Device (CL00) {   // Cluster 0
   Name (_HID, "ACPI0010")
   Name (_UID, 0)
+  Method (_LPI, 0, NotSerialized) {
+Return (\_SB.CLPI)
+  }
 
   Device (CP00) { // 

[edk2-devel] [edk2-platforms][PATCH V2 09/11] Platform/Sgi: ACPI CPPC support for RD-V1 quad-chip platform

[Pranav Madhu]

Enable ACPI CPPC mechanism for RD-V1 quad-chip platform as defined by
the ACPI specification. The implementation uses AMU registers accessible
as Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with SCP to set the
desired performance. RD-V1 quad-chip platform does not support CPPC
revision 1 and below. So update the _OSC method to let OSPM know about
this fact.

Signed-off-by: Pranav Madhu 
---
 Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 162 
 1 file changed, 162 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
index 82eb91638426..622d522532a3 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
@@ -29,6 +29,12 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
 Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
   }
+
+  If (And (CAP0, OSC_CAP_CPPC_SUPPORT)) {
+/* CPPC revision 1 and below not supported */
+And (CAP0, Not (OSC_CAP_CPPC_SUPPORT), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+  }
 } Else {
   And (STS0, Not (OSC_STS_MASK), STS0)
   Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
@@ -102,6 +108,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 0)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000500, 0x06000504, 20, 130, 130, 65, 65, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (0)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -117,6 +132,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 1)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000518, 0x0600051C, 20, 130, 130, 65, 65, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (1)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -132,6 +156,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 2)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000530, 0x06000534, 20, 130, 130, 65, 65, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (2)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -147,6 +180,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 3)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000548, 0x0600054C, 20, 130, 130, 65, 65, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (3)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -162,6 +204,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 4)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x040006000500, 0x040006000504, 20, 130, 130, 65,
+ 65, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (4)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -177,6 +229,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 5)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x040006000518, 0x04000600051C, 20, 130, 130, 65,
+ 65, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (5)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -192,6 +254,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 6)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x040006000530, 0x040006000534, 20, 130, 130, 65,
+ 65, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (6)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -207,6 +279,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 7)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x040006000548, 0x04000600054C, 20, 130, 130, 65,
+ 65, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+  

[edk2-devel] [edk2-platforms][PATCH V2 08/11] Platform/Sgi: Low Power Idle States for RD-V1 quad-chip platform

[Pranav Madhu]

RD-V1 quad-chip platform supports two LPI states, LPI1 (Standby WFI) and
LPI3 (Power-down). Add idle support for RD-V1 quad-chip platform.

Signed-off-by: Pranav Madhu 
---
 Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 144 
 1 file changed, 144 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
index 16919cc5aaa0..82eb91638426 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
@@ -13,6 +13,86 @@
 DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
  EFI_ACPI_ARM_OEM_REVISION) {
   Scope (_SB) {
+/* _OSC: Operating System Capabilities */
+Method (_OSC, 4, Serialized) {
+  CreateDWordField (Arg3, 0x00, STS0)
+  CreateDWordField (Arg3, 0x04, CAP0)
+
+  /* Platform-wide Capabilities */
+  If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+/* OSC rev 1 supported, for other version, return failure */
+If (LEqual (Arg1, One)) {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+
+  If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+/* OS initiated LPI not supported */
+And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+  }
+} Else {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+  Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+}
+  } Else {
+And (STS0, Not (OSC_STS_MASK), STS0)
+Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+  }
+
+  Return (Arg3)
+}
+
+Name (PLPI, Package () {  /* LPI for Processor, support 2 LPI states */
+  0,  // Version
+  1,  // Level Index
+  2,  // Count
+  Package () {// WFI for CPU
+1,// Min residency (uS)
+1,// Wake latency (uS)
+1,// Flags
+0,// Arch Context lost Flags (no loss)
+100,  // Residency Counter Frequency
+0,// No parent state
+ResourceTemplate () { // Register Entry method
+  Register (FFixedHW,
+32,   // Bit Width
+0,// Bit Offset
+0x,   // Address
+3,// Access Size
+  )
+},
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI1-Core"
+  },
+  Package () {// Power Gating state for CPU
+150,  // Min residency (uS)
+350,  // Wake latency (uS)
+1,// Flags
+1,// Arch Context lost Flags (Core context lost)
+100,  // Residency Counter Frequency
+1,// Parent node can be in any shallower state
+ResourceTemplate () { // Register Entry method
+  Register (FFixedHW,
+32,   // Bit Width
+0,// Bit Offset
+0x4002,   // Address (PwrLvl:core, StateTyp:PwrDn)
+3,// Access Size
+  )
+},
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI3-Core"
+  },
+})
+
 Device (CL00) {   // Cluster 0
   Name (_HID, "ACPI0010")
   Name (_UID, 0)
@@ -21,6 +101,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_HID, "ACPI0007")
 Name (_UID, 0)
 Name (_STA, 0xF)
+
+Method (_LPI, 0, NotSerialized) {
+  Return (\_SB.PLPI)
+}
   }
 }
 
@@ -32,6 +116,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_HID, "ACPI0007")
 Name (_UID, 1)
 Name (_STA, 0xF)
+
+Method (_LPI, 0, NotSerialized) {
+  Return (\_SB.PLPI)
+}
   }
 }
 
@@ -43,6 +131,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_HID, "ACPI0007")
 Name (_UID, 2)
 Name (_STA, 0xF)
+
+Method (_LPI, 0, NotSerialized) {
+  Return (\_SB.PLPI)
+}
   }
 }
 
@@ -54,6 +146,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_HID, "ACPI0007")
 Name (_UID, 3)
 Name (_STA, 0xF)
+
+Method (_LPI, 0, NotSerialized) {
+  Return (\_SB.PLPI)
+}
  

[edk2-devel] [edk2-platforms][PATCH V2 07/11] Platform/Sgi: ACPI CPPC support for RD-V1

[Pranav Madhu]

Enable CPPC mechanism for RD-V1 platform as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with SCP to set
the desired performance. RD-V1 platform does not support CPPC revision
1 and below. So update the _OSC method to let OSPM know about this fact.

Signed-off-by: Pranav Madhu 
---
 Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 166 
 1 file changed, 166 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
index fe33b74e3a5b..0f632673d050 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
@@ -29,6 +29,12 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
 Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
   }
+
+  If (And (CAP0, OSC_CAP_CPPC_SUPPORT)) {
+/* CPPC revision 1 and below not supported */
+And (CAP0, Not (OSC_CAP_CPPC_SUPPORT), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+  }
 } Else {
   And (STS0, Not (OSC_STS_MASK), STS0)
   Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
@@ -101,6 +107,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_HID, "ACPI0007")
 Name (_UID, 0)
 Name (_STA, 0xF)
+
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000500, 0x06000504, 20, 130, 130, 65, 65, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (0)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -115,6 +131,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_HID, "ACPI0007")
 Name (_UID, 1)
 Name (_STA, 0xF)
+
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000518, 0x0600051C, 20, 130, 130, 65, 65, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (1)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -129,6 +155,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_HID, "ACPI0007")
 Name (_UID, 2)
 Name (_STA, 0xF)
+
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000530, 0x06000534, 20, 130, 130, 65, 65, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (2)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -143,6 +179,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_HID, "ACPI0007")
 Name (_UID, 3)
 Name (_STA, 0xF)
+
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000548, 0x0600054C, 20, 130, 130, 65, 65, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (3)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -157,6 +203,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_HID, "ACPI0007")
 Name (_UID, 4)
 Name (_STA, 0xF)
+
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000560, 0x06000564, 20, 130, 130, 65, 65, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (4)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -171,6 +227,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_HID, "ACPI0007")
 Name (_UID, 5)
 Name (_STA, 0xF)
+
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000578, 0x0600057C, 20, 130, 130, 65, 65, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (5)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -185,6 +251,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_HID, "ACPI0007")
 Name (_UID, 6)
 Name (_STA, 0xF)
+
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x06000590, 0x06000594, 20, 130, 130, 65, 65, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (6)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -199,6 +275,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_HID, "ACPI0007")
 Name (_UID, 7)
 Name (_STA, 0xF)
+
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x060005A8, 0x060005AC, 20, 130, 130, 65, 

[edk2-devel] [edk2-platforms][PATCH V2 05/11] Platform/Sgi: Low Power Idle states for RD-V1 platform

[Pranav Madhu]

RD-V1 platform supports 2 LPI states, LPI1 (Standby WFI) and LPI3
(Power-down). Add idle support for RD-V1 platform.

Signed-off-by: Pranav Madhu 
---
 Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 128 
 1 file changed, 128 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
index 05e8601290e2..fe33b74e3a5b 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
@@ -13,6 +13,86 @@
 DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
  EFI_ACPI_ARM_OEM_REVISION) {
   Scope (_SB) {
+/* _OSC: Operating System Capabilities */
+Method (_OSC, 4, Serialized) {
+  CreateDWordField (Arg3, 0x00, STS0)
+  CreateDWordField (Arg3, 0x04, CAP0)
+
+  /* Platform-wide Capabilities */
+  If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+/* OSC rev 1 supported, for other version, return failure */
+If (LEqual (Arg1, One)) {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+
+  If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+/* OS initiated LPI not supported */
+And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+  }
+} Else {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+  Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+}
+  } Else {
+And (STS0, Not (OSC_STS_MASK), STS0)
+Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+  }
+
+  Return (Arg3)
+}
+
+Name (PLPI, Package () {  /* LPI for Processor, support 2 LPI states */
+  0,  // Version
+  1,  // Level Index
+  2,  // Count
+  Package () {// WFI for CPU
+1,// Min residency (uS)
+1,// Wake latency (uS)
+1,// Flags
+0,// Arch Context lost Flags (no loss)
+100,  // Residency Counter Frequency
+0,// No parent state
+ResourceTemplate () { // Register Entry method
+  Register (FFixedHW,
+32,   // Bit Width
+0,// Bit Offset
+0x,   // Address
+3,// Access Size
+  )
+},
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI1-Core"
+  },
+  Package () {// Power Gating state for CPU
+150,  // Min residency (uS)
+350,  // Wake latency (uS)
+1,// Flags
+1,// Arch Context lost Flags (Core context lost)
+100,  // Residency Counter Frequency
+1,// Parent node can be in any shallower state
+ResourceTemplate () { // Register Entry method
+  Register (FFixedHW,
+32,   // Bit Width
+0,// Bit Offset
+0x4002,   // Address (PwrLvl:core, StateTyp:PwrDn)
+3,// Access Size
+  )
+},
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI3-Core"
+  },
+})
+
 Device (CL00) {   // Cluster 0
   Name (_HID, "ACPI0010")
   Name (_UID, 0)
@@ -21,6 +101,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_HID, "ACPI0007")
 Name (_UID, 0)
 Name (_STA, 0xF)
+Method (_LPI, 0, NotSerialized) {
+  Return (\_SB.PLPI)
+}
   }
 }
 
@@ -32,6 +115,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_HID, "ACPI0007")
 Name (_UID, 1)
 Name (_STA, 0xF)
+Method (_LPI, 0, NotSerialized) {
+  Return (\_SB.PLPI)
+}
   }
 }
 
@@ -43,6 +129,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_HID, "ACPI0007")
 Name (_UID, 2)
 Name (_STA, 0xF)
+Method (_LPI, 0, NotSerialized) {
+  Return (\_SB.PLPI)
+}
   }
 }
 
@@ -54,6 +143,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_HID, "ACPI0007")
 Name (_UID, 3)
 Name (_STA, 0xF)
+Method (_LPI, 0, NotSerialized) {
+  Return (\_SB.PLPI)
+}
   }
 }
 
@@ -65,6 +157,9 @@ 

[edk2-devel] [edk2-platforms][PATCH V2 04/11] Platform/Sgi: Low Power Idle States for RD-N1-Edge dual-chip

[Pranav Madhu]

RD-N1-Edge platform in multi chip configuration supports 2 LPI states,
LPI1 (Standby WFI) and LPI3 (Power-down). The cluster supports LPI2
(Power-down) state. The LPI implementation also supports combined power
state for core and cluster.

Signed-off-by: Pranav Madhu 
---
 Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 162 
 1 file changed, 162 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
index 2379f20a79ef..5807658e7815 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
@@ -15,62 +15,194 @@
 DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
  EFI_ACPI_ARM_OEM_REVISION) {
   Scope (_SB) {
+/* _OSC: Operating System Capabilities */
+Method (_OSC, 4, Serialized) {
+  CreateDWordField (Arg3, 0x00, STS0)
+  CreateDWordField (Arg3, 0x04, CAP0)
+
+  /* Platform-wide Capabilities */
+  If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+/* OSC rev 1 supported, for other version, return failure */
+If (LEqual (Arg1, One)) {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+
+  If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+/* OS initiated LPI not supported */
+And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+  }
+} Else {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+  Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+}
+  } Else {
+And (STS0, Not (OSC_STS_MASK), STS0)
+Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+  }
+
+  Return (Arg3)
+}
+
+Name (CLPI, Package () {  /* LPI for Cluster, support 1 LPI state */
+  0,  // Version
+  0,  // Level Index
+  1,  // Count
+  Package () {// Power Gating state for Cluster
+2500, // Min residency (uS)
+1150, // Wake latency (uS)
+1,// Flags
+1,// Arch Context Flags
+100,  // Residency Counter Frequency
+0,// No Parent State
+0x0020,   // Integer Entry method
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI2-Cluster"
+  },
+})
+
+Name (PLPI, Package () {  /* LPI for Processor, support 2 LPI states */
+  0,  // Version
+  1,  // Level Index
+  2,  // Count
+  Package () {// WFI for CPU
+1,// Min residency (uS)
+1,// Wake latency (uS)
+1,// Flags
+0,// Arch Context lost Flags (no loss)
+100,  // Residency Counter Frequency
+0,// No parent state
+ResourceTemplate () { // Register Entry method
+  Register (FFixedHW,
+32,   // Bit Width
+0,// Bit Offset
+0x,   // Address
+3,// Access Size
+  )
+},
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI1-Core"
+  },
+  Package () {// Power Gating state for CPU
+150,  // Min residency (uS)
+350,  // Wake latency (uS)
+1,// Flags
+1,// Arch Context lost Flags (Core context lost)
+100,  // Residency Counter Frequency
+1,// Parent node can be in any shallower state
+ResourceTemplate () { // Register Entry method
+  Register (FFixedHW,
+32,   // Bit Width
+0,// Bit Offset
+0x4002,   // Address (PwrLvl:core, StateTyp:PwrDn)
+3,// Access Size
+  )
+},
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI3-Core"
+  },
+})
+
 /* Chip 0 CPUs */
 Device (CLU0) {   // Cluster 0
   Name (_HID, "ACPI0010")
   Name (_UID, 0)
+  Method (_LPI, 0, 

[edk2-devel] [edk2-platforms][PATCH V2 06/11] Platform/Sgi: Macro definitions for ACPI CPPC

[Pranav Madhu]

Add helper macros required for use with ACPI collaborative processor
performance control (CPPC). This patch adds macros for initializing ACPI
_CPC and _PSD control method. The CPC initializer macro initializes _CPC
control method with revision 3 as specified in Arm FFH specification
1.1. The CPC initilizer exposes the reference performance counter and
delivered perfrmance counter (AMU registers) as FFixedHW registers. The
initilizer also expose the fastchannel memories for performance level
set performance limit set protocols as desired performance register and
performance limited register respectively.

Signed-off-by: Pranav Madhu 
---
 Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 74 
 1 file changed, 74 insertions(+)

diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h 
b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index c23938fe3d4f..7b8c16b172c0 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -432,4 +432,78 @@ typedef struct {
 LineSize  /* Line size in bytes */ 
\
   }
 
+/** Helper macro for CPPC _CPC object initialization. Use of this macro is
+restricted to ASL file and not to TDL file.
+
+@param [in] DesiredPerfReg  Fastchannel address for desired performance
+register.
+@param [in] PerfLimitedReg  Fastchannel address for performance limited
+register.
+@param [in] GranularityMHz  Granularity of the performance scale.
+@param [in] HighestPerf Highest performance in linear scale.
+@param [in] NominalPerf Nominal performance in linear scale.
+@param [in] LowestNonlinearPerf Lowest non-linear performnce in linear
+scale.
+@param [in] LowestPerf  Lowest performance in linear scale.
+@param [in] RefPerf Reference performance in linear scale.
+**/
+#define CPPC_PACKAGE_INIT(DesiredPerfReg, PerfLimitedReg, GranularityMHz,  
\
+  HighestPerf, NominalPerf, LowestNonlinearPerf, LowestPerf, RefPerf)  
\
+  {
\
+23, /* NumEntries */   
\
+3,  /* Revision */ 
\
+HighestPerf,/* Highest Performance */  
\
+NominalPerf,/* Nominal Performance */  
\
+LowestNonlinearPerf,/* Lowest Nonlinear Performance */ 
\
+LowestPerf, /* Lowest Performance */   
\
+/* Guaranteed Performance Register */  
\
+ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) },   
\
+/* Desired Performance Register */ 
\
+ResourceTemplate () { Register (SystemMemory, 32, 0, DesiredPerfReg, 3) }, 
\
+/* Minimum Performance Register */ 
\
+ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) },   
\
+/* Maximum Performance Register */ 
\
+ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) },   
\
+/* Performance Reduction Tolerance Register */ 
\
+ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) },   
\
+/* Time Window Register */ 
\
+ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) },   
\
+/* Counter Wraparound Time */  
\
+ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) },   
\
+/* Reference Performance Counter Register */   
\
+ResourceTemplate () { Register (FFixedHW, 64, 0, 1, 4) },  
\
+/* Delivered Performance Counter Register */   
\
+ResourceTemplate () { Register (FFixedHW, 64, 0, 0, 4) },  
\
+/* Performance Limited Register */ 
\
+ResourceTemplate () { Register (SystemMemory, 32, 0, PerfLimitedReg, 3) }, 
\
+/* CPPC Enable Register */ 
\
+ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) },   
\
+/* Autonomous Selection Enable Register */ 
\
+ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) },   
\
+/* Autonomous Activity Window Register */  
\
+ResourceTemplate () { Register (SystemMemory, 0, 0, 0, 0) },   
\
+/* Energy Performance Preference Register */   
\
+

[edk2-devel] [edk2-platforms][PATCH V2 02/11] Platform/Sgi: Low Power Idle states for SGI-575

[Pranav Madhu]

SGI-575 platform supports 2 LPI states, LPI1 (Standby WFI) and LPI3
(Power-down) and the cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.

Signed-off-by: Pranav Madhu 
---
 Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 132 
 1 file changed, 132 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
index 7390849e6231..e879a681fabf 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
@@ -12,61 +12,193 @@
 
 DefinitionBlock("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", 
EFI_ACPI_ARM_OEM_REVISION) {
   Scope(_SB) {
+/* _OSC: Operating System Capabilities */
+Method (_OSC, 4, Serialized) {
+  CreateDWordField (Arg3, 0x00, STS0)
+  CreateDWordField (Arg3, 0x04, CAP0)
+
+  /* Platform-wide Capabilities */
+  If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+/* OSC rev 1 supported, for other version, return failure */
+If (LEqual (Arg1, One)) {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+
+  If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+/* OS initiated LPI not supported */
+And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+  }
+} Else {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+  Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+}
+  } Else {
+And (STS0, Not (OSC_STS_MASK), STS0)
+Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+  }
+
+  Return (Arg3)
+}
+
+Name (CLPI, Package () {  /* LPI for Cluster, support 1 LPI state */
+  0,  // Version
+  0,  // Level Index
+  1,  // Count
+  Package () {// Power Gating state for Cluster
+2500, // Min residency (uS)
+1150, // Wake latency (uS)
+1,// Flags
+1,// Arch Context Flags
+100,  // Residency Counter Frequency
+0,// No Parent State
+0x0020,   // Integer Entry method
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI2-Cluster"
+  },
+})
+
+Name (PLPI, Package () {  /* LPI for Processor, support 2 LPI states */
+  0,  // Version
+  1,  // Level Index
+  2,  // Count
+  Package () {// WFI for CPU
+1,// Min residency (uS)
+1,// Wake latency (uS)
+1,// Flags
+0,// Arch Context lost Flags (no loss)
+100,  // Residency Counter Frequency
+0,// No parent state
+ResourceTemplate () { // Register Entry method
+  Register (FFixedHW,
+32,   // Bit Width
+0,// Bit Offset
+0x,   // Address
+3,// Access Size
+  )
+},
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI1-Core"
+  },
+  Package () {// Power Gating state for CPU
+150,  // Min residency (uS)
+350,  // Wake latency (uS)
+1,// Flags
+1,// Arch Context lost Flags (Core context lost)
+100,  // Residency Counter Frequency
+1,// Parent node can be in any shallower state
+ResourceTemplate () { // Register Entry method
+  Register (FFixedHW,
+32,   // Bit Width
+0,// Bit Offset
+0x4002,   // Address (PwrLvl:core, StateTyp:PwrDn)
+3,// Access Size
+  )
+},
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI3-Core"
+  },
+})
+
 Device (CLU0) {   // Cluster 0
   Name (_HID, "ACPI0010")
   Name (_UID, 0)
+  Method (_LPI, 0, NotSerialized) {
+Return (\_SB.CLPI)
+  }
 
   Device (CP00) { // A75-0: 

[edk2-devel] [edk2-platforms][PATCH V2 00/11] Enable idle state and CPPC support for RD platform

[Pranav Madhu]

Changes since V1:
- Remove patches that add CPU container object into DSDT
- Addressed comments from Sami

Low Power Idle (LPI) and Collaborative Processor Performance Control
(CPPC) are two power management mechanisms described in ACPI 6.4
specification. OSPM uses the _LPI object to select a local power state
for each level of processor hierarchy in the system. Collaborative
processor performance control (CPPC) defines an abstracted and flexible
mechanism for OSPM to collaborate with an entity in the platform to
manage the performance of a processor. In this patch series, CPPC
support depends on the availability of Activity Monitor Unit (AMU)
extension for CPU performance monitoring as defined in the Arm v8.4
architecture reference manuals. So CPPC is supported for RD-V1 and
RD-N2 platforms.

This patch series adds LPI support for all the Neoverse reference
design platforms. CPPC support is added for RD-V1, RD-V1-MC and
RD-N2 platforms.

This patch series should be applied on top of the patch series
https://edk2.groups.io/g/devel/message/74924

Link to github branch with the patches in this series -
https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rd_power_management


Pranav Madhu (11):
  Platform/Sgi: Macro definitions for ACPI _OSC
  Platform/Sgi: Low Power Idle states for SGI-575
  Platform/Sgi: Low Power Idle states for RD-N1-Edge
  Platform/Sgi: Low Power Idle States for RD-N1-Edge dual-chip
  Platform/Sgi: Low Power Idle states for RD-V1 platform
  Platform/Sgi: Macro definitions for ACPI CPPC
  Platform/Sgi: ACPI CPPC support for RD-V1
  Platform/Sgi: Low Power Idle States for RD-V1 quad-chip platform
  Platform/Sgi: ACPI CPPC support for RD-V1 quad-chip platform
  Platform/Sgi: Low Power Idle States for RD-N2
  Platform/Sgi: ACPI CPPC support for RD-N2

 Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h   |  90 +
 .../ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl   | 132 +++
 .../ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 162 
 Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl  | 364 ++
 Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl  | 294 ++
 .../ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 306 +++
 .../ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 132 +++
 7 files changed, 1480 insertions(+)

-- 
2.17.1



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[edk2-devel] [edk2-platforms][PATCH V2 01/11] Platform/Sgi: Macro definitions for ACPI _OSC

[Pranav Madhu]

Add helper macros required for use with ACPI Operating System
Capabilities (_OSC) control method. The macros for capability DWORD and
return status value DWORD are defined.

Signed-off-by: Pranav Madhu 
---
 Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 16 
 1 file changed, 16 insertions(+)

diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h 
b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index 23e6ee14a761..c23938fe3d4f 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -23,6 +23,22 @@
 #define CORE_COUNT  FixedPcdGet32 (PcdCoreCount)
 #define CLUSTER_COUNT   FixedPcdGet32 (PcdClusterCount)
 
+// ACPI OSC Status bits
+#define OSC_STS_BIT0_RES  (1U << 0)
+#define OSC_STS_FAILURE   (1U << 1)
+#define OSC_STS_UNRECOGNIZED_UUID (1U << 2)
+#define OSC_STS_UNRECOGNIZED_REV  (1U << 3)
+#define OSC_STS_CAPABILITY_MASKED (1U << 4)
+#define OSC_STS_MASK  (OSC_STS_BIT0_RES  | \
+   OSC_STS_FAILURE   | \
+   OSC_STS_UNRECOGNIZED_UUID | \
+   OSC_STS_UNRECOGNIZED_REV  | \
+   OSC_STS_CAPABILITY_MASKED)
+
+// ACPI OSC for Platform-Wide Capability
+#define OSC_CAP_CPPC_SUPPORT  (1U << 5)
+#define OSC_CAP_OS_INITIATED_LPI  (1U << 8)
+
 #pragma pack(1)
 // PPTT processor core structure
 typedef struct {
-- 
2.17.1



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[edk2-devel] [edk2-platforms][PATCH V2 03/11] Platform/Sgi: Low Power Idle states for RD-N1-Edge

[Pranav Madhu]

RD-N1-Edge platform supports 2 LPI states, LPI1 (Standby WFI) and LPI3
(Power-down) and the cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.

Signed-off-by: Pranav Madhu 
---
 Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl | 132 
 1 file changed, 132 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
index b88344c3a7ba..a2258f61aeca 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
@@ -13,61 +13,193 @@
 DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
  EFI_ACPI_ARM_OEM_REVISION) {
   Scope (_SB) {
+/* _OSC: Operating System Capabilities */
+Method (_OSC, 4, Serialized) {
+  CreateDWordField (Arg3, 0x00, STS0)
+  CreateDWordField (Arg3, 0x04, CAP0)
+
+  /* Platform-wide Capabilities */
+  If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+/* OSC rev 1 supported, for other version, return failure */
+If (LEqual (Arg1, One)) {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+
+  If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+/* OS initiated LPI not supported */
+And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+  }
+} Else {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+  Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+}
+  } Else {
+And (STS0, Not (OSC_STS_MASK), STS0)
+Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+  }
+
+  Return (Arg3)
+}
+
+Name (CLPI, Package () {  /* LPI for Cluster, support 1 LPI state */
+  0,  // Version
+  0,  // Level Index
+  1,  // Count
+  Package () {// Power Gating state for Cluster
+2500, // Min residency (uS)
+1150, // Wake latency (uS)
+1,// Flags
+1,// Arch Context Flags
+100,  // Residency Counter Frequency
+0,// No Parent State
+0x0020,   // Integer Entry method
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI2-Cluster"
+  },
+})
+
+Name (PLPI, Package () {  /* LPI for Processor, support 2 LPI states */
+  0,  // Version
+  1,  // Level Index
+  2,  // Count
+  Package () {// WFI for CPU
+1,// Min residency (uS)
+1,// Wake latency (uS)
+1,// Flags
+0,// Arch Context lost Flags (no loss)
+100,  // Residency Counter Frequency
+0,// No parent state
+ResourceTemplate () { // Register Entry method
+  Register (FFixedHW,
+32,   // Bit Width
+0,// Bit Offset
+0x,   // Address
+3,// Access Size
+  )
+},
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI1-Core"
+  },
+  Package () {// Power Gating state for CPU
+150,  // Min residency (uS)
+350,  // Wake latency (uS)
+1,// Flags
+1,// Arch Context lost Flags (Core context lost)
+100,  // Residency Counter Frequency
+1,// Parent node can be in any shallower state
+ResourceTemplate () { // Register Entry method
+  Register (FFixedHW,
+32,   // Bit Width
+0,// Bit Offset
+0x4002,   // Address (PwrLvl:core, StateTyp:PwrDn)
+3,// Access Size
+  )
+},
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI3-Core"
+  },
+})
+
 Device (CLU0) {   // Cluster 0
   Name (_HID, "ACPI0010")
   Name (_UID, 0)
+  Method (_LPI, 0, NotSerialized) {
+Return (\_SB.CLPI)
+  }
 
   

[edk2-devel][PATCH v5 7/7] CometlakeOpenBoard: Move ReportCpuHob library path

[sofiax . chuang]

From: SofiaX Chuang 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298

Move ReportCpuHob library from MinPlatformPkg to IntelSiliconPkg.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Rangasai V Chaganty 
Cc: Deepika Kethi Reddy 
Cc: Kathappan Esakkithevar 
---
 .../CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc  | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git 
a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc 
b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc
index 6de834565a..44a1bd54d6 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  The main build description file for the CometlakeURvp board.
 #
-#  Copyright (c) 2020, Intel Corporation. All rights reserved.
+#  Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -161,6 +161,7 @@
   # Silicon Initialization Package
   ###
   
SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
+  ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf
 
   ###
   # Platform Package
@@ -173,7 +174,6 @@
   
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
 !endif
   
SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf
-  
ReportCpuHobLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf
 
   ###
   # Board Package
-- 
2.27.0



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[edk2-devel][PATCH v5 4/7] KabylakeOpenBoard: Move ReportCpuHob library path

[sofiax . chuang]

From: SofiaX Chuang 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3298

Move ReportCpuHob library from MinPlatformPkg to IntelSiliconPkg.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Jeremy Soller 
---
 .../KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc  | 11 ---
 .../KabylakeRvp3/OpenBoardPkg.dsc | 11 ---
 2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc 
b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
index 862e6a6655..302cb679b5 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
@@ -1,7 +1,7 @@
 ## @file

 #  The main build description file for the GalagoPro3 board.

 #

-# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.

+# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.

 #

 # SPDX-License-Identifier: BSD-2-Clause-Patent

 #

@@ -38,7 +38,8 @@
   #

   # Include PCD configuration for this board.

   #

-  !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc

+  !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc

+

   !include OpenBoardPkgPcd.dsc

   !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc

 

@@ -160,7 +161,11 @@
   
DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf

   SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf

   
SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf

-  
ReportCpuHobLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf

+

+  ###

+  # Silicon Package

+  ###

+  ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf

 

   ###

   # Platform Package

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc 
b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
index 0b30da8f96..8523ab3f4f 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
@@ -1,7 +1,7 @@
 ## @file

 #  The main build description file for the KabylakeRvp3 board.

 #

-# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.

+# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.

 #

 # SPDX-License-Identifier: BSD-2-Clause-Patent

 #

@@ -37,7 +37,8 @@
   #

   # Include PCD configuration for this board.

   #

-  !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc

+  !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc

+

   !include OpenBoardPkgPcd.dsc

   !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc

 

@@ -201,6 +202,11 @@
   
SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf

 

 [LibraryClasses.common.PEIM]

+  ###

+  # Silicon Package

+  ###

+  ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf

+

   ###

   # Platform Package

   ###

@@ -212,7 +218,6 @@
   
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf

 !endif

   
SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf

-  
ReportCpuHobLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf

 

   ###

   # Board Package

-- 
2.27.0



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