Re: [edk2-devel] GitHub PR Code Review process now active

[Dhaval Sharma]

Hi Michael,
Just to clarify my understanding. Once a PR is submitted (or it moves from 
draft to regular PR state), it automatically gets reviewers assigned? I 
submitted this one https://github.com/tianocore/edk2/pull/5802 and was 
wondering if I should be sending maintainers an email or be assured that they 
have seen it in which case I would not like to bother them.


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#119664): https://edk2.groups.io/g/devel/message/119664
Mute This Topic: https://groups.io/mt/106355103/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v1 1/1] MdeModulePkg: Avoid efi memory allocation for SP type

[Dhaval Sharma]

I already sent out an update yesterday. PTAL when you get a chance. Thanks!

On Sat, Jun 15, 2024 at 10:24 AM Kinney, Michael D <
michael.d.kin...@intel.com> wrote:

> Liming,
>
> It is here, but needs some commit message updates
>
> https://github.com/tianocore/edk2/pull/5760
>
> Mike
>
> > -Original Message-
> > From: devel@edk2.groups.io  On Behalf Of
> gaoliming via
> > groups.io
> > Sent: Friday, June 14, 2024 8:05 PM
> > To: devel@edk2.groups.io; dha...@rivosinc.com
> > Subject: 回复: [edk2-devel] [PATCH v1 1/1] MdeModulePkg: Avoid efi memory
> > allocation for SP type
> >
> > Can you create pull request for this change? I will add my review for it.
> >
> > > -邮件原件-
> > > 发件人: devel@edk2.groups.io  代表 Dhaval Sharma
> > > 发送时间: 2024年6月11日 12:09
> > > 收件人: devel@edk2.groups.io
> > > 抄送: Liming Gao 
> > > 主题: [edk2-devel] [PATCH v1 1/1] MdeModulePkg: Avoid efi memory
> > allocation
> > > for SP type
> > >
> > > Most of the times it is desirable not to use special purpose
> > > memory for regular edk2 usages. That memory (HBm/CXL) are
> > > either meant for special purposes or are less reliable to
> > > be used. So avoid using them as long as possible. We could
> > > also introduce PCD for this control.
> > >
> > > Cc: Liming Gao 
> > > Signed-off-by: Dhaval Sharma 
> > > ---
> > >  MdeModulePkg/Core/Dxe/Mem/Page.c | 7 +++
> > >  1 file changed, 7 insertions(+)
> > >
> > > diff --git a/MdeModulePkg/Core/Dxe/Mem/Page.c
> > > b/MdeModulePkg/Core/Dxe/Mem/Page.c
> > > index 5a51d9df1a29..e4daa741b971 100644
> > > --- a/MdeModulePkg/Core/Dxe/Mem/Page.c
> > > +++ b/MdeModulePkg/Core/Dxe/Mem/Page.c
> > > @@ -1183,6 +1183,13 @@ CoreFindFreePagesI (
> > >continue;
> > >
> > >  }
> > >
> > >
> > >
> > > +//
> > >
> > > +// Don't allocate out of Special-Purpose memory.
> > >
> > > +//
> > >
> > > +if ((Entry->Attribute & EFI_MEMORY_SP) != 0) {
> > >
> > > +  continue;
> > >
> > > +}
> > >
> > > +
> > >
> > >  DescStart = Entry->Start;
> > >
> > >  DescEnd   = Entry->End;
> > >
> > >
> > >
> > > --
> > > 2.40.1
> > >
> > >
> > >
> > > -=-=-=-=-=-=
> > > Groups.io Links: You receive all messages sent to this group.
> > > View/Reply Online (#119545):
> https://edk2.groups.io/g/devel/message/119545
> > > Mute This Topic: https://groups.io/mt/106607739/4905953
> > > Group Owner: devel+ow...@edk2.groups.io
> > > Unsubscribe: https://edk2.groups.io/g/devel/unsub
> > > [gaolim...@byosoft.com.cn]
> > > -=-=-=-=-=-=
> > >
> >
> >
> >
> >
> >
> > 
> >
>
>

-- 
Thanks!
=D


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#119607): https://edk2.groups.io/g/devel/message/119607
Mute This Topic: https://groups.io/mt/106683481/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v1 1/1] MdeModulePkg: Avoid efi memory allocation for SP type

[Dhaval Sharma]

Most of the times it is desirable not to use special purpose
memory for regular edk2 usages. That memory (HBm/CXL) are
either meant for special purposes or are less reliable to
be used. So avoid using them as long as possible. We could
also introduce PCD for this control.

Cc: Liming Gao 
Signed-off-by: Dhaval Sharma 
---
 MdeModulePkg/Core/Dxe/Mem/Page.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/MdeModulePkg/Core/Dxe/Mem/Page.c b/MdeModulePkg/Core/Dxe/Mem/Page.c
index 5a51d9df1a29..e4daa741b971 100644
--- a/MdeModulePkg/Core/Dxe/Mem/Page.c
+++ b/MdeModulePkg/Core/Dxe/Mem/Page.c
@@ -1183,6 +1183,13 @@ CoreFindFreePagesI (
   continue;
 }
 
+//
+// Don't allocate out of Special-Purpose memory.
+//
+if ((Entry->Attribute & EFI_MEMORY_SP) != 0) {
+  continue;
+}
+
 DescStart = Entry->Start;
 DescEnd   = Entry->End;
 
-- 
2.40.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#119545): https://edk2.groups.io/g/devel/message/119545
Mute This Topic: https://groups.io/mt/106607739/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v1 0/1] Avoid EFI memory alloc from SP_MEMORY

[Dhaval Sharma]

Most of the times it is desirable not to use special purpose
memory for regular edk2 usages. That memory (HBm/CXL) are
either meant for special purposes or are less reliable to
be used. So avoid using them as long as possible. We could
also introduce PCD for this control.

https://github.com/tianocore/edk2/pull/5760

Dhaval (1):
  MdeModulePkg: Avoid efi memory allocation for SP type

 MdeModulePkg/Core/Dxe/Mem/Page.c | 7 +++
 1 file changed, 7 insertions(+)

-- 
2.40.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#119544): https://edk2.groups.io/g/devel/message/119544
Mute This Topic: https://groups.io/mt/106607737/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v1 1/1] UefiPayloadPkg: Enable UPL FIT build config from cmdline

[Dhaval Sharma]

Provide commandline configuration to select proper platform file.

Cc: Gua Guo 
Cc: Guo Dong 
Cc: James Lu 
Cc: Sean Rhodes 

Signed-off-by: Dhaval Sharma 
---
 UefiPayloadPkg/UniversalPayloadBuild.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/UefiPayloadPkg/UniversalPayloadBuild.py 
b/UefiPayloadPkg/UniversalPayloadBuild.py
index 0423e6da17ff..e2d2e3ffbd1f 100644
--- a/UefiPayloadPkg/UniversalPayloadBuild.py
+++ b/UefiPayloadPkg/UniversalPayloadBuild.py
@@ -112,6 +112,7 @@ def RunCommand(cmd):
 raise Exception("ERROR: when run command: %s"%cmd)
 
 def BuildUniversalPayload(Args):
+DscPath = os.path.normpath(Args.DscPath)
 BuildTarget = Args.Target
 ToolChain = Args.ToolChain
 Quiet = "--quiet"  if Args.Quiet else ""
@@ -140,7 +141,6 @@ def BuildUniversalPayload(Args):
 
 EntryOutputDir = os.path.join(BuildDir, "{}_{}".format (BuildTarget, 
PayloadEntryToolChain), 
os.path.normpath("{}/UefiPayloadPkg/UefiPayloadEntry/{}/DEBUG/{}.dll".format 
(Args.Arch, UpldEntryFile, UpldEntryFile)))
 EntryModuleInf = 
os.path.normpath("UefiPayloadPkg/UefiPayloadEntry/{}.inf".format 
(UpldEntryFile))
-DscPath = os.path.normpath("UefiPayloadPkg/UefiPayloadPkg.dsc")
 DxeFvOutputDir = os.path.join(BuildDir, "{}_{}".format (BuildTarget, 
ToolChain), os.path.normpath("FV/DXEFV.Fv"))
 BdsFvOutputDir = os.path.join(BuildDir, "{}_{}".format (BuildTarget, 
ToolChain), os.path.normpath("FV/BDSFV.Fv"))
 NetworkFvOutputDir = os.path.join(BuildDir, "{}_{}".format (BuildTarget, 
ToolChain), os.path.normpath("FV/NETWORKFV.Fv"))
@@ -321,6 +321,7 @@ def main():
 parser.add_argument("-af", "--AddFv", type=ValidateAddFv, action='append', 
help='Add or replace specific FV into payload, Ex: uefi_fv=XXX.fv')
 parser.add_argument("-f", "--Fit", action='store_true', help='Build 
UniversalPayload file as UniversalPayload.fit', default=False)
 parser.add_argument('-l', "--LoadAddress", type=int, help='Specify payload 
load address', default =0x00080)
+parser.add_argument('-c', '--DscPath', type=str, required=True, help='Path 
to the DSC file')
 
 args = parser.parse_args()
 
-- 
2.40.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#119538): https://edk2.groups.io/g/devel/message/119538
Mute This Topic: https://groups.io/mt/106595353/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v3 1/1] MdeModulePkg: Add the EFI_RESOURCE_ATTRIBUTE_SPECIAL_PURPOSE attribute

[Dhaval Sharma]

Related to this, I also faced this issue where in order to prevent edk2 from 
allocating this memory I had to modify CoreFindFreePagesI
//
// Don't allocate out of Special-Purpose memory.
//
if ((Entry->Attribute & EFI_MEMORY_SP) != 0) {
continue;
}
Can't we add PCD based logic here to selectively NOT use SP memory for edk2 
allocations? I think "reserved-memory" attr does not work well because it would 
force OS/drivers not to use it. Which is not what we want. We really want 
special drivers to make use of it.


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#119519): https://edk2.groups.io/g/devel/message/119519
Mute This Topic: https://groups.io/mt/106165072/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v4 6/6] UefiPayloadPkg: Update UefiPayload driver for FDT support.

[Dhaval Sharma]

I also believe this code needs to go through crustify etc to ensure it
follows all edk2 standards?

On Mon, Jun 3, 2024 at 4:57 PM Dhaval Sharma  wrote:

> BuildFitLoadablesFvHob:
>
>- Fdt variable is not initialized.
>- It ONLY gets initialized if GuidHob is found. What if it is not
>found?
>- FdtCheckHeader still evaluating it?
>
>
> On Mon, Jun 3, 2024 at 7:49 AM Linus Liu  wrote:
>
>> Add FDT detection and comsume FDT when needed.
>> Move some x86 specific function in the x86 folder.
>> Create HandOffHob via FDT memory node.
>>
>> Cc: Benny Lin 
>> Cc: Gua Guo 
>> Cc: Chasel Chiu 
>> Cc: James Lu 
>> Cc: Dhaval Sharma 
>>
>> Signed-off-by: Linus Liu 
>> ---
>>  UefiPayloadPkg/UefiPayloadEntry/FitUniversalPayloadEntry.c
>>  | 428 +---
>>  UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c
>>  |  12 +
>>  UefiPayloadPkg/UefiPayloadEntry/Ia32/{DxeLoadFunc.c => DxeLoadFuncFit.c}
>> |  32 +-
>>  UefiPayloadPkg/UefiPayloadEntry/MemoryAllocation.c
>>  |  50 +++
>>  UefiPayloadPkg/UefiPayloadEntry/PrintHob.c
>>  |   6 +-
>>  UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c
>> |   6 -
>>  UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c
>> |  12 +
>>  UefiPayloadPkg/UefiPayloadEntry/X64/{DxeLoadFunc.c => DxeLoadFuncFit.c}
>> |  31 +-
>>  UefiPayloadPkg/UefiPayloadEntry/FitUniversalPayloadEntry.inf
>>  |  20 +-
>>  UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h
>>  |  68 
>>  UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
>> |  16 +-
>>  UefiPayloadPkg/UefiPayloadPkg.dsc
>> |  29 +-
>>  12 files changed, 443 insertions(+), 267 deletions(-)
>>
>> diff --git a/UefiPayloadPkg/UefiPayloadEntry/FitUniversalPayloadEntry.c
>> b/UefiPayloadPkg/UefiPayloadEntry/FitUniversalPayloadEntry.c
>> index eb0b325369a0..813d656950d1 100644
>> --- a/UefiPayloadPkg/UefiPayloadEntry/FitUniversalPayloadEntry.c
>> +++ b/UefiPayloadPkg/UefiPayloadEntry/FitUniversalPayloadEntry.c
>> @@ -6,6 +6,8 @@
>>  #include "UefiPayloadEntry.h"
>>  #include 
>>  #include 
>> +#include 
>> +#include 
>>
>>  #define MEMORY_ATTRIBUTE_MASK  (EFI_RESOURCE_ATTRIBUTE_PRESENT
>>|\
>>
>> EFI_RESOURCE_ATTRIBUTE_INITIALIZED | \
>> @@ -23,6 +25,15 @@
>>
>> EFI_RESOURCE_ATTRIBUTE_INITIALIZED | \
>> EFI_RESOURCE_ATTRIBUTE_TESTED
>>   )
>>
>> +EFI_MEMORY_TYPE_INFORMATION  mDefaultMemoryTypeInformation[] = {
>> +  { EfiACPIReclaimMemory,   FixedPcdGet32
>> (PcdMemoryTypeEfiACPIReclaimMemory)   },
>> +  { EfiACPIMemoryNVS,   FixedPcdGet32
>> (PcdMemoryTypeEfiACPIMemoryNVS)   },
>> +  { EfiReservedMemoryType,  FixedPcdGet32
>> (PcdMemoryTypeEfiReservedMemoryType)  },
>> +  { EfiRuntimeServicesData, FixedPcdGet32
>> (PcdMemoryTypeEfiRuntimeServicesData) },
>> +  { EfiRuntimeServicesCode, FixedPcdGet32
>> (PcdMemoryTypeEfiRuntimeServicesCode) },
>> +  { EfiMaxMemoryType,   0
>>}
>> +};
>> +
>>  extern VOID  *mHobList;
>>
>>  CHAR8  *mLineBuffer = NULL;
>> @@ -36,6 +47,78 @@ PrintHob (
>>IN CONST VOID  *HobStart
>>);
>>
>> +/**
>> +  Add HOB into HOB list
>> +  @param[in]  HobThe HOB to be added into the HOB list.
>> +**/
>> +VOID
>> +AddNewHob (
>> +  IN EFI_PEI_HOB_POINTERS  *Hob
>> +  );
>> +
>> +/**
>> +  Found the Resource Descriptor HOB that contains a range (Base, Top)
>> +  @param[in] HobListHob start address
>> +  @param[in] Base   Memory start address
>> +  @param[in] TopMemory end address.
>> +  @retval The pointer to the Resource Descriptor HOB.
>> +**/
>> +EFI_HOB_RESOURCE_DESCRIPTOR *
>> +FindResourceDescriptorByRange (
>> +  IN VOID  *HobList,
>> +  IN EFI_PHYSICAL_ADDRESS  Base,
>> +  IN EFI_PHYSICAL_ADDRESS  Top
>> +  );
>> +
>> +/**
>> +  Find the highest below 4G memory resource descriptor, except the input
>> Resource Descriptor.
>> +  @param[in] HobList Hob start address
>> +  @param[in] MinimalNeededSize   Minimal needed size.
>> +  @param[in] ExceptResourceHob   Ignore this Resource Descriptor.
>> +  @retval The pointer to the Resource Descriptor HOB.
>> +**/
>> +EFI_HOB_RESOURCE_DESCRIPTOR *
>> +FindAnotherHighestBelow4GResourceDescriptor (
>> +  IN VOID *HobList,
>> +  IN UIN

Re: [edk2-devel] [PATCH v4 6/6] UefiPayloadPkg: Update UefiPayload driver for FDT support.

[Dhaval Sharma]

BuildFitLoadablesFvHob:

   - Fdt variable is not initialized.
   - It ONLY gets initialized if GuidHob is found. What if it is not found?
   - FdtCheckHeader still evaluating it?


On Mon, Jun 3, 2024 at 7:49 AM Linus Liu  wrote:

> Add FDT detection and comsume FDT when needed.
> Move some x86 specific function in the x86 folder.
> Create HandOffHob via FDT memory node.
>
> Cc: Benny Lin 
> Cc: Gua Guo 
> Cc: Chasel Chiu 
> Cc: James Lu 
> Cc: Dhaval Sharma 
>
> Signed-off-by: Linus Liu 
> ---
>  UefiPayloadPkg/UefiPayloadEntry/FitUniversalPayloadEntry.c
>  | 428 +---
>  UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c
>  |  12 +
>  UefiPayloadPkg/UefiPayloadEntry/Ia32/{DxeLoadFunc.c => DxeLoadFuncFit.c}
> |  32 +-
>  UefiPayloadPkg/UefiPayloadEntry/MemoryAllocation.c
>  |  50 +++
>  UefiPayloadPkg/UefiPayloadEntry/PrintHob.c
>  |   6 +-
>  UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c
> |   6 -
>  UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c
> |  12 +
>  UefiPayloadPkg/UefiPayloadEntry/X64/{DxeLoadFunc.c => DxeLoadFuncFit.c}
> |  31 +-
>  UefiPayloadPkg/UefiPayloadEntry/FitUniversalPayloadEntry.inf
>  |  20 +-
>  UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h
>  |  68 
>  UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
> |  16 +-
>  UefiPayloadPkg/UefiPayloadPkg.dsc
> |  29 +-
>  12 files changed, 443 insertions(+), 267 deletions(-)
>
> diff --git a/UefiPayloadPkg/UefiPayloadEntry/FitUniversalPayloadEntry.c
> b/UefiPayloadPkg/UefiPayloadEntry/FitUniversalPayloadEntry.c
> index eb0b325369a0..813d656950d1 100644
> --- a/UefiPayloadPkg/UefiPayloadEntry/FitUniversalPayloadEntry.c
> +++ b/UefiPayloadPkg/UefiPayloadEntry/FitUniversalPayloadEntry.c
> @@ -6,6 +6,8 @@
>  #include "UefiPayloadEntry.h"
>  #include 
>  #include 
> +#include 
> +#include 
>
>  #define MEMORY_ATTRIBUTE_MASK  (EFI_RESOURCE_ATTRIBUTE_PRESENT
>  |\
>
> EFI_RESOURCE_ATTRIBUTE_INITIALIZED | \
> @@ -23,6 +25,15 @@
> EFI_RESOURCE_ATTRIBUTE_INITIALIZED
> | \
> EFI_RESOURCE_ATTRIBUTE_TESTED
> )
>
> +EFI_MEMORY_TYPE_INFORMATION  mDefaultMemoryTypeInformation[] = {
> +  { EfiACPIReclaimMemory,   FixedPcdGet32
> (PcdMemoryTypeEfiACPIReclaimMemory)   },
> +  { EfiACPIMemoryNVS,   FixedPcdGet32
> (PcdMemoryTypeEfiACPIMemoryNVS)   },
> +  { EfiReservedMemoryType,  FixedPcdGet32
> (PcdMemoryTypeEfiReservedMemoryType)  },
> +  { EfiRuntimeServicesData, FixedPcdGet32
> (PcdMemoryTypeEfiRuntimeServicesData) },
> +  { EfiRuntimeServicesCode, FixedPcdGet32
> (PcdMemoryTypeEfiRuntimeServicesCode) },
> +  { EfiMaxMemoryType,   0
>}
> +};
> +
>  extern VOID  *mHobList;
>
>  CHAR8  *mLineBuffer = NULL;
> @@ -36,6 +47,78 @@ PrintHob (
>IN CONST VOID  *HobStart
>);
>
> +/**
> +  Add HOB into HOB list
> +  @param[in]  HobThe HOB to be added into the HOB list.
> +**/
> +VOID
> +AddNewHob (
> +  IN EFI_PEI_HOB_POINTERS  *Hob
> +  );
> +
> +/**
> +  Found the Resource Descriptor HOB that contains a range (Base, Top)
> +  @param[in] HobListHob start address
> +  @param[in] Base   Memory start address
> +  @param[in] TopMemory end address.
> +  @retval The pointer to the Resource Descriptor HOB.
> +**/
> +EFI_HOB_RESOURCE_DESCRIPTOR *
> +FindResourceDescriptorByRange (
> +  IN VOID  *HobList,
> +  IN EFI_PHYSICAL_ADDRESS  Base,
> +  IN EFI_PHYSICAL_ADDRESS  Top
> +  );
> +
> +/**
> +  Find the highest below 4G memory resource descriptor, except the input
> Resource Descriptor.
> +  @param[in] HobList Hob start address
> +  @param[in] MinimalNeededSize   Minimal needed size.
> +  @param[in] ExceptResourceHob   Ignore this Resource Descriptor.
> +  @retval The pointer to the Resource Descriptor HOB.
> +**/
> +EFI_HOB_RESOURCE_DESCRIPTOR *
> +FindAnotherHighestBelow4GResourceDescriptor (
> +  IN VOID *HobList,
> +  IN UINTNMinimalNeededSize,
> +  IN EFI_HOB_RESOURCE_DESCRIPTOR  *ExceptResourceHob
> +  );
> +
> +/**
> +  Check the HOB and decide if it is need inside Payload
> +  Payload maintainer may make decision which HOB is need or needn't
> +  Then add the check logic in the function.
> +  @param[in] Hob The HOB to check
> +  @retval TRUE  If HOB is need inside Payload
> +  @retval FALSE If HOB is needn't inside Payload
> +**/
> +BOOLEAN
> +FitIsHobNeed (
> +  EFI_PEI_HOB_POINTERS  Hob
> +  );
> +
> +/**
> +  Check the HOB and decide if it is need 

Re: [edk2-devel] [edk2-platforms][PATCH v3 1/5] MdeModulePkg: Allow dynamic generation of HEST ACPI table

[Dhaval Sharma]

Hi,
Is there any plan to upstream these HEST/ACPI patches? They seem to be arch 
agnostic.


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#117526): https://edk2.groups.io/g/devel/message/117526
Mute This Topic: https://groups.io/mt/85104605/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v1 1/1] UefiPayloadPkg: Make Dsc accomodative of other archs

[Dhaval Sharma]

Current DSC files contains a lot of files which are
specific to X86 arch. Need to move around files under
arch specific sections.

Cc: Guo Dong 
Cc: Sean Rhodes 
Cc: James Lu 
Cc: Gua Guo 
Signed-off-by: Dhaval Sharma 
Reviewed-by: Gua Guo 
---

Notes:
v1:
- Updated RB tab

 UefiPayloadPkg/UefiPayloadPkg.dsc | 48 +++-
 1 file changed, 27 insertions(+), 21 deletions(-)

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc 
b/UefiPayloadPkg/UefiPayloadPkg.dsc
index 95417cec6aff..433fb51a5695 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -259,24 +259,6 @@ [LibraryClasses]
   BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
   
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
   
FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf
-
-  #
-  # CPU
-  #
-  MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
-  LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
-  MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf
-  CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf
-  SmmCpuSyncLib|UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf
-
-  #
-  # Platform
-  #
-!if $(CPU_TIMER_LIB_ENABLE) == TRUE && $(UNIVERSAL_PAYLOAD) == TRUE
-  TimerLib|UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
-!else
-  TimerLib|UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf
-!endif
   ResetSystemLib|UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf
 !if $(USE_CBMEM_FOR_CONSOLE) == TRUE
   SerialPortLib|UefiPayloadPkg/Library/CbSerialPortLib/CbSerialPortLib.inf
@@ -339,6 +321,22 @@ [LibraryClasses.common]
   BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.inf
 !endif
 
+[LibraryClasses.X64]
+  #
+  # CPU
+  #
+  MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
+  LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
+  MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf
+  IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf
+!if $(CPU_TIMER_LIB_ENABLE) == TRUE && $(UNIVERSAL_PAYLOAD) == TRUE
+  TimerLib|UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
+!else
+  TimerLib|UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf
+!endif
+  
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+  CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf
+
 [LibraryClasses.common.SEC]
   HobLib|UefiPayloadPkg/Library/PayloadEntryHobLib/HobLib.inf
   PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
@@ -355,6 +353,8 @@ [LibraryClasses.common.DXE_CORE]
   
MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
   
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
   
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+
+[LibraryClasses.X64.DXE_CORE]
 !if $(SOURCE_DEBUG_ENABLE)
   DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
 !endif
@@ -368,6 +368,10 @@ [LibraryClasses.common.DXE_DRIVER]
   
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
   
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
   
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+
+[LibraryClasses.X64.DXE_DRIVER]
+  
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+  MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
 !if $(SOURCE_DEBUG_ENABLE)
   DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
 !endif
@@ -394,7 +398,7 @@ 
[LibraryClasses.common.UEFI_DRIVER,LibraryClasses.common.UEFI_APPLICATION]
   PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
 !endif
 
-[LibraryClasses.common.SMM_CORE]
+[LibraryClasses.X64.SMM_CORE]
 !if $(SMM_SUPPORT) == TRUE
   PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
   
SmmServicesTableLib|MdeModulePkg/Library/PiSmmCoreSmmServicesTableLib/PiSmmCoreSmmServicesTableLib.inf
@@ -408,7 +412,7 @@ [LibraryClasses.common.SMM_CORE]
 !endif
 !endif
 
-[LibraryClasses.common.DXE_SMM_DRIVER]
+[LibraryClasses.X64.DXE_SMM_DRIVER]
 !if $(SMM_SUPPORT) == TRUE
   PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
 
@@ -438,13 +442,15 @@ [LibraryClasses.common.DXE_SMM_DRIVER]
 #
 

 [PcdsFeatureFlag]
-  gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
   gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
   gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
   ## This PCD specified whether ACPI SDT protocol is installed.
   gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
   gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRunt

[edk2-devel] [PATCH v1 0/1] UefiPayloadPkg: Make Dsc accomodative of other archs

[Dhaval Sharma]

Current DSC files contains a lot of files which are
specific to X86 arch. Need to move around files under
arch specific sections.

Cc: Guo Dong 
Cc: Sean Rhodes 
Cc: James Lu 
Cc: Gua Guo 
Signed-off-by: Dhaval Sharma 

Dhaval (1):
  UefiPayloadPkg: Make Dsc accomodative of other archs

 UefiPayloadPkg/UefiPayloadPkg.dsc | 48 +++-
 1 file changed, 27 insertions(+), 21 deletions(-)

-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#116009): https://edk2.groups.io/g/devel/message/116009
Mute This Topic: https://groups.io/mt/104564121/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v1 1/1] UefiPayloadPkg: Make Dsc accomodative of other archs

[Dhaval Sharma]

Current DSC files contains a lot of files which are
specific to X86 arch. Need to move around files under
arch specific sections.

Cc: Guo Dong 
Cc: Sean Rhodes 
Cc: James Lu 
Cc: Gua Guo 
Signed-off-by: Dhaval Sharma 
---
 UefiPayloadPkg/UefiPayloadPkg.dsc | 48 +++-
 1 file changed, 27 insertions(+), 21 deletions(-)

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc 
b/UefiPayloadPkg/UefiPayloadPkg.dsc
index 95417cec6aff..433fb51a5695 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -259,24 +259,6 @@ [LibraryClasses]
   BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
   
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
   
FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf
-
-  #
-  # CPU
-  #
-  MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
-  LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
-  MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf
-  CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf
-  SmmCpuSyncLib|UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf
-
-  #
-  # Platform
-  #
-!if $(CPU_TIMER_LIB_ENABLE) == TRUE && $(UNIVERSAL_PAYLOAD) == TRUE
-  TimerLib|UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
-!else
-  TimerLib|UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf
-!endif
   ResetSystemLib|UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf
 !if $(USE_CBMEM_FOR_CONSOLE) == TRUE
   SerialPortLib|UefiPayloadPkg/Library/CbSerialPortLib/CbSerialPortLib.inf
@@ -339,6 +321,22 @@ [LibraryClasses.common]
   BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.inf
 !endif
 
+[LibraryClasses.X64]
+  #
+  # CPU
+  #
+  MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
+  LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
+  MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf
+  IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf
+!if $(CPU_TIMER_LIB_ENABLE) == TRUE && $(UNIVERSAL_PAYLOAD) == TRUE
+  TimerLib|UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
+!else
+  TimerLib|UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf
+!endif
+  
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+  CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf
+
 [LibraryClasses.common.SEC]
   HobLib|UefiPayloadPkg/Library/PayloadEntryHobLib/HobLib.inf
   PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
@@ -355,6 +353,8 @@ [LibraryClasses.common.DXE_CORE]
   
MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
   
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
   
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+
+[LibraryClasses.X64.DXE_CORE]
 !if $(SOURCE_DEBUG_ENABLE)
   DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
 !endif
@@ -368,6 +368,10 @@ [LibraryClasses.common.DXE_DRIVER]
   
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
   
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
   
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+
+[LibraryClasses.X64.DXE_DRIVER]
+  
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+  MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
 !if $(SOURCE_DEBUG_ENABLE)
   DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
 !endif
@@ -394,7 +398,7 @@ 
[LibraryClasses.common.UEFI_DRIVER,LibraryClasses.common.UEFI_APPLICATION]
   PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
 !endif
 
-[LibraryClasses.common.SMM_CORE]
+[LibraryClasses.X64.SMM_CORE]
 !if $(SMM_SUPPORT) == TRUE
   PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
   
SmmServicesTableLib|MdeModulePkg/Library/PiSmmCoreSmmServicesTableLib/PiSmmCoreSmmServicesTableLib.inf
@@ -408,7 +412,7 @@ [LibraryClasses.common.SMM_CORE]
 !endif
 !endif
 
-[LibraryClasses.common.DXE_SMM_DRIVER]
+[LibraryClasses.X64.DXE_SMM_DRIVER]
 !if $(SMM_SUPPORT) == TRUE
   PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
 
@@ -438,13 +442,15 @@ [LibraryClasses.common.DXE_SMM_DRIVER]
 #
 

 [PcdsFeatureFlag]
-  gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
   gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
   gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
   ## This PCD specified whether ACPI SDT protocol is installed.
   gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
   gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
   gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceFo

[edk2-devel] [PATCH v1 0/1] UefiPayloadPkg: Make Dsc accomodative of other archs

[Dhaval Sharma]

Current DSC files contains a lot of files which are
specific to X86 arch. Need to move around files under
arch specific sections.

Cc: Guo Dong 
Cc: Sean Rhodes 
Cc: James Lu 
Cc: Gua Guo 
Signed-off-by: Dhaval Sharma 

Dhaval (1):
  UefiPayloadPkg: Make Dsc accomodative of other archs

 UefiPayloadPkg/UefiPayloadPkg.dsc | 48 +++-
 1 file changed, 27 insertions(+), 21 deletions(-)

-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#115928): https://edk2.groups.io/g/devel/message/115928
Mute This Topic: https://groups.io/mt/104564121/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v1 1/1] UefiPayloadPkg: Make UPL build script arch agnostic

[Dhaval Sharma]

Current implementation makes assumptions about arch it will be built
for. Need to make it more generic to add follow up support for RISCV.
Right now it does not build for RV until relevant dsc file is available.

Cc: Guo Dong 
Cc: Sean Rhodes 
Cc: James Lu 
Cc: Gua Guo 
Signed-off-by: Dhaval Sharma 
---
 UefiPayloadPkg/UefiPayloadPkg.dsc   |  2 +-
 UefiPayloadPkg/Tools/MkFitImage.py  | 18 +++
 UefiPayloadPkg/UniversalPayloadBuild.py | 23 +---
 3 files changed, 25 insertions(+), 18 deletions(-)

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc 
b/UefiPayloadPkg/UefiPayloadPkg.dsc
index 0e142bb7c2a2..abe3d3c3d870 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -22,7 +22,7 @@ [Defines]
   SUPPORTED_ARCHITECTURES = IA32|X64
   BUILD_TARGETS   = DEBUG|RELEASE|NOOPT
   SKUID_IDENTIFIER= DEFAULT
-  OUTPUT_DIRECTORY= Build/UefiPayloadPkgX64
+  OUTPUT_DIRECTORY= Build/UefiPayloadPkg
   FLASH_DEFINITION= UefiPayloadPkg/UefiPayloadPkg.fdf
   PCD_DYNAMIC_AS_DYNAMICEX= TRUE
 
diff --git a/UefiPayloadPkg/Tools/MkFitImage.py 
b/UefiPayloadPkg/Tools/MkFitImage.py
index 41a259960b2b..b76c2156dd18 100644
--- a/UefiPayloadPkg/Tools/MkFitImage.py
+++ b/UefiPayloadPkg/Tools/MkFitImage.py
@@ -59,16 +59,16 @@ def BuildConfNode(Fdt, ParentNode, MultiImage):
 libfdt.fdt_setprop(Fdt, ConfNode1, 'require-fit', b'', 0)
 libfdt.fdt_setprop(Fdt, ConfNode1, 'firmware', bytes('tianocore', 
'utf-8'), len('tianocore') + 1)
 
-def BuildFvImageNode(Fdt, InfoHeader, ParentNode, DataOffset, DataSize, 
Description):
+def BuildFvImageNode(Fdt, InfoHeader, ParentNode, DataOffset, DataSize, 
Description, Arch):
 libfdt.fdt_setprop_u32(Fdt, ParentNode, 'data-size', DataSize)
 libfdt.fdt_setprop_u32(Fdt, ParentNode, 'data-offset', DataOffset)
 libfdt.fdt_setprop(Fdt, ParentNode, 'compression', bytes('none',   
 'utf-8'), len('none') + 1)
 libfdt.fdt_setprop(Fdt, ParentNode, 'project ',bytes('tianocore',  
 'utf-8'), len('tianocore') + 1)
-libfdt.fdt_setprop(Fdt, ParentNode, 'arch',bytes('x86_64', 
 'utf-8'), len('x86_64') + 1)
+libfdt.fdt_setprop(Fdt, ParentNode, 'arch',bytes(Arch, 
 'utf-8'), len(Arch) + 1)
 libfdt.fdt_setprop(Fdt, ParentNode, 'type',bytes('flat-binary',
 'utf-8'), len('flat-binary') + 1)
 libfdt.fdt_setprop(Fdt, ParentNode, 'description', bytes(Description,  
 'utf-8'), len(Description) + 1)
 
-def BuildTianoImageNode(Fdt, InfoHeader, ParentNode, DataOffset, DataSize, 
Description):
+def BuildTianoImageNode(Fdt, InfoHeader, ParentNode, DataOffset, DataSize, 
Description, Arch):
 #
 # Set 'load' and 'data-offset' to reserve the memory first.
 # They would be set again when Fdt completes or this function parses 
target binary file.
@@ -100,7 +100,7 @@ def BuildTianoImageNode(Fdt, InfoHeader, ParentNode, 
DataOffset, DataSize, Descr
 #
 # The subnode would be inserted from bottom to top of structure block.
 #
-def BuildFitImage(Fdt, InfoHeader):
+def BuildFitImage(Fdt, InfoHeader, Arch):
 MultiImage = [
 ["tianocore",   InfoHeader.Binary,BuildTianoImageNode , 
InfoHeader.Description, None, 0 ],
 ["uefi-fv", InfoHeader.UefifvPath,BuildFvImageNode, "UEFI 
Firmware Volume", None, 0 ],
@@ -143,7 +143,7 @@ def BuildFitImage(Fdt, InfoHeader):
 if os.path.exists (Item[1]) == False:
 continue
 FvNode = libfdt.fdt_add_subnode(Fdt, ImageNode, Name)
-BuildFvNode (Fdt, InfoHeader, FvNode, DataOffset, len(BinaryData), 
Description)
+BuildFvNode (Fdt, InfoHeader, FvNode, DataOffset, len(BinaryData), 
Description, Arch)
 
 #
 # Create new image file and combine all binary.
@@ -160,7 +160,7 @@ def BuildFitImage(Fdt, InfoHeader):
 
 return True
 
-def MakeFitImage(InfoHeader):
+def MakeFitImage(InfoHeader, Arch):
 #
 # Allocate fdt byte array.
 #
@@ -175,9 +175,9 @@ def MakeFitImage(InfoHeader):
 #
 # Parse args to build fit image.
 #
-return BuildFitImage(Fdt, InfoHeader)
+return BuildFitImage(Fdt, InfoHeader, Arch)
 
-def ReplaceFv (UplBinary, SectionFvFile, SectionName):
+def ReplaceFv (UplBinary, SectionFvFile, SectionName, Arch):
 try:
 #
 # Get Original Multi Fv
@@ -231,7 +231,7 @@ def ReplaceFv (UplBinary, SectionFvFile, SectionName):
 SectionFvFileBinary = File.read ()
 MultiFvList.append ([SectionName, SectionFvFileBinary])
 FvNode = libfdt.fdt_add_subnode(NewFitHeader, ImagesNode, 
SectionName)
-BuildFvImageNode (NewFitHeader, None, FvNode, FitSize, 
len(SectionFvFileBinary), SectionName + " Firmware Volume")
+BuildFvImageNode (N

[edk2-devel] [PATCH v1 0/1] Make FIT building more generic

[Dhaval Sharma]

Current implementation makes assumptions about arch it will be built
for. Need to make it more generic to add follow up support for RISCV.
Right now it does not build for RV until relevant dsc file is available.
https://github.com/tianocore/edk2/pull/5395

Cc: Guo Dong 
Cc: Sean Rhodes 
Cc: James Lu 
Cc: Gua Guo 

Dhaval (1):
  UefiPayloadPkg: Make UPL build script arch agnostic

 UefiPayloadPkg/UefiPayloadPkg.dsc   |  2 +-
 UefiPayloadPkg/Tools/MkFitImage.py  | 18 +++
 UefiPayloadPkg/UniversalPayloadBuild.py | 23 +---
 3 files changed, 25 insertions(+), 18 deletions(-)

-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#115721): https://edk2.groups.io/g/devel/message/115721
Mute This Topic: https://groups.io/mt/104485239/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v5 1/1] MdeModulePkg/AcpiTableDxe: Prefer xDSDT over DSDT when installing tables

[Dhaval Sharma]

As per ACPI Spec 6.5+ Table 5-9 if xDSDT is available,
it should be used first. Handle required flow when xDSDT
is absent or present.

Test: Tested on RISCV64 Qemu platform with xDSDT and booted to
linux kernel.

Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Dandan Bi 
Cc: Pedro Falcato 
Cc: devel@edk2.groups.io
Signed-off-by: Dhaval Sharma 
Acked-by: Chasel Chiu 
---

Notes:
v5:
- If DSDT is not found, throw error and continue to build other tables
v4:
- Fix typos and commit message adding more clarity to patch subject
v3:
- Added description of ACPI spec clarification based on which this patch is 
created
- Optimizing if-else flow
v2:
- Added proper indentation for else if

 MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 24 
++--
 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c 
b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
index e09bc9b704f5..3879e10b3349 100644
--- a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
+++ b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
@@ -1892,14 +1892,24 @@ InstallAcpiTableFromHob (
   }
 }
 
-if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->Dsdt != 
0) {
+//
+// First check if xDSDT is available, as that is preferred as per
+// ACPI Spec 6.5+ Table 5-9 X_DSDT definition
+//
+if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->XDsdt 
!= 0) {
+  TableToInstall = (VOID 
*)(UINTN)((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->XDsdt;
+} else if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE 
*)ChildTable)->Dsdt != 0) {
   TableToInstall = (VOID 
*)(UINTN)((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->Dsdt;
-  Status = AddTableToList (AcpiTableInstance, TableToInstall, 
TRUE, Version, TRUE, );
-  if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "InstallAcpiTableFromHob: Fail to add ACPI 
table DSDT\n"));
-ASSERT_EFI_ERROR (Status);
-break;
-  }
+} else {
+  DEBUG ((DEBUG_ERROR, "DSDT table not found\n"));
+  continue;
+}
+
+Status = AddTableToList (AcpiTableInstance, TableToInstall, TRUE, 
Version, TRUE, );
+if (EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_ERROR, "InstallAcpiTableFromHob: Fail to add ACPI 
table DSDT\n"));
+  ASSERT_EFI_ERROR (Status);
+  break;
 }
   }
 }
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#114655): https://edk2.groups.io/g/devel/message/114655
Mute This Topic: https://groups.io/mt/104011845/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v5 0/1] MdeModulePkg/AcpiTableDxe: Prefer xDSDT over DSDT when installing tables

[Dhaval Sharma]

As per ACPI Spec 6.5+ Table 5-9 if xDSDT is available,
it should be used first. Handle required flow when xDSDT
is absent or present.

Test: Tested on RISCV64 Qemu platform with xDSDT and booted to
linux kernel.

Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Dandan Bi 
Cc: Pedro Falcato 
Cc: devel@edk2.groups.io
Signed-off-by: Dhaval Sharma 
Acked-by: Chasel Chiu 

Notes:
v5:
- If DSDT is not found, throw error and continue to build other tables with
  an error log
v4:
- Fix typos and commit message adding more clarity to patch subject
v3:
- Added description of ACPI spec clarification based on which this patch is 
created
- Optimizing if-else flow
v2:
- Added proper indentation for else if

https://github.com/tianocore/edk2/pull/5311

Dhaval (1):
  MdeModulePkg/AcpiTableDxe: Prefer xDSDT over DSDT when installing
tables

 MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 24 
++--
 1 file changed, 17 insertions(+), 7 deletions(-)

-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#114654): https://edk2.groups.io/g/devel/message/114654
Mute This Topic: https://groups.io/mt/104011825/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v1 1/1] MdePkg/BaseCacheMaintenanceLib: RV64 replace asserts with logs

[Dhaval Sharma]

"The CpuDxe interface will be the wrapper." Yes, of course. It needs to be
added. I was just saying that maybe any CMO checking is not required there
as cmo library will take care of it.

On Tue, Jan 23, 2024 at 10:24 PM Sunil V L  wrote:

> On Tue, Jan 23, 2024 at 11:42:57AM +0530, Dhaval Sharma wrote:
> > Sunil,
> > I thought "WriteBackDataCacheRange not supported" is more explicit over
> > "CMO not available".
> >
> Okay.
>
> > @Pedro Falcato  For the example you mentioned,
> is
> > your concern more about someone not being able to notice the problem
> (that
> > the system is non-coherent) at the time of development and later ending
> up
> > with corrupted data during production? And you are suggesting that an
> > Assert helps address that problem by making that problem more visible to
> > the developer and a verbose warning does not?
> >
> > I can create a patch for CpuFlushCpuDataCache but I think we should avoid
> > CMO based return in there. Because in case of InvalidateDataCacheRange we
> > have an alternate implementation of fence in the absence of CMO. So it is
> > better to let riscvcache decide the right implementation.
> >
> The CpuDxe interface will be the wrapper. See Arm's implementation.
> Since CMO support is added now, the CpuDxe interface should be updated.
>
> Thanks,
> Sunil
>


-- 
Thanks!
=D


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#114302): https://edk2.groups.io/g/devel/message/114302
Mute This Topic: https://groups.io/mt/103805230/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v1 1/1] MdePkg/BaseCacheMaintenanceLib: RV64 replace asserts with logs

[Dhaval Sharma]

Sunil,
I thought "WriteBackDataCacheRange not supported" is more explicit over
"CMO not available".

@Pedro Falcato  For the example you mentioned, is
your concern more about someone not being able to notice the problem (that
the system is non-coherent) at the time of development and later ending up
with corrupted data during production? And you are suggesting that an
Assert helps address that problem by making that problem more visible to
the developer and a verbose warning does not?

I can create a patch for CpuFlushCpuDataCache but I think we should avoid
CMO based return in there. Because in case of InvalidateDataCacheRange we
have an alternate implementation of fence in the absence of CMO. So it is
better to let riscvcache decide the right implementation.

=D


On Fri, Jan 19, 2024 at 11:06 AM Sunil V L  wrote:

> On Thu, Jan 18, 2024 at 03:20:18PM +0530, Dhaval wrote:
> > Some platforms do not implement cache management operations. Especially
> > for DMA drivers have code to manage data cache. The code seem to depend
> > on the underlying CPU/cache drivers to enact functionality and simply
> > return if such functionality is not implemented. However this causes
> > issue with CMO implementation which has an assert causing flow to
> > hang within debug environment. While it is not an issue in production
> > environment there is a recommendation to conver this assert in to
> > a harmless logger message. Eventually platform/drivers need to have
> > better guard for such functionality.
> >
> > Signed-off-by: Dhaval Sharma 
> > Cc: Liming Gao 
> > Cc: Michael D Kinney 
> > Cc: Zhiguang Liu 
> > Cc: Sunil V L 
> > Cc: Andrei Warkentin 
> > Cc: Laszlo Ersek 
> > Cc: Pedro Falcato 
> > Cc: Yang Cheng 
> > ---
> >  MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 11 ++-
> >  1 file changed, 6 insertions(+), 5 deletions(-)
> >
> > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> > index 73a5a6b6b5d6..d99515bcf38b 100644
> > --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> > @@ -183,9 +183,8 @@ WriteBackInvalidateDataCache (
> >VOID
> >)
> >  {
> > -  ASSERT (FALSE);
> >DEBUG ((
> > -DEBUG_ERROR,
> > +DEBUG_VERBOSE,
> >  "WriteBackInvalidateDataCache: RISC-V unsupported function.\n"
> >  ));
> >  }
> > @@ -226,7 +225,9 @@ WriteBackInvalidateDataCacheRange (
> >if (RiscVIsCMOEnabled ()) {
> >  CacheOpCacheRange (Address, Length, CacheOpFlush);
> >} else {
> > -ASSERT (FALSE);
> > +DEBUG (
> > +  (DEBUG_VERBOSE, "WriteBackInvalidateDataCacheRange not supported
> \n")
>
> Should this be CMO not enabled?
>
> > +  );
> >}
> >
> >return Address;
> > @@ -248,7 +249,7 @@ WriteBackDataCache (
> >VOID
> >)
> >  {
> > -  ASSERT (FALSE);
> > +  DEBUG ((DEBUG_VERBOSE, "WriteBackDataCache not supported \n"));
> >  }
> >
> >  /**
> > @@ -283,7 +284,7 @@ WriteBackDataCacheRange (
> >if (RiscVIsCMOEnabled ()) {
> >  CacheOpCacheRange (Address, Length, CacheOpClean);
> >} else {
> > -ASSERT (FALSE);
> > +DEBUG ((DEBUG_VERBOSE, "WriteBackDataCacheRange not supported \n"));
> Same comment as earlier.
>
> >}
> >
> >return Address;
> > --
> > 2.39.2
> >
>


-- 
Thanks!
=D


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#114179): https://edk2.groups.io/g/devel/message/114179
Mute This Topic: https://groups.io/mt/103805230/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v1 1/1] MdePkg/BaseCacheMaintenanceLib: RV64 replace asserts with logs

[Dhaval Sharma]

Hi Pedro,
Agree Assert is slightly more enforcing over logs, but you could still get
away with even Assert in release mode.
One alternative is to convert VERBOSE into WARNING?
=D

On Thu, Jan 18, 2024 at 9:28 PM Pedro Falcato 
wrote:

> On Thu, Jan 18, 2024 at 9:50 AM Dhaval  wrote:
> >
> > Some platforms do not implement cache management operations. Especially
> > for DMA drivers have code to manage data cache. The code seem to depend
> > on the underlying CPU/cache drivers to enact functionality and simply
> > return if such functionality is not implemented. However this causes
> > issue with CMO implementation which has an assert causing flow to
> > hang within debug environment. While it is not an issue in production
> > environment there is a recommendation to conver this assert in to
>
> I don't agree with this patch. As I see it, the library has a simple
> contract: Do cache operation X and return. We cannot safely return if
> we don't know how to do cache operation X. Say, with a Thead core and
> Xtheadcmo.
> Any other concerns wrt DMA are, in my view, somewhat separate.
>
> One can easily theorize a way this change can come to bite us, say, a
> storage controller writes bogus data to storage (because the platform
> needs explicit cache coherency, and we don't know how to do that) and
> causes data corruption.
>
> > a harmless logger message. Eventually platform/drivers need to have
> > better guard for such functionality.
>
> Like an ASSERT? :)
>
> --
> Pedro
>


-- 
Thanks!
=D


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#113999): https://edk2.groups.io/g/devel/message/113999
Mute This Topic: https://groups.io/mt/103805230/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v1 1/1] MdePkg/BaseCacheMaintenanceLib: RV64 replace asserts with logs

[Dhaval Sharma]

Some platforms do not implement cache management operations. Especially
for DMA drivers have code to manage data cache. The code seem to depend
on the underlying CPU/cache drivers to enact functionality and simply
return if such functionality is not implemented. However this causes
issue with CMO implementation which has an assert causing flow to
hang within debug environment. While it is not an issue in production
environment there is a recommendation to conver this assert in to
a harmless logger message. Eventually platform/drivers need to have
better guard for such functionality.

Signed-off-by: Dhaval Sharma 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Zhiguang Liu 
Cc: Sunil V L 
Cc: Andrei Warkentin 
Cc: Laszlo Ersek 
Cc: Pedro Falcato 
Cc: Yang Cheng 
---
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index 73a5a6b6b5d6..d99515bcf38b 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -183,9 +183,8 @@ WriteBackInvalidateDataCache (
   VOID
   )
 {
-  ASSERT (FALSE);
   DEBUG ((
-DEBUG_ERROR,
+DEBUG_VERBOSE,
 "WriteBackInvalidateDataCache: RISC-V unsupported function.\n"
 ));
 }
@@ -226,7 +225,9 @@ WriteBackInvalidateDataCacheRange (
   if (RiscVIsCMOEnabled ()) {
 CacheOpCacheRange (Address, Length, CacheOpFlush);
   } else {
-ASSERT (FALSE);
+DEBUG (
+  (DEBUG_VERBOSE, "WriteBackInvalidateDataCacheRange not supported \n")
+  );
   }
 
   return Address;
@@ -248,7 +249,7 @@ WriteBackDataCache (
   VOID
   )
 {
-  ASSERT (FALSE);
+  DEBUG ((DEBUG_VERBOSE, "WriteBackDataCache not supported \n"));
 }
 
 /**
@@ -283,7 +284,7 @@ WriteBackDataCacheRange (
   if (RiscVIsCMOEnabled ()) {
 CacheOpCacheRange (Address, Length, CacheOpClean);
   } else {
-ASSERT (FALSE);
+DEBUG ((DEBUG_VERBOSE, "WriteBackDataCacheRange not supported \n"));
   }
 
   return Address;
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#113990): https://edk2.groups.io/g/devel/message/113990
Mute This Topic: https://groups.io/mt/103805230/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v1 0/1] Replace asserts with logs for unimplemented cache ops

[Dhaval Sharma]

Some platforms do not implement cache management operations. i.e DMA drivers
seem to depend on the underlying CPU/cache functions to simply return if such
functionality is not implemented. However this causes issue with CMO
implementation which has an assert, causing flow to hang within debug
environment. While it is not an issue in production environment, there
is a recommendation to convert this assert in to a harmless logger message.
Eventually platform/drivers need to have better guard for such functionality.

Signed-off-by: Dhaval Sharma 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Zhiguang Liu 
Cc: Sunil V L 
Cc: Andrei Warkentin 
Cc: Laszlo Ersek 
Cc: Pedro Falcato 
Cc: Yang Cheng 

Code: https://github.com/tianocore/edk2/pull/5267

Dhaval (1):
  MdePkg/BaseCacheMaintenanceLib: RV64 replace asserts with logs

 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#113989): https://edk2.groups.io/g/devel/message/113989
Mute This Topic: https://groups.io/mt/103805229/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v10 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V

[Dhaval Sharma]

Based on the above discussion, and some more thoughts I am thinking it is
okay to at least replace ASSERT from CMO code and let other platform code
place its own guards to avoid calling this code when it is known that
platform does not support such operations. If there are no objections to
this we can go ahead.

On Tue, Jan 9, 2024 at 9:50 PM Warkentin, Andrei 
wrote:

> For now, this is really something that ought to be hidden by DmaLib
> abstraction (Map/Unmap). This would allow the driver to be minimally aware
> of how the IP is integrated into the SoC.
>
> A
>
> > -Original Message-
> > From: Sunil V L 
> > Sent: Monday, January 8, 2024 11:32 PM
> > To: Pedro Falcato 
> > Cc: devel@edk2.groups.io; dha...@rivosinc.com; yorange
> > ; Warkentin, Andrei
> > ; Ard Biesheuvel  >;
> > Leif Lindholm 
> > Subject: Re: [edk2-devel] [PATCH v10 4/5] MdePkg: Utilize Cache
> > Management Operations Implementation For RISC-V
> >
> > On Mon, Jan 08, 2024 at 09:53:46PM +, Pedro Falcato wrote:
> > > On Mon, Jan 8, 2024 at 4:23 PM Dhaval Sharma 
> > wrote:
> > > >
> > > > Hi yangcheng/Pedro,
> > >
> > > +CC a bunch of relevant people
> > >
> > > Hi, (FYI you did not CC me)
> > >
> > > Looking at yangcheng's example:
> > >
> > >   Status = PrepareDmaData (gpIdmacDesc, Length, Buffer); <-- We write
> > > to the IDMAC desc
> > >   if (EFI_ERROR (Status)) {
> > > goto out;
> > >   }
> > >
> > >   WriteBackDataCacheRange (gpIdmacDesc, DescPages * EFI_PAGE_SIZE);
> > > <-- Make sure it's DMA-coherent
> > >   StartDma (Length); <-- We've flushed the cache, everything is now in
> > > DRAM and DMA-coherent, start DMA
> > >
> > > which screams of "bad abstractions" because you don't actually need to
> > > write data back, if the device and platform are DMA coherent.
> > >
> > > So what we want here really depends. My local "Volume I: RISC-V
> > > Unprivileged ISA V20191213" says, section A.5:
> > >
> > > "Table A.5 provides a mapping of Linux memory ordering macros onto
> > > RISC-V memory instructions.
> > > The Linux fences dma rmb() and dma wmb() map onto FENCE R,R and FENCE
> > > W,W, respectively, since the RISC-V Unix Platform requires coherent
> > > DMA, but would be mapped onto FENCE RI,RI and FENCE WO,WO,
> > > respectively, on a platform with non-coherent DMA.
> > > Platforms with non-
> > > coherent DMA may also require a mechanism by which cache lines can be
> > > flushed and/or invalidated.
> > > Such mechanisms will be device-specific and/or standardized in a
> > > future extension to the ISA."
> > >
> > > The (current date) RISCV Platform Spec also says: "Memory accesses by
> > > I/O masters can be coherent or non-coherent with respect to all
> > > hart-related caches."
> > > which is brilliantly useless.
> > >
> > > so I think the best solution here is to:
> > >
> > > 1) Add a new PCD for platform DMA coherency, and test that on
> > > WriteBackDataCacheRange's ASSERT (if (!Coherent) ASSERT() else
> > > return;)
> > > 2) Add a more abstracting API that doesn't necessarily map to
> > > WriteBackDataCache when all we wanted was to assert DMA coherency
> > >
> > > but, alas, I've seen a lot less funky platforms than many of you, and
> > > DMA/cache-coherency is not really my thing, so I'll defer to others..
> > >
> > My preference is just remove the assertion and add the debug verbose
> > message instead of changing drivers/introduce new interfaces. It is a
> nop in
> > linux as well if CMO is not present.
> >
> > Thanks,
> > Sunil
>


-- 
Thanks!
=D


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#113652): https://edk2.groups.io/g/devel/message/113652
Mute This Topic: https://groups.io/mt/103150435/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v10 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V

[Dhaval Sharma]

Hi yangcheng/Pedro,
Thanks for bringing this up. I understand the issue and probably we could just 
keep it simple with a warning instead of an assert. But wanted to mention a 
couple of points:
1. I think initially even in my patchset it was DEBUG message but there was a 
comment to turn it into Assert and I kind of agreed to it thinking that Assert 
is also typically ignored in release mode and comes into effect during debug 
build.
2. It might be okay to keep it that way because at least in debug mode it 
brings it to a developer's notice that the functionality he/she intends to call 
is not implemented by underlying layer.
Whatever we decide, will be applicable to other places in this file as well. 
Pedro IMO, it would be better to have simple warnings instead of injecting NOPS 
as it at least notifies the user about actual underlying behavior.


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#113406): https://edk2.groups.io/g/devel/message/113406
Mute This Topic: https://groups.io/mt/103150435/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v2 3/4] UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc

[Dhaval Sharma]

Reviewed-by: Dhaval Sharma 


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#113403): https://edk2.groups.io/g/devel/message/113403
Mute This Topic: https://groups.io/mt/103595210/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v4 1/1] MdeModulePkg/AcpiTableDxe: Prefer xDSDT over DSDT when installing tables

[Dhaval Sharma]

As per ACPI Spec 6.5+ Table 5-9 if xDSDT is available,
it should be used first. Handle required flow when xDSDT
is absent or present.

Test: Tested on RISCV64 Qemu platform with xDSDT and booted to
linux kernel.

Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Dandan Bi 
Cc: Pedro Falcato 
Cc: devel@edk2.groups.io
Signed-off-by: Dhaval Sharma 
Acked-by: Chasel Chiu 
---

Notes:
v4:
- Fix typos and commit message adding more clarity to patch subject
v3:
- Added description of ACPI spec clarification based on which this patch is 
created
- Optimizing if-else flow
v2:
- Added proper indentation for else if

 MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 23 
++--
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c 
b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
index e09bc9b704f5..61af6047a2a7 100644
--- a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
+++ b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
@@ -1892,14 +1892,23 @@ InstallAcpiTableFromHob (
   }
 }
 
-if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->Dsdt != 
0) {
+//
+// First check if xDSDT is available, as that is preferred as per
+// ACPI Spec 6.5+ Table 5-9 X_DSDT definition
+//
+if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->XDsdt 
!= 0) {
+  TableToInstall = (VOID 
*)(UINTN)((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->XDsdt;
+} else if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE 
*)ChildTable)->Dsdt != 0) {
   TableToInstall = (VOID 
*)(UINTN)((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->Dsdt;
-  Status = AddTableToList (AcpiTableInstance, TableToInstall, 
TRUE, Version, TRUE, );
-  if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "InstallAcpiTableFromHob: Fail to add ACPI 
table DSDT\n"));
-ASSERT_EFI_ERROR (Status);
-break;
-  }
+} else {
+  break;
+}
+
+Status = AddTableToList (AcpiTableInstance, TableToInstall, TRUE, 
Version, TRUE, );
+if (EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_ERROR, "InstallAcpiTableFromHob: Fail to add ACPI 
table DSDT\n"));
+  ASSERT_EFI_ERROR (Status);
+  break;
 }
   }
 }
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#113401): https://edk2.groups.io/g/devel/message/113401
Mute This Topic: https://groups.io/mt/103598583/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v4 0/1] Prefer XDSDT table over DSDT if available

[Dhaval Sharma]

Enable detection of XDSDT table from ACPI HOB and use it to comply
with ACPI spec 6.5+ Table 5-9. https://github.com/tianocore/edk2/pull/5235

Dhaval (1):
  MdeModulePkg/AcpiTableDxe: Prefer xDSDT over DSDT when installing
tables

 MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 23 
++--
 1 file changed, 16 insertions(+), 7 deletions(-)

-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#113400): https://edk2.groups.io/g/devel/message/113400
Mute This Topic: https://groups.io/mt/103598537/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v10 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V

[Dhaval Sharma]

Thanks. Just to clarify, In the earlier formatting
"InvalidateDataCacheRange:\
> +   Zicbom not supported.\n" \
A missing " after *Range:\ was causing slightly skewed prints. After adding
this " it looks okay. So that is one change I had addressed.
But if keeping it in a single line works better please feel free to update.
And Thanks!


On Tue, Dec 19, 2023 at 12:59 PM Sunil V L  wrote:

> On Wed, Dec 13, 2023 at 08:29:30PM +0530, Dhaval Sharma wrote:
> > Use newly defined cache management operations for RISC-V where possible
> > It builds up on the support added for RISC-V cache management
> > instructions in BaseLib.
> > Cc: Michael D Kinney 
> > Cc: Liming Gao 
> > Cc: Zhiguang Liu 
> > Cc: Laszlo Ersek 
> > Cc: Pedro Falcato 
> >
> > Signed-off-by: Dhaval Sharma 
> > Acked-by: Laszlo Ersek 
> > Reviewed-by: Pedro Falcato 
> > ---
> >
> > Notes:
> > V10:
> > - Fix formatting to keep comments within 80
> > - Replace RV with RISC-V
> > - Fix an issue with multi line comments
> > - Added assert to an unsupported function
> > - Minor case modification in str in .uni
> >
> > V9:
> > - Fixed an issue with Instruction cache invalidation. Use fence.i
> >   instruction as CMO does not support i-cache operations.
> > V8:
> > - Added note to convert PCD into RISC-V feature bitmap pointer
> > - Modified function names to be more explicit about cache ops
> > - Added RB tag
> > V7:
> > - Added PcdLib
> > - Restructure DEBUG message based on feedback on V6
> > - Make naming consistent to CMO, remove all CBO references
> > - Add ASSERT for not supported functions instead of plain debug
> message
> > - Added RB tag
> > V6:
> > - Utilize cache management instructions if HW supports it
> >   This patch is part of restructuring on top of v5
> >
> >  MdePkg/MdePkg.dec  |
>  8 +
> >  MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |
>  5 +
> >  MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c|
> 177 
> >  MdePkg/MdePkg.uni  |
>  4 +
> >  4 files changed, 166 insertions(+), 28 deletions(-)
> >
> > diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
> > index ac54338089e8..fa92673ff633 100644
> > --- a/MdePkg/MdePkg.dec
> > +++ b/MdePkg/MdePkg.dec
> > @@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64,
> PcdsPatchableInModule.AARCH64]
> ># @Prompt CPU Rng algorithm's GUID.
> >
> gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x0037
> >
> > +[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64]
> > +  #
> > +  # Configurability to override RISC-V CPU Features
> > +  # BIT 0 = Cache Management Operations. This bit is relevant only if
> > +  # previous stage has feature enabled and user wants to disable it.
> > +  #
> > +
> gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0x|UINT64|0x69
> > +
> >  [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
> >## This value is used to set the base address of PCI express
> hierarchy.
> ># @Prompt PCI Express Base Address.
> > diff --git
> a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> > index 6fd9cbe5f6c9..601a38d6c109 100644
> > --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> > @@ -56,3 +56,8 @@ [LibraryClasses]
> >BaseLib
> >DebugLib
> >
> > +[LibraryClasses.RISCV64]
> > +  PcdLib
> > +
> > +[Pcd.RISCV64]
> > +  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride  ## CONSUMES
> > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> > index ac2a3c23a249..7c53a17abbb5 100644
> > --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> > @@ -2,6 +2,7 @@
> >RISC-V specific functionality for cache.
> >
> >Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All
> rights reserved.
> > +  Copyright (c) 2023, Rivos Inc. All rights reserved.
> >
> >SPDX-License-Iden

[edk2-devel] [PATCH v10 5/5] OvmfPkg/RiscVVirt: Override for RISC-V CPU Features

[Dhaval Sharma]

This PCD provides a way for platform to override any
HW features that are default enabled by previous stages
of FW (like OpenSBI). For the case where previous/prev
stage has disabled the feature, this override is not
useful and its usage should be avoided.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Sunil V L 
Cc: Andrei Warkentin 
Cc: Laszlo Ersek 
Cc: Pedro Falcato 

Signed-off-by: Dhaval Sharma 
Acked-by: Laszlo Ersek 
Reviewed-by: Andrei Warkentin 
---

Notes:
V10:
- Only keep CMO feature bitmask bit to disabled. Unimplemented bits
  remain 1.
V8:
- Added RV tag
V7:
- Added RB tag
v6:
- Modify PCD name according to changes made in Baselib implementation
V5:
- Introduce PCD for platform

 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc 
b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
index fe320525153f..a050f1ffc1d4 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
+++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
@@ -203,6 +203,7 @@ [PcdsFeatureFlag]
   gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
 
 [PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFE
   gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|100
   gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|100
   gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#112483): https://edk2.groups.io/g/devel/message/112483
Mute This Topic: https://groups.io/mt/103150443/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v10 3/5] MdePkg: Implement RISC-V Cache Management Operations

[Dhaval Sharma]

Implement Cache Management Operations (CMO) defined by
RISC-V spec https://github.com/riscv/riscv-CMOs.

Notes:
1. CMO only supports block based Operations. Meaning cache
   flush/invd/clean Operations are not available for the entire
   range. In that case we fallback on fence.i instructions.
2. Operations are implemented using Opcodes to make them compiler
   independent. binutils 2.39+ compilers support CMO instructions.

Test:
1. Ensured correct instructions are refelecting in asm
2. Qemu implements basic support for CMO operations in that it allwos
   instructions without exceptions. Verified it works properly in
   that sense.
3. SG2042Pkg implements CMO-like instructions. It was verified that
   CpuFlushCpuDataCache works fine. This more of less
   confirms that framework is alright.
4. TODO: Once Silicon is available with exact instructions, we will
   further verify this.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Sunil V L 
Cc: Daniel Schaefer 
Cc: Laszlo Ersek 
Cc: Pedro Falcato 

Signed-off-by: Dhaval Sharma 
Reviewed-by: Laszlo Ersek 
Reviewed-by: Sunil V L 
Reviewed-by: Jingyu Li 
---

Notes:
v8:
- Add *asm* postfix to cmo functions
- Add reviewed by tags
V7:
- Modify instruction names as per feedback from V6
- Added RB
V6:
- Implement Cache management instructions in Baselib

 MdePkg/Library/BaseLib/BaseLib.inf|  2 +-
 MdePkg/Include/Library/BaseLib.h  | 33 

 MdePkg/Include/RiscV64/RiscVasm.inc   | 19 
+++
 MdePkg/Library/BaseLib/RiscV64/{FlushCache.S => RiscVCacheMgmt.S} | 17 
++
 4 files changed, 70 insertions(+), 1 deletion(-)

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
b/MdePkg/Library/BaseLib/BaseLib.inf
index 03c7b02e828b..53389389448c 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -400,7 +400,7 @@ [Sources.RISCV64]
   RiscV64/RiscVCpuBreakpoint.S  | GCC
   RiscV64/RiscVCpuPause.S   | GCC
   RiscV64/RiscVInterrupt.S  | GCC
-  RiscV64/FlushCache.S  | GCC
+  RiscV64/RiscVCacheMgmt.S  | GCC
   RiscV64/CpuScratch.S  | GCC
   RiscV64/ReadTimer.S   | GCC
   RiscV64/RiscVMmu.S| GCC
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index c5e7f6dff0bc..b71e47f41b7f 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -226,6 +226,39 @@ RiscVInvalidateDataCacheFenceAsm (
   VOID
   );
 
+/**
+  RISC-V flush cache block. Atomically perform a clean operation
+  followed by an invalidate operation
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheFlushCmoAsm (
+  IN UINTN
+  );
+
+/**
+Perform a write transfer to another cache or to memory if the
+data in the copy of the cache block have been modified by a store
+operation
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheCleanCmoAsm (
+  IN UINTN
+  );
+
+/**
+Deallocate the copy of the cache block
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheInvalCmoAsm (
+  IN UINTN
+  );
+
 #endif // defined (MDE_CPU_RISCV64)
 
 #if defined (MDE_CPU_LOONGARCH64)
diff --git a/MdePkg/Include/RiscV64/RiscVasm.inc 
b/MdePkg/Include/RiscV64/RiscVasm.inc
new file mode 100644
index ..29de7358855c
--- /dev/null
+++ b/MdePkg/Include/RiscV64/RiscVasm.inc
@@ -0,0 +1,19 @@
+/*
+ *
+ * RISC-V cache operation encoding.
+ * Copyright (c) 2023, Rivos Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ */
+
+.macro RISCVCMOFLUSH
+.word 0x25200f
+.endm
+
+.macro RISCVCMOINVALIDATE
+.word 0x05200f
+.endm
+
+.macro RISCVCMOCLEAN
+.word 0x15200f
+.endm
diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S 
b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
similarity index 56%
rename from MdePkg/Library/BaseLib/RiscV64/FlushCache.S
rename to MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
index 8cfb85097996..4752aa72d95e 100644
--- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
@@ -3,10 +3,12 @@
 // RISC-V cache operation.
 //
 // Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+// Copyright (c) 2023, Rivos Inc. All rights reserved.
 //
 // SPDX-License-Identifier: BSD-2-Clause-Patent
 //
 
//--
+.include "RiscVasm.inc"
 
 .align 3
 ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheFenceAsm)
@@ -19,3 +21,18 @@ ASM_PFX(RiscVInvalidateInstCacheFenceAsm):
 ASM_PFX(RiscVInvalidateDataCacheFenceAsm):
 fence
 ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheFlushCmoAsm)
+ASM_PFX (RiscVCpuCacheFlushCmoAsm):
+RISCVCMOFLUSH
+ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheCleanCmoAsm)
+ASM_PFX (RiscVCpuCacheCleanCmoAsm):
+RISCVCMOCLEAN
+ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheInvalCmoAsm)
+ASM_PFX (RiscVCpuCac

[edk2-devel] [PATCH v10 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V

[Dhaval Sharma]

Use newly defined cache management operations for RISC-V where possible
It builds up on the support added for RISC-V cache management
instructions in BaseLib.
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Laszlo Ersek 
Cc: Pedro Falcato 

Signed-off-by: Dhaval Sharma 
Acked-by: Laszlo Ersek 
Reviewed-by: Pedro Falcato 
---

Notes:
V10:
- Fix formatting to keep comments within 80
- Replace RV with RISC-V
- Fix an issue with multi line comments
- Added assert to an unsupported function
- Minor case modification in str in .uni

V9:
- Fixed an issue with Instruction cache invalidation. Use fence.i
  instruction as CMO does not support i-cache operations.
V8:
- Added note to convert PCD into RISC-V feature bitmap pointer
- Modified function names to be more explicit about cache ops
- Added RB tag
V7:
- Added PcdLib
- Restructure DEBUG message based on feedback on V6
- Make naming consistent to CMO, remove all CBO references
- Add ASSERT for not supported functions instead of plain debug message
- Added RB tag
V6:
- Utilize cache management instructions if HW supports it
  This patch is part of restructuring on top of v5

 MdePkg/MdePkg.dec  |   8 +
 MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |   5 +
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c| 177 

 MdePkg/MdePkg.uni  |   4 +
 4 files changed, 166 insertions(+), 28 deletions(-)

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index ac54338089e8..fa92673ff633 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AARCH64]
   # @Prompt CPU Rng algorithm's GUID.
   
gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x0037
 
+[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64]
+  #
+  # Configurability to override RISC-V CPU Features
+  # BIT 0 = Cache Management Operations. This bit is relevant only if
+  # previous stage has feature enabled and user wants to disable it.
+  #
+  
gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0x|UINT64|0x69
+
 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
   ## This value is used to set the base address of PCI express hierarchy.
   # @Prompt PCI Express Base Address.
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf 
b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
index 6fd9cbe5f6c9..601a38d6c109 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
@@ -56,3 +56,8 @@ [LibraryClasses]
   BaseLib
   DebugLib
 
+[LibraryClasses.RISCV64]
+  PcdLib
+
+[Pcd.RISCV64]
+  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride  ## CONSUMES
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index ac2a3c23a249..7c53a17abbb5 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -2,6 +2,7 @@
   RISC-V specific functionality for cache.
 
   Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+  Copyright (c) 2023, Rivos Inc. All rights reserved.
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -9,10 +10,116 @@
 #include 
 #include 
 #include 
+#include 
+
+//
+// TODO: Grab cache block size and make Cache Management Operation
+// enabling decision based on RISC-V CPU HOB in
+// future when it is available and convert PcdRiscVFeatureOverride
+// PCD to a pointer that contains pointer to bitmap structure
+// which can be operated more elegantly.
+//
+#define RISCV_CACHE_BLOCK_SIZE 64
+#define RISCV_CPU_FEATURE_CMO_BITMASK  0x1
+
+typedef enum {
+  CacheOpClean,
+  CacheOpFlush,
+  CacheOpInvld,
+} CACHE_OP;
+
+/**
+Verify CBOs are supported by this HW
+TODO: Use RISC-V CPU HOB once available.
+
+**/
+STATIC
+BOOLEAN
+RiscVIsCMOEnabled (
+  VOID
+  )
+{
+  // If CMO is disabled in HW, skip Override check
+  // Otherwise this PCD can override settings
+  return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_CMO_BITMASK) 
!= 0);
+}
+
+/**
+  Performs required opeartion on cache lines in the cache coherency domain
+  of the calling CPU. If Address is not aligned on a cache line boundary,
+  then entire cache line containing Address is operated. If Address + Length
+  is not aligned on a cache line boundary, then the entire cache line
+  containing Address + Length -1 is operated.
+  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+  @param  Address The base address of the cache lines to
+  invali

[edk2-devel] [PATCH v10 2/5] MdePkg: Rename Cache Management Function To Clarify Fence Based Op

[Dhaval Sharma]

There are different ways to manage cache on RISC-V Processors.
One way is to use fence instruction. Another way is to use CPU
specific cache management operation instructions ratified as
per RISC-V ISA specifications to be introduced in future
patches. Current method is fence instruction based, rename the
function accordingly to add that clarity.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Sunil V L 
Cc: Daniel Schaefer 
Cc: Laszlo Ersek 
Cc: Pedro Falcato 

Signed-off-by: Dhaval Sharma 
Reviewed-by: Laszlo Ersek 
---

Notes:
V8:
- Update function name to udpate *asm* in the end
V7:
- Add RB tag
V6:
- As part of restructuring, adding cache instruction differentiation
  in function naming

 MdePkg/Include/Library/BaseLib.h| 4 ++--
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 4 ++--
 MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 8 
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 2c69c5f52877..c5e7f6dff0bc 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -212,7 +212,7 @@ RiscVClearPendingTimerInterrupt (
 **/
 VOID
 EFIAPI
-RiscVInvalidateInstCacheAsm (
+RiscVInvalidateInstCacheFenceAsm (
   VOID
   );
 
@@ -222,7 +222,7 @@ RiscVInvalidateInstCacheAsm (
 **/
 VOID
 EFIAPI
-RiscVInvalidateDataCacheAsm (
+RiscVInvalidateDataCacheFenceAsm (
   VOID
   );
 
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index d5efcf49a4bf..ac2a3c23a249 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -21,7 +21,7 @@ InvalidateInstructionCache (
   VOID
   )
 {
-  RiscVInvalidateInstCacheAsm ();
+  RiscVInvalidateInstCacheFenceAsm ();
 }
 
 /**
@@ -193,7 +193,7 @@ InvalidateDataCache (
   VOID
   )
 {
-  RiscVInvalidateDataCacheAsm ();
+  RiscVInvalidateDataCacheFenceAsm ();
 }
 
 /**
diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S 
b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
index 7c10fdd268af..8cfb85097996 100644
--- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
+++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
@@ -9,13 +9,13 @@
 
//--
 
 .align 3
-ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
-ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
+ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheFenceAsm)
+ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheFenceAsm)
 
-ASM_PFX(RiscVInvalidateInstCacheAsm):
+ASM_PFX(RiscVInvalidateInstCacheFenceAsm):
 fence.i
 ret
 
-ASM_PFX(RiscVInvalidateDataCacheAsm):
+ASM_PFX(RiscVInvalidateDataCacheFenceAsm):
 fence
 ret
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#112480): https://edk2.groups.io/g/devel/message/112480
Mute This Topic: https://groups.io/mt/103150383/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v10 1/5] MdePkg: Move RISC-V Cache Management Declarations Into BaseLib

[Dhaval Sharma]

The declarations for cache Management functions belong to BaseLib
instead of instance source file. This helps with further restructuring
of cache management code for RISC-V.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Laszlo Ersek 
Cc: Pedro Falcato 

Signed-off-by: Dhaval Sharma 
Reviewed-by: Laszlo Ersek 
---

Notes:
V7:
- Added RB tag
V6:
- Move cache management function declaration in baselib where it belongs

 MdePkg/Include/Library/BaseLib.h| 20 
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 20 
 2 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 728e89d2bf44..2c69c5f52877 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -206,6 +206,26 @@ RiscVClearPendingTimerInterrupt (
   VOID
   );
 
+/**
+  RISC-V invalidate instruction cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateInstCacheAsm (
+  VOID
+  );
+
+/**
+  RISC-V invalidate data cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateDataCacheAsm (
+  VOID
+  );
+
 #endif // defined (MDE_CPU_RISCV64)
 
 #if defined (MDE_CPU_LOONGARCH64)
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index d08fb9f193ca..d5efcf49a4bf 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -10,26 +10,6 @@
 #include 
 #include 
 
-/**
-  RISC-V invalidate instruction cache.
-
-**/
-VOID
-EFIAPI
-RiscVInvalidateInstCacheAsm (
-  VOID
-  );
-
-/**
-  RISC-V invalidate data cache.
-
-**/
-VOID
-EFIAPI
-RiscVInvalidateDataCacheAsm (
-  VOID
-  );
-
 /**
   Invalidates the entire instruction cache in cache coherency domain of the
   calling CPU.
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#112479): https://edk2.groups.io/g/devel/message/112479
Mute This Topic: https://groups.io/mt/103150382/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v10 0/5] Cache Management Operations Support For RISC-V

[Dhaval Sharma]

Implementing code to support Cache Management Operations (CMO) defined by
RISC-V CMO instructions.https://github.com/riscv/riscv-CMOs
This is a re-write of original series v5.
The patchset contains 5 patches- created based on V5 feedback.
1. Restructuring of existing code and move instruction declarations into BaseLib
2. Renaming existing functions to denote type of instruction used to maanage 
cache.
   This is useful for further patches where more cache management instructions 
are added.
3. Add the new cache maintenance operations to BaseLib, including the
 new assembly instruction encodings.
4. Update BaseCacheMaintenanceLib (utilizing the new BaseLib primitives)
5. Add platform level PCD to allow overriding of RISC-V features.

V10:
- Fix formatting to keep comments within 80
- Replace RV with RISC-V
- Fix an issue with multi line comments
- Added assert to an unsupported function WriteBackInvalidateDataCache
- Only keep CMO feature bitmask bit to disabled. Unimplemented bits remain 1.
- Minor case modification in str in .uni

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Sunil V L 
Cc: Andrei Warkentin 
Cc: Laszlo Ersek 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Laszlo Ersek 
Cc: Pedro Falcato 


Dhaval (5):
  MdePkg: Move RISC-V Cache Management Declarations Into BaseLib
  MdePkg: Rename Cache Management Function To Clarify Fence Based Op
  MdePkg: Implement RISC-V Cache Management Operations
  MdePkg: Utilize Cache Management Operations Implementation For RISC-V
  OvmfPkg/RiscVVirt: Override for RISC-V CPU Features

 MdePkg/MdePkg.dec  |   8 +
 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc|   1 +
 MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |   5 +
 MdePkg/Library/BaseLib/BaseLib.inf |   2 +-
 MdePkg/Include/Library/BaseLib.h   |  53 ++
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c| 181 
+++-
 MdePkg/Include/RiscV64/RiscVasm.inc|  19 ++
 MdePkg/Library/BaseLib/RiscV64/FlushCache.S|  21 ---
 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S|  38 
 MdePkg/MdePkg.uni  |   4 +
 10 files changed, 270 insertions(+), 62 deletions(-)
 create mode 100644 MdePkg/Include/RiscV64/RiscVasm.inc
 delete mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
 create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S

-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#112478): https://edk2.groups.io/g/devel/message/112478
Mute This Topic: https://groups.io/mt/103150381/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v9 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V

[Dhaval Sharma]

Thanks for the review. My comments inline:

On Fri, Dec 8, 2023 at 9:58 AM Sunil V L  wrote:

> On Thu, Dec 07, 2023 at 10:31:48AM +0530, Dhaval Sharma wrote:
> > Comments inline:
> >
> >
> > On Wed, Dec 6, 2023 at 7:50 PM Sunil V L 
> wrote:
> >
> > > Hi Dhaval,
> > >
> > > Thank you very much for fixing the issue with instruction cache
> > > invalidation and confirming with the spec owner. Few minor comments
> > > below.
> > >
> > > On Mon, Dec 04, 2023 at 01:59:49PM +0530, Dhaval Sharma wrote:
> > > > Use newly defined cache management operations for RISC-V where
> possible
> > > > It builds up on the support added for RISC-V cache management
> > > > instructions in BaseLib.
> > > > Cc: Michael D Kinney 
> > > > Cc: Liming Gao 
> > > > Cc: Zhiguang Liu 
> > > > Cc: Laszlo Ersek 
> > > >
> > > > Signed-off-by: Dhaval Sharma 
> > > > Acked-by: Laszlo Ersek 
> > > > ---
> > > >
> > > > Notes:
> > > > V9:
> > > > - Fixed an issue with Instruction cache invalidation. Use fence.i
> > > >   instruction as CMO does not support i-cache operations.
> > > > V8:
> > > > - Added note to convert PCD into RISC-V feature bitmap pointer
> > > > - Modified function names to be more explicit about cache ops
> > > > - Added RB tag
> > > > V7:
> > > > - Added PcdLib
> > > > - Restructure DEBUG message based on feedback on V6
> > > > - Make naming consistent to CMO, remove all CBO references
> > > > - Add ASSERT for not supported functions instead of plain debug
> > > message
> > > > - Added RB tag
> > > > V6:
> > > > - Utilize cache management instructions if HW supports it
> > > >   This patch is part of restructuring on top of v5
> > > >
> > > IMO, it is better to keep the change log in the cover letter. Since not
> > > all patches may be CC'd to every one apart from the cover letter, it is
> > > difficult to understand from the cover letter what has changed in the
> new
> > > series.
> > >
> > [Dhaval] AFAIU notes are tied to specific commits. But it makes sense, I
> > can add an update to the cover letter.
> >
> > >
> > > >  MdePkg/MdePkg.dec  |
> > >  8 +
> > > >  MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |
> > >  5 +
> > > >  MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c|
> > > 173 
> > > >  MdePkg/MdePkg.uni  |
> > >  4 +
> > > >  4 files changed, 160 insertions(+), 30 deletions(-)
> > > >
> > > > diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
> > > > index ac54338089e8..fa92673ff633 100644
> > > > --- a/MdePkg/MdePkg.dec
> > > > +++ b/MdePkg/MdePkg.dec
> > > > @@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64,
> > > PcdsPatchableInModule.AARCH64]
> > > ># @Prompt CPU Rng algorithm's GUID.
> > > >
> > >
> gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x0037
> > > >
> > > > +[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64]
> > > > +  #
> > > > +  # Configurability to override RISC-V CPU Features
> > > > +  # BIT 0 = Cache Management Operations. This bit is relevant only
> if
> > > > +  # previous stage has feature enabled and user wants to disable it.
> > > > +  #
> > > > +
> > >
> gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0x|UINT64|0x69
> > > > +
> > > >  [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic,
> PcdsDynamicEx]
> > > >## This value is used to set the base address of PCI express
> > > hierarchy.
> > > ># @Prompt PCI Express Base Address.
> > > > diff --git
> > > a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> > > b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> > > > index 6fd9cbe5f6c9..601a38d6c109 100644
> > > > ---
> a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> > > > +++
>

Re: [edk2-devel] [PATCH v9 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V

[Dhaval Sharma]

Comments inline:


On Wed, Dec 6, 2023 at 7:50 PM Sunil V L  wrote:

> Hi Dhaval,
>
> Thank you very much for fixing the issue with instruction cache
> invalidation and confirming with the spec owner. Few minor comments
> below.
>
> On Mon, Dec 04, 2023 at 01:59:49PM +0530, Dhaval Sharma wrote:
> > Use newly defined cache management operations for RISC-V where possible
> > It builds up on the support added for RISC-V cache management
> > instructions in BaseLib.
> > Cc: Michael D Kinney 
> > Cc: Liming Gao 
> > Cc: Zhiguang Liu 
> > Cc: Laszlo Ersek 
> >
> > Signed-off-by: Dhaval Sharma 
> > Acked-by: Laszlo Ersek 
> > ---
> >
> > Notes:
> > V9:
> > - Fixed an issue with Instruction cache invalidation. Use fence.i
> >   instruction as CMO does not support i-cache operations.
> > V8:
> > - Added note to convert PCD into RISC-V feature bitmap pointer
> > - Modified function names to be more explicit about cache ops
> > - Added RB tag
> > V7:
> > - Added PcdLib
> > - Restructure DEBUG message based on feedback on V6
> > - Make naming consistent to CMO, remove all CBO references
> > - Add ASSERT for not supported functions instead of plain debug
> message
> > - Added RB tag
> > V6:
> > - Utilize cache management instructions if HW supports it
> >   This patch is part of restructuring on top of v5
> >
> IMO, it is better to keep the change log in the cover letter. Since not
> all patches may be CC'd to every one apart from the cover letter, it is
> difficult to understand from the cover letter what has changed in the new
> series.
>
[Dhaval] AFAIU notes are tied to specific commits. But it makes sense, I
can add an update to the cover letter.

>
> >  MdePkg/MdePkg.dec  |
>  8 +
> >  MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |
>  5 +
> >  MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c|
> 173 
> >  MdePkg/MdePkg.uni  |
>  4 +
> >  4 files changed, 160 insertions(+), 30 deletions(-)
> >
> > diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
> > index ac54338089e8..fa92673ff633 100644
> > --- a/MdePkg/MdePkg.dec
> > +++ b/MdePkg/MdePkg.dec
> > @@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64,
> PcdsPatchableInModule.AARCH64]
> ># @Prompt CPU Rng algorithm's GUID.
> >
> gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x0037
> >
> > +[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64]
> > +  #
> > +  # Configurability to override RISC-V CPU Features
> > +  # BIT 0 = Cache Management Operations. This bit is relevant only if
> > +  # previous stage has feature enabled and user wants to disable it.
> > +  #
> > +
> gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0x|UINT64|0x69
> > +
> >  [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
> >## This value is used to set the base address of PCI express
> hierarchy.
> ># @Prompt PCI Express Base Address.
> > diff --git
> a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> > index 6fd9cbe5f6c9..601a38d6c109 100644
> > --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> > @@ -56,3 +56,8 @@ [LibraryClasses]
> >BaseLib
> >DebugLib
> >
> > +[LibraryClasses.RISCV64]
> > +  PcdLib
> > +
> > +[Pcd.RISCV64]
> > +  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride  ## CONSUMES
> > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> > index ac2a3c23a249..cacc38eff4f4 100644
> > --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> > @@ -2,6 +2,7 @@
> >RISC-V specific functionality for cache.
> >
> >Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All
> rights reserved.
> > +  Copyright (c) 2023, Rivos Inc. All rights reserved.
> >
> >SPDX-License-Identifier: BSD-2-Clause-Patent
> >  **/
> > @@ -9,10 +10,117 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> &

[edk2-devel] [PATCH v9 5/5] OvmfPkg/RiscVVirt: Override for RV CPU Features

[Dhaval Sharma]

This PCD provides a way for platform to override any
HW features that are default enabled by previous stages
of FW (like OpenSBI). For the case where previous/prev
stage has disabled the feature, this override is not
useful and its usage should be avoided.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Sunil V L 
Cc: Andrei Warkentin 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
Acked-by: Laszlo Ersek 
Reviewed-by: Andrei Warkentin 
---

Notes:
V8:
- Added RV tag
V7:
- Added RB tag
v6:
- Modify PCD name according to changes made in Baselib implementation
V5:
- Introduce PCD for platform

 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc 
b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
index fe320525153f..5d66f7fe6ae6 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
+++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
@@ -203,6 +203,7 @@ [PcdsFeatureFlag]
   gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
 
 [PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0
   gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|100
   gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|100
   gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#112023): https://edk2.groups.io/g/devel/message/112023
Mute This Topic: https://groups.io/mt/102967059/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v9 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V

[Dhaval Sharma]

Use newly defined cache management operations for RISC-V where possible
It builds up on the support added for RISC-V cache management
instructions in BaseLib.
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
Acked-by: Laszlo Ersek 
---

Notes:
V9:
- Fixed an issue with Instruction cache invalidation. Use fence.i
  instruction as CMO does not support i-cache operations.
V8:
- Added note to convert PCD into RISC-V feature bitmap pointer
- Modified function names to be more explicit about cache ops
- Added RB tag
V7:
- Added PcdLib
- Restructure DEBUG message based on feedback on V6
- Make naming consistent to CMO, remove all CBO references
- Add ASSERT for not supported functions instead of plain debug message
- Added RB tag
V6:
- Utilize cache management instructions if HW supports it
  This patch is part of restructuring on top of v5

 MdePkg/MdePkg.dec  |   8 +
 MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |   5 +
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c| 173 

 MdePkg/MdePkg.uni  |   4 +
 4 files changed, 160 insertions(+), 30 deletions(-)

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index ac54338089e8..fa92673ff633 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AARCH64]
   # @Prompt CPU Rng algorithm's GUID.
   
gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x0037
 
+[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64]
+  #
+  # Configurability to override RISC-V CPU Features
+  # BIT 0 = Cache Management Operations. This bit is relevant only if
+  # previous stage has feature enabled and user wants to disable it.
+  #
+  
gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0x|UINT64|0x69
+
 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
   ## This value is used to set the base address of PCI express hierarchy.
   # @Prompt PCI Express Base Address.
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf 
b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
index 6fd9cbe5f6c9..601a38d6c109 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
@@ -56,3 +56,8 @@ [LibraryClasses]
   BaseLib
   DebugLib
 
+[LibraryClasses.RISCV64]
+  PcdLib
+
+[Pcd.RISCV64]
+  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride  ## CONSUMES
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index ac2a3c23a249..cacc38eff4f4 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -2,6 +2,7 @@
   RISC-V specific functionality for cache.
 
   Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+  Copyright (c) 2023, Rivos Inc. All rights reserved.
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -9,10 +10,117 @@
 #include 
 #include 
 #include 
+#include 
+
+//
+// TODO: Grab cache block size and make Cache Management Operation
+// enabling decision based on RISC-V CPU HOB in
+// future when it is available and convert PcdRiscVFeatureOverride
+// PCD to a pointer that contains pointer to bitmap structure
+// which can be operated more elegantly.
+//
+#define RISCV_CACHE_BLOCK_SIZE 64
+#define RISCV_CPU_FEATURE_CMO_BITMASK  0x1
+
+typedef enum {
+  CacheOpClean,
+  CacheOpFlush,
+  CacheOpInvld,
+} CACHE_OP;
+
+/**
+Verify CBOs are supported by this HW
+TODO: Use RISC-V CPU HOB once available.
+
+**/
+STATIC
+BOOLEAN
+RiscVIsCMOEnabled (
+  VOID
+  )
+{
+  // If CMO is disabled in HW, skip Override check
+  // Otherwise this PCD can override settings
+  return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_CMO_BITMASK) 
!= 0);
+}
+
+/**
+  Performs required opeartion on cache lines in the cache coherency domain
+  of the calling CPU. If Address is not aligned on a cache line boundary,
+  then entire cache line containing Address is operated. If Address + Length
+  is not aligned on a cache line boundary, then the entire cache line
+  containing Address + Length -1 is operated.
+  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+  @param  Address The base address of the cache lines to
+  invalidate.
+  @param  Length  The number of bytes to invalidate from the instruction
+  cache.
+  @param  Op  Type of CMO operation to be performed
+  @return Address.
+
+**/
+STATIC
+VOID
+CacheOpCacheRange (
+  IN VOID  *Address,
+  IN UINTN Length,
+  IN CACH

[edk2-devel] [PATCH v9 3/5] MdePkg: Implement RISC-V Cache Management Operations

[Dhaval Sharma]

Implement Cache Management Operations (CMO) defined by
RISC-V spec https://github.com/riscv/riscv-CMOs.

Notes:
1. CMO only supports block based Operations. Meaning cache
   flush/invd/clean Operations are not available for the entire
   range. In that case we fallback on fence.i instructions.
2. Operations are implemented using Opcodes to make them compiler
   independent. binutils 2.39+ compilers support CMO instructions.

Test:
1. Ensured correct instructions are refelecting in asm
2. Qemu implements basic support for CMO operations in that it allwos
   instructions without exceptions. Verified it works properly in
   that sense.
3. SG2042Pkg implements CMO-like instructions. It was verified that
   CpuFlushCpuDataCache works fine. This more of less
   confirms that framework is alright.
4. TODO: Once Silicon is available with exact instructions, we will
   further verify this.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Sunil V L 
Cc: Daniel Schaefer 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
Reviewed-by: Laszlo Ersek 
Reviewed-by: Sunil V L 
Reviewed-by: Jingyu Li 
---

Notes:
v8:
- Add *asm* postfix to cmo functions
- Add reviewed by tags
V7:
- Modify instruction names as per feedback from V6
- Added RB
V6:
- Implement Cache management instructions in Baselib

 MdePkg/Library/BaseLib/BaseLib.inf|  2 +-
 MdePkg/Include/Library/BaseLib.h  | 33 

 MdePkg/Include/RiscV64/RiscVasm.inc   | 19 
+++
 MdePkg/Library/BaseLib/RiscV64/{FlushCache.S => RiscVCacheMgmt.S} | 17 
++
 4 files changed, 70 insertions(+), 1 deletion(-)

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
b/MdePkg/Library/BaseLib/BaseLib.inf
index 03c7b02e828b..53389389448c 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -400,7 +400,7 @@ [Sources.RISCV64]
   RiscV64/RiscVCpuBreakpoint.S  | GCC
   RiscV64/RiscVCpuPause.S   | GCC
   RiscV64/RiscVInterrupt.S  | GCC
-  RiscV64/FlushCache.S  | GCC
+  RiscV64/RiscVCacheMgmt.S  | GCC
   RiscV64/CpuScratch.S  | GCC
   RiscV64/ReadTimer.S   | GCC
   RiscV64/RiscVMmu.S| GCC
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index d80e27285424..47424709cd72 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -226,6 +226,39 @@ RiscVInvalidateDataCacheFenceAsm (
   VOID
   );
 
+/**
+  RISC-V flush cache block. Atomically perform a clean operation
+  followed by an invalidate operation
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheFlushCmoAsm (
+  IN UINTN
+  );
+
+/**
+Perform a write transfer to another cache or to memory if the
+data in the copy of the cache block have been modified by a store
+operation
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheCleanCmoAsm (
+  IN UINTN
+  );
+
+/**
+Deallocate the copy of the cache block
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheInvalCmoAsm (
+  IN UINTN
+  );
+
 #endif // defined (MDE_CPU_RISCV64)
 
 #if defined (MDE_CPU_LOONGARCH64)
diff --git a/MdePkg/Include/RiscV64/RiscVasm.inc 
b/MdePkg/Include/RiscV64/RiscVasm.inc
new file mode 100644
index ..29de7358855c
--- /dev/null
+++ b/MdePkg/Include/RiscV64/RiscVasm.inc
@@ -0,0 +1,19 @@
+/*
+ *
+ * RISC-V cache operation encoding.
+ * Copyright (c) 2023, Rivos Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ */
+
+.macro RISCVCMOFLUSH
+.word 0x25200f
+.endm
+
+.macro RISCVCMOINVALIDATE
+.word 0x05200f
+.endm
+
+.macro RISCVCMOCLEAN
+.word 0x15200f
+.endm
diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S 
b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
similarity index 56%
rename from MdePkg/Library/BaseLib/RiscV64/FlushCache.S
rename to MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
index 8cfb85097996..4752aa72d95e 100644
--- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
@@ -3,10 +3,12 @@
 // RISC-V cache operation.
 //
 // Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+// Copyright (c) 2023, Rivos Inc. All rights reserved.
 //
 // SPDX-License-Identifier: BSD-2-Clause-Patent
 //
 
//--
+.include "RiscVasm.inc"
 
 .align 3
 ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheFenceAsm)
@@ -19,3 +21,18 @@ ASM_PFX(RiscVInvalidateInstCacheFenceAsm):
 ASM_PFX(RiscVInvalidateDataCacheFenceAsm):
 fence
 ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheFlushCmoAsm)
+ASM_PFX (RiscVCpuCacheFlushCmoAsm):
+RISCVCMOFLUSH
+ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheCleanCmoAsm)
+ASM_PFX (RiscVCpuCacheCleanCmoAsm):
+RISCVCMOCLEAN
+ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheInvalCmoAsm)
+ASM_PFX (RiscVCpuCacheInvalCmoAsm):
+RISCVCMOINVALI

[edk2-devel] [PATCH v9 2/5] MdePkg: Rename Cache Management Function To Clarify Fence Based Op

[Dhaval Sharma]

There are different ways to manage cache on RISC-V Processors.
One way is to use fence instruction. Another way is to use CPU
specific cache management operation instructions ratified as
per RISC-V ISA specifications to be introduced in future
patches. Current method is fence instruction based, rename the
function accordingly to add that clarity.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Sunil V L 
Cc: Daniel Schaefer 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
Reviewed-by: Laszlo Ersek 
---

Notes:
V8:
- Update function name to udpate *asm* in the end
V7:
- Add RB tag
V6:
- As part of restructuring, adding cache instruction differentiation
  in function naming

 MdePkg/Include/Library/BaseLib.h| 4 ++--
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 4 ++--
 MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 8 
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 7142bbfa42f2..d80e27285424 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -212,7 +212,7 @@ RiscVClearPendingTimerInterrupt (
 **/
 VOID
 EFIAPI
-RiscVInvalidateInstCacheAsm (
+RiscVInvalidateInstCacheFenceAsm (
   VOID
   );
 
@@ -222,7 +222,7 @@ RiscVInvalidateInstCacheAsm (
 **/
 VOID
 EFIAPI
-RiscVInvalidateDataCacheAsm (
+RiscVInvalidateDataCacheFenceAsm (
   VOID
   );
 
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index d5efcf49a4bf..ac2a3c23a249 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -21,7 +21,7 @@ InvalidateInstructionCache (
   VOID
   )
 {
-  RiscVInvalidateInstCacheAsm ();
+  RiscVInvalidateInstCacheFenceAsm ();
 }
 
 /**
@@ -193,7 +193,7 @@ InvalidateDataCache (
   VOID
   )
 {
-  RiscVInvalidateDataCacheAsm ();
+  RiscVInvalidateDataCacheFenceAsm ();
 }
 
 /**
diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S 
b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
index 7c10fdd268af..8cfb85097996 100644
--- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
+++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
@@ -9,13 +9,13 @@
 
//--
 
 .align 3
-ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
-ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
+ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheFenceAsm)
+ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheFenceAsm)
 
-ASM_PFX(RiscVInvalidateInstCacheAsm):
+ASM_PFX(RiscVInvalidateInstCacheFenceAsm):
 fence.i
 ret
 
-ASM_PFX(RiscVInvalidateDataCacheAsm):
+ASM_PFX(RiscVInvalidateDataCacheFenceAsm):
 fence
 ret
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#112020): https://edk2.groups.io/g/devel/message/112020
Mute This Topic: https://groups.io/mt/102967049/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v9 1/5] MdePkg: Move RISC-V Cache Management Declarations Into BaseLib

[Dhaval Sharma]

The declarations for cache Management functions belong to BaseLib
instead of instance source file. This helps with further restructuring
of cache management code for RISC-V.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
Reviewed-by: Laszlo Ersek 
---

Notes:
V7:
- Added RB tag
V6:
- Move cache management function declaration in baselib where it belongs

 MdePkg/Include/Library/BaseLib.h| 20 
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 20 
 2 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 5d7067ee854e..7142bbfa42f2 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -206,6 +206,26 @@ RiscVClearPendingTimerInterrupt (
   VOID
   );
 
+/**
+  RISC-V invalidate instruction cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateInstCacheAsm (
+  VOID
+  );
+
+/**
+  RISC-V invalidate data cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateDataCacheAsm (
+  VOID
+  );
+
 #endif // defined (MDE_CPU_RISCV64)
 
 #if defined (MDE_CPU_LOONGARCH64)
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index d08fb9f193ca..d5efcf49a4bf 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -10,26 +10,6 @@
 #include 
 #include 
 
-/**
-  RISC-V invalidate instruction cache.
-
-**/
-VOID
-EFIAPI
-RiscVInvalidateInstCacheAsm (
-  VOID
-  );
-
-/**
-  RISC-V invalidate data cache.
-
-**/
-VOID
-EFIAPI
-RiscVInvalidateDataCacheAsm (
-  VOID
-  );
-
 /**
   Invalidates the entire instruction cache in cache coherency domain of the
   calling CPU.
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#112019): https://edk2.groups.io/g/devel/message/112019
Mute This Topic: https://groups.io/mt/102967045/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v9 0/5] Cache Management Operations Support For RISC-V

[Dhaval Sharma]

Implementing code to support Cache Management Operations (CMO) defined by
RISC-V CMO instructions.https://github.com/riscv/riscv-CMOs
This is a re-write of original series v5.
The patchset contains 5 patches- created based on V5 feedback.
1. Restructuring of existing code and move instruction declarations into BaseLib
2. Renaming existing functions to denote type of instruction used to maanage 
cache.
   This is useful for further patches where more cache management instructions 
are added.
3. Add the new cache maintenance operations to BaseLib, including the
 new assembly instruction encodings.
4. Update BaseCacheMaintenanceLib (utilizing the new BaseLib primitives)
5. Add platform level PCD to allow overriding of RISC-V features.

Code Link: https://github.com/tianocore/edk2/pull/5103

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Sunil V L 
Cc: Andrei Warkentin 
Cc: Laszlo Ersek 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Daniel Schaefer 


Dhaval (5):
  MdePkg: Move RISC-V Cache Management Declarations Into BaseLib
  MdePkg: Rename Cache Management Function To Clarify Fence Based Op
  MdePkg: Implement RISC-V Cache Management Operations
  MdePkg: Utilize Cache Management Operations Implementation For RISC-V
  OvmfPkg/RiscVVirt: Override for RV CPU Features

 MdePkg/MdePkg.dec  |   8 +
 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc|   1 +
 MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |   5 +
 MdePkg/Library/BaseLib/BaseLib.inf |   2 +-
 MdePkg/Include/Library/BaseLib.h   |  53 ++
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c| 177 
+++-
 MdePkg/Include/RiscV64/RiscVasm.inc|  19 +++
 MdePkg/Library/BaseLib/RiscV64/FlushCache.S|  21 ---
 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S|  38 +
 MdePkg/MdePkg.uni  |   4 +
 10 files changed, 264 insertions(+), 64 deletions(-)
 create mode 100644 MdePkg/Include/RiscV64/RiscVasm.inc
 delete mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
 create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S

-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#112018): https://edk2.groups.io/g/devel/message/112018
Mute This Topic: https://groups.io/mt/102967044/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v4 1/1] MdeModulePkg/AcpiTableDxe: Prefer xDSDT over DSDT when installing tables

[Dhaval Sharma]

As per ACPI Spec 6.5+ Table 5-9 if xDSDT is available,
it should be used first. Handle required flow when xDSDT
is absent or present.

Test: Tested on RISCV64 Qemu platform with xDSDT and booted to
linux kernel.

Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Dandan Bi 
Signed-off-by: Dhaval Sharma 
Acked-by: Chasel Chiu 
---

Notes:
v4:
- Fix typos and commit message adding more clarity to patch subject
v3:
- Added description of ACPI spec clarification based on which this patch is 
created
- Optimizing if-else flow
v2:
- Added proper indentation for else if

 MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 23 
++--
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c 
b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
index e09bc9b704f5..61af6047a2a7 100644
--- a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
+++ b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
@@ -1892,14 +1892,23 @@ InstallAcpiTableFromHob (
   }
 }
 
-if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->Dsdt != 
0) {
+//
+// First check if xDSDT is available, as that is preferred as per
+// ACPI Spec 6.5+ Table 5-9 X_DSDT definition
+//
+if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->XDsdt 
!= 0) {
+  TableToInstall = (VOID 
*)(UINTN)((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->XDsdt;
+} else if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE 
*)ChildTable)->Dsdt != 0) {
   TableToInstall = (VOID 
*)(UINTN)((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->Dsdt;
-  Status = AddTableToList (AcpiTableInstance, TableToInstall, 
TRUE, Version, TRUE, );
-  if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "InstallAcpiTableFromHob: Fail to add ACPI 
table DSDT\n"));
-ASSERT_EFI_ERROR (Status);
-break;
-  }
+} else {
+  break;
+}
+
+Status = AddTableToList (AcpiTableInstance, TableToInstall, TRUE, 
Version, TRUE, );
+if (EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_ERROR, "InstallAcpiTableFromHob: Fail to add ACPI 
table DSDT\n"));
+  ASSERT_EFI_ERROR (Status);
+  break;
 }
   }
 }
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#112003): https://edk2.groups.io/g/devel/message/112003
Mute This Topic: https://groups.io/mt/102965684/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v4 0/1] Prefer XDSDT table over DSDT if available

[Dhaval Sharma]

Enable detection of XDSDT table from ACPI HOB and use it to comply
with ACPI spec 6.5+ Table 5-9.

Dhaval (1):
  MdeModulePkg/AcpiTableDxe: Prefer xDSDT over DSDT when installing
tables

 MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 23 
++--
 1 file changed, 16 insertions(+), 7 deletions(-)

-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#112002): https://edk2.groups.io/g/devel/message/112002
Mute This Topic: https://groups.io/mt/102965679/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v2 1/1] MdeModulePkg: Fix issue with ACPI table creation

[Dhaval Sharma]

Sent an updated patch already.

On Sat, Nov 18, 2023 at 3:27 AM Laszlo Ersek  wrote:

> On 11/17/23 18:50, Chiu, Chasel wrote:
> >
> > Hi Dhaval,
> >
> > Just a small feedback,
> > the only difference will be TableToInstall between XDsdt and Dsdt, could
> we optimize the code flow to reduce duplicate lines?
>
> since a v3 is being requested, let me ask for even more:
>
> - can we specify the precise ACPI spec location in the commit message?
>
> - s/abscent/absent/
>
> thanks!
> Laszlo
>
> >
> > Thanks,
> > Chasel
> >
> >
> >> -Original Message-
> >> From: devel@edk2.groups.io  On Behalf Of Dhaval
> >> Sharma
> >> Sent: Friday, November 17, 2023 3:35 AM
> >> To: devel@edk2.groups.io
> >> Cc: Gao, Liming ; Liu, Zhiguang
> >> ; Bi, Dandan 
> >> Subject: [edk2-devel] [PATCH v2 1/1] MdeModulePkg: Fix issue with ACPI
> table
> >> creation
> >>
> >> As per spec if xDSDT is avaialble, it should be used first.
> >> Handle required flow when xDSDT is abscent or present.
> >>
> >> Test: Tested on RISCV64 Qemu platform with xDSDT and booted to linux
> kernel.
> >>
> >> Cc: Liming Gao 
> >> Cc: Zhiguang Liu 
> >> Cc: Dandan Bi 
> >> Signed-off-by: Dhaval Sharma 
> >> ---
> >>
> >> Notes:
> >> v2:
> >> - Added proper indentation for else if
> >>
> >>  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 13
> >> -
> >>  1 file changed, 12 insertions(+), 1 deletion(-)
> >>
> >> diff --git
> a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
> >> b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
> >> index e09bc9b704f5..11097ed4c3be 100644
> >> --- a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
> >> +++ b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
> >> @@ -1892,7 +1892,18 @@ InstallAcpiTableFromHob (
> >>} } -if
> (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE
> >> *)ChildTable)->Dsdt != 0) {+//+// First check if xDSDT
> is available that is
> >> preferred+//+if
> (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE
> >> *)ChildTable)->XDsdt != 0) {+  TableToInstall = (VOID
> >> *)(UINTN)((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)-
> >>> XDsdt;+  Status = AddTableToList (AcpiTableInstance,
> TableToInstall,
> >> TRUE, Version, TRUE, );+  if (EFI_ERROR (Status)) {+
>   DEBUG
> >> ((DEBUG_ERROR, "InstallAcpiTableFromHob: Fail to add ACPI table
> xDSDT\n"));+
> >> ASSERT_EFI_ERROR (Status);+break;+  }+}
> else if
> >> (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->Dsdt != 0)
> >> {   TableToInstall = (VOID
> >> *)(UINTN)((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)-
> >>> Dsdt;   Status = AddTableToList (AcpiTableInstance,
> TableToInstall,
> >> TRUE, Version, TRUE, );   if (EFI_ERROR (Status)) {--
> >> 2.39.2
> >>
> >>
> >>
> >> -=-=-=-=-=-=
> >> Groups.io Links: You receive all messages sent to this group.
> >> View/Reply Online (#111395):
> https://edk2.groups.io/g/devel/message/111395
> >> Mute This Topic: https://groups.io/mt/102645488/1777047
> >> Group Owner: devel+ow...@edk2.groups.io
> >> Unsubscribe: https://edk2.groups.io/g/devel/unsub [
> chasel.c...@intel.com] -=-
> >> =-=-=-=-=
> >>
> >
> >
> >
> > 
> >
> >
>
>

-- 
Thanks!
=D


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#111809): https://edk2.groups.io/g/devel/message/111809
Mute This Topic: https://groups.io/mt/102645488/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH V3 0/4] Add New Memory Attributes

[Dhaval Sharma]

Did you mean to add it as a memory type by itself like
EFI_MEMORY_TYPE_INFORMATION?
My interpretation of Memory Type is that it is more of SW usability
construct while Memory Attr is more of HW behavioural construct. Together
they define how a memory region can be used.

On Fri, Nov 17, 2023 at 1:55 PM Laszlo Ersek  wrote:

> On 11/17/23 09:07, Dhaval Sharma wrote:
> > Hi,
> > I wanted to revisit this thread and I am maintaining the context as
> > there are a lot of details already mentioned here
> regarding EFI_MEMORY_SP.
> > Other than what has been addressed here, we also would like to have an
> > option in edk2 to *avoid* using this type of memory for its own
> > purposes. This seems like one of the motivations for original request
> > and is being honored by OS today but not edk2 as it does not have any
> > specific implementation today which takes this attribute into
> consideration.
> > I would like to add PCD based implementation which informs edk2 NOT to
> > use this memory for its own purposes and leave it alone (as still
> > available memory to OS).
> >
> > Specific-purpose memory (SPM). The memory is earmarked for
> > specific purposes such as for specific device drivers or applications.
> > The SPM attribute serves as a hint to the OS to avoid allocating this
> > memory for core OS data or code that can not be relocated.
> > Prolonged use of this memory for purposes other than the intended
> > purpose may result in suboptimal platform performance.
> >
> > Some more context:
> > https://lwn.net/Articles/784971/
>
> Why was EFI_MEMORY_SP introduced as a memory attribute, rather than its
> own memory type?
>
> Laszlo
>
>

-- 
Thanks!
=D


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#111457): https://edk2.groups.io/g/devel/message/111457
Mute This Topic: https://groups.io/mt/75267363/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v3 1/1] MdeModulePkg: Fix issue with ACPI table creation

[Dhaval Sharma]

As per ACPI Spec 6.5+ Table 5-9 if xDSDT is avaialble,
it should be used first. Handle required flow when xDSDT
is abscent or present.

Test: Tested on RISCV64 Qemu platform with xDSDT and booted to
linux kernel.

Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Dandan Bi 
Signed-off-by: Dhaval Sharma 
---

Notes:
v2:
- Added proper indentation for else if

 MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 22 
+---
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c 
b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
index e09bc9b704f5..ead8376177c9 100644
--- a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
+++ b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
@@ -1892,14 +1892,22 @@ InstallAcpiTableFromHob (
   }
 }
 
-if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->Dsdt != 
0) {
+//
+// First check if xDSDT is available that is preferred as per
+// ACPI Spec 6.5+ Table 5-9 X_DSDT definition
+//
+if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->XDsdt 
!= 0) {
+  TableToInstall = (VOID 
*)(UINTN)((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->XDsdt;
+} else if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE 
*)ChildTable)->Dsdt != 0) {
   TableToInstall = (VOID 
*)(UINTN)((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->Dsdt;
-  Status = AddTableToList (AcpiTableInstance, TableToInstall, 
TRUE, Version, TRUE, );
-  if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "InstallAcpiTableFromHob: Fail to add ACPI 
table DSDT\n"));
-ASSERT_EFI_ERROR (Status);
-break;
-  }
+} else {
+  break;
+}
+Status = AddTableToList (AcpiTableInstance, TableToInstall, TRUE, 
Version, TRUE, );
+if (EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_ERROR, "InstallAcpiTableFromHob: Fail to add ACPI 
table DSDT\n"));
+  ASSERT_EFI_ERROR (Status);
+  break;
 }
   }
 }
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#111451): https://edk2.groups.io/g/devel/message/111451
Mute This Topic: https://groups.io/mt/102702109/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v3 0/1] Add support for XDSDT table

[Dhaval Sharma]

Enable detection of XDSDT table from ACPI HOB and use it to comply
with ACPI spec 6.5+ Table 5-9.

Dhaval (1):
  MdeModulePkg: Fix issue with ACPI table creation

 MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 22 
+---
 1 file changed, 15 insertions(+), 7 deletions(-)

-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#111450): https://edk2.groups.io/g/devel/message/111450
Mute This Topic: https://groups.io/mt/102702075/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v3 1/1] MdeModulePkg: Fix issue with ACPI table creation

[Dhaval Sharma]

As per ACPI Spec 6.5+ Table 5-9 if xDSDT is avaialble,
it should be used first. Handle required flow when xDSDT
is abscent or present.

Test: Tested on RISCV64 Qemu platform with xDSDT and booted to
linux kernel.

Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Dandan Bi 
Signed-off-by: Dhaval Sharma 
---

Notes:
v2:
- Added proper indentation for else if

 MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 22 
+---
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c 
b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
index e09bc9b704f5..ead8376177c9 100644
--- a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
+++ b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
@@ -1892,14 +1892,22 @@ InstallAcpiTableFromHob (
   }
 }
 
-if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->Dsdt != 
0) {
+//
+// First check if xDSDT is available that is preferred as per
+// ACPI Spec 6.5+ Table 5-9 X_DSDT definition
+//
+if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->XDsdt 
!= 0) {
+  TableToInstall = (VOID 
*)(UINTN)((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->XDsdt;
+} else if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE 
*)ChildTable)->Dsdt != 0) {
   TableToInstall = (VOID 
*)(UINTN)((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->Dsdt;
-  Status = AddTableToList (AcpiTableInstance, TableToInstall, 
TRUE, Version, TRUE, );
-  if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "InstallAcpiTableFromHob: Fail to add ACPI 
table DSDT\n"));
-ASSERT_EFI_ERROR (Status);
-break;
-  }
+} else {
+  break;
+}
+Status = AddTableToList (AcpiTableInstance, TableToInstall, TRUE, 
Version, TRUE, );
+if (EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_ERROR, "InstallAcpiTableFromHob: Fail to add ACPI 
table DSDT\n"));
+  ASSERT_EFI_ERROR (Status);
+  break;
 }
   }
 }
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#111449): https://edk2.groups.io/g/devel/message/111449
Mute This Topic: https://groups.io/mt/102702076/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v3 0/1] Add support for XDSDT table

[Dhaval Sharma]

Enable detection of XDSDT table from ACPI HOB and use it to comply
with ACPI spec 6.5+ Table 5-9.

Dhaval (1):
  MdeModulePkg: Fix issue with ACPI table creation

 MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 22 
+---
 1 file changed, 15 insertions(+), 7 deletions(-)

-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#111448): https://edk2.groups.io/g/devel/message/111448
Mute This Topic: https://groups.io/mt/102702075/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v2 1/1] MdeModulePkg: Fix issue with ACPI table creation

[Dhaval Sharma]

As per spec if xDSDT is avaialble, it should be used first.
Handle required flow when xDSDT is abscent or present.

Test: Tested on RISCV64 Qemu platform with xDSDT and booted to
linux kernel.

Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Dandan Bi 
Signed-off-by: Dhaval Sharma 
---

Notes:
v2:
- Added proper indentation for else if

 MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c 
b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
index e09bc9b704f5..11097ed4c3be 100644
--- a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
+++ b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
@@ -1892,7 +1892,18 @@ InstallAcpiTableFromHob (
   }
 }
 
-if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->Dsdt != 
0) {
+//
+// First check if xDSDT is available that is preferred
+//
+if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->XDsdt 
!= 0) {
+  TableToInstall = (VOID 
*)(UINTN)((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->XDsdt;
+  Status = AddTableToList (AcpiTableInstance, TableToInstall, 
TRUE, Version, TRUE, );
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "InstallAcpiTableFromHob: Fail to add ACPI 
table xDSDT\n"));
+ASSERT_EFI_ERROR (Status);
+break;
+  }
+} else if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE 
*)ChildTable)->Dsdt != 0) {
   TableToInstall = (VOID 
*)(UINTN)((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->Dsdt;
   Status = AddTableToList (AcpiTableInstance, TableToInstall, 
TRUE, Version, TRUE, );
   if (EFI_ERROR (Status)) {
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#111395): https://edk2.groups.io/g/devel/message/111395
Mute This Topic: https://groups.io/mt/102645488/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v2 0/1] Add support for XDSDT table

[Dhaval Sharma]

Enable detection of XDSDT table from ACPI HOB and use it
if it is available: https://github.com/tianocore/edk2/pull/5051

Dhaval (1):
  MdeModulePkg: Fix issue with ACPI table creation

 MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#111394): https://edk2.groups.io/g/devel/message/111394
Mute This Topic: https://groups.io/mt/102645487/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH V3 0/4] Add New Memory Attributes

[Dhaval Sharma]

Hi,
I wanted to revisit this thread and I am maintaining the context as there are a 
lot of details already mentioned here regarding EFI_MEMORY_SP.
Other than what has been addressed here, we also would like to have an option 
in edk2 to *avoid* using this type of memory for its own purposes. This seems 
like one of the motivations for original request and is being honored by OS 
today but not edk2 as it does not have any specific implementation today which 
takes this attribute into consideration.
I would like to add PCD based implementation which informs edk2 NOT to use this 
memory for its own purposes and leave it alone (as still available memory to 
OS).

Specific-purpose memory (SPM). The memory is earmarked for
specific purposes such as for specific device drivers or applications.
The SPM attribute serves as a hint to the OS to avoid allocating this
memory for core OS data or code that can not be relocated.
Prolonged use of this memory for purposes other than the intended
purpose may result in suboptimal platform performance.

Some more context:
https://lwn.net/Articles/784971/


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#111337): https://edk2.groups.io/g/devel/message/111337
Mute This Topic: https://groups.io/mt/75267363/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v8 5/5] OvmfPkg/RiscVVirt: Override for RV CPU Features

[Dhaval Sharma]

This PCD provides a way for platform to override any
HW features that are default enabled by previous stages
of FW (like OpenSBI). For the case where previous/prev
stage has disabled the feature, this override is not
useful and its usage should be avoided.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Sunil V L 
Cc: Andrei Warkentin 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
Acked-by: Laszlo Ersek 
Reviewed-by: Andrei Warkentin 
---

Notes:
V8:
- Added RV tag
V7:
- Added RB tag
v6:
- Modify PCD name according to changes made in Baselib implementation
V5:
- Introduce PCD for platform

 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc 
b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
index fe320525153f..5d66f7fe6ae6 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
+++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
@@ -203,6 +203,7 @@ [PcdsFeatureFlag]
   gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
 
 [PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0
   gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|100
   gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|100
   gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#110702): https://edk2.groups.io/g/devel/message/110702
Mute This Topic: https://groups.io/mt/102413488/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v8 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V

[Dhaval Sharma]

Use newly defined cache management operations for RISC-V where possible
It builds up on the support added for RISC-V cache management
instructions in BaseLib.
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
Acked-by: Laszlo Ersek 
---

Notes:
V8:
- Added note to convert PCD into RISC-V feature bitmap pointer
- Modified function names to be more explicit about cache ops
- Added RB tag
V7:
- Added PcdLib
- Restructure DEBUG message based on feedback on V6
- Make naming consistent to CMO, remove all CBO references
- Add ASSERT for not supported functions instead of plain debug message
- Added RB tag
V6:
- Utilize cache management instructions if HW supports it
  This patch is part of restructuring on top of v5

 MdePkg/MdePkg.dec  |   8 +
 MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |   5 +
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c| 170 
+---
 MdePkg/MdePkg.uni  |   4 +
 4 files changed, 167 insertions(+), 20 deletions(-)

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index ac54338089e8..fa92673ff633 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AARCH64]
   # @Prompt CPU Rng algorithm's GUID.
   
gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x0037
 
+[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64]
+  #
+  # Configurability to override RISC-V CPU Features
+  # BIT 0 = Cache Management Operations. This bit is relevant only if
+  # previous stage has feature enabled and user wants to disable it.
+  #
+  
gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0x|UINT64|0x69
+
 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
   ## This value is used to set the base address of PCI express hierarchy.
   # @Prompt PCI Express Base Address.
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf 
b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
index 6fd9cbe5f6c9..601a38d6c109 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
@@ -56,3 +56,8 @@ [LibraryClasses]
   BaseLib
   DebugLib
 
+[LibraryClasses.RISCV64]
+  PcdLib
+
+[Pcd.RISCV64]
+  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride  ## CONSUMES
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index ac2a3c23a249..16a09db009cd 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -2,6 +2,7 @@
   RISC-V specific functionality for cache.
 
   Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+  Copyright (c) 2023, Rivos Inc. All rights reserved.
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -9,10 +10,117 @@
 #include 
 #include 
 #include 
+#include 
+
+//
+// TODO: Grab cache block size and make Cache Management Operation
+// enabling decision based on RISC-V CPU HOB in
+// future when it is available and convert PcdRiscVFeatureOverride
+// PCD to a pointer that contains pointer to bitmap structure
+// which can be operated more elegantly.
+//
+#define RISCV_CACHE_BLOCK_SIZE 64
+#define RISCV_CPU_FEATURE_CMO_BITMASK  0x1
+
+typedef enum {
+  CacheOpClean,
+  CacheOpFlush,
+  CacheOpInvld,
+} CACHE_OP;
+
+/**
+Verify CBOs are supported by this HW
+TODO: Use RISC-V CPU HOB once available.
+
+**/
+STATIC
+BOOLEAN
+RiscVIsCMOEnabled (
+  VOID
+  )
+{
+  // If CMO is disabled in HW, skip Override check
+  // Otherwise this PCD can override settings
+  return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_CMO_BITMASK) 
!= 0);
+}
+
+/**
+  Performs required opeartion on cache lines in the cache coherency domain
+  of the calling CPU. If Address is not aligned on a cache line boundary,
+  then entire cache line containing Address is operated. If Address + Length
+  is not aligned on a cache line boundary, then the entire cache line
+  containing Address + Length -1 is operated.
+  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+  @param  Address The base address of the cache lines to
+  invalidate.
+  @param  Length  The number of bytes to invalidate from the instruction
+  cache.
+  @param  Op  Type of CMO operation to be performed
+  @return Address.
+
+**/
+STATIC
+VOID
+CacheOpCacheRange (
+  IN VOID  *Address,
+  IN UINTN Length,
+  IN CACHE_OP  Op
+  )
+{
+  UINTN  CacheLineSize;
+  UINTN  Start;
+  UINTN  End;
+
+  if (Length == 0) {
+return;
+  }
+
+  if ((Op != CacheOpI

[edk2-devel] [PATCH v8 3/5] MdePkg: Implement RISC-V Cache Management Operations

[Dhaval Sharma]

Implement Cache Management Operations (CMO) defined by
RISC-V spec https://github.com/riscv/riscv-CMOs.

Notes:
1. CMO only supports block based Operations. Meaning cache
   flush/invd/clean Operations are not available for the entire
   range. In that case we fallback on fence.i instructions.
2. Operations are implemented using Opcodes to make them compiler
   independent. binutils 2.39+ compilers support CMO instructions.

Test:
1. Ensured correct instructions are refelecting in asm
2. Qemu implements basic support for CMO operations in that it allwos
   instructions without exceptions. Verified it works properly in
   that sense.
3. SG2042Pkg implements CMO-like instructions. It was verified that
   CpuFlushCpuDataCache works fine. This more of less
   confirms that framework is alright.
4. TODO: Once Silicon is available with exact instructions, we will
   further verify this.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Sunil V L 
Cc: Daniel Schaefer 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
Reviewed-by: Laszlo Ersek 
Reviewed-by: Sunil V L 
Reviewed-by: Jingyu Li 
---

Notes:
v8:
- Add *asm* postfix to cmo functions
- Add reviewed by tags
V7:
- Modify instruction names as per feedback from V6
- Added RB
V6:
- Implement Cache management instructions in Baselib

 MdePkg/Library/BaseLib/BaseLib.inf|  2 +-
 MdePkg/Include/Library/BaseLib.h  | 33 

 MdePkg/Include/RiscV64/RiscVasm.inc   | 19 
+++
 MdePkg/Library/BaseLib/RiscV64/{FlushCache.S => RiscVCacheMgmt.S} | 17 
++
 4 files changed, 70 insertions(+), 1 deletion(-)

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
b/MdePkg/Library/BaseLib/BaseLib.inf
index 03c7b02e828b..53389389448c 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -400,7 +400,7 @@ [Sources.RISCV64]
   RiscV64/RiscVCpuBreakpoint.S  | GCC
   RiscV64/RiscVCpuPause.S   | GCC
   RiscV64/RiscVInterrupt.S  | GCC
-  RiscV64/FlushCache.S  | GCC
+  RiscV64/RiscVCacheMgmt.S  | GCC
   RiscV64/CpuScratch.S  | GCC
   RiscV64/ReadTimer.S   | GCC
   RiscV64/RiscVMmu.S| GCC
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index d80e27285424..47424709cd72 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -226,6 +226,39 @@ RiscVInvalidateDataCacheFenceAsm (
   VOID
   );
 
+/**
+  RISC-V flush cache block. Atomically perform a clean operation
+  followed by an invalidate operation
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheFlushCmoAsm (
+  IN UINTN
+  );
+
+/**
+Perform a write transfer to another cache or to memory if the
+data in the copy of the cache block have been modified by a store
+operation
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheCleanCmoAsm (
+  IN UINTN
+  );
+
+/**
+Deallocate the copy of the cache block
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheInvalCmoAsm (
+  IN UINTN
+  );
+
 #endif // defined (MDE_CPU_RISCV64)
 
 #if defined (MDE_CPU_LOONGARCH64)
diff --git a/MdePkg/Include/RiscV64/RiscVasm.inc 
b/MdePkg/Include/RiscV64/RiscVasm.inc
new file mode 100644
index ..29de7358855c
--- /dev/null
+++ b/MdePkg/Include/RiscV64/RiscVasm.inc
@@ -0,0 +1,19 @@
+/*
+ *
+ * RISC-V cache operation encoding.
+ * Copyright (c) 2023, Rivos Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ */
+
+.macro RISCVCMOFLUSH
+.word 0x25200f
+.endm
+
+.macro RISCVCMOINVALIDATE
+.word 0x05200f
+.endm
+
+.macro RISCVCMOCLEAN
+.word 0x15200f
+.endm
diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S 
b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
similarity index 56%
rename from MdePkg/Library/BaseLib/RiscV64/FlushCache.S
rename to MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
index 8cfb85097996..4752aa72d95e 100644
--- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
@@ -3,10 +3,12 @@
 // RISC-V cache operation.
 //
 // Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+// Copyright (c) 2023, Rivos Inc. All rights reserved.
 //
 // SPDX-License-Identifier: BSD-2-Clause-Patent
 //
 
//--
+.include "RiscVasm.inc"
 
 .align 3
 ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheFenceAsm)
@@ -19,3 +21,18 @@ ASM_PFX(RiscVInvalidateInstCacheFenceAsm):
 ASM_PFX(RiscVInvalidateDataCacheFenceAsm):
 fence
 ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheFlushCmoAsm)
+ASM_PFX (RiscVCpuCacheFlushCmoAsm):
+RISCVCMOFLUSH
+ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheCleanCmoAsm)
+ASM_PFX (RiscVCpuCacheCleanCmoAsm):
+RISCVCMOCLEAN
+ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheInvalCmoAsm)
+ASM_PFX (RiscVCpuCacheInvalCmoAsm):
+RISCVCMOINVALI

[edk2-devel] [PATCH v8 1/5] MdePkg: Move RISC-V Cache Management Declarations Into BaseLib

[Dhaval Sharma]

The declarations for cache Management functions belong to BaseLib
instead of instance source file. This helps with further restructuring
of cache management code for RISC-V.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
Reviewed-by: Laszlo Ersek 
---

Notes:
V7:
- Added RB tag
V6:
- Move cache management function declaration in baselib where it belongs

 MdePkg/Include/Library/BaseLib.h| 20 
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 20 
 2 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 5d7067ee854e..7142bbfa42f2 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -206,6 +206,26 @@ RiscVClearPendingTimerInterrupt (
   VOID
   );
 
+/**
+  RISC-V invalidate instruction cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateInstCacheAsm (
+  VOID
+  );
+
+/**
+  RISC-V invalidate data cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateDataCacheAsm (
+  VOID
+  );
+
 #endif // defined (MDE_CPU_RISCV64)
 
 #if defined (MDE_CPU_LOONGARCH64)
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index d08fb9f193ca..d5efcf49a4bf 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -10,26 +10,6 @@
 #include 
 #include 
 
-/**
-  RISC-V invalidate instruction cache.
-
-**/
-VOID
-EFIAPI
-RiscVInvalidateInstCacheAsm (
-  VOID
-  );
-
-/**
-  RISC-V invalidate data cache.
-
-**/
-VOID
-EFIAPI
-RiscVInvalidateDataCacheAsm (
-  VOID
-  );
-
 /**
   Invalidates the entire instruction cache in cache coherency domain of the
   calling CPU.
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#110698): https://edk2.groups.io/g/devel/message/110698
Mute This Topic: https://groups.io/mt/102413466/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v8 2/5] MdePkg: Rename Cache Management Function To Clarify Fence Based Op

[Dhaval Sharma]

There are different ways to manage cache on RISC-V Processors.
One way is to use fence instruction. Another way is to use CPU
specific cache management operation instructions ratified as
per RISC-V ISA specifications to be introduced in future
patches. Current method is fence instruction based, rename the
function accordingly to add that clarity.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Sunil V L 
Cc: Daniel Schaefer 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
Reviewed-by: Laszlo Ersek 
---

Notes:
V8:
- Update function name to udpate *asm* in the end
V7:
- Add RB tag
V6:
- As part of restructuring, adding cache instruction differentiation
  in function naming

 MdePkg/Include/Library/BaseLib.h| 4 ++--
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 4 ++--
 MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 8 
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 7142bbfa42f2..d80e27285424 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -212,7 +212,7 @@ RiscVClearPendingTimerInterrupt (
 **/
 VOID
 EFIAPI
-RiscVInvalidateInstCacheAsm (
+RiscVInvalidateInstCacheFenceAsm (
   VOID
   );
 
@@ -222,7 +222,7 @@ RiscVInvalidateInstCacheAsm (
 **/
 VOID
 EFIAPI
-RiscVInvalidateDataCacheAsm (
+RiscVInvalidateDataCacheFenceAsm (
   VOID
   );
 
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index d5efcf49a4bf..ac2a3c23a249 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -21,7 +21,7 @@ InvalidateInstructionCache (
   VOID
   )
 {
-  RiscVInvalidateInstCacheAsm ();
+  RiscVInvalidateInstCacheFenceAsm ();
 }
 
 /**
@@ -193,7 +193,7 @@ InvalidateDataCache (
   VOID
   )
 {
-  RiscVInvalidateDataCacheAsm ();
+  RiscVInvalidateDataCacheFenceAsm ();
 }
 
 /**
diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S 
b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
index 7c10fdd268af..8cfb85097996 100644
--- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
+++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
@@ -9,13 +9,13 @@
 
//--
 
 .align 3
-ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
-ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
+ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheFenceAsm)
+ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheFenceAsm)
 
-ASM_PFX(RiscVInvalidateInstCacheAsm):
+ASM_PFX(RiscVInvalidateInstCacheFenceAsm):
 fence.i
 ret
 
-ASM_PFX(RiscVInvalidateDataCacheAsm):
+ASM_PFX(RiscVInvalidateDataCacheFenceAsm):
 fence
 ret
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#110699): https://edk2.groups.io/g/devel/message/110699
Mute This Topic: https://groups.io/mt/102413467/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v8 0/5] Cache Management Operations Support For RISC-V

[Dhaval Sharma]

Implementing code to support Cache Management Operations (CMO) defined by
RISC-V CMO instructions.https://github.com/riscv/riscv-CMOs
This is a re-write of original series v5.
The patchset contains 5 patches- created based on V5 feedback.
1. Restructuring of existing code and move instruction declarations into BaseLib
2. Renaming existing functions to denote type of instruction used to maanage 
cache.
   This is useful for further patches where more cache management instructions 
are added.
3. Add the new cache maintenance operations to BaseLib, including the
 new assembly instruction encodings.
4. Update BaseCacheMaintenanceLib (utilizing the new BaseLib primitives)
5. Add platform level PCD to allow overriding of RISC-V features.

Code Link: https://github.com/tianocore/edk2/pull/5002

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Sunil V L 
Cc: Andrei Warkentin 
Cc: Laszlo Ersek 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Daniel Schaefer 

Dhaval (5):
  MdePkg: Move RISC-V Cache Management Declarations Into BaseLib
  MdePkg: Rename Cache Management Function To Clarify Fence Based Op
  MdePkg: Implement RISC-V Cache Management Operations
  MdePkg: Utilize Cache Management Operations Implementation For RISC-V
  OvmfPkg/RiscVVirt: Override for RV CPU Features

 MdePkg/MdePkg.dec  |   8 +
 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc|   1 +
 MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |   5 +
 MdePkg/Library/BaseLib/BaseLib.inf |   2 +-
 MdePkg/Include/Library/BaseLib.h   |  53 ++
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c| 174 

 MdePkg/Include/RiscV64/RiscVasm.inc|  19 +++
 MdePkg/Library/BaseLib/RiscV64/FlushCache.S|  21 ---
 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S|  38 +
 MdePkg/MdePkg.uni  |   4 +
 10 files changed, 271 insertions(+), 54 deletions(-)
 create mode 100644 MdePkg/Include/RiscV64/RiscVasm.inc
 delete mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
 create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S

-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#110697): https://edk2.groups.io/g/devel/message/110697
Mute This Topic: https://groups.io/mt/102413464/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v7 5/5] OvmfPkg/RiscVVirt: Override for RV CPU Features

[Dhaval Sharma]

Hi Andrei,
Are you suggesting:

   1. We have a generic PCD to store the address of RVFeatures bitfield.
   2. It gets populated at some point during initialization with let's say
   some kind of global variable address which keeps this bitfield.
   3. SEC/DXE phases deref this address and use where needed?

Is there a reference I can take a look at?

Assuming my above understanding is correct, the whole idea was to keep
implementation based on simple PCD such that it can be used easily as an
override mechanism. The reason to keep it "enabled" by default in MDE is
that if m-mode decides to keep it disabled it is anyways going to remain
that way. So practically this PCD is going to be useful only in cases where
the user wants to "Override Disable". LMK if you still think we should
modify the implementation.

=D

On Tue, Oct 31, 2023 at 10:31 PM Warkentin, Andrei <
andrei.warken...@intel.com> wrote:

> I think I misunderstood the intent. Reviewing the full patchset, it seems
> this is necessary to avoid using the new CMO path in the Virt platform
> (since the default value is all FFs). Shouldn’t the default Pcd value here
> be all 0’s – i.e. CMO or any other feature use becomes “opt in” instead of
> “opt out”?
>
>
>
> It also seems that encoding the meaning inside the bit positions is a bit…
> obscure. Have you considered storing a pointer to a struct with bitfields
> instead? You could then change the logic to be something like “If
> PcdPtrValue != NULL && ((struct cast *) PcdPtrValue)->LegibleFieldName”. I
> think this would do wonders for code maintainability. The cost of course is
> in having to initialize the Pcd now at runtime, and the additional
> dereference, but that seems like a low cost all things considered.
>
>
>
> *From:* Dhaval Sharma 
> *Sent:* Tuesday, October 31, 2023 1:13 AM
> *To:* Warkentin, Andrei ; devel@edk2.groups.io
> *Subject:* Re: [edk2-devel] [PATCH v7 5/5] OvmfPkg/RiscVVirt: Override
> for RV CPU Features
>
>
>
> Thanks. This PCD is for Virt platform only. Or maybe I am missing the
> point.
>


-- 
Thanks!
=D


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#110487): https://edk2.groups.io/g/devel/message/110487
Mute This Topic: https://groups.io/mt/102256471/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v7 3/5] MdePkg: Implement RISC-V Cache Management Operations

[Dhaval Sharma]

rd/SG2042.fdf
@@ -77,7 +77,7 @@ INF
Silicon/Sophgo/SG2042Pkg/Drivers/SdHostDxe/SdHostDxe.inf

 # RISC-V Core Drivers
 INF  UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
-INF
Silicon/Sophgo/SG2042Pkg/Override/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
+INF  UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf

 INF  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
 INF  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf

3. Now the PCIe devices are in work order on PioneerBox. The CMO
instructions are executed as expected.

Reviewed-by: Jingyu Li 

On Mon, Oct 30, 2023 at 10:07 PM Pedro Falcato 
wrote:

> On Mon, Oct 30, 2023 at 9:38 AM Laszlo Ersek  wrote:
> >
> > On 10/29/23 20:12, Pedro Falcato wrote:
> > > On Sun, Oct 29, 2023 at 2:46 PM Dhaval Sharma 
> wrote:
> > >>
> > >> Implement Cache Management Operations (CMO) defined by
> > >> RISC-V spec https://github.com/riscv/riscv-CMOs.
> > >>
> > >> Notes:
> > >> 1. CMO only supports block based Operations. Meaning cache
> > >>flush/invd/clean Operations are not available for the entire
> > >>range. In that case we fallback on fence.i instructions.
> > >> 2. Operations are implemented using Opcodes to make them compiler
> > >>independent. binutils 2.39+ compilers support CMO instructions.
> > >>
> > >> Test:
> > >> 1. Ensured correct instructions are refelecting in asm
> > >
> > > nit: reflecting
> > >
> > >> 2. Not able to verify actual instruction in HW as Qemu ignores
> > >>any actual cache operations.
> > >
> > > Do you have no way to test this in hardware? Since Rivos is a RISCV
> > > vendor and all ;)
> > > I don't like inviting the idea of merging CPU architectural changes
> > > without actually testing them in something resembling real silicon
> > > (i.e QEMU KVM is _fine_, QEMU TCG really isn't).
> > >
> >
> > Hopefully I'm not drawing an incorrect parallel here, but, as I recall
> > arm64 enablement in 2014, nearly all initial enablement in RHEL occurred
> > on software emulators (ARM Foundation Model, ARM FVP, then QEMU TCG).
> > You need to start somewhere. In particular, qemu-system-aarch64 was a
> > huge step forward (performance-wise) once it *existed*, relative to the
> > Foundation Model / FVP, even though qemu-system-aarch64 wouldn't emulate
> > CPU caches (IIRC).
>
> Right. I don't know how faithful those early ARM simulators were, but
> QEMU TCG is not very faithful and uarch details *can* slip through the
> cracks.
> In arm64 it's easy to miss a dsb or a isb if you're not extra careful
> (or read the ARM ARM wrong).
>
> RISCV has a bunch of fun gotchas too. For instance, did you know you
> need to flush the TLB using sfence.vma even when only mapping a page?
> This "small" detail results in boot failures on real hardware (such as
> the visionfive 2), but is completely silent in QEMU TCG.
>
> So this is why I would much prefer a test on real silicon. It's hard
> to prove correctness when all you have is QEMU's spotty simulation
> (rightfully so, it's not a simulator).
>
> --
> Pedro
>


-- 
Thanks!
=D


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#110392): https://edk2.groups.io/g/devel/message/110392
Mute This Topic: https://groups.io/mt/102256466/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v7 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V

[Dhaval Sharma]

Can we define these bits in the header file so that the definitions can
be used by multiple modules?
[Dhaval] I could put it un Baselib.h (MDE_CPU_RISCV64) but sounds like right 
now BaseLib.h is free of such #defines. If you think it is still better would 
do it. I do not have any preference.


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#110372): https://edk2.groups.io/g/devel/message/110372
Mute This Topic: https://groups.io/mt/102256468/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v7 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V

[Dhaval Sharma]

NIT: I am wondering whether PcdRiscVCpuFeatureDisable is better so that
it is explicit.
[Dhaval] Well setting it to 1 would mean feature is enabled. Do it would be 
confusing to see PcdRiscVCpuFeatureDisable == 1 means feature is enabled.


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#110370): https://edk2.groups.io/g/devel/message/110370
Mute This Topic: https://groups.io/mt/102256468/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v7 5/5] OvmfPkg/RiscVVirt: Override for RV CPU Features

[Dhaval Sharma]

Thanks. This PCD is for Virt platform only. Or maybe I am missing the point.


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#110369): https://edk2.groups.io/g/devel/message/110369
Mute This Topic: https://groups.io/mt/102256471/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v7 0/5] Cache Management Operations Support For RISC-V

[Dhaval Sharma]

Here we go. https://github.com/tianocore/edk2/pull/4974


On Tue, Oct 31, 2023 at 9:46 AM Warkentin, Andrei <
andrei.warken...@intel.com> wrote:

> Hi Dhaval,
>
> Do you mind sharing the repo with the full patch set? Like a github link?
>
> A
>
> > -Original Message-
> > From: Dhaval 
> > Sent: Sunday, October 29, 2023 9:46 AM
> > To: devel@edk2.groups.io
> > Cc: Ard Biesheuvel ; Yao, Jiewen
> > ; Justen, Jordan L ;
> Gerd
> > Hoffmann ; Sunil V L ;
> > Warkentin, Andrei ; Laszlo Ersek
> > ; Kinney, Michael D ;
> > Gao, Liming ; Liu, Zhiguang
> > ; Daniel Schaefer 
> > Subject: [PATCH v7 0/5] Cache Management Operations Support For RISC-V
> >
> > Implementing code to support Cache Management Operations (CMO) defined
> > by RISC-V CMO instructions.https://github.com/riscv/riscv-CMOs
> > This is a re-write of original series v5.
> > The patchset contains 5 patches- created based on V5 feedback.
> > 1. Restructuring of existing code and move instruction declarations into
> > BaseLib 2. Renaming existing functions to denote type of instruction
> used to
> > maanage cache.
> >This is useful for further patches where more cache management
> > instructions are added.
> > 3. Add the new cache maintenance operations to BaseLib, including the
> >new assembly instruction encodings.
> > 4. Update BaseCacheMaintenanceLib (utilizing the new BaseLib primitives)
> 5.
> > Add platform level PCD to allow overriding of RISC-V features.
> >
> > Cc: Ard Biesheuvel 
> > Cc: Jiewen Yao 
> > Cc: Jordan Justen 
> > Cc: Gerd Hoffmann 
> > Cc: Sunil V L 
> > Cc: Andrei Warkentin 
> > Cc: Laszlo Ersek 
> > Cc: Michael D Kinney 
> > Cc: Liming Gao 
> > Cc: Zhiguang Liu 
> > Cc: Daniel Schaefer 
> >
> > Dhaval (5):
> >   MdePkg: Move RISC-V Cache Management Declarations Into BaseLib
> >   MdePkg: Rename Cache Management Function To Clarify Fence Based Op
> >   MdePkg: Implement RISC-V Cache Management Operations
> >   MdePkg: Utilize Cache Management Operations Implementation For RISC-V
> >   OvmfPkg/RiscVVirt: Override for RV CPU Features
> >
> >  MdePkg/MdePkg.dec  |
>  8 +
> >  OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc|
>  1 +
> >  MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |
> > 5 +
> >  MdePkg/Library/BaseLib/BaseLib.inf |
>  2 +-
> >  MdePkg/Include/Library/BaseLib.h   |
> 53 ++
> >  MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c| 172
> > 
> >  MdePkg/Include/RiscV64/RiscVasm.inc|
> 19 +++
> >  MdePkg/Library/BaseLib/RiscV64/FlushCache.S|
> 21 ---
> >  MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S|
> 38 +
> >  MdePkg/MdePkg.uni  |
>  4 +
> >  10 files changed, 269 insertions(+), 54 deletions(-)  create mode 100644
> > MdePkg/Include/RiscV64/RiscVasm.inc
> >  delete mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> >  create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
> >
> > --
> > 2.39.2
>
>

-- 
Thanks!
=D


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#110364): https://edk2.groups.io/g/devel/message/110364
Mute This Topic: https://groups.io/mt/102256459/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v6 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V

[Dhaval Sharma]

Replied inline. Most of the cases I have addressed in the new patch I
submitted.

On Wed, Oct 25, 2023 at 1:39 AM Pedro Falcato 
wrote:

> On Sat, Oct 21, 2023 at 6:33 PM Dhaval Sharma  wrote:
> >
> > Use newly defined cache management operations for RISC-V where possible
> > It builds up on the support added for RISC-V cache management
> > instructions in BaseLib.
> > Cc: Michael D Kinney 
> > Cc: Liming Gao 
> > Cc: Zhiguang Liu 
> > Cc: Laszlo Ersek 
> >
> > Signed-off-by: Dhaval Sharma 
> > ---
> >
> > Notes:
> > V1:
> > - Utilize cache management instructions if HW supports it
> >   This patch is part of restructuring on top of v5
> >
> >  MdePkg/MdePkg.dec  |
>  8 +
> >  MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |
>  2 +
> >  MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c|
> 159 +---
> >  MdePkg/MdePkg.uni  |
>  4 +
> >  4 files changed, 154 insertions(+), 19 deletions(-)
> >
> > diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
> > index ac54338089e8..fa92673ff633 100644
> > --- a/MdePkg/MdePkg.dec
> > +++ b/MdePkg/MdePkg.dec
> > @@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64,
> PcdsPatchableInModule.AARCH64]
> ># @Prompt CPU Rng algorithm's GUID.
> >
> gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x0037
> >
> > +[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64]
> > +  #
> > +  # Configurability to override RISC-V CPU Features
> > +  # BIT 0 = Cache Management Operations. This bit is relevant only if
> > +  # previous stage has feature enabled and user wants to disable it.
> > +  #
> > +
> gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0x|UINT64|0x69
> > +
> >  [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
> >## This value is used to set the base address of PCI express
> hierarchy.
> ># @Prompt PCI Express Base Address.
> > diff --git
> a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> > index 6fd9cbe5f6c9..39a7fb963b49 100644
> > --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> > @@ -56,3 +56,5 @@ [LibraryClasses]
> >BaseLib
> >DebugLib
> >
> > +[Pcd.RISCV64]
> > +  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride  ## CONSUMES
> > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> > index 4eb18edb9aa7..6851970c9e16 100644
> > --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> > @@ -1,7 +1,8 @@
> >  /** @file
> > -  RISC-V specific functionality for cache.
> > +  Implement Risc-V Cache Management Operations
>
> Why the change? You're effectively implementing cache management for
> riscv, you're not exclusively using any sort of extension (such as
> CMO).
>
Done. I believe you meant to keep it a generic description.

>
> >
> >Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All
> rights reserved.
> > +  Copyright (c) 2023, Rivos Inc. All rights reserved.
> >
> >SPDX-License-Identifier: BSD-2-Clause-Patent
> >  **/
> > @@ -9,10 +10,111 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> > +
> > +// TODO: This will be removed once RISC-V CPU HOB is available
> > +#define RISCV_CACHE_BLOCK_SIZE 64
> > +#define RISCV_CPU_FEATURE_CMO_BITMASK  0x1
> > +
> > +typedef enum {
> > +  Clean,
> > +  Flush,
> > +  Invld,
> > +} CACHE_OP;
> > +
> > +/**
> > +Verify CBOs are supported by this HW
> > +TODO: Use RISC-V CPU HOB once available.
> > +
> > +**/
> > +STATIC
> > +BOOLEAN
> > +RiscVIsCMOEnabled (
> > +  VOID
> > +  )
> > +{
> > +  // TODO: Add check for CMO from CPU HOB.
>
> Too many TODOs? One TODO at the top of the file (mentioning feature
> detection, cache line size detection) should be enough. There's no
> point in peppering these out throughout the file :)
>
> Done.

> > +  // If CMO is disabled in HW, skip Override check
> > +  // Otherwise thi

[edk2-devel] [PATCH v7 5/5] OvmfPkg/RiscVVirt: Override for RV CPU Features

[Dhaval Sharma]

This PCD provides a way for platform to override any
HW features that are default enabled by previous stages
of FW (like OpenSBI). For the case where previous/prev
stage has disabled the feature, this override is not
useful and its usage should be avoided.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Sunil V L 
Cc: Andrei Warkentin 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
Acked-by: Laszlo Ersek 
---

Notes:
V7:
- Added RB tag
v6:
- Modify PCD name according to changes made in Baselib implementation
V5:
- Introduce PCD for platform

 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc 
b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
index fe320525153f..5d66f7fe6ae6 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
+++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
@@ -203,6 +203,7 @@ [PcdsFeatureFlag]
   gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
 
 [PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0
   gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|100
   gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|100
   gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#110267): https://edk2.groups.io/g/devel/message/110267
Mute This Topic: https://groups.io/mt/102256471/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v7 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V

[Dhaval Sharma]

Use newly defined cache management operations for RISC-V where possible
It builds up on the support added for RISC-V cache management
instructions in BaseLib.
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
Acked-by: Laszlo Ersek 
---

Notes:
V7:
- Added PcdLib
- Restructure DEBUG message based on feedback on V6
- Make naming consistent to CMO, remove all CBO references
- Add ASSERT for not supported functions instead of plain debug message
- Added RB tag
V6:
- Utilize cache management instructions if HW supports it
  This patch is part of restructuring on top of v5

 MdePkg/MdePkg.dec  |   8 +
 MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |   5 +
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c| 168 
+---
 MdePkg/MdePkg.uni  |   4 +
 4 files changed, 165 insertions(+), 20 deletions(-)

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index ac54338089e8..fa92673ff633 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AARCH64]
   # @Prompt CPU Rng algorithm's GUID.
   
gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x0037
 
+[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64]
+  #
+  # Configurability to override RISC-V CPU Features
+  # BIT 0 = Cache Management Operations. This bit is relevant only if
+  # previous stage has feature enabled and user wants to disable it.
+  #
+  
gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0x|UINT64|0x69
+
 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
   ## This value is used to set the base address of PCI express hierarchy.
   # @Prompt PCI Express Base Address.
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf 
b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
index 6fd9cbe5f6c9..601a38d6c109 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
@@ -56,3 +56,8 @@ [LibraryClasses]
   BaseLib
   DebugLib
 
+[LibraryClasses.RISCV64]
+  PcdLib
+
+[Pcd.RISCV64]
+  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride  ## CONSUMES
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index 4eb18edb9aa7..5b3104afb67e 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -2,6 +2,7 @@
   RISC-V specific functionality for cache.
 
   Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+  Copyright (c) 2023, Rivos Inc. All rights reserved.
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -9,10 +10,115 @@
 #include 
 #include 
 #include 
+#include 
+
+//
+// TODO: Grab cache block size and make Cache Management Operation
+// enabling decision based on RISC-V CPU HOB in
+// future when it is available.
+//
+#define RISCV_CACHE_BLOCK_SIZE 64
+#define RISCV_CPU_FEATURE_CMO_BITMASK  0x1
+
+typedef enum {
+  Clean,
+  Flush,
+  Invld,
+} CACHE_OP;
+
+/**
+Verify CBOs are supported by this HW
+TODO: Use RISC-V CPU HOB once available.
+
+**/
+STATIC
+BOOLEAN
+RiscVIsCMOEnabled (
+  VOID
+  )
+{
+  // If CMO is disabled in HW, skip Override check
+  // Otherwise this PCD can override settings
+  return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_CMO_BITMASK) 
!= 0);
+}
+
+/**
+  Performs required opeartion on cache lines in the cache coherency domain
+  of the calling CPU. If Address is not aligned on a cache line boundary,
+  then entire cache line containing Address is operated. If Address + Length
+  is not aligned on a cache line boundary, then the entire cache line
+  containing Address + Length -1 is operated.
+  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+  @param  Address The base address of the cache lines to
+  invalidate.
+  @param  Length  The number of bytes to invalidate from the instruction
+  cache.
+  @param  Op  Type of CMO operation to be performed
+  @return Address.
+
+**/
+STATIC
+VOID
+CacheOpCacheRange (
+  IN VOID  *Address,
+  IN UINTN Length,
+  IN CACHE_OP  Op
+  )
+{
+  UINTN  CacheLineSize;
+  UINTN  Start;
+  UINTN  End;
+
+  if (Length == 0) {
+return;
+  }
+
+  if ((Op != Invld) && (Op != Flush) && (Op != Clean)) {
+return;
+  }
+
+  ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
+
+  CacheLineSize = RISCV_CACHE_BLOCK_SIZE;
+
+  Start = (UINTN)Address;
+  //
+  // Calculate the cache line alignment
+  //
+  End= (Start + Length + (CacheLineSize - 1)) & ~(C

[edk2-devel] [PATCH v7 3/5] MdePkg: Implement RISC-V Cache Management Operations

[Dhaval Sharma]

Implement Cache Management Operations (CMO) defined by
RISC-V spec https://github.com/riscv/riscv-CMOs.

Notes:
1. CMO only supports block based Operations. Meaning cache
   flush/invd/clean Operations are not available for the entire
   range. In that case we fallback on fence.i instructions.
2. Operations are implemented using Opcodes to make them compiler
   independent. binutils 2.39+ compilers support CMO instructions.

Test:
1. Ensured correct instructions are refelecting in asm
2. Not able to verify actual instruction in HW as Qemu ignores
   any actual cache operations.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Sunil V L 
Cc: Daniel Schaefer 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
Reviewed-by: Laszlo Ersek 
---

Notes:
V7:
- Modify instruction names as per feedback from V6
- Added RB
V6:
- Implement Cache management instructions in Baselib

 MdePkg/Library/BaseLib/BaseLib.inf|  2 +-
 MdePkg/Include/Library/BaseLib.h  | 33 

 MdePkg/Include/RiscV64/RiscVasm.inc   | 19 
+++
 MdePkg/Library/BaseLib/RiscV64/{FlushCache.S => RiscVCacheMgmt.S} | 17 
++
 4 files changed, 70 insertions(+), 1 deletion(-)

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
b/MdePkg/Library/BaseLib/BaseLib.inf
index 03c7b02e828b..53389389448c 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -400,7 +400,7 @@ [Sources.RISCV64]
   RiscV64/RiscVCpuBreakpoint.S  | GCC
   RiscV64/RiscVCpuPause.S   | GCC
   RiscV64/RiscVInterrupt.S  | GCC
-  RiscV64/FlushCache.S  | GCC
+  RiscV64/RiscVCacheMgmt.S  | GCC
   RiscV64/CpuScratch.S  | GCC
   RiscV64/ReadTimer.S   | GCC
   RiscV64/RiscVMmu.S| GCC
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index d4b56a9601da..c42cc165dc82 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -226,6 +226,39 @@ RiscVInvalidateDataCacheAsmFence (
   VOID
   );
 
+/**
+  RISC-V flush cache block. Atomically perform a clean operation
+  followed by an invalidate operation
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheFlushAsmCmo (
+  IN UINTN
+  );
+
+/**
+Perform a write transfer to another cache or to memory if the
+data in the copy of the cache block have been modified by a store
+operation
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheCleanAsmCmo (
+  IN UINTN
+  );
+
+/**
+Deallocate the copy of the cache block
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheInvalAsmCmo (
+  IN UINTN
+  );
+
 #endif // defined (MDE_CPU_RISCV64)
 
 #if defined (MDE_CPU_LOONGARCH64)
diff --git a/MdePkg/Include/RiscV64/RiscVasm.inc 
b/MdePkg/Include/RiscV64/RiscVasm.inc
new file mode 100644
index ..29de7358855c
--- /dev/null
+++ b/MdePkg/Include/RiscV64/RiscVasm.inc
@@ -0,0 +1,19 @@
+/*
+ *
+ * RISC-V cache operation encoding.
+ * Copyright (c) 2023, Rivos Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ */
+
+.macro RISCVCMOFLUSH
+.word 0x25200f
+.endm
+
+.macro RISCVCMOINVALIDATE
+.word 0x05200f
+.endm
+
+.macro RISCVCMOCLEAN
+.word 0x15200f
+.endm
diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S 
b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
similarity index 56%
rename from MdePkg/Library/BaseLib/RiscV64/FlushCache.S
rename to MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
index e0eea0b5fb25..3c7be3229e3b 100644
--- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
@@ -3,10 +3,12 @@
 // RISC-V cache operation.
 //
 // Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+// Copyright (c) 2023, Rivos Inc. All rights reserved.
 //
 // SPDX-License-Identifier: BSD-2-Clause-Patent
 //
 
//--
+.include "RiscVasm.inc"
 
 .align 3
 ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsmFence)
@@ -19,3 +21,18 @@ ASM_PFX(RiscVInvalidateInstCacheAsmFence):
 ASM_PFX(RiscVInvalidateDataCacheAsmFence):
 fence
 ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheFlushAsmCmo)
+ASM_PFX (RiscVCpuCacheFlushAsmCmo):
+RISCVCMOFLUSH
+ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheCleanAsmCmo)
+ASM_PFX (RiscVCpuCacheCleanAsmCmo):
+RISCVCMOCLEAN
+ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheInvalAsmCmo)
+ASM_PFX (RiscVCpuCacheInvalAsmCmo):
+RISCVCMOINVALIDATE
+ret
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#110265): https://edk2.groups.io/g/devel/message/110265
Mute This Topic: https://groups.io/mt/102256466/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v7 2/5] MdePkg: Rename Cache Management Function To Clarify Fence Based Op

[Dhaval Sharma]

There are different ways to manage cache on RISC-V Processors.
One way is to use fence instruction. Another way is to use CPU
specific cache management operation instructions ratified as
per RISC-V ISA specifications to be introduced in future
patches. Current method is fence instruction based, rename the
function accordingly to add that clarity.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Sunil V L 
Cc: Daniel Schaefer 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
Reviewed-by: Laszlo Ersek 
---

Notes:
V7:
- Add RB tag
V6:
- As part of restructuring, adding cache instruction differentiation
  in function naming

 MdePkg/Include/Library/BaseLib.h| 4 ++--
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 4 ++--
 MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 8 
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 7142bbfa42f2..d4b56a9601da 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -212,7 +212,7 @@ RiscVClearPendingTimerInterrupt (
 **/
 VOID
 EFIAPI
-RiscVInvalidateInstCacheAsm (
+RiscVInvalidateInstCacheAsmFence (
   VOID
   );
 
@@ -222,7 +222,7 @@ RiscVInvalidateInstCacheAsm (
 **/
 VOID
 EFIAPI
-RiscVInvalidateDataCacheAsm (
+RiscVInvalidateDataCacheAsmFence (
   VOID
   );
 
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index d5efcf49a4bf..4eb18edb9aa7 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -21,7 +21,7 @@ InvalidateInstructionCache (
   VOID
   )
 {
-  RiscVInvalidateInstCacheAsm ();
+  RiscVInvalidateInstCacheAsmFence ();
 }
 
 /**
@@ -193,7 +193,7 @@ InvalidateDataCache (
   VOID
   )
 {
-  RiscVInvalidateDataCacheAsm ();
+  RiscVInvalidateDataCacheAsmFence ();
 }
 
 /**
diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S 
b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
index 7c10fdd268af..e0eea0b5fb25 100644
--- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
+++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
@@ -9,13 +9,13 @@
 
//--
 
 .align 3
-ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
-ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
+ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsmFence)
+ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsmFence)
 
-ASM_PFX(RiscVInvalidateInstCacheAsm):
+ASM_PFX(RiscVInvalidateInstCacheAsmFence):
 fence.i
 ret
 
-ASM_PFX(RiscVInvalidateDataCacheAsm):
+ASM_PFX(RiscVInvalidateDataCacheAsmFence):
 fence
 ret
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#110264): https://edk2.groups.io/g/devel/message/110264
Mute This Topic: https://groups.io/mt/102256464/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v7 1/5] MdePkg: Move RISC-V Cache Management Declarations Into BaseLib

[Dhaval Sharma]

The declarations for cache Management functions belong to BaseLib
instead of instance source file. This helps with further restructuring
of cache management code for RISC-V.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
Reviewed-by: Laszlo Ersek 
---

Notes:
V7:
- Added RB tag
V6:
- Move cache management function declaration in baselib where it belongs

 MdePkg/Include/Library/BaseLib.h| 20 
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 20 
 2 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 5d7067ee854e..7142bbfa42f2 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -206,6 +206,26 @@ RiscVClearPendingTimerInterrupt (
   VOID
   );
 
+/**
+  RISC-V invalidate instruction cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateInstCacheAsm (
+  VOID
+  );
+
+/**
+  RISC-V invalidate data cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateDataCacheAsm (
+  VOID
+  );
+
 #endif // defined (MDE_CPU_RISCV64)
 
 #if defined (MDE_CPU_LOONGARCH64)
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index d08fb9f193ca..d5efcf49a4bf 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -10,26 +10,6 @@
 #include 
 #include 
 
-/**
-  RISC-V invalidate instruction cache.
-
-**/
-VOID
-EFIAPI
-RiscVInvalidateInstCacheAsm (
-  VOID
-  );
-
-/**
-  RISC-V invalidate data cache.
-
-**/
-VOID
-EFIAPI
-RiscVInvalidateDataCacheAsm (
-  VOID
-  );
-
 /**
   Invalidates the entire instruction cache in cache coherency domain of the
   calling CPU.
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#110263): https://edk2.groups.io/g/devel/message/110263
Mute This Topic: https://groups.io/mt/102256462/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v7 0/5] Cache Management Operations Support For RISC-V

[Dhaval Sharma]

Implementing code to support Cache Management Operations (CMO) defined by
RISC-V CMO instructions.https://github.com/riscv/riscv-CMOs
This is a re-write of original series v5.
The patchset contains 5 patches- created based on V5 feedback.
1. Restructuring of existing code and move instruction declarations into BaseLib
2. Renaming existing functions to denote type of instruction used to maanage 
cache.
   This is useful for further patches where more cache management instructions 
are added.
3. Add the new cache maintenance operations to BaseLib, including the
 new assembly instruction encodings.
4. Update BaseCacheMaintenanceLib (utilizing the new BaseLib primitives)
5. Add platform level PCD to allow overriding of RISC-V features.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Sunil V L 
Cc: Andrei Warkentin 
Cc: Laszlo Ersek 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Daniel Schaefer 

Dhaval (5):
  MdePkg: Move RISC-V Cache Management Declarations Into BaseLib
  MdePkg: Rename Cache Management Function To Clarify Fence Based Op
  MdePkg: Implement RISC-V Cache Management Operations
  MdePkg: Utilize Cache Management Operations Implementation For RISC-V
  OvmfPkg/RiscVVirt: Override for RV CPU Features

 MdePkg/MdePkg.dec  |   8 +
 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc|   1 +
 MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |   5 +
 MdePkg/Library/BaseLib/BaseLib.inf |   2 +-
 MdePkg/Include/Library/BaseLib.h   |  53 ++
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c| 172 

 MdePkg/Include/RiscV64/RiscVasm.inc|  19 +++
 MdePkg/Library/BaseLib/RiscV64/FlushCache.S|  21 ---
 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S|  38 +
 MdePkg/MdePkg.uni  |   4 +
 10 files changed, 269 insertions(+), 54 deletions(-)
 create mode 100644 MdePkg/Include/RiscV64/RiscVasm.inc
 delete mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
 create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S

-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#110262): https://edk2.groups.io/g/devel/message/110262
Mute This Topic: https://groups.io/mt/102256459/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v6 5/5] OvmfPkg/RiscVVirt: Override for RV CPU Features

[Dhaval Sharma]

This PCD provides a way for platform to override any
HW features that are default enabled by previous stages
of FW (like OpenSBI). For the case where previous/prev
stage has disabled the feature, this override is not
useful and its usage should be avoided.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Sunil V L 
Cc: Andrei Warkentin 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
---

Notes:
v2:
- Modify PCD name according to changes made in Baselib implementation
V1:
- Introduce PCD for platform

 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc 
b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
index fe320525153f..5d66f7fe6ae6 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
+++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
@@ -203,6 +203,7 @@ [PcdsFeatureFlag]
   gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
 
 [PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0
   gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|100
   gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|100
   gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#109880): https://edk2.groups.io/g/devel/message/109880
Mute This Topic: https://groups.io/mt/102103786/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v6 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V

[Dhaval Sharma]

Use newly defined cache management operations for RISC-V where possible
It builds up on the support added for RISC-V cache management
instructions in BaseLib.
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
---

Notes:
V1:
- Utilize cache management instructions if HW supports it
  This patch is part of restructuring on top of v5

 MdePkg/MdePkg.dec  |   8 +
 MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |   2 +
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c| 159 
+---
 MdePkg/MdePkg.uni  |   4 +
 4 files changed, 154 insertions(+), 19 deletions(-)

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index ac54338089e8..fa92673ff633 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AARCH64]
   # @Prompt CPU Rng algorithm's GUID.
   
gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x0037
 
+[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64]
+  #
+  # Configurability to override RISC-V CPU Features
+  # BIT 0 = Cache Management Operations. This bit is relevant only if
+  # previous stage has feature enabled and user wants to disable it.
+  #
+  
gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0x|UINT64|0x69
+
 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
   ## This value is used to set the base address of PCI express hierarchy.
   # @Prompt PCI Express Base Address.
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf 
b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
index 6fd9cbe5f6c9..39a7fb963b49 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
@@ -56,3 +56,5 @@ [LibraryClasses]
   BaseLib
   DebugLib
 
+[Pcd.RISCV64]
+  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride  ## CONSUMES
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index 4eb18edb9aa7..6851970c9e16 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -1,7 +1,8 @@
 /** @file
-  RISC-V specific functionality for cache.
+  Implement Risc-V Cache Management Operations
 
   Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+  Copyright (c) 2023, Rivos Inc. All rights reserved.
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -9,10 +10,111 @@
 #include 
 #include 
 #include 
+#include 
+
+// TODO: This will be removed once RISC-V CPU HOB is available
+#define RISCV_CACHE_BLOCK_SIZE 64
+#define RISCV_CPU_FEATURE_CMO_BITMASK  0x1
+
+typedef enum {
+  Clean,
+  Flush,
+  Invld,
+} CACHE_OP;
+
+/**
+Verify CBOs are supported by this HW
+TODO: Use RISC-V CPU HOB once available.
+
+**/
+STATIC
+BOOLEAN
+RiscVIsCMOEnabled (
+  VOID
+  )
+{
+  // TODO: Add check for CMO from CPU HOB.
+  // If CMO is disabled in HW, skip Override check
+  // Otherwise this PCD can override settings
+  return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_CMO_BITMASK) 
!= 0);
+}
+
+/**
+  Performs required opeartion on cache lines in the cache coherency domain
+  of the calling CPU. If Address is not aligned on a cache line boundary,
+  then entire cache line containing Address is operated. If Address + Length
+  is not aligned on a cache line boundary, then the entire cache line
+  containing Address + Length -1 is operated.
+  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+  @param  Address The base address of the cache lines to
+  invalidate.
+  @param  Length  The number of bytes to invalidate from the instruction
+  cache.
+  @param  Op  Type of CMO operation to be performed
+  @return Address.
+
+**/
+STATIC
+VOID
+CacheOpCacheRange (
+  IN VOID  *Address,
+  IN UINTN Length,
+  IN CACHE_OP  Op
+  )
+{
+  UINTN  CacheLineSize;
+  UINTN  Start;
+  UINTN  End;
+
+  if (Length == 0) {
+return;
+  }
+
+  if ((Op != Invld) && (Op != Flush) && (Op != Clean)) {
+return;
+  }
+
+  ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
+
+  CacheLineSize = RISCV_CACHE_BLOCK_SIZE;
+
+  Start = (UINTN)Address;
+  //
+  // Calculate the cache line alignment
+  //
+  End= (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1);
+  Start &= ~((UINTN)CacheLineSize - 1);
+
+  DEBUG (
+(DEBUG_INFO,
+ "%a Performing Cache Management Operation %d \n", __func__, Op)
+);
+
+  do {
+switch (Op) {
+  case Invld:
+RiscVCpuCacheInvalAsmCbo (

[edk2-devel] [PATCH v6 3/5] MdePkg: Implement RISC-V Cache Management Operations

[Dhaval Sharma]

Implement Cache Management Operations (CMO) defined by
RISC-V spec https://github.com/riscv/riscv-CMOs.

Notes:
1. CMO only supports block based Operations. Meaning cache
   flush/invd/clean Operations are not available for the entire
   range. In that case we fallback on fence.i instructions.
2. Operations are implemented using Opcodes to make them compiler
   independent. binutils 2.39+ compilers support CMO instructions.

Test:
1. Ensured correct instructions are refelecting in asm
2. Not able to verify actual instruction in HW as Qemu ignores
   any actual cache operations.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Sunil V L 
Cc: Daniel Schaefer 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
---

Notes:
V1:
- Implement Cache management instructions in Baselib

 MdePkg/Library/BaseLib/BaseLib.inf|  2 +-
 MdePkg/Include/Library/BaseLib.h  | 33 

 MdePkg/Include/RiscV64/RiscVasm.inc   | 19 
+++
 MdePkg/Library/BaseLib/RiscV64/{FlushCache.S => RiscVCacheMgmt.S} | 17 
++
 4 files changed, 70 insertions(+), 1 deletion(-)

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
b/MdePkg/Library/BaseLib/BaseLib.inf
index 03c7b02e828b..53389389448c 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -400,7 +400,7 @@ [Sources.RISCV64]
   RiscV64/RiscVCpuBreakpoint.S  | GCC
   RiscV64/RiscVCpuPause.S   | GCC
   RiscV64/RiscVInterrupt.S  | GCC
-  RiscV64/FlushCache.S  | GCC
+  RiscV64/RiscVCacheMgmt.S  | GCC
   RiscV64/CpuScratch.S  | GCC
   RiscV64/ReadTimer.S   | GCC
   RiscV64/RiscVMmu.S| GCC
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index d4b56a9601da..60d60602b876 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -226,6 +226,39 @@ RiscVInvalidateDataCacheAsmFence (
   VOID
   );
 
+/**
+  RISC-V flush cache block. Atomically perform a clean operation
+  followed by an invalidate operation
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheFlushAsmCbo (
+  IN UINTN
+  );
+
+/**
+Perform a write transfer to another cache or to memory if the
+data in the copy of the cache block have been modified by a store
+operation
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheCleanAsmCbo (
+  IN UINTN
+  );
+
+/**
+Deallocate the copy of the cache block
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheInvalAsmCbo (
+  IN UINTN
+  );
+
 #endif // defined (MDE_CPU_RISCV64)
 
 #if defined (MDE_CPU_LOONGARCH64)
diff --git a/MdePkg/Include/RiscV64/RiscVasm.inc 
b/MdePkg/Include/RiscV64/RiscVasm.inc
new file mode 100644
index ..6f418232d507
--- /dev/null
+++ b/MdePkg/Include/RiscV64/RiscVasm.inc
@@ -0,0 +1,19 @@
+/*
+ *
+ * RISC-V cache operation encoding.
+ * Copyright (c) 2023, Rivos Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ */
+
+.macro RISCVCBOFLSH
+.word 0x25200f
+.endm
+
+.macro RISCVCBOINVD
+.word 0x05200f
+.endm
+
+.macro RISCVCBOCLEN
+.word 0x15200f
+.endm
diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S 
b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
similarity index 57%
rename from MdePkg/Library/BaseLib/RiscV64/FlushCache.S
rename to MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
index e0eea0b5fb25..fe3943ae3f7c 100644
--- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
@@ -3,10 +3,12 @@
 // RISC-V cache operation.
 //
 // Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+// Copyright (c) 2023, Rivos Inc. All rights reserved.
 //
 // SPDX-License-Identifier: BSD-2-Clause-Patent
 //
 
//--
+.include "RiscVasm.inc"
 
 .align 3
 ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsmFence)
@@ -19,3 +21,18 @@ ASM_PFX(RiscVInvalidateInstCacheAsmFence):
 ASM_PFX(RiscVInvalidateDataCacheAsmFence):
 fence
 ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheFlushAsmCbo)
+ASM_PFX (RiscVCpuCacheFlushAsmCbo):
+  RISCVCBOFLSH
+  ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheCleanAsmCbo)
+ASM_PFX (RiscVCpuCacheCleanAsmCbo):
+  RISCVCBOCLEN
+  ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheInvalAsmCbo)
+ASM_PFX (RiscVCpuCacheInvalAsmCbo):
+  RISCVCBOINVD
+  ret
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#109878): https://edk2.groups.io/g/devel/message/109878
Mute This Topic: https://groups.io/mt/102103780/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v6 2/5] MdePkg: Rename Cache Management Function To Clarify Fence Based Op

[Dhaval Sharma]

There are different ways to manage cache on RISC-V Processors.
One way is to use fence instruction. Another way is to use CPU
specific cache management operation instructions ratified as
per RISC-V ISA specifications to be introduced in future
patches. Current method is fence instruction based, rename the
function accordingly to add that clarity.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Sunil V L 
Cc: Daniel Schaefer 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
---

Notes:
V6:
- As part of restructuring, adding cache instruction differentiation
  in function naming

 MdePkg/Include/Library/BaseLib.h| 4 ++--
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 4 ++--
 MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 8 
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 7142bbfa42f2..d4b56a9601da 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -212,7 +212,7 @@ RiscVClearPendingTimerInterrupt (
 **/
 VOID
 EFIAPI
-RiscVInvalidateInstCacheAsm (
+RiscVInvalidateInstCacheAsmFence (
   VOID
   );
 
@@ -222,7 +222,7 @@ RiscVInvalidateInstCacheAsm (
 **/
 VOID
 EFIAPI
-RiscVInvalidateDataCacheAsm (
+RiscVInvalidateDataCacheAsmFence (
   VOID
   );
 
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index d5efcf49a4bf..4eb18edb9aa7 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -21,7 +21,7 @@ InvalidateInstructionCache (
   VOID
   )
 {
-  RiscVInvalidateInstCacheAsm ();
+  RiscVInvalidateInstCacheAsmFence ();
 }
 
 /**
@@ -193,7 +193,7 @@ InvalidateDataCache (
   VOID
   )
 {
-  RiscVInvalidateDataCacheAsm ();
+  RiscVInvalidateDataCacheAsmFence ();
 }
 
 /**
diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S 
b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
index 7c10fdd268af..e0eea0b5fb25 100644
--- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
+++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
@@ -9,13 +9,13 @@
 
//--
 
 .align 3
-ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
-ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
+ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsmFence)
+ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsmFence)
 
-ASM_PFX(RiscVInvalidateInstCacheAsm):
+ASM_PFX(RiscVInvalidateInstCacheAsmFence):
 fence.i
 ret
 
-ASM_PFX(RiscVInvalidateDataCacheAsm):
+ASM_PFX(RiscVInvalidateDataCacheAsmFence):
 fence
 ret
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#109877): https://edk2.groups.io/g/devel/message/109877
Mute This Topic: https://groups.io/mt/102103778/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v6 1/5] MdePkg: Move RISC-V Cache Management Declarations Into BaseLib

[Dhaval Sharma]

The declarations for cache Management functions belong to BaseLib
instead of instance source file. This helps with further restructuring
of cache management code for RISC-V.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
---

Notes:
V5:
- Move cache management function declaration in baselib where it belongs

 MdePkg/Include/Library/BaseLib.h| 20 
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 20 
 2 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 5d7067ee854e..7142bbfa42f2 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -206,6 +206,26 @@ RiscVClearPendingTimerInterrupt (
   VOID
   );
 
+/**
+  RISC-V invalidate instruction cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateInstCacheAsm (
+  VOID
+  );
+
+/**
+  RISC-V invalidate data cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateDataCacheAsm (
+  VOID
+  );
+
 #endif // defined (MDE_CPU_RISCV64)
 
 #if defined (MDE_CPU_LOONGARCH64)
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index d08fb9f193ca..d5efcf49a4bf 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -10,26 +10,6 @@
 #include 
 #include 
 
-/**
-  RISC-V invalidate instruction cache.
-
-**/
-VOID
-EFIAPI
-RiscVInvalidateInstCacheAsm (
-  VOID
-  );
-
-/**
-  RISC-V invalidate data cache.
-
-**/
-VOID
-EFIAPI
-RiscVInvalidateDataCacheAsm (
-  VOID
-  );
-
 /**
   Invalidates the entire instruction cache in cache coherency domain of the
   calling CPU.
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#109876): https://edk2.groups.io/g/devel/message/109876
Mute This Topic: https://groups.io/mt/102103776/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v6 0/5] Cache Management Operations Support For RISC-V

[Dhaval Sharma]

Implementing code to support Cache Management Operations (CMO) defined by
RISC-V CMO instructions.https://github.com/riscv/riscv-CMOs
This is a re-write of original series v5.
The patchset contains 5 patches- created based on V5 feedback.
1. Restructuring of existing code and move instruction declarations into BaseLib
2. Renaming existing functions to denote type of instruction used to maanage 
cache.
   This is useful for further patches where more cache management instructions 
are added.
3. Add the new cache maintenance operations to BaseLib, including the
 new assembly instruction encodings.
4. Update BaseCacheMaintenanceLib (utilizing the new BaseLib primitives)
5. Add platform level PCD to allow overriding of RISC-V features.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Sunil V L 
Cc: Andrei Warkentin 
Cc: Laszlo Ersek 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Daniel Schaefer 

Dhaval (5):
  MdePkg: Move RISC-V Cache Management Declarations Into BaseLib
  MdePkg: Rename Cache Management Function To Clarify Fence Based Op
  MdePkg: Implement RISC-V Cache Management Operations
  MdePkg: Utilize Cache Management Operations Implementation For RISC-V
  OvmfPkg/RiscVVirt: Override for RV CPU Features

 MdePkg/MdePkg.dec  |   8 +
 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc|   1 +
 MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |   2 +
 MdePkg/Library/BaseLib/BaseLib.inf |   2 +-
 MdePkg/Include/Library/BaseLib.h   |  53 
+++
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c| 163 

 MdePkg/Include/RiscV64/RiscVasm.inc|  19 +++
 MdePkg/Library/BaseLib/RiscV64/FlushCache.S|  21 ---
 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S|  38 +
 MdePkg/MdePkg.uni  |   4 +
 10 files changed, 258 insertions(+), 53 deletions(-)
 create mode 100644 MdePkg/Include/RiscV64/RiscVasm.inc
 delete mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
 create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S

-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#109875): https://edk2.groups.io/g/devel/message/109875
Mute This Topic: https://groups.io/mt/102103774/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v5 2/2] OvmfPkg/RiscVVirt: Override for RV CPU Features

[Dhaval Sharma]

It was introduced in 2.39 it seems. GCC 12 onwards contains this binutils
version as per my understanding. This version was released quite long back.
I can double check by submitting it through edk2 CI to ensure it works.
Current CI version is already GCC 12.

On Thu, Oct 19, 2023 at 5:47 PM Laszlo Ersek  wrote:

> On 10/19/23 11:22, Laszlo Ersek wrote:
> > On 10/19/23 08:48, Dhaval Sharma wrote:
>
> >> (11) I agree that we should use symbolic names rather than
> >> magic constants, but raw encodings of machine instructions don't belong
> >> into a
> >>  C header file. [Dhaval] This bytecode was introduced thinking what
> >> if all compilers do not support it. but given the default compiler in
> >> edk2 GCC 12 supports it
> >>  we can eliminate this byte encoding completely to make it easy and
> >> simple to consume for others.
> >
> > To be honest, I can't determine the minimum expected gcc version for
> > edk2. "BaseTools/Conf/tools_def.template" states a minimum version for
> > NASM, for example, but I can't find a similar gcc requirement there.
> >
> > gcc-12 does work for me personally, because my riscv cross-compiler is
> > "riscv64-linux-gnu-gcc (GCC) 12.1.1 20220507 (Red Hat Cross 12.1.1-1)".
> >
> > If the CI environment that builds these patches also provides gcc-12+,
> > then I figure you should be set.
>
> Wait, for the assembly language source files, what matters is the
> binutils version, not the gcc version. Mine is "GNU assembler version
> 2.38-3.el9" (from "binutils-riscv64-linux-gnu-2.38-3.el9.x86_64").
>
> Is that sufficient for the instuctions in question?
>
> (More generally -- what version does our CI env expect / provide?)
>
> Thanks
> Laszlo
>
>

-- 
Thanks!
=D


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#109813): https://edk2.groups.io/g/devel/message/109813
Mute This Topic: https://groups.io/mt/102016149/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v5 2/2] OvmfPkg/RiscVVirt: Override for RV CPU Features

[Dhaval Sharma]

Hi Laszlo,
Thanks a lot for your feedback. I have modified my next patchset addressing
most of the comments. Summary below. But *before I submit the final
version* I wanted to seek clarification on a few things mentioned below
with [Dhaval]. Current PR I am planning to submit:
https://github.com/tianocore/edk2/pull/4928

I am summarizing all comments for better readability:
(1) Split into four separate patches, in v6.   *Done*.-
with some comments below
1a. Fix previous error from earlier patch that had declaration outside
baselib.h
1b. Renaming RiscVInvalidateDataCacheAsm() to
RiscVInvalidateDataCacheAsmFence() etc.
1c. Adding the new cache maintenance operations to BaseLib, including
the
  new assembly instruction encodings.
1d. Updating BaseCacheMaintenanceLib (utilizing the new BaseLib
primitives).
1e. I have added another one for RiscvVirt platform kind of an override
as 5th patch.
(2)  This belongs to v6 patch#4, because only BaseCacheMaintenanceLib needs
the PCD.*Done*
(3)  "CMO" should be expanded as "cache management operations".   *Done*
(4)  The whole PCD is insufficiently documented.  *Done*
(5)  Accordingly, the default value of the PCD should be
0x.  *Done*
(6)  The "MdePkg/MdePkg.uni" file should be kept in sync with dec.
*Done*.  [Dhaval] Is this used beyond setup options? For some PCDs I do not
find an entry in uni.
(7)  Belongs to v6 patch#4. *Done*
(8)  Please consider appending the "## CONSUMES" hint. *Done*
(9)  Belongs to v6 patch#3. *Done*
(10) Belongs to v6 patch#3. *Done*
(11) I agree that we should use symbolic names rather than magic constants,
but raw encodings of machine instructions don't belong into a
 C header file. [Dhaval] This bytecode was introduced thinking what if
all compilers do not support it. but given the default compiler in edk2 GCC
12 supports it
 we can eliminate this byte encoding completely to make it easy and
simple to consume for others.
(12) Also, filing a feature request (about these instructions). As per (11)
it is already available.
(13) As stated above, these two interfaces don't belong here. *Done*
(14) As stated above, these function declarations don't belong here. *Done*
(15) I believe this un-indented comment will not pass ECC Check /
 uncrustify. [Dhaval] I attach my stuart_build logs. I do not see
specific errors.https://github.com/tianocore/edk2/pull/4928 Pull request
all passed. Am I missing something?
(16-17-18) The name of the function suggests the return type should be
BOOLEAN. *Done*
(19) Should be STATIC, and should *not* be EFIAPI. (Not a public
interface.) *Done*
(20) This will definitely not pass uncrustify. If you are talking about bad
indent seen on Ops and Length- it is fixed. *Done*
(21) Logging this error for every cache line of the requested range does
not seem useful. I suggest checking Op before the loop. *Done*
(22) As stated above, the API renames -- together with the updated leading
comments -- belong in v6 patch#2. *Done*
(23) As stated above, the API renames -- together with the updated leading
comments -- belong in v6 patch#2. *Done*
(24) The DEBUG message seems bogus; invalidating the whole I-Cache *is*
what is being requested here. *Done*
(25-26) The *API* renames belong to v6 patch#2. & The new APIs, plus the
*file* rename, belong to v6 patch#3. *Done*
(27) Please use the assembler macros from point (11). Please see (11)
(28-29-30-31) Please do not abbreviate RISC-V as "RV". It's incredibly
confusing.  Inconsistent spelling in the patch subject: "RISCV CMO". ditto;
should be RISC-V.ditto, should be PcdRiscVFeatureOverride *Done*
(32-33) Total inconsistency, RV64_ versus RV_.  Should be RiscVIsCMOEnabled
(upper case V). *Done*

On Tue, Oct 17, 2023 at 8:09 PM Laszlo Ersek  wrote:

> On 10/17/23 14:17, Dhaval Sharma wrote:
> > This PCD provides a way for platform to override any
> > HW features that are default enabled by previous stages
> > of FW (like OpenSBI). For the case where previous/prev
> > stage has disabled the feature, this override is not
> > useful and its usage should be avoided.
> >
> > Ard Biesheuvel 
> > Jiewen Yao 
> > Jordan Justen 
> > Gerd Hoffmann 
> > Sunil V L 
> > Andrei Warkentin 
>
> (4) You forgot to prepend "Cc:".
>
> (5) The cover letter (0/2 email here) should contain all the Cc: tags
> from the patches' commit messages, so that whoever gets at least one
> patch CC'd from the series also get the cover letter for the series.
>
> Thanks
> Laszlo
>
> >
> > Signed-off-by: Dhaval Sharma 
> > ---
> >  OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc

[edk2-devel] [PATCH v5 2/2] OvmfPkg/RiscVVirt: Override for RV CPU Features

[Dhaval Sharma]

This PCD provides a way for platform to override any
HW features that are default enabled by previous stages
of FW (like OpenSBI). For the case where previous/prev
stage has disabled the feature, this override is not
useful and its usage should be avoided.

Ard Biesheuvel 
Jiewen Yao 
Jordan Justen 
Gerd Hoffmann 
Sunil V L 
Andrei Warkentin 

Signed-off-by: Dhaval Sharma 
---
 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc 
b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
index fe320525153f..8b5e010316ba 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
+++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
@@ -203,6 +203,8 @@ [PcdsFeatureFlag]
   gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
 
 [PcdsFixedAtBuild.common]
+  gEfiMdePkgTokenSpaceGuid.PcdRVFeatureOverride|0
+
   gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|100
   gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|100
   gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#109679): https://edk2.groups.io/g/devel/message/109679
Mute This Topic: https://groups.io/mt/102016149/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v5 1/2] MdePkg:Implement RISCV CMO

[Dhaval Sharma]

Implementing code to support Cache Management Operations
(CMO) defined by RV spec https://github.com/riscv/riscv-CMOs

Notes:
1. CMO only supports block based Operations. Meaning complete
   cache flush/invd/clean Operations are not available. In that case
   we fallback on fence.i instructions.
2. Rely on the fact that platform init has initialized CMO and this
   implementation just checks if it is enabled.
3. In order to avoid compiler dependency injecting byte code.

Test:
1. Ensured correct instructions are refelecting in asm
2. Able to boot platform with RiscVVirtQemu config
3. Not able to verify actual instruction in HW as Qemu ignores
any actual cache operations.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Sunil V L 
Cc: Andrei Warkentin 
Signed-off-by: Dhaval Sharma 
---

Notes:
v5:
- Addressed comments from v4
- Use #defines instead of numbers in cache instruction encoding
- Addressed function naming issues from previous patch
- Added new PCD to override RV CPU features
- Removed code that relied on ENVCFG registers
- Fixing typos in comments

 MdePkg/MdePkg.dec  |   7 +
 MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |   3 +-
 MdePkg/Library/BaseLib/BaseLib.inf |   2 +-
 MdePkg/Include/Register/RiscV64/RiscVEncoding.h|   6 +
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c| 203 
+---
 MdePkg/Library/BaseLib/RiscV64/FlushCache.S|  21 --
 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S|  38 
 7 files changed, 234 insertions(+), 46 deletions(-)

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index ac54338089e8..2d06cf46b1ca 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -2399,6 +2399,13 @@ [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AARCH64]
   # @Prompt CPU Rng algorithm's GUID.
   
gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x0037
 
+[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64]
+  #
+  # Configurability to override RV CPU Features
+  # BIT 0 = CMO
+  #
+  gEfiMdePkgTokenSpaceGuid.PcdRVFeatureOverride|0x1|UINT64|0x69
+
 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
   ## This value is used to set the base address of PCI express hierarchy.
   # @Prompt PCI Express Base Address.
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf 
b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
index 6fd9cbe5f6c9..037a0b49800a 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
@@ -55,4 +55,5 @@ [Packages]
 [LibraryClasses]
   BaseLib
   DebugLib
-
+[Pcd]
+  gEfiMdePkgTokenSpaceGuid.PcdRVFeatureOverride
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
b/MdePkg/Library/BaseLib/BaseLib.inf
index 03c7b02e828b..53389389448c 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -400,7 +400,7 @@ [Sources.RISCV64]
   RiscV64/RiscVCpuBreakpoint.S  | GCC
   RiscV64/RiscVCpuPause.S   | GCC
   RiscV64/RiscVInterrupt.S  | GCC
-  RiscV64/FlushCache.S  | GCC
+  RiscV64/RiscVCacheMgmt.S  | GCC
   RiscV64/CpuScratch.S  | GCC
   RiscV64/ReadTimer.S   | GCC
   RiscV64/RiscVMmu.S| GCC
diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h 
b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
index 2bde8db478ff..5d6dcab12f74 100644
--- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
+++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
@@ -117,4 +117,10 @@
 #define CAUSE_VIRTUAL_INST_FAULT0x16
 #define CAUSE_STORE_GUEST_PAGE_FAULT0x17
 
+#define CPU_FLUSH_CMO_ASM  0x0025200f
+
+#define CPU_CLEAN_CMO_ASM  0x0015200f
+
+#define CPU_INVLD_CMO_ASM  0x0005200f
+
 #endif
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index d08fb9f193ca..bd8794e1d818 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -1,7 +1,8 @@
 /** @file
-  RISC-V specific functionality for cache.
+  Implement Risc-V Cache Management Operations
 
   Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+  Copyright (c) 2023, Rivos Inc. All rights reserved.
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -9,6 +10,17 @@
 #include 
 #include 
 #include 
+#include 
+
+// TODO: This will be removed once RISC-V CPU HOB is available
+#define RV64_CACHE_BLOCK_SIZE   64
+#define RV_CPU_FEATURE_CMO_BITMASK  0x1
+
+typedef enum {
+  Clean,
+  Flush,
+  Invld,
+} CACHE_OP;
 
 /**
   RISC-V

[edk2-devel] [PATCH v5 0/2] MdePkg:Implement RISCV CMO

[Dhaval Sharma]

Implementing code to support Cache Management Operations (CMO) defined by RV 
spec https://github.com/riscv/riscv-CMOs

Notes:
CMO only supports block based Operations. Meaning complete cache 
flush/invd/clean Operations are not available. In that case we fallback on 
fence.i instructions.
Rely on the fact that platform init has initialized CMO and this implementation 
just checks if it is enabled.
In order to avoid compiler dependency injecting byte code. Code branch 
https://github.com/rivosinc/edk2/tree/dev_rv_cmo_v5

Test:
Ensured correct instructions are refelecting in asm
Able to boot platform with RiscVVirtQemu config
Not able to verify actual instruction in HW as Qemu ignores any actual cache 
operations.

Dhaval (2):
  MdePkg:Implement RISCV CMO
  OvmfPkg/RiscVVirt: Override for RV CPU Features

 MdePkg/MdePkg.dec  |   7 +
 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc|   2 +
 MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf |   3 +-
 MdePkg/Library/BaseLib/BaseLib.inf |   2 +-
 MdePkg/Include/Register/RiscV64/RiscVEncoding.h|   6 +
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c| 203 
+---
 MdePkg/Library/BaseLib/RiscV64/FlushCache.S|  21 --
 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S|  38 
 8 files changed, 236 insertions(+), 46 deletions(-)
 delete mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
 create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S

-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#109677): https://edk2.groups.io/g/devel/message/109677
Mute This Topic: https://groups.io/mt/102016147/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode

[Dhaval Sharma]

Reviewed-by: Dhaval Sharma 


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#109306): https://edk2.groups.io/g/devel/message/109306
Mute This Topic: https://groups.io/mt/101742937/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v1 1/1] MdeModulePkg: Fix issue with ACPI table creation

[Dhaval Sharma]

Hi everyone,
A gentle remonder to review the patch..


-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#109305): https://edk2.groups.io/g/devel/message/109305
Mute This Topic: https://groups.io/mt/101633356/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v1 1/1] MdeModulePkg: Fix issue with ACPI table creation

[Dhaval Sharma]

As per spec if xDSDT is avaialble, it should be used first.
Handle required flow when xDSDT is abscent or present.

Test: Tested on RISCV64 Qemu platform with xDSDT and booted to
linux kernel.

Cc: Jian J Wang 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Dandan Bi 
Signed-off-by: Dhaval Sharma 
---
 MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 15 
++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c 
b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
index e09bc9b704f5..d153c96a6bdb 100644
--- a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
+++ b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c
@@ -1892,7 +1892,20 @@ InstallAcpiTableFromHob (
   }
 }
 
-if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->Dsdt != 
0) {
+//
+// First check if xDSDT is available that is preferred
+//
+if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->XDsdt 
!= 0) {
+  TableToInstall = (VOID 
*)(UINTN)((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->XDsdt;
+  Status = AddTableToList (AcpiTableInstance, TableToInstall, 
TRUE, Version, TRUE, );
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "InstallAcpiTableFromHob: Fail to add ACPI 
table xDSDT\n"));
+ASSERT_EFI_ERROR (Status);
+break;
+  }
+}
+
+else if (((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE 
*)ChildTable)->Dsdt != 0) {
   TableToInstall = (VOID 
*)(UINTN)((EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)ChildTable)->Dsdt;
   Status = AddTableToList (AcpiTableInstance, TableToInstall, 
TRUE, Version, TRUE, );
   if (EFI_ERROR (Status)) {
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#109137): https://edk2.groups.io/g/devel/message/109137
Mute This Topic: https://groups.io/mt/101633356/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v1 0/1] Add support for XDSDT table

[Dhaval Sharma]

Enable detection of XDSDT table from ACPI HOB

Dhaval (1):
  MdeModulePkg: Fix issue with ACPI table creation

 MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 15 
++-
 1 file changed, 14 insertions(+), 1 deletion(-)

Cc: Jian J Wang 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Dandan Bi 
-- 
2.39.2



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#109136): https://edk2.groups.io/g/devel/message/109136
Mute This Topic: https://groups.io/mt/101633355/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH v4 1/1] MdePkg:Implement RISCV CMO

[Dhaval Sharma]

Thanks for your feedback.

   1. Reg coding style, I will remove _ and resubmit but somehow PR CI
   seemed to pass for me (https://github.com/tianocore/edk2/pull/4636).
   2. For size and ext discovery should I wait until your ext discovery
   patch is merged?
   3. Thanks for catching the issue with SENVCFG. Will fix it in the next
   revision after #2 is addressed.

On Mon, Jul 24, 2023 at 10:03 AM Sunil V L  wrote:

> Hi Dhaval,
>
> On Thu, Jul 13, 2023 at 03:03:31PM +0530, Dhaval wrote:
> > From: Dhaval Sharma 
> >
> > Implementing code to support Cache Management Operations
> > (CMO) defined by RV spec https://github.com/riscv/riscv-CMOs
> >
> > Notes:
> > 1. CMO only supports block based Operations. Meaning complete
> >cache flush/invd/clean Operations are not available. In that case
> >we fallback on fence.i instructions.
> > 2. Rely on the fact that platform init has initialized CMO and this
> >implementation just checks if it is enabled.
> > 3. In order to avoid compiler dependency injecting byte code.
> >
> > Test:
> > 1. Ensured correct instructions are refelecting in asm
> > 2. Able to boot platform with RiscVVirtQemu config
> > 3. Not able to verify actual instruction in HW as Qemu ignores
> > any actual cache operations.
> >
> > Cc: Ard Biesheuvel 
> > Cc: Jiewen Yao 
> > Cc: Jordan Justen 
> > Cc: Gerd Hoffmann 
> > Cc: Sunil V L 
> > Cc: Andrei Warkentin 
> > Signed-off-by: Dhaval Sharma 
> > ---
> >
> > Notes:
> > v4:
> > - Removed CMO specific directory in Base Lib
> > - Implemented compiler independent code for CMO
> > - Merged CMO implementation with fence.i
> > - Added logic to confirm CMO is enabled
> >
> >  MdePkg/Library/BaseLib/BaseLib.inf  |   2 +-
> >  MdePkg/Include/Register/RiscV64/RiscVEncoding.h |   4 +
> >  MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 200
> ++--
> >  MdePkg/Library/BaseLib/RiscV64/FlushCache.S |  21 --
> >  MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S |  64 +++
> >  5 files changed, 254 insertions(+), 37 deletions(-)
> >
> > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
> b/MdePkg/Library/BaseLib/BaseLib.inf
> > index 03c7b02e828b..53389389448c 100644
> > --- a/MdePkg/Library/BaseLib/BaseLib.inf
> > +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> > @@ -400,7 +400,7 @@ [Sources.RISCV64]
> >RiscV64/RiscVCpuBreakpoint.S  | GCC
> >RiscV64/RiscVCpuPause.S   | GCC
> >RiscV64/RiscVInterrupt.S  | GCC
> > -  RiscV64/FlushCache.S  | GCC
> > +  RiscV64/RiscVCacheMgmt.S  | GCC
> >RiscV64/CpuScratch.S  | GCC
> >RiscV64/ReadTimer.S   | GCC
> >RiscV64/RiscVMmu.S| GCC
> > diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> > index 5c2989b797bf..ea1493578bd5 100644
> > --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> > +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> > @@ -85,6 +85,10 @@
> >  /* Supervisor Configuration */
> >  #define CSR_SENVCFG  0x10a
> >
> > +/* Defined CBO bits*/
> > +#define SENVCFG_CBCFE  0x40UL
> > +#define SENVCFG_CBIE   0x30UL
> > +
> >  /* Supervisor Trap Handling */
> >  #define CSR_SSCRATCH  0x140
> >  #define CSR_SEPC  0x141
> > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> > index d08fb9f193ca..8b853e5b69fa 100644
> > --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> > @@ -1,7 +1,8 @@
> >  /** @file
> > -  RISC-V specific functionality for cache.
> > +  Implement Risc-V Cache Management Operations
> >
> >Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All
> rights reserved.
> > +  Copyright (c) 2023, Rivos Inc. All rights reserved.
> >
> >SPDX-License-Identifier: BSD-2-Clause-Patent
> >  **/
> > @@ -10,13 +11,21 @@
> >  #include 
> >  #include 
> >
> > +#define RV64_CACHE_BLOCK_SIZE  64
> > +
> Can we avoid hard coding this? We can get it from DT.
>
> > +typedef enum {
> > +  Clean,
> > +  Flush,
> > +  Invld,
> > +} CACHE_OP;
> > +
> >  /**
> >RISC-V invalidate instruction cache.
> >
> >  **/
> >  VOID
> >  EFIAPI
> > -RiscVInvalidateInstCacheAsm (
> > 

[edk2-devel] [PATCH v4 1/1] MdePkg:Implement RISCV CMO

[Dhaval Sharma]

From: Dhaval Sharma 

Implementing code to support Cache Management Operations
(CMO) defined by RV spec https://github.com/riscv/riscv-CMOs

Notes:
1. CMO only supports block based Operations. Meaning complete
   cache flush/invd/clean Operations are not available. In that case
   we fallback on fence.i instructions.
2. Rely on the fact that platform init has initialized CMO and this
   implementation just checks if it is enabled.
3. In order to avoid compiler dependency injecting byte code.

Test:
1. Ensured correct instructions are refelecting in asm
2. Able to boot platform with RiscVVirtQemu config
3. Not able to verify actual instruction in HW as Qemu ignores
any actual cache operations.

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Sunil V L 
Cc: Andrei Warkentin 
Signed-off-by: Dhaval Sharma 
---

Notes:
v4:
- Removed CMO specific directory in Base Lib
- Implemented compiler independent code for CMO
- Merged CMO implementation with fence.i
- Added logic to confirm CMO is enabled

 MdePkg/Library/BaseLib/BaseLib.inf  |   2 +-
 MdePkg/Include/Register/RiscV64/RiscVEncoding.h |   4 +
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 200 ++--
 MdePkg/Library/BaseLib/RiscV64/FlushCache.S |  21 --
 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S |  64 +++
 5 files changed, 254 insertions(+), 37 deletions(-)

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf 
b/MdePkg/Library/BaseLib/BaseLib.inf
index 03c7b02e828b..53389389448c 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -400,7 +400,7 @@ [Sources.RISCV64]
   RiscV64/RiscVCpuBreakpoint.S  | GCC
   RiscV64/RiscVCpuPause.S   | GCC
   RiscV64/RiscVInterrupt.S  | GCC
-  RiscV64/FlushCache.S  | GCC
+  RiscV64/RiscVCacheMgmt.S  | GCC
   RiscV64/CpuScratch.S  | GCC
   RiscV64/ReadTimer.S   | GCC
   RiscV64/RiscVMmu.S| GCC
diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h 
b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
index 5c2989b797bf..ea1493578bd5 100644
--- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
+++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
@@ -85,6 +85,10 @@
 /* Supervisor Configuration */
 #define CSR_SENVCFG  0x10a
 
+/* Defined CBO bits*/
+#define SENVCFG_CBCFE  0x40UL
+#define SENVCFG_CBIE   0x30UL
+
 /* Supervisor Trap Handling */
 #define CSR_SSCRATCH  0x140
 #define CSR_SEPC  0x141
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index d08fb9f193ca..8b853e5b69fa 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -1,7 +1,8 @@
 /** @file
-  RISC-V specific functionality for cache.
+  Implement Risc-V Cache Management Operations
 
   Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+  Copyright (c) 2023, Rivos Inc. All rights reserved.
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -10,13 +11,21 @@
 #include 
 #include 
 
+#define RV64_CACHE_BLOCK_SIZE  64
+
+typedef enum {
+  Clean,
+  Flush,
+  Invld,
+} CACHE_OP;
+
 /**
   RISC-V invalidate instruction cache.
 
 **/
 VOID
 EFIAPI
-RiscVInvalidateInstCacheAsm (
+RiscVInvalidateInstCacheAsm_Fence (
   VOID
   );
 
@@ -26,13 +35,144 @@ RiscVInvalidateInstCacheAsm (
 **/
 VOID
 EFIAPI
-RiscVInvalidateDataCacheAsm (
+RiscVInvalidateDataCacheAsm_Fence (
   VOID
   );
 
+/**
+  RISC-V flush cache block. Atomically perform a clean operation
+  followed by an invalidate operation
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheFlushAsm_Cbo (
+  UINTN
+  );
+
+/**
+Perform a write transfer to another cache or to memory if the
+data in the copy of the cache block have been modified by a store
+operation
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheCleanAsm_Cbo (
+  UINTN
+  );
+
+/**
+Deallocate the copy of the cache block
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheInvalAsm_Cbo (
+  UINTN
+  );
+
+/**
+Verify CBOs are supported by this HW
+CBCFE == Cache Block Clean and Flush instruction Enable
+CBIE == Cache Block Invalidate instruction Enable
+
+**/
+UINTN
+RiscvIsCbcfeEnabledAsm (
+  VOID
+  );
+
+UINTN
+RiscvIsCbiEnabledAsm (
+  VOID
+  );
+
+/**
+  Performs required opeartion on cache lines in the cache coherency domain
+  of the calling CPU. If Address is not aligned on a cache line boundary,
+  then entire cache line containing Address is operated. If Address + Length
+  is not aligned on a cache line boundary, then the entire cache line
+  containing Address + Length -1 is operated.
+
+  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+  @param  Address The base address of the cache lines to
+  invalidate. If the CPU is in a physical addressing mode,
+  then Address is a physical address. If the CPU is in a virtual
+  addressing

[edk2-devel] [PATCH v4 0/1] MdePkg:Implement RISCV CMO

[Dhaval Sharma]

Implementing code to support Cache Management Operations (CMO) defined by RV 
spec https://github.com/riscv/riscv-CMOs

Notes:

CMO only supports block based Operations. Meaning complete cache 
flush/invd/clean Operations are not available. In that case we fallback on 
fence.i instructions.
Rely on the fact that platform init has initialized CMO and this implementation 
just checks if it is enabled.
In order to avoid compiler dependency injecting byte code.
Test:

Ensured correct instructions are refelecting in asm
Able to boot platform with RiscVVirtQemu config
Not able to verify actual instruction in HW as Qemu ignores any actual cache 
operations.

Dhaval Sharma (1):
  MdePkg:Implement RISCV CMO

 MdePkg/Library/BaseLib/BaseLib.inf  |   2 +-
 MdePkg/Include/Register/RiscV64/RiscVEncoding.h |   4 +
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 200 ++--
 MdePkg/Library/BaseLib/RiscV64/FlushCache.S |  21 --
 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S |  64 +++
 5 files changed, 254 insertions(+), 37 deletions(-)
 delete mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
 create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S

-- 
2.34.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#106901): https://edk2.groups.io/g/devel/message/106901
Mute This Topic: https://groups.io/mt/100117168/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v1 8/8] UefiPayloadPkg: Add RV64 driver to boot to UEFI Shell

[Dhaval Sharma]

Added required Dxe and Arch Proto drivers to ensure we
are able to boot to Shell.

Test: Able to boot to UEFI Shell

Cc: Guo Dong 
Cc: Ray Ni 
Cc: Sean Rhodes 
Cc: James Lu 
Cc: Gua Guo 
Cc: Sunil V 
Signed-off-by: Dhaval Sharma 
---
 UefiPayloadPkg/UefiPayloadPkgRV64.dsc | 33 +++--
 UefiPayloadPkg/UefiPayloadPkgRV64.fdf | 51 +++-
 2 files changed, 46 insertions(+), 38 deletions(-)

diff --git a/UefiPayloadPkg/UefiPayloadPkgRV64.dsc 
b/UefiPayloadPkg/UefiPayloadPkgRV64.dsc
index 8b226c483855..81a59f486837 100644
--- a/UefiPayloadPkg/UefiPayloadPkgRV64.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkgRV64.dsc
@@ -211,7 +211,7 @@ [LibraryClasses.common]
   
CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
   RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
   
ResetSystemLib|OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf
-
+  TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
 
 [LibraryClasses.common.SEC]
   HobLib|UefiPayloadPkg/Library/PayloadEntryHobLib/HobLib.inf
@@ -252,7 +252,6 @@ [LibraryClasses.common.DXE_RUNTIME_DRIVER]
 !if $(PERFORMANCE_MEASUREMENT_ENABLE)
   PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
 !endif
-  ResetSystemLib|OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf
   UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
 
 !ifdef $(DEBUG_ON_SERIAL_PORT)
@@ -466,11 +465,25 @@ [Components]
   #
   # RISC-V Platform module
   #
-   EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
-   UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
   #
   # Components that produce the architectural protocols
   #
+  UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
+  UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+
+!if $(DISABLE_RESET_SYSTEM) == FALSE
+  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+!endif
+!if $(EMU_VARIABLE_ENABLE) == TRUE
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+!endif
+
 !if $(SECURITY_STUB_ENABLE) == TRUE
   MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
 !endif
@@ -488,17 +501,6 @@ [Components]
 
   
NULL|UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
   }
-  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
-  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
-  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
-  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
-  
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
-!if $(DISABLE_RESET_SYSTEM) == FALSE
-  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
-!endif
-!if $(EMU_VARIABLE_ENABLE) == TRUE
-  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
-!endif
   #
   # Following are the DXE drivers
   #
@@ -593,7 +595,6 @@ [LibraryClasses]
   FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
   ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
   !include NetworkPkg/NetworkLibs.dsc.inc
-  TimeBaseLib|EmbeddedPkg//Library/TimeBaseLib/TimeBaseLib.inf
   
OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
 
 [Components]
diff --git a/UefiPayloadPkg/UefiPayloadPkgRV64.fdf 
b/UefiPayloadPkg/UefiPayloadPkgRV64.fdf
index 747c617b0f60..90128713f544 100644
--- a/UefiPayloadPkg/UefiPayloadPkgRV64.fdf
+++ b/UefiPayloadPkg/UefiPayloadPkgRV64.fdf
@@ -104,34 +104,13 @@ [FV.DXEFV]
 !if $(CRYPTO_PROTOCOL_SUPPORT) == TRUE
 INF CryptoPkg/Driver/CryptoDxe.inf
 !endif
-!if $(SECURITY_STUB_ENABLE) == TRUE
-INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
-!endif
 INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
 INF RuleOverride = UI MdeModulePkg/Application/UiApp/UiApp.inf
 INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
-INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
 INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
-INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
-INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
-INF 
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
-
-!if $(DISABLE_RESET_SYSTEM) == FALSE
-INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
-!endif
-
-!if $(VARIABLE_SUPPORT) == "EMU"
-  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
-!elseif $(VARIABLE_SUPPORT) == "SPI"
-  INF UefiPayloadPkg/FvbRuntimeDxe/FvbSmm.inf
-  INF MdeModulePkg/Universal/F

[edk2-devel] [PATCH v1 6/8] UefiPayloadPkg: Add FirmwareContext for RV64

[Dhaval Sharma]

RV CPU driver requires access to HartID and FDT passed by BL.
Set it through FirmwareContext. In future this should be passed
as part of FDT itself to avoid any custome structures.

Cc: Guo Dong 
Cc: Ray Ni 
Cc: Sean Rhodes 
Cc: James Lu 
Cc: Gua Guo 
Cc: Sunil V 
Signed-off-by: Dhaval Sharma 
---
 UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf  | 2 ++
 UefiPayloadPkg/UefiPayloadEntry/RiscV64/Rv64FdtParserLib.c | 9 +
 2 files changed, 11 insertions(+)

diff --git a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf 
b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
index 9b21b218a657..0cc3c0994aa1 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
@@ -61,6 +61,8 @@ [LibraryClasses]
   CpuLib
   FdtLib
 
+[LibraryClasses.RISCV64]
+  RiscVSbiLib
 [Guids]
   gEfiMemoryTypeInformationGuid
   gEfiFirmwareFileSystem2Guid
diff --git a/UefiPayloadPkg/UefiPayloadEntry/RiscV64/Rv64FdtParserLib.c 
b/UefiPayloadPkg/UefiPayloadEntry/RiscV64/Rv64FdtParserLib.c
index 76f0600482f7..7be38bb742f6 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/RiscV64/Rv64FdtParserLib.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/RiscV64/Rv64FdtParserLib.c
@@ -30,6 +30,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #define E820_RAM1
@@ -376,6 +377,14 @@ BuildBlHobs (
   UINTN   FdtPages;
   UINT64  *FdtHobData;
   CONST VOID  *Fdt;
+  EFI_FFS_FILE_HEADER *FileHeader;
+  EFI_FIRMWARE_VOLUME_HEADER  *DxeCoreFv;
+  EFI_STATUS  Status;
+  EFI_RISCV_FIRMWARE_CONTEXT  FirmwareContext;
+
+  FirmwareContext.BootHartId  = Param1;
+  FirmwareContext.FlattenedDeviceTree = Param2;
+  SetFirmwareContextPointer ();
 
   Fdt   = (VOID *)Param2;
   MinimalNeededSize = FixedPcdGet32 (PcdSystemMemoryUefiRegionSize);
-- 
2.34.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#104679): https://edk2.groups.io/g/devel/message/104679
Mute This Topic: https://groups.io/mt/98822713/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v1 7/8] UefiPayloadPkg: Find DxeFV and create required FV HOB

[Dhaval Sharma]

UPL expects to have Dxe info from gUniversalPayloadExtraDataGuid HOB.
With new FDT proposal this requirement should go away. But for now
satisfying this requirement through RV hook.

Test: Able to enter DxeMain function after finding correct DxeFv.

Cc: Guo Dong 
Cc: Ray Ni 
Cc: Sean Rhodes 
Cc: James Lu 
Cc: Gua Guo 
Cc: Sunil V 
Signed-off-by: Dhaval Sharma 
---
 UefiPayloadPkg/UefiPayloadEntry/RiscV64/DxeLoadFunc.c  |  46 ++
 UefiPayloadPkg/UefiPayloadEntry/RiscV64/Rv64FdtParserLib.c | 149 
+++-
 2 files changed, 194 insertions(+), 1 deletion(-)

diff --git a/UefiPayloadPkg/UefiPayloadEntry/RiscV64/DxeLoadFunc.c 
b/UefiPayloadPkg/UefiPayloadEntry/RiscV64/DxeLoadFunc.c
index db44b38cc7c7..ecd249337151 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/RiscV64/DxeLoadFunc.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/RiscV64/DxeLoadFunc.c
@@ -7,6 +7,16 @@
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "UefiPayloadEntry.h"
+
+#define STACK_SIZE  0x2
 
 /**
Transfers control to DxeCore.
@@ -25,4 +35,40 @@ HandOffToDxeCore (
   IN EFI_PEI_HOB_POINTERS  HobList
   )
 {
+  VOID  *BaseOfStack;
+  VOID  *TopOfStack;
+
+  //
+  //
+  // Allocate 128KB for the Stack
+  //
+  BaseOfStack = AllocatePages (EFI_SIZE_TO_PAGES (STACK_SIZE));
+  if (BaseOfStack == NULL) {
+DEBUG ((DEBUG_ERROR, "%a: Can't allocate memory for stack.", __func__));
+ASSERT (FALSE);
+  }
+
+  //
+  // Compute the top of the stack we were allocated. Pre-allocate a UINTN
+  // for safety.
+  //
+  TopOfStack = (VOID *)((UINTN)BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * 
EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT);
+  TopOfStack = ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);
+
+  //
+  // Update the contents of BSP stack HOB to reflect the real stack info 
passed to DxeCore.
+  //
+  UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN)BaseOfStack, STACK_SIZE);
+
+  DEBUG ((DEBUG_INFO, "DXE Core new stack at %x, stack pointer at %x\n", 
BaseOfStack, TopOfStack));
+
+  //
+  // Transfer the control to the entry point of DxeCore.
+  //
+  SwitchStack (
+(SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
+HobList.Raw,
+NULL,
+TopOfStack
+);
 }
diff --git a/UefiPayloadPkg/UefiPayloadEntry/RiscV64/Rv64FdtParserLib.c 
b/UefiPayloadPkg/UefiPayloadEntry/RiscV64/Rv64FdtParserLib.c
index 7be38bb742f6..b1251a83a236 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/RiscV64/Rv64FdtParserLib.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/RiscV64/Rv64FdtParserLib.c
@@ -41,6 +41,8 @@
 #define E820_DISABLED   6
 #define E820_PMEM   7
 #define E820_UNDEFINED  8
+#define GET_OCCUPIED_SIZE(ActualSize, Alignment) \
+  ((ActualSize) + (((Alignment) - ((ActualSize) & ((Alignment) - 1))) & 
((Alignment) - 1)))
 
 /**
   Auto-generated function that calls the library constructors for all of the 
module's
@@ -341,6 +343,138 @@ BuildSerialHobFromFDT (
   return TRUE;
 }
 
+/**
+  This function searchs a given file type with a given Guid within a valid FV.
+  If input Guid is NULL, will locate the first section having the given file 
type
+
+  @param FvHeaderA pointer to firmware volume header that contains the 
set of files
+ to be searched.
+  @param FileTypeFile type to be searched.
+  @param GuidWill ignore if it is NULL.
+  @param FileHeader  A pointer to the discovered file, if successful.
+
+  @retval EFI_SUCCESSSuccessfully found FileType
+  @retval EFI_NOT_FOUND  File type can't be found.
+**/
+STATIC EFI_STATUS
+FvFindFileByTypeGuid (
+  IN  EFI_FIRMWARE_VOLUME_HEADER  *FvHeader,
+  IN  EFI_FV_FILETYPE FileType,
+  IN  EFI_GUID*Guid  OPTIONAL,
+  OUT EFI_FFS_FILE_HEADER **FileHeader
+  )
+{
+  EFI_PHYSICAL_ADDRESS  CurrentAddress;
+  EFI_PHYSICAL_ADDRESS  EndOfFirmwareVolume;
+  EFI_FFS_FILE_HEADER   *File;
+  UINT32Size;
+  EFI_PHYSICAL_ADDRESS  EndOfFile;
+
+  CurrentAddress  = (EFI_PHYSICAL_ADDRESS)(UINTN)FvHeader;
+  EndOfFirmwareVolume = CurrentAddress + FvHeader->FvLength;
+
+  //
+  // Loop through the FFS files
+  //
+  for (EndOfFile = CurrentAddress + FvHeader->HeaderLength; ; ) {
+CurrentAddress = (EndOfFile + 7) & 0xfff8ULL;
+if (CurrentAddress > EndOfFirmwareVolume) {
+  break;
+}
+
+File = (EFI_FFS_FILE_HEADER *)(UINTN)CurrentAddress;
+if (IS_FFS_FILE2 (File)) {
+  Size = FFS_FILE2_SIZE (File);
+  if (Size <= 0x00FF) {
+break;
+  }
+} else {
+  Size = FFS_FILE_SIZE (File);
+  if (Size < sizeof (EFI_FFS_FILE_HEADER)) {
+break;
+  }
+}
+
+EndOfFile = CurrentAddress + Size;
+if (EndOfFile > EndOfFirmwareVolume) {
+  break;
+}
+
+//
+// Look for file type
+//
+if (File->Type == FileType) {
+  if ((Guid == NULL) || CompareGui

[edk2-devel] [PATCH v1 3/8] UefiPayloadPkg: Basic Infra To Enable RV64 UPL Support

[Dhaval Sharma]

Add support for RiscV64 Arch for UPL. The Patch primarily
allows one to compile UPL with RV64 GCC tools.
It builds on top of earlier patches submitted for UPL
boot flow modifications where arch specific initialization
was removed. Follow up patches will be added to further the
boot flow.

Test: Tested that code compiles UPL Pkg with RV64 GCC5

Cc: Guo Dong 
Cc: Ray Ni 
Cc: Sean Rhodes 
Cc: James Lu 
Cc: Gua Guo 
Cc: Sunil V 

Signed-off-by: Dhaval Sharma 
---
 UefiPayloadPkg/UefiPayloadPkgRV64.dsc | 637 

 UefiPayloadPkg/UefiPayloadPkgRV64.fdf | 318 ++
 UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf |   4 +-
 UefiPayloadPkg/UefiPayloadEntry/RiscV64/DxeLoadFunc.c |  28 +
 4 files changed, 986 insertions(+), 1 deletion(-)

diff --git a/UefiPayloadPkg/UefiPayloadPkgRV64.dsc 
b/UefiPayloadPkg/UefiPayloadPkgRV64.dsc
new file mode 100644
index ..8b226c483855
--- /dev/null
+++ b/UefiPayloadPkg/UefiPayloadPkgRV64.dsc
@@ -0,0 +1,637 @@
+## @file
+# Bootloader Payload Package
+#
+# Provides drivers and definitions to create uefi payload for bootloaders.
+#
+# Copyright (c) 2023, Rivos Inc
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  PLATFORM_NAME   = UefiPayloadPkg
+  PLATFORM_GUID   = F71608AB-D63D-4491-B744-A8C8CD96
+  PLATFORM_VERSION= 0.1
+  DSC_SPECIFICATION   = 0x00010005
+  SUPPORTED_ARCHITECTURES = RISCV64
+  BUILD_TARGETS   = DEBUG|RELEASE|NOOPT
+  SKUID_IDENTIFIER= DEFAULT
+  OUTPUT_DIRECTORY= Build/UefiPayloadPkgRV64
+  FLASH_DEFINITION= UefiPayloadPkg/UefiPayloadPkgRV64.fdf
+  PCD_DYNAMIC_AS_DYNAMICEX= TRUE
+
+  DEFINE SECURITY_STUB_ENABLE = TRUE
+  DEFINE PLATFORM_BOOT_TIMEOUT= 3
+  DEFINE UNIVERSAL_PAYLOAD= TRUE
+  DEFINE DEBUG_ON_SERIAL_PORT = TRUE
+  #
+  # CPU options
+  #
+  DEFINE MAX_LOGICAL_PROCESSORS   = 256
+
+  #
+  # PCI options
+  #
+  DEFINE PCIE_BASE_SUPPORT= TRUE
+
+  #
+  # Serial port set up
+  #
+  DEFINE BAUD_RATE= 115200
+  DEFINE SERIAL_CLOCK_RATE= 1843200
+  DEFINE SERIAL_LINE_CONTROL  = 3 # 8-bits, no parity
+  DEFINE SERIAL_HARDWARE_FLOW_CONTROL = FALSE
+  DEFINE SERIAL_DETECT_CABLE  = FALSE
+  DEFINE SERIAL_FIFO_CONTROL  = 7 # Enable FIFO
+  DEFINE UART_DEFAULT_BAUD_RATE   = $(BAUD_RATE)
+  DEFINE UART_DEFAULT_DATA_BITS   = 8
+  DEFINE UART_DEFAULT_PARITY  = 1
+  DEFINE UART_DEFAULT_STOP_BITS   = 1
+  DEFINE DEFAULT_TERMINAL_TYPE= 0
+
+  # Enabling the serial terminal will slow down the boot menu redering!
+  DEFINE DISABLE_SERIAL_TERMINAL  = FALSE
+
+  #   [Vendor]   [Device]  
[ClockRate---]  [Offset---] [Bar] [Stride] [RxFifo] 
[TxFifo]   [Rsvd]   [Vendor]
+  DEFINE PCI_SERIAL_PARAMETERS= {0xff,0xff, 0x00,0x00, 
0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00,0x01, 0x0,0x0, 
0x0,0x0, 0x0,0x0, 0xff,0xff}
+
+  #
+  # Shell options: [BUILD_SHELL, MIN_BIN, NONE, UEFI_BIN]
+  #
+  DEFINE SHELL_TYPE   = BUILD_SHELL
+
+  #
+  # EMU:  UEFI payload with EMU variable
+  # SPI:  UEFI payload with SPI NV variable support
+  # NONE: UEFI payload with no variable modules
+  #
+  DEFINE VARIABLE_SUPPORT  = EMU
+
+  DEFINE SERIAL_DRIVER_ENABLE = TRUE
+
+  # For recent X86 CPU, 0x15 CPUID instruction will return Time Stamp Counter 
Frequence.
+  # This is how BaseCpuTimerLib works, and a recommended way to get Frequence, 
so set the default value as TRUE.
+  # Note: for emulation platform such as QEMU, this may not work and should 
set it as FALSE
+  DEFINE CPU_TIMER_LIB_ENABLE  = TRUE
+
+[BuildOptions]
+  *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
+  GCC:RELEASE_*_*_CC_FLAGS   = -DMDEPKG_NDEBUG
+  INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+  GCC:*_*_*_DLINK_FLAGS  = -z common-page-size=0x1000
+  XCODE:*_*_*_DLINK_FLAGS= -seg1addr 0x1000 -segalign 0x1000
+  XCODE:*_*_*_MTOC_FLAGS = -align 0x1000
+  CLANGPDB:*_*_*_DLINK_FLAGS = /ALIGN:4096
+
+
+#
+# SKU Identification section - list of all SKU IDs supported by this Platform.
+#
+
+[SkuIds]
+  0|DEFAULT

[edk2-devel] [PATCH v1 5/8] UefiPayloadPkg: Hook to parse IN params as per UPL spec

[Dhaval Sharma]

Provide an arch specific hook which will consume IN params
to UPL and populate FDT variable properly. Each Arch has its
own ABI and accordingly input param changes. First part, This
hook will ensure correct input param is used to populate FDT
value. Second part, after finding proper FDT, it uses FDT to
create HOBs that are later consumed by UPL.New implementation
may remove HOB creation as per latest spec. First part will
still be relevant.

Test: Able to parse FDT, create HOBs and get serial debug logs.

Cc: Guo Dong 
Cc: Ray Ni 
Cc: Sean Rhodes 
Cc: James Lu 
Cc: Gua Guo 
Cc: Sunil V 

Signed-off-by: Dhaval Sharma 
---
 UefiPayloadPkg/UefiPayloadPkg.dsc  |   2 +-
 UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf  |   6 +
 UefiPayloadPkg/UefiPayloadEntry/Ia32/Ia32FdtParserLib.c|  33 ++
 UefiPayloadPkg/UefiPayloadEntry/RiscV64/Rv64FdtParserLib.c | 469 

 UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c|  13 +-
 UefiPayloadPkg/UefiPayloadEntry/X64/X64FdtParserLib.c  |  33 ++
 6 files changed, 553 insertions(+), 3 deletions(-)

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc 
b/UefiPayloadPkg/UefiPayloadPkg.dsc
index 998d22290922..e5eac44d06b2 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -305,7 +305,7 @@ [LibraryClasses]
   
VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseVariableFlashInfoLib.inf
   CcExitLib|UefiCpuPkg/Library/CcExitLibNull/CcExitLibNull.inf
   
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
-
+  FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
 [LibraryClasses.common]
 !if $(BOOTSPLASH_IMAGE)
   SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
diff --git a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf 
b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
index 14d072e1198f..9b21b218a657 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
@@ -32,19 +32,23 @@ [Sources.Ia32]
   X64/VirtualMemory.c
   Ia32/DxeLoadFunc.c
   Ia32/IdtVectorAsm.nasm
+  Ia32/Ia32FdtParserLib.c
 
 [Sources.X64]
   X64/VirtualMemory.h
   X64/VirtualMemory.c
   X64/DxeLoadFunc.c
+  X64/X64FdtParserLib.c
 
 [Sources.RISCV64]
   RiscV64/DxeLoadFunc.c
+  RiscV64/Rv64FdtParserLib.c
 [Packages]
   MdePkg/MdePkg.dec
   MdeModulePkg/MdeModulePkg.dec
   UefiCpuPkg/UefiCpuPkg.dec
   UefiPayloadPkg/UefiPayloadPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
 
 [LibraryClasses]
   BaseMemoryLib
@@ -55,6 +59,7 @@ [LibraryClasses]
   HobLib
   PeCoffLib
   CpuLib
+  FdtLib
 
 [Guids]
   gEfiMemoryTypeInformationGuid
@@ -72,6 +77,7 @@ [Guids]
   gUniversalPayloadPciRootBridgeInfoGuid
   gUniversalPayloadSmbios3TableGuid
   gEdkiiBootManagerMenuFileGuid
+  gFdtHobGuid
 
 [FeaturePcd.IA32]
   gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode  ## CONSUMES
diff --git a/UefiPayloadPkg/UefiPayloadEntry/Ia32/Ia32FdtParserLib.c 
b/UefiPayloadPkg/UefiPayloadEntry/Ia32/Ia32FdtParserLib.c
new file mode 100644
index ..ec35834a782b
--- /dev/null
+++ b/UefiPayloadPkg/UefiPayloadEntry/Ia32/Ia32FdtParserLib.c
@@ -0,0 +1,33 @@
+/** @file
+  This library will parse the coreboot table in memory and extract those 
required
+  information.
+
+  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+EFI_STATUS
+BuildBlHobs (
+  IN  UINTN   Param1,
+  IN  UINTN   Param2,
+  OUT EFI_FIRMWARE_VOLUME_HEADER  **DxeFv
+  );
+
+/**
+  It will build HOBs based on information from bootloaders.
+
+  @param[in]  Param1   Hard ID
+  @param[in]  Param2   FDT blob pointer
+  @param[out] DxeFvThe pointer to the DXE FV in memory.
+
+  @retval EFI_SUCCESSIf it completed successfully.
+**/
+EFI_STATUS
+BuildBlHobs (
+  IN  UINTN   Param1,
+  IN  UINTN   Param2,
+  OUT EFI_FIRMWARE_VOLUME_HEADER  **DxeFv
+  )
+{
+  return EFI_SUCCESS;
+}
diff --git a/UefiPayloadPkg/UefiPayloadEntry/RiscV64/Rv64FdtParserLib.c 
b/UefiPayloadPkg/UefiPayloadEntry/RiscV64/Rv64FdtParserLib.c
new file mode 100644
index ..76f0600482f7
--- /dev/null
+++ b/UefiPayloadPkg/UefiPayloadEntry/RiscV64/Rv64FdtParserLib.c
@@ -0,0 +1,469 @@
+/** @file
+  This library will parse the coreboot table in memory and extract those 
required
+  information.
+
+  Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define E820_RAM1
+#define E820_RESERVED   2
+#define E820_ACPI   3
+#define

[edk2-devel] [PATCH v1 4/8] UefiPayloadPkg: Update input params as per latest UPL spec

[Dhaval Sharma]

According to UPL spec for various archs ABIs we have different
input passing arguments. We provide Arch specific hooks to
ensure FDT is populated from the correct argument following the
spec. TODO: Will have to create one parser per arch.

Cc: Guo Dong 
Cc: Ray Ni 
Cc: Sean Rhodes 
Cc: James Lu 
Cc: Gua Guo 
Cc: Sunil V 
Signed-off-by: Dhaval Sharma 
---
 UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c | 11 +++
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c 
b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c
index 3f7f72ea7f06..59cb4d56e314 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c
@@ -450,16 +450,15 @@ BuildHobs (
 EFI_STATUS
 EFIAPI
 _ModuleEntryPoint (
-  IN UINTN  BootloaderParameter
+  IN UINTN  Param1,
+  IN UINTN  Param2
   )
 {
   EFI_STATUS  Status;
   PHYSICAL_ADDRESSDxeCoreEntryPoint;
   EFI_PEI_HOB_POINTERSHob;
-  EFI_FIRMWARE_VOLUME_HEADER  *DxeFv;
+  EFI_FIRMWARE_VOLUME_HEADER  *DxeFv = NULL;
 
-  mHobList = (VOID *)BootloaderParameter;
-  DxeFv= NULL;
   // Call constructor for all libraries
   ProcessLibraryConstructorList ();
 
@@ -473,10 +472,6 @@ _ModuleEntryPoint (
 PrintHob (mHobList);
 );
 
-  // Build HOB based on information from Bootloader
-  Status = BuildHobs (BootloaderParameter, );
-  ASSERT_EFI_ERROR (Status);
-
   FixUpPcdDatabase (DxeFv);
   Status = UniversalLoadDxeCore (DxeFv, );
   ASSERT_EFI_ERROR (Status);
-- 
2.34.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#104677): https://edk2.groups.io/g/devel/message/104677
Mute This Topic: https://groups.io/mt/98822709/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v1 2/8] UefiPayloadPkg: Move INT prog outside common flow

[Dhaval Sharma]

8259 is very arch specific programming. It needs to be moved out to
the respective arch flow. Added in both x64 and x32 paths

Test: Able to boot UEFI shell with Coreboot Tianocore payload on
x86 qemu

Cc: Guo Dong 
Cc: Ray Ni 
Cc: Sean Rhodes 
Cc: James Lu 
Cc: Gua Guo 

Signed-off-by: Dhaval Sharma 

Reviewed-by: Gua Guo 
Reviewed-by: James Lu 
---

Notes:
v3:
- Added legacy INT intialization to X64 path as well
v4:
- Updated reviewed-by tag

 UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c  | 6 ++
 UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c | 6 --
 UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c   | 6 ++
 3 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c 
b/UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c
index 921a38555e21..695d751bbb50 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c
@@ -271,6 +271,12 @@ HandOffToDxeCore (
   // Initialize floating point operating environment to be compliant with UEFI 
spec.
   InitializeFloatingPointUnits ();
 
+  //
+  // Mask off all legacy 8259 interrupt sources
+  //
+  IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, 0xFF);
+  IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, 0xFF);
+
   //
   // Clear page 0 and mark it as allocated if NULL pointer detection is 
enabled.
   //
diff --git a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c 
b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c
index 8aff00142971..3f7f72ea7f06 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c
@@ -481,12 +481,6 @@ _ModuleEntryPoint (
   Status = UniversalLoadDxeCore (DxeFv, );
   ASSERT_EFI_ERROR (Status);
 
-  //
-  // Mask off all legacy 8259 interrupt sources
-  //
-  IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, 0xFF);
-  IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, 0xFF);
-
   Hob.HandoffInformationTable = (EFI_HOB_HANDOFF_INFO_TABLE *)GetFirstHob 
(EFI_HOB_TYPE_HANDOFF);
   HandOffToDxeCore (DxeCoreEntryPoint, Hob);
 
diff --git a/UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c 
b/UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c
index 84a6112ce64a..1dfb7459e85a 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c
@@ -43,6 +43,12 @@ HandOffToDxeCore (
   // Initialize floating point operating environment to be compliant with UEFI 
spec.
   InitializeFloatingPointUnits ();
 
+  //
+  // Mask off all legacy 8259 interrupt sources
+  //
+  IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, 0xFF);
+  IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, 0xFF);
+
   //
   // Clear page 0 and mark it as allocated if NULL pointer detection is 
enabled.
   //
-- 
2.34.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#104675): https://edk2.groups.io/g/devel/message/104675
Mute This Topic: https://groups.io/mt/98822707/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v1 1/8] UefiPayloadPkg: Remove FP Init from UPL entry

[Dhaval Sharma]

According to UPL spec BL should initialize FP init meaning UPL
does not need to initialize it. Besides this is arch specific init
and needs to be moved out of UPL common flow. In order to not break
current BL implementations, for now just moving the init to later
point of time but for both x32 and x64 eventually this should be
removed once BL impelement this logic.

Test: Verified booting  UEFI shell on coreboot on qemu.

Cc: Guo Dong 
Cc: Ray Ni 
Cc: Sean Rhodes 
Cc: James Lu 
Cc: Gua Guo 

Signed-off-by: Dhaval Sharma 

Reviewed-by: Gua Guo 
Reviewed-by: James Lu 
---

Notes:
v3:
- Added FP initialization to X64 path as well
v4:
- Updated reviewed-by tag

 UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c  | 3 +++
 UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c | 3 ---
 UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c   | 3 +++
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c 
b/UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c
index 61a9f01ec9e7..921a38555e21 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c
@@ -268,6 +268,9 @@ HandOffToDxeCore (
   UINT32   Index;
   X64_IDT_TABLE*IdtTableForX64;
 
+  // Initialize floating point operating environment to be compliant with UEFI 
spec.
+  InitializeFloatingPointUnits ();
+
   //
   // Clear page 0 and mark it as allocated if NULL pointer detection is 
enabled.
   //
diff --git a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c 
b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c
index f8939efe70db..8aff00142971 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c
@@ -473,9 +473,6 @@ _ModuleEntryPoint (
 PrintHob (mHobList);
 );
 
-  // Initialize floating point operating environment to be compliant with UEFI 
spec.
-  InitializeFloatingPointUnits ();
-
   // Build HOB based on information from Bootloader
   Status = BuildHobs (BootloaderParameter, );
   ASSERT_EFI_ERROR (Status);
diff --git a/UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c 
b/UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c
index 346e3feb0459..84a6112ce64a 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c
@@ -40,6 +40,9 @@ HandOffToDxeCore (
   VOID   *GhcbBase;
   UINTN  GhcbSize;
 
+  // Initialize floating point operating environment to be compliant with UEFI 
spec.
+  InitializeFloatingPointUnits ();
+
   //
   // Clear page 0 and mark it as allocated if NULL pointer detection is 
enabled.
   //
-- 
2.34.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#104674): https://edk2.groups.io/g/devel/message/104674
Mute This Topic: https://groups.io/mt/98822705/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] DRAFT: [PATCH v1 0/8] RiscV64 Support In UPL

[Dhaval Sharma]

This patchset contains modifications required in UPL boot flow to
enable RiscV64 support. Squashing earlier series of patches
related to arch specific removal from UPL boot path to this release such
that all chnages can be viewed in the entirety.
1. Add required infra to support RiscV64
2. New UPL proposal supports multiple Archs and accordingly ABI
   is also different. This is a proposal to accomodate these changes.
   This patch adds a hook to parse RiscV64 specific IN params and extract
   FDT from the same.
3. Take FDT received from BL and parse it to create required HOBs that
   are later consumed by UPL.
4. Add FirmwareContext structure which is specific to RV and used by RV
   CPU driver.
5. Add required modifications to extrace DxeFv from overall UPL FD.
6. Add required RV drivers to boot to UEFI Shell

P.S. This patch is review only at this point as it is tested in a limited
fashion for RV to get to early debug logs from FDT described serial device.
It will require modifications to work on other Archs.

Branch https://github.com/rivosinc/edk2/tree/upl-rv64-enable-compilation-v1

Dhaval Sharma (8):
  UefiPayloadPkg: Remove FP Init from UPL entry
  UefiPayloadPkg: Move INT prog outside common flow
  UefiPayloadPkg: Basic Infra To Enable RV64 UPL Support
  UefiPayloadPkg: Update input params as per latest UPL spec
  UefiPayloadPkg: Hook to parse IN params as per UPL spec
  UefiPayloadPkg: Add FirmwareContext for RV64
  UefiPayloadPkg: Find DxeFV and create required FV HOB
  UefiPayloadPkg: Add RV64 driver to boot to UEFI Shell

 UefiPayloadPkg/UefiPayloadPkg.dsc  |   2 +-
 UefiPayloadPkg/{UefiPayloadPkg.dsc => UefiPayloadPkgRV64.dsc}  | 448 
+++---
 UefiPayloadPkg/UefiPayloadPkgRV64.fdf  | 325 ++
 UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf  |  12 +-
 UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c |   9 +
 UefiPayloadPkg/UefiPayloadEntry/Ia32/Ia32FdtParserLib.c|  33 ++
 UefiPayloadPkg/UefiPayloadEntry/{X64 => RiscV64}/DxeLoadFunc.c |  62 +-
 UefiPayloadPkg/UefiPayloadEntry/RiscV64/Rv64FdtParserLib.c | 625 

 UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c|  29 +-
 UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c  |   9 +
 UefiPayloadPkg/UefiPayloadEntry/X64/X64FdtParserLib.c  |  33 ++
 11 files changed, 1166 insertions(+), 421 deletions(-)
 copy UefiPayloadPkg/{UefiPayloadPkg.dsc => UefiPayloadPkgRV64.dsc} (63%)
 create mode 100644 UefiPayloadPkg/UefiPayloadPkgRV64.fdf
 create mode 100644 UefiPayloadPkg/UefiPayloadEntry/Ia32/Ia32FdtParserLib.c
 copy UefiPayloadPkg/UefiPayloadEntry/{X64 => RiscV64}/DxeLoadFunc.c (51%)
 create mode 100644 UefiPayloadPkg/UefiPayloadEntry/RiscV64/Rv64FdtParserLib.c
 create mode 100644 UefiPayloadPkg/UefiPayloadEntry/X64/X64FdtParserLib.c

-- 
2.34.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#104673): https://edk2.groups.io/g/devel/message/104673
Mute This Topic: https://groups.io/mt/98822671/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

[edk2-devel] [PATCH v1 1/8] UefiPayloadPkg: Remove FP Init from UPL entry

[Dhaval Sharma]

According to UPL spec BL should initialize FP init meaning UPL
does not need to initialize it. Besides this is arch specific init
and needs to be moved out of UPL common flow. In order to not break
current BL implementations, for now just moving the init to later
point of time but for both x32 and x64 eventually this should be
removed once BL impelement this logic.

Test: Verified booting  UEFI shell on coreboot on qemu.

Cc: Guo Dong 
Cc: Ray Ni 
Cc: Sean Rhodes 
Cc: James Lu 
Cc: Gua Guo 

Signed-off-by: Dhaval Sharma 

Reviewed-by: Gua Guo 
Reviewed-by: James Lu 
---

Notes:
v3:
- Added FP initialization to X64 path as well
v4:
- Updated reviewed-by tag

 UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c  | 3 +++
 UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c | 3 ---
 UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c   | 3 +++
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c 
b/UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c
index 61a9f01ec9e7..921a38555e21 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/Ia32/DxeLoadFunc.c
@@ -268,6 +268,9 @@ HandOffToDxeCore (
   UINT32   Index;
   X64_IDT_TABLE*IdtTableForX64;
 
+  // Initialize floating point operating environment to be compliant with UEFI 
spec.
+  InitializeFloatingPointUnits ();
+
   //
   // Clear page 0 and mark it as allocated if NULL pointer detection is 
enabled.
   //
diff --git a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c 
b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c
index f8939efe70db..8aff00142971 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c
@@ -473,9 +473,6 @@ _ModuleEntryPoint (
 PrintHob (mHobList);
 );
 
-  // Initialize floating point operating environment to be compliant with UEFI 
spec.
-  InitializeFloatingPointUnits ();
-
   // Build HOB based on information from Bootloader
   Status = BuildHobs (BootloaderParameter, );
   ASSERT_EFI_ERROR (Status);
diff --git a/UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c 
b/UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c
index 346e3feb0459..84a6112ce64a 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c
@@ -40,6 +40,9 @@ HandOffToDxeCore (
   VOID   *GhcbBase;
   UINTN  GhcbSize;
 
+  // Initialize floating point operating environment to be compliant with UEFI 
spec.
+  InitializeFloatingPointUnits ();
+
   //
   // Clear page 0 and mark it as allocated if NULL pointer detection is 
enabled.
   //
-- 
2.34.1



-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#104672): https://edk2.groups.io/g/devel/message/104672
Mute This Topic: https://groups.io/mt/98822676/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-