Re: [edk2-devel] [PATCH v4 3/4] UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension
On Tue, Mar 19, 2024 at 9:45 AM Tuan Phan via groups.io wrote:
> Hi Sunil,
>
> On Mon, Mar 18, 2024 at 6:00 AM Sunil V L
> wrote:
>
>> Hi Tuan,
>>
>> On Thu, Mar 14, 2024 at 01:19:16PM -0700, Tuan Phan wrote:
>> > The GCD EFI_MEMORY_UC and EFI_MEMORY_WC memory attributes will be
>> > supported when Svpbmt extension available.
>> >
>> > Cc: Gerd Hoffmann
>> > Cc: Laszlo Ersek
>> > Cc: Rahul Kumar
>> > Cc: Ray Ni
>> > Signed-off-by: Tuan Phan
>> > ---
>> > .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 106 ++
>> > .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 1 +
>> > 2 files changed, 86 insertions(+), 21 deletions(-)
>> >
>> > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
>> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
>> > index 46ba4b4709b1..34300dca5c34 100644
>> > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
>> > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
>> > @@ -36,6 +36,11 @@
>> > #define PTE_PPN_SHIFT 10
>> > #define RISCV_MMU_PAGE_SHIFT 12
>> >
>> > +#define RISCV_CPU_FEATURE_PBMT_BITMASK BIT2
>> > +#define PTE_PBMT_NC BIT61
>> > +#define PTE_PBMT_IO BIT62
>> > +#define PTE_PBMT_MASK (PTE_PBMT_NC | PTE_PBMT_IO)
>> > +
>> > STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
>> SATP_MODE_SV39, SATP_MODE_OFF };
>> > STATIC UINTN mMaxRootTableLevel;
>> > STATIC UINTN mBitPerLevel;
>> > @@ -487,32 +492,82 @@ UpdateRegionMapping (
>> > /**
>> >Convert GCD attribute to RISC-V page attribute.
>> >
>> > - @param GcdAttributes The GCD attribute.
>> > + @param GcdAttributes The GCD attribute.
>> > + @param RiscVAttributes The pointer of RISC-V page attribute.
>> >
>> > - @return The RISC-V page attribute.
>> > + @retval EFI_INVALID_PARAMETER The RiscVAttributes is NULL or cache
>> type mask not valid.
>> > + @retval EFI_SUCCESS The operation succesfully.
>> >
>> > **/
>> > STATIC
>> > -UINT64
>> > +EFI_STATUS
>> > GcdAttributeToPageAttribute (
>> > - IN UINT64 GcdAttributes
>> > + IN UINT64 GcdAttributes,
>> > + OUT UINT64 *RiscVAttributes
>> >)
>> > {
>> > - UINT64 RiscVAttributes;
>> > + UINT64 CacheTypeMask;
>> > + BOOLEAN PmbtExtEnabled;
>> >
>> Why not read the PCD once and save in a static variable?
>>
> I can put it into a static variable if you think it is more clean.
>
Looks like PcdRiscVFeatureOverride can be a patchable PCD so putting it to
a static variable may not work.
>
>> > - RiscVAttributes = RISCV_PG_R | RISCV_PG_W | RISCV_PG_X;
>> > + if (RiscVAttributes == NULL) {
>> > +return EFI_INVALID_PARAMETER;
>> > + }
>> > +
>> > + *RiscVAttributes = RISCV_PG_R | RISCV_PG_W | RISCV_PG_X;
>> > +
>> > + PmbtExtEnabled = FALSE;
>> > + if ((PcdGet64 (PcdRiscVFeatureOverride) &
>> RISCV_CPU_FEATURE_PBMT_BITMASK) != 0) {
>> > +PmbtExtEnabled = TRUE;
>> > + }
>> >
>> >// Determine protection attributes
>> >if ((GcdAttributes & EFI_MEMORY_RO) != 0) {
>> > -RiscVAttributes &= ~(UINT64)(RISCV_PG_W);
>> > +*RiscVAttributes &= ~(UINT64)(RISCV_PG_W);
>> >}
>> >
>> >// Process eXecute Never attribute
>> >if ((GcdAttributes & EFI_MEMORY_XP) != 0) {
>> > -RiscVAttributes &= ~(UINT64)RISCV_PG_X;
>> > +*RiscVAttributes &= ~(UINT64)RISCV_PG_X;
>> > + }
>> > +
>> > + CacheTypeMask = GcdAttributes & EFI_CACHE_ATTRIBUTE_MASK;
>> > + if ((CacheTypeMask != 0) &&
>> > + (((CacheTypeMask - 1) & CacheTypeMask) != 0))
>> > + {
>> > +DEBUG ((
>> > + DEBUG_ERROR,
>> > + "%a: More than one bit set in cache type mask (0x%LX)\n",
>> > + __func__,
>> > + CacheTypeMask
>> > + ));
>> > +return EFI_INVALID_PARAMETER;
>> > + }
>> > +
>> > + switch (CacheTypeMask) {
>> > +case EFI_MEMORY_UC:
>> > + if (PmbtExtEnabled) {
>> > +*RiscVAttributes |= PTE_PBMT_IO;
>> >
Re: [edk2-devel] [PATCH v4 3/4] UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension
Hi Sunil,
On Mon, Mar 18, 2024 at 6:00 AM Sunil V L wrote:
> Hi Tuan,
>
> On Thu, Mar 14, 2024 at 01:19:16PM -0700, Tuan Phan wrote:
> > The GCD EFI_MEMORY_UC and EFI_MEMORY_WC memory attributes will be
> > supported when Svpbmt extension available.
> >
> > Cc: Gerd Hoffmann
> > Cc: Laszlo Ersek
> > Cc: Rahul Kumar
> > Cc: Ray Ni
> > Signed-off-by: Tuan Phan
> > ---
> > .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 106 ++
> > .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 1 +
> > 2 files changed, 86 insertions(+), 21 deletions(-)
> >
> > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > index 46ba4b4709b1..34300dca5c34 100644
> > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > @@ -36,6 +36,11 @@
> > #define PTE_PPN_SHIFT 10
> > #define RISCV_MMU_PAGE_SHIFT 12
> >
> > +#define RISCV_CPU_FEATURE_PBMT_BITMASK BIT2
> > +#define PTE_PBMT_NC BIT61
> > +#define PTE_PBMT_IO BIT62
> > +#define PTE_PBMT_MASK (PTE_PBMT_NC | PTE_PBMT_IO)
> > +
> > STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
> SATP_MODE_SV39, SATP_MODE_OFF };
> > STATIC UINTN mMaxRootTableLevel;
> > STATIC UINTN mBitPerLevel;
> > @@ -487,32 +492,82 @@ UpdateRegionMapping (
> > /**
> >Convert GCD attribute to RISC-V page attribute.
> >
> > - @param GcdAttributes The GCD attribute.
> > + @param GcdAttributes The GCD attribute.
> > + @param RiscVAttributes The pointer of RISC-V page attribute.
> >
> > - @return The RISC-V page attribute.
> > + @retval EFI_INVALID_PARAMETER The RiscVAttributes is NULL or cache
> type mask not valid.
> > + @retval EFI_SUCCESS The operation succesfully.
> >
> > **/
> > STATIC
> > -UINT64
> > +EFI_STATUS
> > GcdAttributeToPageAttribute (
> > - IN UINT64 GcdAttributes
> > + IN UINT64 GcdAttributes,
> > + OUT UINT64 *RiscVAttributes
> >)
> > {
> > - UINT64 RiscVAttributes;
> > + UINT64 CacheTypeMask;
> > + BOOLEAN PmbtExtEnabled;
> >
> Why not read the PCD once and save in a static variable?
>
I can put it into a static variable if you think it is more clean.
>
> > - RiscVAttributes = RISCV_PG_R | RISCV_PG_W | RISCV_PG_X;
> > + if (RiscVAttributes == NULL) {
> > +return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + *RiscVAttributes = RISCV_PG_R | RISCV_PG_W | RISCV_PG_X;
> > +
> > + PmbtExtEnabled = FALSE;
> > + if ((PcdGet64 (PcdRiscVFeatureOverride) &
> RISCV_CPU_FEATURE_PBMT_BITMASK) != 0) {
> > +PmbtExtEnabled = TRUE;
> > + }
> >
> >// Determine protection attributes
> >if ((GcdAttributes & EFI_MEMORY_RO) != 0) {
> > -RiscVAttributes &= ~(UINT64)(RISCV_PG_W);
> > +*RiscVAttributes &= ~(UINT64)(RISCV_PG_W);
> >}
> >
> >// Process eXecute Never attribute
> >if ((GcdAttributes & EFI_MEMORY_XP) != 0) {
> > -RiscVAttributes &= ~(UINT64)RISCV_PG_X;
> > +*RiscVAttributes &= ~(UINT64)RISCV_PG_X;
> > + }
> > +
> > + CacheTypeMask = GcdAttributes & EFI_CACHE_ATTRIBUTE_MASK;
> > + if ((CacheTypeMask != 0) &&
> > + (((CacheTypeMask - 1) & CacheTypeMask) != 0))
> > + {
> > +DEBUG ((
> > + DEBUG_ERROR,
> > + "%a: More than one bit set in cache type mask (0x%LX)\n",
> > + __func__,
> > + CacheTypeMask
> > + ));
> > +return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + switch (CacheTypeMask) {
> > +case EFI_MEMORY_UC:
> > + if (PmbtExtEnabled) {
> > +*RiscVAttributes |= PTE_PBMT_IO;
> > + }
> > +
> > + break;
> > +case EFI_MEMORY_WC:
> > + if (PmbtExtEnabled) {
> > +*RiscVAttributes |= PTE_PBMT_NC;
> > + } else {
> > +DEBUG ((
> > + DEBUG_VERBOSE,
> > + "%a: EFI_MEMORY_WC set but Pmbt extension not available\n",
> > + __func__
> > + ));
> > + }
> > +
> > + break;
> > +default:
> > + // Default PMA mode
> > + break;
> >}
> >
> > - return RiscVAttributes;
> > + return EFI_SUCCESS;
> > }
>
[edk2-devel] [PATCH v4 3/4] UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension
The GCD EFI_MEMORY_UC and EFI_MEMORY_WC memory attributes will be
supported when Svpbmt extension available.
Cc: Gerd Hoffmann
Cc: Laszlo Ersek
Cc: Rahul Kumar
Cc: Ray Ni
Signed-off-by: Tuan Phan
---
.../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 106 ++
.../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 1 +
2 files changed, 86 insertions(+), 21 deletions(-)
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
index 46ba4b4709b1..34300dca5c34 100644
--- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
@@ -36,6 +36,11 @@
#define PTE_PPN_SHIFT 10
#define RISCV_MMU_PAGE_SHIFT 12
+#define RISCV_CPU_FEATURE_PBMT_BITMASK BIT2
+#define PTE_PBMT_NC BIT61
+#define PTE_PBMT_IO BIT62
+#define PTE_PBMT_MASK (PTE_PBMT_NC | PTE_PBMT_IO)
+
STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
SATP_MODE_SV39, SATP_MODE_OFF };
STATIC UINTN mMaxRootTableLevel;
STATIC UINTN mBitPerLevel;
@@ -487,32 +492,82 @@ UpdateRegionMapping (
/**
Convert GCD attribute to RISC-V page attribute.
- @param GcdAttributes The GCD attribute.
+ @param GcdAttributes The GCD attribute.
+ @param RiscVAttributes The pointer of RISC-V page attribute.
- @return The RISC-V page attribute.
+ @retval EFI_INVALID_PARAMETER The RiscVAttributes is NULL or cache type
mask not valid.
+ @retval EFI_SUCCESS The operation succesfully.
**/
STATIC
-UINT64
+EFI_STATUS
GcdAttributeToPageAttribute (
- IN UINT64 GcdAttributes
+ IN UINT64 GcdAttributes,
+ OUT UINT64 *RiscVAttributes
)
{
- UINT64 RiscVAttributes;
+ UINT64 CacheTypeMask;
+ BOOLEAN PmbtExtEnabled;
- RiscVAttributes = RISCV_PG_R | RISCV_PG_W | RISCV_PG_X;
+ if (RiscVAttributes == NULL) {
+return EFI_INVALID_PARAMETER;
+ }
+
+ *RiscVAttributes = RISCV_PG_R | RISCV_PG_W | RISCV_PG_X;
+
+ PmbtExtEnabled = FALSE;
+ if ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_PBMT_BITMASK) !=
0) {
+PmbtExtEnabled = TRUE;
+ }
// Determine protection attributes
if ((GcdAttributes & EFI_MEMORY_RO) != 0) {
-RiscVAttributes &= ~(UINT64)(RISCV_PG_W);
+*RiscVAttributes &= ~(UINT64)(RISCV_PG_W);
}
// Process eXecute Never attribute
if ((GcdAttributes & EFI_MEMORY_XP) != 0) {
-RiscVAttributes &= ~(UINT64)RISCV_PG_X;
+*RiscVAttributes &= ~(UINT64)RISCV_PG_X;
+ }
+
+ CacheTypeMask = GcdAttributes & EFI_CACHE_ATTRIBUTE_MASK;
+ if ((CacheTypeMask != 0) &&
+ (((CacheTypeMask - 1) & CacheTypeMask) != 0))
+ {
+DEBUG ((
+ DEBUG_ERROR,
+ "%a: More than one bit set in cache type mask (0x%LX)\n",
+ __func__,
+ CacheTypeMask
+ ));
+return EFI_INVALID_PARAMETER;
+ }
+
+ switch (CacheTypeMask) {
+case EFI_MEMORY_UC:
+ if (PmbtExtEnabled) {
+*RiscVAttributes |= PTE_PBMT_IO;
+ }
+
+ break;
+case EFI_MEMORY_WC:
+ if (PmbtExtEnabled) {
+*RiscVAttributes |= PTE_PBMT_NC;
+ } else {
+DEBUG ((
+ DEBUG_VERBOSE,
+ "%a: EFI_MEMORY_WC set but Pmbt extension not available\n",
+ __func__
+ ));
+ }
+
+ break;
+default:
+ // Default PMA mode
+ break;
}
- return RiscVAttributes;
+ return EFI_SUCCESS;
}
/**
@@ -535,29 +590,38 @@ RiscVSetMemoryAttributes (
IN UINT64Attributes
)
{
- UINT64 PageAttributesSet;
+ UINT64 PageAttributesSet;
+ UINT64 PageAttributesClear;
+ EFI_STATUS Status;
- PageAttributesSet = GcdAttributeToPageAttribute (Attributes);
+ Status = GcdAttributeToPageAttribute (Attributes, );
+ if (EFI_ERROR (Status)) {
+return Status;
+ }
if (!RiscVMmuEnabled ()) {
return EFI_SUCCESS;
}
- DEBUG (
-(
- DEBUG_VERBOSE,
- "%a: Set %llX page attribute 0x%X\n",
- __func__,
- BaseAddress,
- PageAttributesSet
-)
-);
+ PageAttributesClear = PTE_ATTRIBUTES_MASK;
+ if ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_PBMT_BITMASK) !=
0) {
+PageAttributesClear |= PTE_PBMT_MASK;
+ }
+
+ DEBUG ((
+DEBUG_VERBOSE,
+"%a: %LX: set attributes 0x%LX, clear attributes 0x%LX\n",
+__func__,
+BaseAddress,
+PageAttributesSet,
+PageAttributesClear
+));
return UpdateRegionMapping (
BaseAddress,
Length,
PageAttributesSet,
- PTE_ATTRIBUTES_MASK,
+ PageAttributesClear,
(UINT64 *)RiscVGetRootTranslateTable (),
TRUE
);
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
index 51ebe1750e97..1dbaa81f3608 100644
--- a/UefiCpuPkg/Library/BaseRisc
[edk2-devel] [PATCH v4 1/4] MdePkg.dec: RISC-V: Define override bit for Svpbmt extension
Define the BIT 2 as the override bit for Svpbmt extension. This will be used by RISC-V MMU library to support EFI_MEMORY_UC and EFI_MEMORY_WC. Cc: Liming Gao Cc: Michael D Kinney Cc: Zhiguang Liu Reviewed-by: Laszlo Ersek Signed-off-by: Tuan Phan --- MdePkg/MdePkg.dec | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 0459418906f8..6850acb96b92 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -2407,6 +2407,8 @@ # previous stage has feature enabled and user wants to disable it. # BIT 1 = Supervisor Time Compare (Sstc). This bit is relevant only if # previous stage has feature enabled and user wants to disable it. + # BIT 2 = Page-Based Memory Types (Pbmt). This bit is relevant only if + # previous stage has feature enabled and user wants to disable it. # gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0x|UINT64|0x69 -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#116776): https://edk2.groups.io/g/devel/message/116776 Mute This Topic: https://groups.io/mt/104934687/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v4 2/4] UefiCpuPkg: RISC-V: MMU: Explictly use UINT64 instead of UINTN
While UINTN defined for RISC-V 64 bits is UINT64, explictly using UINT64
for those variables that clearly are UINT64.
Cc: Gerd Hoffmann
Cc: Laszlo Ersek
Cc: Rahul Kumar
Cc: Ray Ni
Signed-off-by: Tuan Phan
---
.../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 158 +-
1 file changed, 76 insertions(+), 82 deletions(-)
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
index 826a1d32a1d4..46ba4b4709b1 100644
--- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
@@ -65,7 +65,7 @@ RiscVMmuEnabled (
**/
STATIC
-UINTN
+UINT64
RiscVGetRootTranslateTable (
VOID
)
@@ -86,7 +86,7 @@ RiscVGetRootTranslateTable (
STATIC
BOOLEAN
IsValidPte (
- IN UINTN Entry
+ IN UINT64 Entry
)
{
if (((Entry & RISCV_PG_V) == 0) ||
@@ -107,9 +107,9 @@ IsValidPte (
**/
STATIC
-UINTN
+UINT64
SetValidPte (
- IN UINTN Entry
+ IN UINT64 Entry
)
{
/* Set Valid and Global mapping bits */
@@ -128,7 +128,7 @@ SetValidPte (
STATIC
BOOLEAN
IsBlockEntry (
- IN UINTN Entry
+ IN UINT64 Entry
)
{
return IsValidPte (Entry) &&
@@ -147,7 +147,7 @@ IsBlockEntry (
STATIC
BOOLEAN
IsTableEntry (
- IN UINTN Entry
+ IN UINT64 Entry
)
{
return IsValidPte (Entry) &&
@@ -163,13 +163,13 @@ IsTableEntry (
**/
STATIC
-UINTN
+UINT64
SetTableEntry (
- IN UINTN Entry
+ IN UINT64 Entry
)
{
Entry = SetValidPte (Entry);
- Entry &= ~(RISCV_PG_X | RISCV_PG_W | RISCV_PG_R);
+ Entry &= ~(UINT64)(RISCV_PG_X | RISCV_PG_W | RISCV_PG_R);
return Entry;
}
@@ -186,9 +186,9 @@ SetTableEntry (
STATIC
VOID
ReplaceTableEntry (
- IN UINTN*Entry,
- IN UINTNValue,
- IN UINTNRegionStart,
+ IN UINT64 *Entry,
+ IN UINT64 Value,
+ IN UINT64 RegionStart,
IN BOOLEAN IsLiveBlockMapping
)
{
@@ -208,9 +208,9 @@ ReplaceTableEntry (
**/
STATIC
-UINTN
+UINT64
GetPpnfromPte (
- IN UINTN Entry
+ IN UINT64 Entry
)
{
return ((Entry & PTE_PPN_MASK) >> PTE_PPN_SHIFT);
@@ -226,13 +226,13 @@ GetPpnfromPte (
**/
STATIC
-UINTN
+UINT64
SetPpnToPte (
- UINTN Entry,
- UINTN Address
+ UINT64 Entry,
+ UINT64 Address
)
{
- UINTN Ppn;
+ UINT64 Ppn;
Ppn = ((Address >> RISCV_MMU_PAGE_SHIFT) << PTE_PPN_SHIFT);
ASSERT (~(Ppn & ~PTE_PPN_MASK));
@@ -250,8 +250,8 @@ SetPpnToPte (
STATIC
VOID
FreePageTablesRecursive (
- IN UINTN *TranslationTable,
- IN UINTN Level
+ IN UINT64 *TranslationTable,
+ IN UINTN Level
)
{
UINTN Index;
@@ -260,8 +260,8 @@ FreePageTablesRecursive (
for (Index = 0; Index < mTableEntryCount; Index++) {
if (IsTableEntry (TranslationTable[Index])) {
FreePageTablesRecursive (
- (UINTN *)(GetPpnfromPte ((TranslationTable[Index])) <<
-RISCV_MMU_PAGE_SHIFT),
+ (UINT64 *)(GetPpnfromPte ((TranslationTable[Index])) <<
+ RISCV_MMU_PAGE_SHIFT),
Level + 1
);
}
@@ -289,22 +289,22 @@ FreePageTablesRecursive (
STATIC
EFI_STATUS
UpdateRegionMappingRecursive (
- IN UINTNRegionStart,
- IN UINTNRegionEnd,
- IN UINTNAttributeSetMask,
- IN UINTNAttributeClearMask,
- IN UINTN*PageTable,
+ IN UINT64 RegionStart,
+ IN UINT64 RegionEnd,
+ IN UINT64 AttributeSetMask,
+ IN UINT64 AttributeClearMask,
+ IN UINT64 *PageTable,
IN UINTNLevel,
IN BOOLEAN TableIsLive
)
{
EFI_STATUS Status;
- UINTN BlockShift;
- UINTN BlockMask;
- UINTN BlockEnd;
- UINTN *Entry;
- UINTN EntryValue;
- UINTN *TranslationTable;
+ UINT64 BlockShift;
+ UINT64 BlockMask;
+ UINT64 BlockEnd;
+ UINT64 *Entry;
+ UINT64 EntryValue;
+ UINT64 *TranslationTable;
BOOLEAN NextTableIsLive;
ASSERT (Level < mMaxRootTableLevel);
@@ -313,18 +313,16 @@ UpdateRegionMappingRecursive (
BlockShift = (mMaxRootTableLevel - Level - 1) * mBitPerLevel +
RISCV_MMU_PAGE_SHIFT;
BlockMask = MAX_ADDRESS >> (64 - BlockShift);
- DEBUG (
-(
- DEBUG_VERBOSE,
- "%a(%d): %llx - %llx set %lx clr %lx\n",
- __func__,
- Level,
- RegionStart,
- RegionEnd,
- AttributeSetMask,
- AttributeClearMask
-)
-);
+ DEBUG ((
+DEBUG_VERBOSE,
+"%a(%d): %LX - %LX set %LX clr %LX\n",
+__func__,
+Level,
+RegionStart,
+RegionEnd,
+AttributeSetMask,
+AttributeClearMask
+));
for ( ; RegionStart < RegionEnd; RegionStart = BlockEnd) {
BlockEnd = MIN (RegionEnd, (RegionStart | BlockMask) + 1);
@@ -380,7 +378,7 @@ UpdateRegionMappingRecursive (
NextTableIsLive = FALSE;
} else {
-TranslationTable = (UINTN *)(GetPpnfromPte (*Entry) <<
RISCV_MMU_PAGE_SHIFT);
+
[edk2-devel] [PATCH v4 4/4] OvmfPkg/RiscVVirt: Disable Svpbmt extension
Disable Svpbmt extension as QEMU not enables it in default config. Cc: Andrei Warkentin Cc: Ard Biesheuvel Cc: Gerd Hoffmann Cc: Jiewen Yao Cc: Sunil V L Reviewed-by: Laszlo Ersek Signed-off-by: Tuan Phan --- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc index 6bc7c90f31dc..b8338d2eb5f5 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc @@ -203,7 +203,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE [PcdsFixedAtBuild.common] - gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFC + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFF8 gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|100 gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|100 gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0 -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#116778): https://edk2.groups.io/g/devel/message/116778 Mute This Topic: https://groups.io/mt/104934689/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v4 0/4] RISC-V: Support Svpbmt extension
This series adds support for RISC-V Svpbmt extension. The GCD EFI_MEMORY_UC and EFI_MEMORY_WC attributes will be mapped to IO and NC mode defined in PBMT field. v4: - Changed UINTN to UINT64. - Fixed format error. - Addressed Andrei's comment. v3: - Addressed Laszlo's comments. v2: - Generated patch for each package. Tuan Phan (4): MdePkg.dec: RISC-V: Define override bit for Svpbmt extension UefiCpuPkg: RISC-V: MMU: Explictly use UINT64 instead of UINTN UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension OvmfPkg/RiscVVirt: Disable Svpbmt extension MdePkg/MdePkg.dec | 2 + OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 +- .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 252 +++--- .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 1 + 4 files changed, 159 insertions(+), 98 deletions(-) -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#116775): https://edk2.groups.io/g/devel/message/116775 Mute This Topic: https://groups.io/mt/104934682/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v3 2/3] UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension
On Mon, Mar 4, 2024 at 10:01 AM Laszlo Ersek wrote:
> On 3/2/24 00:20, Tuan Phan wrote:
> > Thanks for the detailed review. Please see my comments below.
> >
> > On Fri, Mar 1, 2024 at 4:14 AM Laszlo Ersek > <mailto:ler...@redhat.com>> wrote:
> >
> > On 3/1/24 02:29, Tuan Phan wrote:
> > > The GCD EFI_MEMORY_UC and EFI_MEMORY_WC memory attributes will be
> > > supported when Svpbmt extension available.
> > >
> > > Cc: Gerd Hoffmann mailto:kra...@redhat.com>>
> > > Cc: Laszlo Ersek mailto:ler...@redhat.com>>
> > > Cc: Rahul Kumar > <mailto:rahul1.ku...@intel.com>>
> > > Cc: Ray Ni mailto:ray...@intel.com>>
> > > Signed-off-by: Tuan Phan > <mailto:tp...@ventanamicro.com>>
> > > ---
> > > .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 101
> > +++---
> > > .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 1 +
> > > 2 files changed, 88 insertions(+), 14 deletions(-)
> > >
> > > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > > index 826a1d32a1d4..f4419bb8f380 100644
> > > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > > @@ -36,6 +36,11 @@
> > > #define PTE_PPN_SHIFT 10
> > > #define RISCV_MMU_PAGE_SHIFT 12
> > >
> > > +#define RISCV_CPU_FEATURE_PBMT_BITMASK BIT2
> > > +#define PTE_PBMT_NC BIT61
> > > +#define PTE_PBMT_IO BIT62
> > > +#define PTE_PBMT_MASK (PTE_PBMT_NC |
> PTE_PBMT_IO)
> > > +
> > > STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
> > SATP_MODE_SV39, SATP_MODE_OFF };
> > > STATIC UINTN mMaxRootTableLevel;
> > > STATIC UINTN mBitPerLevel;
> > > @@ -489,32 +494,89 @@ UpdateRegionMapping (
> > > /**
> > >Convert GCD attribute to RISC-V page attribute.
> > >
> > > - @param GcdAttributes The GCD attribute.
> > > + @param GcdAttributes The GCD attribute.
> > > + @param RiscVAttribtues The pointer of RISC-V page attribute.
> > >
> > > - @return The RISC-V page attribute.
> > > + @retval EFI_INVALID_PARAMETER The RiscVAttribtues is NULL or
> > cache type mask not valid.
> > > + @retval EFI_SUCCESS The operation succesfully.
> > >
> > > **/
> > > STATIC
> > > -UINTN
> > > +EFI_STATUS
> > > GcdAttributeToPageAttribute (
> > > - IN UINTN GcdAttributes
> > > + IN UINTN GcdAttributes,
> >
> > Just noticing: why is GcdAttributes *not* UINT64 in the first place?
> >
> > All the bit macros we test against it, such as EFI_MEMORY_RO
> > (0x0002ULL) are of type unsigned long long (UINT64).
> >
> > Good catch. Will fix it.
> >
> >
> > > + OUT UINTN *RiscVAttributes
> > >)
> > > {
> > > - UINTN RiscVAttributes;
> > > + UINT64 CacheTypeMask;
> > > + BOOLEAN PmbtExtEnabled = (PcdGet64 (PcdRiscVFeatureOverride) &
> > RISCV_CPU_FEATURE_PBMT_BITMASK) ? TRUE : FALSE;
> >
> > - Per the edk2 coding style, locals should not be initialized
> (separate
> > assignment is needed).
> >
> > - Bitmask checks always need an explicit comparison, such as
> >
> > ((a & b) != 0)
> >
> > or similar. Implicitly interpreting (a & b) as a truth value is not
> > appropriate.
> >
> > - "(whatever) ? TRUE : FALSE" is both bad style and unnecessary.
> >
> > BOOLEAN PmbtExtEnabled;
> >
> > PmbtExtEnabled = (PcdGet64 (PcdRiscVFeatureOverride) &
> > RISCV_CPU_FEATURE_PBMT_BITMASK) != 0;
> >
> > Will fix it.
> >
> > >
> > > - RiscVAttributes = RISCV_PG_R | RISCV_PG_W | RISCV_PG_X;
> > > + if (!RiscVAttributes) {
> >
> > - The coding style requires an explicit nullity check:
> >
> > if (RiscVAttributes == NULL) {
> >
> > Will fix it.
> >
> >
> > > +return EFI_INVALID_PARAME
Re: [edk2-devel] [PATCH v3 2/3] UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension
Thanks for the detailed review. Please see my comments below.
On Fri, Mar 1, 2024 at 4:14 AM Laszlo Ersek wrote:
> On 3/1/24 02:29, Tuan Phan wrote:
> > The GCD EFI_MEMORY_UC and EFI_MEMORY_WC memory attributes will be
> > supported when Svpbmt extension available.
> >
> > Cc: Gerd Hoffmann
> > Cc: Laszlo Ersek
> > Cc: Rahul Kumar
> > Cc: Ray Ni
> > Signed-off-by: Tuan Phan
> > ---
> > .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 101 +++---
> > .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 1 +
> > 2 files changed, 88 insertions(+), 14 deletions(-)
> >
> > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > index 826a1d32a1d4..f4419bb8f380 100644
> > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > @@ -36,6 +36,11 @@
> > #define PTE_PPN_SHIFT 10
> > #define RISCV_MMU_PAGE_SHIFT 12
> >
> > +#define RISCV_CPU_FEATURE_PBMT_BITMASK BIT2
> > +#define PTE_PBMT_NC BIT61
> > +#define PTE_PBMT_IO BIT62
> > +#define PTE_PBMT_MASK (PTE_PBMT_NC | PTE_PBMT_IO)
> > +
> > STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
> SATP_MODE_SV39, SATP_MODE_OFF };
> > STATIC UINTN mMaxRootTableLevel;
> > STATIC UINTN mBitPerLevel;
> > @@ -489,32 +494,89 @@ UpdateRegionMapping (
> > /**
> >Convert GCD attribute to RISC-V page attribute.
> >
> > - @param GcdAttributes The GCD attribute.
> > + @param GcdAttributes The GCD attribute.
> > + @param RiscVAttribtues The pointer of RISC-V page attribute.
> >
> > - @return The RISC-V page attribute.
> > + @retval EFI_INVALID_PARAMETER The RiscVAttribtues is NULL or cache
> type mask not valid.
> > + @retval EFI_SUCCESS The operation succesfully.
> >
> > **/
> > STATIC
> > -UINTN
> > +EFI_STATUS
> > GcdAttributeToPageAttribute (
> > - IN UINTN GcdAttributes
> > + IN UINTN GcdAttributes,
>
> Just noticing: why is GcdAttributes *not* UINT64 in the first place?
>
> All the bit macros we test against it, such as EFI_MEMORY_RO
> (0x0002ULL) are of type unsigned long long (UINT64).
>
Good catch. Will fix it.
>
> > + OUT UINTN *RiscVAttributes
> >)
> > {
> > - UINTN RiscVAttributes;
> > + UINT64 CacheTypeMask;
> > + BOOLEAN PmbtExtEnabled = (PcdGet64 (PcdRiscVFeatureOverride) &
> RISCV_CPU_FEATURE_PBMT_BITMASK) ? TRUE : FALSE;
>
> - Per the edk2 coding style, locals should not be initialized (separate
> assignment is needed).
>
> - Bitmask checks always need an explicit comparison, such as
>
> ((a & b) != 0)
>
> or similar. Implicitly interpreting (a & b) as a truth value is not
> appropriate.
>
> - "(whatever) ? TRUE : FALSE" is both bad style and unnecessary.
>
> BOOLEAN PmbtExtEnabled;
>
> PmbtExtEnabled = (PcdGet64 (PcdRiscVFeatureOverride) &
> RISCV_CPU_FEATURE_PBMT_BITMASK) != 0;
>
> Will fix it.
> >
> > - RiscVAttributes = RISCV_PG_R | RISCV_PG_W | RISCV_PG_X;
> > + if (!RiscVAttributes) {
>
> - The coding style requires an explicit nullity check:
>
> if (RiscVAttributes == NULL) {
>
Will fix it.
>
> > +return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + *RiscVAttributes = RISCV_PG_R | RISCV_PG_W | RISCV_PG_X;
> >
> >// Determine protection attributes
> >if ((GcdAttributes & EFI_MEMORY_RO) != 0) {
> > -RiscVAttributes &= ~(RISCV_PG_W);
> > +*RiscVAttributes &= ~(RISCV_PG_W);
> >}
> >
> >// Process eXecute Never attribute
> >if ((GcdAttributes & EFI_MEMORY_XP) != 0) {
> > -RiscVAttributes &= ~RISCV_PG_X;
> > +*RiscVAttributes &= ~RISCV_PG_X;
> > + }
> > +
>
> My next comment is unrelated to the patch, it's just something that
> catches my eye, and I think is worth fixing:
>
> RISCV_PG_W is BIT2 (0x0004), and RISCV_PG_X is BIT3 (0x0008).
> Meaning, they are of type *signed int* (INT32). Applying the bit-neg
> operator on them produces a negative value (because it flips the sign
> bit), which is very ugly.
>
> I suggest a separate patch for changing these into
>
> ~(UINTN)RISCV_PG_W
> ~(UINTN)RISCV_PG_X
>
> Alternatively, you could do
>
Will fix it in a separate patch along with the above change.
>
> *RiscVAttribu
[edk2-devel] [PATCH v3 3/3] OvmfPkg/RiscVVirt: Disable Svpbmt extension
Disable Svpbmt extension as QEMU not enables it in default config. Cc: Andrei Warkentin Cc: Ard Biesheuvel Cc: Gerd Hoffmann Cc: Jiewen Yao Cc: Sunil V L Reviewed-by: Laszlo Ersek Signed-off-by: Tuan Phan --- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc index 6bc7c90f31dc..b8338d2eb5f5 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc @@ -203,7 +203,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE [PcdsFixedAtBuild.common] - gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFC + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFF8 gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|100 gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|100 gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0 -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#116199): https://edk2.groups.io/g/devel/message/116199 Mute This Topic: https://groups.io/mt/104656467/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v3 2/3] UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension
The GCD EFI_MEMORY_UC and EFI_MEMORY_WC memory attributes will be
supported when Svpbmt extension available.
Cc: Gerd Hoffmann
Cc: Laszlo Ersek
Cc: Rahul Kumar
Cc: Ray Ni
Signed-off-by: Tuan Phan
---
.../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 101 +++---
.../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 1 +
2 files changed, 88 insertions(+), 14 deletions(-)
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
index 826a1d32a1d4..f4419bb8f380 100644
--- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
@@ -36,6 +36,11 @@
#define PTE_PPN_SHIFT 10
#define RISCV_MMU_PAGE_SHIFT 12
+#define RISCV_CPU_FEATURE_PBMT_BITMASK BIT2
+#define PTE_PBMT_NC BIT61
+#define PTE_PBMT_IO BIT62
+#define PTE_PBMT_MASK (PTE_PBMT_NC | PTE_PBMT_IO)
+
STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
SATP_MODE_SV39, SATP_MODE_OFF };
STATIC UINTN mMaxRootTableLevel;
STATIC UINTN mBitPerLevel;
@@ -489,32 +494,89 @@ UpdateRegionMapping (
/**
Convert GCD attribute to RISC-V page attribute.
- @param GcdAttributes The GCD attribute.
+ @param GcdAttributes The GCD attribute.
+ @param RiscVAttribtues The pointer of RISC-V page attribute.
- @return The RISC-V page attribute.
+ @retval EFI_INVALID_PARAMETER The RiscVAttribtues is NULL or cache type
mask not valid.
+ @retval EFI_SUCCESS The operation succesfully.
**/
STATIC
-UINTN
+EFI_STATUS
GcdAttributeToPageAttribute (
- IN UINTN GcdAttributes
+ IN UINTN GcdAttributes,
+ OUT UINTN *RiscVAttributes
)
{
- UINTN RiscVAttributes;
+ UINT64 CacheTypeMask;
+ BOOLEAN PmbtExtEnabled = (PcdGet64 (PcdRiscVFeatureOverride) &
RISCV_CPU_FEATURE_PBMT_BITMASK) ? TRUE : FALSE;
- RiscVAttributes = RISCV_PG_R | RISCV_PG_W | RISCV_PG_X;
+ if (!RiscVAttributes) {
+return EFI_INVALID_PARAMETER;
+ }
+
+ *RiscVAttributes = RISCV_PG_R | RISCV_PG_W | RISCV_PG_X;
// Determine protection attributes
if ((GcdAttributes & EFI_MEMORY_RO) != 0) {
-RiscVAttributes &= ~(RISCV_PG_W);
+*RiscVAttributes &= ~(RISCV_PG_W);
}
// Process eXecute Never attribute
if ((GcdAttributes & EFI_MEMORY_XP) != 0) {
-RiscVAttributes &= ~RISCV_PG_X;
+*RiscVAttributes &= ~RISCV_PG_X;
+ }
+
+ CacheTypeMask = GcdAttributes & EFI_CACHE_ATTRIBUTE_MASK;
+ if ((CacheTypeMask != 0) &&
+ (((CacheTypeMask - 1) & CacheTypeMask) != 0))
+ {
+DEBUG (
+ (
+ DEBUG_ERROR,
+ "%a: The cache type mask (0x%llX) should contain exactly one bit set\n",
+ __func__,
+ CacheTypeMask
+ )
+ );
+return EFI_INVALID_PARAMETER;
}
- return RiscVAttributes;
+ switch (CacheTypeMask) {
+case EFI_MEMORY_UC:
+ if (PmbtExtEnabled) {
+*RiscVAttributes |= PTE_PBMT_IO;
+ } else {
+DEBUG (
+ (
+ DEBUG_VERBOSE,
+ "%a: EFI_MEMORY_UC set but Pmbt extension not available\n",
+ __func__
+ )
+ );
+ }
+
+ break;
+case EFI_MEMORY_WC:
+ if (PmbtExtEnabled) {
+*RiscVAttributes |= PTE_PBMT_NC;
+ } else {
+DEBUG (
+ (
+ DEBUG_VERBOSE,
+ "%a: EFI_MEMORY_WC set but Pmbt extension not available\n",
+ __func__
+ )
+ );
+ }
+
+ break;
+default:
+ // Default PMA mode
+ break;
+ }
+
+ return EFI_SUCCESS;
}
/**
@@ -537,21 +599,32 @@ RiscVSetMemoryAttributes (
IN UINTN Attributes
)
{
- UINTN PageAttributesSet;
+ UINTN PageAttributesSet;
+ UINTN PageAttributesClear;
+ EFI_STATUS Status;
- PageAttributesSet = GcdAttributeToPageAttribute (Attributes);
+ Status = GcdAttributeToPageAttribute (Attributes, );
+ if (EFI_ERROR (Status)) {
+return Status;
+ }
if (!RiscVMmuEnabled ()) {
return EFI_SUCCESS;
}
+ PageAttributesClear = PTE_ATTRIBUTES_MASK;
+ if ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_PBMT_BITMASK) !=
0) {
+PageAttributesClear |= PTE_PBMT_MASK;
+ }
+
DEBUG (
(
DEBUG_VERBOSE,
- "%a: Set %llX page attribute 0x%X\n",
+ "%a: %llX: set attributes 0x%X, clear attributes 0x%X\n",
__func__,
BaseAddress,
- PageAttributesSet
+ PageAttributesSet,
+ PageAttributesClear
)
);
@@ -559,7 +632,7 @@ RiscVSetMemoryAttributes (
BaseAddress,
Length,
PageAttributesSet,
- PTE_ATTRIBUTES_MASK,
+ PageAttributesClear,
(UINTN *)RiscVGetRootTranslateTable (),
TRUE
);
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
b/UefiCpuPkg/Library/Ba
[edk2-devel] [PATCH v3 1/3] MdePkg.dec: RISC-V: Define override bit for Svpbmt extension
Define the BIT 2 as the override bit for Svpbmt extension. This will be used by RISC-V MMU library to support EFI_MEMORY_UC and EFI_MEMORY_WC. Cc: Liming Gao Cc: Michael D Kinney Cc: Zhiguang Liu Reviewed-by: Laszlo Ersek Signed-off-by: Tuan Phan --- MdePkg/MdePkg.dec | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 0459418906f8..6850acb96b92 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -2407,6 +2407,8 @@ # previous stage has feature enabled and user wants to disable it. # BIT 1 = Supervisor Time Compare (Sstc). This bit is relevant only if # previous stage has feature enabled and user wants to disable it. + # BIT 2 = Page-Based Memory Types (Pbmt). This bit is relevant only if + # previous stage has feature enabled and user wants to disable it. # gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0x|UINT64|0x69 -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#116197): https://edk2.groups.io/g/devel/message/116197 Mute This Topic: https://groups.io/mt/104656465/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v3 0/3] RISC-V: Support Svpbmt extension
This series adds support for RISC-V Svpbmt extension. The GCD EFI_MEMORY_UC and EFI_MEMORY_WC attributes will be mapped to IO and NC mode defined in PBMT field. v3: - Addressed Laszlo's comments. v2: - Generated patch for each package. Tuan Phan (3): MdePkg.dec: RISC-V: Define override bit for Svpbmt extension UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension OvmfPkg/RiscVVirt: Disable Svpbmt extension MdePkg/MdePkg.dec | 2 + OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 +- .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 101 +++--- .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 1 + 4 files changed, 91 insertions(+), 15 deletions(-) -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#116196): https://edk2.groups.io/g/devel/message/116196 Mute This Topic: https://groups.io/mt/104656464/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2 2/3] UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension
On Wed, Feb 7, 2024 at 10:15 AM Laszlo Ersek wrote:
> On 2/7/24 02:29, Tuan Phan wrote:
> > The GCD EFI_MEMORY_UC and EFI_MEMORY_WC attributes will be
> > supported when Svpbmt extension available.
> >
> > Signed-off-by: Tuan Phan
> > ---
> > .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 25 ++-
> > .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 1 +
> > 2 files changed, 25 insertions(+), 1 deletion(-)
> >
> > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > index 826a1d32a1d4..c50a28e97e4b 100644
> > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > @@ -36,6 +36,15 @@
> > #define PTE_PPN_SHIFT 10
> > #define RISCV_MMU_PAGE_SHIFT 12
> >
> > +#define RISCV_CPU_FEATURE_PBMT_BITMASK BIT2
> > +#define PTE_PBMT_NC BIT61
> > +#define PTE_PBMT_IO BIT62
> > +#define PTE_PBMT_MASK (PTE_PBMT_NC | PTE_PBMT_IO)
> > +
> > +#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
> > + EFI_MEMORY_WT | EFI_MEMORY_WB | \
> > + EFI_MEMORY_UCE)
> > +
>
> (1) I've stated this elsewhere -- introducing such a macro is justified,
> but calling it EFI_* is not. The EFI_ prefix is reserved for the spec.
>
Will fix it.
>
> > STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
> SATP_MODE_SV39, SATP_MODE_OFF };
> > STATIC UINTN mMaxRootTableLevel;
> > STATIC UINTN mBitPerLevel;
> > @@ -514,6 +523,20 @@ GcdAttributeToPageAttribute (
> > RiscVAttributes &= ~RISCV_PG_X;
> >}
> >
> > + if ((PcdGet64 (PcdRiscVFeatureOverride) &
> RISCV_CPU_FEATURE_PBMT_BITMASK) != 0) {
> > +switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) {
> > + case EFI_MEMORY_UC:
> > +RiscVAttributes |= PTE_PBMT_IO;
> > +break;
> > + case EFI_MEMORY_WC:
> > +RiscVAttributes |= PTE_PBMT_NC;
> > +break;
> > + default:
> > +// Default PMA mode
> > +break;
> > +}
> > + }
> > +
> >return RiscVAttributes;
> > }
> >
>
> Several questions / observations:
>
> (2) If the feature is cleared in the PCD, does it deserve a warning that
> the attribute setting request cannot be honored?
>
Sure, I will add a warning if the feature has not been enabled.
>
> (3) The memory cacheability attributes are expressed as distinct bits of
> a bitmask because, for expressing *capabilities*, they must be possible
> to OR together. However, when setting actual attributes, I think the
> bitmask should contain *exactly* one bit set -- in other words, the
> value of the bitmask should be an integral power of two (that's not hard
> to check).
>
> Do you agree about this? If so, I'd suggest rejecting the request (with
> an appropriate status code) if zero bits, or multiple bits, are set.
>
> UINT64 CacheTypeMask;
>
> CacheType = GcdAttributes & MEMORY_CACHETYPE_MASK;
> if ((CacheType == 0) ||
> (((CacheType - 1) & CacheType) != 0)) {
> return EFI_INVALID_PARAMETER;
> }
> switch (CacheType) {
> ...
> }
>
> This would of course require changing the GcdAttributeToPageAttribute()
> prototype, because right now the function cannot return an error.
>
> That makes sense. Will fix it. Thanks
>
> > @@ -559,7 +582,7 @@ RiscVSetMemoryAttributes (
> > BaseAddress,
> > Length,
> > PageAttributesSet,
> > - PTE_ATTRIBUTES_MASK,
> > + PTE_ATTRIBUTES_MASK | PTE_PBMT_MASK,
> > (UINTN *)RiscVGetRootTranslateTable (),
> > TRUE
> > );
>
> (4) I feel we shouldn't try to clear PTE_PBMT_MASK if
> PcdRiscVFeatureOverride tells us that Svpbmt is not available. Just a
> thought.
>
Sure.
>
> > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > index 51ebe1750e97..1dbaa81f3608 100644
> > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > @@ -28,3 +28,4 @@
> >
> > [Pcd]
> >gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ## CONSUMES
> > + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES
>
> Thanks
> Laszlo
>
>
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Re: [edk2-devel] [PATCH v2 0/3] RISC-V: Support Svpbmt extension
On Tue, Feb 27, 2024 at 8:42 PM Sunil V L wrote: > Hi Tuan, > > On Mon, Feb 26, 2024 at 08:34:22PM -0800, Tuan Phan wrote: > > Hi Sunil/ Andrei, > > Any comments on this series? > > > Did I miss your response to Laszlo's feedback on PATCH 2 - [1]? Apart > from that, don't we need to handle EFI_MEMORY_WT similar to > EFI_MEMORY_WC? > > Somehow I missed that feedback. Thanks. About EFI_MEMORY_WT, ARM treats it as EFI_MEMORY_WC under hood but I don't see RISC-V specs mentions it explicitly so don't feel confident to add that. > [1] - https://edk2.groups.io/g/devel/message/115243 > > Thanks, > Sunil > > Regards, > > > > On Wed, Feb 14, 2024 at 10:16 PM Tuan Phan via groups.io > ventanamicro@groups.io> wrote: > > > > > > > > > > > On Wed, Feb 14, 2024 at 9:43 PM Warkentin, Andrei < > > > andrei.warken...@intel.com> wrote: > > > > > >> Do you mind sharing a GH branch with the patch set? > > >> > > > https://github.com/pttuan/edk2/tree/tphan/riscv_mmu_svpbmt > > > Tuan > > > > > >> > > >> A > > >> > > >> > -Original Message- > > >> > From: Tuan Phan > > >> > Sent: Tuesday, February 6, 2024 7:29 PM > > >> > To: devel@edk2.groups.io > > >> > Cc: Kinney, Michael D ; > > >> > gaolim...@byosoft.com.cn; Liu, Zhiguang ; > > >> > kra...@redhat.com; ler...@redhat.com; Kumar, Rahul R > > >> > ; Ni, Ray ; > > >> > suni...@ventanamicro.com; Yao, Jiewen ; > > >> Warkentin, > > >> > Andrei ; ardb+tianoc...@kernel.org; > Tuan > > >> Phan > > >> > > > >> > Subject: [PATCH v2 0/3] RISC-V: Support Svpbmt extension > > >> > > > >> > This patchset adds support for RISC-V Svpbmt extension. > > >> > > > >> > The GCD EFI_MEMORY_UC and EFI_MEMORY_WC attributes will be mapped to > > >> > IO and NC mode defined in PBMT field. > > >> > > > >> > v2: > > >> > - Generated patch for each package. > > >> > > > >> > Tuan Phan (3): > > >> > MdePkg.dec: RISC-V: Define override bit for Svpbmt extension > > >> > UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension > > >> > OvmfPkg/RiscVVirt: Override Svpbmt extension > > >> > > > >> > MdePkg/MdePkg.dec | 2 ++ > > >> > OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 +- > > >> > .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 25 > ++- > > >> > .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 1 + > > >> > 4 files changed, 28 insertions(+), 2 deletions(-) > > >> > > > >> > -- > > >> > 2.25.1 > > >> > > >> > > > > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#116125): https://edk2.groups.io/g/devel/message/116125 Mute This Topic: https://groups.io/mt/104211191/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2 0/3] RISC-V: Support Svpbmt extension
Hi Sunil/ Andrei, Any comments on this series? Regards, On Wed, Feb 14, 2024 at 10:16 PM Tuan Phan via groups.io wrote: > > > On Wed, Feb 14, 2024 at 9:43 PM Warkentin, Andrei < > andrei.warken...@intel.com> wrote: > >> Do you mind sharing a GH branch with the patch set? >> > https://github.com/pttuan/edk2/tree/tphan/riscv_mmu_svpbmt > Tuan > >> >> A >> >> > -Original Message- >> > From: Tuan Phan >> > Sent: Tuesday, February 6, 2024 7:29 PM >> > To: devel@edk2.groups.io >> > Cc: Kinney, Michael D ; >> > gaolim...@byosoft.com.cn; Liu, Zhiguang ; >> > kra...@redhat.com; ler...@redhat.com; Kumar, Rahul R >> > ; Ni, Ray ; >> > suni...@ventanamicro.com; Yao, Jiewen ; >> Warkentin, >> > Andrei ; ardb+tianoc...@kernel.org; Tuan >> Phan >> > >> > Subject: [PATCH v2 0/3] RISC-V: Support Svpbmt extension >> > >> > This patchset adds support for RISC-V Svpbmt extension. >> > >> > The GCD EFI_MEMORY_UC and EFI_MEMORY_WC attributes will be mapped to >> > IO and NC mode defined in PBMT field. >> > >> > v2: >> > - Generated patch for each package. >> > >> > Tuan Phan (3): >> > MdePkg.dec: RISC-V: Define override bit for Svpbmt extension >> > UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension >> > OvmfPkg/RiscVVirt: Override Svpbmt extension >> > >> > MdePkg/MdePkg.dec | 2 ++ >> > OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 +- >> > .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 25 ++- >> > .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 1 + >> > 4 files changed, 28 insertions(+), 2 deletions(-) >> > >> > -- >> > 2.25.1 >> >> > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#115999): https://edk2.groups.io/g/devel/message/115999 Mute This Topic: https://groups.io/mt/104211191/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v2] OvmfPkg: RiscVVirt: Fix network drivers not be built
Only need to include Network.dsc.inc to have all network
drivers/components be built. Otherwise, there were missing definition
that prevent them from be built for RiscVVirt platform.
Signed-off-by: Tuan Phan
---
v2:
- Rebase
OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 15 +--
1 file changed, 1 insertion(+), 14 deletions(-)
diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
index f8b9479345d7..774dc8184049 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
+++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
@@ -52,6 +52,7 @@
!include MdePkg/MdeLibs.dsc.inc
+!include NetworkPkg/Network.dsc.inc
[BuildOptions]
GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
@@ -69,8 +70,6 @@
#
-!include NetworkPkg/NetworkDefines.dsc.inc
-
!include OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
!include MdePkg/MdeLibs.dsc.inc
@@ -126,8 +125,6 @@
UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
PciExpressLib|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpressLib.inf
-#!include NetworkPkg/NetworkBuildOptions.dsc.inc
-
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
@@ -166,11 +163,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|3686400
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1
- #
- # Network Pcds
- #
-!include NetworkPkg/NetworkPcds.dsc.inc
-
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c,
0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
@@ -399,11 +391,6 @@
NULL|OvmfPkg/Library/BlobVerifierLibNull/BlobVerifierLibNull.inf
}
- #
- # Networking stack
- #
-!include NetworkPkg/NetworkComponents.dsc.inc
-
NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf {
NULL|OvmfPkg/Library/PxeBcPcdProducerLib/PxeBcPcdProducerLib.inf
--
2.25.1
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Re: [edk2-devel] [PATCH v3 7/7] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices
On Thu, Dec 7, 2023 at 11:36 PM Andrei Warkentin
wrote:
> Hi Tuan,
>
>
>
> I noticed that the OvmfPkg RV Sec uses PopulateIoResources by adding
> entries to GCD of type EFI_RESOURCE_MEMORY_MAPPED_IO. Contrast this with
> edk2-platforms/Platforms/RaspberryPi/Library/MemoryInitPeiLib/MemoryInitPeiLib.c,
> which adds these as memory and then allocates them away as
> EfiReservedMemoryType. I remember this came up during the upstreaming of
> the Raspberry Pi port…
>
>
>
> Anything we add as MMIO will end up growing the Runtime Services mappings,
> as MMIO are specifically non-memory mappings that need to be present during
> OS use of RT services. It’s probably a good idea to avoid using MMIO
> regions for all I/O used by Boot Services.
>
>
>
Agree. Will post a patch to fix it.
> A
>
>
>
>
>
> *From:* Tuan Phan
> *Sent:* Thursday, June 22, 2023 3:28 PM
> *To:* devel@edk2.groups.io; tp...@ventanamicro.com
> *Cc:* Ard Biesheuvel ; Kinney, Michael D <
> michael.d.kin...@intel.com>; Gao, Liming ; Liu,
> Zhiguang ; suni...@ventanamicro.com;
> g...@danielschaefer.me; Warkentin, Andrei
> *Subject:* Re: [edk2-devel] [PATCH v3 7/7] OvmfPkg/RiscVVirt: SEC: Add IO
> memory resource hob for platform devices
>
>
>
>
>
>
>
> On Thu, Jun 22, 2023 at 11:41 AM Tuan Phan wrote:
>
>
>
>
>
> On Tue, May 30, 2023 at 10:38 AM Tuan Phan via groups.io ventanamicro@groups.io> wrote:
>
>
>
>
>
> On Mon, May 29, 2023 at 7:07 AM Ard Biesheuvel wrote:
>
> On Sat, 27 May 2023 at 01:18, Tuan Phan wrote:
> >
> > Normally, DXE driver would add device resource to GCD before start using.
> > But some key resources such as uart, flash base address are being
> accessing
> > directly in some core modules.
> >
> > Those resources should be populated to HOB in SEC phase so they are
> > added to GCD before anyone can access them.
> >
>
> Why should these be in the GCD to begin with?
>
>
>
> These resources should be in memory space so their addresses and size are
> registered with MMU. If not when MMU enabled, illegal access exception when
> someone access them.
>
>
>
> Hi Ard,
>
> Do you still have concerns about this patch?
>
> BTW, I will drop this patch and put VirtNorFlashDxe in APRIORI DXE list to
> make sure it runs before VariableRuntimeDxe.
>
>
> > Signed-off-by: Tuan Phan
> > Reviewed-by: Andrei Warkentin
>
> > ---
> > OvmfPkg/RiscVVirt/Sec/Platform.c | 62 +++
> > OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 +
> > 2 files changed, 63 insertions(+)
> >
> > diff --git a/OvmfPkg/RiscVVirt/Sec/Platform.c
> b/OvmfPkg/RiscVVirt/Sec/Platform.c
> > index 3645c27b0b12..944b82c84a6e 100644
> > --- a/OvmfPkg/RiscVVirt/Sec/Platform.c
> > +++ b/OvmfPkg/RiscVVirt/Sec/Platform.c
> > @@ -21,6 +21,63 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> > #include
> > #include
> >
> > +/**
> > + Build memory map I/O range resource HOB using the
> > + base address and size.
> > +
> > + @param MemoryBase Memory map I/O base.
> > + @param MemorySize Memory map I/O size.
> > +
> > +**/
> > +STATIC
> > +VOID
> > +AddIoMemoryBaseSizeHob (
> > + EFI_PHYSICAL_ADDRESS MemoryBase,
> > + UINT64MemorySize
> > + )
> > +{
> > + /* Align to EFI_PAGE_SIZE */
> > + MemorySize = ALIGN_VALUE (MemorySize, EFI_PAGE_SIZE);
> > + BuildResourceDescriptorHob (
> > +EFI_RESOURCE_MEMORY_MAPPED_IO,
> > +EFI_RESOURCE_ATTRIBUTE_PRESENT |
> > +EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> > +EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
> > +EFI_RESOURCE_ATTRIBUTE_TESTED,
> > +MemoryBase,
> > +MemorySize
> > +);
> > +}
> > +
> > +/**
> > + Populate IO resources from FDT that not added to GCD by its
> > + driver in the DXE phase.
> > +
> > + @param FdtBase Fdt base address
> > + @param CompatibleCompatible string
> > +
> > +**/
> > +STATIC
> > +VOID
> > +PopulateIoResources (
> > + VOID *FdtBase,
> > + CONST CHAR8* Compatible
> > + )
> > +{
> > + UINT64 *Reg;
> > + INT32 Node, LenP;
> > +
> > + Node = fdt_node_offset_by_compatible (FdtBase, -1, Compatible);
> > + while (Node != -FDT_ERR_NOTFOUND) {
> > +Reg = (UINT64 *)fdt_getprop (FdtBase, Node, "reg", );
> > +if (Reg) {
> > + ASSERT (LenP == (2 * sizeof (UINT64)));
> > + AddIoMemo
Re: [edk2-devel] [PATCH v3 2/2] StandaloneMmPkg: Arm: Update to use the new StandaloneMmCpu driver
Hi Sami,
Not sure if you can merge this series or let me know who can do it.
Thanks,
From: Sami Mujawar
Date: Thursday, October 5, 2023 at 4:12 AM
To: Tuan Phan , devel@edk2.groups.io
Cc: ardb+tianoc...@kernel.org , ray...@intel.com
, huangm...@linux.alibaba.com ,
suni...@ventanamicro.com , yong...@intel.com
, yeoreum@arm.com , n...@arm.com
Subject: Re: [PATCH v3 2/2] StandaloneMmPkg: Arm: Update to use the new
StandaloneMmCpu driver
Hi Tuan,
Thank you for this patch.
These changes look good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 28/09/2023 10:14 pm, Tuan Phan wrote:
> Update entry point library for Arm to use the new architecture independent
> StandaloneMmCpu driver.
>
> Signed-off-by: Tuan Phan
> Reviewed-by: levi.yun
> ---
> .../Library/Arm/StandaloneMmCoreEntryPoint.h | 17 +
> .../Arm/CreateHobList.c | 43 ++--
> .../Arm/StandaloneMmCoreEntryPoint.c | 69 +++
> .../StandaloneMmCoreEntryPoint.inf| 2 +-
> 4 files changed, 67 insertions(+), 64 deletions(-)
>
> diff --git a/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
> b/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
> index 41bf0f132b4f..dbb81610ff8e 100644
> --- a/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
> +++ b/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
> @@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #ifndef __STANDALONEMMCORE_ENTRY_POINT_H__
>
> #define __STANDALONEMMCORE_ENTRY_POINT_H__
>
>
>
> +#include
>
> #include
>
> #include
>
>
>
> @@ -47,18 +48,6 @@ typedef struct {
> EFI_SECURE_PARTITION_CPU_INFO*CpuInfo;
>
> } EFI_SECURE_PARTITION_BOOT_INFO;
>
>
>
> -typedef
>
> -EFI_STATUS
>
> -(*PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT) (
>
> - IN UINTN EventId,
>
> - IN UINTN CpuNumber,
>
> - IN UINTN NsCommBufferAddr
>
> - );
>
> -
>
> -typedef struct {
>
> - PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT*ArmTfCpuDriverEpPtr;
>
> -} ARM_TF_CPU_DRIVER_EP_DESCRIPTOR;
>
> -
>
> typedef RETURN_STATUS (*REGION_PERMISSION_UPDATE_FUNC) (
>
> IN EFI_PHYSICAL_ADDRESS BaseAddress,
>
> IN UINT64Length
>
> @@ -145,8 +134,8 @@ LocateStandaloneMmCorePeCoffData (
> VOID *
>
> EFIAPI
>
> CreateHobListFromBootInfo (
>
> - IN OUT PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
>
> - IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo
>
> + IN OUT PI_MM_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
>
> + IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo
>
> );
>
>
>
> /**
>
> diff --git
> a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
> b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
> index 2ac2d354f06a..80ed532352af 100644
> --- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
> +++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
> @@ -13,6 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #include
>
> #include
>
>
>
> +#include
>
> #include
>
> #include
>
> #include
>
> @@ -39,7 +40,7 @@ extern EFI_GUID gEfiStandaloneMmNonSecureBufferGuid;
> // GUID to identify HOB where the entry point of the CPU driver will be
>
> // populated to allow this entry point driver to invoke it upon receipt of
> an
>
> // event
>
> -extern EFI_GUID gEfiArmTfCpuDriverEpDescriptorGuid;
>
> +extern EFI_GUID gEfiMmCpuDriverEpDescriptorGuid;
>
>
>
> /**
>
> Use the boot information passed by privileged firmware to populate a HOB
> list
>
> @@ -52,22 +53,22 @@ extern EFI_GUID gEfiArmTfCpuDriverEpDescriptorGuid;
> **/
>
> VOID *
>
> CreateHobListFromBootInfo (
>
> - IN OUT PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
>
> - IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo
>
> + IN OUT PI_MM_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
>
> + IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo
>
> )
>
> {
>
> - EFI_HOB_HANDOFF_INFO_TABLE *HobStart;
>
> - EFI_RESOURCE_ATTRIBUTE_TYPE Attributes;
>
> - UINT32 Index;
>
> - UINT32 BufferSize;
>
> - UINT32 Flags;
>
> - EFI_MMRAM_HOB_DESCRIPTOR_BLOCK *MmramRangesHob;
>
> - EFI_MMRAM_DESCRIPTOR *MmramRanges;
>
> - EFI_MMRAM_DESCRIPTOR *NsCommB
Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
https://github.com/pttuan/edk2.git
branch: tphan/riscv_mmu_new_pcd
From: devel@edk2.groups.io on behalf of Andrei Warkentin
Date: Wednesday, October 4, 2023 at 11:42 AM
To: Tuan Phan , devel@edk2.groups.io
Cc: Kinney, Michael D , Gao, Liming
, Liu, Zhiguang ,
suni...@ventanamicro.com , g...@danielschaefer.me
, ardb+tianoc...@kernel.org
Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for
SATP mode
Do you happen to have a link to a Github tree?
A
> -Original Message-
> From: Tuan Phan
> Sent: Tuesday, October 3, 2023 4:00 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
> ; Liu, Zhiguang ;
> suni...@ventanamicro.com; g...@danielschaefer.me; Warkentin, Andrei
> ; ardb+tianoc...@kernel.org; Tuan Phan
>
> Subject: [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
>
> Introduce a PCD to control the maximum SATP mode that MMU allowed to
> use. This PCD helps RISC-V platform set bare or minimum SATA mode during
> bring up to debug memory map issue.
>
> Signed-off-by: Tuan Phan
> ---
> UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 +-
> UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++
> UefiCpuPkg/UefiCpuPkg.dec | 8
> 3 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> index 9cca5fc128af..826a1d32a1d4 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> @@ -36,7 +36,7 @@
> #define PTE_PPN_SHIFT 10 #define RISCV_MMU_PAGE_SHIFT 12 -
> STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
> SATP_MODE_SV39 };+STATIC UINTN mModeSupport[] = { SATP_MODE_SV57,
> SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF }; STATIC UINTN
> mMaxRootTableLevel; STATIC UINTN mBitPerLevel; STATIC UINTN
> mTableEntryCount;@@ -590,6 +590,10 @@ RiscVMmuSetSatpMode (
>UINTNIndex; EFI_STATUS
> Status; + if
> (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {+return
> EFI_DEVICE_ERROR;+ }+ switch (SatpMode) { case SATP_MODE_OFF:
> return EFI_SUCCESS;diff --git
> a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> index 9b28a98cb346..51ebe1750e97 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> @@ -25,3 +25,6 @@
> [LibraryClasses] BaseLib++[Pcd]+
> gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ##
> CONSUMESdiff --git a/UefiCpuPkg/UefiCpuPkg.dec
> b/UefiCpuPkg/UefiCpuPkg.dec
> index 68473fc640e6..79191af18a05 100644
> --- a/UefiCpuPkg/UefiCpuPkg.dec
> +++ b/UefiCpuPkg/UefiCpuPkg.dec
> @@ -396,6 +396,14 @@
># @Prompt Access to non-SMRAM memory is restricted to reserved,
> runtime and ACPI NVS type after SmmReadyToLock.
> gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|B
> OOLEAN|0x3213210F +[PcdsFixedAtBuild.RISCV64]+ ## Indicate the
> maximum SATP mode allowed.+ # 0 - Bare mode.+ # 8 - 39bit mode.+ # 9 -
> 48bit mode.+ # 10 - 57bit mode.+
> gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0|UINT32|0x6
> 021+ [PcdsDynamic, PcdsDynamicEx] ## Contains the pointer to a CPU
> S3 data buffer of structure ACPI_CPU_DATA. # @Prompt The pointer to a CPU
> S3 data buffer.--
> 2.25.1
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[edk2-devel] [PATCH v2] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
Introduce a PCD to control the maximum SATP mode that MMU allowed
to use. This PCD helps RISC-V platform set bare or minimum SATP mode
during bring up to debug memory map issue.
Signed-off-by: Tuan Phan
Reviewed-by: Dhaval Sharma
---
Changes:
V2
- Changed default mode to SV57
UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 +-
UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++
UefiCpuPkg/UefiCpuPkg.dec | 8
3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
index 9cca5fc128af..826a1d32a1d4 100644
--- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
@@ -36,7 +36,7 @@
#define PTE_PPN_SHIFT 10
#define RISCV_MMU_PAGE_SHIFT 12
-STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
SATP_MODE_SV39 };
+STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
SATP_MODE_SV39, SATP_MODE_OFF };
STATIC UINTN mMaxRootTableLevel;
STATIC UINTN mBitPerLevel;
STATIC UINTN mTableEntryCount;
@@ -590,6 +590,10 @@ RiscVMmuSetSatpMode (
UINTNIndex;
EFI_STATUS Status;
+ if (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {
+return EFI_DEVICE_ERROR;
+ }
+
switch (SatpMode) {
case SATP_MODE_OFF:
return EFI_SUCCESS;
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
index 9b28a98cb346..51ebe1750e97 100644
--- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
@@ -25,3 +25,6 @@
[LibraryClasses]
BaseLib
+
+[Pcd]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ## CONSUMES
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 68473fc640e6..0b5431dbf70a 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -396,6 +396,14 @@
# @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and
ACPI NVS type after SmmReadyToLock.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
+[PcdsFixedAtBuild.RISCV64]
+ ## Indicate the maximum SATP mode allowed.
+ # 0 - Bare mode.
+ # 8 - 39bit mode.
+ # 9 - 48bit mode.
+ # 10 - 57bit mode.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|10|UINT32|0x6021
+
[PcdsDynamic, PcdsDynamicEx]
## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
# @Prompt The pointer to a CPU S3 data buffer.
--
2.25.1
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Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
If we agree that default should be 10 then i will change it in the next
version.
On Wed, Oct 4, 2023 at 4:36 AM Sunil V L wrote:
> Hi Tuan,
>
> Thanks for the patch!. Adding UefiCpuPkg maintainers.
>
> On Tue, Oct 03, 2023 at 02:00:21PM -0700, Tuan Phan wrote:
> > Introduce a PCD to control the maximum SATP mode that MMU allowed
> > to use. This PCD helps RISC-V platform set bare or minimum SATA mode
>
> SATA -> SATP
>
> > during bring up to debug memory map issue.
> >
> > Signed-off-by: Tuan Phan
> > ---
> > UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 +-
> > UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++
> > UefiCpuPkg/UefiCpuPkg.dec | 8
> > 3 files changed, 16 insertions(+), 1 deletion(-)
> >
> > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > index 9cca5fc128af..826a1d32a1d4 100644
> > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > @@ -36,7 +36,7 @@
> > #define PTE_PPN_SHIFT 10
> > #define RISCV_MMU_PAGE_SHIFT 12
> >
> > -STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
> SATP_MODE_SV39 };
> > +STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
> SATP_MODE_SV39, SATP_MODE_OFF };
> > STATIC UINTN mMaxRootTableLevel;
> > STATIC UINTN mBitPerLevel;
> > STATIC UINTN mTableEntryCount;
> > @@ -590,6 +590,10 @@ RiscVMmuSetSatpMode (
> >UINTNIndex;
> >EFI_STATUS Status;
> >
> > + if (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {
> > +return EFI_DEVICE_ERROR;
> > + }
> > +
> >switch (SatpMode) {
> > case SATP_MODE_OFF:
> >return EFI_SUCCESS;
> > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > index 9b28a98cb346..51ebe1750e97 100644
> > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > @@ -25,3 +25,6 @@
> >
> > [LibraryClasses]
> >BaseLib
> > +
> > +[Pcd]
> > + gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ## CONSUMES
> > diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
> > index 68473fc640e6..79191af18a05 100644
> > --- a/UefiCpuPkg/UefiCpuPkg.dec
> > +++ b/UefiCpuPkg/UefiCpuPkg.dec
> > @@ -396,6 +396,14 @@
> ># @Prompt Access to non-SMRAM memory is restricted to reserved,
> runtime and ACPI NVS type after SmmReadyToLock.
> >
> gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
> >
> > +[PcdsFixedAtBuild.RISCV64]
> > + ## Indicate the maximum SATP mode allowed.
> > + # 0 - Bare mode.
> > + # 8 - 39bit mode.
> > + # 9 - 48bit mode.
> > + # 10 - 57bit mode.
> > +
> gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0|UINT32|0x6021
> > +
> Shouldn't the default value be 10?
>
> Thanks,
> Sunil
>
> > [PcdsDynamic, PcdsDynamicEx]
> >## Contains the pointer to a CPU S3 data buffer of structure
> ACPI_CPU_DATA.
> ># @Prompt The pointer to a CPU S3 data buffer.
> > --
> > 2.25.1
> >
>
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[edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
Introduce a PCD to control the maximum SATP mode that MMU allowed
to use. This PCD helps RISC-V platform set bare or minimum SATA mode
during bring up to debug memory map issue.
Signed-off-by: Tuan Phan
---
UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 +-
UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++
UefiCpuPkg/UefiCpuPkg.dec | 8
3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
index 9cca5fc128af..826a1d32a1d4 100644
--- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
@@ -36,7 +36,7 @@
#define PTE_PPN_SHIFT 10
#define RISCV_MMU_PAGE_SHIFT 12
-STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
SATP_MODE_SV39 };
+STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
SATP_MODE_SV39, SATP_MODE_OFF };
STATIC UINTN mMaxRootTableLevel;
STATIC UINTN mBitPerLevel;
STATIC UINTN mTableEntryCount;
@@ -590,6 +590,10 @@ RiscVMmuSetSatpMode (
UINTNIndex;
EFI_STATUS Status;
+ if (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {
+return EFI_DEVICE_ERROR;
+ }
+
switch (SatpMode) {
case SATP_MODE_OFF:
return EFI_SUCCESS;
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
index 9b28a98cb346..51ebe1750e97 100644
--- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
@@ -25,3 +25,6 @@
[LibraryClasses]
BaseLib
+
+[Pcd]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ## CONSUMES
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 68473fc640e6..79191af18a05 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -396,6 +396,14 @@
# @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and
ACPI NVS type after SmmReadyToLock.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
+[PcdsFixedAtBuild.RISCV64]
+ ## Indicate the maximum SATP mode allowed.
+ # 0 - Bare mode.
+ # 8 - 39bit mode.
+ # 9 - 48bit mode.
+ # 10 - 57bit mode.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0|UINT32|0x6021
+
[PcdsDynamic, PcdsDynamicEx]
## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
# @Prompt The pointer to a CPU S3 data buffer.
--
2.25.1
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Re: [edk2-devel] [PATCH v2 2/2] StandaloneMmPkg: Arm: Update to use the new StandaloneMmCpu driver
Hi Sami,
I just sent the V3 series to address your comments.
Regards,
On Thu, Sep 28, 2023 at 11:16 AM Tuan Phan via groups.io wrote:
> Hi Sami,
> Please see my comments below.
>
> On Thu, Sep 28, 2023 at 9:16 AM Sami Mujawar wrote:
>
>> Hi Tuan,
>>
>> Thank you for this patch.
>>
>> Please see my response inline marked [SAMI].
>>
>> Regards,
>>
>> Sami Mujawar
>>
>> On 15/09/2023 12:10 am, Tuan Phan wrote:
>> > Update entry point library for Arm to use the new platform independent
>>
>> [SAMI] Should this be worded as architecture independent instead of
>> platform independent?
>>
>> Can you also check the subject line and commit message for patch 1/2,
>> please?
>>
> [Tuan] Sure, that makes sense.
>
>>
>> [/SAMI]
>>
>> > StandaloneMmCpu driver.
>> >
>> > Signed-off-by: Tuan Phan
>> > ---
>> > .../Library/Arm/StandaloneMmCoreEntryPoint.h | 17 ++--
>> > .../Arm/CreateHobList.c | 43 ++-
>> > .../Arm/StandaloneMmCoreEntryPoint.c | 15 ++-
>> > .../StandaloneMmCoreEntryPoint.inf| 2 +-
>> > 4 files changed, 40 insertions(+), 37 deletions(-)
>> >
>> > diff --git
>> a/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
>> b/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
>> > index 41bf0f132b4f..dbb81610ff8e 100644
>> > --- a/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
>> > +++ b/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
>> > @@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
>> > #ifndef __STANDALONEMMCORE_ENTRY_POINT_H__
>> >
>> > #define __STANDALONEMMCORE_ENTRY_POINT_H__
>> >
>> >
>> >
>> > +#include
>> >
>> > #include
>> >
>> > #include
>> >
>> >
>> >
>> > @@ -47,18 +48,6 @@ typedef struct {
>> > EFI_SECURE_PARTITION_CPU_INFO*CpuInfo;
>> >
>> > } EFI_SECURE_PARTITION_BOOT_INFO;
>> >
>> >
>> >
>> > -typedef
>> >
>> > -EFI_STATUS
>> >
>> > -(*PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT) (
>> >
>> > - IN UINTN EventId,
>> >
>> > - IN UINTN CpuNumber,
>> >
>> > - IN UINTN NsCommBufferAddr
>> >
>> > - );
>> >
>> > -
>> >
>> > -typedef struct {
>> >
>> > - PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT*ArmTfCpuDriverEpPtr;
>> >
>> > -} ARM_TF_CPU_DRIVER_EP_DESCRIPTOR;
>> >
>> > -
>> >
>> > typedef RETURN_STATUS (*REGION_PERMISSION_UPDATE_FUNC) (
>> >
>> > IN EFI_PHYSICAL_ADDRESS BaseAddress,
>> >
>> > IN UINT64Length
>> >
>> > @@ -145,8 +134,8 @@ LocateStandaloneMmCorePeCoffData (
>> > VOID *
>> >
>> > EFIAPI
>> >
>> > CreateHobListFromBootInfo (
>> >
>> > - IN OUT PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
>> >
>> > - IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo
>> >
>> > + IN OUT PI_MM_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
>> >
>> > + IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo
>> >
>> > );
>> >
>> >
>> >
>> > /**
>> >
>> > diff --git
>> a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
>> b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
>> > index 2ac2d354f06a..80ed532352af 100644
>> > ---
>> a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
>> > +++
>> b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
>> > @@ -13,6 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
>> > #include
>> >
>> > #include
>> >
>> >
>> >
>> > +#include
>> >
>> > #include
>> >
>> > #include
>> >
>> > #include
>> >
>> > @@ -39,7 +40,7 @@ extern EFI_GUID gEfiStandaloneMmNonSecureBufferGuid;
>> > // GUID to identify HOB where the entry point of the CPU driver will
>> be
>> >
>> > // populated to allow this entry point driver to invoke it upon
>> receipt
[edk2-devel] [PATCH v3 2/2] StandaloneMmPkg: Arm: Update to use the new StandaloneMmCpu driver
Update entry point library for Arm to use the new architecture independent
StandaloneMmCpu driver.
Signed-off-by: Tuan Phan
Reviewed-by: levi.yun
---
.../Library/Arm/StandaloneMmCoreEntryPoint.h | 17 +
.../Arm/CreateHobList.c | 43 ++--
.../Arm/StandaloneMmCoreEntryPoint.c | 69 +++
.../StandaloneMmCoreEntryPoint.inf| 2 +-
4 files changed, 67 insertions(+), 64 deletions(-)
diff --git a/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
b/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
index 41bf0f132b4f..dbb81610ff8e 100644
--- a/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
+++ b/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
@@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef __STANDALONEMMCORE_ENTRY_POINT_H__
#define __STANDALONEMMCORE_ENTRY_POINT_H__
+#include
#include
#include
@@ -47,18 +48,6 @@ typedef struct {
EFI_SECURE_PARTITION_CPU_INFO*CpuInfo;
} EFI_SECURE_PARTITION_BOOT_INFO;
-typedef
-EFI_STATUS
-(*PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT) (
- IN UINTN EventId,
- IN UINTN CpuNumber,
- IN UINTN NsCommBufferAddr
- );
-
-typedef struct {
- PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT*ArmTfCpuDriverEpPtr;
-} ARM_TF_CPU_DRIVER_EP_DESCRIPTOR;
-
typedef RETURN_STATUS (*REGION_PERMISSION_UPDATE_FUNC) (
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64Length
@@ -145,8 +134,8 @@ LocateStandaloneMmCorePeCoffData (
VOID *
EFIAPI
CreateHobListFromBootInfo (
- IN OUT PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
- IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo
+ IN OUT PI_MM_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
+ IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo
);
/**
diff --git
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
index 2ac2d354f06a..80ed532352af 100644
--- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
+++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
@@ -13,6 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include
#include
+#include
#include
#include
#include
@@ -39,7 +40,7 @@ extern EFI_GUID gEfiStandaloneMmNonSecureBufferGuid;
// GUID to identify HOB where the entry point of the CPU driver will be
// populated to allow this entry point driver to invoke it upon receipt of an
// event
-extern EFI_GUID gEfiArmTfCpuDriverEpDescriptorGuid;
+extern EFI_GUID gEfiMmCpuDriverEpDescriptorGuid;
/**
Use the boot information passed by privileged firmware to populate a HOB list
@@ -52,22 +53,22 @@ extern EFI_GUID gEfiArmTfCpuDriverEpDescriptorGuid;
**/
VOID *
CreateHobListFromBootInfo (
- IN OUT PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
- IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo
+ IN OUT PI_MM_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
+ IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo
)
{
- EFI_HOB_HANDOFF_INFO_TABLE *HobStart;
- EFI_RESOURCE_ATTRIBUTE_TYPE Attributes;
- UINT32 Index;
- UINT32 BufferSize;
- UINT32 Flags;
- EFI_MMRAM_HOB_DESCRIPTOR_BLOCK *MmramRangesHob;
- EFI_MMRAM_DESCRIPTOR *MmramRanges;
- EFI_MMRAM_DESCRIPTOR *NsCommBufMmramRange;
- MP_INFORMATION_HOB_DATA *MpInformationHobData;
- EFI_PROCESSOR_INFORMATION*ProcInfoBuffer;
- EFI_SECURE_PARTITION_CPU_INFO*CpuInfo;
- ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *CpuDriverEntryPointDesc;
+ EFI_HOB_HANDOFF_INFO_TABLE *HobStart;
+ EFI_RESOURCE_ATTRIBUTE_TYPE Attributes;
+ UINT32 Index;
+ UINT32 BufferSize;
+ UINT32 Flags;
+ EFI_MMRAM_HOB_DESCRIPTOR_BLOCK *MmramRangesHob;
+ EFI_MMRAM_DESCRIPTOR*MmramRanges;
+ EFI_MMRAM_DESCRIPTOR*NsCommBufMmramRange;
+ MP_INFORMATION_HOB_DATA *MpInformationHobData;
+ EFI_PROCESSOR_INFORMATION *ProcInfoBuffer;
+ EFI_SECURE_PARTITION_CPU_INFO *CpuInfo;
+ MM_CPU_DRIVER_EP_DESCRIPTOR *CpuDriverEntryPointDesc;
// Create a hoblist with a PHIT and EOH
HobStart = HobConstructor (
@@ -144,13 +145,13 @@ CreateHobListFromBootInfo (
// Create a Guided HOB to enable the ARM TF CPU driver to share its entry
// point and populate it with the address of the shared buffer
- CpuDriverEntryPointDesc = (ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *)BuildGuidHob (
-
,
- sizeof
(ARM_TF_CPU_DRIVER_EP_DESCRIPTOR)
- );
+ CpuDriverEntryPointDesc
[edk2-devel] [PATCH v3 1/2] StandaloneMmPkg: Make StandaloneMmCpu driver architecture independent
StandaloneMmCpu now can supports more architectures like RISC-V besides
ARM/AARCH64.
Signed-off-by: Tuan Phan
Reviewed-by: levi.yun
Reviewed-by: Sami Mujawar
---
.../Drivers/StandaloneMmCpu/EventHandle.c | 25 +++
.../Drivers/StandaloneMmCpu/StandaloneMmCpu.c | 42 +--
.../StandaloneMmCpu/StandaloneMmCpu.inf | 9 ++--
.../StandaloneMmCpu.h | 22 +++---
StandaloneMmPkg/StandaloneMmPkg.dec | 2 +-
5 files changed, 46 insertions(+), 54 deletions(-)
rename StandaloneMmPkg/{Drivers/StandaloneMmCpu => Include}/StandaloneMmCpu.h
(82%)
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
index 818e147f874c..dc11d4375a02 100644
--- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
+++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
@@ -3,6 +3,7 @@
Copyright (c) 2016 HP Development Company, L.P.
Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.
Copyright (c) 2021, Linaro Limited
+ Copyright (c) 2023, Ventana Micro System Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -11,8 +12,6 @@
#include
#include
-#include
-#include
#include
#include
#include
@@ -22,10 +21,7 @@
#include
#include
-#include
-#include
-
-#include "StandaloneMmCpu.h"
+#include
EFI_STATUS
EFIAPI
@@ -108,7 +104,7 @@ CheckBufferAddr (
}
/**
- The PI Standalone MM entry point for the TF-A CPU driver.
+ The PI Standalone MM entry point for the CPU driver.
@param [in] EventIdThe event Id.
@param [in] CpuNumber The CPU number.
@@ -121,7 +117,7 @@ CheckBufferAddr (
@retval EFI_UNSUPPORTED Operation not supported.
**/
EFI_STATUS
-PiMmStandaloneArmTfCpuDriverEntry (
+PiMmStandaloneMmCpuDriverEntry (
IN UINTN EventId,
IN UINTN CpuNumber,
IN UINTN NsCommBufferAddr
@@ -135,17 +131,6 @@ PiMmStandaloneArmTfCpuDriverEntry (
DEBUG ((DEBUG_INFO, "Received event - 0x%x on cpu %d\n", EventId,
CpuNumber));
Status = EFI_SUCCESS;
- //
- // ARM TF passes SMC FID of the MM_COMMUNICATE interface as the Event ID upon
- // receipt of a synchronous MM request. Use the Event ID to distinguish
- // between synchronous and asynchronous events.
- //
- if ((ARM_SMC_ID_MM_COMMUNICATE != EventId) &&
- (ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ != EventId))
- {
-DEBUG ((DEBUG_ERROR, "UnRecognized Event - 0x%x\n", EventId));
-return EFI_INVALID_PARAMETER;
- }
// Perform parameter validation of NsCommBufferAddr
if (NsCommBufferAddr == (UINTN)NULL) {
@@ -177,7 +162,7 @@ PiMmStandaloneArmTfCpuDriverEntry (
}
// X1 contains the VA of the normal world memory accessible from
- // S-EL0
+ // secure world.
CopyMem (GuidedEventContext, (CONST VOID *)NsCommBufferAddr,
NsCommBufferSize);
// Stash the pointer to the allocated Event Context for this CPU
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
index 3d1dc6181bd9..c5ec1a5a80c5 100644
--- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
+++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
@@ -3,6 +3,7 @@
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
Copyright (c) 2016 HP Development Company, L.P.
Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.
+ Copyright (c) 2023, Ventana Micro System Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -10,10 +11,7 @@
#include
#include
-#include
#include
-#include
-#include
#include
#include
@@ -22,7 +20,7 @@
#include
#include
-#include "StandaloneMmCpu.h"
+#include
// GUID to identify HOB with whereabouts of communication buffer with Normal
// World
@@ -31,7 +29,7 @@ extern EFI_GUID gEfiStandaloneMmNonSecureBufferGuid;
// GUID to identify HOB where the entry point of this CPU driver will be
// populated to allow the entry point driver to invoke it upon receipt of an
// event
-extern EFI_GUID gEfiArmTfCpuDriverEpDescriptorGuid;
+extern EFI_GUID gEfiMmCpuDriverEpDescriptorGuid;
//
// Private copy of the MM system table for future use
@@ -96,17 +94,17 @@ StandaloneMmCpuInitialize (
IN EFI_MM_SYSTEM_TABLE *SystemTable // not actual systemtable
)
{
- ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *CpuDriverEntryPointDesc;
- EFI_CONFIGURATION_TABLE *ConfigurationTable;
- MP_INFORMATION_HOB_DATA *MpInformationHobData;
- EFI_MMRAM_DESCRIPTOR *NsCommBufMmramRange;
- EFI_STATUS Status;
- EFI_HANDLE DispatchHandle;
- UINT32 MpInfoSize;
- UINTNIndex;
- UINTNArraySize;
- VOID *HobStart;
- EFI_MMRAM_HOB_DESCRIPTOR_BLOC
[edk2-devel] [PATCH v3 0/2] Make StandaloneMmCpu architecture independent
This series makes StandaloneMmCpu architecture independent so other
architectures besides ARM/AARCH64 can use it without creating new driver.
There are two parts in this series:
1. Remove ARM/AARCH64 code from StandaloneMmCpu.
2. Update ARM/AARCH64 entry point library code.
V3:
- Addressed Sami's comments.
V2:
- Seperated changes between CPU driver and Arm entry point library.
Tuan Phan (2):
StandaloneMmPkg: Make StandaloneMmCpu driver architecture independent
StandaloneMmPkg: Arm: Update to use the new StandaloneMmCpu driver
.../Drivers/StandaloneMmCpu/EventHandle.c | 25 ++-
.../Drivers/StandaloneMmCpu/StandaloneMmCpu.c | 42 ++-
.../StandaloneMmCpu/StandaloneMmCpu.inf | 9 +--
.../Library/Arm/StandaloneMmCoreEntryPoint.h | 17 +
.../StandaloneMmCpu.h | 22 --
.../Arm/CreateHobList.c | 43 ++--
.../Arm/StandaloneMmCoreEntryPoint.c | 69 +++
.../StandaloneMmCoreEntryPoint.inf| 2 +-
StandaloneMmPkg/StandaloneMmPkg.dec | 2 +-
9 files changed, 113 insertions(+), 118 deletions(-)
rename StandaloneMmPkg/{Drivers/StandaloneMmCpu => Include}/StandaloneMmCpu.h
(82%)
--
2.25.1
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Re: [edk2-devel] [PATCH v2 2/2] StandaloneMmPkg: Arm: Update to use the new StandaloneMmCpu driver
Hi Sami,
Please see my comments below.
On Thu, Sep 28, 2023 at 9:16 AM Sami Mujawar wrote:
> Hi Tuan,
>
> Thank you for this patch.
>
> Please see my response inline marked [SAMI].
>
> Regards,
>
> Sami Mujawar
>
> On 15/09/2023 12:10 am, Tuan Phan wrote:
> > Update entry point library for Arm to use the new platform independent
>
> [SAMI] Should this be worded as architecture independent instead of
> platform independent?
>
> Can you also check the subject line and commit message for patch 1/2,
> please?
>
[Tuan] Sure, that makes sense.
>
> [/SAMI]
>
> > StandaloneMmCpu driver.
> >
> > Signed-off-by: Tuan Phan
> > ---
> > .../Library/Arm/StandaloneMmCoreEntryPoint.h | 17 ++--
> > .../Arm/CreateHobList.c | 43 ++-
> > .../Arm/StandaloneMmCoreEntryPoint.c | 15 ++-
> > .../StandaloneMmCoreEntryPoint.inf| 2 +-
> > 4 files changed, 40 insertions(+), 37 deletions(-)
> >
> > diff --git
> a/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
> b/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
> > index 41bf0f132b4f..dbb81610ff8e 100644
> > --- a/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
> > +++ b/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
> > @@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> > #ifndef __STANDALONEMMCORE_ENTRY_POINT_H__
> >
> > #define __STANDALONEMMCORE_ENTRY_POINT_H__
> >
> >
> >
> > +#include
> >
> > #include
> >
> > #include
> >
> >
> >
> > @@ -47,18 +48,6 @@ typedef struct {
> > EFI_SECURE_PARTITION_CPU_INFO*CpuInfo;
> >
> > } EFI_SECURE_PARTITION_BOOT_INFO;
> >
> >
> >
> > -typedef
> >
> > -EFI_STATUS
> >
> > -(*PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT) (
> >
> > - IN UINTN EventId,
> >
> > - IN UINTN CpuNumber,
> >
> > - IN UINTN NsCommBufferAddr
> >
> > - );
> >
> > -
> >
> > -typedef struct {
> >
> > - PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT*ArmTfCpuDriverEpPtr;
> >
> > -} ARM_TF_CPU_DRIVER_EP_DESCRIPTOR;
> >
> > -
> >
> > typedef RETURN_STATUS (*REGION_PERMISSION_UPDATE_FUNC) (
> >
> > IN EFI_PHYSICAL_ADDRESS BaseAddress,
> >
> > IN UINT64Length
> >
> > @@ -145,8 +134,8 @@ LocateStandaloneMmCorePeCoffData (
> > VOID *
> >
> > EFIAPI
> >
> > CreateHobListFromBootInfo (
> >
> > - IN OUT PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
> >
> > - IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo
> >
> > + IN OUT PI_MM_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
> >
> > + IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo
> >
> > );
> >
> >
> >
> > /**
> >
> > diff --git
> a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
> b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
> > index 2ac2d354f06a..80ed532352af 100644
> > ---
> a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
> > +++
> b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
> > @@ -13,6 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> > #include
> >
> > #include
> >
> >
> >
> > +#include
> >
> > #include
> >
> > #include
> >
> > #include
> >
> > @@ -39,7 +40,7 @@ extern EFI_GUID gEfiStandaloneMmNonSecureBufferGuid;
> > // GUID to identify HOB where the entry point of the CPU driver will be
> >
> > // populated to allow this entry point driver to invoke it upon
> receipt of an
> >
> > // event
> >
> > -extern EFI_GUID gEfiArmTfCpuDriverEpDescriptorGuid;
> >
> > +extern EFI_GUID gEfiMmCpuDriverEpDescriptorGuid;
> >
> >
> >
> > /**
> >
> > Use the boot information passed by privileged firmware to populate a
> HOB list
> >
> > @@ -52,22 +53,22 @@ extern EFI_GUID gEfiArmTfCpuDriverEpDescriptorGuid;
> > **/
> >
> > VOID *
> >
> > CreateHobListFromBootInfo (
> >
> > - IN OUT PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
> >
> > - IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo
> >
> > + IN OUT PI_M
Re: [edk2-devel] [PATCH v2 0/2] StandaloneMmPkg: Make StandaloneMmCpu platform
Hi Sami/Yeo
Do you have any comments on this series?
Regards,
On Thu, Sep 14, 2023 at 4:10 PM Tuan Phan wrote:
> This series makes StandaloneMmCpu platform independent so that
> other platforms besides ARM/AARCH64 can use it without creating
> new driver.
>
> There are two parts in this series:
> 1. Remove ARM/AARCH64 code from StandaloneMmCpu.
> 2. Update ARM/AARCH64 entry point library code.
>
> Tuan Phan (2):
> StandaloneMmPkg: Make StandaloneMmCpu driver platform independent
> StandaloneMmPkg: Arm: Update to use the new StandaloneMmCpu driver
>
> .../Drivers/StandaloneMmCpu/EventHandle.c | 25 +++
> .../Drivers/StandaloneMmCpu/StandaloneMmCpu.c | 42 +-
> .../StandaloneMmCpu/StandaloneMmCpu.inf | 9 ++--
> .../Library/Arm/StandaloneMmCoreEntryPoint.h | 17 ++--
> .../StandaloneMmCpu.h | 22 +++---
> .../Arm/CreateHobList.c | 43 ++-
> .../Arm/StandaloneMmCoreEntryPoint.c | 15 ++-
> .../StandaloneMmCoreEntryPoint.inf| 2 +-
> StandaloneMmPkg/StandaloneMmPkg.dec | 2 +-
> 9 files changed, 86 insertions(+), 91 deletions(-)
> rename StandaloneMmPkg/{Drivers/StandaloneMmCpu =>
> Include}/StandaloneMmCpu.h (82%)
>
> --
> 2.25.1
>
>
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[edk2-devel] [PATCH v2 0/2] StandaloneMmPkg: Make StandaloneMmCpu platform
This series makes StandaloneMmCpu platform independent so that
other platforms besides ARM/AARCH64 can use it without creating
new driver.
There are two parts in this series:
1. Remove ARM/AARCH64 code from StandaloneMmCpu.
2. Update ARM/AARCH64 entry point library code.
Tuan Phan (2):
StandaloneMmPkg: Make StandaloneMmCpu driver platform independent
StandaloneMmPkg: Arm: Update to use the new StandaloneMmCpu driver
.../Drivers/StandaloneMmCpu/EventHandle.c | 25 +++
.../Drivers/StandaloneMmCpu/StandaloneMmCpu.c | 42 +-
.../StandaloneMmCpu/StandaloneMmCpu.inf | 9 ++--
.../Library/Arm/StandaloneMmCoreEntryPoint.h | 17 ++--
.../StandaloneMmCpu.h | 22 +++---
.../Arm/CreateHobList.c | 43 ++-
.../Arm/StandaloneMmCoreEntryPoint.c | 15 ++-
.../StandaloneMmCoreEntryPoint.inf| 2 +-
StandaloneMmPkg/StandaloneMmPkg.dec | 2 +-
9 files changed, 86 insertions(+), 91 deletions(-)
rename StandaloneMmPkg/{Drivers/StandaloneMmCpu => Include}/StandaloneMmCpu.h
(82%)
--
2.25.1
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[edk2-devel] [PATCH v2 2/2] StandaloneMmPkg: Arm: Update to use the new StandaloneMmCpu driver
Update entry point library for Arm to use the new platform independent
StandaloneMmCpu driver.
Signed-off-by: Tuan Phan
---
.../Library/Arm/StandaloneMmCoreEntryPoint.h | 17 ++--
.../Arm/CreateHobList.c | 43 ++-
.../Arm/StandaloneMmCoreEntryPoint.c | 15 ++-
.../StandaloneMmCoreEntryPoint.inf| 2 +-
4 files changed, 40 insertions(+), 37 deletions(-)
diff --git a/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
b/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
index 41bf0f132b4f..dbb81610ff8e 100644
--- a/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
+++ b/StandaloneMmPkg/Include/Library/Arm/StandaloneMmCoreEntryPoint.h
@@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef __STANDALONEMMCORE_ENTRY_POINT_H__
#define __STANDALONEMMCORE_ENTRY_POINT_H__
+#include
#include
#include
@@ -47,18 +48,6 @@ typedef struct {
EFI_SECURE_PARTITION_CPU_INFO*CpuInfo;
} EFI_SECURE_PARTITION_BOOT_INFO;
-typedef
-EFI_STATUS
-(*PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT) (
- IN UINTN EventId,
- IN UINTN CpuNumber,
- IN UINTN NsCommBufferAddr
- );
-
-typedef struct {
- PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT*ArmTfCpuDriverEpPtr;
-} ARM_TF_CPU_DRIVER_EP_DESCRIPTOR;
-
typedef RETURN_STATUS (*REGION_PERMISSION_UPDATE_FUNC) (
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64Length
@@ -145,8 +134,8 @@ LocateStandaloneMmCorePeCoffData (
VOID *
EFIAPI
CreateHobListFromBootInfo (
- IN OUT PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
- IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo
+ IN OUT PI_MM_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
+ IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo
);
/**
diff --git
a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
index 2ac2d354f06a..80ed532352af 100644
--- a/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
+++ b/StandaloneMmPkg/Library/StandaloneMmCoreEntryPoint/Arm/CreateHobList.c
@@ -13,6 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include
#include
+#include
#include
#include
#include
@@ -39,7 +40,7 @@ extern EFI_GUID gEfiStandaloneMmNonSecureBufferGuid;
// GUID to identify HOB where the entry point of the CPU driver will be
// populated to allow this entry point driver to invoke it upon receipt of an
// event
-extern EFI_GUID gEfiArmTfCpuDriverEpDescriptorGuid;
+extern EFI_GUID gEfiMmCpuDriverEpDescriptorGuid;
/**
Use the boot information passed by privileged firmware to populate a HOB list
@@ -52,22 +53,22 @@ extern EFI_GUID gEfiArmTfCpuDriverEpDescriptorGuid;
**/
VOID *
CreateHobListFromBootInfo (
- IN OUT PI_MM_ARM_TF_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
- IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo
+ IN OUT PI_MM_CPU_DRIVER_ENTRYPOINT *CpuDriverEntryPoint,
+ IN EFI_SECURE_PARTITION_BOOT_INFO *PayloadBootInfo
)
{
- EFI_HOB_HANDOFF_INFO_TABLE *HobStart;
- EFI_RESOURCE_ATTRIBUTE_TYPE Attributes;
- UINT32 Index;
- UINT32 BufferSize;
- UINT32 Flags;
- EFI_MMRAM_HOB_DESCRIPTOR_BLOCK *MmramRangesHob;
- EFI_MMRAM_DESCRIPTOR *MmramRanges;
- EFI_MMRAM_DESCRIPTOR *NsCommBufMmramRange;
- MP_INFORMATION_HOB_DATA *MpInformationHobData;
- EFI_PROCESSOR_INFORMATION*ProcInfoBuffer;
- EFI_SECURE_PARTITION_CPU_INFO*CpuInfo;
- ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *CpuDriverEntryPointDesc;
+ EFI_HOB_HANDOFF_INFO_TABLE *HobStart;
+ EFI_RESOURCE_ATTRIBUTE_TYPE Attributes;
+ UINT32 Index;
+ UINT32 BufferSize;
+ UINT32 Flags;
+ EFI_MMRAM_HOB_DESCRIPTOR_BLOCK *MmramRangesHob;
+ EFI_MMRAM_DESCRIPTOR*MmramRanges;
+ EFI_MMRAM_DESCRIPTOR*NsCommBufMmramRange;
+ MP_INFORMATION_HOB_DATA *MpInformationHobData;
+ EFI_PROCESSOR_INFORMATION *ProcInfoBuffer;
+ EFI_SECURE_PARTITION_CPU_INFO *CpuInfo;
+ MM_CPU_DRIVER_EP_DESCRIPTOR *CpuDriverEntryPointDesc;
// Create a hoblist with a PHIT and EOH
HobStart = HobConstructor (
@@ -144,13 +145,13 @@ CreateHobListFromBootInfo (
// Create a Guided HOB to enable the ARM TF CPU driver to share its entry
// point and populate it with the address of the shared buffer
- CpuDriverEntryPointDesc = (ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *)BuildGuidHob (
-
,
- sizeof
(ARM_TF_CPU_DRIVER_EP_DESCRIPTOR)
- );
+ CpuDriverEntryPointDesc = (MM_CPU_DRIVER_EP_DESCRIPTOR
[edk2-devel] [PATCH v2 1/2] StandaloneMmPkg: Make StandaloneMmCpu driver platform independent
StandaloneMmCpu now can supports more platforms like RISC-V besides
ARM/AARCH64.
Signed-off-by: Tuan Phan
---
.../Drivers/StandaloneMmCpu/EventHandle.c | 25 +++
.../Drivers/StandaloneMmCpu/StandaloneMmCpu.c | 42 +--
.../StandaloneMmCpu/StandaloneMmCpu.inf | 9 ++--
.../StandaloneMmCpu.h | 22 +++---
StandaloneMmPkg/StandaloneMmPkg.dec | 2 +-
5 files changed, 46 insertions(+), 54 deletions(-)
rename StandaloneMmPkg/{Drivers/StandaloneMmCpu => Include}/StandaloneMmCpu.h
(82%)
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
index 818e147f874c..dc11d4375a02 100644
--- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
+++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
@@ -3,6 +3,7 @@
Copyright (c) 2016 HP Development Company, L.P.
Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.
Copyright (c) 2021, Linaro Limited
+ Copyright (c) 2023, Ventana Micro System Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -11,8 +12,6 @@
#include
#include
-#include
-#include
#include
#include
#include
@@ -22,10 +21,7 @@
#include
#include
-#include
-#include
-
-#include "StandaloneMmCpu.h"
+#include
EFI_STATUS
EFIAPI
@@ -108,7 +104,7 @@ CheckBufferAddr (
}
/**
- The PI Standalone MM entry point for the TF-A CPU driver.
+ The PI Standalone MM entry point for the CPU driver.
@param [in] EventIdThe event Id.
@param [in] CpuNumber The CPU number.
@@ -121,7 +117,7 @@ CheckBufferAddr (
@retval EFI_UNSUPPORTED Operation not supported.
**/
EFI_STATUS
-PiMmStandaloneArmTfCpuDriverEntry (
+PiMmStandaloneMmCpuDriverEntry (
IN UINTN EventId,
IN UINTN CpuNumber,
IN UINTN NsCommBufferAddr
@@ -135,17 +131,6 @@ PiMmStandaloneArmTfCpuDriverEntry (
DEBUG ((DEBUG_INFO, "Received event - 0x%x on cpu %d\n", EventId,
CpuNumber));
Status = EFI_SUCCESS;
- //
- // ARM TF passes SMC FID of the MM_COMMUNICATE interface as the Event ID upon
- // receipt of a synchronous MM request. Use the Event ID to distinguish
- // between synchronous and asynchronous events.
- //
- if ((ARM_SMC_ID_MM_COMMUNICATE != EventId) &&
- (ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ != EventId))
- {
-DEBUG ((DEBUG_ERROR, "UnRecognized Event - 0x%x\n", EventId));
-return EFI_INVALID_PARAMETER;
- }
// Perform parameter validation of NsCommBufferAddr
if (NsCommBufferAddr == (UINTN)NULL) {
@@ -177,7 +162,7 @@ PiMmStandaloneArmTfCpuDriverEntry (
}
// X1 contains the VA of the normal world memory accessible from
- // S-EL0
+ // secure world.
CopyMem (GuidedEventContext, (CONST VOID *)NsCommBufferAddr,
NsCommBufferSize);
// Stash the pointer to the allocated Event Context for this CPU
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
index 3d1dc6181bd9..c5ec1a5a80c5 100644
--- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
+++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
@@ -3,6 +3,7 @@
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
Copyright (c) 2016 HP Development Company, L.P.
Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.
+ Copyright (c) 2023, Ventana Micro System Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -10,10 +11,7 @@
#include
#include
-#include
#include
-#include
-#include
#include
#include
@@ -22,7 +20,7 @@
#include
#include
-#include "StandaloneMmCpu.h"
+#include
// GUID to identify HOB with whereabouts of communication buffer with Normal
// World
@@ -31,7 +29,7 @@ extern EFI_GUID gEfiStandaloneMmNonSecureBufferGuid;
// GUID to identify HOB where the entry point of this CPU driver will be
// populated to allow the entry point driver to invoke it upon receipt of an
// event
-extern EFI_GUID gEfiArmTfCpuDriverEpDescriptorGuid;
+extern EFI_GUID gEfiMmCpuDriverEpDescriptorGuid;
//
// Private copy of the MM system table for future use
@@ -96,17 +94,17 @@ StandaloneMmCpuInitialize (
IN EFI_MM_SYSTEM_TABLE *SystemTable // not actual systemtable
)
{
- ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *CpuDriverEntryPointDesc;
- EFI_CONFIGURATION_TABLE *ConfigurationTable;
- MP_INFORMATION_HOB_DATA *MpInformationHobData;
- EFI_MMRAM_DESCRIPTOR *NsCommBufMmramRange;
- EFI_STATUS Status;
- EFI_HANDLE DispatchHandle;
- UINT32 MpInfoSize;
- UINTNIndex;
- UINTNArraySize;
- VOID *HobStart;
- EFI_MMRAM_HOB_DESCRIPTOR_BLOCK *MmramRangesHob;
+ MM_CPU_DRIVER_EP_DESCRIPTOR *
Re: [edk2-devel] [PATCH] StandaloneMmPkg: Make StandaloneMmCpu driver platform independent
On Fri, Sep 8, 2023 at 12:12 AM Yeo Reum Yun wrote:
> > Signed-off-by: Tuan Phan
> > ---
> > .../Drivers/StandaloneMmCpu/EventHandle.c | 25 +++
> > .../Drivers/StandaloneMmCpu/StandaloneMmCpu.c | 42 +-
> > .../StandaloneMmCpu/StandaloneMmCpu.inf | 9 ++--
> > .../Library/Arm/StandaloneMmCoreEntryPoint.h | 17 ++--
> > .../StandaloneMmCpu.h | 22 +++---
> > .../Arm/CreateHobList.c | 43 ++-
> > .../Arm/StandaloneMmCoreEntryPoint.c | 15 ++-
> > .../StandaloneMmCoreEntryPoint.inf| 2 +-
> > StandaloneMmPkg/StandaloneMmPkg.dec | 2 +-
> > 9 files changed, 86 insertions(+), 91 deletions(-)
> > rename StandaloneMmPkg/{Drivers/StandaloneMmCpu =>
> Include}/StandaloneMmCpu.h (82%)
>
>
> @Sami, This patch looks good to me :)
> BTW, I think it's much better to split this patch to platform independent
> part and ARM specific part.
> Many thanks.
>
Sure, will seperate it to 2 parts in the next version.
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> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
> contents to any other person, use it for any purpose, or store or copy the
> information in any medium. Thank you.
>
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[edk2-devel] [PATCH] StandaloneMmPkg: Make StandaloneMmCpu driver platform independent
StandaloneMmCpu now can supports more platforms like RISC-V besides
ARM/AARCH64.
Signed-off-by: Tuan Phan
---
.../Drivers/StandaloneMmCpu/EventHandle.c | 25 +++
.../Drivers/StandaloneMmCpu/StandaloneMmCpu.c | 42 +-
.../StandaloneMmCpu/StandaloneMmCpu.inf | 9 ++--
.../Library/Arm/StandaloneMmCoreEntryPoint.h | 17 ++--
.../StandaloneMmCpu.h | 22 +++---
.../Arm/CreateHobList.c | 43 ++-
.../Arm/StandaloneMmCoreEntryPoint.c | 15 ++-
.../StandaloneMmCoreEntryPoint.inf| 2 +-
StandaloneMmPkg/StandaloneMmPkg.dec | 2 +-
9 files changed, 86 insertions(+), 91 deletions(-)
rename StandaloneMmPkg/{Drivers/StandaloneMmCpu => Include}/StandaloneMmCpu.h
(82%)
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
index 818e147f874c..dc11d4375a02 100644
--- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
+++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/EventHandle.c
@@ -3,6 +3,7 @@
Copyright (c) 2016 HP Development Company, L.P.
Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.
Copyright (c) 2021, Linaro Limited
+ Copyright (c) 2023, Ventana Micro System Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -11,8 +12,6 @@
#include
#include
-#include
-#include
#include
#include
#include
@@ -22,10 +21,7 @@
#include
#include
-#include
-#include
-
-#include "StandaloneMmCpu.h"
+#include
EFI_STATUS
EFIAPI
@@ -108,7 +104,7 @@ CheckBufferAddr (
}
/**
- The PI Standalone MM entry point for the TF-A CPU driver.
+ The PI Standalone MM entry point for the CPU driver.
@param [in] EventIdThe event Id.
@param [in] CpuNumber The CPU number.
@@ -121,7 +117,7 @@ CheckBufferAddr (
@retval EFI_UNSUPPORTED Operation not supported.
**/
EFI_STATUS
-PiMmStandaloneArmTfCpuDriverEntry (
+PiMmStandaloneMmCpuDriverEntry (
IN UINTN EventId,
IN UINTN CpuNumber,
IN UINTN NsCommBufferAddr
@@ -135,17 +131,6 @@ PiMmStandaloneArmTfCpuDriverEntry (
DEBUG ((DEBUG_INFO, "Received event - 0x%x on cpu %d\n", EventId,
CpuNumber));
Status = EFI_SUCCESS;
- //
- // ARM TF passes SMC FID of the MM_COMMUNICATE interface as the Event ID upon
- // receipt of a synchronous MM request. Use the Event ID to distinguish
- // between synchronous and asynchronous events.
- //
- if ((ARM_SMC_ID_MM_COMMUNICATE != EventId) &&
- (ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ != EventId))
- {
-DEBUG ((DEBUG_ERROR, "UnRecognized Event - 0x%x\n", EventId));
-return EFI_INVALID_PARAMETER;
- }
// Perform parameter validation of NsCommBufferAddr
if (NsCommBufferAddr == (UINTN)NULL) {
@@ -177,7 +162,7 @@ PiMmStandaloneArmTfCpuDriverEntry (
}
// X1 contains the VA of the normal world memory accessible from
- // S-EL0
+ // secure world.
CopyMem (GuidedEventContext, (CONST VOID *)NsCommBufferAddr,
NsCommBufferSize);
// Stash the pointer to the allocated Event Context for this CPU
diff --git a/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
index 3d1dc6181bd9..c5ec1a5a80c5 100644
--- a/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
+++ b/StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.c
@@ -3,6 +3,7 @@
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
Copyright (c) 2016 HP Development Company, L.P.
Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.
+ Copyright (c) 2023, Ventana Micro System Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -10,10 +11,7 @@
#include
#include
-#include
#include
-#include
-#include
#include
#include
@@ -22,7 +20,7 @@
#include
#include
-#include "StandaloneMmCpu.h"
+#include
// GUID to identify HOB with whereabouts of communication buffer with Normal
// World
@@ -31,7 +29,7 @@ extern EFI_GUID gEfiStandaloneMmNonSecureBufferGuid;
// GUID to identify HOB where the entry point of this CPU driver will be
// populated to allow the entry point driver to invoke it upon receipt of an
// event
-extern EFI_GUID gEfiArmTfCpuDriverEpDescriptorGuid;
+extern EFI_GUID gEfiMmCpuDriverEpDescriptorGuid;
//
// Private copy of the MM system table for future use
@@ -96,17 +94,17 @@ StandaloneMmCpuInitialize (
IN EFI_MM_SYSTEM_TABLE *SystemTable // not actual systemtable
)
{
- ARM_TF_CPU_DRIVER_EP_DESCRIPTOR *CpuDriverEntryPointDesc;
- EFI_CONFIGURATION_TABLE *ConfigurationTable;
- MP_INFORMATION_HOB_DATA *MpInformationHobData;
- EFI_MMRAM_DESCRIPTOR *NsCommBufMmramRange;
- EFI_STATUS Status;
- EFI_HANDLE DispatchHandle;
- UI
Re: [edk2-devel] [PATCH v4 7/7] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
On Fri, Jul 14, 2023 at 3:24 AM Sunil V L wrote:
> On Fri, Jun 23, 2023 at 11:39:34AM -0700, Tuan Phan wrote:
> > During CpuDxe initialization, MMU will be setup with the highest
> > mode that HW supports.
> >
> > Reviewed-by: Andrei Warkentin
> > Signed-off-by: Tuan Phan
> > ---
> Hi Tuan,
>
> CI tests are failing for these changes primarily due to code formatting
> errors. Can you please fix them and send the next version?
>
Hi Sunil,
I sent the next version. It passed CI at this pull request:
https://github.com/tianocore/edk2/pull/4569
>
> Thanks,
> Sunil
> > OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
> > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +-
> > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 +
> > UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf| 2 +
> > UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h | 39 ++
> > .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++
> > .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 26 +
> > .../Library/BaseRiscVMmuLib/RiscVMmuCore.S| 31 +
> > 8 files changed, 677 insertions(+), 2 deletions(-)
> > create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
> > create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > create mode 100644
> UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
> >
> > diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> > index 731f54f73f81..bc204ba5fe52 100644
> > --- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> > +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> > @@ -83,6 +83,7 @@
> ># RISC-V Architectural Libraries
> >
> CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
> >RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
> > + RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> >
> PlatformBootManagerLib|OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> >
> ResetSystemLib|OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf
> >
> > diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
> b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
> > index 25fe3f54c325..2af3b6223450 100644
> > --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
> > +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
> > @@ -296,8 +296,7 @@ CpuSetMemoryAttributes (
> >IN UINT64 Attributes
> >)
> > {
> > - DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n",
> __func__));
> > - return EFI_SUCCESS;
> > + return RiscVSetMemoryAttributes (BaseAddress, Length, Attributes);
> > }
> >
> > /**
> > @@ -340,6 +339,12 @@ InitializeCpu (
> >//
> >DisableInterrupts ();
> >
> > + //
> > + // Enable MMU
> > + //
> > + Status = RiscVConfigureMmu ();
> > + ASSERT_EFI_ERROR (Status);
> > +
> >//
> >// Install Boot protocol
> >//
> > diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
> b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
> > index 49f4e119665a..68e6d038b66e 100644
> > --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
> > +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
> > @@ -15,11 +15,13 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > #include
> > #include
> > +#include
> >
> > /**
> >Flush CPU data cache. If the instruction cache is fully coherent
> > diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> > index e8fa25446aef..6d52085df0d5 100644
> > --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> > +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> > @@ -37,6 +37,8 @@
> >TimerLib
> >PeCoffGetEntryPointLib
> >RiscVSbiLib
> > + RiscVMmuLib
> > + CacheMaintenanceLib
> >
> > [Sources]
> >CpuDxe.c
> > diff --git a/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
> b/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
> > new file mode 100644
> > index ..f71d6a4a1e7b
> > --- /dev/null
> > +++ b/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
> > @@ -0,0 +1,39 @@
> > +/** @file
> > +
> > + Copyright (c) 2015 - 2016, Linaro Ltd. All rights reserved.
> > + Copyright (c) 2023, Ventana Micro Systems Inc. All Rights
> Reserved.
> > +
[edk2-devel] [PATCH v5 7/7] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf| 2 +
UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h | 68 ++
.../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 730 ++
.../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 27 +
.../Library/BaseRiscVMmuLib/RiscVMmuCore.S| 31 +
UefiCpuPkg/UefiCpuPkg.dec | 5 +
UefiCpuPkg/UefiCpuPkg.dsc | 1 +
10 files changed, 874 insertions(+), 2 deletions(-)
create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
index 731f54f73f81..bc204ba5fe52 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
+++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
@@ -83,6 +83,7 @@
# RISC-V Architectural Libraries
CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
+ RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
PlatformBootManagerLib|OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
ResetSystemLib|OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
index 25fe3f54c325..2af3b6223450 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
@@ -296,8 +296,7 @@ CpuSetMemoryAttributes (
IN UINT64 Attributes
)
{
- DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n",
__func__));
- return EFI_SUCCESS;
+ return RiscVSetMemoryAttributes (BaseAddress, Length, Attributes);
}
/**
@@ -340,6 +339,12 @@ InitializeCpu (
//
DisableInterrupts ();
+ //
+ // Enable MMU
+ //
+ Status = RiscVConfigureMmu ();
+ ASSERT_EFI_ERROR (Status);
+
//
// Install Boot protocol
//
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
index 49f4e119665a..68e6d038b66e 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
@@ -15,11 +15,13 @@
#include
#include
#include
+#include
#include
#include
#include
#include
#include
+#include
/**
Flush CPU data cache. If the instruction cache is fully coherent
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
index e8fa25446aef..9d9a5ef8f247 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
@@ -37,6 +37,8 @@
TimerLib
PeCoffGetEntryPointLib
RiscVSbiLib
+ RiscVMmuLib
+ CacheMaintenanceLib
[Sources]
CpuDxe.c
diff --git a/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
b/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
new file mode 100644
index ..f1e609d28dc2
--- /dev/null
+++ b/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
@@ -0,0 +1,68 @@
+/** @file
+
+ Copyright (c) 2015 - 2016, Linaro Ltd. All rights reserved.
+ Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef BASE_RISCV_MMU_LIB_H_
+#define BASE_RISCV_MMU_LIB_H_
+
+/**
+ The API to flush all local TLBs.
+
+**/
+VOID
+EFIAPI
+RiscVLocalTlbFlushAll (
+ VOID
+ );
+
+/**
+ The API to flush local TLB at a virtual address.
+
+ @param VirtAddr The virtual address.
+
+**/
+VOID
+EFIAPI
+RiscVLocalTlbFlush (
+ UINTN VirtAddr
+ );
+
+/**
+ The API to set a GCD attribute on an memory region.
+
+ @param BaseAddress The base address of the region.
+ @param Length The length of the region.
+ @param Attributes The GCD attributes.
+
+ @retval EFI_INVALID_PARAMETER The BaseAddress or Length was not valid.
+ @retval EFI_OUT_OF_RESOURCESNot enough resource.
+ @retval EFI_SUCCESS The operation succesfully.
+
+**/
+EFI_STATUS
+EFIAPI
+RiscVSetMemoryAttributes (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64Length,
+ IN UINT64Attributes
+ );
+
+/**
+ The API to configure and enable RISC-V MMU with the highest mode supported.
+
+ @retval EFI_OUT_OF_RESOURCESNot enough resource.
+ @retval EFI_SUCCESS The operation succesfully.
+
+**/
+EFI_STATUS
+EFIAPI
+RiscVConfigureMmu (
+ VOID
+ );
+
+#endif /* BASE_RISCV_MMU_LIB_H_ */
diff --git a/UefiCpuPkg/Library/BaseR
[edk2-devel] [PATCH v5 6/7] OvmfPkg: RiscVVirt: Remove satp bare mode setting
There is no point to set satp to bare mode as that should be the
default mode when booting edk2.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
---
OvmfPkg/RiscVVirt/Sec/Memory.c | 18 ++
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/OvmfPkg/RiscVVirt/Sec/Memory.c b/OvmfPkg/RiscVVirt/Sec/Memory.c
index 0e2690c73687..aad71ee5dcbb 100644
--- a/OvmfPkg/RiscVVirt/Sec/Memory.c
+++ b/OvmfPkg/RiscVVirt/Sec/Memory.c
@@ -85,21 +85,6 @@ AddMemoryRangeHob (
AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
}
-/**
- Configure MMU
-**/
-STATIC
-VOID
-InitMmu (
- )
-{
- //
- // Set supervisor translation mode to Bare mode
- //
- RiscVSetSupervisorAddressTranslationRegister ((UINT64)SATP_MODE_OFF << 60);
- DEBUG ((DEBUG_INFO, "%a: Set Supervisor address mode to bare-metal mode.\n",
__func__));
-}
-
/**
Publish system RAM and reserve memory regions.
@@ -327,7 +312,8 @@ MemoryPeimInitialization (
AddReservedMemoryMap (FdtPointer);
- InitMmu ();
+ /* Make sure SEC is booting with bare mode */
+ ASSERT ((RiscVGetSupervisorAddressTranslationRegister () & SATP64_MODE) ==
(SATP_MODE_OFF << SATP64_MODE_SHIFT));
BuildMemoryTypeInformationHob ();
--
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[edk2-devel] [PATCH v5 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list
Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it
is the backend flash driver.
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 ++
1 file changed, 10 insertions(+)
diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
index 21e4ba67379f..9ab8eb3ba7d8 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
+++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
@@ -53,6 +53,16 @@ READ_STATUS= TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
+APRIORI DXE {
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ INF
MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+ INF
MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+ INF EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf
+ INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
+ INF OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf
+}
+
#
# DXE Phase modules
#
--
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[edk2-devel] [PATCH v5 4/7] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices
Normally, DXE driver would add device resource to GCD before start using.
But some key resources such as uart used for printing info at very early
stage.
Those resources should be populated to HOB in SEC phase so they are
added to GCD before MMU enabled.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
OvmfPkg/RiscVVirt/Sec/Platform.c | 62
1 file changed, 62 insertions(+)
diff --git a/OvmfPkg/RiscVVirt/Sec/Platform.c b/OvmfPkg/RiscVVirt/Sec/Platform.c
index 3645c27b0b12..c66432473067 100644
--- a/OvmfPkg/RiscVVirt/Sec/Platform.c
+++ b/OvmfPkg/RiscVVirt/Sec/Platform.c
@@ -21,6 +21,64 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include
#include
+/**
+ Build memory map I/O range resource HOB using the
+ base address and size.
+
+ @param MemoryBase Memory map I/O base.
+ @param MemorySize Memory map I/O size.
+
+**/
+STATIC
+VOID
+AddIoMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64MemorySize
+ )
+{
+ /* Align to EFI_PAGE_SIZE */
+ MemorySize = ALIGN_VALUE (MemorySize, EFI_PAGE_SIZE);
+ BuildResourceDescriptorHob (
+EFI_RESOURCE_MEMORY_MAPPED_IO,
+EFI_RESOURCE_ATTRIBUTE_PRESENT |
+EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+EFI_RESOURCE_ATTRIBUTE_TESTED,
+MemoryBase,
+MemorySize
+);
+}
+
+/**
+ Populate IO resources from FDT that not added to GCD by its
+ driver in the DXE phase.
+
+ @param FdtBase Fdt base address
+ @param CompatibleCompatible string
+
+**/
+STATIC
+VOID
+PopulateIoResources (
+ VOID *FdtBase,
+ CONST CHAR8 *Compatible
+ )
+{
+ UINT64 *Reg;
+ INT32 Node, LenP;
+
+ Node = fdt_node_offset_by_compatible (FdtBase, -1, Compatible);
+ while (Node != -FDT_ERR_NOTFOUND) {
+Reg = (UINT64 *)fdt_getprop (FdtBase, Node, "reg", );
+if (Reg) {
+ ASSERT (LenP == (2 * sizeof (UINT64)));
+ AddIoMemoryBaseSizeHob (SwapBytes64 (Reg[0]), SwapBytes64 (Reg[1]));
+}
+
+Node = fdt_node_offset_by_compatible (FdtBase, Node, Compatible);
+ }
+}
+
/**
@retval EFI_SUCCESSThe address of FDT is passed in HOB.
EFI_UNSUPPORTEDCan't locate FDT.
@@ -80,5 +138,9 @@ PlatformPeimInitialization (
BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32 (PcdOvmfDxeMemFvSize));
+ PopulateIoResources (Base, "ns16550a");
+ PopulateIoResources (Base, "qemu,fw-cfg-mmio");
+ PopulateIoResources (Base, "virtio,mmio");
+
return EFI_SUCCESS;
}
--
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[edk2-devel] [PATCH v5 3/7] OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size
The size should be for single region, not the whole firmware FD.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
---
.../Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c| 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
index fdc2ccb6294e..33f3a01b06f4 100644
--- a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
+++ b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
@@ -24,7 +24,8 @@ VIRT_NOR_FLASH_DESCRIPTION mNorFlashDevice =
{
FixedPcdGet32 (PcdOvmfFdBaseAddress),
FixedPcdGet64 (PcdFlashNvStorageVariableBase),
- FixedPcdGet32 (PcdOvmfFirmwareFdSize),
+ FixedPcdGet32 (PcdOvmfFirmwareFdSize) -
+ (FixedPcdGet64 (PcdFlashNvStorageVariableBase) - FixedPcdGet32
(PcdOvmfFdBaseAddress)),
QEMU_NOR_BLOCK_SIZE
};
--
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[edk2-devel] [PATCH v5 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition
The satp mode bits shift is used cross modules. It should be defined in one place. Signed-off-by: Tuan Phan Reviewed-by: Andrei Warkentin Reviewed-by: Sunil V L Reviewed-by: Michael D Kinney --- MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h index 5c2989b797bf..2bde8db478ff 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -58,9 +58,10 @@ #define PRV_S 1UL #define PRV_M 3UL -#define SATP64_MODE 0xF000ULL -#define SATP64_ASID 0x0000ULL -#define SATP64_PPN 0x0FFFULL +#define SATP64_MODE0xF000ULL +#define SATP64_MODE_SHIFT 60 +#define SATP64_ASID0x0000ULL +#define SATP64_PPN 0x0FFFULL #define SATP_MODE_OFF 0UL #define SATP_MODE_SV32 1UL -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#106939): https://edk2.groups.io/g/devel/message/106939 Mute This Topic: https://groups.io/mt/100147808/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v5 1/7] MdePkg/BaseLib: RISC-V: Support getting satp register value
Add an API to retrieve satp register value. Signed-off-by: Tuan Phan Reviewed-by: Andrei Warkentin Reviewed-by: Sunil V L --- MdePkg/Include/Library/BaseLib.h | 5 + MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 2 files changed, 13 insertions(+) diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 8f2df76c29a3..5d7067ee854e 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -181,6 +181,11 @@ RiscVSetSupervisorAddressTranslationRegister ( IN UINT64 ); +UINT64 +RiscVGetSupervisorAddressTranslationRegister ( + VOID + ); + UINT64 RiscVReadTimer ( VOID diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S index ac8f92f38aed..c9cf60c1664b 100644 --- a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S @@ -21,3 +21,11 @@ ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister) csrw CSR_SATP, a0 ret + +// +// Get the value of Supervisor Address Translation and +// Protection Register. +// +ASM_FUNC (RiscVGetSupervisorAddressTranslationRegister) +csrr a0, CSR_SATP +ret -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#106938): https://edk2.groups.io/g/devel/message/106938 Mute This Topic: https://groups.io/mt/100147807/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v5 0/7] Add RISC-V MMU support
This series adds MMU support for RISC-V. Only SV39/48/57 modes are supported and tested. The MMU is required to support setting page attribute which is the first basic step to support security booting on RISC-V. There are two parts: 1. Add MMU base library. MMU will be enabled during CpuDxe initialization. 2. Fix all resources should be populated in HOB or added to GCD by driver before accessing when MMU enabled. All changes can be found in the branch tphan/riscv_mmu at: https://github.com/pttuan/edk2.git Changes in V5: - Rebased master. - Fix CI issue. Changes in v4: - Rebased master. - Added VirtNorFlashDxe to APRIORI DXE list. Changes in v3: - Move MMU library to UefiCpuPkg. - Add Andrei reviewed-by. Changes in v2: - Move MMU core to a library. - Setup SATP mode as highest possible that HW supports. Tuan Phan (7): MdePkg/BaseLib: RISC-V: Support getting satp register value MdePkg/Register: RISC-V: Add satp mode bits shift definition OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list OvmfPkg: RiscVVirt: Remove satp bare mode setting UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode MdePkg/Include/Library/BaseLib.h | 5 + .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + .../VirtNorFlashStaticLib.c | 3 +- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 + OvmfPkg/RiscVVirt/Sec/Memory.c| 18 +- OvmfPkg/RiscVVirt/Sec/Platform.c | 62 ++ UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf| 2 + UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h | 68 ++ .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 730 ++ .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 27 + .../Library/BaseRiscVMmuLib/RiscVMmuCore.S| 31 + UefiCpuPkg/UefiCpuPkg.dec | 5 + UefiCpuPkg/UefiCpuPkg.dsc | 1 + 17 files changed, 967 insertions(+), 22 deletions(-) create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#106937): https://edk2.groups.io/g/devel/message/106937 Mute This Topic: https://groups.io/mt/100147803/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v4 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list
On Tue, Jul 4, 2023 at 12:01 AM Sunil V L wrote:
> On Mon, Jul 03, 2023 at 11:45:45PM -0700, Tuan Phan wrote:
> > As i said, VirtNorFlashDxe needed to be loaded before VariableRuntimeDxe
> so
> > your suggestion will not work.
> >
> Okay, at least for me, by removing APRIORI patch and adding this depex,
> edk2 boots fine with your series. I am not sure what won't work.
>
> Hi Ard, any thoughts? If no better way, may be we have to use APRIORI.
>
It doesn't work as your workaround trying to make CpuDxe depends on
variable protocol which has nothing to do with it. Also, CpuDxe is an
essential module and should not depend on anything, what happens if the
variable driver before generating the protocol tries to use CPU protocol?
It is worse than having APRIORI workaround.
>
> Thanks,
> Sunil
> > On Mon, Jul 3, 2023 at 10:07 PM Sunil V L
> wrote:
> >
> > > On Wed, Jun 28, 2023 at 02:27:10PM -0700, Tuan Phan wrote:
> > > > On Wed, Jun 28, 2023 at 9:47 AM Sunil V L
> > > wrote:
> > > >
> > > > > On Fri, Jun 23, 2023 at 11:39:32AM -0700, Tuan Phan wrote:
> > > > > > Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it
> > > > > > is the backend flash driver.
> > > > > >
> > > > > > Signed-off-by: Tuan Phan
> > > > > > ---
> > > > > > OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 ++
> > > > > > 1 file changed, 10 insertions(+)
> > > > > >
> > > > > > diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > > > b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > > > > index 21e4ba67379f..9ab8eb3ba7d8 100644
> > > > > > --- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > > > > +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > > > > @@ -53,6 +53,16 @@ READ_STATUS= TRUE
> > > > > > READ_LOCK_CAP = TRUE
> > > > > > READ_LOCK_STATUS = TRUE
> > > > > >
> > > > > > +APRIORI DXE {
> > > > > > + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> > > > > > + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> > > > > > + INF
> > > > >
> > >
> MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
> > > > > > + INF
> > > > >
> > >
> MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
> > > > > > + INF EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf
> > > > > > + INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> > > > > > + INF OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf
> > > > > > +}
> > > > > > +
> > > > > Hi Tuan,
> > > > >
> > > > > Actually, Ard had recommended not to use APRIORI and hence we
> avoided
> > > > > it when we upstreamed RiscVVirt. So, I am wondering whether this
> can be
> > > > > avoided by using depex in CpuDxe on gEfiVariableArchProtocolGuid?
> > > > >
> > > > > Hi Sunil,
> > > > Not sure what the reason behind avoiding APRIORI besides it is a
> > > workaround
> > > > for broken DEPEX. BTW, what we need is to put VirtNorFlashDxe loaded
> > > before
> > > > VariableRuntimeDxe which doesn't depend on any modules. I don't see
> any
> > > > other clearer way than modifying VirNorFlashDxe as shown in the first
> > > > version of this series.
> > > >
> > > > The CpuDxeRiscV64 in the aprioriy list as VirNorFlashDxe depends on
> it.
> > > >
> > > Hi Tuan,
> > >
> > > I couldn't locate old mail from Ard recommending to remove APRIORI in
> > > RISC-V. But here is the recent mail on different context but those
> > > reasons are still valid in any case.
> > > https://edk2.groups.io/g/devel/message/104543
> > >
> > > IMO, there is no dependency between VirtNorFlashDxe and
> > > VariableRuntimeDxe. I think what we need is CpuDxeRiscV64 loaded after
> > > VariableRuntimeDxe and before VirtNorFlashDxe. A simple depex like I
> > > suggested in previous mail should work. I still prefer this than
> > > introducing APRIORI unless there are other issues I am now aware of.
> > > What do you think?
> > >
> > > Thanks!
> > > Sunil
> > >
>
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Re: [edk2-devel] [PATCH v4 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list
As i said, VirtNorFlashDxe needed to be loaded before VariableRuntimeDxe so
your suggestion will not work.
On Mon, Jul 3, 2023 at 10:07 PM Sunil V L wrote:
> On Wed, Jun 28, 2023 at 02:27:10PM -0700, Tuan Phan wrote:
> > On Wed, Jun 28, 2023 at 9:47 AM Sunil V L
> wrote:
> >
> > > On Fri, Jun 23, 2023 at 11:39:32AM -0700, Tuan Phan wrote:
> > > > Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it
> > > > is the backend flash driver.
> > > >
> > > > Signed-off-by: Tuan Phan
> > > > ---
> > > > OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 ++
> > > > 1 file changed, 10 insertions(+)
> > > >
> > > > diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > > index 21e4ba67379f..9ab8eb3ba7d8 100644
> > > > --- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > > +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > > > @@ -53,6 +53,16 @@ READ_STATUS= TRUE
> > > > READ_LOCK_CAP = TRUE
> > > > READ_LOCK_STATUS = TRUE
> > > >
> > > > +APRIORI DXE {
> > > > + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> > > > + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> > > > + INF
> > >
> MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
> > > > + INF
> > >
> MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
> > > > + INF EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf
> > > > + INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> > > > + INF OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf
> > > > +}
> > > > +
> > > Hi Tuan,
> > >
> > > Actually, Ard had recommended not to use APRIORI and hence we avoided
> > > it when we upstreamed RiscVVirt. So, I am wondering whether this can be
> > > avoided by using depex in CpuDxe on gEfiVariableArchProtocolGuid?
> > >
> > > Hi Sunil,
> > Not sure what the reason behind avoiding APRIORI besides it is a
> workaround
> > for broken DEPEX. BTW, what we need is to put VirtNorFlashDxe loaded
> before
> > VariableRuntimeDxe which doesn't depend on any modules. I don't see any
> > other clearer way than modifying VirNorFlashDxe as shown in the first
> > version of this series.
> >
> > The CpuDxeRiscV64 in the aprioriy list as VirNorFlashDxe depends on it.
> >
> Hi Tuan,
>
> I couldn't locate old mail from Ard recommending to remove APRIORI in
> RISC-V. But here is the recent mail on different context but those
> reasons are still valid in any case.
> https://edk2.groups.io/g/devel/message/104543
>
> IMO, there is no dependency between VirtNorFlashDxe and
> VariableRuntimeDxe. I think what we need is CpuDxeRiscV64 loaded after
> VariableRuntimeDxe and before VirtNorFlashDxe. A simple depex like I
> suggested in previous mail should work. I still prefer this than
> introducing APRIORI unless there are other issues I am now aware of.
> What do you think?
>
> Thanks!
> Sunil
>
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Re: [edk2-devel] [PATCH v4 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list
On Wed, Jun 28, 2023 at 9:47 AM Sunil V L wrote:
> On Fri, Jun 23, 2023 at 11:39:32AM -0700, Tuan Phan wrote:
> > Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it
> > is the backend flash driver.
> >
> > Signed-off-by: Tuan Phan
> > ---
> > OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 ++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > index 21e4ba67379f..9ab8eb3ba7d8 100644
> > --- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
> > @@ -53,6 +53,16 @@ READ_STATUS= TRUE
> > READ_LOCK_CAP = TRUE
> > READ_LOCK_STATUS = TRUE
> >
> > +APRIORI DXE {
> > + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> > + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> > + INF
> MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
> > + INF
> MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
> > + INF EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf
> > + INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> > + INF OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf
> > +}
> > +
> Hi Tuan,
>
> Actually, Ard had recommended not to use APRIORI and hence we avoided
> it when we upstreamed RiscVVirt. So, I am wondering whether this can be
> avoided by using depex in CpuDxe on gEfiVariableArchProtocolGuid?
>
> Hi Sunil,
Not sure what the reason behind avoiding APRIORI besides it is a workaround
for broken DEPEX. BTW, what we need is to put VirtNorFlashDxe loaded before
VariableRuntimeDxe which doesn't depend on any modules. I don't see any
other clearer way than modifying VirNorFlashDxe as shown in the first
version of this series.
The CpuDxeRiscV64 in the aprioriy list as VirNorFlashDxe depends on it.
Thanks,
> Sunil
>
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Re: [edk2-devel] [PATCH] UefiCpuPkg: CpuTimerDxeRiscV64: Fix timer event not working correctly
Thanks Sunil, Updated pull request: https://github.com/tianocore/edk2/pull/4585 Please help merge it if no objection. Thanks, From: Sunil V L Date: Wednesday, June 28, 2023 at 7:43 AM To: Tuan Phan Cc: devel@edk2.groups.io , andrei.warken...@intel.com Subject: Re: [PATCH] UefiCpuPkg: CpuTimerDxeRiscV64: Fix timer event not working correctly On Tue, Jun 27, 2023 at 06:15:57PM -0700, Tuan Phan wrote: > The timer notify function should be called with timer period, not the > value read from timer register. > > Signed-off-by: Tuan Phan > --- LGTM. Reviewed-by: Sunil V L Thanks! Sunil -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#106486): https://edk2.groups.io/g/devel/message/106486 Mute This Topic: https://groups.io/mt/99822131/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH] UefiCpuPkg: CpuTimerDxeRiscV64: Fix timer event not working correctly
The timer notify function should be called with timer period, not the
value read from timer register.
Signed-off-by: Tuan Phan
---
UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
index 358057e7c6a4..30e48061cd06 100644
--- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
+++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
@@ -9,6 +9,7 @@
#include
#include
+#include
#include "Timer.h"
//
@@ -71,7 +72,12 @@ TimerInterruptHandler (
// time to increment slower. So when we take an interrupt,
// account for the actual time passed.
//
-mTimerNotifyFunction (PeriodStart - mLastPeriodStart);
+mTimerNotifyFunction (
+ DivU64x32 (
+EFI_TIMER_PERIOD_SECONDS (PeriodStart - mLastPeriodStart),
+PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+)
+ );
}
if (mTimerPeriod == 0) {
--
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[edk2-devel] [PATCH v4 7/7] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.
Reviewed-by: Andrei Warkentin
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf| 2 +
UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h | 39 ++
.../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++
.../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 26 +
.../Library/BaseRiscVMmuLib/RiscVMmuCore.S| 31 +
8 files changed, 677 insertions(+), 2 deletions(-)
create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
index 731f54f73f81..bc204ba5fe52 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
+++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
@@ -83,6 +83,7 @@
# RISC-V Architectural Libraries
CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
+ RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
PlatformBootManagerLib|OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
ResetSystemLib|OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
index 25fe3f54c325..2af3b6223450 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
@@ -296,8 +296,7 @@ CpuSetMemoryAttributes (
IN UINT64 Attributes
)
{
- DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n",
__func__));
- return EFI_SUCCESS;
+ return RiscVSetMemoryAttributes (BaseAddress, Length, Attributes);
}
/**
@@ -340,6 +339,12 @@ InitializeCpu (
//
DisableInterrupts ();
+ //
+ // Enable MMU
+ //
+ Status = RiscVConfigureMmu ();
+ ASSERT_EFI_ERROR (Status);
+
//
// Install Boot protocol
//
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
index 49f4e119665a..68e6d038b66e 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
@@ -15,11 +15,13 @@
#include
#include
#include
+#include
#include
#include
#include
#include
#include
+#include
/**
Flush CPU data cache. If the instruction cache is fully coherent
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
index e8fa25446aef..6d52085df0d5 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
@@ -37,6 +37,8 @@
TimerLib
PeCoffGetEntryPointLib
RiscVSbiLib
+ RiscVMmuLib
+ CacheMaintenanceLib
[Sources]
CpuDxe.c
diff --git a/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
b/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
new file mode 100644
index ..f71d6a4a1e7b
--- /dev/null
+++ b/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
@@ -0,0 +1,39 @@
+/** @file
+
+ Copyright (c) 2015 - 2016, Linaro Ltd. All rights reserved.
+ Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef BASE_RISCV_MMU_LIB_H_
+#define BASE_RISCV_MMU_LIB_H_
+
+VOID
+EFIAPI
+RiscVLocalTlbFlushAll (
+ VOID
+ );
+
+VOID
+EFIAPI
+RiscVLocalTlbFlush (
+ UINTN VirtAddr
+ );
+
+EFI_STATUS
+EFIAPI
+RiscVSetMemoryAttributes (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64Length,
+ IN UINT64Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+RiscVConfigureMmu (
+ VOID
+ );
+
+#endif /* BASE_RISCV_MMU_LIB_H_ */
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
new file mode 100644
index ..e6841b793bfc
--- /dev/null
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
@@ -0,0 +1,569 @@
+/** @file
+* MMU implementation for RISC-V
+*
+* Copyright (c) 2011-2020, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+* Copyright (c) 2017, Intel Corporation. All rights reserved.
+* Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define RISCV_PG_V BIT0
+#define RISCV_PG_R BIT1
+#define RISCV_PG_W BIT2
+#define RISCV_PG_X BIT3
+#define RISCV_PG_G BIT5
+#define
[edk2-devel] [PATCH v4 6/7] OvmfPkg: RiscVVirt: Remove satp bare mode setting
There is no point to set satp to bare mode as that should be the
default mode when booting edk2.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
---
OvmfPkg/RiscVVirt/Sec/Memory.c | 18 ++
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/OvmfPkg/RiscVVirt/Sec/Memory.c b/OvmfPkg/RiscVVirt/Sec/Memory.c
index 0e2690c73687..aad71ee5dcbb 100644
--- a/OvmfPkg/RiscVVirt/Sec/Memory.c
+++ b/OvmfPkg/RiscVVirt/Sec/Memory.c
@@ -85,21 +85,6 @@ AddMemoryRangeHob (
AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
}
-/**
- Configure MMU
-**/
-STATIC
-VOID
-InitMmu (
- )
-{
- //
- // Set supervisor translation mode to Bare mode
- //
- RiscVSetSupervisorAddressTranslationRegister ((UINT64)SATP_MODE_OFF << 60);
- DEBUG ((DEBUG_INFO, "%a: Set Supervisor address mode to bare-metal mode.\n",
__func__));
-}
-
/**
Publish system RAM and reserve memory regions.
@@ -327,7 +312,8 @@ MemoryPeimInitialization (
AddReservedMemoryMap (FdtPointer);
- InitMmu ();
+ /* Make sure SEC is booting with bare mode */
+ ASSERT ((RiscVGetSupervisorAddressTranslationRegister () & SATP64_MODE) ==
(SATP_MODE_OFF << SATP64_MODE_SHIFT));
BuildMemoryTypeInformationHob ();
--
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[edk2-devel] [PATCH v4 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list
Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it
is the backend flash driver.
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 ++
1 file changed, 10 insertions(+)
diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
index 21e4ba67379f..9ab8eb3ba7d8 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
+++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
@@ -53,6 +53,16 @@ READ_STATUS= TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
+APRIORI DXE {
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ INF
MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+ INF
MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+ INF EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf
+ INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
+ INF OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf
+}
+
#
# DXE Phase modules
#
--
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[edk2-devel] [PATCH v4 4/7] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices
Normally, DXE driver would add device resource to GCD before start using.
But some key resources such as uart used for printing info at very early
stage.
Those resources should be populated to HOB in SEC phase so they are
added to GCD before MMU enabled.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
OvmfPkg/RiscVVirt/Sec/Platform.c | 62
1 file changed, 62 insertions(+)
diff --git a/OvmfPkg/RiscVVirt/Sec/Platform.c b/OvmfPkg/RiscVVirt/Sec/Platform.c
index 3645c27b0b12..c66432473067 100644
--- a/OvmfPkg/RiscVVirt/Sec/Platform.c
+++ b/OvmfPkg/RiscVVirt/Sec/Platform.c
@@ -21,6 +21,64 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include
#include
+/**
+ Build memory map I/O range resource HOB using the
+ base address and size.
+
+ @param MemoryBase Memory map I/O base.
+ @param MemorySize Memory map I/O size.
+
+**/
+STATIC
+VOID
+AddIoMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64MemorySize
+ )
+{
+ /* Align to EFI_PAGE_SIZE */
+ MemorySize = ALIGN_VALUE (MemorySize, EFI_PAGE_SIZE);
+ BuildResourceDescriptorHob (
+EFI_RESOURCE_MEMORY_MAPPED_IO,
+EFI_RESOURCE_ATTRIBUTE_PRESENT |
+EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+EFI_RESOURCE_ATTRIBUTE_TESTED,
+MemoryBase,
+MemorySize
+);
+}
+
+/**
+ Populate IO resources from FDT that not added to GCD by its
+ driver in the DXE phase.
+
+ @param FdtBase Fdt base address
+ @param CompatibleCompatible string
+
+**/
+STATIC
+VOID
+PopulateIoResources (
+ VOID *FdtBase,
+ CONST CHAR8 *Compatible
+ )
+{
+ UINT64 *Reg;
+ INT32 Node, LenP;
+
+ Node = fdt_node_offset_by_compatible (FdtBase, -1, Compatible);
+ while (Node != -FDT_ERR_NOTFOUND) {
+Reg = (UINT64 *)fdt_getprop (FdtBase, Node, "reg", );
+if (Reg) {
+ ASSERT (LenP == (2 * sizeof (UINT64)));
+ AddIoMemoryBaseSizeHob (SwapBytes64 (Reg[0]), SwapBytes64 (Reg[1]));
+}
+
+Node = fdt_node_offset_by_compatible (FdtBase, Node, Compatible);
+ }
+}
+
/**
@retval EFI_SUCCESSThe address of FDT is passed in HOB.
EFI_UNSUPPORTEDCan't locate FDT.
@@ -80,5 +138,9 @@ PlatformPeimInitialization (
BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32 (PcdOvmfDxeMemFvSize));
+ PopulateIoResources (Base, "ns16550a");
+ PopulateIoResources (Base, "qemu,fw-cfg-mmio");
+ PopulateIoResources (Base, "virtio,mmio");
+
return EFI_SUCCESS;
}
--
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[edk2-devel] [PATCH v4 3/7] OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size
The size should be for single region, not the whole firmware FD.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
---
.../Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c| 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
index fdc2ccb6294e..33f3a01b06f4 100644
--- a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
+++ b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
@@ -24,7 +24,8 @@ VIRT_NOR_FLASH_DESCRIPTION mNorFlashDevice =
{
FixedPcdGet32 (PcdOvmfFdBaseAddress),
FixedPcdGet64 (PcdFlashNvStorageVariableBase),
- FixedPcdGet32 (PcdOvmfFirmwareFdSize),
+ FixedPcdGet32 (PcdOvmfFirmwareFdSize) -
+ (FixedPcdGet64 (PcdFlashNvStorageVariableBase) - FixedPcdGet32
(PcdOvmfFdBaseAddress)),
QEMU_NOR_BLOCK_SIZE
};
--
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[edk2-devel] [PATCH v4 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition
The satp mode bits shift is used cross modules. It should be defined in one place. Signed-off-by: Tuan Phan Reviewed-by: Andrei Warkentin Reviewed-by: Sunil V L --- MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h index 5c2989b797bf..2bde8db478ff 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -58,9 +58,10 @@ #define PRV_S 1UL #define PRV_M 3UL -#define SATP64_MODE 0xF000ULL -#define SATP64_ASID 0x0000ULL -#define SATP64_PPN 0x0FFFULL +#define SATP64_MODE0xF000ULL +#define SATP64_MODE_SHIFT 60 +#define SATP64_ASID0x0000ULL +#define SATP64_PPN 0x0FFFULL #define SATP_MODE_OFF 0UL #define SATP_MODE_SV32 1UL -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#106304): https://edk2.groups.io/g/devel/message/106304 Mute This Topic: https://groups.io/mt/99724471/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v4 0/7] RISC-V: Add MMU support
This series adds MMU support for RISC-V. Only SV39/48/57 modes are supported and tested. The MMU is required to support setting page attribute which is the first basic step to support security booting on RISC-V. There are two parts: 1. Add MMU base library. MMU will be enabled during CpuDxe initialization. 2. Fix all resources should be populated in HOB or added to GCD by driver before accessing when MMU enabled. All changes can be found in the branch tphan/riscv_mmu at: https://github.com/pttuan/edk2.git Changes in v4: - Rebased master. - Added VirtNorFlashDxe to APRIORI DXE list. Changes in v3: - Move MMU library to UefiCpuPkg. - Add Andrei reviewed-by. Changes in v2: - Move MMU core to a library. - Setup SATP mode as highest possible that HW supports. Tuan Phan (7): MdePkg/BaseLib: RISC-V: Support getting satp register value MdePkg/Register: RISC-V: Add satp mode bits shift definition OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list OvmfPkg: RiscVVirt: Remove satp bare mode setting UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode MdePkg/Include/Library/BaseLib.h | 5 + .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + .../VirtNorFlashStaticLib.c | 3 +- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 + OvmfPkg/RiscVVirt/Sec/Memory.c| 18 +- OvmfPkg/RiscVVirt/Sec/Platform.c | 62 ++ UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf| 2 + UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h | 39 ++ .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++ .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 26 + .../Library/BaseRiscVMmuLib/RiscVMmuCore.S| 31 + 15 files changed, 770 insertions(+), 22 deletions(-) create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#106302): https://edk2.groups.io/g/devel/message/106302 Mute This Topic: https://groups.io/mt/99724468/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v4 1/7] MdePkg/BaseLib: RISC-V: Support getting satp register value
Add an API to retrieve satp register value. Signed-off-by: Tuan Phan Reviewed-by: Andrei Warkentin Reviewed-by: Sunil V L --- MdePkg/Include/Library/BaseLib.h | 5 + MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 2 files changed, 13 insertions(+) diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 8f2df76c29a3..5d7067ee854e 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -181,6 +181,11 @@ RiscVSetSupervisorAddressTranslationRegister ( IN UINT64 ); +UINT64 +RiscVGetSupervisorAddressTranslationRegister ( + VOID + ); + UINT64 RiscVReadTimer ( VOID diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S index ac8f92f38aed..c9cf60c1664b 100644 --- a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S @@ -21,3 +21,11 @@ ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister) csrw CSR_SATP, a0 ret + +// +// Get the value of Supervisor Address Translation and +// Protection Register. +// +ASM_FUNC (RiscVGetSupervisorAddressTranslationRegister) +csrr a0, CSR_SATP +ret -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#106303): https://edk2.groups.io/g/devel/message/106303 Mute This Topic: https://groups.io/mt/99724469/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v3 7/7] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices
On Thu, Jun 22, 2023 at 11:41 AM Tuan Phan wrote:
>
>
> On Tue, May 30, 2023 at 10:38 AM Tuan Phan via groups.io ventanamicro@groups.io> wrote:
>
>>
>>
>> On Mon, May 29, 2023 at 7:07 AM Ard Biesheuvel wrote:
>>
>>> On Sat, 27 May 2023 at 01:18, Tuan Phan wrote:
>>> >
>>> > Normally, DXE driver would add device resource to GCD before start
>>> using.
>>> > But some key resources such as uart, flash base address are being
>>> accessing
>>> > directly in some core modules.
>>> >
>>> > Those resources should be populated to HOB in SEC phase so they are
>>> > added to GCD before anyone can access them.
>>> >
>>>
>>> Why should these be in the GCD to begin with?
>>>
>>
>> These resources should be in memory space so their addresses and size are
>> registered with MMU. If not when MMU enabled, illegal access exception when
>> someone access them.
>>
>> Hi Ard,
> Do you still have concerns about this patch?
>
BTW, I will drop this patch and put VirtNorFlashDxe in APRIORI DXE list to
make sure it runs before VariableRuntimeDxe.
>
>>> > Signed-off-by: Tuan Phan
>>> > Reviewed-by: Andrei Warkentin
>>>
>>> > ---
>>> > OvmfPkg/RiscVVirt/Sec/Platform.c | 62 +++
>>> > OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 +
>>> > 2 files changed, 63 insertions(+)
>>> >
>>> > diff --git a/OvmfPkg/RiscVVirt/Sec/Platform.c
>>> b/OvmfPkg/RiscVVirt/Sec/Platform.c
>>> > index 3645c27b0b12..944b82c84a6e 100644
>>> > --- a/OvmfPkg/RiscVVirt/Sec/Platform.c
>>> > +++ b/OvmfPkg/RiscVVirt/Sec/Platform.c
>>> > @@ -21,6 +21,63 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
>>> > #include
>>> > #include
>>> >
>>> > +/**
>>> > + Build memory map I/O range resource HOB using the
>>> > + base address and size.
>>> > +
>>> > + @param MemoryBase Memory map I/O base.
>>> > + @param MemorySize Memory map I/O size.
>>> > +
>>> > +**/
>>> > +STATIC
>>> > +VOID
>>> > +AddIoMemoryBaseSizeHob (
>>> > + EFI_PHYSICAL_ADDRESS MemoryBase,
>>> > + UINT64MemorySize
>>> > + )
>>> > +{
>>> > + /* Align to EFI_PAGE_SIZE */
>>> > + MemorySize = ALIGN_VALUE (MemorySize, EFI_PAGE_SIZE);
>>> > + BuildResourceDescriptorHob (
>>> > +EFI_RESOURCE_MEMORY_MAPPED_IO,
>>> > +EFI_RESOURCE_ATTRIBUTE_PRESENT |
>>> > +EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
>>> > +EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
>>> > +EFI_RESOURCE_ATTRIBUTE_TESTED,
>>> > +MemoryBase,
>>> > +MemorySize
>>> > +);
>>> > +}
>>> > +
>>> > +/**
>>> > + Populate IO resources from FDT that not added to GCD by its
>>> > + driver in the DXE phase.
>>> > +
>>> > + @param FdtBase Fdt base address
>>> > + @param CompatibleCompatible string
>>> > +
>>> > +**/
>>> > +STATIC
>>> > +VOID
>>> > +PopulateIoResources (
>>> > + VOID *FdtBase,
>>> > + CONST CHAR8* Compatible
>>> > + )
>>> > +{
>>> > + UINT64 *Reg;
>>> > + INT32 Node, LenP;
>>> > +
>>> > + Node = fdt_node_offset_by_compatible (FdtBase, -1, Compatible);
>>> > + while (Node != -FDT_ERR_NOTFOUND) {
>>> > +Reg = (UINT64 *)fdt_getprop (FdtBase, Node, "reg", );
>>> > +if (Reg) {
>>> > + ASSERT (LenP == (2 * sizeof (UINT64)));
>>> > + AddIoMemoryBaseSizeHob (SwapBytes64 (Reg[0]), SwapBytes64
>>> (Reg[1]));
>>> > +}
>>> > +Node = fdt_node_offset_by_compatible (FdtBase, Node, Compatible);
>>> > + }
>>> > +}
>>> > +
>>> > /**
>>> >@retval EFI_SUCCESSThe address of FDT is passed in HOB.
>>> >EFI_UNSUPPORTEDCan't locate FDT.
>>> > @@ -80,5 +137,10 @@ PlatformPeimInitialization (
>>> >
>>> >BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32
>>> (PcdOvmfDxeMemFvSize));
>>> >
>&g
Re: [edk2-devel] [PATCH v3 7/7] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices
On Tue, May 30, 2023 at 10:38 AM Tuan Phan via groups.io wrote:
>
>
> On Mon, May 29, 2023 at 7:07 AM Ard Biesheuvel wrote:
>
>> On Sat, 27 May 2023 at 01:18, Tuan Phan wrote:
>> >
>> > Normally, DXE driver would add device resource to GCD before start
>> using.
>> > But some key resources such as uart, flash base address are being
>> accessing
>> > directly in some core modules.
>> >
>> > Those resources should be populated to HOB in SEC phase so they are
>> > added to GCD before anyone can access them.
>> >
>>
>> Why should these be in the GCD to begin with?
>>
>
> These resources should be in memory space so their addresses and size are
> registered with MMU. If not when MMU enabled, illegal access exception when
> someone access them.
>
> Hi Ard,
Do you still have concerns about this patch?
>
>> > Signed-off-by: Tuan Phan
>> > Reviewed-by: Andrei Warkentin
>>
>> > ---
>> > OvmfPkg/RiscVVirt/Sec/Platform.c | 62 +++
>> > OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 +
>> > 2 files changed, 63 insertions(+)
>> >
>> > diff --git a/OvmfPkg/RiscVVirt/Sec/Platform.c
>> b/OvmfPkg/RiscVVirt/Sec/Platform.c
>> > index 3645c27b0b12..944b82c84a6e 100644
>> > --- a/OvmfPkg/RiscVVirt/Sec/Platform.c
>> > +++ b/OvmfPkg/RiscVVirt/Sec/Platform.c
>> > @@ -21,6 +21,63 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
>> > #include
>> > #include
>> >
>> > +/**
>> > + Build memory map I/O range resource HOB using the
>> > + base address and size.
>> > +
>> > + @param MemoryBase Memory map I/O base.
>> > + @param MemorySize Memory map I/O size.
>> > +
>> > +**/
>> > +STATIC
>> > +VOID
>> > +AddIoMemoryBaseSizeHob (
>> > + EFI_PHYSICAL_ADDRESS MemoryBase,
>> > + UINT64MemorySize
>> > + )
>> > +{
>> > + /* Align to EFI_PAGE_SIZE */
>> > + MemorySize = ALIGN_VALUE (MemorySize, EFI_PAGE_SIZE);
>> > + BuildResourceDescriptorHob (
>> > +EFI_RESOURCE_MEMORY_MAPPED_IO,
>> > +EFI_RESOURCE_ATTRIBUTE_PRESENT |
>> > +EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
>> > +EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
>> > +EFI_RESOURCE_ATTRIBUTE_TESTED,
>> > +MemoryBase,
>> > +MemorySize
>> > +);
>> > +}
>> > +
>> > +/**
>> > + Populate IO resources from FDT that not added to GCD by its
>> > + driver in the DXE phase.
>> > +
>> > + @param FdtBase Fdt base address
>> > + @param CompatibleCompatible string
>> > +
>> > +**/
>> > +STATIC
>> > +VOID
>> > +PopulateIoResources (
>> > + VOID *FdtBase,
>> > + CONST CHAR8* Compatible
>> > + )
>> > +{
>> > + UINT64 *Reg;
>> > + INT32 Node, LenP;
>> > +
>> > + Node = fdt_node_offset_by_compatible (FdtBase, -1, Compatible);
>> > + while (Node != -FDT_ERR_NOTFOUND) {
>> > +Reg = (UINT64 *)fdt_getprop (FdtBase, Node, "reg", );
>> > +if (Reg) {
>> > + ASSERT (LenP == (2 * sizeof (UINT64)));
>> > + AddIoMemoryBaseSizeHob (SwapBytes64 (Reg[0]), SwapBytes64
>> (Reg[1]));
>> > +}
>> > +Node = fdt_node_offset_by_compatible (FdtBase, Node, Compatible);
>> > + }
>> > +}
>> > +
>> > /**
>> >@retval EFI_SUCCESSThe address of FDT is passed in HOB.
>> >EFI_UNSUPPORTEDCan't locate FDT.
>> > @@ -80,5 +137,10 @@ PlatformPeimInitialization (
>> >
>> >BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32
>> (PcdOvmfDxeMemFvSize));
>> >
>> > + PopulateIoResources (Base, "ns16550a");
>> > + PopulateIoResources (Base, "qemu,fw-cfg-mmio");
>> > + PopulateIoResources (Base, "virtio,mmio");
>> > + AddIoMemoryBaseSizeHob (PcdGet32 (PcdOvmfFdBaseAddress), PcdGet32
>> (PcdOvmfFirmwareFdSize));
>> > +
>> >return EFI_SUCCESS;
>> > }
>> > diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf
>> b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
>> > index 0e2a5785e8a4..75d5b74b3d3f 100644
>> > --- a/OvmfPkg/RiscVVirt/Sec/SecMain.inf
>> > +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
>> > @@ -62,6 +62,7 @@
>> >gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase
>> >gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize
>> >gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress
>> > + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize
>> >
>> > [Guids]
>> >gFdtHobGuid
>> > --
>> > 2.25.1
>> >
>> >
>> >
>> >
>> > Groups.io Links: You receive all messages sent to this group.
>> > View/Reply Online (#105346):
>> https://edk2.groups.io/g/devel/message/105346
>> > Mute This Topic: https://groups.io/mt/9916/1131722
>> > Group Owner: devel+ow...@edk2.groups.io
>> > Unsubscribe: https://edk2.groups.io/g/devel/unsub [a...@kernel.org]
>> >
>> >
>> >
>>
>
>
>
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[edk2-devel] [PATCH v2 2/2] UefiCpuPkg: RISC-V: TimerLib: Fix delay function to use 64-bit
The timer compare register is 64-bit so simplifying the delay
function.
Cc: Andrei Warkentin
Signed-off-by: Tuan Phan
Reviewed-by: Sunil V L
---
V2: Fix format issue with uncrustify.
MdePkg/Include/Register/RiscV64/RiscVImpl.h | 1 -
.../BaseRiscV64CpuTimerLib/CpuTimerLib.c | 53 ---
2 files changed, 23 insertions(+), 31 deletions(-)
diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h
b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
index ee5c2ba60377..6997de6cc001 100644
--- a/MdePkg/Include/Register/RiscV64/RiscVImpl.h
+++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
@@ -20,6 +20,5 @@
Name:
#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
-#define RISCV_TIMER_COMPARE_BITS 32
#endif
diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
index 9c8efc0f3530..27d7276aaa8a 100644
--- a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
+++ b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
@@ -22,26 +22,19 @@
@param Delay A period of time to delay in ticks.
**/
+STATIC
VOID
InternalRiscVTimerDelay (
- IN UINT32 Delay
+ IN UINT64 Delay
)
{
- UINT32 Ticks;
- UINT32 Times;
-
- Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
- Delay &= ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
- do {
-//
-// The target timer count is calculated here
-//
-Ticks = RiscVReadTimer () + Delay;
-Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
-while (((Ticks - RiscVReadTimer ()) & (1 << (RISCV_TIMER_COMPARE_BITS -
1))) == 0) {
- CpuPause ();
-}
- } while (Times-- > 0);
+ UINT64 Ticks;
+
+ Ticks = RiscVReadTimer () + Delay;
+
+ while (RiscVReadTimer () <= Ticks) {
+CpuPause ();
+ }
}
/**
@@ -61,13 +54,13 @@ MicroSecondDelay (
)
{
InternalRiscVTimerDelay (
-(UINT32)DivU64x32 (
- MultU64x32 (
-MicroSeconds,
-PcdGet64 (PcdCpuCoreCrystalClockFrequency)
-),
- 100u
- )
+DivU64x32 (
+ MultU64x32 (
+MicroSeconds,
+PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+),
+ 100u
+ )
);
return MicroSeconds;
}
@@ -89,13 +82,13 @@ NanoSecondDelay (
)
{
InternalRiscVTimerDelay (
-(UINT32)DivU64x32 (
- MultU64x32 (
-NanoSeconds,
-PcdGet64 (PcdCpuCoreCrystalClockFrequency)
-),
- 10u
- )
+DivU64x32 (
+ MultU64x32 (
+NanoSeconds,
+PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+),
+ 10u
+ )
);
return NanoSeconds;
}
--
2.25.1
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[edk2-devel] [PATCH v2 1/2] UefiCpuPkg: CpuTimerDxeRiscV64: Fix incorrect value sent to SbiSetTimer
SbiSetTimer expects core tick value.
Cc: Andrei Warkentin
Signed-off-by: Tuan Phan
Reviewed-by: Sunil V L
---
V2: Fixed format issue with uncrustify.
.../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 3 +++
UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 26 ---
UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h | 2 +-
3 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
index c76bd9648373..aba660186dc0 100644
--- a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
+++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
@@ -40,6 +40,9 @@
Timer.h
Timer.c
+[Pcd]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## CONSUMES
+
[Protocols]
gEfiCpuArchProtocolGuid ## CONSUMES
gEfiTimerArchProtocolGuid ## PRODUCES
diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
index fa957ba5e3e9..358057e7c6a4 100644
--- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
+++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
@@ -80,8 +80,15 @@ TimerInterruptHandler (
return;
}
- mLastPeriodStart = PeriodStart;
- SbiSetTimer (PeriodStart += mTimerPeriod);
+ mLastPeriodStart = PeriodStart;
+ PeriodStart += DivU64x32 (
+ MultU64x32 (
+ mTimerPeriod,
+ PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+ ),
+ 100u
+ ); // convert to tick
+ SbiSetTimer (PeriodStart);
RiscVEnableTimerInterrupt (); // enable SMode timer int
gBS->RestoreTPL (OriginalTPL);
}
@@ -163,6 +170,8 @@ TimerDriverSetTimerPeriod (
IN UINT64 TimerPeriod
)
{
+ UINT64 PeriodStart;
+
DEBUG ((DEBUG_INFO, "TimerDriverSetTimerPeriod(0x%lx)\n", TimerPeriod));
if (TimerPeriod == 0) {
@@ -171,9 +180,18 @@ TimerDriverSetTimerPeriod (
return EFI_SUCCESS;
}
- mTimerPeriod = TimerPeriod / 10; // convert unit from 100ns to 1us
+ mTimerPeriod = TimerPeriod / 10; // convert unit from 100ns to 1us
+
mLastPeriodStart = RiscVReadTimer ();
- SbiSetTimer (mLastPeriodStart + mTimerPeriod);
+ PeriodStart = mLastPeriodStart;
+ PeriodStart += DivU64x32 (
+ MultU64x32 (
+ mTimerPeriod,
+ PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+ ),
+ 100u
+ ); // convert to tick
+ SbiSetTimer (PeriodStart);
mCpu->EnableInterrupt (mCpu);
RiscVEnableTimerInterrupt (); // enable SMode timer int
diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
index 586eb0cfadb4..9b3542230cb5 100644
--- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
+++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
@@ -21,7 +21,7 @@
#include
//
-// RISC-V use 100us timer.
+// RISC-V use 100ns timer.
// The default timer tick duration is set to 10 ms = 10 * 1000 * 10 100 ns
units
//
#define DEFAULT_TIMER_TICK_DURATION 10
--
2.25.1
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[edk2-devel] [PATCH] OvmfPkg: RiscVVirt: Fix wrong checking Pci IO access
RiscV uses memory access for IO and MMIO resources, the address limit
is MAX_ADDRESS for both of them.
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c
b/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c
index f3bf07e63141..75389235d897 100644
--- a/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c
+++ b/OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c
@@ -19,8 +19,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include
#include
-#define MAX_IO_PORT_ADDRESS 0x
-
//
// Handle for the CPU I/O 2 Protocol
//
@@ -143,16 +141,16 @@ CpuIoCheckParameter (
// Address + Size * Count. If the following condition is met, then the
transfer
// is not supported.
//
- //Address + Size * Count > (MmioOperation ? MAX_ADDRESS :
MAX_IO_PORT_ADDRESS) + 1
+ //Address + Size * Count > MAX_ADDRESS + 1
//
// Since MAX_ADDRESS can be the maximum integer value supported by the CPU
and Count
// can also be the maximum integer value supported by the CPU, this range
// check must be adjusted to avoid all overflow conditions.
//
// The following form of the range check is equivalent but assumes that
- // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).
+ // MAX_ADDRESS is of the form (2^n - 1).
//
- Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);
+ Limit = MAX_ADDRESS;
if (Count == 0) {
if (Address > Limit) {
return EFI_UNSUPPORTED;
--
2.25.1
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[edk2-devel] [PATCH] OvmfPkg: RiscVVirt: Fix network drivers not be built
Only need to include Network.dsc.inc to have all network
drivers/components be built. Otherwise, there were missing definition
that prevent them from be built for RiscVVirt platform.
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 15 +--
1 file changed, 1 insertion(+), 14 deletions(-)
diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
index 414d186179fb..5281b611d453 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
+++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
@@ -52,6 +52,7 @@
!include MdePkg/MdeLibs.dsc.inc
+!include NetworkPkg/Network.dsc.inc
[BuildOptions]
GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
@@ -69,8 +70,6 @@
#
-!include NetworkPkg/NetworkDefines.dsc.inc
-
!include OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
!include MdePkg/MdeLibs.dsc.inc
@@ -124,8 +123,6 @@
UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
PciExpressLib|OvmfPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpressLib.inf
-#!include NetworkPkg/NetworkBuildOptions.dsc.inc
-
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
@@ -164,11 +161,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|3686400
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1
- #
- # Network Pcds
- #
-!include NetworkPkg/NetworkPcds.dsc.inc
-
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c,
0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
@@ -397,11 +389,6 @@
NULL|OvmfPkg/Library/BlobVerifierLibNull/BlobVerifierLibNull.inf
}
- #
- # Networking stack
- #
-!include NetworkPkg/NetworkComponents.dsc.inc
-
NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf {
NULL|OvmfPkg/Library/PxeBcPcdProducerLib/PxeBcPcdProducerLib.inf
--
2.25.1
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Re: [edk2-devel] [PATCH 2/2] UefiCpuPkg: RISC-V: TimerLib: Fix delay function to use 64-bit
On Tue, Jun 6, 2023 at 10:10 AM Sunil V L wrote:
> On Tue, Jun 06, 2023 at 10:02:08AM -0700, Tuan Phan wrote:
> > On Tue, Jun 6, 2023 at 3:27 AM Sunil V L
> wrote:
> >
> > > On Fri, May 26, 2023 at 04:25:18PM -0700, Tuan Phan wrote:
> > > > The timer compare register is 64-bit so simplifying the delay
> > > > function.
> > > >
> > > > Signed-off-by: Tuan Phan
> > > > ---
> > > > MdePkg/Include/Register/RiscV64/RiscVImpl.h | 1 -
> > > > .../BaseRiscV64CpuTimerLib/CpuTimerLib.c | 62
> +--
> > > > 2 files changed, 28 insertions(+), 35 deletions(-)
> > > >
> > > > diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h
> > > b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
> > > > index ee5c2ba60377..6997de6cc001 100644
> > > > --- a/MdePkg/Include/Register/RiscV64/RiscVImpl.h
> > > > +++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
> > > > @@ -20,6 +20,5 @@
> > > >Name:
> > > >
> > > > #define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
> > > > -#define RISCV_TIMER_COMPARE_BITS 32
> > > >
> > > > #endif
> > > > diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
> > > b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
> > > > index 9c8efc0f3530..57800177023c 100644
> > > > --- a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
> > > > +++ b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
> > > > @@ -22,26 +22,19 @@
> > > >@param Delay A period of time to delay in ticks.
> > > >
> > > > **/
> > > > +STATIC
> > > > VOID
> > > > InternalRiscVTimerDelay (
> > > > - IN UINT32 Delay
> > > > + IN UINT64 Delay
> > > >)
> > > > {
> > > > - UINT32 Ticks;
> > > > - UINT32 Times;
> > > > -
> > > > - Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
> > > > - Delay &= ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
> > > > - do {
> > > > -//
> > > > -// The target timer count is calculated here
> > > > -//
> > > > -Ticks = RiscVReadTimer () + Delay;
> > > > -Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
> > > > -while (((Ticks - RiscVReadTimer ()) & (1 <<
> > > (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
> > > > - CpuPause ();
> > > > -}
> > > > - } while (Times-- > 0);
> > > > + UINT64 Ticks;
> > > > +
> > > > + Ticks = RiscVReadTimer () + Delay;
> > > > +
> > > > + while (RiscVReadTimer () <= Ticks) {
> > > > +CpuPause ();
> > > > + }
> > > > }
> > > >
> > > > /**
> > > > @@ -61,14 +54,14 @@ MicroSecondDelay (
> > > >)
> > > > {
> > > >InternalRiscVTimerDelay (
> > > > -(UINT32)DivU64x32 (
> > > > - MultU64x32 (
> > > > -MicroSeconds,
> > > > -PcdGet64 (PcdCpuCoreCrystalClockFrequency)
> > > > -),
> > > > - 100u
> > > > - )
> > > > -);
> > > > +DivU64x32 (
> > > > + MultU64x32 (
> > > > +MicroSeconds,
> > > > +PcdGet64 (PcdCpuCoreCrystalClockFrequency)
> > > > + ),
> > > > + 100u
> > > > +)
> > > > + );
> > > >return MicroSeconds;
> > > > }
> > > >
> > > > @@ -89,14 +82,14 @@ NanoSecondDelay (
> > > >)
> > > > {
> > > >InternalRiscVTimerDelay (
> > > > -(UINT32)DivU64x32 (
> > > > - MultU64x32 (
> > > > -NanoSeconds,
> > > > -PcdGet64 (PcdCpuCoreCrystalClockFrequency)
> > > > -),
> > > > - 10u
> > > > - )
> > > > -);
> > > > +DivU64x32 (
> > > > + MultU64x32 (
> > > > +NanoSeconds,
> > > > +PcdGet64 (PcdCpuCoreCrystalClockFrequency)
> > > > + ),
> > > > + 10u
> > >
Re: [edk2-devel] [PATCH 2/2] UefiCpuPkg: RISC-V: TimerLib: Fix delay function to use 64-bit
On Tue, Jun 6, 2023 at 3:27 AM Sunil V L wrote:
> On Fri, May 26, 2023 at 04:25:18PM -0700, Tuan Phan wrote:
> > The timer compare register is 64-bit so simplifying the delay
> > function.
> >
> > Signed-off-by: Tuan Phan
> > ---
> > MdePkg/Include/Register/RiscV64/RiscVImpl.h | 1 -
> > .../BaseRiscV64CpuTimerLib/CpuTimerLib.c | 62 +--
> > 2 files changed, 28 insertions(+), 35 deletions(-)
> >
> > diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h
> b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
> > index ee5c2ba60377..6997de6cc001 100644
> > --- a/MdePkg/Include/Register/RiscV64/RiscVImpl.h
> > +++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
> > @@ -20,6 +20,5 @@
> >Name:
> >
> > #define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
> > -#define RISCV_TIMER_COMPARE_BITS 32
> >
> > #endif
> > diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
> b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
> > index 9c8efc0f3530..57800177023c 100644
> > --- a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
> > +++ b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
> > @@ -22,26 +22,19 @@
> >@param Delay A period of time to delay in ticks.
> >
> > **/
> > +STATIC
> > VOID
> > InternalRiscVTimerDelay (
> > - IN UINT32 Delay
> > + IN UINT64 Delay
> >)
> > {
> > - UINT32 Ticks;
> > - UINT32 Times;
> > -
> > - Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
> > - Delay &= ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
> > - do {
> > -//
> > -// The target timer count is calculated here
> > -//
> > -Ticks = RiscVReadTimer () + Delay;
> > -Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
> > -while (((Ticks - RiscVReadTimer ()) & (1 <<
> (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
> > - CpuPause ();
> > -}
> > - } while (Times-- > 0);
> > + UINT64 Ticks;
> > +
> > + Ticks = RiscVReadTimer () + Delay;
> > +
> > + while (RiscVReadTimer () <= Ticks) {
> > +CpuPause ();
> > + }
> > }
> >
> > /**
> > @@ -61,14 +54,14 @@ MicroSecondDelay (
> >)
> > {
> >InternalRiscVTimerDelay (
> > -(UINT32)DivU64x32 (
> > - MultU64x32 (
> > -MicroSeconds,
> > -PcdGet64 (PcdCpuCoreCrystalClockFrequency)
> > -),
> > - 100u
> > - )
> > -);
> > +DivU64x32 (
> > + MultU64x32 (
> > +MicroSeconds,
> > +PcdGet64 (PcdCpuCoreCrystalClockFrequency)
> > + ),
> > + 100u
> > +)
> > + );
> >return MicroSeconds;
> > }
> >
> > @@ -89,14 +82,14 @@ NanoSecondDelay (
> >)
> > {
> >InternalRiscVTimerDelay (
> > -(UINT32)DivU64x32 (
> > - MultU64x32 (
> > -NanoSeconds,
> > -PcdGet64 (PcdCpuCoreCrystalClockFrequency)
> > -),
> > - 10u
> > - )
> > -);
> > +DivU64x32 (
> > + MultU64x32 (
> > +NanoSeconds,
> > +PcdGet64 (PcdCpuCoreCrystalClockFrequency)
> > + ),
> > + 10u
> > +)
> > + );
> >return NanoSeconds;
> > }
> >
> > @@ -147,8 +140,9 @@ GetPerformanceCounter (
> > UINT64
> > EFIAPI
> > GetPerformanceCounterProperties (
> > - OUT UINT64 *StartValue, OPTIONAL
> > - OUT UINT64*EndValue OPTIONAL
> > + OUT UINT64 *StartValue,
> > + OPTIONAL
> > + OUT UINT64 *EndValue OPTIONAL
>
> Hi Tuan,
>
> What is this change? The formatting doesn't look correct. Have you run
> CI tests?
>
=> That is the result of running crutinize tool with edk2 config. Should I
leave it as before?
>
> Otherwise LGTM. Thanks for the fix!
>
> Reviewed-by: Sunil V L
>
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Re: [edk2-devel] [PATCH v3 7/7] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices
On Mon, May 29, 2023 at 7:07 AM Ard Biesheuvel wrote:
> On Sat, 27 May 2023 at 01:18, Tuan Phan wrote:
> >
> > Normally, DXE driver would add device resource to GCD before start using.
> > But some key resources such as uart, flash base address are being
> accessing
> > directly in some core modules.
> >
> > Those resources should be populated to HOB in SEC phase so they are
> > added to GCD before anyone can access them.
> >
>
> Why should these be in the GCD to begin with?
>
These resources should be in memory space so their addresses and size are
registered with MMU. If not when MMU enabled, illegal access exception when
someone access them.
> > Signed-off-by: Tuan Phan
> > Reviewed-by: Andrei Warkentin
>
> > ---
> > OvmfPkg/RiscVVirt/Sec/Platform.c | 62 +++
> > OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 +
> > 2 files changed, 63 insertions(+)
> >
> > diff --git a/OvmfPkg/RiscVVirt/Sec/Platform.c
> b/OvmfPkg/RiscVVirt/Sec/Platform.c
> > index 3645c27b0b12..944b82c84a6e 100644
> > --- a/OvmfPkg/RiscVVirt/Sec/Platform.c
> > +++ b/OvmfPkg/RiscVVirt/Sec/Platform.c
> > @@ -21,6 +21,63 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> > #include
> > #include
> >
> > +/**
> > + Build memory map I/O range resource HOB using the
> > + base address and size.
> > +
> > + @param MemoryBase Memory map I/O base.
> > + @param MemorySize Memory map I/O size.
> > +
> > +**/
> > +STATIC
> > +VOID
> > +AddIoMemoryBaseSizeHob (
> > + EFI_PHYSICAL_ADDRESS MemoryBase,
> > + UINT64MemorySize
> > + )
> > +{
> > + /* Align to EFI_PAGE_SIZE */
> > + MemorySize = ALIGN_VALUE (MemorySize, EFI_PAGE_SIZE);
> > + BuildResourceDescriptorHob (
> > +EFI_RESOURCE_MEMORY_MAPPED_IO,
> > +EFI_RESOURCE_ATTRIBUTE_PRESENT |
> > +EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> > +EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
> > +EFI_RESOURCE_ATTRIBUTE_TESTED,
> > +MemoryBase,
> > +MemorySize
> > +);
> > +}
> > +
> > +/**
> > + Populate IO resources from FDT that not added to GCD by its
> > + driver in the DXE phase.
> > +
> > + @param FdtBase Fdt base address
> > + @param CompatibleCompatible string
> > +
> > +**/
> > +STATIC
> > +VOID
> > +PopulateIoResources (
> > + VOID *FdtBase,
> > + CONST CHAR8* Compatible
> > + )
> > +{
> > + UINT64 *Reg;
> > + INT32 Node, LenP;
> > +
> > + Node = fdt_node_offset_by_compatible (FdtBase, -1, Compatible);
> > + while (Node != -FDT_ERR_NOTFOUND) {
> > +Reg = (UINT64 *)fdt_getprop (FdtBase, Node, "reg", );
> > +if (Reg) {
> > + ASSERT (LenP == (2 * sizeof (UINT64)));
> > + AddIoMemoryBaseSizeHob (SwapBytes64 (Reg[0]), SwapBytes64
> (Reg[1]));
> > +}
> > +Node = fdt_node_offset_by_compatible (FdtBase, Node, Compatible);
> > + }
> > +}
> > +
> > /**
> >@retval EFI_SUCCESSThe address of FDT is passed in HOB.
> >EFI_UNSUPPORTEDCan't locate FDT.
> > @@ -80,5 +137,10 @@ PlatformPeimInitialization (
> >
> >BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32
> (PcdOvmfDxeMemFvSize));
> >
> > + PopulateIoResources (Base, "ns16550a");
> > + PopulateIoResources (Base, "qemu,fw-cfg-mmio");
> > + PopulateIoResources (Base, "virtio,mmio");
> > + AddIoMemoryBaseSizeHob (PcdGet32 (PcdOvmfFdBaseAddress), PcdGet32
> (PcdOvmfFirmwareFdSize));
> > +
> >return EFI_SUCCESS;
> > }
> > diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf
> b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
> > index 0e2a5785e8a4..75d5b74b3d3f 100644
> > --- a/OvmfPkg/RiscVVirt/Sec/SecMain.inf
> > +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
> > @@ -62,6 +62,7 @@
> >gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase
> >gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize
> >gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress
> > + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize
> >
> > [Guids]
> >gFdtHobGuid
> > --
> > 2.25.1
> >
> >
> >
> >
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> >
> >
> >
>
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[edk2-devel] [PATCH 2/2] UefiCpuPkg: RISC-V: TimerLib: Fix delay function to use 64-bit
The timer compare register is 64-bit so simplifying the delay
function.
Signed-off-by: Tuan Phan
---
MdePkg/Include/Register/RiscV64/RiscVImpl.h | 1 -
.../BaseRiscV64CpuTimerLib/CpuTimerLib.c | 62 +--
2 files changed, 28 insertions(+), 35 deletions(-)
diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h
b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
index ee5c2ba60377..6997de6cc001 100644
--- a/MdePkg/Include/Register/RiscV64/RiscVImpl.h
+++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
@@ -20,6 +20,5 @@
Name:
#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
-#define RISCV_TIMER_COMPARE_BITS 32
#endif
diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
index 9c8efc0f3530..57800177023c 100644
--- a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
+++ b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
@@ -22,26 +22,19 @@
@param Delay A period of time to delay in ticks.
**/
+STATIC
VOID
InternalRiscVTimerDelay (
- IN UINT32 Delay
+ IN UINT64 Delay
)
{
- UINT32 Ticks;
- UINT32 Times;
-
- Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
- Delay &= ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
- do {
-//
-// The target timer count is calculated here
-//
-Ticks = RiscVReadTimer () + Delay;
-Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
-while (((Ticks - RiscVReadTimer ()) & (1 << (RISCV_TIMER_COMPARE_BITS -
1))) == 0) {
- CpuPause ();
-}
- } while (Times-- > 0);
+ UINT64 Ticks;
+
+ Ticks = RiscVReadTimer () + Delay;
+
+ while (RiscVReadTimer () <= Ticks) {
+CpuPause ();
+ }
}
/**
@@ -61,14 +54,14 @@ MicroSecondDelay (
)
{
InternalRiscVTimerDelay (
-(UINT32)DivU64x32 (
- MultU64x32 (
-MicroSeconds,
-PcdGet64 (PcdCpuCoreCrystalClockFrequency)
-),
- 100u
- )
-);
+DivU64x32 (
+ MultU64x32 (
+MicroSeconds,
+PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+ ),
+ 100u
+)
+ );
return MicroSeconds;
}
@@ -89,14 +82,14 @@ NanoSecondDelay (
)
{
InternalRiscVTimerDelay (
-(UINT32)DivU64x32 (
- MultU64x32 (
-NanoSeconds,
-PcdGet64 (PcdCpuCoreCrystalClockFrequency)
-),
- 10u
- )
-);
+DivU64x32 (
+ MultU64x32 (
+NanoSeconds,
+PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+ ),
+ 10u
+)
+ );
return NanoSeconds;
}
@@ -147,8 +140,9 @@ GetPerformanceCounter (
UINT64
EFIAPI
GetPerformanceCounterProperties (
- OUT UINT64 *StartValue, OPTIONAL
- OUT UINT64*EndValue OPTIONAL
+ OUT UINT64 *StartValue,
+ OPTIONAL
+ OUT UINT64 *EndValue OPTIONAL
)
{
if (StartValue != NULL) {
--
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[edk2-devel] [PATCH 1/2] UefiCpuPkg: CpuTimerDxeRiscV64: Fix incorrect value sent to SbiSetTimer
SbiSetTimer expects core tick value.
Signed-off-by: Tuan Phan
---
.../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 3 +++
UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 26 ---
UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h | 2 +-
3 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
index c76bd9648373..cd58d3a2f86b 100644
--- a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
+++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
@@ -40,6 +40,9 @@
Timer.h
Timer.c
+[Pcd]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## CONSUMES
+
[Protocols]
gEfiCpuArchProtocolGuid ## CONSUMES
gEfiTimerArchProtocolGuid ## PRODUCES
diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
index fa957ba5e3e9..a8afb649149f 100644
--- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
+++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
@@ -80,8 +80,15 @@ TimerInterruptHandler (
return;
}
- mLastPeriodStart = PeriodStart;
- SbiSetTimer (PeriodStart += mTimerPeriod);
+ mLastPeriodStart = PeriodStart;
+ PeriodStart += DivU64x32 (
+MultU64x32 (
+ mTimerPeriod,
+ PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+),
+100u
+ ); // convert to tick
+ SbiSetTimer (PeriodStart);
RiscVEnableTimerInterrupt (); // enable SMode timer int
gBS->RestoreTPL (OriginalTPL);
}
@@ -163,6 +170,8 @@ TimerDriverSetTimerPeriod (
IN UINT64 TimerPeriod
)
{
+ UINT64 PeriodStart;
+
DEBUG ((DEBUG_INFO, "TimerDriverSetTimerPeriod(0x%lx)\n", TimerPeriod));
if (TimerPeriod == 0) {
@@ -171,9 +180,18 @@ TimerDriverSetTimerPeriod (
return EFI_SUCCESS;
}
- mTimerPeriod = TimerPeriod / 10; // convert unit from 100ns to 1us
+ mTimerPeriod = TimerPeriod / 10; // convert unit from 100ns to 1us
+
mLastPeriodStart = RiscVReadTimer ();
- SbiSetTimer (mLastPeriodStart + mTimerPeriod);
+ PeriodStart = mLastPeriodStart;
+ PeriodStart += DivU64x32 (
+MultU64x32 (
+ mTimerPeriod,
+ PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+),
+100u
+ ); // convert to tick
+ SbiSetTimer (PeriodStart);
mCpu->EnableInterrupt (mCpu);
RiscVEnableTimerInterrupt (); // enable SMode timer int
diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
index 586eb0cfadb4..9b3542230cb5 100644
--- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
+++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
@@ -21,7 +21,7 @@
#include
//
-// RISC-V use 100us timer.
+// RISC-V use 100ns timer.
// The default timer tick duration is set to 10 ms = 10 * 1000 * 10 100 ns
units
//
#define DEFAULT_TIMER_TICK_DURATION 10
--
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[edk2-devel] [PATCH v3 7/7] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices
Normally, DXE driver would add device resource to GCD before start using.
But some key resources such as uart, flash base address are being accessing
directly in some core modules.
Those resources should be populated to HOB in SEC phase so they are
added to GCD before anyone can access them.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
OvmfPkg/RiscVVirt/Sec/Platform.c | 62 +++
OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 +
2 files changed, 63 insertions(+)
diff --git a/OvmfPkg/RiscVVirt/Sec/Platform.c b/OvmfPkg/RiscVVirt/Sec/Platform.c
index 3645c27b0b12..944b82c84a6e 100644
--- a/OvmfPkg/RiscVVirt/Sec/Platform.c
+++ b/OvmfPkg/RiscVVirt/Sec/Platform.c
@@ -21,6 +21,63 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include
#include
+/**
+ Build memory map I/O range resource HOB using the
+ base address and size.
+
+ @param MemoryBase Memory map I/O base.
+ @param MemorySize Memory map I/O size.
+
+**/
+STATIC
+VOID
+AddIoMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64MemorySize
+ )
+{
+ /* Align to EFI_PAGE_SIZE */
+ MemorySize = ALIGN_VALUE (MemorySize, EFI_PAGE_SIZE);
+ BuildResourceDescriptorHob (
+EFI_RESOURCE_MEMORY_MAPPED_IO,
+EFI_RESOURCE_ATTRIBUTE_PRESENT |
+EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+EFI_RESOURCE_ATTRIBUTE_TESTED,
+MemoryBase,
+MemorySize
+);
+}
+
+/**
+ Populate IO resources from FDT that not added to GCD by its
+ driver in the DXE phase.
+
+ @param FdtBase Fdt base address
+ @param CompatibleCompatible string
+
+**/
+STATIC
+VOID
+PopulateIoResources (
+ VOID *FdtBase,
+ CONST CHAR8* Compatible
+ )
+{
+ UINT64 *Reg;
+ INT32 Node, LenP;
+
+ Node = fdt_node_offset_by_compatible (FdtBase, -1, Compatible);
+ while (Node != -FDT_ERR_NOTFOUND) {
+Reg = (UINT64 *)fdt_getprop (FdtBase, Node, "reg", );
+if (Reg) {
+ ASSERT (LenP == (2 * sizeof (UINT64)));
+ AddIoMemoryBaseSizeHob (SwapBytes64 (Reg[0]), SwapBytes64 (Reg[1]));
+}
+Node = fdt_node_offset_by_compatible (FdtBase, Node, Compatible);
+ }
+}
+
/**
@retval EFI_SUCCESSThe address of FDT is passed in HOB.
EFI_UNSUPPORTEDCan't locate FDT.
@@ -80,5 +137,10 @@ PlatformPeimInitialization (
BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32 (PcdOvmfDxeMemFvSize));
+ PopulateIoResources (Base, "ns16550a");
+ PopulateIoResources (Base, "qemu,fw-cfg-mmio");
+ PopulateIoResources (Base, "virtio,mmio");
+ AddIoMemoryBaseSizeHob (PcdGet32 (PcdOvmfFdBaseAddress), PcdGet32
(PcdOvmfFirmwareFdSize));
+
return EFI_SUCCESS;
}
diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf
b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
index 0e2a5785e8a4..75d5b74b3d3f 100644
--- a/OvmfPkg/RiscVVirt/Sec/SecMain.inf
+++ b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
@@ -62,6 +62,7 @@
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize
[Guids]
gFdtHobGuid
--
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[edk2-devel] [PATCH v3 6/7] OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists
The flash base address can be added to GCD before this driver run.
So only add it if it has not been done.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +++
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
b/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
index 6b9ef261335e..bbd1697a51dd 100644
--- a/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
+++ b/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
@@ -372,10 +372,11 @@ NorFlashFvbInitialize (
IN NOR_FLASH_INSTANCE *Instance
)
{
- EFI_STATUS Status;
- UINT32 FvbNumLba;
- EFI_BOOT_MODE BootMode;
- UINTN RuntimeMmioRegionSize;
+ EFI_STATUS Status;
+ UINT32 FvbNumLba;
+ EFI_BOOT_MODE BootMode;
+ UINTN RuntimeMmioRegionSize;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR Desc;
DEBUG ((DEBUG_BLKIO, "NorFlashFvbInitialize\n"));
ASSERT ((Instance != NULL));
@@ -390,13 +391,19 @@ NorFlashFvbInitialize (
// is written as the base of the flash region (ie:
Instance->DeviceBaseAddress)
RuntimeMmioRegionSize = (Instance->RegionBaseAddress -
Instance->DeviceBaseAddress) + Instance->Size;
- Status = gDS->AddMemorySpace (
- EfiGcdMemoryTypeMemoryMappedIo,
+ Status = gDS->GetMemorySpaceDescriptor (
Instance->DeviceBaseAddress,
- RuntimeMmioRegionSize,
- EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+
);
- ASSERT_EFI_ERROR (Status);
+ if (Status == EFI_NOT_FOUND) {
+Status = gDS->AddMemorySpace (
+EfiGcdMemoryTypeMemoryMappedIo,
+Instance->DeviceBaseAddress,
+RuntimeMmioRegionSize,
+EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+);
+ASSERT_EFI_ERROR (Status);
+ }
Status = gDS->SetMemorySpaceAttributes (
Instance->DeviceBaseAddress,
--
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[edk2-devel] [PATCH v3 5/7] OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size
The size should be for single region, not the whole firmware FD.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
.../Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c| 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
index fdc2ccb6294e..33f3a01b06f4 100644
--- a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
+++ b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
@@ -24,7 +24,8 @@ VIRT_NOR_FLASH_DESCRIPTION mNorFlashDevice =
{
FixedPcdGet32 (PcdOvmfFdBaseAddress),
FixedPcdGet64 (PcdFlashNvStorageVariableBase),
- FixedPcdGet32 (PcdOvmfFirmwareFdSize),
+ FixedPcdGet32 (PcdOvmfFirmwareFdSize) -
+ (FixedPcdGet64 (PcdFlashNvStorageVariableBase) - FixedPcdGet32
(PcdOvmfFdBaseAddress)),
QEMU_NOR_BLOCK_SIZE
};
--
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[edk2-devel] [PATCH v3 3/7] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf| 2 +
UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h | 39 ++
.../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++
.../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 26 +
.../Library/BaseRiscVMmuLib/RiscVMmuCore.S| 31 +
7 files changed, 676 insertions(+), 2 deletions(-)
create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
index 25fe3f54c325..2af3b6223450 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
@@ -296,8 +296,7 @@ CpuSetMemoryAttributes (
IN UINT64 Attributes
)
{
- DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n",
__func__));
- return EFI_SUCCESS;
+ return RiscVSetMemoryAttributes (BaseAddress, Length, Attributes);
}
/**
@@ -340,6 +339,12 @@ InitializeCpu (
//
DisableInterrupts ();
+ //
+ // Enable MMU
+ //
+ Status = RiscVConfigureMmu ();
+ ASSERT_EFI_ERROR (Status);
+
//
// Install Boot protocol
//
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
index 49f4e119665a..68e6d038b66e 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
@@ -15,11 +15,13 @@
#include
#include
#include
+#include
#include
#include
#include
#include
#include
+#include
/**
Flush CPU data cache. If the instruction cache is fully coherent
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
index e8fa25446aef..9d9a5ef8f247 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
@@ -37,6 +37,8 @@
TimerLib
PeCoffGetEntryPointLib
RiscVSbiLib
+ RiscVMmuLib
+ CacheMaintenanceLib
[Sources]
CpuDxe.c
diff --git a/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
b/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
new file mode 100644
index ..f71d6a4a1e7b
--- /dev/null
+++ b/UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h
@@ -0,0 +1,39 @@
+/** @file
+
+ Copyright (c) 2015 - 2016, Linaro Ltd. All rights reserved.
+ Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef BASE_RISCV_MMU_LIB_H_
+#define BASE_RISCV_MMU_LIB_H_
+
+VOID
+EFIAPI
+RiscVLocalTlbFlushAll (
+ VOID
+ );
+
+VOID
+EFIAPI
+RiscVLocalTlbFlush (
+ UINTN VirtAddr
+ );
+
+EFI_STATUS
+EFIAPI
+RiscVSetMemoryAttributes (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64Length,
+ IN UINT64Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+RiscVConfigureMmu (
+ VOID
+ );
+
+#endif /* BASE_RISCV_MMU_LIB_H_ */
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
new file mode 100644
index ..230f34261d8b
--- /dev/null
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
@@ -0,0 +1,569 @@
+/** @file
+* MMU implementation for RISC-V
+*
+* Copyright (c) 2011-2020, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+* Copyright (c) 2017, Intel Corporation. All rights reserved.
+* Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define RISCV_PG_V BIT0
+#define RISCV_PG_R BIT1
+#define RISCV_PG_W BIT2
+#define RISCV_PG_X BIT3
+#define RISCV_PG_G BIT5
+#define RISCV_PG_A BIT6
+#define RISCV_PG_D BIT7
+#define PTE_ATTRIBUTES_MASK 0xE
+
+#define PTE_PPN_MASK 0x3FFC00ULL
+#define PTE_PPN_SHIFT 10
+#define RISCV_MMU_PAGE_SHIFT 12
+
+STATIC UINTN mMaxRootTableLevel;
+STATIC UINTN mBitPerLevel;
+STATIC UINTN mTableEntryCount;
+
+STATIC
+BOOLEAN
+RiscVMmuEnabled (
+ VOID
+ )
+{
+ return ((RiscVGetSupervisorAddressTranslationRegister () &
+ SATP64_MODE) != (SATP_MODE_OFF << SATP64_MODE_SHIFT));
+}
+
+STATIC
+UINTN
+RiscVGetRootTranslateTable (
+ VOID
+ )
+{
+ return (RiscVGetSupervisorAddressTranslationRegister () & SATP64_PPN) <<
+ RISCV_MMU_PAGE_SHIFT;
+}
+
+STATIC
+BOOLEAN
+IsValidPte (
+ IN UINTN Entry
+ )
+{
+ if (!(Entry &a
[edk2-devel] [PATCH v3 4/7] OvmfPkg/RiscVVirt: Remove satp bare mode setting
MMU now is initialized in CpuDxe. There is no point to set satp to bare
mode as that should be the default mode when booting edk2.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
OvmfPkg/RiscVVirt/Sec/Memory.c | 18 ++
2 files changed, 3 insertions(+), 16 deletions(-)
diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
index 731f54f73f81..bc204ba5fe52 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
+++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
@@ -83,6 +83,7 @@
# RISC-V Architectural Libraries
CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
+ RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
PlatformBootManagerLib|OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
ResetSystemLib|OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf
diff --git a/OvmfPkg/RiscVVirt/Sec/Memory.c b/OvmfPkg/RiscVVirt/Sec/Memory.c
index 0e2690c73687..aad71ee5dcbb 100644
--- a/OvmfPkg/RiscVVirt/Sec/Memory.c
+++ b/OvmfPkg/RiscVVirt/Sec/Memory.c
@@ -85,21 +85,6 @@ AddMemoryRangeHob (
AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
}
-/**
- Configure MMU
-**/
-STATIC
-VOID
-InitMmu (
- )
-{
- //
- // Set supervisor translation mode to Bare mode
- //
- RiscVSetSupervisorAddressTranslationRegister ((UINT64)SATP_MODE_OFF << 60);
- DEBUG ((DEBUG_INFO, "%a: Set Supervisor address mode to bare-metal mode.\n",
__func__));
-}
-
/**
Publish system RAM and reserve memory regions.
@@ -327,7 +312,8 @@ MemoryPeimInitialization (
AddReservedMemoryMap (FdtPointer);
- InitMmu ();
+ /* Make sure SEC is booting with bare mode */
+ ASSERT ((RiscVGetSupervisorAddressTranslationRegister () & SATP64_MODE) ==
(SATP_MODE_OFF << SATP64_MODE_SHIFT));
BuildMemoryTypeInformationHob ();
--
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[edk2-devel] [PATCH v3 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition
The satp mode bits shift is used cross modules. It should be defined in one place. Signed-off-by: Tuan Phan Reviewed-by: Andrei Warkentin --- MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h index 5c2989b797bf..2bde8db478ff 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -58,9 +58,10 @@ #define PRV_S 1UL #define PRV_M 3UL -#define SATP64_MODE 0xF000ULL -#define SATP64_ASID 0x0000ULL -#define SATP64_PPN 0x0FFFULL +#define SATP64_MODE0xF000ULL +#define SATP64_MODE_SHIFT 60 +#define SATP64_ASID0x0000ULL +#define SATP64_PPN 0x0FFFULL #define SATP_MODE_OFF 0UL #define SATP_MODE_SV32 1UL -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#105341): https://edk2.groups.io/g/devel/message/105341 Mute This Topic: https://groups.io/mt/99159995/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v3 1/7] MdePkg/BaseLib: RISC-V: Support getting satp register value
Add an API to retrieve satp register value. Signed-off-by: Tuan Phan Reviewed-by: Andrei Warkentin --- MdePkg/Include/Library/BaseLib.h | 5 + MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 2 files changed, 13 insertions(+) diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 8f2df76c29a3..5d7067ee854e 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -181,6 +181,11 @@ RiscVSetSupervisorAddressTranslationRegister ( IN UINT64 ); +UINT64 +RiscVGetSupervisorAddressTranslationRegister ( + VOID + ); + UINT64 RiscVReadTimer ( VOID diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S index ac8f92f38aed..c9cf60c1664b 100644 --- a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S @@ -21,3 +21,11 @@ ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister) csrw CSR_SATP, a0 ret + +// +// Get the value of Supervisor Address Translation and +// Protection Register. +// +ASM_FUNC (RiscVGetSupervisorAddressTranslationRegister) +csrr a0, CSR_SATP +ret -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#105340): https://edk2.groups.io/g/devel/message/105340 Mute This Topic: https://groups.io/mt/99159993/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v3 0/7] RISC-V: MMU support
RISC-V: Add MMU support This series adds MMU support for RISC-V. Only SV39/48/57 modes are supported and tested. The MMU is required to support setting page attribute which is the first basic step to support security booting on RISC-V. There are three parts: 1. Add MMU base library. MMU will be enabled during CpuDxe initialization. 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base address to GCD if already done. 3. Fix all resources should be populated in HOB or added to GCD by driver before accessing when MMU enabled. All changes can be found in the branch tphan/riscv_mmu at: https://github.com/pttuan/edk2.git Changes in v3: - Move MMU library to UefiCpuPkg. - Add Andrei reviewed-by. Changes in v2: - Move MMU core to a library. - Setup SATP mode as highest possible that HW supports. Tuan Phan (7): MdePkg/BaseLib: RISC-V: Support getting satp register value MdePkg/Register: RISC-V: Add satp mode bits shift definition UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode OvmfPkg/RiscVVirt: Remove satp bare mode setting OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices MdePkg/Include/Library/BaseLib.h | 5 + .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + .../VirtNorFlashStaticLib.c | 3 +- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + OvmfPkg/RiscVVirt/Sec/Memory.c| 18 +- OvmfPkg/RiscVVirt/Sec/Platform.c | 62 ++ OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf| 2 + UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h | 39 ++ .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++ .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 26 + .../Library/BaseRiscVMmuLib/RiscVMmuCore.S| 31 + 16 files changed, 777 insertions(+), 31 deletions(-) create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#105339): https://edk2.groups.io/g/devel/message/105339 Mute This Topic: https://groups.io/mt/99159992/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH 5/7] OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists
On Thu, May 25, 2023 at 7:27 AM Ard Biesheuvel wrote:
> On Wed, 24 May 2023 at 20:13, Tuan Phan wrote:
> >
> >
> >
> > On Mon, Mar 6, 2023 at 9:53 AM Ard Biesheuvel wrote:
> >>
> >> On Mon, 6 Mar 2023 at 18:33, Tuan Phan wrote:
> >> >
> >> > The flash base address can be added to GCD before this driver run.
> >> > So only add it if it has not been done.
> >> >
> >>
> >> How do you end up in this situation?
> >>
> >> You cannot skip this registration, as it is required to get the region
> >> marked as EFI_MEMORY_RUNTIME, and without that, EFI variables will be
> >> broken when running under the OS.
> >
> >
> > Ard,
> > The patch only skips AddMemorySpace if it is already done in the early
> SEC phase for RiscV platform.
> > The EFI_MEMORY_RUNTIME always be set in the next line with
> SetMemorySpaceAttributes.
> >
>
> So how does the SEC phase create GCD regions to begin with?
>
> This really sounds like there is a problem elsewhere tbh.
>
The SEC phase just simply adds that region to the memory hob with
BuildResourceDescriptorHob.
Agree, the problem is VariableRuntimeDxe.efi accessing the region before
this VirtNorFlashDxe starts so when
MMU enabled, edk2 will hang due to page fault exception.
>
>
> >>
> >> > Signed-off-by: Tuan Phan
> >> > ---
> >> > OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25
> +++
> >> > 1 file changed, 16 insertions(+), 9 deletions(-)
> >> >
> >> > diff --git a/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
> b/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
> >> > index f9a41f6aab0f..8875824f 100644
> >> > --- a/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
> >> > +++ b/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
> >> > @@ -372,10 +372,11 @@ NorFlashFvbInitialize (
> >> >IN NOR_FLASH_INSTANCE *Instance
> >> >)
> >> > {
> >> > - EFI_STATUS Status;
> >> > - UINT32 FvbNumLba;
> >> > - EFI_BOOT_MODE BootMode;
> >> > - UINTN RuntimeMmioRegionSize;
> >> > + EFI_STATUS Status;
> >> > + UINT32 FvbNumLba;
> >> > + EFI_BOOT_MODE BootMode;
> >> > + UINTN RuntimeMmioRegionSize;
> >> > + EFI_GCD_MEMORY_SPACE_DESCRIPTOR Desc;
> >> >
> >> >DEBUG ((DEBUG_BLKIO, "NorFlashFvbInitialize\n"));
> >> >ASSERT ((Instance != NULL));
> >> > @@ -390,13 +391,19 @@ NorFlashFvbInitialize (
> >> >// is written as the base of the flash region (ie:
> Instance->DeviceBaseAddress)
> >> >RuntimeMmioRegionSize = (Instance->RegionBaseAddress -
> Instance->DeviceBaseAddress) + Instance->Size;
> >> >
> >> > - Status = gDS->AddMemorySpace (
> >> > - EfiGcdMemoryTypeMemoryMappedIo,
> >> > + Status = gDS->GetMemorySpaceDescriptor (
> >> >Instance->DeviceBaseAddress,
> >> > - RuntimeMmioRegionSize,
> >> > - EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
> >> > +
> >> >);
> >> > - ASSERT_EFI_ERROR (Status);
> >> > + if (Status == EFI_NOT_FOUND) {
> >> > +Status = gDS->AddMemorySpace (
> >> > +EfiGcdMemoryTypeMemoryMappedIo,
> >> > +Instance->DeviceBaseAddress,
> >> > +RuntimeMmioRegionSize,
> >> > +EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
> >> > +);
> >> > +ASSERT_EFI_ERROR (Status);
> >> > + }
> >> >
> >> >Status = gDS->SetMemorySpaceAttributes (
> >> >Instance->DeviceBaseAddress,
> >> > --
> >> > 2.25.1
> >> >
> >> >
> >> >
> >> >
> >> > Groups.io Links: You receive all messages sent to this group.
> >> > View/Reply Online (#100754):
> https://edk2.groups.io/g/devel/message/100754
> >> > Mute This Topic: https://groups.io/mt/97430554/1131722
> >> > Group Owner: devel+ow...@edk2.groups.io
> >> > Unsubscribe: https://edk2.groups.io/g/devel/unsub [a...@kernel.org]
> >> >
> >> >
> >> >
> >
> >
>
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Re: [edk2-devel] [PATCH v2 3/6] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
Agree it makes more sense to put the MMU library into UefiCpuPkg.
From: Ni, Ray
Date: Wednesday, May 24, 2023 at 2:52 AM
To: devel@edk2.groups.io , lic...@loongson.cn
, tp...@ventanamicro.com , Ard
Biesheuvel
Cc: Kinney, Michael D , Gao, Liming
, Liu, Zhiguang ,
suni...@ventanamicro.com , g...@danielschaefer.me
, Warkentin, Andrei
Subject: RE: [edk2-devel] [PATCH v2 3/6] UefiCpuPkg: RISC-V: Support MMU with
SV39/48/57 mode
X86 version is in UefiCpuPkg.
So be consistent, I would prefer the LoongArch64 version be in UefiCpuPkg as
well.
I know that ARM has similar code (I didn’t check in detail, +@Ard
Biesheuvel<mailto:a...@kernel.org>).
The trending is to abstract the memory attribute implementation behind
MemoryAttribute PPI/Protocol for using by other modules.
Thanks,
Ray
From: devel@edk2.groups.io On Behalf Of Chao Li
Sent: Wednesday, May 24, 2023 10:11 AM
To: devel@edk2.groups.io; tp...@ventanamicro.com
Cc: Kinney, Michael D ; Gao, Liming
; Liu, Zhiguang ;
suni...@ventanamicro.com; g...@danielschaefer.me; Warkentin, Andrei
; Ni, Ray
Subject: Re: [edk2-devel] [PATCH v2 3/6] UefiCpuPkg: RISC-V: Support MMU with
SV39/48/57 mode
Dear all,
I'm also porting MMU library of LoongArch64 to EDK2, I added it in to
UefiCpuPkg and make it possible to use the same headers for both the no-IA32
and no-X64 platforms, and I also saw that IA32 and X64 added the
CpuPageTableLib to UefiCpuPkg, this library are similar to MMU libraries. I
have a question, should the MMU library be in the MdePkg or UefiCpuPkg?
Thanks,
Chao
在 2023/4/15 02:58, Tuan Phan 写道:
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.
Signed-off-by: Tuan Phan <mailto:tp...@ventanamicro.com>
---
MdePkg/Include/Library/BaseRiscVMmuLib.h | 39 ++
.../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++
.../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 25 +
MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S | 31 +
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
OvmfPkg/RiscVVirt/Sec/Memory.c| 18 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf| 2 +
9 files changed, 678 insertions(+), 18 deletions(-)
create mode 100644 MdePkg/Include/Library/BaseRiscVMmuLib.h
create mode 100644 MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
create mode 100644 MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
create mode 100644 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
diff --git a/MdePkg/Include/Library/BaseRiscVMmuLib.h
b/MdePkg/Include/Library/BaseRiscVMmuLib.h
new file mode 100644
index ..f71d6a4a1e7b
--- /dev/null
+++ b/MdePkg/Include/Library/BaseRiscVMmuLib.h
@@ -0,0 +1,39 @@
+/** @file
+
+ Copyright (c) 2015 - 2016, Linaro Ltd. All rights reserved.
+ Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef BASE_RISCV_MMU_LIB_H_
+#define BASE_RISCV_MMU_LIB_H_
+
+VOID
+EFIAPI
+RiscVLocalTlbFlushAll (
+ VOID
+ );
+
+VOID
+EFIAPI
+RiscVLocalTlbFlush (
+ UINTN VirtAddr
+ );
+
+EFI_STATUS
+EFIAPI
+RiscVSetMemoryAttributes (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64Length,
+ IN UINT64Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+RiscVConfigureMmu (
+ VOID
+ );
+
+#endif /* BASE_RISCV_MMU_LIB_H_ */
diff --git a/MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
b/MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
new file mode 100644
index ..230f34261d8b
--- /dev/null
+++ b/MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
@@ -0,0 +1,569 @@
+/** @file
+* MMU implementation for RISC-V
+*
+* Copyright (c) 2011-2020, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+* Copyright (c) 2017, Intel Corporation. All rights reserved.
+* Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define RISCV_PG_V BIT0
+#define RISCV_PG_R BIT1
+#define RISCV_PG_W BIT2
+#define RISCV_PG_X BIT3
+#define RISCV_PG_G BIT5
+#define RISCV_PG_A BIT6
+#define RISCV_PG_D BIT7
+#define PTE_ATTRIBUTES_MASK 0xE
+
+#define PTE_PPN_MASK 0x3FFC00ULL
+#define PTE_PPN_SHIFT 10
+#define RISCV_MMU_PAGE_SHIFT 12
+
+STATIC UINTN mMaxRootTableLevel;
+STATIC UINTN mBitPerLevel;
+STATIC UINTN mTableEntryCount;
+
+STATIC
+BOOLEAN
+RiscVMmuEnabled (
+ VOID
+ )
+{
+ return ((RiscVGetSupervisorAddressTranslationRegister () &
+ SATP64_MODE) !
Re: [edk2-devel] [PATCH 5/7] OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists
On Mon, Mar 6, 2023 at 9:53 AM Ard Biesheuvel wrote:
> On Mon, 6 Mar 2023 at 18:33, Tuan Phan wrote:
> >
> > The flash base address can be added to GCD before this driver run.
> > So only add it if it has not been done.
> >
>
> How do you end up in this situation?
>
> You cannot skip this registration, as it is required to get the region
> marked as EFI_MEMORY_RUNTIME, and without that, EFI variables will be
> broken when running under the OS.
>
Ard,
The patch only skips AddMemorySpace if it is already done in the early SEC
phase for RiscV platform.
The EFI_MEMORY_RUNTIME always be set in the next line with
SetMemorySpaceAttributes.
> > Signed-off-by: Tuan Phan
> > ---
> > OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +++
> > 1 file changed, 16 insertions(+), 9 deletions(-)
> >
> > diff --git a/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
> b/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
> > index f9a41f6aab0f..8875824f 100644
> > --- a/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
> > +++ b/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
> > @@ -372,10 +372,11 @@ NorFlashFvbInitialize (
> >IN NOR_FLASH_INSTANCE *Instance
> >)
> > {
> > - EFI_STATUS Status;
> > - UINT32 FvbNumLba;
> > - EFI_BOOT_MODE BootMode;
> > - UINTN RuntimeMmioRegionSize;
> > + EFI_STATUS Status;
> > + UINT32 FvbNumLba;
> > + EFI_BOOT_MODE BootMode;
> > + UINTN RuntimeMmioRegionSize;
> > + EFI_GCD_MEMORY_SPACE_DESCRIPTOR Desc;
> >
> >DEBUG ((DEBUG_BLKIO, "NorFlashFvbInitialize\n"));
> >ASSERT ((Instance != NULL));
> > @@ -390,13 +391,19 @@ NorFlashFvbInitialize (
> >// is written as the base of the flash region (ie:
> Instance->DeviceBaseAddress)
> >RuntimeMmioRegionSize = (Instance->RegionBaseAddress -
> Instance->DeviceBaseAddress) + Instance->Size;
> >
> > - Status = gDS->AddMemorySpace (
> > - EfiGcdMemoryTypeMemoryMappedIo,
> > + Status = gDS->GetMemorySpaceDescriptor (
> >Instance->DeviceBaseAddress,
> > - RuntimeMmioRegionSize,
> > - EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
> > +
> >);
> > - ASSERT_EFI_ERROR (Status);
> > + if (Status == EFI_NOT_FOUND) {
> > +Status = gDS->AddMemorySpace (
> > +EfiGcdMemoryTypeMemoryMappedIo,
> > +Instance->DeviceBaseAddress,
> > +RuntimeMmioRegionSize,
> > +EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
> > +);
> > +ASSERT_EFI_ERROR (Status);
> > + }
> >
> >Status = gDS->SetMemorySpaceAttributes (
> >Instance->DeviceBaseAddress,
> > --
> > 2.25.1
> >
> >
> >
> >
> > Groups.io Links: You receive all messages sent to this group.
> > View/Reply Online (#100754):
> https://edk2.groups.io/g/devel/message/100754
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> >
> >
> >
>
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Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support
Thanks Andrei, Sunil, any comments or it is good to go. As this patchset spans across MdePkg, UefiCpuPkg and OvmfPkg, do I need to separate it so each package maintainer can merge independently? On Mon, May 8, 2023 at 10:19 AM Warkentin, Andrei < andrei.warken...@intel.com> wrote: > Apologies for the late review. I added my comments on GH. Aside from a > request for more context for > https://github.com/tianocore/edk2/commit/b7387dae40cc3a72562c6461d007d20087ab7414#comments, > I think this patch set from a functionality standpoint looks good enough to > be submitted. > > > > Reviewed-by: Andrei Warkentin > > > > *From:* devel@edk2.groups.io *On Behalf Of *Tuan > Phan > *Sent:* Wednesday, April 19, 2023 5:37 PM > *To:* devel@edk2.groups.io; Warkentin, Andrei > *Cc:* Kinney, Michael D ; Gao, Liming < > gaolim...@byosoft.com.cn>; Liu, Zhiguang ; > suni...@ventanamicro.com; g...@danielschaefer.me > *Subject:* Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support > > > > Hi Andrei, > > Here you go: https://github.com/pttuan/edk2/tree/tphan/riscv_mmu > > Will put the link in the cover letter next round. > > > > *From: *devel@edk2.groups.io on behalf of Andrei > Warkentin > *Date: *Tuesday, April 18, 2023 at 9:04 AM > *To: *Tuan Phan , devel@edk2.groups.io < > devel@edk2.groups.io> > *Cc: *Kinney, Michael D , Gao, Liming < > gaolim...@byosoft.com.cn>, Liu, Zhiguang , > suni...@ventanamicro.com , g...@danielschaefer.me > > *Subject: *Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support > > Hi Tuan, > > Do you mind sharing the GitHub branch as well? It would help with the > review immensely. > > A > > > -Original Message- > > From: Tuan Phan > > Sent: Friday, April 14, 2023 1:58 PM > > To: devel@edk2.groups.io > > Cc: Kinney, Michael D ; Gao, Liming > > ; Liu, Zhiguang ; > > suni...@ventanamicro.com; g...@danielschaefer.me; Warkentin, Andrei > > ; Tuan Phan > > Subject: [PATCH v2 0/6] RISC-V MMU support > > > > RISC-V: Add MMU support > > > > This series adds MMU support for RISC-V. Only SV39/48/57 modes are > > supported and tested. The MMU is required to support setting page > > attribute which is the first basic step to support security booting on > RISC-V. > > > > There are three parts: > > 1. Add MMU base library. MMU will be enabled during CpuDxe > initialization. > > 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base address to > GCD > > if already done. > > 3. Fix all resources should be populated in HOB or added to GCD by driver > > before accessing when MMU enabled. > > > > Changes in v2: > > - Move MMU core to a library. > > - Setup SATP mode as highest possible that HW supports. > > > > Tuan Phan (6): > > MdePkg/BaseLib: RISC-V: Support getting satp register value > > MdePkg/Register: RISC-V: Add satp mode bits shift definition > > UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode > > OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size > > OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists > > OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform > > devices > > > > MdePkg/Include/Library/BaseLib.h | 5 + > > MdePkg/Include/Library/BaseRiscVMmuLib.h | 39 ++ > > .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- > > MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + > > .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 > > ++ > > .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 25 + > > MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S | 31 + > > .../VirtNorFlashStaticLib.c | 3 +- > > OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + > > OvmfPkg/RiscVVirt/Sec/Memory.c| 18 +- > > OvmfPkg/RiscVVirt/Sec/Platform.c | 62 ++ > > OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + > > OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +- > > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +- > > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 + > > UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf| 2 + > > 16 files changed, 776 insertions(+), 31 deletions(-) create mode 100644 > > MdePkg/Include/Library/BaseRiscVMmuLib.h > > create mode 100644 > > MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > > create mode 100644 > > MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > > create mode 100644 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S > > > > -- > > 2.25.1 > > > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#105207): https://edk2.groups.io/g/devel/message/105207 Mute This Topic: https://groups.io/mt/98269071/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support
Hi Andrei, Here you go: https://github.com/pttuan/edk2/tree/tphan/riscv_mmu Will put the link in the cover letter next round. From: devel@edk2.groups.io on behalf of Andrei Warkentin Date: Tuesday, April 18, 2023 at 9:04 AM To: Tuan Phan , devel@edk2.groups.io Cc: Kinney, Michael D , Gao, Liming , Liu, Zhiguang , suni...@ventanamicro.com , g...@danielschaefer.me Subject: Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support Hi Tuan, Do you mind sharing the GitHub branch as well? It would help with the review immensely. A > -Original Message- > From: Tuan Phan > Sent: Friday, April 14, 2023 1:58 PM > To: devel@edk2.groups.io > Cc: Kinney, Michael D ; Gao, Liming > ; Liu, Zhiguang ; > suni...@ventanamicro.com; g...@danielschaefer.me; Warkentin, Andrei > ; Tuan Phan > Subject: [PATCH v2 0/6] RISC-V MMU support > > RISC-V: Add MMU support > > This series adds MMU support for RISC-V. Only SV39/48/57 modes are > supported and tested. The MMU is required to support setting page > attribute which is the first basic step to support security booting on RISC-V. > > There are three parts: > 1. Add MMU base library. MMU will be enabled during CpuDxe initialization. > 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base address to GCD > if already done. > 3. Fix all resources should be populated in HOB or added to GCD by driver > before accessing when MMU enabled. > > Changes in v2: > - Move MMU core to a library. > - Setup SATP mode as highest possible that HW supports. > > Tuan Phan (6): > MdePkg/BaseLib: RISC-V: Support getting satp register value > MdePkg/Register: RISC-V: Add satp mode bits shift definition > UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode > OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size > OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists > OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform > devices > > MdePkg/Include/Library/BaseLib.h | 5 + > MdePkg/Include/Library/BaseRiscVMmuLib.h | 39 ++ > .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- > MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + > .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 > ++ > .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 25 + > MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S | 31 + > .../VirtNorFlashStaticLib.c | 3 +- > OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + > OvmfPkg/RiscVVirt/Sec/Memory.c| 18 +- > OvmfPkg/RiscVVirt/Sec/Platform.c | 62 ++ > OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + > OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +- > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +- > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 + > UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf| 2 + > 16 files changed, 776 insertions(+), 31 deletions(-) create mode 100644 > MdePkg/Include/Library/BaseRiscVMmuLib.h > create mode 100644 > MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > create mode 100644 > MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > create mode 100644 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S > > -- > 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103261): https://edk2.groups.io/g/devel/message/103261 Mute This Topic: https://groups.io/mt/98269071/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v2 5/6] OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists
The flash base address can be added to GCD before this driver run.
So only add it if it has not been done.
Signed-off-by: Tuan Phan
---
OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +++
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
b/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
index 6b9ef261335e..bbd1697a51dd 100644
--- a/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
+++ b/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
@@ -372,10 +372,11 @@ NorFlashFvbInitialize (
IN NOR_FLASH_INSTANCE *Instance
)
{
- EFI_STATUS Status;
- UINT32 FvbNumLba;
- EFI_BOOT_MODE BootMode;
- UINTN RuntimeMmioRegionSize;
+ EFI_STATUS Status;
+ UINT32 FvbNumLba;
+ EFI_BOOT_MODE BootMode;
+ UINTN RuntimeMmioRegionSize;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR Desc;
DEBUG ((DEBUG_BLKIO, "NorFlashFvbInitialize\n"));
ASSERT ((Instance != NULL));
@@ -390,13 +391,19 @@ NorFlashFvbInitialize (
// is written as the base of the flash region (ie:
Instance->DeviceBaseAddress)
RuntimeMmioRegionSize = (Instance->RegionBaseAddress -
Instance->DeviceBaseAddress) + Instance->Size;
- Status = gDS->AddMemorySpace (
- EfiGcdMemoryTypeMemoryMappedIo,
+ Status = gDS->GetMemorySpaceDescriptor (
Instance->DeviceBaseAddress,
- RuntimeMmioRegionSize,
- EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+
);
- ASSERT_EFI_ERROR (Status);
+ if (Status == EFI_NOT_FOUND) {
+Status = gDS->AddMemorySpace (
+EfiGcdMemoryTypeMemoryMappedIo,
+Instance->DeviceBaseAddress,
+RuntimeMmioRegionSize,
+EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+);
+ASSERT_EFI_ERROR (Status);
+ }
Status = gDS->SetMemorySpaceAttributes (
Instance->DeviceBaseAddress,
--
2.25.1
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[edk2-devel] [PATCH v2 6/6] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices
Normally, DXE driver would add device resource to GCD before start using.
But some key resources such as uart, flash base address are being accessing
directly in some core modules.
Those resources should be populated to HOB in SEC phase so they are
added to GCD before anyone can access them.
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/Sec/Platform.c | 62 +++
OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 +
2 files changed, 63 insertions(+)
diff --git a/OvmfPkg/RiscVVirt/Sec/Platform.c b/OvmfPkg/RiscVVirt/Sec/Platform.c
index 3645c27b0b12..944b82c84a6e 100644
--- a/OvmfPkg/RiscVVirt/Sec/Platform.c
+++ b/OvmfPkg/RiscVVirt/Sec/Platform.c
@@ -21,6 +21,63 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include
#include
+/**
+ Build memory map I/O range resource HOB using the
+ base address and size.
+
+ @param MemoryBase Memory map I/O base.
+ @param MemorySize Memory map I/O size.
+
+**/
+STATIC
+VOID
+AddIoMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64MemorySize
+ )
+{
+ /* Align to EFI_PAGE_SIZE */
+ MemorySize = ALIGN_VALUE (MemorySize, EFI_PAGE_SIZE);
+ BuildResourceDescriptorHob (
+EFI_RESOURCE_MEMORY_MAPPED_IO,
+EFI_RESOURCE_ATTRIBUTE_PRESENT |
+EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+EFI_RESOURCE_ATTRIBUTE_TESTED,
+MemoryBase,
+MemorySize
+);
+}
+
+/**
+ Populate IO resources from FDT that not added to GCD by its
+ driver in the DXE phase.
+
+ @param FdtBase Fdt base address
+ @param CompatibleCompatible string
+
+**/
+STATIC
+VOID
+PopulateIoResources (
+ VOID *FdtBase,
+ CONST CHAR8* Compatible
+ )
+{
+ UINT64 *Reg;
+ INT32 Node, LenP;
+
+ Node = fdt_node_offset_by_compatible (FdtBase, -1, Compatible);
+ while (Node != -FDT_ERR_NOTFOUND) {
+Reg = (UINT64 *)fdt_getprop (FdtBase, Node, "reg", );
+if (Reg) {
+ ASSERT (LenP == (2 * sizeof (UINT64)));
+ AddIoMemoryBaseSizeHob (SwapBytes64 (Reg[0]), SwapBytes64 (Reg[1]));
+}
+Node = fdt_node_offset_by_compatible (FdtBase, Node, Compatible);
+ }
+}
+
/**
@retval EFI_SUCCESSThe address of FDT is passed in HOB.
EFI_UNSUPPORTEDCan't locate FDT.
@@ -80,5 +137,10 @@ PlatformPeimInitialization (
BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32 (PcdOvmfDxeMemFvSize));
+ PopulateIoResources (Base, "ns16550a");
+ PopulateIoResources (Base, "qemu,fw-cfg-mmio");
+ PopulateIoResources (Base, "virtio,mmio");
+ AddIoMemoryBaseSizeHob (PcdGet32 (PcdOvmfFdBaseAddress), PcdGet32
(PcdOvmfFirmwareFdSize));
+
return EFI_SUCCESS;
}
diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf
b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
index aed35d3af596..e1f562264eea 100644
--- a/OvmfPkg/RiscVVirt/Sec/SecMain.inf
+++ b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
@@ -61,6 +61,7 @@
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize
[Guids]
gFdtHobGuid
--
2.25.1
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[edk2-devel] [PATCH v2 4/6] OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size
The size should be for single region, not the whole firmware FD.
Signed-off-by: Tuan Phan
---
.../Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c| 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
index fdc2ccb6294e..33f3a01b06f4 100644
--- a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
+++ b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
@@ -24,7 +24,8 @@ VIRT_NOR_FLASH_DESCRIPTION mNorFlashDevice =
{
FixedPcdGet32 (PcdOvmfFdBaseAddress),
FixedPcdGet64 (PcdFlashNvStorageVariableBase),
- FixedPcdGet32 (PcdOvmfFirmwareFdSize),
+ FixedPcdGet32 (PcdOvmfFirmwareFdSize) -
+ (FixedPcdGet64 (PcdFlashNvStorageVariableBase) - FixedPcdGet32
(PcdOvmfFdBaseAddress)),
QEMU_NOR_BLOCK_SIZE
};
--
2.25.1
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[edk2-devel] [PATCH v2 3/6] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.
Signed-off-by: Tuan Phan
---
MdePkg/Include/Library/BaseRiscVMmuLib.h | 39 ++
.../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++
.../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 25 +
MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S | 31 +
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
OvmfPkg/RiscVVirt/Sec/Memory.c| 18 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf| 2 +
9 files changed, 678 insertions(+), 18 deletions(-)
create mode 100644 MdePkg/Include/Library/BaseRiscVMmuLib.h
create mode 100644 MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
create mode 100644 MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
create mode 100644 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
diff --git a/MdePkg/Include/Library/BaseRiscVMmuLib.h
b/MdePkg/Include/Library/BaseRiscVMmuLib.h
new file mode 100644
index ..f71d6a4a1e7b
--- /dev/null
+++ b/MdePkg/Include/Library/BaseRiscVMmuLib.h
@@ -0,0 +1,39 @@
+/** @file
+
+ Copyright (c) 2015 - 2016, Linaro Ltd. All rights reserved.
+ Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef BASE_RISCV_MMU_LIB_H_
+#define BASE_RISCV_MMU_LIB_H_
+
+VOID
+EFIAPI
+RiscVLocalTlbFlushAll (
+ VOID
+ );
+
+VOID
+EFIAPI
+RiscVLocalTlbFlush (
+ UINTN VirtAddr
+ );
+
+EFI_STATUS
+EFIAPI
+RiscVSetMemoryAttributes (
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64Length,
+ IN UINT64Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+RiscVConfigureMmu (
+ VOID
+ );
+
+#endif /* BASE_RISCV_MMU_LIB_H_ */
diff --git a/MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
b/MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
new file mode 100644
index ..230f34261d8b
--- /dev/null
+++ b/MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
@@ -0,0 +1,569 @@
+/** @file
+* MMU implementation for RISC-V
+*
+* Copyright (c) 2011-2020, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+* Copyright (c) 2017, Intel Corporation. All rights reserved.
+* Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define RISCV_PG_V BIT0
+#define RISCV_PG_R BIT1
+#define RISCV_PG_W BIT2
+#define RISCV_PG_X BIT3
+#define RISCV_PG_G BIT5
+#define RISCV_PG_A BIT6
+#define RISCV_PG_D BIT7
+#define PTE_ATTRIBUTES_MASK 0xE
+
+#define PTE_PPN_MASK 0x3FFC00ULL
+#define PTE_PPN_SHIFT 10
+#define RISCV_MMU_PAGE_SHIFT 12
+
+STATIC UINTN mMaxRootTableLevel;
+STATIC UINTN mBitPerLevel;
+STATIC UINTN mTableEntryCount;
+
+STATIC
+BOOLEAN
+RiscVMmuEnabled (
+ VOID
+ )
+{
+ return ((RiscVGetSupervisorAddressTranslationRegister () &
+ SATP64_MODE) != (SATP_MODE_OFF << SATP64_MODE_SHIFT));
+}
+
+STATIC
+UINTN
+RiscVGetRootTranslateTable (
+ VOID
+ )
+{
+ return (RiscVGetSupervisorAddressTranslationRegister () & SATP64_PPN) <<
+ RISCV_MMU_PAGE_SHIFT;
+}
+
+STATIC
+BOOLEAN
+IsValidPte (
+ IN UINTN Entry
+ )
+{
+ if (!(Entry & RISCV_PG_V) ||
+ (((Entry & (RISCV_PG_R | RISCV_PG_W)) == RISCV_PG_W)))
+ {
+return FALSE;
+ }
+
+ return TRUE;
+}
+
+STATIC
+UINTN
+SetValidPte (
+ IN UINTN Entry
+ )
+{
+ /* Set Valid and Global mapping bits */
+ return Entry | RISCV_PG_G | RISCV_PG_V;
+}
+
+STATIC
+BOOLEAN
+IsBlockEntry (
+ IN UINTN Entry
+ )
+{
+ return IsValidPte (Entry) &&
+ (Entry & (RISCV_PG_X | RISCV_PG_R));
+}
+
+STATIC
+BOOLEAN
+IsTableEntry (
+ IN UINTN Entry
+ )
+{
+ return IsValidPte (Entry) &&
+ !IsBlockEntry (Entry);
+}
+
+STATIC
+UINTN
+SetTableEntry (
+ IN UINTN Entry
+ )
+{
+ Entry = SetValidPte (Entry);
+ Entry &= ~(RISCV_PG_X | RISCV_PG_W | RISCV_PG_R);
+
+ return Entry;
+}
+
+STATIC
+VOID
+ReplaceTableEntry (
+ IN UINTN*Entry,
+ IN UINTNValue,
+ IN UINTNRegionStart,
+ IN BOOLEAN IsLiveBlockMapping
+ )
+{
+ *Entry = Value;
+
+ if (IsLiveBlockMapping && RiscVMmuEnabled ()) {
+RiscVLocalTlbFlush (RegionStart);
+ }
+}
+
+STATIC
+UINTN
+GetPpnfromPte (
+ UINTN Entry,
+ UINTN Level
+ )
+{
+ return ((Entry & PTE_PPN_MASK) >> PTE_PPN_SHIFT);
+}
+
+STATIC
+UINTN
+SetPpnToPte (
+ UINTN Entry,
+ UINTN Address,
+ UINTN Level
+ )
+{
+ UINTN Ppn;
+
+ Ppn = ((Address >> RISCV_MMU_PAGE_SHIFT) << PTE_PPN_SHIFT);
+ ASSERT (~(Ppn & ~PTE_PPN_MASK));
+ Entry &= ~PTE_PPN_MASK;
+ return
[edk2-devel] [PATCH v2 2/6] MdePkg/Register: RISC-V: Add satp mode bits shift definition
The satp mode bits shift is used cross modules. It should be defined in one place. Signed-off-by: Tuan Phan --- MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h index 5c2989b797bf..2bde8db478ff 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -58,9 +58,10 @@ #define PRV_S 1UL #define PRV_M 3UL -#define SATP64_MODE 0xF000ULL -#define SATP64_ASID 0x0000ULL -#define SATP64_PPN 0x0FFFULL +#define SATP64_MODE0xF000ULL +#define SATP64_MODE_SHIFT 60 +#define SATP64_ASID0x0000ULL +#define SATP64_PPN 0x0FFFULL #define SATP_MODE_OFF 0UL #define SATP_MODE_SV32 1UL -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103017): https://edk2.groups.io/g/devel/message/103017 Mute This Topic: https://groups.io/mt/98269075/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v2 1/6] MdePkg/BaseLib: RISC-V: Support getting satp register value
Add an API to retrieve satp register value. Signed-off-by: Tuan Phan --- MdePkg/Include/Library/BaseLib.h | 5 + MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 2 files changed, 13 insertions(+) diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 8f2df76c29a3..5d7067ee854e 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -181,6 +181,11 @@ RiscVSetSupervisorAddressTranslationRegister ( IN UINT64 ); +UINT64 +RiscVGetSupervisorAddressTranslationRegister ( + VOID + ); + UINT64 RiscVReadTimer ( VOID diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S index ac8f92f38aed..c9cf60c1664b 100644 --- a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S @@ -21,3 +21,11 @@ ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister) csrw CSR_SATP, a0 ret + +// +// Get the value of Supervisor Address Translation and +// Protection Register. +// +ASM_FUNC (RiscVGetSupervisorAddressTranslationRegister) +csrr a0, CSR_SATP +ret -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103016): https://edk2.groups.io/g/devel/message/103016 Mute This Topic: https://groups.io/mt/98269072/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v2 0/6] RISC-V MMU support
RISC-V: Add MMU support This series adds MMU support for RISC-V. Only SV39/48/57 modes are supported and tested. The MMU is required to support setting page attribute which is the first basic step to support security booting on RISC-V. There are three parts: 1. Add MMU base library. MMU will be enabled during CpuDxe initialization. 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base address to GCD if already done. 3. Fix all resources should be populated in HOB or added to GCD by driver before accessing when MMU enabled. Changes in v2: - Move MMU core to a library. - Setup SATP mode as highest possible that HW supports. Tuan Phan (6): MdePkg/BaseLib: RISC-V: Support getting satp register value MdePkg/Register: RISC-V: Add satp mode bits shift definition UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices MdePkg/Include/Library/BaseLib.h | 5 + MdePkg/Include/Library/BaseRiscVMmuLib.h | 39 ++ .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++ .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 25 + MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S | 31 + .../VirtNorFlashStaticLib.c | 3 +- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + OvmfPkg/RiscVVirt/Sec/Memory.c| 18 +- OvmfPkg/RiscVVirt/Sec/Platform.c | 62 ++ OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf| 2 + 16 files changed, 776 insertions(+), 31 deletions(-) create mode 100644 MdePkg/Include/Library/BaseRiscVMmuLib.h create mode 100644 MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c create mode 100644 MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf create mode 100644 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103015): https://edk2.groups.io/g/devel/message/103015 Mute This Topic: https://groups.io/mt/98269071/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH 0/7] RISC-V: Add MMU support
Hi Andrei, Here it is: https://github.com/pttuan/edk2/tree/tphan/riscv_mmu On Thu, Mar 9, 2023 at 1:34 PM Warkentin, Andrei wrote: > Hi Tuan, > > > > Could you share a GitHub link to a branch with the patch set? Somehow my > email client is mangling one of your patches where it’s all one giant line > of code. > > > > A > > > > *From:* Tuan Phan > *Sent:* Thursday, March 9, 2023 1:20 PM > *To:* devel@edk2.groups.io > *Cc:* Kinney, Michael D ; Gao, Liming < > gaolim...@byosoft.com.cn>; Liu, Zhiguang ; > suni...@ventanamicro.com; g...@danielschaefer.me; Warkentin, Andrei < > andrei.warken...@intel.com> > *Subject:* RE: [PATCH 0/7] RISC-V: Add MMU support > > > > Hi All, > > Any updates on this series? > > > > Thanks, > > > > *From: *Tuan Phan > *Sent: *Monday, March 6, 2023 9:33 AM > *To: *devel@edk2.groups.io > *Cc: *michael.d.kin...@intel.com; gaolim...@byosoft.com.cn; > zhiguang@intel.com; suni...@ventanamicro.com; g...@danielschaefer.me; > andrei.warken...@intel.com; Tuan Phan > *Subject: *[PATCH 0/7] RISC-V: Add MMU support > > > > This series adds MMU support for RISC-V. Only SV39/48/57 modes > > are supported and tested. The MMU is required to support setting > > page attribute which is the first basic step to support security > > booting on RISC-V. > > > > There are three parts: > > 1. Add MMU core to UefiCpuPkg. MMU will be enabled during > > CpuDxe initialization. > > 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base > > address to GCD if already done. > > 3. Enable MMU for RiscVVirt platform and populating its device > > resources in SEC phase. All resources should be populated in HOB > > or added to GCD by driver before accessing them when MMU enabled. > > > > Tuan Phan (7): > > MdePkg/BaseLib: RISC-V: Support getting satp register value > > MdePkg/Register: RISC-V: Add satp mode bits shift definition > > UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode > > OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size > > OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists > > OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform > > devices > > OvmfPkg/RiscVVirt: Enable MMU with SV39 mode > > > > MdePkg/Include/Library/BaseLib.h | 5 + > > .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- > > MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + > > .../VirtNorFlashStaticLib.c | 3 +- > > OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + > > OvmfPkg/RiscVVirt/Sec/Memory.c| 17 - > > OvmfPkg/RiscVVirt/Sec/Platform.c | 62 +++ > > OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + > > OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +- > > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 10 +- > > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 1 + > > UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf| 5 + > > UefiCpuPkg/CpuDxeRiscV64/Mmu.c| 493 ++ > > UefiCpuPkg/CpuDxeRiscV64/Mmu.h| 33 ++ > > UefiCpuPkg/CpuDxeRiscV64/MmuCore.S| 29 ++ > > UefiCpuPkg/UefiCpuPkg.dec | 8 + > > 16 files changed, 676 insertions(+), 32 deletions(-) > > create mode 100644 UefiCpuPkg/CpuDxeRiscV64/Mmu.c > > create mode 100644 UefiCpuPkg/CpuDxeRiscV64/Mmu.h > > create mode 100644 UefiCpuPkg/CpuDxeRiscV64/MmuCore.S > > > > -- > > 2.25.1 > > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101037): https://edk2.groups.io/g/devel/message/101037 Mute This Topic: https://groups.io/mt/97430547/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH v2] MdePkg/BaseCacheMaintenanceLib: RISC-V: Fix instruction cache not been invalidated
When the range instruction cache invalidating not supported, the whole
instruction cache should be invalidated instead.
Signed-off-by: Tuan Phan
---
V2:
- Format with uncrustify.
MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index 67a3387ff3c6..09de53fb5687 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -76,7 +76,12 @@ InvalidateInstructionCacheRange (
IN UINTN Length
)
{
- DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
+ DEBUG (
+ (DEBUG_WARN,
+ "%a:RISC-V unsupported function.\n"
+ "Invalidating the whole instruction cache instead.\n", __func__)
+ );
+ InvalidateInstructionCache ();
return Address;
}
--
2.25.1
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Re: [edk2-devel] [PATCH 0/7] RISC-V: Add MMU support
Hi All,Any updates on this series? Thanks, From: Tuan PhanSent: Monday, March 6, 2023 9:33 AMTo: devel@edk2.groups.ioCc: michael.d.kin...@intel.com; gaolim...@byosoft.com.cn; zhiguang@intel.com; suni...@ventanamicro.com; g...@danielschaefer.me; andrei.warken...@intel.com; Tuan PhanSubject: [PATCH 0/7] RISC-V: Add MMU support This series adds MMU support for RISC-V. Only SV39/48/57 modesare supported and tested. The MMU is required to support settingpage attribute which is the first basic step to support securitybooting on RISC-V. There are three parts:1. Add MMU core to UefiCpuPkg. MMU will be enabled duringCpuDxe initialization.2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash baseaddress to GCD if already done.3. Enable MMU for RiscVVirt platform and populating its deviceresources in SEC phase. All resources should be populated in HOBor added to GCD by driver before accessing them when MMU enabled. Tuan Phan (7): MdePkg/BaseLib: RISC-V: Support getting satp register value MdePkg/Register: RISC-V: Add satp mode bits shift definition UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices OvmfPkg/RiscVVirt: Enable MMU with SV39 mode MdePkg/Include/Library/BaseLib.h | 5 + .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + .../VirtNorFlashStaticLib.c | 3 +- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + OvmfPkg/RiscVVirt/Sec/Memory.c | 17 - OvmfPkg/RiscVVirt/Sec/Platform.c | 62 +++ OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 10 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 1 + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 5 + UefiCpuPkg/CpuDxeRiscV64/Mmu.c | 493 ++ UefiCpuPkg/CpuDxeRiscV64/Mmu.h | 33 ++ UefiCpuPkg/CpuDxeRiscV64/MmuCore.S | 29 ++ UefiCpuPkg/UefiCpuPkg.dec | 8 + 16 files changed, 676 insertions(+), 32 deletions(-) create mode 100644 UefiCpuPkg/CpuDxeRiscV64/Mmu.c create mode 100644 UefiCpuPkg/CpuDxeRiscV64/Mmu.h create mode 100644 UefiCpuPkg/CpuDxeRiscV64/MmuCore.S -- 2.25.1 _._,_._,_ Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100962) | | Mute This Topic | New Topic Your Subscription | Contact Group Owner | Unsubscribe [arch...@mail-archive.com] _._,_._,_
Re: [edk2-devel] [PATCH] MdePkg/BaseCacheMaintenanceLib: RISC-V: Fix instruction cache not been invalidated
Hi All,Any updates on this patch? Thanks, From: Tuan Phan via groups.ioSent: Monday, March 6, 2023 9:11 AMTo: devel@edk2.groups.ioCc: michael.d.kin...@intel.com; gaolim...@byosoft.com.cn; zhiguang@intel.com; suni...@ventanamicro.com; g...@danielschaefer.me; Tuan PhanSubject: [edk2-devel] [PATCH] MdePkg/BaseCacheMaintenanceLib: RISC-V: Fix instruction cache not been invalidated When the range instruction cache invalidating not supported, the wholeinstruction cache should be invalidated instead. Signed-off-by: Tuan Phan --- MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.cindex 67a3387ff3c6..a744b2a6f889 100644--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c@@ -76,7 +76,10 @@ InvalidateInstructionCacheRange ( IN UINTN Length ) { - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); + DEBUG ((DEBUG_WARN, + "%a:RISC-V unsupported function.\n" + "Invalidating the whole instruction cache instead.\n", __func__)); + InvalidateInstructionCache (); return Address; } -- 2.25.1 -=-=-=-=-=-=Groups.io Links: You receive all messages sent to this group.View/Reply Online (#100744): https://edk2.groups.io/g/devel/message/100744Mute This Topic: https://groups.io/mt/97429987/7027451Group Owner: devel+ow...@edk2.groups.ioUnsubscribe: https://edk2.groups.io/g/devel/unsub [tp...@ventanamicro.com]-=-=-=-=-=-=
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[edk2-devel] [PATCH 7/7] OvmfPkg/RiscVVirt: Enable MMU with SV39 mode
As MMU will be enabled in CpuDxe, remove the code that set up satp
mode in SEC phase.
Enable SV39 as default mode.
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
OvmfPkg/RiscVVirt/Sec/Memory.c | 17 -
2 files changed, 1 insertion(+), 17 deletions(-)
diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
index 731f54f73f81..ef268481ca07 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
+++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
@@ -207,6 +207,7 @@
gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|1000
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVSatpMode|8
# DEBUG_ASSERT_ENABLED 0x01
# DEBUG_PRINT_ENABLED0x02
diff --git a/OvmfPkg/RiscVVirt/Sec/Memory.c b/OvmfPkg/RiscVVirt/Sec/Memory.c
index 70935b07b56b..0b589cd1d071 100644
--- a/OvmfPkg/RiscVVirt/Sec/Memory.c
+++ b/OvmfPkg/RiscVVirt/Sec/Memory.c
@@ -110,21 +110,6 @@ AddMemoryRangeHob (
AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
}
-/**
- Configure MMU
-**/
-STATIC
-VOID
-InitMmu (
- )
-{
- //
- // Set supervisor translation mode to Bare mode
- //
- RiscVSetSupervisorAddressTranslationRegister ((UINT64)SATP_MODE_OFF << 60);
- DEBUG ((DEBUG_INFO, "%a: Set Supervisor address mode to bare-metal mode.\n",
__FUNCTION__));
-}
-
/**
Publish system RAM and reserve memory regions.
@@ -255,8 +240,6 @@ MemoryPeimInitialization (
}
}
- InitMmu ();
-
BuildMemoryTypeInformationHob ();
return EFI_SUCCESS;
--
2.25.1
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[edk2-devel] [PATCH 6/7] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices
Normally, DXE driver would add device resource to GCD before start using.
But some key resources such as uart, flash base address are being accessing
directly in some core modules.
Those resources should be populated to HOB in SEC phase so they are
added to GCD before anyone can access them.
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/Sec/Platform.c | 62 +++
OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 +
2 files changed, 63 insertions(+)
diff --git a/OvmfPkg/RiscVVirt/Sec/Platform.c b/OvmfPkg/RiscVVirt/Sec/Platform.c
index e8fd126cf800..63bc21eb3f60 100644
--- a/OvmfPkg/RiscVVirt/Sec/Platform.c
+++ b/OvmfPkg/RiscVVirt/Sec/Platform.c
@@ -21,6 +21,63 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include
#include
+/**
+ Build memory map I/O range resource HOB using the
+ base address and size.
+
+ @param MemoryBase Memory map I/O base.
+ @param MemorySize Memory map I/O size.
+
+**/
+STATIC
+VOID
+AddIoMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64MemorySize
+ )
+{
+ /* Align to EFI_PAGE_SIZE */
+ MemorySize = ALIGN_VALUE (MemorySize, EFI_PAGE_SIZE);
+ BuildResourceDescriptorHob (
+EFI_RESOURCE_MEMORY_MAPPED_IO,
+EFI_RESOURCE_ATTRIBUTE_PRESENT |
+EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+EFI_RESOURCE_ATTRIBUTE_TESTED,
+MemoryBase,
+MemorySize
+);
+}
+
+/**
+ Populate IO resources from FDT that not added to GCD by its
+ driver in the DXE phase.
+
+ @param FdtBase Fdt base address
+ @param CompatibleCompatible string
+
+**/
+STATIC
+VOID
+PopulateIoResources (
+ VOID *FdtBase,
+ CONST CHAR8* Compatible
+ )
+{
+ UINT64 *Reg;
+ INT32 Node, LenP;
+
+ Node = fdt_node_offset_by_compatible (FdtBase, -1, Compatible);
+ while (Node != -FDT_ERR_NOTFOUND) {
+Reg = (UINT64 *)fdt_getprop (FdtBase, Node, "reg", );
+if (Reg) {
+ ASSERT (LenP == (2 * sizeof (UINT64)));
+ AddIoMemoryBaseSizeHob (SwapBytes64 (Reg[0]), SwapBytes64 (Reg[1]));
+}
+Node = fdt_node_offset_by_compatible (FdtBase, Node, Compatible);
+ }
+}
+
/**
@retval EFI_SUCCESSThe address of FDT is passed in HOB.
EFI_UNSUPPORTEDCan't locate FDT.
@@ -80,5 +137,10 @@ PlatformPeimInitialization (
BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32 (PcdOvmfDxeMemFvSize));
+ PopulateIoResources (Base, "ns16550a");
+ PopulateIoResources (Base, "qemu,fw-cfg-mmio");
+ PopulateIoResources (Base, "virtio,mmio");
+ AddIoMemoryBaseSizeHob (PcdGet32 (PcdOvmfFdBaseAddress), PcdGet32
(PcdOvmfFirmwareFdSize));
+
return EFI_SUCCESS;
}
diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf
b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
index aed35d3af596..e1f562264eea 100644
--- a/OvmfPkg/RiscVVirt/Sec/SecMain.inf
+++ b/OvmfPkg/RiscVVirt/Sec/SecMain.inf
@@ -61,6 +61,7 @@
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize
[Guids]
gFdtHobGuid
--
2.25.1
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[edk2-devel] [PATCH 5/7] OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists
The flash base address can be added to GCD before this driver run.
So only add it if it has not been done.
Signed-off-by: Tuan Phan
---
OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +++
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
b/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
index f9a41f6aab0f..8875824f 100644
--- a/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
+++ b/OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c
@@ -372,10 +372,11 @@ NorFlashFvbInitialize (
IN NOR_FLASH_INSTANCE *Instance
)
{
- EFI_STATUS Status;
- UINT32 FvbNumLba;
- EFI_BOOT_MODE BootMode;
- UINTN RuntimeMmioRegionSize;
+ EFI_STATUS Status;
+ UINT32 FvbNumLba;
+ EFI_BOOT_MODE BootMode;
+ UINTN RuntimeMmioRegionSize;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR Desc;
DEBUG ((DEBUG_BLKIO, "NorFlashFvbInitialize\n"));
ASSERT ((Instance != NULL));
@@ -390,13 +391,19 @@ NorFlashFvbInitialize (
// is written as the base of the flash region (ie:
Instance->DeviceBaseAddress)
RuntimeMmioRegionSize = (Instance->RegionBaseAddress -
Instance->DeviceBaseAddress) + Instance->Size;
- Status = gDS->AddMemorySpace (
- EfiGcdMemoryTypeMemoryMappedIo,
+ Status = gDS->GetMemorySpaceDescriptor (
Instance->DeviceBaseAddress,
- RuntimeMmioRegionSize,
- EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+
);
- ASSERT_EFI_ERROR (Status);
+ if (Status == EFI_NOT_FOUND) {
+Status = gDS->AddMemorySpace (
+EfiGcdMemoryTypeMemoryMappedIo,
+Instance->DeviceBaseAddress,
+RuntimeMmioRegionSize,
+EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+);
+ASSERT_EFI_ERROR (Status);
+ }
Status = gDS->SetMemorySpaceAttributes (
Instance->DeviceBaseAddress,
--
2.25.1
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[edk2-devel] [PATCH 4/7] OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size
The size should be for single region, not the whole firmware FD.
Signed-off-by: Tuan Phan
---
.../Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c| 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
index fdc2ccb6294e..067065bd6ef9 100644
--- a/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
+++ b/OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c
@@ -24,7 +24,8 @@ VIRT_NOR_FLASH_DESCRIPTION mNorFlashDevice =
{
FixedPcdGet32 (PcdOvmfFdBaseAddress),
FixedPcdGet64 (PcdFlashNvStorageVariableBase),
- FixedPcdGet32 (PcdOvmfFirmwareFdSize),
+ FixedPcdGet32 (PcdOvmfFirmwareFdSize) -
+ (FixedPcdGet64 (PcdFlashNvStorageVariableBase) - FixedPcdGet32
(PcdOvmfFdBaseAddress)),
QEMU_NOR_BLOCK_SIZE
};
--
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[edk2-devel] [PATCH 3/7] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
During CpuDxe initialization, MMU will be setup based on the value
get from the PCD satp mode. Default is bare mode.
Signed-off-by: Tuan Phan
---
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 10 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 1 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 5 +
UefiCpuPkg/CpuDxeRiscV64/Mmu.c | 493 +
UefiCpuPkg/CpuDxeRiscV64/Mmu.h | 33 ++
UefiCpuPkg/CpuDxeRiscV64/MmuCore.S | 29 ++
UefiCpuPkg/UefiCpuPkg.dec | 8 +
7 files changed, 577 insertions(+), 2 deletions(-)
create mode 100644 UefiCpuPkg/CpuDxeRiscV64/Mmu.c
create mode 100644 UefiCpuPkg/CpuDxeRiscV64/Mmu.h
create mode 100644 UefiCpuPkg/CpuDxeRiscV64/MmuCore.S
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
index 7551e0653603..144e4b49ea5a 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
@@ -9,6 +9,7 @@
**/
#include "CpuDxe.h"
+#include "Mmu.h"
//
// Global Variables
@@ -296,8 +297,7 @@ CpuSetMemoryAttributes (
IN UINT64 Attributes
)
{
- DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n",
__FUNCTION__));
- return EFI_SUCCESS;
+ return RiscVSetMemoryAttributes (BaseAddress, Length, Attributes);
}
/**
@@ -340,6 +340,12 @@ InitializeCpu (
//
DisableInterrupts ();
+ //
+ // Enable MMU
+ //
+ Status = RiscVConfigureMmu (PcdGet64 (PcdCpuRiscVSatpMode));
+ ASSERT_EFI_ERROR (Status);
+
//
// Install Boot protocol
//
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
index 49f4e119665a..2f2f970a7887 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
/**
Flush CPU data cache. If the instruction cache is fully coherent
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
index e8fa25446aef..6c2d65be789d 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
@@ -37,10 +37,14 @@
TimerLib
PeCoffGetEntryPointLib
RiscVSbiLib
+ CacheMaintenanceLib
[Sources]
CpuDxe.c
CpuDxe.h
+ Mmu.c
+ Mmu.h
+ MmuCore.S
[Protocols]
gEfiCpuArchProtocolGuid ## PRODUCES
@@ -60,6 +64,7 @@
gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList ##
CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize##
CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ##
CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVSatpMode ##
CONSUMES
[Depex]
TRUE
diff --git a/UefiCpuPkg/CpuDxeRiscV64/Mmu.c b/UefiCpuPkg/CpuDxeRiscV64/Mmu.c
new file mode 100644
index ..bec78b0ea514
--- /dev/null
+++ b/UefiCpuPkg/CpuDxeRiscV64/Mmu.c
@@ -0,0 +1,493 @@
+/** @file
+* MMU implementation for RISC-V
+*
+* Copyright (c) 2011-2020, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+* Copyright (c) 2017, Intel Corporation. All rights reserved.
+* Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "Mmu.h"
+
+#define RISCV_PG_V BIT0
+#define RISCV_PG_R BIT1
+#define RISCV_PG_W BIT2
+#define RISCV_PG_X BIT3
+#define RISCV_PG_G BIT5
+#define RISCV_PG_A BIT6
+#define RISCV_PG_D BIT7
+#define PTE_ATTRIBUTES_MASK 0xE
+
+#define PTE_PPN_MASK0x3FFC00ULL
+#define PTE_PPN_SHIFT 10
+#define RISCV_MMU_PAGE_SHIFT12
+
+STATIC UINTNmMaxRootTableLevel;
+STATIC UINTNmBitPerLevel;
+STATIC UINTNmTableEntryCount;
+
+STATIC
+BOOLEAN
+RiscVMmuEnabled (VOID)
+{
+ return ((RiscVGetSupervisorAddressTranslationRegister () &
+ SATP64_MODE) != (SATP_MODE_OFF << SATP64_MODE_SHIFT));
+}
+
+STATIC
+UINTN
+RiscVGetRootTranslateTable (VOID)
+{
+ return (RiscVGetSupervisorAddressTranslationRegister () & SATP64_PPN) <<
+RISCV_MMU_PAGE_SHIFT;
+}
+
+STATIC
+BOOLEAN
+IsValidPte (
+ IN UINTN Entry
+ )
+{
+ if (!(Entry & RISCV_PG_V) ||
+ (((Entry & (RISCV_PG_R | RISCV_PG_W)) == RISCV_PG_W))) {
+return FALSE;
+ }
+
+ return TRUE;
+}
+
+STATIC
+UINTN
+SetValidPte (
+ IN UINTN Entry
+ )
+{
+ /* Set Valid and Global mapping bits */
+ return Entry | RISCV_PG_G | RISCV_PG_V;
+}
+
+STATIC
+BOOLEAN
+IsBlockEntry (
+ IN UINTN Entry
+
[edk2-devel] [PATCH 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition
The satp mode bits shift is used cross modules. It should be defined in one place. Signed-off-by: Tuan Phan --- MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h index 5c2989b797bf..c60972892825 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -58,9 +58,10 @@ #define PRV_S 1UL #define PRV_M 3UL -#define SATP64_MODE 0xF000ULL -#define SATP64_ASID 0x0000ULL -#define SATP64_PPN 0x0FFFULL +#define SATP64_MODE 0xF000ULL +#define SATP64_MODE_SHIFT 60 +#define SATP64_ASID 0x0000ULL +#define SATP64_PPN0x0FFFULL #define SATP_MODE_OFF 0UL #define SATP_MODE_SV32 1UL -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100751): https://edk2.groups.io/g/devel/message/100751 Mute This Topic: https://groups.io/mt/97430549/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH 1/7] MdePkg/BaseLib: RISC-V: Support getting satp register value
Add an API to retrieve satp register value. Signed-off-by: Tuan Phan --- MdePkg/Include/Library/BaseLib.h | 5 + MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 2 files changed, 13 insertions(+) diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 8f2df76c29a3..5d7067ee854e 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -181,6 +181,11 @@ RiscVSetSupervisorAddressTranslationRegister ( IN UINT64 ); +UINT64 +RiscVGetSupervisorAddressTranslationRegister ( + VOID + ); + UINT64 RiscVReadTimer ( VOID diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S index ac8f92f38aed..c9cf60c1664b 100644 --- a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S @@ -21,3 +21,11 @@ ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister) csrw CSR_SATP, a0 ret + +// +// Get the value of Supervisor Address Translation and +// Protection Register. +// +ASM_FUNC (RiscVGetSupervisorAddressTranslationRegister) +csrr a0, CSR_SATP +ret -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100750): https://edk2.groups.io/g/devel/message/100750 Mute This Topic: https://groups.io/mt/97430548/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH 0/7] RISC-V: Add MMU support
This series adds MMU support for RISC-V. Only SV39/48/57 modes are supported and tested. The MMU is required to support setting page attribute which is the first basic step to support security booting on RISC-V. There are three parts: 1. Add MMU core to UefiCpuPkg. MMU will be enabled during CpuDxe initialization. 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base address to GCD if already done. 3. Enable MMU for RiscVVirt platform and populating its device resources in SEC phase. All resources should be populated in HOB or added to GCD by driver before accessing them when MMU enabled. Tuan Phan (7): MdePkg/BaseLib: RISC-V: Support getting satp register value MdePkg/Register: RISC-V: Add satp mode bits shift definition UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices OvmfPkg/RiscVVirt: Enable MMU with SV39 mode MdePkg/Include/Library/BaseLib.h | 5 + .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + .../VirtNorFlashStaticLib.c | 3 +- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + OvmfPkg/RiscVVirt/Sec/Memory.c| 17 - OvmfPkg/RiscVVirt/Sec/Platform.c | 62 +++ OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 10 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 1 + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf| 5 + UefiCpuPkg/CpuDxeRiscV64/Mmu.c| 493 ++ UefiCpuPkg/CpuDxeRiscV64/Mmu.h| 33 ++ UefiCpuPkg/CpuDxeRiscV64/MmuCore.S| 29 ++ UefiCpuPkg/UefiCpuPkg.dec | 8 + 16 files changed, 676 insertions(+), 32 deletions(-) create mode 100644 UefiCpuPkg/CpuDxeRiscV64/Mmu.c create mode 100644 UefiCpuPkg/CpuDxeRiscV64/Mmu.h create mode 100644 UefiCpuPkg/CpuDxeRiscV64/MmuCore.S -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100749): https://edk2.groups.io/g/devel/message/100749 Mute This Topic: https://groups.io/mt/97430547/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH] MdePkg/BaseCacheMaintenanceLib: RISC-V: Fix instruction cache not been invalidated
When the range instruction cache invalidating not supported, the whole
instruction cache should be invalidated instead.
Signed-off-by: Tuan Phan
---
MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index 67a3387ff3c6..a744b2a6f889 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -76,7 +76,10 @@ InvalidateInstructionCacheRange (
IN UINTN Length
)
{
- DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
+ DEBUG ((DEBUG_WARN,
+ "%a:RISC-V unsupported function.\n"
+ "Invalidating the whole instruction cache instead.\n", __func__));
+ InvalidateInstructionCache ();
return Address;
}
--
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