[PATCH] Add CGEM definitions for ZynqMP

[Kinsey Moore]

---
 rtemsbsd/include/bsp/nexus-devices.h   |  7 +++
 rtemsbsd/include/machine/rtems-bsd-nexus-bus.h | 16 
 2 files changed, 23 insertions(+)

diff --git a/rtemsbsd/include/bsp/nexus-devices.h 
b/rtemsbsd/include/bsp/nexus-devices.h
index 630572a8..51bca3aa 100644
--- a/rtemsbsd/include/bsp/nexus-devices.h
+++ b/rtemsbsd/include/bsp/nexus-devices.h
@@ -100,6 +100,13 @@ RTEMS_BSD_DRIVER_XILINX_ZYNQ_SLCR;
 RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM0(ZYNQ_IRQ_ETHERNET_0);
 RTEMS_BSD_DRIVER_E1000PHY;
 
+#elif defined(LIBBSP_AARCH64_XILINX_ZYNQMP_BSP_H)
+
+#include 
+
+RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM0(ZYNQMP_IRQ_ETHERNET_0);
+RTEMS_BSD_DRIVER_E1000PHY;
+
 #elif defined(LIBBSP_ARM_ATSAM_BSP_H)
 
 RTEMS_BSD_DRIVER_USB;
diff --git a/rtemsbsd/include/machine/rtems-bsd-nexus-bus.h 
b/rtemsbsd/include/machine/rtems-bsd-nexus-bus.h
index ff545dc0..f1ca66d7 100644
--- a/rtemsbsd/include/machine/rtems-bsd-nexus-bus.h
+++ b/rtemsbsd/include/machine/rtems-bsd-nexus-bus.h
@@ -371,6 +371,22 @@ extern "C" {
   #define RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM1(_irq)   \
 RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM(1, 0xe000c000, _irq)
 #endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM1 */
+#if !defined(RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM0)
+  #define RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM0(_irq)\
+RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM(0, 0xff0b, _irq)
+#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM0 */
+#if !defined(RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM1)
+  #define RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM1(_irq)   \
+RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM(1, 0xff0c, _irq)
+#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM1 */
+#if !defined(RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM2)
+  #define RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM2(_irq)\
+RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM(2, 0xff0d, _irq)
+#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM2 */
+#if !defined(RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM3)
+  #define RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM3(_irq)   \
+RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM(3, 0xff0e, _irq)
+#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM3 */
 
 /*
  * Designware/Synopsys Ethernet MAC Controller.
-- 
2.20.1

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[PATCH] score/aarch64: Resolve warning in exception dump

[Kinsey Moore]

This resolves a warning in the exception frame dump for AArch64 relating
to a missized printf format specifier.
---
 cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c 
b/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
index cd919c3214..59b5d06032 100644
--- a/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
+++ b/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
@@ -65,7 +65,7 @@ void _CPU_Exception_frame_print( const CPU_Exception_frame 
*frame )
 "X11  = 0x%016" PRIx64  " X28  = 0x%016" PRIx64 "\n"
 "X12  = 0x%016" PRIx64  " FP   = 0x%016" PRIx64 "\n"
 "X13  = 0x%016" PRIx64  " LR   = 0x%016" PRIxPTR "\n"
-"X14  = 0x%016" PRIx64  " SP   = 0x%016" PRIx64 "\n"
+"X14  = 0x%016" PRIx64  " SP   = 0x%016" PRIxPTR "\n"
 "X15  = 0x%016" PRIx64  " PC   = 0x%016" PRIxPTR "\n"
 "X16  = 0x%016" PRIx64  " DAIF = 0x%016" PRIx64 "\n"
 "VEC  = 0x%016" PRIxPTR " CPSR = 0x%016" PRIx64 "\n"
@@ -84,7 +84,7 @@ void _CPU_Exception_frame_print( const CPU_Exception_frame 
*frame )
 frame->register_x11, frame->register_x28,
 frame->register_x12, frame->register_fp,
 frame->register_x13, (intptr_t)frame->register_lr,
-frame->register_x14, frame->register_sp,
+frame->register_x14, (intptr_t)frame->register_sp,
 frame->register_x15, (intptr_t)frame->register_pc,
 frame->register_x16, frame->register_daif,
 (intptr_t) frame->vector, frame->register_cpsr,
-- 
2.20.1

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[PATCH] wscript: Apply test state expectations correctly

[Kinsey Moore]

The variety of expected test states are not currently applied to tests
with names containing '-' correctly due to a failure to replace '-' with
'_' before adding the CPPFLAGS to the environment for that test. This
ensures that all additions of CPPFLAGS have that replacement performed
so that the CPPFLAGS are applied properly during compilation.
---
 wscript | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/wscript b/wscript
index 5ad93de453..f5b7629b3b 100755
--- a/wscript
+++ b/wscript
@@ -723,7 +723,7 @@ class OptionItem(Item):
 print("{} = {}".format(self.data["name"], value))
 
 def _do_append_test_cppflags(self, conf, name, state):
-conf.env.append_value("TEST_" + name.upper() + "_CPPFLAGS", state)
+conf.env.append_value("TEST_" + name.upper().replace("-", "_") + 
"_CPPFLAGS", state)
 
 def _append_test_cppflags(self, conf, cic, value, arg):
 self._do_append_test_cppflags(conf, arg, value)
-- 
2.20.1

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RE: [PATCH] libtest: Fix undefined setjmp() behaviour

[Kinsey Moore]

-Original Message-
From: devel  On Behalf Of Sebastian Huber
Sent: Monday, November 23, 2020 03:19
To: devel@rtems.org
Subject: [PATCH] libtest: Fix undefined setjmp() behaviour

> Bug was introduced by 78baeb757957fa0807c30e6c4d21ae99c9639e6a.
>
> Update #3199.
> ---
>  cpukit/include/rtems/test.h |   3 +-
>  cpukit/libtest/t-test.c | 110 +++-
>  2 files changed, 60 insertions(+), 53 deletions(-)

This fixes the bug for me, thanks!

Kinsey
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RE: [PATCH 5/8] libtest: Allow assert checks during test begin

[Kinsey Moore]

-Original Message-
From: devel  On Behalf Of Sebastian Huber
Sent: Friday, November 13, 2020 04:08
To: devel@rtems.org
Subject: [PATCH 5/8] libtest: Allow assert checks during test begin

> Allow assert checks in test begin actions and setup fixture methods.
> ---
>  cpukit/include/rtems/test.h |  2 +-
>  cpukit/libtest/t-test.c | 29 +
>  2 files changed, 18 insertions(+), 13 deletions(-)

This patch appears to have broken ttest01.exe for arm/xilinx-zynq as well as 
aarch64 targets. I suspect it has also broken other arm targets. I tried 
looking into the failure, but I'm unfamiliar with the test framework in use.

Test output from arm/xilinx-zynq:
$ qemu-system-arm -no-reboot -nographic -serial null -serial mon:stdio -machine 
xilinx-zynq-a9 -m 4096 -kernel 
build/arm/xilinx_zynq_a9_qemu/testsuites/libtests/ttest01.exe


*** BEGIN OF TEST TTEST 1 ***
*** TEST VERSION: 6.0.0.46bf926570503dec3d70a8f09d12e461fd7e0914
*** TEST STATE: EXPECTED_PASS
*** TEST BUILD:
*** TEST TOOLS: 10.2.1 20200918 (RTEMS 6, RSB 
748525234945de047196f9974b866f8595efd66e, Newlib 749cbcc)
A:ttest01
S:Platform:RTEMS
S:Compiler:*
S:Version:*
S:BSP:*
S:RTEMS_DEBUG:*
S:RTEMS_MULTIPROCESSING:*
S:RTEMS_POSIX_API:*
S:RTEMS_PROFILING:*
S:RTEMS_SMP:*
B:zalloc_auto
P:0:0:UI1:test-malloc.c:35
P:1:0:UI1:test-malloc.c:36
P:2:0:UI1:test-malloc.c:26
E:zalloc_auto:N:3:F:0:D:0.001000
B:wrong_step
P:0:0:UI1:test-plan.c:6
F:1:0:UI1:test-plan.c:7:planned step (2)
E:wrong_step:N:2:F:1:D:0.001000
B:verbosity_changes
F:3:0:UI1:test-verbosity.c:12:normal: check fails -> with output
P:4:0:UI1:test-verbosity.c:14
F:5:0:UI1:test-verbosity.c:15:verbose: check fails -> with output
E:verbosity_changes:N:6:F:3:D:0.001000
B:timer
P:0:0:UI1:test-rtems.c:26
P:1:0:UI1:test-rtems.c:29
P:2:0:UI1:test-rtems.c:39
P:3:0:ISR:test-rtems.c:14
P:4:0:ISR:test-rtems.c:15
P:5:0:UI1:test-rtems.c:44
P:6:0:UI1:test-rtems.c:45
P:7:0:UI1:test-rtems.c:48
E:timer:N:8:F:0:D:0.001000
B:time_to_string
P:0:0:UI1:test-time.c:11
P:1:0:UI1:test-time.c:12
P:2:0:UI1:test-time.c:13
P:3:0:UI1:test-time.c:14
P:4:0:UI1:test-time.c:17
P:5:0:UI1:test-time.c:18
E:time_to_string:N:6:F:0:D:0.001000
B:time
P:0:0:UI1:test-time.c:55
P:1:0:UI1:test-time.c:56
P:2:0:UI1:test-time.c:57
P:3:0:UI1:test-time.c:58
P:4:0:UI1:test-time.c:61
P:5:0:UI1:test-time.c:63
P:6:0:UI1:test-time.c:64
P:7:0:UI1:test-time.c:67
P:8:0:UI1:test-time.c:69
P:9:0:UI1:test-time.c:70
P:10:0:UI1:test-time.c:73
P:11:0:UI1:test-time.c:75
P:12:0:UI1:test-time.c:76
P:13:0:UI1:test-time.c:79
P:14:0:UI1:test-time.c:81
P:15:0:UI1:test-time.c:82
P:16:0:UI1:test-time.c:85
P:17:0:UI1:test-time.c:87
P:18:0:UI1:test-time.c:88
P:19:0:UI1:test-time.c:91
P:20:0:UI1:test-time.c:93
P:21:0:UI1:test-time.c:94
P:22:0:UI1:test-time.c:97
P:23:0:UI1:test-time.c:99
P:24:0:UI1:test-time.c:100
P:25:0:UI1:test-time.c:103
P:26:0:UI1:test-time.c:105
P:27:0:UI1:test-time.c:106
P:28:0:UI1:test-time.c:109
P:29:0:UI1:test-time.c:111
P:30:0:UI1:test-time.c:112
P:31:0:UI1:test-time.c:115
P:32:0:UI1:test-time.c:117
P:33:0:UI1:test-time.c:118
P:34:0:UI1:test-time.c:121
P:35:0:UI1:test-time.c:123
P:36:0:UI1:test-time.c:124
P:37:0:UI1:test-time.c:127
P:38:0:UI1:test-time.c:129
P:39:0:UI1:test-time.c:130
E:time:N:40:F:0:D:0.001000
B:ticks
P:0:0:UI1:test-time.c:147
P:1:0:UI1:test-time.c:151
P:2:0:UI1:test-time.c:152
P:3:0:UI1:test-time.c:172
P:4:0:UI1:test-time.c:173
P:5:0:UI1:test-time.c:174
P:6:0:UI1:test-time.c:175
E:ticks:N:7:F:0:D:0.001000
B:tick
P:0:0:UI1:test-time.c:44
E:tick:N:1:F:0:D:0.001000
B:test_psx_success
P:0:0:UI1:test-psx.c:31
F:1:0:UI1:test-psx.c:32:-1 == 0, 0
F:*:0:UI1:test-psx.c:34:-1 == 0, 0
P:2:0:UI1:test-psx.c:35
F:3:0:UI1:test-psx.c:36:-1 == 0, 0
E:
*** FATAL ***
fatal source: 9 (RTEMS_FATAL_SOURCE_EXCEPTION)

R0   = 0xfff8 R8  = 0x
R1   = 0x0030 R9  = 0x00116d79
R2   = 0x00207798 R10 = 0x0002
R3   = 0x0001 R11 = 0x00204378
R4   = 0x R12 = 0x
R5   = 0xffecb9a8 SP  = 0x00207700
R6   = 0x0030 LR  = 0x001108b3
R7   = 0x0013465a PC  = 0x00119f6c
CPSR = 0x600f0173 VEC = 0x0004
FPEXC = 0x4000
FPSCR = 0x
D00 = 0x
D01 = 0x
D02 = 0x
D03 = 0x
D04 = 0x
D05 = 0x
D06 = 0x
D07 = 0x
D08 = 0x
D09 = 0x
D10 = 0x
D11 = 0x
D12 = 0x
D13 = 0x
D14 = 0x
D15 = 0x
D16 = 0x
D17 = 0x
D18 = 0x
D19 = 0x
D20 = 0x
D21 = 0x
D22 = 0x
D23 = 0x
D24 = 0x
D25 = 0x
D26 = 0x
D27 = 0x
D28 = 0x
D29 = 0x
D30 = 0x
D31 = 0x
RTEMS version: 6.0.0.46bf926570503dec3d70a8f09d12e461fd7e0914
RTEMS 

RE: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Monday, November 16, 2020 07:44
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

> On 16/11/2020 14:40, Kinsey Moore wrote:
>
>> -Original Message-
>> From: Sebastian Huber
>> Sent: Monday, November 16, 2020 07:35
>> To: Kinsey Moore;devel@rtems.org
>> Subject: Re: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32
>>
>>> On 16/11/2020 14:15, Kinsey Moore wrote:
>>>
>>>> The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 
>>>> builds was previously present on LP64 builds and causes no issues 
>>>> within RTEMS, but causes relocation/alignment issues when building libbsd.
>>>> This restricts those alignment changes to ILP32 builds.
>>> Please check it in if you think it is necessary.
>>>
>>> What troubles me a bit is that these SUBALIGN() stuff is present at all.
>>>
>>> It also troubles me that the splinkersets01 test case didn't catch this 
>>> problem.
>> That test was what originally caught the problem during development of the 
>> A53 BSP. This patch isn't the addition of a fix for the alignment problems, 
>> it's an adjustment of the original fix to be compatible with libbsd's use of 
>> rtemsroset/rtemsrwset linker sections.
> So, this SUBALIGN() is just a workaround for some other problem? It would be 
> good to document this known issue somewhere, for example a ticket. Is this an 
> upstream problem in GCC or the GNU linker?

Yes, SUBALIGN() is the workaround for ILP32 defaulting to 8 byte alignment in 
the rtemsroset and rtemsrwset linker sections because RTEMS expects them to 
default to 4 byte alignment when using 4 byte pointers. I suspect it's an issue 
in the GNU linker, but I haven't had a chance to track down the root cause. 
This patch is necessary because while RTEMS works fine with 4 byte alignment in 
those sections in the context of 8 byte pointers, libbsd puts things other than 
pointers in those sections and requires the alignment of those sections to 
exactly match the pointer size.

I'll open a ticket for documentation purposes.

Kinsey
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RE: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Monday, November 16, 2020 07:35
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

>On 16/11/2020 14:15, Kinsey Moore wrote:
>
>> The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 builds 
>> was previously present on LP64 builds and causes no issues within 
>> RTEMS, but causes relocation/alignment issues when building libbsd. 
>> This restricts those alignment changes to ILP32 builds.
>
> Please check it in if you think it is necessary.
>
> What troubles me a bit is that these SUBALIGN() stuff is present at all.
>
> It also troubles me that the splinkersets01 test case didn't catch this 
> problem.

That test was what originally caught the problem during development of the A53 
BSP. This patch isn't the addition of a fix for the alignment problems, it's an 
adjustment of the original fix to be compatible with libbsd's use of 
rtemsroset/rtemsrwset linker sections.

Kinsey
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[PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

[Kinsey Moore]

The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 builds
was previously present on LP64 builds and causes no issues within RTEMS,
but causes relocation/alignment issues when building libbsd. This
restricts those alignment changes to ILP32 builds.
---
 bsps/aarch64/shared/start/linkcmds.base| 6 --
 spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/bsps/aarch64/shared/start/linkcmds.base 
b/bsps/aarch64/shared/start/linkcmds.base
index 450c3ba2a9..4bf5b10746 100644
--- a/bsps/aarch64/shared/start/linkcmds.base
+++ b/bsps/aarch64/shared/start/linkcmds.base
@@ -43,6 +43,8 @@ STARTUP (start.o)
 
 bsp_stack_align = DEFINED (bsp_stack_align) ? bsp_stack_align : 16;
 
+bsp_set_align = DEFINED (bsp_set_align) ? bsp_set_align : 8;
+
 bsp_stack_exception_size = DEFINED (bsp_stack_exception_size) ? 
bsp_stack_exception_size : 0;
 bsp_stack_exception_size = ALIGN (bsp_stack_exception_size, bsp_stack_align);
 
@@ -243,7 +245,7 @@ SECTIONS {
.got : ALIGN_WITH_INPUT {
*(.got.plt) *(.igot.plt) *(.got) *(.igot)
} > REGION_RODATA AT > REGION_RODATA_LOAD
-   .rtemsroset : ALIGN_WITH_INPUT SUBALIGN(4) {
+   .rtemsroset : ALIGN_WITH_INPUT SUBALIGN(bsp_set_align) {
/* Special FreeBSD linker set sections */
__start_set_sysctl_set = .;
*(set_sysctl_*);
@@ -297,7 +299,7 @@ SECTIONS {
.data1 : ALIGN_WITH_INPUT {
*(.data1)
} > REGION_DATA AT > REGION_DATA_LOAD
-   .rtemsrwset : ALIGN_WITH_INPUT SUBALIGN(4) {
+   .rtemsrwset : ALIGN_WITH_INPUT SUBALIGN(bsp_set_align) {
KEEP (*(SORT(.rtemsrwset.*)))
bsp_section_data_end = .;
} > REGION_DATA AT > REGION_DATA_LOAD
diff --git a/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml 
b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
index ed585f1950..085c9c707c 100644
--- a/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
+++ b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
@@ -60,6 +60,7 @@ content: |
 
   OUTPUT_FORMAT ("elf32-littleaarch64")
   OUTPUT_ARCH (aarch64:ilp32)
+  bsp_set_align = 4;
 
   INCLUDE linkcmds.base
 copyrights:
-- 
2.20.1

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[PATCH 1/2] spec/aarch64: Ensure that libbsd can build properly

[Kinsey Moore]

These files are required for libbsd to build against the AArch64 A53
BSPs.
---
 spec/build/bsps/aarch64/grp.yml | 4 
 1 file changed, 4 insertions(+)

diff --git a/spec/build/bsps/aarch64/grp.yml b/spec/build/bsps/aarch64/grp.yml
index 4b5f998a12..1b8dc1c629 100644
--- a/spec/build/bsps/aarch64/grp.yml
+++ b/spec/build/bsps/aarch64/grp.yml
@@ -5,6 +5,10 @@ copyrights:
 enabled-by: true
 includes: []
 install:
+- destination: ${BSP_INCLUDEDIR}/bsp
+  source:
+  - bsps/aarch64/include/bsp/linker-symbols.h
+  - bsps/aarch64/include/bsp/start.h
 - destination: ${BSP_INCLUDEDIR}/dev/clock
   source:
   - bsps/include/dev/clock/arm-generic-timer.h
-- 
2.20.1

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RE: [PATCH rtems-tools] bsps/a53_*: Fix typo in qemu options

[Kinsey Moore]

Odd, "gic_version" works just fine in the version of qemu-system-aarch64 in the 
Debian package repos which is what I've been testing against. As you've 
provided in the patch, the official option name is "gic-version" and that also 
works. Just out of curiosity, does this cause Qemu to fail for you?

Either way, this change looks good to me.

Kinsey

-Original Message-
From: devel  On Behalf Of Vijay Kumar Banerjee
Sent: Saturday, November 14, 2020 14:51
To: devel@rtems.org
Subject: [PATCH rtems-tools] bsps/a53_*: Fix typo in qemu options

---
 tester/rtems/testing/bsps/a53_ilp32_qemu.ini | 2 +-  
tester/rtems/testing/bsps/a53_lp64_qemu.ini  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/tester/rtems/testing/bsps/a53_ilp32_qemu.ini 
b/tester/rtems/testing/bsps/a53_ilp32_qemu.ini
index 6dfc883..3beba06 100644
--- a/tester/rtems/testing/bsps/a53_ilp32_qemu.ini
+++ b/tester/rtems/testing/bsps/a53_ilp32_qemu.ini
@@ -35,4 +35,4 @@
 bsp   = a53_ilp32_qemu
 arch  = aarch64
 tester= %{_rtscripts}/qemu.cfg
-bsp_qemu_opts = %{qemu_opts_base} -serial mon:stdio -machine 
virt,gic_version=3 -cpu cortex-a53 -m 4096
+bsp_qemu_opts = %{qemu_opts_base} -serial mon:stdio -machine 
+virt,gic-version=3 -cpu cortex-a53 -m 4096
diff --git a/tester/rtems/testing/bsps/a53_lp64_qemu.ini 
b/tester/rtems/testing/bsps/a53_lp64_qemu.ini
index f29ab13..1b89284 100644
--- a/tester/rtems/testing/bsps/a53_lp64_qemu.ini
+++ b/tester/rtems/testing/bsps/a53_lp64_qemu.ini
@@ -35,4 +35,4 @@
 bsp   = a53_lp64_qemu
 arch  = aarch64
 tester= %{_rtscripts}/qemu.cfg
-bsp_qemu_opts = %{qemu_opts_base} -serial mon:stdio -machine 
virt,gic_version=3 -cpu cortex-a53 -m 4096
+bsp_qemu_opts = %{qemu_opts_base} -serial mon:stdio -machine 
+virt,gic-version=3 -cpu cortex-a53 -m 4096
--
2.21.1

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RE: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Saturday, November 14, 2020 06:24
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

>On 13/11/2020 15:53, Kinsey Moore wrote:
>
>>>> -Original Message-
>>>> From: Sebastian Huber
>>>> Sent: Friday, November 13, 2020 04:26
>>>> To: Kinsey Moore;devel@rtems.org
>>>> Subject: Re: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to 
>>>> ILP32
>>>>
>>>>> On 12/11/2020 14:32, Kinsey Moore wrote:
>>>>>
>>>>>> The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 
>>>>>> builds was previously present on LP64 builds and causes no issues 
>>>>>> within RTEMS, but causes relocation/alignment issues when building 
>>>>>> libbsd.
>>>>>> This restricts those alignment changes to ILP32 builds.
>>>>> The SUBALIGN() is currently only used on aarch64 in RTEMS. Why is it 
>>>>> necessary? The PowerPC port for example uses a single linkcmds.base for 
>>>>> the 32-bit and 64-bit without a SUBALIGN().
>>>> The SUBALIGN was necessary because the default alignment was 8 bytes and 
>>>> the ILP32 code would fail during initialization while iterating over the 
>>>> linker sets since the upper half-word of every address was zeroed out and 
>>>> was being treated as another init call. Is there a preferred way to 
>>>> accomplish this that doesn't involve SUBALIGN?
>>> Why can't you remove all the SUBALIGN() from the linker script?
>>>
>>> For example
>>>
>>> aarch64-rtems6-ld --verbose | grep SUBALIGN
>>>
>>> has no output.
>> That output is specifically for LP64 AArch64. ILP32 linker scripts have 
>> different OUTPUT_ARCH and OUTPUT_FORMAT directives. I wasn't able to get 
>> aarch64-rtems6-ld to output an ILP32 default linker script.
>What happens if you remove all the SUBALIGN() stuff from the linker script?

The LP64 multilib variant works just fine, but the ILP32 variant crashes during 
init on a null pointer since the elements of the linker set are aligned on 8 
byte boundaries and the iteration occurs for 4 byte pointers.

Kinsey
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RE: [PATCH 1/2] spec/aarch64: Ensure that libbsd can build properly

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Saturday, November 14, 2020 06:23
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH 1/2] spec/aarch64: Ensure that libbsd can build properly

>On 13/11/2020 16:04, Kinsey Moore wrote:
>
>> -Original Message-
>> From: Sebastian Huber
>> Sent: Friday, November 13, 2020 04:23
>> To: Kinsey Moore;devel@rtems.org
>> Subject: Re: [PATCH 1/2] spec/aarch64: Ensure that libbsd can build 
>> properly
>>
>> On 12/11/2020 14:32, Kinsey Moore wrote:
>>>>install:
>>>> +- destination: ${BSP_INCLUDEDIR}/bsp
>>>> +  source:
>>>> +  - bsps/arm/include/bsp/linker-symbols.h
>>>> +  - bsps/arm/include/bsp/start.h
>>>>- destination: ${BSP_INCLUDEDIR}/dev/clock
>>>>  source:
>>>>  - bsps/include/dev/clock/arm-generic-timer.h
>>> This is a bit strange. You install files which are not used to build the 
>>> BSP?
>> They are used by bspstart.c and bspstarthooks.c so they're used to build the 
>> BSP, but they're only required for some external applications and libraries 
>> which is why they weren't already being installed. This matches how ARM, 
>> RISC-V, and other BSPs install start.h and linker-symbols.h.
> How did you add "bsps/arm/include" to the include path used for the
> aarch64 BSPs?

Ah, sorry. I was missing the point you were trying to make. Those files are 
similar enough that it would allow compilation, but you're right. Those are the 
wrong file paths. I'll update the patch.

Kinsey
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RE: [PATCH 1/2] spec/aarch64: Ensure that libbsd can build properly

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Friday, November 13, 2020 04:23
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH 1/2] spec/aarch64: Ensure that libbsd can build properly

On 12/11/2020 14:32, Kinsey Moore wrote:
>>   install:
>> +- destination: ${BSP_INCLUDEDIR}/bsp
>> +  source:
>> +  - bsps/arm/include/bsp/linker-symbols.h
>> +  - bsps/arm/include/bsp/start.h
>>   - destination: ${BSP_INCLUDEDIR}/dev/clock
>> source:
>> - bsps/include/dev/clock/arm-generic-timer.h
> This is a bit strange. You install files which are not used to build the BSP?

They are used by bspstart.c and bspstarthooks.c so they're used to build the 
BSP, but they're only required for some external applications and libraries 
which is why they weren't already being installed. This matches how ARM, 
RISC-V, and other BSPs install start.h and linker-symbols.h.

Kinsey
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RE: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Friday, November 13, 2020 08:16
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

>On 13/11/2020 15:13, Kinsey Moore wrote:
>
>> -Original Message-
>> From: Sebastian Huber
>> Sent: Friday, November 13, 2020 04:26
>> To: Kinsey Moore;devel@rtems.org
>> Subject: Re: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32
>>
>>> On 12/11/2020 14:32, Kinsey Moore wrote:
>>>
>>>> The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 
>>>> builds was previously present on LP64 builds and causes no issues 
>>>> within RTEMS, but causes relocation/alignment issues when building libbsd.
>>>> This restricts those alignment changes to ILP32 builds.
>>> The SUBALIGN() is currently only used on aarch64 in RTEMS. Why is it 
>>> necessary? The PowerPC port for example uses a single linkcmds.base for the 
>>> 32-bit and 64-bit without a SUBALIGN().
>> The SUBALIGN was necessary because the default alignment was 8 bytes and the 
>> ILP32 code would fail during initialization while iterating over the linker 
>> sets since the upper half-word of every address was zeroed out and was being 
>> treated as another init call. Is there a preferred way to accomplish this 
>> that doesn't involve SUBALIGN?
>
> Why can't you remove all the SUBALIGN() from the linker script?
>
> For example
>
> aarch64-rtems6-ld --verbose | grep SUBALIGN
>
> has no output.

That output is specifically for LP64 AArch64. ILP32 linker scripts have 
different OUTPUT_ARCH and OUTPUT_FORMAT directives. I wasn't able to get 
aarch64-rtems6-ld to output an ILP32 default linker script.

Kinsey
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RE: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Friday, November 13, 2020 04:26
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

>On 12/11/2020 14:32, Kinsey Moore wrote:
>
>> The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 builds 
>> was previously present on LP64 builds and causes no issues within 
>> RTEMS, but causes relocation/alignment issues when building libbsd. 
>> This restricts those alignment changes to ILP32 builds.
>The SUBALIGN() is currently only used on aarch64 in RTEMS. Why is it 
>necessary? The PowerPC port for example uses a single linkcmds.base for the 
>32-bit and 64-bit without a SUBALIGN().

The SUBALIGN was necessary because the default alignment was 8 bytes and the 
ILP32 code would fail during initialization while iterating over the linker 
sets since the upper half-word of every address was zeroed out and was being 
treated as another init call. Is there a preferred way to accomplish this that 
doesn't involve SUBALIGN?

Given my experience with AArch64, I would expect the PowerPC linker script to 
need to do the same though upon review it obviously doesn't. The difference may 
be due to a bug in the ILP32 portions of the AArch64 toolchain since it's 
relatively new.

Kinsey
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[PATCH rtems-libbsd] Update arm64/aarch64 support

[Kinsey Moore]

---
 freebsd/sys/arm64/arm64/in_cksum.c| 243 +++
 freebsd/sys/arm64/include/machine/armreg.h| 665 ++
 freebsd/sys/arm64/include/machine/cpu.h   | 203 ++
 freebsd/sys/arm64/include/machine/cpufunc.h   | 153 
 freebsd/sys/arm64/include/machine/in_cksum.h  |  83 +++
 .../ck/include/gcc/aarch64/ck_pr_llsc.h   | 352 +
 .../ck/include/gcc/aarch64/ck_pr_lse.h| 298 
 libbsd.py |  21 +
 rtemsbsd/include/machine/frame.h  |   1 +
 9 files changed, 2019 insertions(+)
 create mode 100644 freebsd/sys/arm64/arm64/in_cksum.c
 create mode 100644 freebsd/sys/arm64/include/machine/armreg.h
 create mode 100644 freebsd/sys/arm64/include/machine/cpu.h
 create mode 100644 freebsd/sys/arm64/include/machine/cpufunc.h
 create mode 100644 freebsd/sys/arm64/include/machine/in_cksum.h
 create mode 100644 freebsd/sys/contrib/ck/include/gcc/aarch64/ck_pr_llsc.h
 create mode 100644 freebsd/sys/contrib/ck/include/gcc/aarch64/ck_pr_lse.h
 create mode 100644 rtemsbsd/include/machine/frame.h

diff --git a/freebsd/sys/arm64/arm64/in_cksum.c 
b/freebsd/sys/arm64/arm64/in_cksum.c
new file mode 100644
index ..9f92f2ff
--- /dev/null
+++ b/freebsd/sys/arm64/arm64/in_cksum.c
@@ -0,0 +1,243 @@
+#include 
+
+/* $NetBSD: in_cksum.c,v 1.7 1997/09/02 13:18:15 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 1988, 1992, 1993
+ * The Regents of the University of California.  All rights reserved.
+ * Copyright (c) 1996
+ * Matt Thomas 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *may be used to endorse or promote products derived from this software
+ *without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)in_cksum.c  8.1 (Berkeley) 6/10/93
+ */
+
+#include  /* RCS ID & Copyright macro defns */
+__FBSDID("$FreeBSD$");
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * Checksum routine for Internet Protocol family headers
+ *(Portable Alpha version).
+ *
+ * This routine is very heavily used in the network
+ * code and should be modified for each CPU to be as fast as possible.
+ */
+
+#define ADDCARRY(x)  (x > 65535 ? x -= 65535 : x)
+#define REDUCE32 \
+{\
+   q_util.q = sum;   \
+   sum = q_util.s[0] + q_util.s[1] + q_util.s[2] + q_util.s[3];  \
+}
+#define REDUCE16 \
+{\
+   q_util.q = sum;   \
+   l_util.l = q_util.s[0] + q_util.s[1] + q_util.s[2] + q_util.s[3]; \
+   sum = l_util.s[0] + l_util.s[1];  \
+   ADDCARRY(sum);\
+}
+
+static const u_int32_t in_masks[] = {
+   /*0 bytes*/ /*1 byte*/  /*2 bytes*/ /*3 bytes*/
+   0x, 0x00FF, 0x, 0x00FF, /* offset 0 */
+   0x, 0xFF00, 0x0000, 0xFF00, /* offset 1 */
+   0x, 0x00FF, 0x, 0x, /* offset 2 */
+   0x, 0xFF00, 0xFF00, 0xFF00, /* offset 3 */
+};
+
+union l_util {
+   

[PATCH 2/2] spec/aarch64: Only apply SUBALIGN(4) to ILP32

[Kinsey Moore]

The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 builds
was previously present on LP64 builds and causes no issues within RTEMS,
but causes relocation/alignment issues when building libbsd. This
restricts those alignment changes to ILP32 builds.
---
 bsps/aarch64/shared/start/linkcmds.base| 6 --
 spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/bsps/aarch64/shared/start/linkcmds.base 
b/bsps/aarch64/shared/start/linkcmds.base
index 450c3ba2a9..4bf5b10746 100644
--- a/bsps/aarch64/shared/start/linkcmds.base
+++ b/bsps/aarch64/shared/start/linkcmds.base
@@ -43,6 +43,8 @@ STARTUP (start.o)
 
 bsp_stack_align = DEFINED (bsp_stack_align) ? bsp_stack_align : 16;
 
+bsp_set_align = DEFINED (bsp_set_align) ? bsp_set_align : 8;
+
 bsp_stack_exception_size = DEFINED (bsp_stack_exception_size) ? 
bsp_stack_exception_size : 0;
 bsp_stack_exception_size = ALIGN (bsp_stack_exception_size, bsp_stack_align);
 
@@ -243,7 +245,7 @@ SECTIONS {
.got : ALIGN_WITH_INPUT {
*(.got.plt) *(.igot.plt) *(.got) *(.igot)
} > REGION_RODATA AT > REGION_RODATA_LOAD
-   .rtemsroset : ALIGN_WITH_INPUT SUBALIGN(4) {
+   .rtemsroset : ALIGN_WITH_INPUT SUBALIGN(bsp_set_align) {
/* Special FreeBSD linker set sections */
__start_set_sysctl_set = .;
*(set_sysctl_*);
@@ -297,7 +299,7 @@ SECTIONS {
.data1 : ALIGN_WITH_INPUT {
*(.data1)
} > REGION_DATA AT > REGION_DATA_LOAD
-   .rtemsrwset : ALIGN_WITH_INPUT SUBALIGN(4) {
+   .rtemsrwset : ALIGN_WITH_INPUT SUBALIGN(bsp_set_align) {
KEEP (*(SORT(.rtemsrwset.*)))
bsp_section_data_end = .;
} > REGION_DATA AT > REGION_DATA_LOAD
diff --git a/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml 
b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
index ed585f1950..085c9c707c 100644
--- a/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
+++ b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
@@ -60,6 +60,7 @@ content: |
 
   OUTPUT_FORMAT ("elf32-littleaarch64")
   OUTPUT_ARCH (aarch64:ilp32)
+  bsp_set_align = 4;
 
   INCLUDE linkcmds.base
 copyrights:
-- 
2.20.1

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[PATCH 1/2] spec/aarch64: Ensure that libbsd can build properly

[Kinsey Moore]

These files are required for libbsd to build against the AArch64 A53
BSPs.
---
 spec/build/bsps/aarch64/grp.yml | 4 
 1 file changed, 4 insertions(+)

diff --git a/spec/build/bsps/aarch64/grp.yml b/spec/build/bsps/aarch64/grp.yml
index 4b5f998a12..e0a8e607a5 100644
--- a/spec/build/bsps/aarch64/grp.yml
+++ b/spec/build/bsps/aarch64/grp.yml
@@ -5,6 +5,10 @@ copyrights:
 enabled-by: true
 includes: []
 install:
+- destination: ${BSP_INCLUDEDIR}/bsp
+  source:
+  - bsps/arm/include/bsp/linker-symbols.h
+  - bsps/arm/include/bsp/start.h
 - destination: ${BSP_INCLUDEDIR}/dev/clock
   source:
   - bsps/include/dev/clock/arm-generic-timer.h
-- 
2.20.1

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RE: [PATCH] score/aarch64: Size saved SP register for ABI

[Kinsey Moore]

From: Hesham Almatary 
Sent: Thursday, October 22, 2020 14:51
To: Kinsey Moore 
Cc: devel@rtems.org
Subject: Re: [PATCH] score/aarch64: Size saved SP register for ABI



On Thu, 22 Oct 2020 at 20:07, Kinsey Moore 
mailto:kinsey.mo...@oarcorp.com>> wrote:
This ensures that the saved SP register is sized appropriately depending
on the chosen ABI and prevents a warning in the libmisc stack checker.
---
 cpukit/score/cpu/aarch64/include/rtems/score/cpu.h | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h 
b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
index da2140a2a8..b33f6a1c85 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
@@ -489,7 +489,10 @@ typedef struct {
 #ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
   uint32_t _register_lr_top;
 #endif
-  uint64_t register_sp;
+  uintptr_t register_sp;
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+  uint32_t _register_sp_top;
Won’t uintptr_t work here (and for all of the other integer registers) as well 
and consequently we get rid of all of such multiarch  ifdefs?

It doesn’t get rid of the multiarch ifdefs, it would just move them to the 
offsets #define block above and into the assembly for generating the stack 
frame. I’d much rather have the exception frame be a static size and avoid 
adjusting the assembly and offsets based on ABI since from the machine’s 
perspective it’s still a 64bit pointer even if C and C++ view it as a 32bit 
pointer.


Kinsey
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[PATCH] score/aarch64: Size saved SP register for ABI

[Kinsey Moore]

This ensures that the saved SP register is sized appropriately depending
on the chosen ABI and prevents a warning in the libmisc stack checker.
---
 cpukit/score/cpu/aarch64/include/rtems/score/cpu.h | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h 
b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
index da2140a2a8..b33f6a1c85 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
@@ -489,7 +489,10 @@ typedef struct {
 #ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
   uint32_t _register_lr_top;
 #endif
-  uint64_t register_sp;
+  uintptr_t register_sp;
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+  uint32_t _register_sp_top;
+#endif
   void *register_pc;
 #ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
   uint32_t _register_pc_top;
-- 
2.20.1

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RE: aarch64/a53_ilp32_qemu: implicit declaration of function 'truncl'

[Kinsey Moore]

On Sat, Oct 10, 2020 at 8:13 AM Sebastian Huber 
mailto:sebastian.hu...@embedded-brains.de>> 
wrote:
On 10/10/2020 15:11, Sebastian Huber wrote:

> Hello Kinsey,
>
> the new aarch64/a53_ilp32_qemu produces a lot of warnings like this:
>
> ../../../testsuites/psxtests/psxhdrs/math/truncl.c:45:12: warning:
> implicit declaration of function 'truncl'
> [-Wimplicit-function-declaration]
> ../../../testsuites/psxtests/psxhdrs/math/truncl.c:45:12: warning:
> incompatible implicit declaration of built-in function 'truncl'
>
> Is this a known issue?

It is likely that this is because some/many architectures do not
have long double support in newlib. Or have a true long double
type. This will require a newlib discussion.


There is also this warning:

cpukit/libmisc/stackchk/check.c:455:5: warning: cast to pointer from
integer of different size [-Wint-to-pointer-cast]

This is probably an error. Could you please fix the warnings specific to
the new BSPs.

This looks like code being sloppy that isn't the fault of this BSP. It is
just one where sizeof(int) != sizeof(void *).

Kinsey.. likely solution is to replace the cast/type with intptr_t or uintptr_t.

[]
Sorry, I didn’t see these when I was developing. I’ll work up some patches for 
them.

Kinsey
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RE: [PATCH] testsuites/samples/fileio - Increase of stack size

[Kinsey Moore]

I'm not sure it's specifically a GCC10 issue, but I've encountered something 
like this before (I think it was GCC8 or GCC9).
https://github.com/ISI-apex/rtems/commit/edd6d90c3ad21393dd0de93056f371c7abc89b78

I thought I'd sent in a patch for this or at least created a ticket, but I 
can't find either at the moment.

Kinsey

-Original Message-
From: devel  On Behalf Of Frank Kühndel
Sent: Friday, October 9, 2020 09:06
To: j...@rtems.org
Cc: rtems-de...@rtems.org 
Subject: Re: [PATCH] testsuites/samples/fileio - Increase of stack size

Hi Joel,

Sebastian is the opinion its a "GCC 10 issue".

On 10/9/20 3:32 PM, Joel Sherrill wrote:
> This is interesting. When I teach RTEMS classes, I always run this 
> application and the last time, this BSP was the one used. It was a 
> rare case of all Zynq users with no LEON users. :)
> 
> What version of RTEMS and how did you configure it? 

Version is the newest, I think 6:

remote.origin.url=git://git.rtems.org/rtems.git

The branch bases on origin/master.
The preceding commit was:
commit 558a19d3adff6a3ecf678f94408b48beccbbc9fb (origin/master, origin/HEAD, 
master)

The config.ini is

[arm/realview_pbx_a9_qemu]
RTEMS_DEBUG = True
RTEMS_NETWORKING = True
RTEMS_POSIX_API = True
RTEMS_SMP = True
BUILD_TESTS = True

> 
> This sounds like it may need a ticket since it likely needs to be 
> included on the 5 branch.pa 

I can open a ticket for 5 and 6 if you like.

Greetings
Frank

> 
> I don't doubt it crashed. Just want details so we can apply the patch 
> properly.
> 
> --joel
> 
> On Fri, Oct 9, 2020 at 8:07 AM Frank Kuehndel 
>  > wrote:
> 
> When I use the 'shell' from the fileio sample with the command below:
> 
>    env QEMU_AUDIO_DRV="none" \
>    qemu-system-arm -no-reboot -net none -nographic -M
> realview-pbx-a9 -m 256M \
>    -kernel 
> build/arm/realview_pbx_a9_qemu/testsuites/samples/fileio.exe
> 
> The executable crashes with an "BLOWN STACK!!!" as soon as I try to
> login
> as 'root' with password. (The logins without password work fine.)
> Increasing
> the stack size of the affected thread a bit solves the issue. Hence,
> I suggest this patch.
> ---
>  testsuites/samples/fileio/init.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/testsuites/samples/fileio/init.c
> b/testsuites/samples/fileio/init.c
> index 86b34b99dd..c552d33613 100644
> --- a/testsuites/samples/fileio/init.c
> +++ b/testsuites/samples/fileio/init.c
> @@ -630,7 +630,7 @@ static void fileio_start_shell(void)
>    printf(" =\n");
>    rtems_shell_init(
>      "SHLL",                          /* task_name */
> -    RTEMS_MINIMUM_STACK_SIZE * 4,    /* task_stacksize */
> +    RTEMS_MINIMUM_STACK_SIZE * 5,    /* task_stacksize */
>      100,                             /* task_priority */
>      "/dev/foobar",                   /* devname */
>      /* device is currently ignored by the shell if it is not a pty */
> -- 
> 2.26.2
> 
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RE: Re: I can not run rtems 5.1 smp correctly on bsp xilinx-zynqmp

[Kinsey Moore]

Is it possible that the application was only started on the first core instead 
of all cores? Is it possible to check the execution state of the other cores?

Kinsey

From: Joel Sherrill 
Sent: Tuesday, October 6, 2020 08:11
To: small...@aliyun.com
Cc: Gedare Bloom ; devel ; Kinsey Moore 

Subject: Re: Re: I can not run rtems 5.1 smp correctly on bsp xilinx-zynqmp

Maybe Kinsey has an idea.

On Tue, Oct 6, 2020 at 1:29 AM small...@aliyun.com<mailto:small...@aliyun.com> 
mailto:small...@aliyun.com>> wrote:
The board is Ultra96 board with JTAG boot.
And yes, there is a bspsmp.c in rtems-5.1\bsps\arm\xilinx-zynqmp\start\


small...@aliyun.com<mailto:small...@aliyun.com>

From: Gedare Bloom<mailto:ged...@rtems.org>
Date: 2020-10-06 00:16
To: small...@aliyun.com<mailto:small...@aliyun.com>
CC: devel<mailto:devel@rtems.org>
Subject: Re: I can not run rtems 5.1 smp correctly on bsp xilinx-zynqmp
It should, I believe. The bsp has bspsmp.c file.

How did you configure (../rtems/configure)?

What board/target do you run it on?

On Mon, Oct 5, 2020 at 2:24 AM small...@aliyun.com<mailto:small...@aliyun.com> 
mailto:small...@aliyun.com>> wrote:
>
> Hi, all
> I compile rtems 5.1 with bsp xilinx-zynqmp. The single core mode is ok.
> But I can not use 2 or 3 or 4 cores of this bsp.
> After analysing the source code, I found there is no code to address smp 
> condition. Does rtems 5.1 indeed not support smp mode for xilinx-zynqmp bsp?
>
> 
> small...@aliyun.com<mailto:small...@aliyun.com>
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RE: [PATCH v1] tester: Prevent crash with json output

[Kinsey Moore]

From: Joel Sherrill 
Sent: Monday, October 5, 2020 17:03
To: Chris Johns 
Cc: Kinsey Moore ; rtems-de...@rtems.org 

Subject: Re: [PATCH v1] tester: Prevent crash with json output



On Mon, Oct 5, 2020 at 4:57 PM Chris Johns 
mailto:chr...@rtems.org>> wrote:
On 6/10/20 7:41 am, Kinsey Moore wrote:
> This fixes an issue with json report output that causes a crash due to
> the incorrect object member being accessed for test-too-long. This also
> changes treatment of fatal errors to match how they are displayed in the
> tester log output and changes "fatal error" to "fatal-error" to better
> match the naming of all the other failure types.
> ---
>  tester/rt/report.py | 2 +-
>  tester/rt/test.py   | 9 ++---
>  2 files changed, 7 insertions(+), 4 deletions(-)

OK to push. Thanks.

I'm OK to push this but should it also have a  ticket and go to 5?

I'm sure that's the question Kinsey wants to hear. :)
[]
This was necessary due to a change that didn’t go into 5, so it really 
shouldn’t go into 5, either

Kinsey
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[PATCH v1] tester: Prevent crash with json output

[Kinsey Moore]

This fixes an issue with json report output that causes a crash due to
the incorrect object member being accessed for test-too-long. This also
changes treatment of fatal errors to match how they are displayed in the
tester log output and changes "fatal error" to "fatal-error" to better
match the naming of all the other failure types.
---
 tester/rt/report.py | 2 +-
 tester/rt/test.py   | 9 ++---
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/tester/rt/report.py b/tester/rt/report.py
index 5f871dc..be8df74 100644
--- a/tester/rt/report.py
+++ b/tester/rt/report.py
@@ -194,7 +194,7 @@ class report(object):
 status = 'passed'
 self.passed += 1
 elif fatal:
-status = 'fatal error'
+status = 'fatal-error'
 self.failed += 1
 elif timeout:
 status = 'timeout'
diff --git a/tester/rt/test.py b/tester/rt/test.py
index fa9ddf5..9b157e9 100644
--- a/tester/rt/test.py
+++ b/tester/rt/test.py
@@ -235,7 +235,7 @@ def generate_json_report(args, reports, start_time, 
end_time,
 json_log['summary']['indeterminate_count'] = reports.indeterminate
 json_log['summary']['benchmark_count'] = reports.benchmark
 json_log['summary']['timeout_count'] = reports.timeouts
-json_log['summary']['too_long_count'] = reports.too_long
+json_log['summary']['test-too-long_count'] = reports.test_too_long
 json_log['summary']['invalid_count'] = reports.invalids
 json_log['summary']['wrong-version_count'] = reports.wrong_version
 json_log['summary']['wrong-build_count'] = reports.wrong_build
@@ -247,7 +247,7 @@ def generate_json_report(args, reports, start_time, 
end_time,
 
 result_types = [
 'failed', 'user-input', 'expected-fail', 'indeterminate',
-'benchmark', 'timeout', 'too-long', 'invalid', 'wrong-version',
+'benchmark', 'timeout', 'test-too-long', 'invalid', 
'wrong-version',
 'wrong-build', 'wrong-tools'
 ]
 json_results = {}
@@ -257,6 +257,9 @@ def generate_json_report(args, reports, start_time, 
end_time,
 # collate results for JSON log
 for name in reports.results:
 result_type = reports.results[name]['result']
+# map fatal-error on to failed since the report adds both to the 
failed count
+if result_type == "fatal-error":
+result_type = "failed"
 test_parts = name.split("/")
 test_category = test_parts[-2]
 test_name = test_parts[-1]
@@ -305,7 +308,7 @@ def generate_junit_report(args, reports, start_time, 
end_time,
 junit_prop['indeterminate_count'] = reports.indeterminate
 junit_prop['benchmark_count'] = reports.benchmark
 junit_prop['timeout_count'] = reports.timeouts
-junit_prop['too_long_count'] = reports.too_long
+junit_prop['test-too-long_count'] = reports.test_too_long
 junit_prop['invalid_count'] = reports.invalids
 junit_prop['wrong-version_count'] = reports.wrong_version
 junit_prop['wrong-build_count'] = reports.wrong_build
-- 
2.20.1

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[PATCH v4 5/9] bsps/shared: Add PSCI-based bspreset implementation

[Kinsey Moore]

This adds a bsp_reset implementation based on the ARM PSCI
specification often present in ARMv8 systems.
---
 bsps/shared/start/bspreset-arm-psci.c | 56 +++
 1 file changed, 56 insertions(+)
 create mode 100644 bsps/shared/start/bspreset-arm-psci.c

diff --git a/bsps/shared/start/bspreset-arm-psci.c 
b/bsps/shared/start/bspreset-arm-psci.c
new file mode 100644
index 00..215be5c9b5
--- /dev/null
+++ b/bsps/shared/start/bspreset-arm-psci.c
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsShared
+ *
+ * @brief PSCI-based BSP reset hook.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+void bsp_reset(void)
+{
+   uint32_t PSCI_FN_SYSTEM_RESET = 0x8409;
+   __asm__ volatile(
+#if defined(AARCH64_MULTILIB_ARCH_V8) || 
defined(AARCH64_MULTILIB_ARCH_V8_ILP32)
+   "mov x0, %0\n"
+#else
+   "mov r0, %0\n"
+#endif
+#ifdef BSP_RESET_SMC
+   "smc #0\n"
+#else
+   "hvc #0\n"
+#endif
+   : : "r" (PSCI_FN_SYSTEM_RESET)
+   );
+}
-- 
2.20.1

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[PATCH v4 7/9] score: Add AArch64 port

[Kinsey Moore]

This adds a CPU port for AArch64(ARMv8) with support for exceptions and
interrupts.
---
 cpukit/include/rtems/score/tls.h  |   6 +-
 .../cpu/aarch64/aarch64-context-validate.S| 305 ++
 .../aarch64-context-volatile-clobber.S| 100 
 .../cpu/aarch64/aarch64-exception-default.S   | 490 
 .../cpu/aarch64/aarch64-exception-default.c   |  50 ++
 .../aarch64/aarch64-exception-frame-print.c   | 108 
 .../cpu/aarch64/aarch64-exception-interrupt.S | 322 ++
 .../score/cpu/aarch64/aarch64-thread-idle.c   |  47 ++
 cpukit/score/cpu/aarch64/cpu.c| 197 +++
 cpukit/score/cpu/aarch64/cpu_asm.S| 134 +
 .../cpu/aarch64/include/libcpu/vectors.h  | 100 
 cpukit/score/cpu/aarch64/include/rtems/asm.h  |  89 +++
 .../cpu/aarch64/include/rtems/score/aarch64.h |  83 +++
 .../cpu/aarch64/include/rtems/score/cpu.h | 554 ++
 .../cpu/aarch64/include/rtems/score/cpu_irq.h |  50 ++
 .../aarch64/include/rtems/score/cpuatomic.h   |  42 ++
 .../cpu/aarch64/include/rtems/score/cpuimpl.h |  83 +++
 spec/build/cpukit/cpuaarch64.yml  |  36 ++
 spec/build/cpukit/librtemscpu.yml |   2 +
 19 files changed, 2797 insertions(+), 1 deletion(-)
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-validate.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-volatile-clobber.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-interrupt.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-thread-idle.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu_asm.S
 create mode 100644 cpukit/score/cpu/aarch64/include/libcpu/vectors.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/asm.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/aarch64.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpu_irq.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuatomic.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
 create mode 100644 spec/build/cpukit/cpuaarch64.yml

diff --git a/cpukit/include/rtems/score/tls.h b/cpukit/include/rtems/score/tls.h
index 65a49d87be..57063990e7 100644
--- a/cpukit/include/rtems/score/tls.h
+++ b/cpukit/include/rtems/score/tls.h
@@ -85,7 +85,11 @@ typedef struct TLS_Thread_control_block {
   struct TLS_Thread_control_block *tcb;
 #else /* !__i386__ */
   TLS_Dynamic_thread_vector *dtv;
-#if CPU_SIZEOF_POINTER == 4
+/*
+ * GCC under AArch64/LP64 expects a 16 byte TCB at the beginning of the TLS
+ * data segment and indexes into it accordingly for TLS variable addresses.
+ */
+#if CPU_SIZEOF_POINTER == 4 || defined(AARCH64_MULTILIB_ARCH_V8)
   uintptr_t reserved;
 #endif
 #endif /* __i386__ */
diff --git a/cpukit/score/cpu/aarch64/aarch64-context-validate.S 
b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
new file mode 100644
index 00..31c8d5571c
--- /dev/null
+++ b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUAArch64
+ *
+ * @brief Implementation of _CPU_Context_validate
+ *
+ * This file implements _CPU_Context_validate for use in spcontext01.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFT

[PATCH v4 8/9] bsps: Add Cortex-A53 LP64 basic BSP

[Kinsey Moore]

This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with
interrupt support using GICv3 and clock support using the ARM GPT.
---
 bsps/aarch64/a53/console/console.c|  69 ++
 bsps/aarch64/a53/include/bsp.h|  74 +++
 bsps/aarch64/a53/include/bsp/irq.h|  67 ++
 bsps/aarch64/a53/include/tm27.h   |  46 ++
 bsps/aarch64/a53/start/bspstart.c |  49 ++
 bsps/aarch64/a53/start/bspstarthooks.c|  50 ++
 bsps/aarch64/include/bsp/linker-symbols.h | 161 +
 bsps/aarch64/include/bsp/start.h  | 189 ++
 bsps/aarch64/shared/cache/cache.c | 616 ++
 .../shared/clock/arm-generic-timer-aarch64.c  | 110 
 .../shared/irq/irq-arm-gicv3-aarch64.c|  64 ++
 bsps/aarch64/shared/start/linkcmds.base   | 425 
 bsps/aarch64/shared/start/start.S | 219 +++
 spec/build/bsps/aarch64/a53/abi.yml   |  17 +
 .../build/bsps/aarch64/a53/bspa53lp64qemu.yml |  19 +
 spec/build/bsps/aarch64/a53/grp.yml   |  42 ++
 spec/build/bsps/aarch64/a53/linkcmds_lp64.yml |  71 ++
 spec/build/bsps/aarch64/a53/obj.yml   |  37 ++
 spec/build/bsps/aarch64/a53/optloadoff.yml|  18 +
 spec/build/bsps/aarch64/a53/optnocachelen.yml |  18 +
 spec/build/bsps/aarch64/a53/optramlen.yml |  18 +
 spec/build/bsps/aarch64/a53/optramori.yml |  18 +
 spec/build/bsps/aarch64/a53/tsta53.yml|  45 ++
 spec/build/bsps/aarch64/grp.yml   |  24 +
 spec/build/bsps/aarch64/start.yml |  14 +
 25 files changed, 2480 insertions(+)
 create mode 100644 bsps/aarch64/a53/console/console.c
 create mode 100644 bsps/aarch64/a53/include/bsp.h
 create mode 100644 bsps/aarch64/a53/include/bsp/irq.h
 create mode 100644 bsps/aarch64/a53/include/tm27.h
 create mode 100644 bsps/aarch64/a53/start/bspstart.c
 create mode 100644 bsps/aarch64/a53/start/bspstarthooks.c
 create mode 100644 bsps/aarch64/include/bsp/linker-symbols.h
 create mode 100644 bsps/aarch64/include/bsp/start.h
 create mode 100644 bsps/aarch64/shared/cache/cache.c
 create mode 100644 bsps/aarch64/shared/clock/arm-generic-timer-aarch64.c
 create mode 100644 bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c
 create mode 100644 bsps/aarch64/shared/start/linkcmds.base
 create mode 100644 bsps/aarch64/shared/start/start.S
 create mode 100644 spec/build/bsps/aarch64/a53/abi.yml
 create mode 100644 spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
 create mode 100644 spec/build/bsps/aarch64/a53/grp.yml
 create mode 100644 spec/build/bsps/aarch64/a53/linkcmds_lp64.yml
 create mode 100644 spec/build/bsps/aarch64/a53/obj.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optloadoff.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optnocachelen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramlen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramori.yml
 create mode 100644 spec/build/bsps/aarch64/a53/tsta53.yml
 create mode 100644 spec/build/bsps/aarch64/grp.yml
 create mode 100644 spec/build/bsps/aarch64/start.yml

diff --git a/bsps/aarch64/a53/console/console.c 
b/bsps/aarch64/a53/console/console.c
new file mode 100644
index 00..1854909c98
--- /dev/null
+++ b/bsps/aarch64/a53/console/console.c
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64A53
+ *
+ * @brief Console Configuration
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+arm_pl011_context a53_qemu_vpl011_context = 

[PATCH v4 6/9] spmsgq_err01: Use correct max values and fix 64bit

[Kinsey Moore]

Fix spmsgq_err01 on systems with 64-bit pointers and correct max value
mismatches and inaccuracies that are more noticable on 64-bit systems.
---
 testsuites/sptests/spmsgq_err01/init.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/testsuites/sptests/spmsgq_err01/init.c 
b/testsuites/sptests/spmsgq_err01/init.c
index c68d30da16..cb1a82c0e1 100644
--- a/testsuites/sptests/spmsgq_err01/init.c
+++ b/testsuites/sptests/spmsgq_err01/init.c
@@ -101,7 +101,7 @@ rtems_task Init(
   /* not enough memory for messages */
   status = rtems_message_queue_create(
 Queue_name[ 1 ],
-SIZE_MAX / ( sizeof( uintptr_t ) + sizeof( CORE_message_queue_Buffer ) ),
+UINT32_MAX / ( sizeof( uintptr_t ) + sizeof( CORE_message_queue_Buffer ) ),
 1,
 RTEMS_DEFAULT_ATTRIBUTES,
 _id[ 1 ]
@@ -116,8 +116,8 @@ rtems_task Init(
   /* too large a request for messages */
   status = rtems_message_queue_create(
 Queue_name[ 1 ],
-INT_MAX,
-INT_MAX,
+UINT32_MAX,
+SIZE_MAX - sizeof( uintptr_t ) + 1 - sizeof( CORE_message_queue_Buffer ),
 RTEMS_DEFAULT_ATTRIBUTES,
 _id[ 1 ]
   );
-- 
2.20.1

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[PATCH v5 2/2] Add AArch64 documentation

[Kinsey Moore]

---
 cpu-supplement/aarch64.rst | 134 +
 user/bsps/aarch64/a53.rst  |  26 +++
 user/bsps/bsps-aarch64.rst |   2 +-
 3 files changed, 161 insertions(+), 1 deletion(-)
 create mode 100644 cpu-supplement/aarch64.rst
 create mode 100644 user/bsps/aarch64/a53.rst

diff --git a/cpu-supplement/aarch64.rst b/cpu-supplement/aarch64.rst
new file mode 100644
index 000..b76895b
--- /dev/null
+++ b/cpu-supplement/aarch64.rst
@@ -0,0 +1,134 @@
+.. SPDX-License-Identifier: CC-BY-SA-4.0
+
+.. Copyright (C) 1988, 2020 On-Line Applications Research Corporation (OAR)
+
+AArch64 Specific Information
+
+
+This chapter discusses the dependencies of the
+*ARM AArch64 architecture*
+(https://en.wikipedia.org/wiki/ARM_architecture#AArch64_features) in this port
+of RTEMS.  The ARMv8-A versions are supported by RTEMS.  Processors with a MMU
+use a static configuration which is set up during system start.  SMP is not
+supported.
+
+**Architecture Documents**
+
+For information on the ARM AArch64 architecture refer to the *ARM Infocenter*
+(http://infocenter.arm.com/).
+
+CPU Model Dependent Features
+
+
+This section presents the set of features which vary across ARM AArch64
+implementations and are of importance to RTEMS.  The set of CPU model feature
+macros are defined in the file 
:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
+based upon the particular CPU model flags specified on the compilation command
+line.
+
+CPU Model Name
+--
+
+The macro ``CPU_MODEL_NAME`` is a string which designates the architectural
+level of this CPU model.  See in 
:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
+for the values.
+
+Floating Point Unit and SIMD
+
+
+The Advanced SIMD (NEON) and Floating-point instruction set extension is
+supported and expected to be present since all ARMv8-A CPUs are expected to
+support it as per the *ARMv8-A Programmer's Guide Chapter 7 introduction*
+(https://developer.arm.com/docs/den0024/a/aarch64-floating-point-and-neon). As
+such, ``CPU_HARDWARE_FP`` will always be set to ``TRUE``.
+
+Multilibs
+=
+
+The following multilib variants are available:
+
+#. ``ILP32``: AArch64 instruction set and registers using 32bit long int and 
pointers
+
+#. ``LP64``: AArch64 instruction set and registers using 64bit long int and 
pointers
+
+Use for example the following GCC options:
+
+.. code-block:: shell
+
+-mcpu=cortex-a53 -mabi=ilp32
+
+to build an application or BSP for the ARMv8-A architecture and tune the code
+for a Cortex-A53 processor.  It is important to select the correct ABI.
+
+Calling Conventions
+===
+
+Please refer to the *Procedure Call Standard for the ARM 64-bit Architecture*
+(https://github.com/ARM-software/abi-aa/releases/download/2019Q4/aapcs64.pdf).
+
+Memory Model
+
+
+A flat 64-bit or 32-bit memory model is supported depending on the selected 
multilib
+variant.  All AArch64 CPU variants support a built-in MMU for which basic 
initialization
+for a flat memory model is handled.
+
+Interrupt Processing
+
+
+The Reset Vector is determined using RVBAR and is Read-Only. RVBAR is set using
+configuration signals only sampled at reset.  The ARMv8 architecture has four
+exception types: 
+
+- Synchronous Exception
+
+- Interrupt (IRQ)
+
+- Fast Interrupt (FIQ)
+
+- System Error Exception
+
+Of these types only the synchronous and IRQ exceptions have explicit operating
+system support.  It is intentional that the FIQ is not supported by the 
operating
+system.  Without operating system support for the FIQ it is not necessary to
+disable them during critical sections of the system.
+
+Interrupt Levels
+
+
+There are exactly two interrupt levels on ARMv8 with respect to RTEMS.  Level
+zero corresponds to interrupts enabled.  Level one corresponds to interrupts
+disabled.
+
+Interrupt Stack
+---
+
+The board support package must initialize the interrupt stack. The memory for
+the stacks is usually reserved in the linker script.
+
+Default Fatal Error Processing
+==
+
+The default fatal error handler for this architecture performs the following
+actions:
+
+- disables operating system supported interrupts (IRQ),
+
+- places the error code in ``x0``, and
+
+- executes an infinite loop to simulate a halt processor instruction.
+
+Symmetric Multiprocessing
+=
+
+SMP is not currently supported on ARMv8-A.
+
+Thread-Local Storage
+
+
+Thread-local storage (TLS) is supported. AArch64 uses unmodified TLS variant I
+which is not explcitly stated, but can be inferred from the behavior of GCC and
+*Addenda to, and Errata in, the ABI for the Arm® Architecture*
+(https://developer.arm.com/documentation/ihi0045/g). This alters expectations
+for the size of the TLS Thread Control Block (TCB) such that, under the 

[PATCH v4 4/9] bsps: Break out AArch32 GICv3 support

[Kinsey Moore]

644
--- a/bsps/arm/realview-pbx-a9/include/tm27.h
+++ b/bsps/arm/realview-pbx-a9/include/tm27.h
@@ -36,6 +36,6 @@
 #ifndef __tm27_h
 #define __tm27_h
 
-#include 
+#include 
 
 #endif /* __tm27_h */
diff --git a/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c 
b/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
new file mode 100644
index 00..b805199ba9
--- /dev/null
+++ b/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief ARM-specific IRQ handlers.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+void arm_interrupt_handler_dispatch(rtems_vector_number vector)
+{
+  uint32_t psr = _ARMV4_Status_irq_enable();
+  bsp_interrupt_handler_dispatch(vector);
+
+  _ARMV4_Status_restore(psr);
+}
+
+void arm_interrupt_facility_set_exception_handler(void)
+{
+  arm_cp15_set_exception_handler(
+ARM_EXCEPTION_IRQ,
+_ARMV4_Exception_interrupt
+  );
+}
+
+void bsp_interrupt_dispatch(void)
+{
+  gicv3_interrupt_dispatch();
+}
diff --git a/bsps/arm/shared/irq/irq-gic.c b/bsps/arm/shared/irq/irq-gic.c
index 42ae6c4d7d..1a401b67b6 100644
--- a/bsps/arm/shared/irq/irq-gic.c
+++ b/bsps/arm/shared/irq/irq-gic.c
@@ -12,7 +12,7 @@
  * http://www.rtems.org/license/LICENSE.
  */
 
-#include 
+#include 
 
 #include 
 
diff --git a/bsps/arm/xen/include/bsp/irq.h b/bsps/arm/xen/include/bsp/irq.h
index dc09e52373..a147a1c079 100644
--- a/bsps/arm/xen/include/bsp/irq.h
+++ b/bsps/arm/xen/include/bsp/irq.h
@@ -34,7 +34,7 @@
 #include 
 #include 
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xen/include/tm27.h b/bsps/arm/xen/include/tm27.h
index 2fc4afa4f2..4c1dfaa213 100644
--- a/bsps/arm/xen/include/tm27.h
+++ b/bsps/arm/xen/include/tm27.h
@@ -33,6 +33,6 @@
 #ifndef __tm27_h
 #define __tm27_h
 
-#include 
+#include 
 
 #endif /* __tm27_h */
diff --git a/bsps/arm/xilinx-zynq/include/bsp/irq.h 
b/bsps/arm/xilinx-zynq/include/bsp/irq.h
index edea29b7df..e707337fa1 100644
--- a/bsps/arm/xilinx-zynq/include/bsp/irq.h
+++ b/bsps/arm/xilinx-zynq/include/bsp/irq.h
@@ -40,7 +40,7 @@
 #include 
 
 #include 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xilinx-zynq/include/tm27.h 
b/bsps/arm/xilinx-zynq/include/tm27.h
index 885b97a30c..7fc8dd7edd 100644
--- a/bsps/arm/xilinx-zynq/include/tm27.h
+++ b/bsps/arm/xilinx-zynq/include/tm27.h
@@ -44,6 +44,6 @@
  * @brief Interrupt Mechanisms for tm27 test
  */
 
-#include 
+#include 
 
 #endif /* __tm27_h */
diff --git a/bsps/arm/xilinx-zynqmp/include/bsp/irq.h 
b/bsps/arm/xilinx-zynqmp/include/bsp/irq.h
index 73567da011..6496d2312e 100644
--- a/bsps/arm/xilinx-zynqmp/include/bsp/irq.h
+++ b/bsps/arm/xilinx-zynqmp/include/bsp/irq.h
@@ -44,7 +44,7 @@
 #include 
 #include 
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xilinx-zynqmp/include/tm27.h 
b/bsps/arm/xilinx-zynqmp/include/tm27.h
index 0f02a3b195..14214fe151 100644
--- a/bsps/arm/xilinx-zynqmp/include/tm27.h
+++ b/bsps/arm/xilinx-zynqmp/include/tm27.h
@@ -49,6 +49,6 @@
  * @brief Interrupt Mechanisms for tm27 test
  */
 
-#include 
+#include 
 
 #endif /* __tm27_h */
diff --git a/bsps/headers.am b/bsps/headers.am
index aaf13284bd..b433c2d8d4 100644
--- a/bsps/headers.am
+++ b/bsps/headers.am
@@ -21,6 +21,13 @@ include_bsp_HEADERS += ../../bsps/include/bsp/u-boot.h
 include_bsp_HEADERS += ../../bsps/include/bsp/uart-output-char.h
 include_bsp_HEADERS += ../../bsps/inclu

[PATCH v5 1/2] cpu-supplement: Fix formatting and missing words

[Kinsey Moore]

---
 cpu-supplement/arm.rst | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/cpu-supplement/arm.rst b/cpu-supplement/arm.rst
index 63aa532..ac9e8c6 100644
--- a/cpu-supplement/arm.rst
+++ b/cpu-supplement/arm.rst
@@ -34,10 +34,10 @@ for the values.
 Count Leading Zeroes Instruction
 
 
-The ARMv5 and later has the count leading zeroes ``clz`` instruction which
-could be used to speed up the find first bit operation.  The use of this
-instruction should significantly speed up the scheduling associated with a
-thread blocking.  This is currently not used.
+The ARMv5 and later instruction sets have the count leading zeroes ``clz``
+instruction which could be used to speed up the find first bit operation. The
+use of this instruction should significantly speed up the scheduling associated
+with a thread blocking.  This is currently not used.
 
 Floating Point Unit
 ---
@@ -130,7 +130,7 @@ Memory Model
 
 
 A flat 32-bit memory model is supported.  The board support package must take
-care about the MMU if necessary.
+care of initializing the MMU if necessary.
 
 Interrupt Processing
 
@@ -194,13 +194,13 @@ actions:
 Symmetric Multiprocessing
 =
 
-SMP is supported on ARMv7-A.  Available platforms are
+SMP is supported on ARMv7-A.  Available platforms are:
 
-- Altera Cyclone V,
+- Altera Cyclone V
 
-- NXP i.MX 7, and
+- NXP i.MX 7
 
-- Xilinx Zynq.
+- Xilinx Zynq
 
 Thread-Local Storage
 
-- 
2.20.1

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[PATCH v4 2/9] spec: Add missing spintrcritical24 definition

[Kinsey Moore]

---
 spec/build/bsps/tstnointrcrit.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/spec/build/bsps/tstnointrcrit.yml 
b/spec/build/bsps/tstnointrcrit.yml
index 0460aaabb3..46f7d974c8 100644
--- a/spec/build/bsps/tstnointrcrit.yml
+++ b/spec/build/bsps/tstnointrcrit.yml
@@ -24,6 +24,7 @@ actions:
 spintrcritical21: exclude
 spintrcritical22: exclude
 spintrcritical23: exclude
+spintrcritical24: exclude
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-- 
2.20.1

___
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[PATCH v4 3/9] bsps: Break out AArch32 portions of GPT driver

[Kinsey Moore]

This breaks AArch32-specific portions of the ARM GPT driver into their
own file so that the generic code can be moved for reuse by other
architectures.
---
 bsps/arm/imx/headers.am   |  4 +
 bsps/arm/imx/include/bsp.h|  2 -
 bsps/arm/imx/start/bspstart.c |  1 +
 .../shared/clock/arm-generic-timer-aarch32.c  | 76 +++
 bsps/arm/xen/headers.am   |  4 +
 bsps/arm/xen/include/bsp.h|  2 -
 bsps/arm/xen/start/bspstart.c |  1 +
 bsps/arm/xilinx-zynqmp/headers.am |  4 +
 bsps/arm/xilinx-zynqmp/include/bsp.h  |  2 -
 bsps/arm/xilinx-zynqmp/start/bspstart.c   |  1 +
 bsps/include/dev/clock/arm-generic-timer.h| 76 +++
 .../dev/clock/arm-generic-timer.c}| 43 +--
 c/src/lib/libbsp/arm/imx/Makefile.am  |  3 +-
 c/src/lib/libbsp/arm/xen/Makefile.am  |  3 +-
 .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am  |  3 +-
 spec/build/bsps/arm/imx/bspimx.yml|  6 +-
 spec/build/bsps/arm/xen/bspxen.yml|  6 +-
 .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml |  6 +-
 18 files changed, 191 insertions(+), 52 deletions(-)
 create mode 100644 bsps/arm/shared/clock/arm-generic-timer-aarch32.c
 create mode 100644 bsps/include/dev/clock/arm-generic-timer.h
 rename bsps/{arm/shared/clock/clock-generic-timer.c => 
shared/dev/clock/arm-generic-timer.c} (79%)

diff --git a/bsps/arm/imx/headers.am b/bsps/arm/imx/headers.am
index 3a093b1698..9863f34300 100644
--- a/bsps/arm/imx/headers.am
+++ b/bsps/arm/imx/headers.am
@@ -21,3 +21,7 @@ include_bspdir = $(includedir)/bsp
 include_bsp_HEADERS =
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/imx-gpio.h
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/irq.h
+
+include_dev_clockdir = $(includedir)/dev/clock
+include_dev_clock_HEADERS =
+include_dev_clock_HEADERS += 
../../../../../../bsps/include/dev/clock/arm-generic-timer.h
diff --git a/bsps/arm/imx/include/bsp.h b/bsps/arm/imx/include/bsp.h
index 134b3fd858..99b7a0d1d7 100644
--- a/bsps/arm/imx/include/bsp.h
+++ b/bsps/arm/imx/include/bsp.h
@@ -57,8 +57,6 @@ extern uintptr_t imx_gic_dist_base;
 
 #define BSP_ARM_A9MPCORE_SCU_BASE 0
 
-void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq);
-
 void *imx_get_reg_of_node(const void *fdt, int node);
 
 int imx_iomux_configure_pins(const void *fdt, uint32_t phandle);
diff --git a/bsps/arm/imx/start/bspstart.c b/bsps/arm/imx/start/bspstart.c
index 5fb07bf60a..9f610d1ff5 100644
--- a/bsps/arm/imx/start/bspstart.c
+++ b/bsps/arm/imx/start/bspstart.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
diff --git a/bsps/arm/shared/clock/arm-generic-timer-aarch32.c 
b/bsps/arm/shared/clock/arm-generic-timer-aarch32.c
new file mode 100644
index 00..d242c116ac
--- /dev/null
+++ b/bsps/arm/shared/clock/arm-generic-timer-aarch32.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief ARM-specific clock driver functions.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+uint64_t arm_gt_clock_get_compare_value(void)
+{
+#ifdef ARM_GENERIC_TIMER_USE_VIRTUAL
+  return arm_cp15_get_counter_pl1_virtual_compare_value();
+#else
+  return arm_cp15_get_counter_pl1_physical_compare_value();
+#endif
+}
+
+void arm_gt_clock_set_compare_value(uint64_t cval)
+{
+#ifdef ARM_GENERIC_TIMER_USE_VIRTUAL
+  arm_cp15_set_counter_pl1_virtual_compa

[PATCH v4 9/9] bsps: Add Cortex-A53 ILP32 BSP variant

[Kinsey Moore]

This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53
emulation with interrupt support using GICv3 and clock support using
the ARM GPT.
---
 bsps/aarch64/shared/start/start.S | 16 +
 spec/build/bsps/aarch64/a53/abi.yml   |  7 +-
 .../bsps/aarch64/a53/bspa53ilp32qemu.yml  | 19 +
 .../build/bsps/aarch64/a53/linkcmds_ilp32.yml | 71 +++
 4 files changed, 112 insertions(+), 1 deletion(-)
 create mode 100644 spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml
 create mode 100644 spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml

diff --git a/bsps/aarch64/shared/start/start.S 
b/bsps/aarch64/shared/start/start.S
index f60e840137..f4c62b2b6c 100644
--- a/bsps/aarch64/shared/start/start.S
+++ b/bsps/aarch64/shared/start/start.S
@@ -101,19 +101,31 @@ _start:
  * Get current per-CPU control and store it in PL1 only Thread ID
  * Register (TPIDRPRW).
  */
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w1, =_Per_CPU_Information
+#else
ldr x1, =_Per_CPU_Information
+#endif
add x1, x1, x7, asl #PER_CPU_CONTROL_SIZE_LOG2
mcr p15, 0, x1, c13, c0, 4
 
 #endif
 
/* Calculate interrupt stack area end for current processor */
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w1, =_ISR_Stack_size
+#else
ldr x1, =_ISR_Stack_size
+#endif
 #ifdef RTEMS_SMP
add x3, x7, #1
mul x1, x1, x3
 #endif
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w2, =_ISR_Stack_area_begin
+#else
ldr x2, =_ISR_Stack_area_begin
+#endif
add x3, x1, x2
 
/* Save original DAIF value */
@@ -135,7 +147,11 @@ _start:
 * Normal operation for RTEMS on AArch64 uses SPx and runs on EL1
 * Exception operation (synchronous errors, IRQ, FIQ, System Errors) 
uses SP0
*/
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w1, =bsp_stack_exception_size
+#else
ldr x1, =bsp_stack_exception_size
+#endif
/* Switch to SP0 and set exception stack */
msr spsel, #0
mov sp, x3
diff --git a/spec/build/bsps/aarch64/a53/abi.yml 
b/spec/build/bsps/aarch64/a53/abi.yml
index 894839aa24..b65c10981e 100644
--- a/spec/build/bsps/aarch64/a53/abi.yml
+++ b/spec/build/bsps/aarch64/a53/abi.yml
@@ -8,7 +8,12 @@ copyrights:
 - Copyright (C) 2020 On-Line Applications Research (OAR)
 default:
 - -mcpu=cortex-a53
-default-by-variant: []
+default-by-variant:
+- value:
+  - -mcpu=cortex-a53
+  - -mabi=ilp32
+  variants:
+  - aarch64/a53_ilp32_qemu
 enabled-by: true
 links: []
 name: ABI_FLAGS
diff --git a/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml 
b/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml
new file mode 100644
index 00..019e97fcb3
--- /dev/null
+++ b/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: aarch64
+bsp: a53_ilp32_qemu
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2020 On-Line Applications Research (OAR)
+cppflags: []
+enabled-by: true
+family: a53
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: grp
+- role: build-dependency
+  uid: linkcmds_ilp32
+source: []
+type: build
diff --git a/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml 
b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
new file mode 100644
index 00..ed585f1950
--- /dev/null
+++ b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
@@ -0,0 +1,71 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: config-file
+content: |
+  /*
+   * SPDX-License-Identifier: BSD-2-Clause
+   *
+   * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+   * Written by Kinsey Moore 
+   *
+   * Redistribution and use in source and binary forms, with or without
+   * modification, are permitted provided that the following conditions
+   * are met:
+   * 1. Redistributions of source code must retain the above copyright
+   *notice, this list of conditions and the following disclaimer.
+   * 2. Redistributions in binary form must reproduce the above copyright
+   *notice, this list of conditions and the following disclaimer in the
+   *documentation and/or other materials provided with the distribution.
+   *
+   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
IS"
+   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 

[PATCH v4 1/9] Move ARM PL011 UART driver

[Kinsey Moore]

This UART driver is now needed for BSPs other than ARM.
---
 bsps/arm/headers.am  | 2 --
 bsps/arm/raspberrypi/console/console-config.c| 2 +-
 bsps/arm/realview-pbx-a9/include/bsp/console.h   | 2 +-
 bsps/arm/xen/console/console.c   | 2 +-
 bsps/headers.am  | 5 +
 .../{arm/include/bsp => include/dev/serial}/arm-pl011-regs.h | 0
 bsps/{arm/include/bsp => include/dev/serial}/arm-pl011.h | 2 +-
 bsps/{arm/shared => shared/dev}/serial/arm-pl011.c   | 2 +-
 c/src/lib/libbsp/arm/raspberrypi/Makefile.am | 2 +-
 c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am | 2 +-
 c/src/lib/libbsp/arm/xen/Makefile.am | 2 +-
 spec/build/bsps/arm/grp.yml  | 2 --
 spec/build/bsps/arm/raspberrypi/obj.yml  | 1 -
 spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml | 1 -
 spec/build/bsps/arm/xen/bspxen.yml   | 1 -
 spec/build/bsps/obj.yml  | 5 +
 16 files changed, 18 insertions(+), 15 deletions(-)
 rename bsps/{arm/include/bsp => include/dev/serial}/arm-pl011-regs.h (100%)
 rename bsps/{arm/include/bsp => include/dev/serial}/arm-pl011.h (96%)
 rename bsps/{arm/shared => shared/dev}/serial/arm-pl011.c (98%)

diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am
index 3d2b09effa..f0d498c8f4 100644
--- a/bsps/arm/headers.am
+++ b/bsps/arm/headers.am
@@ -21,8 +21,6 @@ include_bsp_HEADERS += 
../../../../../bsps/arm/include/bsp/arm-gic-irq.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-tm27.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011-regs.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl111-fb.h
diff --git a/bsps/arm/raspberrypi/console/console-config.c 
b/bsps/arm/raspberrypi/console/console-config.c
index bb0b596019..6b8eb80aa4 100644
--- a/bsps/arm/raspberrypi/console/console-config.c
+++ b/bsps/arm/raspberrypi/console/console-config.c
@@ -25,13 +25,13 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/bsps/arm/realview-pbx-a9/include/bsp/console.h 
b/bsps/arm/realview-pbx-a9/include/bsp/console.h
index da2e4099e2..2019fc2509 100644
--- a/bsps/arm/realview-pbx-a9/include/bsp/console.h
+++ b/bsps/arm/realview-pbx-a9/include/bsp/console.h
@@ -15,7 +15,7 @@
 #ifndef LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 #define LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xen/console/console.c b/bsps/arm/xen/console/console.c
index 786b98f3ba..05eceae438 100644
--- a/bsps/arm/xen/console/console.c
+++ b/bsps/arm/xen/console/console.c
@@ -29,7 +29,7 @@
 #include 
 
 #include 
-#include 
+#include 
 #include 
 #include 
 
diff --git a/bsps/headers.am b/bsps/headers.am
index 5af7e43b4a..aaf13284bd 100644
--- a/bsps/headers.am
+++ b/bsps/headers.am
@@ -21,6 +21,11 @@ include_bsp_HEADERS += ../../bsps/include/bsp/u-boot.h
 include_bsp_HEADERS += ../../bsps/include/bsp/uart-output-char.h
 include_bsp_HEADERS += ../../bsps/include/bsp/utility.h
 
+include_dev_serialdir = $(includedir)/dev/serial
+include_dev_serial_HEADERS =
+include_dev_serial_HEADERS += ../../bsps/include/dev/serial/arm-pl011-regs.h
+include_dev_serial_HEADERS += ../../bsps/include/dev/serial/arm-pl011.h
+
 include_grlibdir = $(includedir)/grlib
 include_grlib_HEADERS =
 include_grlib_HEADERS += ../../bsps/include/grlib/ahbstat.h
diff --git a/bsps/arm/include/bsp/arm-pl011-regs.h 
b/bsps/include/dev/serial/arm-pl011-regs.h
similarity index 100%
rename from bsps/arm/include/bsp/arm-pl011-regs.h
rename to bsps/include/dev/serial/arm-pl011-regs.h
diff --git a/bsps/arm/include/bsp/arm-pl011.h 
b/bsps/include/dev/serial/arm-pl011.h
similarity index 96%
rename from bsps/arm/include/bsp/arm-pl011.h
rename to bsps/include/dev/serial/arm-pl011.h
index 49ff413581..c7e65656a3 100644
--- a/bsps/arm/include/bsp/arm-pl011.h
+++ b/bsps/include/dev/serial/arm-pl011.h
@@ -25,7 +25,7 @@
 
 #include 
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/shared/serial/arm-pl011.c 
b/bsps/shared/dev/serial/arm-pl011.c
similarity index 98%
rename from bsps/arm/shared/serial/arm-pl011.c
rename to bsps/shared/dev/serial/arm-pl011.c
index 44a409e551..c3cbab6f3e 100644
--- a/bsps/arm/shared/serial/arm-pl011.c
+++ 

RE: [PATCH v3 04/10] bsps: Break out AArch32 GICv3 support

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Monday, October 5, 2020 08:10
To: j...@rtems.org
Cc: Kinsey Moore ; rtems-de...@rtems.org 

Subject: Re: [PATCH v3 04/10] bsps: Break out AArch32 GICv3 support

On 05/10/2020 14:27, Joel Sherrill wrote:

>
>
> On Mon, Oct 5, 2020 at 2:04 AM Sebastian Huber 
>  <mailto:sebastian.hu...@embedded-brains.de>> wrote:
>
> On 04/10/2020 06:18, Kinsey Moore wrote:
>
> > +/**
> > + * This architecture-specific function sets the exception
> vector for handling
> > + * IRQs.
> > + */
> > +void aarch_interrupt_facility_set_exception_handler(void);
> What are the rules for using an aarch prefix instead of an arm prefix?
>
>
> I haven't talked to Kinsey about this but I would assume based on the 
> terminology I see in ARM documentation.
>
> + arm - only 32-bit. Now referred to as aarch32 or A32
> + aarch64 - only 64-bit. AKA A64
> + aarch - shared across 32 and 64 bit modes.
>
> Looks like Microsoft also uses ARM32 and ARM64
Linux uses "arm" and "arm64". You find some aarch32 stuff in "arch/arm64" but 
not in "arch/arm". I think we should do the same. 
Existing and shared stuff between "arm" and "aarch64" should just use "arm".
[] 
Joel was correct as to my reasoning behind using that prefix. It sounds like 
arm_ is the preferred prefix for shared code in that vein, so I'll swap the 
relevant patches over to that instead of aarch_.

Kinsey
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RE: [PATCH v3 2/2] Add AArch64 documentation

[Kinsey Moore]

-Original Message-
From: Gedare Bloom  
Sent: Monday, October 5, 2020 10:19
To: Kinsey Moore 
Cc: devel@rtems.org
Subject: Re: [PATCH v3 2/2] Add AArch64 documentation

On Mon, Oct 5, 2020 at 9:13 AM Gedare Bloom  wrote:
>
> On Sat, Oct 3, 2020 at 10:23 PM Kinsey Moore  wrote:
> >
> > ---
> >  cpu-supplement/aarch64.rst | 134 
> > +
> >  user/bsps/aarch64/a53.rst  |  26 +++
> >  user/bsps/bsps-aarch64.rst |   2 +-
> >  3 files changed, 161 insertions(+), 1 deletion(-)  create mode 
> > 100644 cpu-supplement/aarch64.rst  create mode 100644 
> > user/bsps/aarch64/a53.rst
> >
> > diff --git a/cpu-supplement/aarch64.rst b/cpu-supplement/aarch64.rst 
> > new file mode 100644 index 000..178ea10
> > --- /dev/null
> > +++ b/cpu-supplement/aarch64.rst
> > @@ -0,0 +1,134 @@
> > +.. SPDX-License-Identifier: CC-BY-SA-4.0
> > +
> > +.. Copyright (C) 1988, 2020 On-Line Applications Research 
> > +Corporation (OAR)
> > +
> > +AArch64 Specific Information
> > +
> > +
> > +This chapter discusses the dependencies of the *ARM AArch64 
> > +architecture*
> > +(https://en.wikipedia.org/wiki/ARM_architecture#AArch64_features) 
> > +in this port of RTEMS.  The ARMv8-A versions are supported by 
> > +RTEMS.  Processors with a MMU use a static configuration which is 
> > +set up during system start.  SMP is not supported.
> > +
> > +**Architecture Documents**
> > +
> > +For information on the ARM AArch64 architecture refer to the *ARM 
> > +Infocenter* (http://infocenter.arm.com/).
> > +
> > +CPU Model Dependent Features
> > +
> > +
> > +This section presents the set of features which vary across ARM 
> > +AArch64 implementations and are of importance to RTEMS.  The set of 
> > +CPU model feature macros are defined in the file 
> > +:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
> > +based upon the particular CPU model flags specified on the 
> > +compilation command line.
> > +
> > +CPU Model Name
> > +--
> > +
> > +The macro ``CPU_MODEL_NAME`` is a string which designates the 
> > +architectural level of this CPU model.  See in 
> > +:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
> > +for the values.
> > +
> > +Floating Point Unit and SIMD
> > +
> > +
> > +The Advanced SIMD (NEON) and Floating-point instruction set 
> > +extension is supported and expected to be present since all ARMv8-A 
> > +CPUs are expected to support it as per the *ARMv8-A Programmer's 
> > +Guide Chapter 7 introduction* 
> > +(https://developer.arm.com/docs/den0024/a/aarch64-floating-point-and-neon).
> >  As such, ``CPU_HARDWARE_FP`` will always be set to ``TRUE``.
> > +
> > +Multilibs
> > +=
> > +
> > +The following multilib variants are available:
> > +
> > +#. ``ILP32``: AArch64 instruction set and registers using 32bit 
> > +long int and pointers
> > +
> > +#. ``LP64``: AArch64 instruction set and registers using 64bit long 
> > +int and pointers
> > +
> > +Use for example the following GCC options:
> > +
> > +.. code-block:: shell
> > +
> > +-mcpu=cortex-a53 -mabi=ilp32
> > +
> > +to build an application or BSP for the ARMv8-A architecture and 
> > +tune the code for a Cortex-A53 processor.  It is important to select the 
> > correct ABI.
> > +
> > +Calling Conventions
> > +===
> > +
> > +Please refer to the *Procedure Call Standard for the ARM 64-bit 
> > +Architecture* 
> > (https://github.com/ARM-software/abi-aa/releases/download/2019Q4/aapcs64.pdf).
> > +
> > +Memory Model
> > +
> > +
> > +A flat 64-bit or 32-bit memory model is supported depending on the 
> > +selected multilib variant.  All AArch64 CPU variants support a 
> > +built-in MMU for which basic initialization for a flat memory model is 
> > handled.
> > +
> > +Interrupt Processing
> > +
> > +
> > +The Reset Vector is determined using RVBAR and is Read-Only. RVBAR 
> > +is set using configuration signals only sampled at reset.  The 
> > +ARMv8 architecture has four exception types:
> > +
> > +- Synchronous Exception
> > +
> > +- Interrupt (IRQ)
> > +
> > +- Fast Interrupt (FIQ)
> > +
> > +- System Error Exception
> > +
> > +Of these types only the synchronous and IRQ except

RE: [PATCH v3 06/10] bsps/arm: Break out linker script for AArch64

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Monday, October 5, 2020 02:11
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH v3 06/10] bsps/arm: Break out linker script for AArch64

On 04/10/2020 06:18, Kinsey Moore wrote:

> This breaks out the common section of the ARM linker script that is 
> usable by AArch64 BSPs to avoid duplication of the vast majority. To 
> do so, it was necessary to add a new linker path at bsps/shared/start.
Sorry, I didn't consider that using a linker script shared by different 
architectures requires a new library path in the build. I think in this case I 
would prefer a copy and paste linkcmds.base. One for arm and one for aarch64.
[] 
Oh well, on the plus side, undoing this change will be much more trivial than 
doing/testing it was in the first place.

Kinsey
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[PATCH v4 2/2] Add AArch64 documentation

[Kinsey Moore]

---
 cpu-supplement/aarch64.rst | 134 +
 user/bsps/aarch64/a53.rst  |  26 +++
 user/bsps/bsps-aarch64.rst |   2 +-
 3 files changed, 161 insertions(+), 1 deletion(-)
 create mode 100644 cpu-supplement/aarch64.rst
 create mode 100644 user/bsps/aarch64/a53.rst

diff --git a/cpu-supplement/aarch64.rst b/cpu-supplement/aarch64.rst
new file mode 100644
index 000..178ea10
--- /dev/null
+++ b/cpu-supplement/aarch64.rst
@@ -0,0 +1,134 @@
+.. SPDX-License-Identifier: CC-BY-SA-4.0
+
+.. Copyright (C) 1988, 2020 On-Line Applications Research Corporation (OAR)
+
+AArch64 Specific Information
+
+
+This chapter discusses the dependencies of the
+*ARM AArch64 architecture*
+(https://en.wikipedia.org/wiki/ARM_architecture#AArch64_features) in this port
+of RTEMS.  The ARMv8-A versions are supported by RTEMS.  Processors with a MMU
+use a static configuration which is set up during system start.  SMP is not
+supported.
+
+**Architecture Documents**
+
+For information on the ARM AArch64 architecture refer to the *ARM Infocenter*
+(http://infocenter.arm.com/).
+
+CPU Model Dependent Features
+
+
+This section presents the set of features which vary across ARM AArch64
+implementations and are of importance to RTEMS.  The set of CPU model feature
+macros are defined in the file 
:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
+based upon the particular CPU model flags specified on the compilation command
+line.
+
+CPU Model Name
+--
+
+The macro ``CPU_MODEL_NAME`` is a string which designates the architectural
+level of this CPU model.  See in 
:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
+for the values.
+
+Floating Point Unit and SIMD
+
+
+The Advanced SIMD (NEON) and Floating-point instruction set extension is
+supported and expected to be present since all ARMv8-A CPUs are expected to
+support it as per the *ARMv8-A Programmer's Guide Chapter 7 introduction*
+(https://developer.arm.com/docs/den0024/a/aarch64-floating-point-and-neon). As
+such, ``CPU_HARDWARE_FP`` will always be set to ``TRUE``.
+
+Multilibs
+=
+
+The following multilib variants are available:
+
+#. ``ILP32``: AArch64 instruction set and registers using 32bit long int and 
pointers
+
+#. ``LP64``: AArch64 instruction set and registers using 64bit long int and 
pointers
+
+Use for example the following GCC options:
+
+.. code-block:: shell
+
+-mcpu=cortex-a53 -mabi=ilp32
+
+to build an application or BSP for the ARMv8-A architecture and tune the code
+for a Cortex-A53 processor.  It is important to select the correct ABI.
+
+Calling Conventions
+===
+
+Please refer to the *Procedure Call Standard for the ARM 64-bit Architecture*
+(https://github.com/ARM-software/abi-aa/releases/download/2019Q4/aapcs64.pdf).
+
+Memory Model
+
+
+A flat 64-bit or 32-bit memory model is supported depending on the selected 
multilib
+variant.  All AArch64 CPU variants support a built-in MMU for which basic 
initialization
+for a flat memory model is handled.
+
+Interrupt Processing
+
+
+The Reset Vector is determined using RVBAR and is Read-Only. RVBAR is set using
+configuration signals only sampled at reset.  The ARMv8 architecture has four
+exception types: 
+
+- Synchronous Exception
+
+- Interrupt (IRQ)
+
+- Fast Interrupt (FIQ)
+
+- System Error Exception
+
+Of these types only the synchronous and IRQ exceptions have explicit operating
+system support.  It is intentional that the FIQ is not supported by the 
operating
+system.  Without operating system support for the FIQ it is not necessary to
+disable them during critical sections of the system.
+
+Interrupt Levels
+
+
+There are exactly two interrupt levels on ARMv8 with respect to RTEMS.  Level
+zero corresponds to interrupts enabled.  Level one corresponds to interrupts
+disabled.
+
+Interrupt Stack
+---
+
+The board support package must initialize the interrupt stack. The memory for
+the stacks is usually reserved in the linker script.
+
+Default Fatal Error Processing
+==
+
+The default fatal error handler for this architecture performs the following
+actions:
+
+- disables operating system supported interrupts (IRQ),
+
+- places the error code in ``x0``, and
+
+- executes an infinite loop to simulate a halt processor instruction.
+
+Symmetric Multiprocessing
+=
+
+SMP is not currently supported on ARMv8-A.
+
+Thread-Local Storage
+
+
+Thread-local storage (TLS) is supported. AArch64 uses unmodified TLS variant I
+which is not explcitly stated, but can be inferred from the behavior of GCC and
+*Addenda to, and Errata in, the ABI for the Arm® Architecture*
+(https://developer.arm.com/documentation/ihi0045/g). This alters expectations
+for the size of the TLS Thread Control Block (TCB) such that, under the 

[PATCH v4 1/2] cpu-supplement: Fix formatting and missing words

[Kinsey Moore]

---
 cpu-supplement/arm.rst | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/cpu-supplement/arm.rst b/cpu-supplement/arm.rst
index 63aa532..ac9e8c6 100644
--- a/cpu-supplement/arm.rst
+++ b/cpu-supplement/arm.rst
@@ -34,10 +34,10 @@ for the values.
 Count Leading Zeroes Instruction
 
 
-The ARMv5 and later has the count leading zeroes ``clz`` instruction which
-could be used to speed up the find first bit operation.  The use of this
-instruction should significantly speed up the scheduling associated with a
-thread blocking.  This is currently not used.
+The ARMv5 and later instruction sets have the count leading zeroes ``clz``
+instruction which could be used to speed up the find first bit operation. The
+use of this instruction should significantly speed up the scheduling associated
+with a thread blocking.  This is currently not used.
 
 Floating Point Unit
 ---
@@ -130,7 +130,7 @@ Memory Model
 
 
 A flat 32-bit memory model is supported.  The board support package must take
-care about the MMU if necessary.
+care of initializing the MMU if necessary.
 
 Interrupt Processing
 
@@ -194,13 +194,13 @@ actions:
 Symmetric Multiprocessing
 =
 
-SMP is supported on ARMv7-A.  Available platforms are
+SMP is supported on ARMv7-A.  Available platforms are:
 
-- Altera Cyclone V,
+- Altera Cyclone V
 
-- NXP i.MX 7, and
+- NXP i.MX 7
 
-- Xilinx Zynq.
+- Xilinx Zynq
 
 Thread-Local Storage
 
-- 
2.20.1

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[PATCH v3 1/2] cpu-supplement: Fix formatting and missing words

[Kinsey Moore]

---
 cpu-supplement/arm.rst | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/cpu-supplement/arm.rst b/cpu-supplement/arm.rst
index 63aa532..ac9e8c6 100644
--- a/cpu-supplement/arm.rst
+++ b/cpu-supplement/arm.rst
@@ -34,10 +34,10 @@ for the values.
 Count Leading Zeroes Instruction
 
 
-The ARMv5 and later has the count leading zeroes ``clz`` instruction which
-could be used to speed up the find first bit operation.  The use of this
-instruction should significantly speed up the scheduling associated with a
-thread blocking.  This is currently not used.
+The ARMv5 and later instruction sets have the count leading zeroes ``clz``
+instruction which could be used to speed up the find first bit operation. The
+use of this instruction should significantly speed up the scheduling associated
+with a thread blocking.  This is currently not used.
 
 Floating Point Unit
 ---
@@ -130,7 +130,7 @@ Memory Model
 
 
 A flat 32-bit memory model is supported.  The board support package must take
-care about the MMU if necessary.
+care of initializing the MMU if necessary.
 
 Interrupt Processing
 
@@ -194,13 +194,13 @@ actions:
 Symmetric Multiprocessing
 =
 
-SMP is supported on ARMv7-A.  Available platforms are
+SMP is supported on ARMv7-A.  Available platforms are:
 
-- Altera Cyclone V,
+- Altera Cyclone V
 
-- NXP i.MX 7, and
+- NXP i.MX 7
 
-- Xilinx Zynq.
+- Xilinx Zynq
 
 Thread-Local Storage
 
-- 
2.20.1

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[PATCH v3 2/2] Add AArch64 documentation

[Kinsey Moore]

 the LP64
+multilib variant, the the TCB is 16 bytes in size instead of 8 bytes.
diff --git a/user/bsps/aarch64/a53.rst b/user/bsps/aarch64/a53.rst
new file mode 100644
index 000..0052773
--- /dev/null
+++ b/user/bsps/aarch64/a53.rst
@@ -0,0 +1,26 @@
+.. SPDX-License-Identifier: CC-BY-SA-4.0
+
+.. Copyright (C) 2020 Kinsey Moore, On-Line Applications Research Corporation 
(OAR)
+
+.. _BSP_aarch64_qemu_a53_ilp32:
+.. _BSP_aarch64_qemu_a53_lp64:
+
+Qemu A53
+
+
+This BSP supports two variants, `qemu_a53_ilp32` and `qemu-a53_lp64`. The basic
+hardware initialization is performed by the BSP.
+
+Boot via ELF
+
+The executable image is booted by Qemu in ELF format.
+
+Clock Driver
+
+
+The clock driver uses the `ARM Generic Timer`.
+
+Console Driver
+--
+
+The console driver supports the default Qemu emulated ARM PL011 PrimeCell UART.
diff --git a/user/bsps/bsps-aarch64.rst b/user/bsps/bsps-aarch64.rst
index 4b2e749..319310e 100644
--- a/user/bsps/bsps-aarch64.rst
+++ b/user/bsps/bsps-aarch64.rst
@@ -5,4 +5,4 @@
 aarch64 (AArch64)
 *
 
-There are no AArch64 BSPs yet.
+.. include:: aarch64/a53.rst
-- 
2.20.1

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[PATCH v3 05/10] bsps/shared: Add PSCI-based bspreset implementation

[Kinsey Moore]

This adds a bsp_reset implementation based on the ARM PSCI
specification often present in ARMv8 systems.
---
 bsps/shared/start/bspreset-arm-psci.c | 56 +++
 1 file changed, 56 insertions(+)
 create mode 100644 bsps/shared/start/bspreset-arm-psci.c

diff --git a/bsps/shared/start/bspreset-arm-psci.c 
b/bsps/shared/start/bspreset-arm-psci.c
new file mode 100644
index 00..215be5c9b5
--- /dev/null
+++ b/bsps/shared/start/bspreset-arm-psci.c
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsShared
+ *
+ * @brief PSCI-based BSP reset hook.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+void bsp_reset(void)
+{
+   uint32_t PSCI_FN_SYSTEM_RESET = 0x8409;
+   __asm__ volatile(
+#if defined(AARCH64_MULTILIB_ARCH_V8) || 
defined(AARCH64_MULTILIB_ARCH_V8_ILP32)
+   "mov x0, %0\n"
+#else
+   "mov r0, %0\n"
+#endif
+#ifdef BSP_RESET_SMC
+   "smc #0\n"
+#else
+   "hvc #0\n"
+#endif
+   : : "r" (PSCI_FN_SYSTEM_RESET)
+   );
+}
-- 
2.20.1

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[PATCH v3 10/10] bsps: Add Cortex-A53 ILP32 BSP variant

[Kinsey Moore]

This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53
emulation with interrupt support using GICv3 and clock support using
the ARM GPT.
---
 bsps/aarch64/shared/start/start.S | 16 +
 spec/build/bsps/aarch64/a53/abi.yml   |  7 +-
 .../bsps/aarch64/a53/bspa53ilp32qemu.yml  | 19 +
 .../build/bsps/aarch64/a53/linkcmds_ilp32.yml | 71 +++
 4 files changed, 112 insertions(+), 1 deletion(-)
 create mode 100644 spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml
 create mode 100644 spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml

diff --git a/bsps/aarch64/shared/start/start.S 
b/bsps/aarch64/shared/start/start.S
index f60e840137..f4c62b2b6c 100644
--- a/bsps/aarch64/shared/start/start.S
+++ b/bsps/aarch64/shared/start/start.S
@@ -101,19 +101,31 @@ _start:
  * Get current per-CPU control and store it in PL1 only Thread ID
  * Register (TPIDRPRW).
  */
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w1, =_Per_CPU_Information
+#else
ldr x1, =_Per_CPU_Information
+#endif
add x1, x1, x7, asl #PER_CPU_CONTROL_SIZE_LOG2
mcr p15, 0, x1, c13, c0, 4
 
 #endif
 
/* Calculate interrupt stack area end for current processor */
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w1, =_ISR_Stack_size
+#else
ldr x1, =_ISR_Stack_size
+#endif
 #ifdef RTEMS_SMP
add x3, x7, #1
mul x1, x1, x3
 #endif
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w2, =_ISR_Stack_area_begin
+#else
ldr x2, =_ISR_Stack_area_begin
+#endif
add x3, x1, x2
 
/* Save original DAIF value */
@@ -135,7 +147,11 @@ _start:
 * Normal operation for RTEMS on AArch64 uses SPx and runs on EL1
 * Exception operation (synchronous errors, IRQ, FIQ, System Errors) 
uses SP0
*/
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w1, =bsp_stack_exception_size
+#else
ldr x1, =bsp_stack_exception_size
+#endif
/* Switch to SP0 and set exception stack */
msr spsel, #0
mov sp, x3
diff --git a/spec/build/bsps/aarch64/a53/abi.yml 
b/spec/build/bsps/aarch64/a53/abi.yml
index 894839aa24..b65c10981e 100644
--- a/spec/build/bsps/aarch64/a53/abi.yml
+++ b/spec/build/bsps/aarch64/a53/abi.yml
@@ -8,7 +8,12 @@ copyrights:
 - Copyright (C) 2020 On-Line Applications Research (OAR)
 default:
 - -mcpu=cortex-a53
-default-by-variant: []
+default-by-variant:
+- value:
+  - -mcpu=cortex-a53
+  - -mabi=ilp32
+  variants:
+  - aarch64/a53_ilp32_qemu
 enabled-by: true
 links: []
 name: ABI_FLAGS
diff --git a/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml 
b/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml
new file mode 100644
index 00..019e97fcb3
--- /dev/null
+++ b/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: aarch64
+bsp: a53_ilp32_qemu
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2020 On-Line Applications Research (OAR)
+cppflags: []
+enabled-by: true
+family: a53
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: grp
+- role: build-dependency
+  uid: linkcmds_ilp32
+source: []
+type: build
diff --git a/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml 
b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
new file mode 100644
index 00..ed585f1950
--- /dev/null
+++ b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
@@ -0,0 +1,71 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: config-file
+content: |
+  /*
+   * SPDX-License-Identifier: BSD-2-Clause
+   *
+   * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+   * Written by Kinsey Moore 
+   *
+   * Redistribution and use in source and binary forms, with or without
+   * modification, are permitted provided that the following conditions
+   * are met:
+   * 1. Redistributions of source code must retain the above copyright
+   *notice, this list of conditions and the following disclaimer.
+   * 2. Redistributions in binary form must reproduce the above copyright
+   *notice, this list of conditions and the following disclaimer in the
+   *documentation and/or other materials provided with the distribution.
+   *
+   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
IS"
+   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 

[PATCH v3 09/10] bsps: Add Cortex-A53 LP64 basic BSP

[Kinsey Moore]

This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with
interrupt support using GICv3 and clock support using the ARM GPT.
---
 bsps/aarch64/a53/console/console.c|  69 ++
 bsps/aarch64/a53/include/bsp.h|  74 +++
 bsps/aarch64/a53/include/bsp/irq.h|  67 ++
 bsps/aarch64/a53/include/tm27.h   |  46 ++
 bsps/aarch64/a53/start/bspstart.c |  49 ++
 bsps/aarch64/a53/start/bspstarthooks.c|  50 ++
 bsps/aarch64/include/bsp/linker-symbols.h | 161 +
 bsps/aarch64/include/bsp/start.h  | 189 ++
 bsps/aarch64/shared/cache/cache.c | 616 ++
 .../shared/clock/arm-generic-timer-aarch64.c  | 110 
 .../shared/irq/irq-arm-gicv3-aarch64.c|  64 ++
 bsps/aarch64/shared/start/linkcmds.base   |  46 ++
 bsps/aarch64/shared/start/start.S | 219 +++
 spec/build/bsps/aarch64/a53/abi.yml   |  17 +
 .../build/bsps/aarch64/a53/bspa53lp64qemu.yml |  19 +
 spec/build/bsps/aarch64/a53/grp.yml   |  42 ++
 spec/build/bsps/aarch64/a53/linkcmds_lp64.yml |  71 ++
 spec/build/bsps/aarch64/a53/obj.yml   |  37 ++
 spec/build/bsps/aarch64/a53/optloadoff.yml|  18 +
 spec/build/bsps/aarch64/a53/optnocachelen.yml |  18 +
 spec/build/bsps/aarch64/a53/optramlen.yml |  18 +
 spec/build/bsps/aarch64/a53/optramori.yml |  18 +
 spec/build/bsps/aarch64/a53/tsta53.yml|  44 ++
 spec/build/bsps/aarch64/grp.yml   |  25 +
 spec/build/bsps/aarch64/start.yml |  14 +
 25 files changed, 2101 insertions(+)
 create mode 100644 bsps/aarch64/a53/console/console.c
 create mode 100644 bsps/aarch64/a53/include/bsp.h
 create mode 100644 bsps/aarch64/a53/include/bsp/irq.h
 create mode 100644 bsps/aarch64/a53/include/tm27.h
 create mode 100644 bsps/aarch64/a53/start/bspstart.c
 create mode 100644 bsps/aarch64/a53/start/bspstarthooks.c
 create mode 100644 bsps/aarch64/include/bsp/linker-symbols.h
 create mode 100644 bsps/aarch64/include/bsp/start.h
 create mode 100644 bsps/aarch64/shared/cache/cache.c
 create mode 100644 bsps/aarch64/shared/clock/arm-generic-timer-aarch64.c
 create mode 100644 bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c
 create mode 100644 bsps/aarch64/shared/start/linkcmds.base
 create mode 100644 bsps/aarch64/shared/start/start.S
 create mode 100644 spec/build/bsps/aarch64/a53/abi.yml
 create mode 100644 spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
 create mode 100644 spec/build/bsps/aarch64/a53/grp.yml
 create mode 100644 spec/build/bsps/aarch64/a53/linkcmds_lp64.yml
 create mode 100644 spec/build/bsps/aarch64/a53/obj.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optloadoff.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optnocachelen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramlen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramori.yml
 create mode 100644 spec/build/bsps/aarch64/a53/tsta53.yml
 create mode 100644 spec/build/bsps/aarch64/grp.yml
 create mode 100644 spec/build/bsps/aarch64/start.yml

diff --git a/bsps/aarch64/a53/console/console.c 
b/bsps/aarch64/a53/console/console.c
new file mode 100644
index 00..1854909c98
--- /dev/null
+++ b/bsps/aarch64/a53/console/console.c
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64A53
+ *
+ * @brief Console Configuration
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+arm_pl011_context a53_qemu_vpl011_context = 

[PATCH v3 07/10] spmsgq_err01: Use correct max values and fix 64bit

[Kinsey Moore]

Fix spmsgq_err01 on systems with 64-bit pointers and correct max value
mismatches and inaccuracies that are more noticable on 64-bit systems.
---
 testsuites/sptests/spmsgq_err01/init.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/testsuites/sptests/spmsgq_err01/init.c 
b/testsuites/sptests/spmsgq_err01/init.c
index c68d30da16..9a6a8855be 100644
--- a/testsuites/sptests/spmsgq_err01/init.c
+++ b/testsuites/sptests/spmsgq_err01/init.c
@@ -101,7 +101,7 @@ rtems_task Init(
   /* not enough memory for messages */
   status = rtems_message_queue_create(
 Queue_name[ 1 ],
-SIZE_MAX / ( sizeof( uintptr_t ) + sizeof( CORE_message_queue_Buffer ) ),
+UINT_MAX / ( sizeof( uintptr_t ) + sizeof( CORE_message_queue_Buffer ) ),
 1,
 RTEMS_DEFAULT_ATTRIBUTES,
 _id[ 1 ]
@@ -116,8 +116,8 @@ rtems_task Init(
   /* too large a request for messages */
   status = rtems_message_queue_create(
 Queue_name[ 1 ],
-INT_MAX,
-INT_MAX,
+UINT_MAX,
+SIZE_MAX - sizeof( uintptr_t ) + 1 - sizeof( CORE_message_queue_Buffer ),
 RTEMS_DEFAULT_ATTRIBUTES,
 _id[ 1 ]
   );
-- 
2.20.1

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[PATCH v3 08/10] score: Add AArch64 port

[Kinsey Moore]

This adds a CPU port for AArch64(ARMv8) with support for exceptions and
interrupts.
---
 cpukit/include/rtems/score/tls.h  |   6 +-
 .../cpu/aarch64/aarch64-context-validate.S| 305 ++
 .../aarch64-context-volatile-clobber.S| 100 
 .../cpu/aarch64/aarch64-exception-default.S   | 490 
 .../cpu/aarch64/aarch64-exception-default.c   |  50 ++
 .../aarch64/aarch64-exception-frame-print.c   | 108 
 .../cpu/aarch64/aarch64-exception-interrupt.S | 322 ++
 .../score/cpu/aarch64/aarch64-thread-idle.c   |  47 ++
 cpukit/score/cpu/aarch64/cpu.c| 197 +++
 cpukit/score/cpu/aarch64/cpu_asm.S| 134 +
 .../cpu/aarch64/include/libcpu/vectors.h  | 100 
 cpukit/score/cpu/aarch64/include/rtems/asm.h  |  89 +++
 .../cpu/aarch64/include/rtems/score/aarch64.h |  83 +++
 .../cpu/aarch64/include/rtems/score/cpu.h | 554 ++
 .../cpu/aarch64/include/rtems/score/cpu_irq.h |  50 ++
 .../aarch64/include/rtems/score/cpuatomic.h   |  42 ++
 .../cpu/aarch64/include/rtems/score/cpuimpl.h |  83 +++
 spec/build/cpukit/cpuaarch64.yml  |  36 ++
 spec/build/cpukit/librtemscpu.yml |   2 +
 19 files changed, 2797 insertions(+), 1 deletion(-)
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-validate.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-volatile-clobber.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-interrupt.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-thread-idle.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu_asm.S
 create mode 100644 cpukit/score/cpu/aarch64/include/libcpu/vectors.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/asm.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/aarch64.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpu_irq.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuatomic.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
 create mode 100644 spec/build/cpukit/cpuaarch64.yml

diff --git a/cpukit/include/rtems/score/tls.h b/cpukit/include/rtems/score/tls.h
index 65a49d87be..57063990e7 100644
--- a/cpukit/include/rtems/score/tls.h
+++ b/cpukit/include/rtems/score/tls.h
@@ -85,7 +85,11 @@ typedef struct TLS_Thread_control_block {
   struct TLS_Thread_control_block *tcb;
 #else /* !__i386__ */
   TLS_Dynamic_thread_vector *dtv;
-#if CPU_SIZEOF_POINTER == 4
+/*
+ * GCC under AArch64/LP64 expects a 16 byte TCB at the beginning of the TLS
+ * data segment and indexes into it accordingly for TLS variable addresses.
+ */
+#if CPU_SIZEOF_POINTER == 4 || defined(AARCH64_MULTILIB_ARCH_V8)
   uintptr_t reserved;
 #endif
 #endif /* __i386__ */
diff --git a/cpukit/score/cpu/aarch64/aarch64-context-validate.S 
b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
new file mode 100644
index 00..31c8d5571c
--- /dev/null
+++ b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUAArch64
+ *
+ * @brief Implementation of _CPU_Context_validate
+ *
+ * This file implements _CPU_Context_validate for use in spcontext01.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFT

[PATCH v3 04/10] bsps: Break out AArch32 GICv3 support

[Kinsey Moore]

644
--- a/bsps/arm/realview-pbx-a9/include/tm27.h
+++ b/bsps/arm/realview-pbx-a9/include/tm27.h
@@ -36,6 +36,6 @@
 #ifndef __tm27_h
 #define __tm27_h
 
-#include 
+#include 
 
 #endif /* __tm27_h */
diff --git a/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c 
b/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
new file mode 100644
index 00..2a86201208
--- /dev/null
+++ b/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief ARM-specific IRQ handlers.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+void aarch_interrupt_handler_dispatch(rtems_vector_number vector)
+{
+  uint32_t psr = _ARMV4_Status_irq_enable();
+  bsp_interrupt_handler_dispatch(vector);
+
+  _ARMV4_Status_restore(psr);
+}
+
+void aarch_interrupt_facility_set_exception_handler(void)
+{
+  arm_cp15_set_exception_handler(
+ARM_EXCEPTION_IRQ,
+_ARMV4_Exception_interrupt
+  );
+}
+
+void bsp_interrupt_dispatch(void)
+{
+  gicv3_interrupt_dispatch();
+}
diff --git a/bsps/arm/shared/irq/irq-gic.c b/bsps/arm/shared/irq/irq-gic.c
index 42ae6c4d7d..1a401b67b6 100644
--- a/bsps/arm/shared/irq/irq-gic.c
+++ b/bsps/arm/shared/irq/irq-gic.c
@@ -12,7 +12,7 @@
  * http://www.rtems.org/license/LICENSE.
  */
 
-#include 
+#include 
 
 #include 
 
diff --git a/bsps/arm/xen/include/bsp/irq.h b/bsps/arm/xen/include/bsp/irq.h
index dc09e52373..a147a1c079 100644
--- a/bsps/arm/xen/include/bsp/irq.h
+++ b/bsps/arm/xen/include/bsp/irq.h
@@ -34,7 +34,7 @@
 #include 
 #include 
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xen/include/tm27.h b/bsps/arm/xen/include/tm27.h
index 2fc4afa4f2..4c1dfaa213 100644
--- a/bsps/arm/xen/include/tm27.h
+++ b/bsps/arm/xen/include/tm27.h
@@ -33,6 +33,6 @@
 #ifndef __tm27_h
 #define __tm27_h
 
-#include 
+#include 
 
 #endif /* __tm27_h */
diff --git a/bsps/arm/xilinx-zynq/include/bsp/irq.h 
b/bsps/arm/xilinx-zynq/include/bsp/irq.h
index edea29b7df..e707337fa1 100644
--- a/bsps/arm/xilinx-zynq/include/bsp/irq.h
+++ b/bsps/arm/xilinx-zynq/include/bsp/irq.h
@@ -40,7 +40,7 @@
 #include 
 
 #include 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xilinx-zynq/include/tm27.h 
b/bsps/arm/xilinx-zynq/include/tm27.h
index 885b97a30c..7fc8dd7edd 100644
--- a/bsps/arm/xilinx-zynq/include/tm27.h
+++ b/bsps/arm/xilinx-zynq/include/tm27.h
@@ -44,6 +44,6 @@
  * @brief Interrupt Mechanisms for tm27 test
  */
 
-#include 
+#include 
 
 #endif /* __tm27_h */
diff --git a/bsps/arm/xilinx-zynqmp/include/bsp/irq.h 
b/bsps/arm/xilinx-zynqmp/include/bsp/irq.h
index 73567da011..6496d2312e 100644
--- a/bsps/arm/xilinx-zynqmp/include/bsp/irq.h
+++ b/bsps/arm/xilinx-zynqmp/include/bsp/irq.h
@@ -44,7 +44,7 @@
 #include 
 #include 
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xilinx-zynqmp/include/tm27.h 
b/bsps/arm/xilinx-zynqmp/include/tm27.h
index 0f02a3b195..14214fe151 100644
--- a/bsps/arm/xilinx-zynqmp/include/tm27.h
+++ b/bsps/arm/xilinx-zynqmp/include/tm27.h
@@ -49,6 +49,6 @@
  * @brief Interrupt Mechanisms for tm27 test
  */
 
-#include 
+#include 
 
 #endif /* __tm27_h */
diff --git a/bsps/headers.am b/bsps/headers.am
index aaf13284bd..b433c2d8d4 100644
--- a/bsps/headers.am
+++ b/bsps/headers.am
@@ -21,6 +21,13 @@ include_bsp_HEADERS += ../../bsps/include/bsp/u-boot.h
 include_bsp_HEADERS += ../../bsps/include/bsp/uart-output-char.h
 include_bsp_HE

[PATCH v3 06/10] bsps/arm: Break out linker script for AArch64

[Kinsey Moore]

. += ORIGIN (REGION_WORK) + LENGTH (REGION_WORK) - ABSOLUTE (.);
-   bsp_section_work_end = .;
-   } > REGION_WORK AT > REGION_WORK
-   bsp_section_work_size = bsp_section_work_end - bsp_section_work_begin;
-
-   .stack : ALIGN_WITH_INPUT {
-   /*
-* The stack section will occupy the remaining REGION_STACK 
region and may
-* contain the task stacks.  Depending on the region 
distribution this
-* section may be of zero size.
-*/
-   bsp_section_stack_begin = .;
-   . += ORIGIN (REGION_STACK) + LENGTH (REGION_STACK) - ABSOLUTE 
(.);
-   bsp_section_stack_end = .;
-   } > REGION_STACK AT > REGION_STACK
-   bsp_section_stack_size = bsp_section_stack_end - 
bsp_section_stack_begin;
-
-   .nocache : ALIGN_WITH_INPUT {
-   bsp_section_nocache_begin = .;
-   *(SORT_BY_ALIGNMENT (SORT_BY_NAME (.bsp_nocache*)))
-   bsp_section_nocache_end = .;
-   } > REGION_NOCACHE AT > REGION_NOCACHE_LOAD
-   bsp_section_nocache_size = bsp_section_nocache_end - 
bsp_section_nocache_begin;
-   bsp_section_nocache_load_begin = LOADADDR (.nocache);
-   bsp_section_nocache_load_end = bsp_section_nocache_load_begin + 
bsp_section_nocache_size;
-
-   .nocachenoload (NOLOAD) : ALIGN_WITH_INPUT {
-   bsp_section_nocachenoload_begin = .;
-   *(SORT_BY_ALIGNMENT (SORT_BY_NAME (.bsp_noload_nocache*)))
-   bsp_section_nocacheheap_begin = .;
-   . += ORIGIN (REGION_NOCACHE) + LENGTH (REGION_NOCACHE) - 
ABSOLUTE (.);
-   bsp_section_nocacheheap_end = .;
-   bsp_section_nocachenoload_end = .;
-   } > REGION_NOCACHE AT > REGION_NOCACHE
-   bsp_section_nocacheheap_size = bsp_section_nocacheheap_end - 
bsp_section_nocacheheap_begin;
-   bsp_section_nocachenoload_size = bsp_section_nocachenoload_end - 
bsp_section_nocachenoload_begin;
-
-   /* FIXME */
-   RamBase = ORIGIN (REGION_WORK);
-   RamSize = LENGTH (REGION_WORK);
-   RamEnd = RamBase + RamSize;
-   WorkAreaBase = bsp_section_work_begin;
-   HeapSize = 0;
-
-   /* Stabs debugging sections.  */
-   .stab  0 : { *(.stab) }
-   .stabstr   0 : { *(.stabstr) }
-   .stab.excl 0 : { *(.stab.excl) }
-   .stab.exclstr  0 : { *(.stab.exclstr) }
-   .stab.index0 : { *(.stab.index) }
-   .stab.indexstr 0 : { *(.stab.indexstr) }
-   .comment   0 : { *(.comment) }
-   /* DWARF debug sections.
-  Symbols in the DWARF debugging sections are relative to the beginning
-  of the section so we begin them at 0.  */
-   /* DWARF 1 */
-   .debug  0 : { *(.debug) }
-   .line   0 : { *(.line) }
-   /* GNU DWARF 1 extensions */
-   .debug_srcinfo  0 : { *(.debug_srcinfo) }
-   .debug_sfnames  0 : { *(.debug_sfnames) }
-   /* DWARF 1.1 and DWARF 2 */
-   .debug_aranges  0 : { *(.debug_aranges) }
-   .debug_pubnames 0 : { *(.debug_pubnames) }
-   /* DWARF 2 */
-   .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
-   .debug_abbrev   0 : { *(.debug_abbrev) }
-   .debug_line 0 : { *(.debug_line) }
-   .debug_frame0 : { *(.debug_frame) }
-   .debug_str  0 : { *(.debug_str) }
-   .debug_loc  0 : { *(.debug_loc) }
-   .debug_macinfo  0 : { *(.debug_macinfo) }
-   /* SGI/MIPS DWARF 2 extensions */
-   .debug_weaknames 0 : { *(.debug_weaknames) }
-   .debug_funcnames 0 : { *(.debug_funcnames) }
-   .debug_typenames 0 : { *(.debug_typenames) }
-   .debug_varnames  0 : { *(.debug_varnames) }
-   /* DWARF 3 */
-   .debug_pubtypes 0 : { *(.debug_pubtypes) }
-   .debug_ranges   0 : { *(.debug_ranges) }
-   /* DWARF extension */
-   .debug_macro0 : { *(.debug_macro) }
-   .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) KEEP 
(*(.gnu.attributes)) }
-   .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
-   /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
-
-   /*
-* This is a RTEMS specific section to catch all unexpected input
-* sections.  In case you get an error like
-*   "section `.unexpected_sections' will not fit in region
-*   `UNEXPECTED_SECTIONS'"
-* you have to figure out the offending input section and add it to the
-* appropriate output section definition above.
-*/
-   .unexpected_sections : { *(*) } > UNEXPECTED_SECTIONS
-}
+INCLUDE linkcmds-aarch.base
diff --git a/bsps/shared/start/linkcmds-aarch.base 
b/bsps/shared/start/linkcmds-aarch.base
new file mode 100644
index 000000..e69461a434
--- /dev/null
+++ b/bsps/shared/start/linkcmds-aarch.base
@@ -0,0 +1,420 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup bs

[PATCH v3 03/10] bsps: Break out AArch32 portions of GPT driver

[Kinsey Moore]

This breaks AArch32-specific portions of the ARM GPT driver into their
own file so that the generic code can be moved for reuse by other
architectures.
---
 bsps/arm/imx/headers.am   |  4 +
 bsps/arm/imx/include/bsp.h|  2 -
 bsps/arm/imx/start/bspstart.c |  3 +-
 .../shared/clock/arm-generic-timer-aarch32.c  | 76 +++
 bsps/arm/xen/headers.am   |  4 +
 bsps/arm/xen/include/bsp.h|  2 -
 bsps/arm/xen/start/bspstart.c |  3 +-
 bsps/arm/xilinx-zynqmp/headers.am |  4 +
 bsps/arm/xilinx-zynqmp/include/bsp.h  |  2 -
 bsps/arm/xilinx-zynqmp/start/bspstart.c   |  3 +-
 bsps/include/dev/clock/arm-generic-timer.h| 76 +++
 .../dev/clock/arm-generic-timer.c}| 65 
 c/src/lib/libbsp/arm/imx/Makefile.am  |  3 +-
 c/src/lib/libbsp/arm/xen/Makefile.am  |  3 +-
 .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am  |  3 +-
 spec/build/bsps/arm/imx/bspimx.yml|  6 +-
 spec/build/bsps/arm/xen/bspxen.yml|  6 +-
 .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml |  6 +-
 18 files changed, 205 insertions(+), 66 deletions(-)
 create mode 100644 bsps/arm/shared/clock/arm-generic-timer-aarch32.c
 create mode 100644 bsps/include/dev/clock/arm-generic-timer.h
 rename bsps/{arm/shared/clock/clock-generic-timer.c => 
shared/dev/clock/arm-generic-timer.c} (71%)

diff --git a/bsps/arm/imx/headers.am b/bsps/arm/imx/headers.am
index 3a093b1698..9863f34300 100644
--- a/bsps/arm/imx/headers.am
+++ b/bsps/arm/imx/headers.am
@@ -21,3 +21,7 @@ include_bspdir = $(includedir)/bsp
 include_bsp_HEADERS =
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/imx-gpio.h
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/irq.h
+
+include_dev_clockdir = $(includedir)/dev/clock
+include_dev_clock_HEADERS =
+include_dev_clock_HEADERS += 
../../../../../../bsps/include/dev/clock/arm-generic-timer.h
diff --git a/bsps/arm/imx/include/bsp.h b/bsps/arm/imx/include/bsp.h
index 134b3fd858..99b7a0d1d7 100644
--- a/bsps/arm/imx/include/bsp.h
+++ b/bsps/arm/imx/include/bsp.h
@@ -57,8 +57,6 @@ extern uintptr_t imx_gic_dist_base;
 
 #define BSP_ARM_A9MPCORE_SCU_BASE 0
 
-void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq);
-
 void *imx_get_reg_of_node(const void *fdt, int node);
 
 int imx_iomux_configure_pins(const void *fdt, uint32_t phandle);
diff --git a/bsps/arm/imx/start/bspstart.c b/bsps/arm/imx/start/bspstart.c
index 5fb07bf60a..ff4b204790 100644
--- a/bsps/arm/imx/start/bspstart.c
+++ b/bsps/arm/imx/start/bspstart.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -58,7 +59,7 @@ uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
   return intr[1] + MAGIC_IRQ_OFFSET;
 }
 
-void arm_generic_timer_get_config(
+void aarch_generic_timer_get_config(
   uint32_t *frequency,
   uint32_t *irq
 )
diff --git a/bsps/arm/shared/clock/arm-generic-timer-aarch32.c 
b/bsps/arm/shared/clock/arm-generic-timer-aarch32.c
new file mode 100644
index 00..8ce65ee5ad
--- /dev/null
+++ b/bsps/arm/shared/clock/arm-generic-timer-aarch32.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief ARM-specific clock driver functions.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+uint64_t aarch_gt_clock_get_compare_value(void)
+{
+#ifdef ARM_GENERIC_TIMER_USE_VIRT

[PATCH v3 01/10] Move ARM PL011 UART driver

[Kinsey Moore]

This UART driver is now needed for BSPs other than ARM.
---
 bsps/arm/headers.am  | 2 --
 bsps/arm/raspberrypi/console/console-config.c| 2 +-
 bsps/arm/realview-pbx-a9/include/bsp/console.h   | 2 +-
 bsps/arm/xen/console/console.c   | 2 +-
 bsps/headers.am  | 5 +
 .../{arm/include/bsp => include/dev/serial}/arm-pl011-regs.h | 0
 bsps/{arm/include/bsp => include/dev/serial}/arm-pl011.h | 2 +-
 bsps/{arm/shared => shared/dev}/serial/arm-pl011.c   | 2 +-
 c/src/lib/libbsp/arm/raspberrypi/Makefile.am | 2 +-
 c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am | 2 +-
 c/src/lib/libbsp/arm/xen/Makefile.am | 2 +-
 spec/build/bsps/arm/grp.yml  | 2 --
 spec/build/bsps/arm/raspberrypi/obj.yml  | 1 -
 spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml | 1 -
 spec/build/bsps/arm/xen/bspxen.yml   | 1 -
 spec/build/bsps/obj.yml  | 5 +
 16 files changed, 18 insertions(+), 15 deletions(-)
 rename bsps/{arm/include/bsp => include/dev/serial}/arm-pl011-regs.h (100%)
 rename bsps/{arm/include/bsp => include/dev/serial}/arm-pl011.h (96%)
 rename bsps/{arm/shared => shared/dev}/serial/arm-pl011.c (98%)

diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am
index 3d2b09effa..f0d498c8f4 100644
--- a/bsps/arm/headers.am
+++ b/bsps/arm/headers.am
@@ -21,8 +21,6 @@ include_bsp_HEADERS += 
../../../../../bsps/arm/include/bsp/arm-gic-irq.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-tm27.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011-regs.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl111-fb.h
diff --git a/bsps/arm/raspberrypi/console/console-config.c 
b/bsps/arm/raspberrypi/console/console-config.c
index bb0b596019..6b8eb80aa4 100644
--- a/bsps/arm/raspberrypi/console/console-config.c
+++ b/bsps/arm/raspberrypi/console/console-config.c
@@ -25,13 +25,13 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/bsps/arm/realview-pbx-a9/include/bsp/console.h 
b/bsps/arm/realview-pbx-a9/include/bsp/console.h
index da2e4099e2..2019fc2509 100644
--- a/bsps/arm/realview-pbx-a9/include/bsp/console.h
+++ b/bsps/arm/realview-pbx-a9/include/bsp/console.h
@@ -15,7 +15,7 @@
 #ifndef LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 #define LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xen/console/console.c b/bsps/arm/xen/console/console.c
index 786b98f3ba..05eceae438 100644
--- a/bsps/arm/xen/console/console.c
+++ b/bsps/arm/xen/console/console.c
@@ -29,7 +29,7 @@
 #include 
 
 #include 
-#include 
+#include 
 #include 
 #include 
 
diff --git a/bsps/headers.am b/bsps/headers.am
index 5af7e43b4a..aaf13284bd 100644
--- a/bsps/headers.am
+++ b/bsps/headers.am
@@ -21,6 +21,11 @@ include_bsp_HEADERS += ../../bsps/include/bsp/u-boot.h
 include_bsp_HEADERS += ../../bsps/include/bsp/uart-output-char.h
 include_bsp_HEADERS += ../../bsps/include/bsp/utility.h
 
+include_dev_serialdir = $(includedir)/dev/serial
+include_dev_serial_HEADERS =
+include_dev_serial_HEADERS += ../../bsps/include/dev/serial/arm-pl011-regs.h
+include_dev_serial_HEADERS += ../../bsps/include/dev/serial/arm-pl011.h
+
 include_grlibdir = $(includedir)/grlib
 include_grlib_HEADERS =
 include_grlib_HEADERS += ../../bsps/include/grlib/ahbstat.h
diff --git a/bsps/arm/include/bsp/arm-pl011-regs.h 
b/bsps/include/dev/serial/arm-pl011-regs.h
similarity index 100%
rename from bsps/arm/include/bsp/arm-pl011-regs.h
rename to bsps/include/dev/serial/arm-pl011-regs.h
diff --git a/bsps/arm/include/bsp/arm-pl011.h 
b/bsps/include/dev/serial/arm-pl011.h
similarity index 96%
rename from bsps/arm/include/bsp/arm-pl011.h
rename to bsps/include/dev/serial/arm-pl011.h
index 49ff413581..c7e65656a3 100644
--- a/bsps/arm/include/bsp/arm-pl011.h
+++ b/bsps/include/dev/serial/arm-pl011.h
@@ -25,7 +25,7 @@
 
 #include 
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/shared/serial/arm-pl011.c 
b/bsps/shared/dev/serial/arm-pl011.c
similarity index 98%
rename from bsps/arm/shared/serial/arm-pl011.c
rename to bsps/shared/dev/serial/arm-pl011.c
index 44a409e551..c3cbab6f3e 100644
--- a/bsps/arm/shared/serial/arm-pl011.c
+++ 

[PATCH v3 02/10] spec: Add missing spintrcritical24 definition

[Kinsey Moore]

---
 spec/build/bsps/tstnointrcrit.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/spec/build/bsps/tstnointrcrit.yml 
b/spec/build/bsps/tstnointrcrit.yml
index 0460aaabb3..46f7d974c8 100644
--- a/spec/build/bsps/tstnointrcrit.yml
+++ b/spec/build/bsps/tstnointrcrit.yml
@@ -24,6 +24,7 @@ actions:
 spintrcritical21: exclude
 spintrcritical22: exclude
 spintrcritical23: exclude
+spintrcritical24: exclude
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-- 
2.20.1

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RE: [PATCH v2 7/8] bsps: Add Cortex-A53 LP64 basic BSP

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Thursday, October 1, 2020 00:05
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH v2 7/8] bsps: Add Cortex-A53 LP64 basic BSP

On 30/09/2020 22:04, Kinsey Moore wrote:
> -Original Message-
> From: Sebastian Huber
> Sent: Tuesday, September 29, 2020 06:49
> To: Kinsey Moore;devel@rtems.org
> Subject: Re: [PATCH v2 7/8] bsps: Add Cortex-A53 LP64 basic BSP
> 
> On 28/09/2020 17:24, Kinsey Moore wrote:
> 
>> diff --git a/bsps/aarch64/shared/start/linkcmds.base
>> b/bsps/aarch64/shared/start/linkcmds.base
>> new file mode 100644
>> index 00..f67404ab62
>> --- /dev/null
>> +++ b/bsps/aarch64/shared/start/linkcmds.base
>> @@ -0,0 +1,450 @@
>> +/* SPDX-License-Identifier: BSD-2-Clause */
>> +
>> +/**
>> + * @file
>> + *
>> + * @ingroup bsp_linker
>> + *
>> + * @brief Linker command base file.
>> + */
>> +
>> +/*
>> + * Copyright (C) 2020 On-Line Applications Research Corporation 
>> +(OAR)
>> + * Written by Kinsey Moore
> This looks like a modified copy of bsps/arm/shared/start/linkcmds.base.
> Are there significant differences or could we share this linker script on arm 
> and aarch64?
> []
> They are similar and could probably share large sections, but a single base 
> linker script is not shareable between arm and aarch64 due to aarch64 
> multilibs needing different OUTPUT_FORMAT and OUTPUT_ARCH directives as well 
> as having differing setups for their various respective exception stacks.

Can't this be solved via an INCLUDE similar to linkcmds.armv4 and 
linkcmds.armv7m?

[] 
If 32-bit ARM isn't broken by having the extra SUBALIGN(4) here and there, then 
they can share a single base include. Otherwise, it will have to be 3 or 4 
different includes. I'll have to setup a test environment to see if one of the 
ARM QEMU BSPs is affected.

Kinsey
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RE: [PATCH v2 7/8] bsps: Add Cortex-A53 LP64 basic BSP

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Tuesday, September 29, 2020 06:49
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH v2 7/8] bsps: Add Cortex-A53 LP64 basic BSP

On 28/09/2020 17:24, Kinsey Moore wrote:

> diff --git a/bsps/aarch64/shared/start/linkcmds.base 
> b/bsps/aarch64/shared/start/linkcmds.base
> new file mode 100644
> index 00..f67404ab62
> --- /dev/null
> +++ b/bsps/aarch64/shared/start/linkcmds.base
> @@ -0,0 +1,450 @@
> +/* SPDX-License-Identifier: BSD-2-Clause */
> +
> +/**
> + * @file
> + *
> + * @ingroup bsp_linker
> + *
> + * @brief Linker command base file.
> + */
> +
> +/*
> + * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
> + * Written by Kinsey Moore
This looks like a modified copy of bsps/arm/shared/start/linkcmds.base. 
Are there significant differences or could we share this linker script on arm 
and aarch64?
[] 
They are similar and could probably share large sections, but a single base 
linker script is not shareable between arm and aarch64 due to aarch64 multilibs 
needing different OUTPUT_FORMAT and OUTPUT_ARCH directives as well as having 
differing setups for their various respective exception stacks.

Kinsey
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RE: [PATCH v2 3/8] bsps: Break out AArch32 portions of GPT driver

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Tuesday, September 29, 2020 06:22
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH v2 3/8] bsps: Break out AArch32 portions of GPT driver

On 28/09/2020 17:24, Kinsey Moore wrote:

>   create mode 100644 bsps/include/bsp/clock-arm-generic-timer.h
>   rename bsps/{arm/shared/clock/clock-generic-timer.c => 
> shared/clock/clock-arm-generic-timer.c} (71%)

I would add it as:

bsps/shared/dev/clock/arm-generic-timer.c

bsps/include/dev/clock/arm-generic-timer.h

[] 
Your comment on the pl011 adjustments specified bsps/shared/include/dev while 
this comment mentions bsps/include/dev. Which is the preferred location?

Kinsey
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RE: [PATCH v2 2/8] spec: Add missing spintrcritical24 definition

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Tuesday, September 29, 2020 06:09
To: Kinsey Moore ; RTEMS 
Subject: Re: [PATCH v2 2/8] spec: Add missing spintrcritical24 definition

On 28/09/2020 17:24, Kinsey Moore wrote:

> ---
>   spec/build/bsps/tstnointrcrit.yml | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/spec/build/bsps/tstnointrcrit.yml 
> b/spec/build/bsps/tstnointrcrit.yml
> index 0460aaabb3..46f7d974c8 100644
> --- a/spec/build/bsps/tstnointrcrit.yml
> +++ b/spec/build/bsps/tstnointrcrit.yml
> @@ -24,6 +24,7 @@ actions:
>   spintrcritical21: exclude
>   spintrcritical22: exclude
>   spintrcritical23: exclude
> +spintrcritical24: exclude
>   build-type: option
>   copyrights:
>   - Copyright (C) 2020 embedded brains GmbH 
> (http://www.embedded-brains.de)

I changed the test support for critical sections recently. Now, this test 
framework part is used:

https://docs.rtems.org/branches/master/eng/test-framework.html#interrupt-tests

Could you please run the spintrcritical* tests also on the new port. My 
intention was to be able to run these tests on Qemu.

[] 
I'll make sure these are working before I push the next patch version.

Kinsey
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RE: [PATCH v2 1/8] Move ARM PL011 UART driver

[Kinsey Moore]

I'll include this change in the next version of the patch.

Kinsey

-Original Message-
From: Sebastian Huber  
Sent: Tuesday, September 29, 2020 05:59
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH v2 1/8] Move ARM PL011 UART driver

On 28/09/2020 17:24, Kinsey Moore wrote:

> This UART driver is now needed for BSPs other than ARM.
> ---
>   bsps/arm/headers.am| 2 --
>   bsps/arm/raspberrypi/console/console-config.c  | 2 +-
>   bsps/arm/realview-pbx-a9/include/bsp/console.h | 2 +-
>   bsps/arm/xen/console/console.c | 2 +-
>   bsps/headers.am| 2 ++
>   bsps/{arm/include/bsp => include/libchip}/arm-pl011-regs.h | 0
>   bsps/{arm/include/bsp => include/libchip}/arm-pl011.h  | 2 +-

For me this libchip inline stuff is a legacy thing. If you really want to 
change the include path, then I suggest to move the serial driver header files 
to:

bsps/shared/include/dev/serial

This is in line with cpukit/include/dev/serial and the source location 
bsps/shared/dev/serial.

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RE: [PATCH v2 2/2] Add AArch64 documentation

[Kinsey Moore]

There are some rudimentary pieces of SMP support in the port itself, but it is 
certainly not complete and is untested. That work is planned for the next phase 
of development at which point I'll update the BSPs to support that as well if 
they require any changes at all.

Kinsey

-Original Message-
From: Sebastian Huber  
Sent: Monday, September 28, 2020 23:40
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH v2 2/2] Add AArch64 documentation

On 28/09/2020 17:25, Kinsey Moore wrote:

> +Symmetric Multiprocessing
> +=
> +
> +SMP is not currently supported on ARMv8-A.
Is this a limitation of the CPU port or just a missing BSP support?
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RE: [PATCH v2 1/2] cpu-supplement: Fix formatting and missing words

[Kinsey Moore]

It was already an odd hybrid of a marked up list and a grammatical list that I 
noticed while I was working on the AArch64 documentation. I figured I'd push it 
one way or the other since mixing the constructs looks weird, but I can drop 
the changes unrelated to AArch64 if you prefer.

Kinsey

-Original Message-
From: Sebastian Huber  
Sent: Monday, September 28, 2020 23:36
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH v2 1/2] cpu-supplement: Fix formatting and missing words

On 28/09/2020 17:25, Kinsey Moore wrote:

> @@ -196,11 +196,11 @@ Symmetric Multiprocessing
>   
>   SMP is supported on ARMv7-A.  Available platforms are
>   
> -- Altera Cyclone V,
> +- Altera Cyclone V
>   
> -- NXP i.MX 7, and
> +- NXP i.MX 7
>   
> -- Xilinx Zynq.
> +- Xilinx Zynq

What is the reason for this change?


If you change the formatting like this, then it should be

"Available platforms are:"

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[PATCH v2 1/2] cpu-supplement: Fix formatting and missing words

[Kinsey Moore]

---
 cpu-supplement/arm.rst | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/cpu-supplement/arm.rst b/cpu-supplement/arm.rst
index 63aa532..26d88ea 100644
--- a/cpu-supplement/arm.rst
+++ b/cpu-supplement/arm.rst
@@ -34,7 +34,7 @@ for the values.
 Count Leading Zeroes Instruction
 
 
-The ARMv5 and later has the count leading zeroes ``clz`` instruction which
+The ARMv5 and later instruction sets have the count leading zeroes ``clz`` 
instruction which
 could be used to speed up the find first bit operation.  The use of this
 instruction should significantly speed up the scheduling associated with a
 thread blocking.  This is currently not used.
@@ -130,7 +130,7 @@ Memory Model
 
 
 A flat 32-bit memory model is supported.  The board support package must take
-care about the MMU if necessary.
+care of initializing the MMU if necessary.
 
 Interrupt Processing
 
@@ -196,11 +196,11 @@ Symmetric Multiprocessing
 
 SMP is supported on ARMv7-A.  Available platforms are
 
-- Altera Cyclone V,
+- Altera Cyclone V
 
-- NXP i.MX 7, and
+- NXP i.MX 7
 
-- Xilinx Zynq.
+- Xilinx Zynq
 
 Thread-Local Storage
 
-- 
2.20.1

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[PATCH v2 6/8] score: Add AArch64 port

[Kinsey Moore]

This adds a CPU port for AArch64(ARMv8) with support for exceptions and
interrupts.
---
 cpukit/include/rtems/score/tls.h  |   4 +-
 .../cpu/aarch64/aarch64-context-validate.S| 305 ++
 .../aarch64-context-volatile-clobber.S| 100 
 .../cpu/aarch64/aarch64-exception-default.S   | 418 +
 .../cpu/aarch64/aarch64-exception-default.c   |  50 ++
 .../aarch64/aarch64-exception-frame-print.c   | 108 
 .../cpu/aarch64/aarch64-exception-interrupt.S | 317 ++
 .../score/cpu/aarch64/aarch64-thread-idle.c   |  48 ++
 cpukit/score/cpu/aarch64/cpu.c| 196 +++
 cpukit/score/cpu/aarch64/cpu_asm.S| 134 +
 .../cpu/aarch64/include/libcpu/vectors.h  | 100 
 cpukit/score/cpu/aarch64/include/rtems/asm.h  |  89 +++
 .../cpu/aarch64/include/rtems/score/aarch64.h |  83 +++
 .../cpu/aarch64/include/rtems/score/cpu.h | 549 ++
 .../aarch64/include/rtems/score/cpuatomic.h   |  42 ++
 .../cpu/aarch64/include/rtems/score/cpuimpl.h |  83 +++
 spec/build/cpukit/cpuaarch64.yml  |  35 ++
 spec/build/cpukit/librtemscpu.yml |   2 +
 18 files changed, 2662 insertions(+), 1 deletion(-)
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-validate.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-volatile-clobber.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-interrupt.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-thread-idle.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu_asm.S
 create mode 100644 cpukit/score/cpu/aarch64/include/libcpu/vectors.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/asm.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/aarch64.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuatomic.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
 create mode 100644 spec/build/cpukit/cpuaarch64.yml

diff --git a/cpukit/include/rtems/score/tls.h b/cpukit/include/rtems/score/tls.h
index 65a49d87be..66961f0083 100644
--- a/cpukit/include/rtems/score/tls.h
+++ b/cpukit/include/rtems/score/tls.h
@@ -85,7 +85,9 @@ typedef struct TLS_Thread_control_block {
   struct TLS_Thread_control_block *tcb;
 #else /* !__i386__ */
   TLS_Dynamic_thread_vector *dtv;
-#if CPU_SIZEOF_POINTER == 4
+/* gcc under AArch64/LP64 expects a 16 byte TCB at the beginning of the TLS
+ * data segment and indexes into it accordingly for TLS variable addresses */
+#if CPU_SIZEOF_POINTER == 4 || defined(AARCH64_MULTILIB_ARCH_V8)
   uintptr_t reserved;
 #endif
 #endif /* __i386__ */
diff --git a/cpukit/score/cpu/aarch64/aarch64-context-validate.S 
b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
new file mode 100644
index 00..31c8d5571c
--- /dev/null
+++ b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUAArch64
+ *
+ * @brief Implementation of _CPU_Context_validate
+ *
+ * This file implements _CPU_Context_validate for use in spcontext01.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+

[PATCH v2 5/8] bsps/shared: Add PSCI-based bspreset implementation

[Kinsey Moore]

This adds a bsp_reset implementation based on the ARM PSCI
specification often present in ARMv8 systems.
---
 bsps/shared/start/bspreset-psci.c | 56 +++
 1 file changed, 56 insertions(+)
 create mode 100644 bsps/shared/start/bspreset-psci.c

diff --git a/bsps/shared/start/bspreset-psci.c 
b/bsps/shared/start/bspreset-psci.c
new file mode 100644
index 00..215be5c9b5
--- /dev/null
+++ b/bsps/shared/start/bspreset-psci.c
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsShared
+ *
+ * @brief PSCI-based BSP reset hook.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+void bsp_reset(void)
+{
+   uint32_t PSCI_FN_SYSTEM_RESET = 0x8409;
+   __asm__ volatile(
+#if defined(AARCH64_MULTILIB_ARCH_V8) || 
defined(AARCH64_MULTILIB_ARCH_V8_ILP32)
+   "mov x0, %0\n"
+#else
+   "mov r0, %0\n"
+#endif
+#ifdef BSP_RESET_SMC
+   "smc #0\n"
+#else
+   "hvc #0\n"
+#endif
+   : : "r" (PSCI_FN_SYSTEM_RESET)
+   );
+}
-- 
2.20.1

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[PATCH v2 8/8] bsps: Add Cortex-A53 ILP32 BSP variant

[Kinsey Moore]

bsps/aarch64/a53/start/bspstarthooks.c
+- bsps/shared/dev/getentropy/getentropy-cpucounter.c
+- bsps/shared/dev/serial/console-termios-init.c
+- bsps/shared/dev/serial/console-termios.c
+- bsps/shared/start/bspfatal-default.c
+- bsps/shared/start/bspgetworkarea-default.c
+- bsps/shared/start/bspreset-psci.c
+- bsps/shared/start/sbrk.c
+- bsps/shared/irq/irq-arm-gicv3.c
+- bsps/shared/irq/irq-default-handler.c
+- bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c
+- bsps/shared/dev/btimer/btimer-cpucounter.c
+- bsps/shared/clock/clock-arm-generic-timer.c
+- bsps/aarch64/shared/clock/clock-arm-generic-timer-aarch64.c
+type: build
diff --git a/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml 
b/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
index cda7450cb8..05f1dc71c4 100644
--- a/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
+++ b/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
@@ -49,7 +49,7 @@ links:
 - role: build-dependency
   uid: ../../opto2
 - role: build-dependency
-  uid: linkcmds
+  uid: linkcmds_lp64
 - role: build-dependency
   uid: ../../bspopts
 source:
diff --git a/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml 
b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
new file mode 100644
index 00..ed585f1950
--- /dev/null
+++ b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
@@ -0,0 +1,71 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: config-file
+content: |
+  /*
+   * SPDX-License-Identifier: BSD-2-Clause
+   *
+   * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+   * Written by Kinsey Moore 
+   *
+   * Redistribution and use in source and binary forms, with or without
+   * modification, are permitted provided that the following conditions
+   * are met:
+   * 1. Redistributions of source code must retain the above copyright
+   *notice, this list of conditions and the following disclaimer.
+   * 2. Redistributions in binary form must reproduce the above copyright
+   *notice, this list of conditions and the following disclaimer in the
+   *documentation and/or other materials provided with the distribution.
+   *
+   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
IS"
+   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   * POSSIBILITY OF SUCH DAMAGE.
+   */
+
+  MEMORY {
+RAM   : ORIGIN = ${BSP_A53_RAM_BASE} + ${BSP_A53_LOAD_OFFSET}, LENGTH 
= ${BSP_A53_RAM_LENGTH} - ${BSP_A53_LOAD_OFFSET} - ${BSP_A53_NOCACHE_LENGTH}
+NOCACHE   : ORIGIN = ${BSP_A53_RAM_BASE} + ${BSP_A53_RAM_LENGTH} - 
${BSP_A53_NOCACHE_LENGTH}, LENGTH = ${BSP_A53_NOCACHE_LENGTH}
+  }
+
+  REGION_ALIAS ("REGION_START",  RAM);
+  REGION_ALIAS ("REGION_VECTOR", RAM);
+  REGION_ALIAS ("REGION_TEXT",   RAM);
+  REGION_ALIAS ("REGION_TEXT_LOAD",  RAM);
+  REGION_ALIAS ("REGION_RODATA", RAM);
+  REGION_ALIAS ("REGION_RODATA_LOAD",RAM);
+  REGION_ALIAS ("REGION_DATA",   RAM);
+  REGION_ALIAS ("REGION_DATA_LOAD",  RAM);
+  REGION_ALIAS ("REGION_FAST_TEXT",  RAM);
+  REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM);
+  REGION_ALIAS ("REGION_FAST_DATA",  RAM);
+  REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM);
+  REGION_ALIAS ("REGION_BSS",RAM);
+  REGION_ALIAS ("REGION_WORK",   RAM);
+  REGION_ALIAS ("REGION_STACK",  RAM);
+  REGION_ALIAS ("REGION_NOCACHE",NOCACHE);
+  REGION_ALIAS ("REGION_NOCACHE_LOAD",   NOCACHE);
+
+  bsp_stack_exception_size = DEFINED (bsp_stack_exception_size) ? 
bsp_stack_exception_size : 1024;
+
+  bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? 
bsp_section_rwbarrier_align : 1M;
+
+  bsp_vector_table_in_start_section = 1;
+
+  OUTPUT_FORMAT ("elf32-littleaarch64")
+  OUTPUT_ARCH (aarch64:ilp32)
+
+  INCLUDE linkcmds.base
+copyrights:
+- Copyright (C) 2020 On-Line Applications Research (OAR)
+enabled-by: true
+install-path: ${BSP_LIBDIR}
+links: []
+target: linkcmds
+type: build
diff --git a/spec/build/bsps/aarch64/a53/linkcmds.yml 
b/spec/build/bsps/aarch64/a53/linkcmds_lp64.yml
similarity index 97%
rename from spec/build/bsps/aarch64/a53/linkcmds.yml
rename to 

[PATCH v2 7/8] bsps: Add Cortex-A53 LP64 basic BSP

[Kinsey Moore]

This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with
interrupt support using GICv3 and clock support using the ARM GPT.
---
 bsps/aarch64/a53/console/console.c|  69 ++
 bsps/aarch64/a53/include/bsp.h|  74 +++
 bsps/aarch64/a53/include/bsp/irq.h|  67 ++
 bsps/aarch64/a53/include/tm27.h   |  46 ++
 bsps/aarch64/a53/start/bspstart.c |  49 ++
 bsps/aarch64/a53/start/bspstarthooks.c|  50 ++
 bsps/aarch64/include/bsp/irq-arch.h   |  50 ++
 bsps/aarch64/include/bsp/linker-symbols.h | 161 +
 bsps/aarch64/include/bsp/start.h  | 189 ++
 bsps/aarch64/shared/cache/cache.c | 612 ++
 .../clock/clock-arm-generic-timer-aarch64.c   | 110 
 .../shared/irq/irq-arm-gicv3-aarch64.c|  58 ++
 bsps/aarch64/shared/start/linkcmds.base   | 450 +
 bsps/aarch64/shared/start/start.S | 219 +++
 spec/build/bsps/aarch64/a53/abi.yml   |  17 +
 .../build/bsps/aarch64/a53/bspa53lp64qemu.yml |  73 +++
 spec/build/bsps/aarch64/a53/linkcmds.yml  |  68 ++
 spec/build/bsps/aarch64/a53/optloadoff.yml|  18 +
 spec/build/bsps/aarch64/a53/optnocachelen.yml |  18 +
 spec/build/bsps/aarch64/a53/optramlen.yml |  18 +
 spec/build/bsps/aarch64/a53/optramori.yml |  18 +
 spec/build/bsps/aarch64/a53/tsta53.yml|  56 ++
 spec/build/bsps/aarch64/start.yml |  14 +
 23 files changed, 2504 insertions(+)
 create mode 100644 bsps/aarch64/a53/console/console.c
 create mode 100644 bsps/aarch64/a53/include/bsp.h
 create mode 100644 bsps/aarch64/a53/include/bsp/irq.h
 create mode 100644 bsps/aarch64/a53/include/tm27.h
 create mode 100644 bsps/aarch64/a53/start/bspstart.c
 create mode 100644 bsps/aarch64/a53/start/bspstarthooks.c
 create mode 100644 bsps/aarch64/include/bsp/irq-arch.h
 create mode 100644 bsps/aarch64/include/bsp/linker-symbols.h
 create mode 100644 bsps/aarch64/include/bsp/start.h
 create mode 100644 bsps/aarch64/shared/cache/cache.c
 create mode 100644 bsps/aarch64/shared/clock/clock-arm-generic-timer-aarch64.c
 create mode 100644 bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c
 create mode 100644 bsps/aarch64/shared/start/linkcmds.base
 create mode 100644 bsps/aarch64/shared/start/start.S
 create mode 100644 spec/build/bsps/aarch64/a53/abi.yml
 create mode 100644 spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
 create mode 100644 spec/build/bsps/aarch64/a53/linkcmds.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optloadoff.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optnocachelen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramlen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramori.yml
 create mode 100644 spec/build/bsps/aarch64/a53/tsta53.yml
 create mode 100644 spec/build/bsps/aarch64/start.yml

diff --git a/bsps/aarch64/a53/console/console.c 
b/bsps/aarch64/a53/console/console.c
new file mode 100644
index 00..d9fffb1e0c
--- /dev/null
+++ b/bsps/aarch64/a53/console/console.c
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64A53
+ *
+ * @brief Console Configuration
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+arm_pl011_context a53_qemu_vpl011_context = {
+  .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("PL011"),
+  .regs = (volatile pl011 *) BSP_A53_QEMU_VPL011_BASE,
+  .initial_baud = 115200
+};
+
+const console_device console_device_table[] = {
+  {
+

[PATCH v2 2/2] Add AArch64 documentation

[Kinsey Moore]

 the LP64
+multilib variant, the the TCB is 16 bytes in size instead of 8 bytes.
diff --git a/user/bsps/aarch64/a53.rst b/user/bsps/aarch64/a53.rst
new file mode 100644
index 000..0052773
--- /dev/null
+++ b/user/bsps/aarch64/a53.rst
@@ -0,0 +1,26 @@
+.. SPDX-License-Identifier: CC-BY-SA-4.0
+
+.. Copyright (C) 2020 Kinsey Moore, On-Line Applications Research Corporation 
(OAR)
+
+.. _BSP_aarch64_qemu_a53_ilp32:
+.. _BSP_aarch64_qemu_a53_lp64:
+
+Qemu A53
+
+
+This BSP supports two variants, `qemu_a53_ilp32` and `qemu-a53_lp64`. The basic
+hardware initialization is performed by the BSP.
+
+Boot via ELF
+
+The executable image is booted by Qemu in ELF format.
+
+Clock Driver
+
+
+The clock driver uses the `ARM Generic Timer`.
+
+Console Driver
+--
+
+The console driver supports the default Qemu emulated ARM PL011 PrimeCell UART.
diff --git a/user/bsps/bsps-aarch64.rst b/user/bsps/bsps-aarch64.rst
index 4b2e749..319310e 100644
--- a/user/bsps/bsps-aarch64.rst
+++ b/user/bsps/bsps-aarch64.rst
@@ -5,4 +5,4 @@
 aarch64 (AArch64)
 *
 
-There are no AArch64 BSPs yet.
+.. include:: aarch64/a53.rst
-- 
2.20.1

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[PATCH v2 2/8] spec: Add missing spintrcritical24 definition

[Kinsey Moore]

---
 spec/build/bsps/tstnointrcrit.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/spec/build/bsps/tstnointrcrit.yml 
b/spec/build/bsps/tstnointrcrit.yml
index 0460aaabb3..46f7d974c8 100644
--- a/spec/build/bsps/tstnointrcrit.yml
+++ b/spec/build/bsps/tstnointrcrit.yml
@@ -24,6 +24,7 @@ actions:
 spintrcritical21: exclude
 spintrcritical22: exclude
 spintrcritical23: exclude
+spintrcritical24: exclude
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-- 
2.20.1

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[PATCH v2 4/8] bsps: Break out AArch32 GICv3 support

[Kinsey Moore]

nclude/bsp/arm-pl111-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-release-id.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/armv7m-irq.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/clock-armv7m.h
+include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/irq-arch.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/linker-symbols.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-dma.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-emc.h
diff --git a/bsps/arm/include/bsp/irq-arch.h b/bsps/arm/include/bsp/irq-arch.h
new file mode 100644
index 00..b3be1bc10b
--- /dev/null
+++ b/bsps/arm/include/bsp/irq-arch.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARM
+ *
+ * @brief ARM IRQ definitions
+ */
+
+/*
+ *
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_IRQ_ARCH_H
+#define LIBBSP_ARM_SHARED_IRQ_ARCH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+void bsp_interrupt_dispatch( void );
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_IRQ_ARCH_H */
diff --git a/bsps/arm/lpc24xx/irq/irq-dispatch.c 
b/bsps/arm/lpc24xx/irq/irq-dispatch.c
index 66d05fdf9d..7baa527595 100644
--- a/bsps/arm/lpc24xx/irq/irq-dispatch.c
+++ b/bsps/arm/lpc24xx/irq/irq-dispatch.c
@@ -24,6 +24,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 
diff --git a/bsps/arm/lpc32xx/irq/irq.c b/bsps/arm/lpc32xx/irq/irq.c
index eac32b..f0c1f4f548 100644
--- a/bsps/arm/lpc32xx/irq/irq.c
+++ b/bsps/arm/lpc32xx/irq/irq.c
@@ -23,6 +23,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/bsps/arm/raspberrypi/irq/irq.c b/bsps/arm/raspberrypi/irq/irq.c
index 835cdf97d9..1e5e4735b3 100644
--- a/bsps/arm/raspberrypi/irq/irq.c
+++ b/bsps/arm/raspberrypi/irq/irq.c
@@ -25,6 +25,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/bsps/arm/rtl22xx/irq/irq.c b/bsps/arm/rtl22xx/irq/irq.c
index 83e140bd7b..7f94958105 100644
--- a/bsps/arm/rtl22xx/irq/irq.c
+++ b/bsps/arm/rtl22xx/irq/irq.c
@@ -13,6 +13,7 @@
 
 #include 
 #include 
+#include 
 #include 
 
 #include 
diff --git a/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c 
b/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
new file mode 100644
index 00..a26c254787
--- /dev/null
+++ b/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief ARM-specific IRQ handlers.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE

[PATCH v2 3/8] bsps: Break out AArch32 portions of GPT driver

[Kinsey Moore]

This breaks AArch32-specific portions of the ARM GPT driver into their
own file so that the generic code can be moved for reuse by other
architectures.
---
 bsps/arm/imx/headers.am   |  1 +
 bsps/arm/imx/include/bsp.h|  2 -
 bsps/arm/imx/start/bspstart.c |  3 +-
 .../clock/clock-arm-generic-timer-aarch32.c   | 76 +++
 bsps/arm/xen/headers.am   |  1 +
 bsps/arm/xen/include/bsp.h|  2 -
 bsps/arm/xen/start/bspstart.c |  3 +-
 bsps/arm/xilinx-zynqmp/headers.am |  1 +
 bsps/arm/xilinx-zynqmp/include/bsp.h  |  2 -
 bsps/arm/xilinx-zynqmp/start/bspstart.c   |  3 +-
 bsps/include/bsp/clock-arm-generic-timer.h| 73 ++
 .../clock/clock-arm-generic-timer.c}  | 65 
 c/src/lib/libbsp/arm/imx/Makefile.am  |  3 +-
 c/src/lib/libbsp/arm/xen/Makefile.am  |  3 +-
 .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am  |  3 +-
 spec/build/bsps/arm/imx/bspimx.yml|  4 +-
 spec/build/bsps/arm/xen/bspxen.yml|  4 +-
 .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml |  4 +-
 18 files changed, 187 insertions(+), 66 deletions(-)
 create mode 100644 bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c
 create mode 100644 bsps/include/bsp/clock-arm-generic-timer.h
 rename bsps/{arm/shared/clock/clock-generic-timer.c => 
shared/clock/clock-arm-generic-timer.c} (71%)

diff --git a/bsps/arm/imx/headers.am b/bsps/arm/imx/headers.am
index 3a093b1698..76c1607871 100644
--- a/bsps/arm/imx/headers.am
+++ b/bsps/arm/imx/headers.am
@@ -21,3 +21,4 @@ include_bspdir = $(includedir)/bsp
 include_bsp_HEADERS =
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/imx-gpio.h
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/irq.h
+include_bsp_HEADERS += 
../../../../../../bsps/include/bsp/clock-arm-generic-timer.h
diff --git a/bsps/arm/imx/include/bsp.h b/bsps/arm/imx/include/bsp.h
index 134b3fd858..99b7a0d1d7 100644
--- a/bsps/arm/imx/include/bsp.h
+++ b/bsps/arm/imx/include/bsp.h
@@ -57,8 +57,6 @@ extern uintptr_t imx_gic_dist_base;
 
 #define BSP_ARM_A9MPCORE_SCU_BASE 0
 
-void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq);
-
 void *imx_get_reg_of_node(const void *fdt, int node);
 
 int imx_iomux_configure_pins(const void *fdt, uint32_t phandle);
diff --git a/bsps/arm/imx/start/bspstart.c b/bsps/arm/imx/start/bspstart.c
index 5fb07bf60a..ff5edaf5a1 100644
--- a/bsps/arm/imx/start/bspstart.c
+++ b/bsps/arm/imx/start/bspstart.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -58,7 +59,7 @@ uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
   return intr[1] + MAGIC_IRQ_OFFSET;
 }
 
-void arm_generic_timer_get_config(
+void aarch_generic_timer_get_config(
   uint32_t *frequency,
   uint32_t *irq
 )
diff --git a/bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c 
b/bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c
new file mode 100644
index 00..70509e2a86
--- /dev/null
+++ b/bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief ARM-specific clock driver functions.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+uint64_t aarch_gt_clock_get_compare_value(void)
+{
+#ifdef ARM_GENERIC_TIMER_USE_VIRTUAL
+  return arm_cp15_get_counter_pl1_virtual_compare_value();
+#e

[PATCH v2 1/8] Move ARM PL011 UART driver

[Kinsey Moore]

This UART driver is now needed for BSPs other than ARM.
---
 bsps/arm/headers.am| 2 --
 bsps/arm/raspberrypi/console/console-config.c  | 2 +-
 bsps/arm/realview-pbx-a9/include/bsp/console.h | 2 +-
 bsps/arm/xen/console/console.c | 2 +-
 bsps/headers.am| 2 ++
 bsps/{arm/include/bsp => include/libchip}/arm-pl011-regs.h | 0
 bsps/{arm/include/bsp => include/libchip}/arm-pl011.h  | 2 +-
 bsps/{arm/shared => shared/dev}/serial/arm-pl011.c | 2 +-
 c/src/lib/libbsp/arm/raspberrypi/Makefile.am   | 2 +-
 c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am   | 2 +-
 c/src/lib/libbsp/arm/xen/Makefile.am   | 2 +-
 spec/build/bsps/arm/grp.yml| 2 --
 spec/build/bsps/arm/raspberrypi/obj.yml| 1 -
 spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml   | 1 -
 spec/build/bsps/arm/xen/bspxen.yml | 1 -
 spec/build/bsps/obj.yml| 3 +++
 16 files changed, 13 insertions(+), 15 deletions(-)
 rename bsps/{arm/include/bsp => include/libchip}/arm-pl011-regs.h (100%)
 rename bsps/{arm/include/bsp => include/libchip}/arm-pl011.h (96%)
 rename bsps/{arm/shared => shared/dev}/serial/arm-pl011.c (98%)

diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am
index 3d2b09effa..f0d498c8f4 100644
--- a/bsps/arm/headers.am
+++ b/bsps/arm/headers.am
@@ -21,8 +21,6 @@ include_bsp_HEADERS += 
../../../../../bsps/arm/include/bsp/arm-gic-irq.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-tm27.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011-regs.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl111-fb.h
diff --git a/bsps/arm/raspberrypi/console/console-config.c 
b/bsps/arm/raspberrypi/console/console-config.c
index bb0b596019..27d02bbe39 100644
--- a/bsps/arm/raspberrypi/console/console-config.c
+++ b/bsps/arm/raspberrypi/console/console-config.c
@@ -25,13 +25,13 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/bsps/arm/realview-pbx-a9/include/bsp/console.h 
b/bsps/arm/realview-pbx-a9/include/bsp/console.h
index da2e4099e2..0ed99ec86e 100644
--- a/bsps/arm/realview-pbx-a9/include/bsp/console.h
+++ b/bsps/arm/realview-pbx-a9/include/bsp/console.h
@@ -15,7 +15,7 @@
 #ifndef LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 #define LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xen/console/console.c b/bsps/arm/xen/console/console.c
index 786b98f3ba..446bd2c3b8 100644
--- a/bsps/arm/xen/console/console.c
+++ b/bsps/arm/xen/console/console.c
@@ -29,7 +29,7 @@
 #include 
 
 #include 
-#include 
+#include 
 #include 
 #include 
 
diff --git a/bsps/headers.am b/bsps/headers.am
index 5af7e43b4a..825574a5a9 100644
--- a/bsps/headers.am
+++ b/bsps/headers.am
@@ -110,6 +110,8 @@ include_libchip_HEADERS += 
../../bsps/include/libchip/mc68681.h
 include_libchip_HEADERS += ../../bsps/include/libchip/ns16550.h
 include_libchip_HEADERS += ../../bsps/include/libchip/ns16550_p.h
 include_libchip_HEADERS += ../../bsps/include/libchip/open_eth.h
+include_libchip_HEADERS += ../../bsps/include/libchip/arm-pl011-regs.h
+include_libchip_HEADERS += ../../bsps/include/libchip/arm-pl011.h
 include_libchip_HEADERS += ../../bsps/include/libchip/rtc.h
 include_libchip_HEADERS += ../../bsps/include/libchip/serial.h
 include_libchip_HEADERS += ../../bsps/include/libchip/sersupp.h
diff --git a/bsps/arm/include/bsp/arm-pl011-regs.h 
b/bsps/include/libchip/arm-pl011-regs.h
similarity index 100%
rename from bsps/arm/include/bsp/arm-pl011-regs.h
rename to bsps/include/libchip/arm-pl011-regs.h
diff --git a/bsps/arm/include/bsp/arm-pl011.h b/bsps/include/libchip/arm-pl011.h
similarity index 96%
rename from bsps/arm/include/bsp/arm-pl011.h
rename to bsps/include/libchip/arm-pl011.h
index 49ff413581..947c254bd8 100644
--- a/bsps/arm/include/bsp/arm-pl011.h
+++ b/bsps/include/libchip/arm-pl011.h
@@ -25,7 +25,7 @@
 
 #include 
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/shared/serial/arm-pl011.c 
b/bsps/shared/dev/serial/arm-pl011.c
similarity index 98%
rename from bsps/arm/shared/serial/arm-pl011.c
rename to bsps/shared/dev/serial/arm-pl011.c
index 44a409e551..39225e8349 100644
--- a/bsps/arm/shared/serial/arm-pl011.c
+++ b/bsps/shared/dev/serial/arm-pl011.c

RE: [PATCH v1 6/8] score: Add AArch64 port

[Kinsey Moore]

-Original Message-
From: Sebastian Huber  
Sent: Friday, September 25, 2020 11:20
To: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH v1 6/8] score: Add AArch64 port

On 25/09/2020 17:27, Kinsey Moore wrote:

> diff --git a/cpukit/include/rtems/score/tls.h 
> b/cpukit/include/rtems/score/tls.h
> index 65a49d87be..8c15eee569 100644
> --- a/cpukit/include/rtems/score/tls.h
> +++ b/cpukit/include/rtems/score/tls.h
> @@ -85,7 +85,7 @@ typedef struct TLS_Thread_control_block {
> struct TLS_Thread_control_block *tcb;
>   #else /* !__i386__ */
> TLS_Dynamic_thread_vector *dtv;
> -#if CPU_SIZEOF_POINTER == 4
> +#if CPU_SIZEOF_POINTER == 4 || CPU_SIZEOF_POINTER == 8
> uintptr_t reserved;
>   #endif
>   #endif /* __i386__ */
Are you sure this is correct? TLS_Dynamic_thread_vector *dtv; is 8 bytes in 
this case.
[] 
Dropping this change causes sptls01 to fail. This was added pretty early in the 
implementation, so I've just had to go back and refresh my memories of the 
reasoning behind it which still may not be entirely accurate. Sptls01 fails 
without this patch because under AArch64/LP64, gcc and gdb expect a 16 byte 
offset to the TLS data segment. If this patch is not present, the TCB is half 
the size it needs to be and so getting a TLS variable address ends up indexing 
into the TCB+TLS data segment at a compiler-expected offset that does not 
correspond to the actual data layout. I adjusted this to match the compiler's 
offset expectations. There may be a better way to fix this issue, but this is 
the most appropriate location I could find that made the most sense. The 
biggest worry I have here is that this may break other architectures that also 
have 8 byte pointers. When I fix the file headers, I'll see if I can make this 
more specific to AArch64.

Kinsey
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[PATCH v1 1/2] tester: Add a53_lp64_qemu.ini

[Kinsey Moore]

---
 tester/rtems/testing/bsps/a53_lp64_qemu.ini | 38 +
 1 file changed, 38 insertions(+)
 create mode 100644 tester/rtems/testing/bsps/a53_lp64_qemu.ini

diff --git a/tester/rtems/testing/bsps/a53_lp64_qemu.ini 
b/tester/rtems/testing/bsps/a53_lp64_qemu.ini
new file mode 100644
index 000..f29ab13
--- /dev/null
+++ b/tester/rtems/testing/bsps/a53_lp64_qemu.ini
@@ -0,0 +1,38 @@
+#
+# RTEMS Tools Project (http://www.rtems.org/)
+# Copyright 2020 Kinsey Moore(kinsey.mo...@oarcorp.com)
+# All rights reserved.
+#
+# This file is part of the RTEMS Tools package in 'rtems-tools'.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+#
+# The AArch64 Cortex-A53 LP64 BSP.
+#
+[a53_lp64_qemu]
+bsp   = a53_lp64_qemu
+arch  = aarch64
+tester= %{_rtscripts}/qemu.cfg
+bsp_qemu_opts = %{qemu_opts_base} -serial mon:stdio -machine 
virt,gic_version=3 -cpu cortex-a53 -m 4096
-- 
2.20.1

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[PATCH v1 2/2] tester: Add a53_ilp32_qemu.ini

[Kinsey Moore]

---
 tester/rtems/testing/bsps/a53_ilp32_qemu.ini | 38 
 1 file changed, 38 insertions(+)
 create mode 100644 tester/rtems/testing/bsps/a53_ilp32_qemu.ini

diff --git a/tester/rtems/testing/bsps/a53_ilp32_qemu.ini 
b/tester/rtems/testing/bsps/a53_ilp32_qemu.ini
new file mode 100644
index 000..6dfc883
--- /dev/null
+++ b/tester/rtems/testing/bsps/a53_ilp32_qemu.ini
@@ -0,0 +1,38 @@
+#
+# RTEMS Tools Project (http://www.rtems.org/)
+# Copyright 2020 Kinsey Moore(kinsey.mo...@oarcorp.com)
+# All rights reserved.
+#
+# This file is part of the RTEMS Tools package in 'rtems-tools'.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+#
+# The AArch64 Cortex-A53 ILP32 BSP.
+#
+[a53_ilp32_qemu]
+bsp   = a53_ilp32_qemu
+arch  = aarch64
+tester= %{_rtscripts}/qemu.cfg
+bsp_qemu_opts = %{qemu_opts_base} -serial mon:stdio -machine 
virt,gic_version=3 -cpu cortex-a53 -m 4096
-- 
2.20.1

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[PATCH v1 2/2] Add AArch64 documentation

[Kinsey Moore]

---
 cpu-supplement/aarch64.rst | 129 +
 user/bsps/aarch64/a53.rst  |  26 
 user/bsps/bsps-aarch64.rst |   2 +-
 3 files changed, 156 insertions(+), 1 deletion(-)
 create mode 100644 cpu-supplement/aarch64.rst
 create mode 100644 user/bsps/aarch64/a53.rst

diff --git a/cpu-supplement/aarch64.rst b/cpu-supplement/aarch64.rst
new file mode 100644
index 000..b23f7dc
--- /dev/null
+++ b/cpu-supplement/aarch64.rst
@@ -0,0 +1,129 @@
+.. SPDX-License-Identifier: CC-BY-SA-4.0
+
+.. Copyright (C) 1988, 2020 On-Line Applications Research Corporation (OAR)
+
+AArch64 Specific Information
+
+
+This chapter discusses the dependencies of the
+*ARM AArch64 architecture*
+(https://en.wikipedia.org/wiki/ARM_architecture#AArch64_features) in this port
+of RTEMS.  The ARMv8-A versions are supported by RTEMS.  Processors with a MMU
+use a static configuration which is set up during system start.  SMP is not
+supported.
+
+**Architecture Documents**
+
+For information on the ARM AArch64 architecture refer to the *ARM Infocenter*
+(http://infocenter.arm.com/).
+
+CPU Model Dependent Features
+
+
+This section presents the set of features which vary across ARM AArch64
+implementations and are of importance to RTEMS.  The set of CPU model feature
+macros are defined in the file 
:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
+based upon the particular CPU model flags specified on the compilation command
+line.
+
+CPU Model Name
+--
+
+The macro ``CPU_MODEL_NAME`` is a string which designates the architectural
+level of this CPU model.  See in 
:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
+for the values.
+
+Floating Point Unit and SIMD
+
+
+The Advanced SIMD (NEON) and Floating-point instruction set extension is
+supported and expected to be present since all ARMv8-A CPUs are expected to
+support it as per the *ARMv8-A Programmer's Guide Chapter 7 introduction*
+(https://developer.arm.com/docs/den0024/a/aarch64-floating-point-and-neon). As
+such, ``CPU_HARDWARE_FP`` will always be set to ``TRUE``.
+
+Multilibs
+=
+
+The following multilib variants are available:
+
+#. ``ILP32``: AArch64 instruction set and registers using 32bit long int and 
pointers
+
+#. ``LP64``: AArch64 instruction set and registers using 64bit long int and 
pointers
+
+Use for example the following GCC options:
+
+.. code-block:: shell
+
+-mcpu=cortex-a53 -mabi=ilp32
+
+to build an application or BSP for the ARMv8-A architecture and tune the code
+for a Cortex-A53 processor.  It is important to select the correct ABI.
+
+Calling Conventions
+===
+
+Please refer to the *Procedure Call Standard for the ARM 64-bit Architecture*
+(https://github.com/ARM-software/abi-aa/releases/download/2019Q4/aapcs64.pdf).
+
+Memory Model
+
+
+A flat 64-bit or 32-bit memory model is supported depending on the selected 
multilib
+variant.  All AArch64 CPU variants support a built-in MMU for which basic 
initialization
+for a flat memory model is handled.
+
+Interrupt Processing
+
+
+The Reset Vector is determined using RVBAR and is Read-Only. RVBAR is set using
+configuration signals only sampled at reset.  The ARMv8 architecture has four
+exception types: 
+
+- Synchronous Exception
+
+- Interrupt (IRQ)
+
+- Fast Interrupt (FIQ)
+
+- System Error Exception
+
+Of these types only the synchronous and IRQ exceptions have explicit operating
+system support.  It is intentional that the FIQ is not supported by the 
operating
+system.  Without operating system support for the FIQ it is not necessary to
+disable them during critical sections of the system.
+
+Interrupt Levels
+
+
+There are exactly two interrupt levels on ARMv8 with respect to RTEMS.  Level
+zero corresponds to interrupts enabled.  Level one corresponds to interrupts
+disabled.
+
+Interrupt Stack
+---
+
+The board support package must initialize the interrupt stack. The memory for
+the stacks is usually reserved in the linker script.
+
+Default Fatal Error Processing
+==
+
+The default fatal error handler for this architecture performs the following
+actions:
+
+- disables operating system supported interrupts (IRQ),
+
+- places the error code in ``x0``, and
+
+- executes an infinite loop to simulate a halt processor instruction.
+
+Symmetric Multiprocessing
+=
+
+SMP is not currently supported on ARMv8-A.
+
+Thread-Local Storage
+
+
+Thread-local storage is supported.
diff --git a/user/bsps/aarch64/a53.rst b/user/bsps/aarch64/a53.rst
new file mode 100644
index 000..0052773
--- /dev/null
+++ b/user/bsps/aarch64/a53.rst
@@ -0,0 +1,26 @@
+.. SPDX-License-Identifier: CC-BY-SA-4.0
+
+.. Copyright (C) 2020 Kinsey Moore, On-Line Applications Research Corporation 
(OAR)
+
+.. _BSP_aarch64_qemu_a53_ilp32

[PATCH v1 1/2] cpu-supplement: Fix formatting and missing words

[Kinsey Moore]

---
 cpu-supplement/arm.rst | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/cpu-supplement/arm.rst b/cpu-supplement/arm.rst
index 63aa532..26d88ea 100644
--- a/cpu-supplement/arm.rst
+++ b/cpu-supplement/arm.rst
@@ -34,7 +34,7 @@ for the values.
 Count Leading Zeroes Instruction
 
 
-The ARMv5 and later has the count leading zeroes ``clz`` instruction which
+The ARMv5 and later instruction sets have the count leading zeroes ``clz`` 
instruction which
 could be used to speed up the find first bit operation.  The use of this
 instruction should significantly speed up the scheduling associated with a
 thread blocking.  This is currently not used.
@@ -130,7 +130,7 @@ Memory Model
 
 
 A flat 32-bit memory model is supported.  The board support package must take
-care about the MMU if necessary.
+care of initializing the MMU if necessary.
 
 Interrupt Processing
 
@@ -196,11 +196,11 @@ Symmetric Multiprocessing
 
 SMP is supported on ARMv7-A.  Available platforms are
 
-- Altera Cyclone V,
+- Altera Cyclone V
 
-- NXP i.MX 7, and
+- NXP i.MX 7
 
-- Xilinx Zynq.
+- Xilinx Zynq
 
 Thread-Local Storage
 
-- 
2.20.1

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[PATCH v1 6/8] score: Add AArch64 port

[Kinsey Moore]

This adds a CPU port for AArch64(ARMv8) with support for exceptions and
interrupts.
---
 cpukit/include/rtems/score/tls.h  |   2 +-
 .../cpu/aarch64/aarch64-context-validate.S| 295 ++
 .../aarch64-context-volatile-clobber.S|  90 +++
 .../cpu/aarch64/aarch64-exception-default.S   | 407 +
 .../cpu/aarch64/aarch64-exception-default.c   |  39 ++
 .../aarch64/aarch64-exception-frame-print.c   |  96 +++
 .../cpu/aarch64/aarch64-exception-interrupt.S | 306 ++
 .../score/cpu/aarch64/aarch64-thread-idle.c   |  48 ++
 cpukit/score/cpu/aarch64/cpu.c| 196 +++
 cpukit/score/cpu/aarch64/cpu_asm.S| 134 +
 .../cpu/aarch64/include/libcpu/vectors.h  | 101 
 cpukit/score/cpu/aarch64/include/rtems/asm.h  |  90 +++
 .../cpu/aarch64/include/rtems/score/aarch64.h |  81 +++
 .../cpu/aarch64/include/rtems/score/cpu.h | 548 ++
 .../aarch64/include/rtems/score/cpuatomic.h   |  34 ++
 .../cpu/aarch64/include/rtems/score/cpuimpl.h |  81 +++
 spec/build/cpukit/cpuaarch64.yml  |  32 +
 spec/build/cpukit/librtemscpu.yml |   2 +
 18 files changed, 2581 insertions(+), 1 deletion(-)
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-validate.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-volatile-clobber.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-interrupt.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-thread-idle.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu_asm.S
 create mode 100644 cpukit/score/cpu/aarch64/include/libcpu/vectors.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/asm.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/aarch64.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuatomic.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
 create mode 100644 spec/build/cpukit/cpuaarch64.yml

diff --git a/cpukit/include/rtems/score/tls.h b/cpukit/include/rtems/score/tls.h
index 65a49d87be..8c15eee569 100644
--- a/cpukit/include/rtems/score/tls.h
+++ b/cpukit/include/rtems/score/tls.h
@@ -85,7 +85,7 @@ typedef struct TLS_Thread_control_block {
   struct TLS_Thread_control_block *tcb;
 #else /* !__i386__ */
   TLS_Dynamic_thread_vector *dtv;
-#if CPU_SIZEOF_POINTER == 4
+#if CPU_SIZEOF_POINTER == 4 || CPU_SIZEOF_POINTER == 8
   uintptr_t reserved;
 #endif
 #endif /* __i386__ */
diff --git a/cpukit/score/cpu/aarch64/aarch64-context-validate.S 
b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
new file mode 100644
index 00..afd339ad85
--- /dev/null
+++ b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
@@ -0,0 +1,295 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+#include 
+
+#define FRAME_OFFSET_X4 0
+#define FRAME_OFFSET_X5 8
+#define FRAME_OFFSET_X6 16
+#define FRAME_OFFSET_X7 24
+#define FRAME_OFFSET_X8 32
+#define FRAME_OFFSET_X9 40
+#define FRAME_OFFSET_X10 48
+#define FRAME_OFFSET_X11 56
+#define FRAME_OFFSET_LR 64
+
+#ifdef AARCH64_MULTILIB_VFP
+  #define FRAME_OFFSET_V8 72
+  #define FRAME_OFFSET_V9 88
+  #def

[PATCH v1 4/8] bsps: Break out AArch32 GICv3 support

[Kinsey Moore]

nclude/bsp/arm-pl111-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-release-id.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/armv7m-irq.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/clock-armv7m.h
+include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/irq-arch.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/linker-symbols.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-dma.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/lpc-emc.h
diff --git a/bsps/arm/include/bsp/irq-arch.h b/bsps/arm/include/bsp/irq-arch.h
new file mode 100644
index 00..c902f68953
--- /dev/null
+++ b/bsps/arm/include/bsp/irq-arch.h
@@ -0,0 +1,42 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_IRQ_ARCH_H
+#define LIBBSP_ARM_SHARED_IRQ_ARCH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+void bsp_interrupt_dispatch( void );
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_SHARED_IRQ_ARCH_H */
diff --git a/bsps/arm/lpc24xx/irq/irq-dispatch.c 
b/bsps/arm/lpc24xx/irq/irq-dispatch.c
index 66d05fdf9d..7baa527595 100644
--- a/bsps/arm/lpc24xx/irq/irq-dispatch.c
+++ b/bsps/arm/lpc24xx/irq/irq-dispatch.c
@@ -24,6 +24,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 
diff --git a/bsps/arm/lpc32xx/irq/irq.c b/bsps/arm/lpc32xx/irq/irq.c
index eac32b..f0c1f4f548 100644
--- a/bsps/arm/lpc32xx/irq/irq.c
+++ b/bsps/arm/lpc32xx/irq/irq.c
@@ -23,6 +23,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/bsps/arm/raspberrypi/irq/irq.c b/bsps/arm/raspberrypi/irq/irq.c
index 835cdf97d9..1e5e4735b3 100644
--- a/bsps/arm/raspberrypi/irq/irq.c
+++ b/bsps/arm/raspberrypi/irq/irq.c
@@ -25,6 +25,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/bsps/arm/rtl22xx/irq/irq.c b/bsps/arm/rtl22xx/irq/irq.c
index 83e140bd7b..7f94958105 100644
--- a/bsps/arm/rtl22xx/irq/irq.c
+++ b/bsps/arm/rtl22xx/irq/irq.c
@@ -13,6 +13,7 @@
 
 #include 
 #include 
+#include 
 #include 
 
 #include 
diff --git a/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c 
b/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
new file mode 100644
index 00..bff1256533
--- /dev/null
+++ b/bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
@@ -0,0 +1,47 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,

[PATCH v1 3/8] bsps: Break out AArch32 portions of GPT driver

[Kinsey Moore]

This breaks AArch32-specific portions of the ARM GPT driver into their
own file so that the generic code can be moved for reuse by other
architectures.
---
 bsps/arm/imx/headers.am   |  1 +
 bsps/arm/imx/include/bsp.h|  2 -
 bsps/arm/imx/start/bspstart.c |  3 +-
 .../clock/clock-arm-generic-timer-aarch32.c   | 68 +++
 bsps/arm/xen/headers.am   |  1 +
 bsps/arm/xen/include/bsp.h|  2 -
 bsps/arm/xen/start/bspstart.c |  3 +-
 bsps/arm/xilinx-zynqmp/headers.am |  1 +
 bsps/arm/xilinx-zynqmp/include/bsp.h  |  2 -
 bsps/arm/xilinx-zynqmp/start/bspstart.c   |  3 +-
 bsps/include/bsp/clock-arm-generic-timer.h| 65 ++
 .../clock/clock-arm-generic-timer.c}  | 65 --
 c/src/lib/libbsp/arm/imx/Makefile.am  |  3 +-
 c/src/lib/libbsp/arm/xen/Makefile.am  |  3 +-
 .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am  |  3 +-
 spec/build/bsps/arm/imx/bspimx.yml|  4 +-
 spec/build/bsps/arm/xen/bspxen.yml|  4 +-
 .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml |  4 +-
 18 files changed, 171 insertions(+), 66 deletions(-)
 create mode 100644 bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c
 create mode 100644 bsps/include/bsp/clock-arm-generic-timer.h
 rename bsps/{arm/shared/clock/clock-generic-timer.c => 
shared/clock/clock-arm-generic-timer.c} (71%)

diff --git a/bsps/arm/imx/headers.am b/bsps/arm/imx/headers.am
index 3a093b1698..76c1607871 100644
--- a/bsps/arm/imx/headers.am
+++ b/bsps/arm/imx/headers.am
@@ -21,3 +21,4 @@ include_bspdir = $(includedir)/bsp
 include_bsp_HEADERS =
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/imx-gpio.h
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/irq.h
+include_bsp_HEADERS += 
../../../../../../bsps/include/bsp/clock-arm-generic-timer.h
diff --git a/bsps/arm/imx/include/bsp.h b/bsps/arm/imx/include/bsp.h
index 134b3fd858..99b7a0d1d7 100644
--- a/bsps/arm/imx/include/bsp.h
+++ b/bsps/arm/imx/include/bsp.h
@@ -57,8 +57,6 @@ extern uintptr_t imx_gic_dist_base;
 
 #define BSP_ARM_A9MPCORE_SCU_BASE 0
 
-void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq);
-
 void *imx_get_reg_of_node(const void *fdt, int node);
 
 int imx_iomux_configure_pins(const void *fdt, uint32_t phandle);
diff --git a/bsps/arm/imx/start/bspstart.c b/bsps/arm/imx/start/bspstart.c
index 5fb07bf60a..ff5edaf5a1 100644
--- a/bsps/arm/imx/start/bspstart.c
+++ b/bsps/arm/imx/start/bspstart.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -58,7 +59,7 @@ uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
   return intr[1] + MAGIC_IRQ_OFFSET;
 }
 
-void arm_generic_timer_get_config(
+void aarch_generic_timer_get_config(
   uint32_t *frequency,
   uint32_t *irq
 )
diff --git a/bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c 
b/bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c
new file mode 100644
index 00..c9d26945ea
--- /dev/null
+++ b/bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c
@@ -0,0 +1,68 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+uint64_t aarch_gt_clock_get_compare_value(void)
+{
+#ifdef ARM_GENERIC_TIMER_USE_VIRTUAL
+  return arm_cp15_get_counter_pl1_virtual_compare_value();
+#else
+  return arm_cp15_get_counter_pl1_physical_compare_value();
+#endif
+}
+
+void aarch_gt_clock_set_compare_value(uint64_t cva

[PATCH v1 0/8] AArch64 port and BSPs

[Kinsey Moore]

This patch set includes changes to move several required drivers
into bsps/shared so that they can be used by both AArch32(known in RTEMS
as "arm") and AArch64 as well as possibly other future architectures.
The changes made in breaking out these drivers have been tested on 10 or
so affected BSPs under both the old autotools build system and the new
waf build system.

In addition to the AArch64 port itself, this patch set includes a pair
of sample BSPs that run on QEMU and demonstrate use of the two available
multilib variants: lp64 and ilp32. These BSPs are only configurable
under the waf build system. The port and these BSPs do not currently
support SMP, even though there is some SMP-related code currently in
place.

Look for related patch sets for rtems-doc and rtems-tools following
shortly.


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[PATCH v1 7/8] bsps: Add Cortex-A53 LP64 basic BSP

[Kinsey Moore]

This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with
interrupt support using GICv3 and clock support using the ARM GPT.
---
 bsps/aarch64/a53/console/console.c|  61 ++
 bsps/aarch64/a53/include/bsp.h|  74 +++
 bsps/aarch64/a53/include/bsp/irq.h|  59 ++
 bsps/aarch64/a53/include/tm27.h   |  38 ++
 bsps/aarch64/a53/start/bspstart.c |  41 ++
 bsps/aarch64/a53/start/bspstarthooks.c|  42 ++
 bsps/aarch64/include/bsp/irq-arch.h   |  42 ++
 bsps/aarch64/include/bsp/linker-symbols.h | 161 +
 bsps/aarch64/include/bsp/start.h  | 189 ++
 bsps/aarch64/shared/cache/cache.c | 612 ++
 .../clock/clock-arm-generic-timer-aarch64.c   | 102 +++
 .../shared/irq/irq-arm-gicv3-aarch64.c|  50 ++
 bsps/aarch64/shared/start/linkcmds.base   | 450 +
 bsps/aarch64/shared/start/start.S | 217 +++
 spec/build/bsps/aarch64/a53/abi.yml   |  14 +
 .../build/bsps/aarch64/a53/bspa53lp64qemu.yml |  70 ++
 spec/build/bsps/aarch64/a53/linkcmds.yml  |  65 ++
 spec/build/bsps/aarch64/a53/optloadoff.yml|  15 +
 spec/build/bsps/aarch64/a53/optnocachelen.yml |  15 +
 spec/build/bsps/aarch64/a53/optramlen.yml |  15 +
 spec/build/bsps/aarch64/a53/optramori.yml |  15 +
 spec/build/bsps/aarch64/a53/tsta53.yml|  53 ++
 spec/build/bsps/aarch64/start.yml |  11 +
 23 files changed, 2411 insertions(+)
 create mode 100644 bsps/aarch64/a53/console/console.c
 create mode 100644 bsps/aarch64/a53/include/bsp.h
 create mode 100644 bsps/aarch64/a53/include/bsp/irq.h
 create mode 100644 bsps/aarch64/a53/include/tm27.h
 create mode 100644 bsps/aarch64/a53/start/bspstart.c
 create mode 100644 bsps/aarch64/a53/start/bspstarthooks.c
 create mode 100644 bsps/aarch64/include/bsp/irq-arch.h
 create mode 100644 bsps/aarch64/include/bsp/linker-symbols.h
 create mode 100644 bsps/aarch64/include/bsp/start.h
 create mode 100644 bsps/aarch64/shared/cache/cache.c
 create mode 100644 bsps/aarch64/shared/clock/clock-arm-generic-timer-aarch64.c
 create mode 100644 bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c
 create mode 100644 bsps/aarch64/shared/start/linkcmds.base
 create mode 100644 bsps/aarch64/shared/start/start.S
 create mode 100644 spec/build/bsps/aarch64/a53/abi.yml
 create mode 100644 spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
 create mode 100644 spec/build/bsps/aarch64/a53/linkcmds.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optloadoff.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optnocachelen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramlen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramori.yml
 create mode 100644 spec/build/bsps/aarch64/a53/tsta53.yml
 create mode 100644 spec/build/bsps/aarch64/start.yml

diff --git a/bsps/aarch64/a53/console/console.c 
b/bsps/aarch64/a53/console/console.c
new file mode 100644
index 00..1a3c8fe8b0
--- /dev/null
+++ b/bsps/aarch64/a53/console/console.c
@@ -0,0 +1,61 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+arm_pl011_context a53_qemu_vpl011_context = {
+  .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("PL011"),
+  .regs = (volatile pl011 *) BSP_A53_QEMU_VPL011_BASE,
+  .initial_baud = 115200
+};
+
+const console_device console_device_table[] = {
+  {
+.device_file = "/dev/ttyS0",
+.probe = console_device_probe_default,
+.handl

[PATCH v1 5/8] bsps/shared: Add PSCI-based bspreset implementation

[Kinsey Moore]

This adds a bsp_reset implementation based on the ARM PSCI
specification often present in ARMv8 systems.
---
 bsps/shared/start/bspreset-psci.c | 48 +++
 1 file changed, 48 insertions(+)
 create mode 100644 bsps/shared/start/bspreset-psci.c

diff --git a/bsps/shared/start/bspreset-psci.c 
b/bsps/shared/start/bspreset-psci.c
new file mode 100644
index 00..33dd38e814
--- /dev/null
+++ b/bsps/shared/start/bspreset-psci.c
@@ -0,0 +1,48 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+void bsp_reset(void)
+{
+   uint32_t PSCI_FN_SYSTEM_RESET = 0x8409;
+   __asm__ volatile(
+#if defined(AARCH64_MULTILIB_ARCH_V8) || 
defined(AARCH64_MULTILIB_ARCH_V8_ILP32)
+   "mov x0, %0\n"
+#else
+   "mov r0, %0\n"
+#endif
+#ifdef BSP_RESET_SMC
+   "smc #0\n"
+#else
+   "hvc #0\n"
+#endif
+   : : "r" (PSCI_FN_SYSTEM_RESET)
+   );
+}
-- 
2.20.1

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[PATCH v1 8/8] bsps: Add Cortex-A53 ILP32 BSP variant

[Kinsey Moore]

v/serial/console-termios.c
+- bsps/shared/start/bspfatal-default.c
+- bsps/shared/start/bspgetworkarea-default.c
+- bsps/shared/start/bspreset-psci.c
+- bsps/shared/start/sbrk.c
+- bsps/shared/irq/irq-arm-gicv3.c
+- bsps/shared/irq/irq-default-handler.c
+- bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c
+- bsps/shared/dev/btimer/btimer-cpucounter.c
+- bsps/shared/clock/clock-arm-generic-timer.c
+- bsps/aarch64/shared/clock/clock-arm-generic-timer-aarch64.c
+type: build
diff --git a/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml 
b/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
index 06c3a91265..ee99200b18 100644
--- a/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
+++ b/spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
@@ -46,7 +46,7 @@ links:
 - role: build-dependency
   uid: ../../opto2
 - role: build-dependency
-  uid: linkcmds
+  uid: linkcmds_lp64
 - role: build-dependency
   uid: ../../bspopts
 source:
diff --git a/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml 
b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
new file mode 100644
index 00..9f6872215a
--- /dev/null
+++ b/spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
@@ -0,0 +1,68 @@
+build-type: config-file
+content: |
+  /*
+   * SPDX-License-Identifier: BSD-2-Clause
+   *
+   * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+   * Written by Kinsey Moore 
+   *
+   * Redistribution and use in source and binary forms, with or without
+   * modification, are permitted provided that the following conditions
+   * are met:
+   * 1. Redistributions of source code must retain the above copyright
+   *notice, this list of conditions and the following disclaimer.
+   * 2. Redistributions in binary form must reproduce the above copyright
+   *notice, this list of conditions and the following disclaimer in the
+   *documentation and/or other materials provided with the distribution.
+   *
+   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
IS"
+   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   * POSSIBILITY OF SUCH DAMAGE.
+   */
+
+  MEMORY {
+RAM   : ORIGIN = ${BSP_A53_RAM_BASE} + ${BSP_A53_LOAD_OFFSET}, LENGTH 
= ${BSP_A53_RAM_LENGTH} - ${BSP_A53_LOAD_OFFSET} - ${BSP_A53_NOCACHE_LENGTH}
+NOCACHE   : ORIGIN = ${BSP_A53_RAM_BASE} + ${BSP_A53_RAM_LENGTH} - 
${BSP_A53_NOCACHE_LENGTH}, LENGTH = ${BSP_A53_NOCACHE_LENGTH}
+  }
+
+  REGION_ALIAS ("REGION_START",  RAM);
+  REGION_ALIAS ("REGION_VECTOR", RAM);
+  REGION_ALIAS ("REGION_TEXT",   RAM);
+  REGION_ALIAS ("REGION_TEXT_LOAD",  RAM);
+  REGION_ALIAS ("REGION_RODATA", RAM);
+  REGION_ALIAS ("REGION_RODATA_LOAD",RAM);
+  REGION_ALIAS ("REGION_DATA",   RAM);
+  REGION_ALIAS ("REGION_DATA_LOAD",  RAM);
+  REGION_ALIAS ("REGION_FAST_TEXT",  RAM);
+  REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM);
+  REGION_ALIAS ("REGION_FAST_DATA",  RAM);
+  REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM);
+  REGION_ALIAS ("REGION_BSS",RAM);
+  REGION_ALIAS ("REGION_WORK",   RAM);
+  REGION_ALIAS ("REGION_STACK",  RAM);
+  REGION_ALIAS ("REGION_NOCACHE",NOCACHE);
+  REGION_ALIAS ("REGION_NOCACHE_LOAD",   NOCACHE);
+
+  bsp_stack_exception_size = DEFINED (bsp_stack_exception_size) ? 
bsp_stack_exception_size : 1024;
+
+  bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? 
bsp_section_rwbarrier_align : 1M;
+
+  bsp_vector_table_in_start_section = 1;
+
+  OUTPUT_FORMAT ("elf32-littleaarch64")
+  OUTPUT_ARCH (aarch64:ilp32)
+
+  INCLUDE linkcmds.base
+enabled-by: true
+install-path: ${BSP_LIBDIR}
+links: []
+target: linkcmds
+type: build
diff --git a/spec/build/bsps/aarch64/a53/linkcmds.yml 
b/spec/build/bsps/aarch64/a53/linkcmds_lp64.yml
similarity index 97%
rename from spec/build/bsps/aarch64/a53/linkcmds.yml
rename to spec/build/bsps/aarch64/a53/linkcmds_lp64.yml
index 23c99f693a..33732a7fbb 100644
--- a/spec/build/bsps/aarch64/a53/linkcmds.yml
+++ b/spec/build/bsps/aarch64/a53/linkcmds_lp64.yml
@@ -57,6 +57,9 @@ content: |
 
   bsp_vector_table_in_start_section = 1;
 
+  OUTPUT_FORMAT ("elf64-littleaarch64")

[PATCH v1 2/8] spec: Add missing spintrcritical24 definition

[Kinsey Moore]

---
 spec/build/bsps/tstnointrcrit.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/spec/build/bsps/tstnointrcrit.yml 
b/spec/build/bsps/tstnointrcrit.yml
index 0460aaabb3..46f7d974c8 100644
--- a/spec/build/bsps/tstnointrcrit.yml
+++ b/spec/build/bsps/tstnointrcrit.yml
@@ -24,6 +24,7 @@ actions:
 spintrcritical21: exclude
 spintrcritical22: exclude
 spintrcritical23: exclude
+spintrcritical24: exclude
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-- 
2.20.1

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[PATCH v1 1/8] Move ARM PL011 UART driver

[Kinsey Moore]

This UART driver is now needed for BSPs other than ARM.
---
 bsps/arm/headers.am| 2 --
 bsps/arm/raspberrypi/console/console-config.c  | 2 +-
 bsps/arm/realview-pbx-a9/include/bsp/console.h | 2 +-
 bsps/arm/xen/console/console.c | 2 +-
 bsps/headers.am| 2 ++
 bsps/{arm/include/bsp => include/libchip}/arm-pl011-regs.h | 0
 bsps/{arm/include/bsp => include/libchip}/arm-pl011.h  | 2 +-
 bsps/{arm/shared => shared/dev}/serial/arm-pl011.c | 2 +-
 c/src/lib/libbsp/arm/raspberrypi/Makefile.am   | 2 +-
 c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am   | 2 +-
 c/src/lib/libbsp/arm/xen/Makefile.am   | 2 +-
 spec/build/bsps/arm/grp.yml| 2 --
 spec/build/bsps/arm/raspberrypi/obj.yml| 1 -
 spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml   | 1 -
 spec/build/bsps/arm/xen/bspxen.yml | 1 -
 spec/build/bsps/obj.yml| 3 +++
 16 files changed, 13 insertions(+), 15 deletions(-)
 rename bsps/{arm/include/bsp => include/libchip}/arm-pl011-regs.h (100%)
 rename bsps/{arm/include/bsp => include/libchip}/arm-pl011.h (96%)
 rename bsps/{arm/shared => shared/dev}/serial/arm-pl011.c (98%)

diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am
index 3d2b09effa..f0d498c8f4 100644
--- a/bsps/arm/headers.am
+++ b/bsps/arm/headers.am
@@ -21,8 +21,6 @@ include_bsp_HEADERS += 
../../../../../bsps/arm/include/bsp/arm-gic-irq.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-tm27.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011-regs.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl111-fb.h
diff --git a/bsps/arm/raspberrypi/console/console-config.c 
b/bsps/arm/raspberrypi/console/console-config.c
index bb0b596019..27d02bbe39 100644
--- a/bsps/arm/raspberrypi/console/console-config.c
+++ b/bsps/arm/raspberrypi/console/console-config.c
@@ -25,13 +25,13 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/bsps/arm/realview-pbx-a9/include/bsp/console.h 
b/bsps/arm/realview-pbx-a9/include/bsp/console.h
index da2e4099e2..0ed99ec86e 100644
--- a/bsps/arm/realview-pbx-a9/include/bsp/console.h
+++ b/bsps/arm/realview-pbx-a9/include/bsp/console.h
@@ -15,7 +15,7 @@
 #ifndef LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 #define LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xen/console/console.c b/bsps/arm/xen/console/console.c
index 786b98f3ba..446bd2c3b8 100644
--- a/bsps/arm/xen/console/console.c
+++ b/bsps/arm/xen/console/console.c
@@ -29,7 +29,7 @@
 #include 
 
 #include 
-#include 
+#include 
 #include 
 #include 
 
diff --git a/bsps/headers.am b/bsps/headers.am
index 5af7e43b4a..825574a5a9 100644
--- a/bsps/headers.am
+++ b/bsps/headers.am
@@ -110,6 +110,8 @@ include_libchip_HEADERS += 
../../bsps/include/libchip/mc68681.h
 include_libchip_HEADERS += ../../bsps/include/libchip/ns16550.h
 include_libchip_HEADERS += ../../bsps/include/libchip/ns16550_p.h
 include_libchip_HEADERS += ../../bsps/include/libchip/open_eth.h
+include_libchip_HEADERS += ../../bsps/include/libchip/arm-pl011-regs.h
+include_libchip_HEADERS += ../../bsps/include/libchip/arm-pl011.h
 include_libchip_HEADERS += ../../bsps/include/libchip/rtc.h
 include_libchip_HEADERS += ../../bsps/include/libchip/serial.h
 include_libchip_HEADERS += ../../bsps/include/libchip/sersupp.h
diff --git a/bsps/arm/include/bsp/arm-pl011-regs.h 
b/bsps/include/libchip/arm-pl011-regs.h
similarity index 100%
rename from bsps/arm/include/bsp/arm-pl011-regs.h
rename to bsps/include/libchip/arm-pl011-regs.h
diff --git a/bsps/arm/include/bsp/arm-pl011.h b/bsps/include/libchip/arm-pl011.h
similarity index 96%
rename from bsps/arm/include/bsp/arm-pl011.h
rename to bsps/include/libchip/arm-pl011.h
index 49ff413581..947c254bd8 100644
--- a/bsps/arm/include/bsp/arm-pl011.h
+++ b/bsps/include/libchip/arm-pl011.h
@@ -25,7 +25,7 @@
 
 #include 
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/shared/serial/arm-pl011.c 
b/bsps/shared/dev/serial/arm-pl011.c
similarity index 98%
rename from bsps/arm/shared/serial/arm-pl011.c
rename to bsps/shared/dev/serial/arm-pl011.c
index 44a409e551..39225e8349 100644
--- a/bsps/arm/shared/serial/arm-pl011.c
+++ b/bsps/shared/dev/serial/arm-pl011.c

RE: New build system ready for testing

[Kinsey Moore]

This is great news as the AArch64 work I've been doing was built on your waf 
branch and now I can rebase on to mainline code. I had assumed that the old 
build system would be removed when the new build system got added, but that 
obviously didn't happen. Will it eventually be removed after a transition 
period is over or will they both exist and be maintained going forward?

Kinsey

-Original Message-
From: devel  On Behalf Of Sebastian Huber
Sent: Monday, September 14, 2020 02:08
To: RTEMS 
Subject: New build system ready for testing

Hello,

I checked in the new build system today. Now is a good time to test your 
favourite BSP if it still works. You find the user oriented documentation of 
build system here:

https://docs.rtems.org/branches/master/user/bld/index.html

The documentation for RTEMS maintainers is here:

https://docs.rtems.org/branches/master/eng/build-system.html

How to check the new build system for a particular BSP?

1. Build the BSP with all tests enabled.

2. Run the tests and compare the results with the old build system. 
Ideally use the RTEMS Tester to run the tests and report them to the RTEMS 
Project.

3. Check if all BSP options are available (./waf bsp_defaults). Check the type 
and values of the BSP options.

4. Check the linker command file.

5. Check the compiler machine flags.

6. Install the BSP and build your third-party libraries and applications with 
it.

--
Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail  : sebastian.hu...@embedded-brains.de
PGP : Public key available on request.

Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
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AArch64 support and sharing of various drivers

[Kinsey Moore]

Hi,
I've been working on proper AArch64 support for RTEMS (versus running 32-bit 
ARM RTEMS behind a bootloader or JTAG device that switches the CPU to AArch32 
mode) and while the vast majority of the architecture support code is new, 
lives in its own aarch64 directories, and is unrelated to RTEMS's ARM support, 
there are several drivers living in the ARM shared directory that are critical 
to AArch64 support and many more that could potentially be shared. Given the 
limited scope of initial bringup on Qemu, that list is currently: GICv3, 
GPT(timer), and PL011(uart). I don't really see a precedent for this type of 
sharing other than the global bsps/shared and bsps/include directories. The 
global shared directories might make sense for the PL011 since it could 
theoretically be used by anything that supports AXI/AMBA, but the GIC and GPT 
drivers rely on ARM system registers to function with both AArch32 and AArch64.

In short, where should the GICv3 and GPT drivers be relocated along with their 
associated headers, if at all?

Thanks,
Kinsey Moore
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[PATCH v3] libcsupport: Address *tors FIXME

[Kinsey Moore]

This introduces the CPU_USE_LIBC_INIT_FINI_ARRAY define for use by CPU
ports to determine which global constructor and destructor methods are
used instead of placing architecture defines where they shouldn't be.

Close #4018
---
 cpukit/libcsupport/src/newlibc_exit.c   | 5 +
 cpukit/score/cpu/arm/include/rtems/score/cpu.h  | 2 ++
 cpukit/score/cpu/bfin/include/rtems/score/cpu.h | 2 ++
 cpukit/score/cpu/epiphany/include/rtems/score/cpu.h | 2 ++
 cpukit/score/cpu/i386/include/rtems/score/cpu.h | 2 ++
 cpukit/score/cpu/lm32/include/rtems/score/cpu.h | 2 ++
 cpukit/score/cpu/m68k/include/rtems/score/cpu.h | 2 ++
 cpukit/score/cpu/mips/include/rtems/score/cpu.h | 2 ++
 cpukit/score/cpu/moxie/include/rtems/score/cpu.h| 2 ++
 cpukit/score/cpu/nios2/include/rtems/score/cpu.h| 2 ++
 cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h   | 7 +++
 cpukit/score/cpu/or1k/include/rtems/score/cpu.h | 2 ++
 cpukit/score/cpu/powerpc/include/rtems/score/cpu.h  | 3 +++
 cpukit/score/cpu/riscv/include/rtems/score/cpu.h| 2 ++
 cpukit/score/cpu/sh/include/rtems/score/cpu.h   | 2 ++
 cpukit/score/cpu/sparc/include/rtems/score/cpu.h| 2 ++
 cpukit/score/cpu/sparc64/include/rtems/score/cpu.h  | 2 ++
 cpukit/score/cpu/v850/include/rtems/score/cpu.h | 2 ++
 cpukit/score/cpu/x86_64/include/rtems/score/cpu.h   | 2 ++
 cpukit/score/src/threadhandler.c| 8 ++--
 20 files changed, 49 insertions(+), 6 deletions(-)

diff --git a/cpukit/libcsupport/src/newlibc_exit.c 
b/cpukit/libcsupport/src/newlibc_exit.c
index 650b692c74..d29214af3f 100644
--- a/cpukit/libcsupport/src/newlibc_exit.c
+++ b/cpukit/libcsupport/src/newlibc_exit.c
@@ -17,11 +17,8 @@
 #include 
 #include 
 
-/* FIXME: These defines are a blatant hack */
-
   #if defined(__USE_INIT_FINI__)
-#if defined(__ARM_EABI__) || defined(__riscv) \
-  || defined(__or1k__) || defined(__or1knd__)
+#if CPU_USE_LIBC_INIT_FINI_ARRAY == TRUE
   #define FINI_SYMBOL __libc_fini_array
 #else
   #define FINI_SYMBOL _fini
diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpu.h 
b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
index b7b48a3ac3..b90fb1f394 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
@@ -153,6 +153,8 @@
 
 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
 
+#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
+
 #define CPU_MAXIMUM_PROCESSORS 32
 
 #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpu.h 
b/cpukit/score/cpu/bfin/include/rtems/score/cpu.h
index 893a3ae359..3b0f0bece3 100644
--- a/cpukit/score/cpu/bfin/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/bfin/include/rtems/score/cpu.h
@@ -507,6 +507,8 @@ void _CPU_Context_Initialize(
 
 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
 
+#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
+
 /* functions */
 
 /**
diff --git a/cpukit/score/cpu/epiphany/include/rtems/score/cpu.h 
b/cpukit/score/cpu/epiphany/include/rtems/score/cpu.h
index 462ffab040..70a9790606 100644
--- a/cpukit/score/cpu/epiphany/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/epiphany/include/rtems/score/cpu.h
@@ -445,6 +445,8 @@ void _CPU_Context_Initialize(
 
 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
 
+#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
+
 #endif /* ASM */
 
 /**
diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpu.h 
b/cpukit/score/cpu/i386/include/rtems/score/cpu.h
index 0145ff8db3..225b72802d 100644
--- a/cpukit/score/cpu/i386/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/i386/include/rtems/score/cpu.h
@@ -503,6 +503,8 @@ extern void _CPU_Fatal_halt(uint32_t source, uint32_t error)
 
 /* end of Fatal Error manager macros */
 
+#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
+
 /*
  *  Bitfield handler macros
  *
diff --git a/cpukit/score/cpu/lm32/include/rtems/score/cpu.h 
b/cpukit/score/cpu/lm32/include/rtems/score/cpu.h
index 13f8f36194..8e702992c1 100644
--- a/cpukit/score/cpu/lm32/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/lm32/include/rtems/score/cpu.h
@@ -628,6 +628,8 @@ extern char _gp[];
 
 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
 
+#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
+
 /* functions */
 
 /**
diff --git a/cpukit/score/cpu/m68k/include/rtems/score/cpu.h 
b/cpukit/score/cpu/m68k/include/rtems/score/cpu.h
index de085c9f7d..777fbfeb30 100644
--- a/cpukit/score/cpu/m68k/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/m68k/include/rtems/score/cpu.h
@@ -433,6 +433,8 @@ void *_CPU_Thread_Idle_body( uintptr_t ignored );
 
 /* end of Fatal Error manager macros */
 
+#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
+
 /*
  *  Bitfield handler macros
  *
diff --git a/cpukit/score/cpu/mips/include/rtems/score/cpu.h 
b/cpukit/score/cpu/mips/include/rtems/score/cpu.h
index c9c212eab5..2b662cd549 100644
--- a/cpukit/score/cpu/mips/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/mips/include/rtems/score/cpu.h
@@ -740,6 +740,8 @@ 

[PATCH v2] libcsupport: Address *tors FIXME

[Kinsey Moore]

This introduces the CPU_USE_LIBC_INIT_FINI_ARRAY define for use by
CPU ports to determine which global constructor and destructor methods
are used instead of placing architecture defines where they shouldn't
be.

Close #4018
---
 cpukit/libcsupport/src/newlibc_exit.c| 5 +
 cpukit/score/cpu/arm/include/rtems/score/cpu.h   | 2 ++
 cpukit/score/cpu/or1k/include/rtems/score/cpu.h  | 2 ++
 cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 2 ++
 cpukit/score/src/threadhandler.c | 3 +--
 5 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/cpukit/libcsupport/src/newlibc_exit.c 
b/cpukit/libcsupport/src/newlibc_exit.c
index 650b692c74..67dec1393a 100644
--- a/cpukit/libcsupport/src/newlibc_exit.c
+++ b/cpukit/libcsupport/src/newlibc_exit.c
@@ -17,11 +17,8 @@
 #include 
 #include 
 
-/* FIXME: These defines are a blatant hack */
-
   #if defined(__USE_INIT_FINI__)
-#if defined(__ARM_EABI__) || defined(__riscv) \
-  || defined(__or1k__) || defined(__or1knd__)
+#if defined(CPU_USE_LIBC_INIT_FINI_ARRAY)
   #define FINI_SYMBOL __libc_fini_array
 #else
   #define FINI_SYMBOL _fini
diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpu.h 
b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
index b7b48a3ac3..b90fb1f394 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
@@ -153,6 +153,8 @@
 
 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
 
+#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
+
 #define CPU_MAXIMUM_PROCESSORS 32
 
 #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
diff --git a/cpukit/score/cpu/or1k/include/rtems/score/cpu.h 
b/cpukit/score/cpu/or1k/include/rtems/score/cpu.h
index 39920bebc3..6790694b05 100644
--- a/cpukit/score/cpu/or1k/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/or1k/include/rtems/score/cpu.h
@@ -435,6 +435,8 @@ void _CPU_Context_Initialize(
 
 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
 
+#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
+
 #endif /* ASM */
 
 #define CPU_SIZEOF_POINTER 4
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h 
b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
index e08307d372..501973a6dc 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
@@ -219,6 +219,8 @@ extern void _CPU_Fatal_halt(uint32_t source, uint32_t 
error) RTEMS_NO_RETURN;
 
 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
 
+#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
+
 #define CPU_MAXIMUM_PROCESSORS 32
 
 typedef uint16_t Priority_bit_map_Word;
diff --git a/cpukit/score/src/threadhandler.c b/cpukit/score/src/threadhandler.c
index acbe186a53..0502ea9d19 100644
--- a/cpukit/score/src/threadhandler.c
+++ b/cpukit/score/src/threadhandler.c
@@ -29,8 +29,7 @@
  *  initialization this target and compiler version uses.
  */
 #if defined(__USE_INIT_FINI__)
-  #if defined(__ARM_EABI__) || defined(__riscv) \
-|| defined(__or1k__) || defined(__or1knd__)
+  #if defined(CPU_USE_LIBC_INIT_FINI_ARRAY)
 #define INIT_NAME __libc_init_array
   #else
 #define INIT_NAME _init
-- 
2.20.1

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[PATCH v1] libcsupport: Address *tors FIXME

[Kinsey Moore]

This introduces the CPU_USE_LIBC_XTORS define for use by CPU ports to
determine which global constructor and destructor methods are used
instead of placing architecture defines where they shouldn't be.

Close #4018
---
 cpukit/libcsupport/src/newlibc_exit.c| 5 +
 cpukit/score/cpu/arm/include/rtems/score/cpu.h   | 2 ++
 cpukit/score/cpu/or1k/include/rtems/score/cpu.h  | 2 ++
 cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 2 ++
 cpukit/score/src/threadhandler.c | 3 +--
 5 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/cpukit/libcsupport/src/newlibc_exit.c 
b/cpukit/libcsupport/src/newlibc_exit.c
index 650b692c74..8e009da096 100644
--- a/cpukit/libcsupport/src/newlibc_exit.c
+++ b/cpukit/libcsupport/src/newlibc_exit.c
@@ -17,11 +17,8 @@
 #include 
 #include 
 
-/* FIXME: These defines are a blatant hack */
-
   #if defined(__USE_INIT_FINI__)
-#if defined(__ARM_EABI__) || defined(__riscv) \
-  || defined(__or1k__) || defined(__or1knd__)
+#if defined(CPU_USE_LIBC_XTORS)
   #define FINI_SYMBOL __libc_fini_array
 #else
   #define FINI_SYMBOL _fini
diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpu.h 
b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
index b7b48a3ac3..634efe64b9 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
@@ -153,6 +153,8 @@
 
 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
 
+#define CPU_USE_LIBC_XTORS TRUE
+
 #define CPU_MAXIMUM_PROCESSORS 32
 
 #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
diff --git a/cpukit/score/cpu/or1k/include/rtems/score/cpu.h 
b/cpukit/score/cpu/or1k/include/rtems/score/cpu.h
index 39920bebc3..84f73e06ca 100644
--- a/cpukit/score/cpu/or1k/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/or1k/include/rtems/score/cpu.h
@@ -435,6 +435,8 @@ void _CPU_Context_Initialize(
 
 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
 
+#define CPU_USE_LIBC_XTORS TRUE
+
 #endif /* ASM */
 
 #define CPU_SIZEOF_POINTER 4
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h 
b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
index e08307d372..08647e814f 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
@@ -219,6 +219,8 @@ extern void _CPU_Fatal_halt(uint32_t source, uint32_t 
error) RTEMS_NO_RETURN;
 
 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
 
+#define CPU_USE_LIBC_XTORS TRUE
+
 #define CPU_MAXIMUM_PROCESSORS 32
 
 typedef uint16_t Priority_bit_map_Word;
diff --git a/cpukit/score/src/threadhandler.c b/cpukit/score/src/threadhandler.c
index acbe186a53..091455b86c 100644
--- a/cpukit/score/src/threadhandler.c
+++ b/cpukit/score/src/threadhandler.c
@@ -29,8 +29,7 @@
  *  initialization this target and compiler version uses.
  */
 #if defined(__USE_INIT_FINI__)
-  #if defined(__ARM_EABI__) || defined(__riscv) \
-|| defined(__or1k__) || defined(__or1knd__)
+  #if defined(CPU_USE_LIBC_XTORS)
 #define INIT_NAME __libc_init_array
   #else
 #define INIT_NAME _init
-- 
2.20.1

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RE: [PATCH] posix: Only check shm_unlink obj_err if necessary

[Kinsey Moore]

Sorry, accidentally sent from my personal account. That was, in fact, me.

Kinsey

From: Will 
Sent: Saturday, June 27, 2020 19:24
To: Gedare Bloom 
Cc: Kinsey Moore ; devel@rtems.org
Subject: Re: [PATCH] posix: Only check shm_unlink obj_err if necessary

Ticket 4016 opened for 5.1 and patch sent with appropriate close tag.

On Sat, Jun 27, 2020 at 4:30 PM Gedare Bloom 
mailto:ged...@rtems.org>> wrote:
This needs a ticket now to apply to 5, and we'll want to apply to 6 also. Can 
you open a ticket and post a patch for 5.1?

On Thu, Jun 25, 2020, 5:49 PM Kinsey Moore 
mailto:kinsey.mo...@oarcorp.com>> wrote:
Hey Gedare,
Setting obj_err to 0 would get the desired outcome, but the logic as it exists 
now is faulty. Setting obj_err to a value that can't be produced by 
_POSIX_Shm_Get_by_name would be a better option, but it would still be checking 
an error value after successful execution. _POSIX_Shm_Get_by_name relies on 
_Objects_Get_by_name internally which states about obj_err: The error 
indication in case of failure. If _POSIX_Shm_Get_by_name returns 
OBJECTS_GET_BY_NAME_NO_OBJECT (which it can), the current logic treats that as 
a success and operates on a NULL pointer.

-Original Message-
From: Gedare Bloom mailto:ged...@rtems.org>>
Sent: Thursday, June 25, 2020 16:49
To: Kinsey Moore mailto:kinsey.mo...@oarcorp.com>>
Cc: devel@rtems.org<mailto:devel@rtems.org>
Subject: Re: [PATCH] posix: Only check shm_unlink obj_err if necessary

Hi Kinsey,

I missed seeing this. Two quick questions for you.

1. does it also work to initialize obj_err to 0? that would be simpler code.

2. I see the error handling logic changes slightly, with 
OBJECTS_GET_BY_NAME_NO_OBJECT now returning ENOENT. I guess if it works to init 
obj_err to 0, this case should be merged back to the 
OBJECTS_GET_BY_NAME_INVALID_NAME case?

On Thu, Jun 25, 2020 at 2:21 PM Kinsey Moore 
mailto:kinsey.mo...@oarcorp.com>> wrote:
>
> Is there anything stopping this from being merged? I just ran into this bug 
> again on the current project I'm working on.
>
> Kinsey
>
> -Original Message-
> From: Kinsey Moore mailto:kinsey.mo...@oarcorp.com>>
> Sent: Tuesday, January 28, 2020 12:37
> To: devel@rtems.org<mailto:devel@rtems.org>
> Cc: Kinsey Moore mailto:kinsey.mo...@oarcorp.com>>
> Subject: [PATCH] posix: Only check shm_unlink obj_err if necessary
>
> In the nominal case checked by spsysinit01, obj_err is unmodified if 
> _POSIX_Shm_Get_by_name returns non-NULL. In the case of shm_unlink, this 
> means an uninitialized value is passed into the switch and it appears this 
> test was passing by virtue of the stack having the right value on it in most 
> cases. This now checks obj_err only if _POSIX_Shm_Get_by_name returns NULL.
> ---
>  cpukit/posix/src/shmunlink.c | 45
> ++--
>  1 file changed, 23 insertions(+), 22 deletions(-)
>
> diff --git a/cpukit/posix/src/shmunlink.c
> b/cpukit/posix/src/shmunlink.c index 00d743ac80..39c2ba0d87 100644
> --- a/cpukit/posix/src/shmunlink.c
> +++ b/cpukit/posix/src/shmunlink.c
> @@ -29,28 +29,29 @@ int shm_unlink( const char *name )
>_Objects_Allocator_lock();
>
>shm = _POSIX_Shm_Get_by_name( name, 0, _err );
> -  switch ( obj_err ) {
> -case OBJECTS_GET_BY_NAME_INVALID_NAME:
> -  err = ENOENT;
> -  break;
> -
> -case OBJECTS_GET_BY_NAME_NAME_TOO_LONG:
> -  err = ENAMETOOLONG;
> -  break;
> -
> -case OBJECTS_GET_BY_NAME_NO_OBJECT:
> -default:
> -  _Objects_Namespace_remove_string(
> -&_POSIX_Shm_Information,
> ->Object
> -  );
> -
> -  if ( shm->reference_count == 0 ) {
> -/* Only remove the shm object if no references exist to it. 
> Otherwise,
> - * the shm object will be freed later in _POSIX_Shm_Attempt_delete */
> -_POSIX_Shm_Free( shm );
> -  }
> -  break;
> +  if ( shm ) {
> +_Objects_Namespace_remove_string(
> +  &_POSIX_Shm_Information,
> +  >Object
> +);
> +
> +if ( shm->reference_count == 0 ) {
> +  /* Only remove the shm object if no references exist to it. Otherwise,
> +   * the shm object will be freed later in _POSIX_Shm_Attempt_delete */
> +  _POSIX_Shm_Free( shm );
> +}
> +  } else {
> +switch ( obj_err ) {
> +  case OBJECTS_GET_BY_NAME_NAME_TOO_LONG:
> +err = ENAMETOOLONG;
> +break;
> +
> +  case OBJECTS_GET_BY_NAME_INVALID_NAME:
> +  case OBJECTS_GET_BY_NAME_NO_OBJECT:
> +  default:
> +err = ENOENT;
> +break;
> +}
>}
>
>_Objects_Allocator_unlock();
> --
> 2.20.1
>
> ___
> devel

[PATCH v1] posix: Only check shm_unlink obj_err if necessary

[Kinsey Moore]

In the nominal case checked by spsysinit01, obj_err is unmodified if
_POSIX_Shm_Get_by_name returns non-NULL. In the case of shm_unlink, this means
an uninitialized value is passed into the switch and it appears tests using it
were passing by virtue of the stack having the right value on it in most cases.
This now checks obj_err only if _POSIX_Shm_Get_by_name returns NULL.

Close #4016
---
 cpukit/posix/src/shmunlink.c | 45 ++--
 1 file changed, 23 insertions(+), 22 deletions(-)

diff --git a/cpukit/posix/src/shmunlink.c b/cpukit/posix/src/shmunlink.c
index 053b9c4946..a889b4029c 100644
--- a/cpukit/posix/src/shmunlink.c
+++ b/cpukit/posix/src/shmunlink.c
@@ -29,28 +29,29 @@ int shm_unlink( const char *name )
   _Objects_Allocator_lock();
 
   shm = _POSIX_Shm_Get_by_name( name, 0, _err );
-  switch ( obj_err ) {
-case OBJECTS_GET_BY_NAME_INVALID_NAME:
-  err = ENOENT;
-  break;
-
-case OBJECTS_GET_BY_NAME_NAME_TOO_LONG:
-  err = ENAMETOOLONG;
-  break;
-
-case OBJECTS_GET_BY_NAME_NO_OBJECT:
-default:
-  _Objects_Namespace_remove_string(
-&_POSIX_Shm_Information,
->Object
-  );
-
-  if ( shm->reference_count == 0 ) {
-/* Only remove the shm object if no references exist to it. Otherwise,
- * the shm object will be freed later in _POSIX_Shm_Attempt_delete */
-_POSIX_Shm_Free( shm );
-  }
-  break;
+  if ( shm ) {
+_Objects_Namespace_remove_string(
+  &_POSIX_Shm_Information,
+  >Object
+);
+
+if ( shm->reference_count == 0 ) {
+  /* Only remove the shm object if no references exist to it. Otherwise,
+   * the shm object will be freed later in _POSIX_Shm_Attempt_delete */
+  _POSIX_Shm_Free( shm );
+}
+  } else {
+switch ( obj_err ) {
+  case OBJECTS_GET_BY_NAME_NAME_TOO_LONG:
+err = ENAMETOOLONG;
+break;
+
+  case OBJECTS_GET_BY_NAME_INVALID_NAME:
+  case OBJECTS_GET_BY_NAME_NO_OBJECT:
+  default:
+err = ENOENT;
+break;
+}
   }
 
   _Objects_Allocator_unlock();
-- 
2.20.1

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RE: [PATCH] posix: Only check shm_unlink obj_err if necessary

[Kinsey Moore]

Hey Gedare,
Setting obj_err to 0 would get the desired outcome, but the logic as it exists 
now is faulty. Setting obj_err to a value that can't be produced by 
_POSIX_Shm_Get_by_name would be a better option, but it would still be checking 
an error value after successful execution. _POSIX_Shm_Get_by_name relies on 
_Objects_Get_by_name internally which states about obj_err: The error 
indication in case of failure. If _POSIX_Shm_Get_by_name returns 
OBJECTS_GET_BY_NAME_NO_OBJECT (which it can), the current logic treats that as 
a success and operates on a NULL pointer.

-Original Message-
From: Gedare Bloom  
Sent: Thursday, June 25, 2020 16:49
To: Kinsey Moore 
Cc: devel@rtems.org
Subject: Re: [PATCH] posix: Only check shm_unlink obj_err if necessary

Hi Kinsey,

I missed seeing this. Two quick questions for you.

1. does it also work to initialize obj_err to 0? that would be simpler code.

2. I see the error handling logic changes slightly, with 
OBJECTS_GET_BY_NAME_NO_OBJECT now returning ENOENT. I guess if it works to init 
obj_err to 0, this case should be merged back to the 
OBJECTS_GET_BY_NAME_INVALID_NAME case?

On Thu, Jun 25, 2020 at 2:21 PM Kinsey Moore  wrote:
>
> Is there anything stopping this from being merged? I just ran into this bug 
> again on the current project I'm working on.
>
> Kinsey
>
> -Original Message-
> From: Kinsey Moore 
> Sent: Tuesday, January 28, 2020 12:37
> To: devel@rtems.org
> Cc: Kinsey Moore 
> Subject: [PATCH] posix: Only check shm_unlink obj_err if necessary
>
> In the nominal case checked by spsysinit01, obj_err is unmodified if 
> _POSIX_Shm_Get_by_name returns non-NULL. In the case of shm_unlink, this 
> means an uninitialized value is passed into the switch and it appears this 
> test was passing by virtue of the stack having the right value on it in most 
> cases. This now checks obj_err only if _POSIX_Shm_Get_by_name returns NULL.
> ---
>  cpukit/posix/src/shmunlink.c | 45 
> ++--
>  1 file changed, 23 insertions(+), 22 deletions(-)
>
> diff --git a/cpukit/posix/src/shmunlink.c 
> b/cpukit/posix/src/shmunlink.c index 00d743ac80..39c2ba0d87 100644
> --- a/cpukit/posix/src/shmunlink.c
> +++ b/cpukit/posix/src/shmunlink.c
> @@ -29,28 +29,29 @@ int shm_unlink( const char *name )
>_Objects_Allocator_lock();
>
>shm = _POSIX_Shm_Get_by_name( name, 0, _err );
> -  switch ( obj_err ) {
> -case OBJECTS_GET_BY_NAME_INVALID_NAME:
> -  err = ENOENT;
> -  break;
> -
> -case OBJECTS_GET_BY_NAME_NAME_TOO_LONG:
> -  err = ENAMETOOLONG;
> -  break;
> -
> -case OBJECTS_GET_BY_NAME_NO_OBJECT:
> -default:
> -  _Objects_Namespace_remove_string(
> -&_POSIX_Shm_Information,
> ->Object
> -  );
> -
> -  if ( shm->reference_count == 0 ) {
> -/* Only remove the shm object if no references exist to it. 
> Otherwise,
> - * the shm object will be freed later in _POSIX_Shm_Attempt_delete */
> -_POSIX_Shm_Free( shm );
> -  }
> -  break;
> +  if ( shm ) {
> +_Objects_Namespace_remove_string(
> +  &_POSIX_Shm_Information,
> +  >Object
> +);
> +
> +if ( shm->reference_count == 0 ) {
> +  /* Only remove the shm object if no references exist to it. Otherwise,
> +   * the shm object will be freed later in _POSIX_Shm_Attempt_delete */
> +  _POSIX_Shm_Free( shm );
> +}
> +  } else {
> +switch ( obj_err ) {
> +  case OBJECTS_GET_BY_NAME_NAME_TOO_LONG:
> +err = ENAMETOOLONG;
> +break;
> +
> +  case OBJECTS_GET_BY_NAME_INVALID_NAME:
> +  case OBJECTS_GET_BY_NAME_NO_OBJECT:
> +  default:
> +err = ENOENT;
> +break;
> +}
>}
>
>_Objects_Allocator_unlock();
> --
> 2.20.1
>
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RE: [PATCH] posix: Only check shm_unlink obj_err if necessary

[Kinsey Moore]

Is there anything stopping this from being merged? I just ran into this bug 
again on the current project I'm working on.

Kinsey

-Original Message-
From: Kinsey Moore  
Sent: Tuesday, January 28, 2020 12:37
To: devel@rtems.org
Cc: Kinsey Moore 
Subject: [PATCH] posix: Only check shm_unlink obj_err if necessary

In the nominal case checked by spsysinit01, obj_err is unmodified if 
_POSIX_Shm_Get_by_name returns non-NULL. In the case of shm_unlink, this means 
an uninitialized value is passed into the switch and it appears this test was 
passing by virtue of the stack having the right value on it in most cases. This 
now checks obj_err only if _POSIX_Shm_Get_by_name returns NULL.
---
 cpukit/posix/src/shmunlink.c | 45 ++--
 1 file changed, 23 insertions(+), 22 deletions(-)

diff --git a/cpukit/posix/src/shmunlink.c b/cpukit/posix/src/shmunlink.c index 
00d743ac80..39c2ba0d87 100644
--- a/cpukit/posix/src/shmunlink.c
+++ b/cpukit/posix/src/shmunlink.c
@@ -29,28 +29,29 @@ int shm_unlink( const char *name )
   _Objects_Allocator_lock();
 
   shm = _POSIX_Shm_Get_by_name( name, 0, _err );
-  switch ( obj_err ) {
-case OBJECTS_GET_BY_NAME_INVALID_NAME:
-  err = ENOENT;
-  break;
-
-case OBJECTS_GET_BY_NAME_NAME_TOO_LONG:
-  err = ENAMETOOLONG;
-  break;
-
-case OBJECTS_GET_BY_NAME_NO_OBJECT:
-default:
-  _Objects_Namespace_remove_string(
-&_POSIX_Shm_Information,
->Object
-  );
-
-  if ( shm->reference_count == 0 ) {
-/* Only remove the shm object if no references exist to it. Otherwise,
- * the shm object will be freed later in _POSIX_Shm_Attempt_delete */
-_POSIX_Shm_Free( shm );
-  }
-  break;
+  if ( shm ) {
+_Objects_Namespace_remove_string(
+  &_POSIX_Shm_Information,
+  >Object
+);
+
+if ( shm->reference_count == 0 ) {
+  /* Only remove the shm object if no references exist to it. Otherwise,
+   * the shm object will be freed later in _POSIX_Shm_Attempt_delete */
+  _POSIX_Shm_Free( shm );
+}
+  } else {
+switch ( obj_err ) {
+  case OBJECTS_GET_BY_NAME_NAME_TOO_LONG:
+err = ENAMETOOLONG;
+break;
+
+  case OBJECTS_GET_BY_NAME_INVALID_NAME:
+  case OBJECTS_GET_BY_NAME_NO_OBJECT:
+  default:
+err = ENOENT;
+break;
+}
   }
 
   _Objects_Allocator_unlock();
--
2.20.1

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[PATCH] posix: Only check shm_unlink obj_err if necessary

[Kinsey Moore]

In the nominal case checked by spsysinit01, obj_err is unmodified if
_POSIX_Shm_Get_by_name returns non-NULL. In the case of shm_unlink, this
means an uninitialized value is passed into the switch and it appears
this test was passing by virtue of the stack having the right value on
it in most cases. This now checks obj_err only if _POSIX_Shm_Get_by_name
returns NULL.
---
 cpukit/posix/src/shmunlink.c | 45 ++--
 1 file changed, 23 insertions(+), 22 deletions(-)

diff --git a/cpukit/posix/src/shmunlink.c b/cpukit/posix/src/shmunlink.c
index 00d743ac80..39c2ba0d87 100644
--- a/cpukit/posix/src/shmunlink.c
+++ b/cpukit/posix/src/shmunlink.c
@@ -29,28 +29,29 @@ int shm_unlink( const char *name )
   _Objects_Allocator_lock();
 
   shm = _POSIX_Shm_Get_by_name( name, 0, _err );
-  switch ( obj_err ) {
-case OBJECTS_GET_BY_NAME_INVALID_NAME:
-  err = ENOENT;
-  break;
-
-case OBJECTS_GET_BY_NAME_NAME_TOO_LONG:
-  err = ENAMETOOLONG;
-  break;
-
-case OBJECTS_GET_BY_NAME_NO_OBJECT:
-default:
-  _Objects_Namespace_remove_string(
-&_POSIX_Shm_Information,
->Object
-  );
-
-  if ( shm->reference_count == 0 ) {
-/* Only remove the shm object if no references exist to it. Otherwise,
- * the shm object will be freed later in _POSIX_Shm_Attempt_delete */
-_POSIX_Shm_Free( shm );
-  }
-  break;
+  if ( shm ) {
+_Objects_Namespace_remove_string(
+  &_POSIX_Shm_Information,
+  >Object
+);
+
+if ( shm->reference_count == 0 ) {
+  /* Only remove the shm object if no references exist to it. Otherwise,
+   * the shm object will be freed later in _POSIX_Shm_Attempt_delete */
+  _POSIX_Shm_Free( shm );
+}
+  } else {
+switch ( obj_err ) {
+  case OBJECTS_GET_BY_NAME_NAME_TOO_LONG:
+err = ENAMETOOLONG;
+break;
+
+  case OBJECTS_GET_BY_NAME_INVALID_NAME:
+  case OBJECTS_GET_BY_NAME_NO_OBJECT:
+  default:
+err = ENOENT;
+break;
+}
   }
 
   _Objects_Allocator_unlock();
-- 
2.20.1

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RE: [PATCH] bsps/arm: Update GICv3 to use newer affinity interface

[Kinsey Moore]

This patch looks good to me.

Kinsey Moore

> -Original Message-
> From: Jeff Kubascik 
> Sent: Thursday, January 23, 2020 08:49
> To: devel@rtems.org
> Cc: Kinsey Moore ; Joel Sherrill
> 
> Subject: [PATCH] bsps/arm: Update GICv3 to use newer affinity interface
> 
> The GICv3 implementation uses the GICD_ITARGETSR register to configure
> interrupt affinity. The GIC uses this register only when affinity routing is 
> disabled,
> which is called legacy operation mode. However, affinity routing is being
> enabled, by setting the ARE_NS bit in the GICD_CTLR register; therefore
> GICD_ITARGETSR will be ignored.
> 
> While affinity routing could be disabled, this legacy operation mode is 
> optional
> for a GIC implementation - it should be avoided.
> 
> This change uses the newer affinity register GICD_IROUTER. The register is 64
> bits wide, so any access would need to be performed with two store operations
> on a 32 bit RTEMS build. This had to be done with assembly code, as the
> compiler optimizer will try to use the 64 bit floating point store operation 
> VSTM
> to write to the register. This does not work with virtual GICD registers on 
> the
> Xen hypervisor, as the VSTM instruction data abort does not provide syndrome
> information.
> 
> Affinity routing allows for hierarchical routing of interrupts. To take 
> advantage
> of this feature, it would require an understanding of the processor/core
> hierarchy. RTEMS specifies the desired processor affinity with a mask, which
> does not provide this information. For now, assume a simple single level 
> routing
> hierarchy.
> 
> Signed-off-by: Jeff Kubascik 
> ---
>  bsps/arm/include/bsp/arm-gic-regs.h | 15 +++
>  bsps/arm/shared/irq/irq-gicv3.c | 26 +++---
>  2 files changed, 38 insertions(+), 3 deletions(-)
> 
> diff --git a/bsps/arm/include/bsp/arm-gic-regs.h b/bsps/arm/include/bsp/arm-
> gic-regs.h
> index 8a65294b6f..13b715a3b1 100644
> --- a/bsps/arm/include/bsp/arm-gic-regs.h
> +++ b/bsps/arm/include/bsp/arm-gic-regs.h
> @@ -151,6 +151,21 @@ typedef struct {
>  #define GIC_DIST_ICDSGIR_SGIINTID(val) BSP_FLD32(val, 0, 3)  #define
> GIC_DIST_ICDSGIR_SGIINTID_GET(reg) BSP_FLD32GET(reg, 0, 3)  #define
> GIC_DIST_ICDSGIR_SGIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
> +  uint32_t reserved_f04[5247];
> +  uint64_t icdirr[988];
> +#define GIC_DIST_ICDIRR_AFF3(val) BSP_FLD64(val, 32, 39) #define
> +GIC_DIST_ICDIRR_AFF3_GET(reg) BSP_FLD64GET(val, 32, 39) #define
> +GIC_DIST_ICDIRR_AFF3_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)
> +#define GIC_DIST_ICDIRR_INTERRUPT_ROUTING_MODE BSP_BIT64(31)
> #define
> +GIC_DIST_ICDIRR_AFF2(val) BSP_FLD64(val, 16, 23) #define
> +GIC_DIST_ICDIRR_AFF2_GET(reg) BSP_FLD64GET(val, 16, 23) #define
> +GIC_DIST_ICDIRR_AFF2_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)
> +#define GIC_DIST_ICDIRR_AFF1(val) BSP_FLD64(val, 8, 15) #define
> +GIC_DIST_ICDIRR_AFF1_GET(reg) BSP_FLD64GET(val, 8, 15) #define
> +GIC_DIST_ICDIRR_AFF1_SET(reg, val) BSP_FLD64SET(reg, val, 8, 15)
> +#define GIC_DIST_ICDIRR_AFF0(val) BSP_FLD64(val, 0, 7) #define
> +GIC_DIST_ICDIRR_AFF0_GET(reg) BSP_FLD64GET(val, 0, 7) #define
> +GIC_DIST_ICDIRR_AFF0_SET(reg, val) BSP_FLD64SET(reg, val, 0, 7)
>  } gic_dist;
> 
>  /* GICv3 only */
> diff --git a/bsps/arm/shared/irq/irq-gicv3.c b/bsps/arm/shared/irq/irq-gicv3.c
> index 138b565b9b..1b127fb4a1 100644
> --- a/bsps/arm/shared/irq/irq-gicv3.c
> +++ b/bsps/arm/shared/irq/irq-gicv3.c
> @@ -107,6 +107,12 @@
>  #define WRITE64_SR(SR_NAME, VALUE) \
>  __asm__ volatile("mcrr" SR_NAME "  \n" : : "r" (VALUE) );
> 
> +#define WRITE64_REG(ADDR, VALUE) \
> +({ \
> +  __asm__ volatile("str %0, [%1, #0]"::"r"(VALUE), "r"(ADDR)); \
> +  __asm__ volatile("str %0, [%1, #4]"::"r"(VALUE >> 32), "r"(ADDR)); \
> +})
> +
>  #define ARM_GIC_REDIST ((volatile gic_redist *) BSP_ARM_GIC_REDIST_BASE)
> #define ARM_GIC_SGI_PPI (((volatile gic_sgi_ppi *)
> ((char*)BSP_ARM_GIC_REDIST_BASE + (1 << 16
> 
> @@ -166,6 +172,16 @@ static inline uint32_t get_id_count(volatile gic_dist
> *dist)
>return id_count;
>  }
> 
> +static uint64_t cpu_to_affinity(uint32_t cpu) {
> +  /* CPU logical mapping is not present - keep it simple with a single level
> + routing hierarchy */
> +  return (GIC_DIST_ICDIRR_AFF3(0) |
> +  GIC_DIST_ICDIRR_AFF2(0) |
> +  GIC_DIST_ICDIRR_AFF1(0) |
> +  GIC_DIST_ICDIRR_AFF0(cpu));
> +}
> +
>  static void init_cpu_interface(void)
>  {
>uint32_t sre_value = 0x7;
> @@ -222,7 +238,7 @@ rtems_status_code bsp_inte

RE: [PATCH] bsps/arm/shared: Add GICv3 implementation

[Kinsey Moore]

Hi,
These changes look good. As you said, we want to avoid operating in legacy mode 
since it's optional and hardware isn't guaranteed to support it. The R52 cores 
I used to implement and test GICv3 support omitted legacy functionality and I 
expect most newer cores to do so as well. I suspect that the GICv3 driver will 
continue operating normally with these changes and I'll test them out as soon 
as I see the patch.

Kinsey

> -Original Message-
> From: Jeff Kubascik 
> Sent: Monday, January 20, 2020 10:59
> To: j...@rtems.org
> Cc: rtems-de...@rtems.org ; Kinsey Moore
> 
> Subject: Re: [PATCH] bsps/arm/shared: Add GICv3 implementation
> 
> Hello,
> 
> My integration work with Xen has identified one potential issue with the gicv3
> driver implementation - see comments below.
> 
> On 1/17/2020 5:20 PM, Joel Sherrill wrote:
> > On Fri, Jan 17, 2020 at 1:24 PM Jeff Kubascik
> > mailto:jeff.kubas...@dornerworks.com>>
> wrote:
> >
> > Hello,
> >
> > Have there been any updates on this patch? I do not see it in mainline.
> >
> >
> > I was hoping someone would comment. :)
> >
> >
> >
> > I am currently using it for work on the arm/xen BSP to add support for
> platforms
> > with a GICv3 interrupt controller. With a few minor changes, I have 
> > confirm
> that
> > it works with the Xen hypervisor on qemu. Before I can submit these
> patches,
> > though, this patch would need to be accepted first.
> >
> >
> > Thank you for using it and reporting back. I just pushed it and look
> > forward to your patch.
> >
> > CC'ing Kinsey so he is on the lookout for your patch and verifies it
> > still works on HPSC Qemu.
> >
> > --joel
> >
> >
> > On 8/16/2019 3:14 PM, Kinsey Moore wrote:
> > > This adds support for the GICv3 interrupt controller along with the
> > > redistributor to control SGIs and PPIs which wasn't present in GICv2
> > > implementations. GICv3 implementations only optionally support
> > > memory-mapped GICC interface interaction and require system register
> > > access be implemented, so the GICC interface is accessed only
> > > through system registers.
> > > ---
> > >  bsps/arm/include/bsp/arm-gic-irq.h  |  15 +-
> > >  bsps/arm/include/bsp/arm-gic-regs.h |  76 -
> > >  bsps/arm/shared/irq/irq-gic.c       |  16 ++
> > >  bsps/arm/shared/irq/irq-gicv3.c     | 329
> > 
> > >  4 files changed, 427 insertions(+), 9 deletions(-)
> > >  create mode 100644 bsps/arm/shared/irq/irq-gicv3.c
> > >
> > > diff --git a/bsps/arm/include/bsp/arm-gic-irq.h
> > b/bsps/arm/include/bsp/arm-gic-irq.h
> > > index b3e893de72..219c3c7189 100644
> > > --- a/bsps/arm/include/bsp/arm-gic-irq.h
> > > +++ b/bsps/arm/include/bsp/arm-gic-irq.h
> > > @@ -85,6 +85,12 @@ typedef enum {
> > >    ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF
> > >  } arm_gic_irq_software_irq_target_filter;
> > >
> > > +void arm_gic_trigger_sgi(
> > > +  rtems_vector_number vector,
> > > +  arm_gic_irq_software_irq_target_filter filter,
> > > +  uint8_t targets
> > > +);
> > > +
> > >  static inline rtems_status_code arm_gic_irq_generate_software_irq(
> > >    rtems_vector_number vector,
> > >    arm_gic_irq_software_irq_target_filter filter,
> > > @@ -94,14 +100,7 @@ static inline rtems_status_code
> > arm_gic_irq_generate_software_irq(
> > >    rtems_status_code sc = RTEMS_SUCCESSFUL;
> > >
> > >    if (vector <= ARM_GIC_IRQ_SGI_15) {
> > > -    volatile gic_dist *dist = ARM_GIC_DIST;
> > > -
> > > -    dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter)
> > > -      | GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets)
> > > -#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
> > > -      | GIC_DIST_ICDSGIR_NSATT
> > > -#endif
> > > -      | GIC_DIST_ICDSGIR_SGIINTID(vector);
> > > +    arm_gic_trigger_sgi(vector, filter, targets);
> > >    } else {
> > >      sc = RTEMS_INVALID_ID;
> > >    }
> > > diff --git a/bsps/arm/include/bsp/arm-gic-regs.h
> > b/bsps/arm/include/bsp/arm-gic-regs.h
> > > index 2915313b71..8a65294b6f 100644
> > > --- a/bsps/arm/include/bsp/arm-gic-regs.h
> >

[PATCH] Fix exception when no output format is specified

[Kinsey Moore]

The JSON log generation patch introduced a bug when the report output
generation was not configured due to attempting to iterate over 'None'.
---
 tester/rt/test.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tester/rt/test.py b/tester/rt/test.py
index d5c7c66..d258b11 100644
--- a/tester/rt/test.py
+++ b/tester/rt/test.py
@@ -345,6 +345,8 @@ def run(args, command_path = None):
 raise error.general('invalid RTEMS report formats option')
 report_formats = report_formats[1].split(',')
 check_report_formats(report_formats, report_location)
+else:
+report_formats = []
 log.notice('RTEMS Testing - Tester, %s' % (version.string()))
 if opts.find_arg('--list-bsps'):
 bsps.list(opts)
-- 
2.11.0

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RE: rtems-tester initial port getting "'NoneType' object is not iterable"

[Kinsey Moore]

> -Original Message-
> From: devel  On Behalf Of dufa...@hda.com
> Sent: Saturday, September 21, 2019 08:48
> To: Joel Sherrill 
> Cc: rtems-de...@rtems.org 
> Subject: Re: rtems-tester initial port getting "'NoneType' object is not 
> iterable"
> 
> 
> 
> > On Sep 20, 2019, at 21:43 , Joel Sherrill  wrote:
> >
> >
> >
> > On Fri, Sep 20, 2019, 8:21 PM Chris Johns  wrote:
> > On 21/9/19 5:56 am, dufa...@hda.com wrote:
> > > One thing I should have said is that “rtems" and "rtems-tester" are the
> master branches, "rtems-tester" is updated as of yesterday, and “rtems” is
> recent.
> >
> > Thanks.
> >
> > >
> > >> On Sep 20, 2019, at 15:46 , Peter Dufault  wrote:
> > >>
> > >> I’m bringing up the rtems-tester for the PowerPC “beatnik” bsp.  I’m
> impressed with how easy it is to implement (well done, Chris).
> >
> > Thanks, it is good to get this type of feedback and things are just working.
> >
> > > But after doing all the easy work, and just as I thought my initial run 
> > > of the
> “samples" was about to exit successfully, the script faulted and gave me the
> error "TypeError: 'NoneType' object is not iterable”.  I’ve pasted the output 
> of
> my run below.
> >
> > OK.
> >
> > >> Average test time: 0:00:40.583694
> >
> > Does this target take a bit of time to boot?
> 
> There’s at least 16 seconds overhead - 2 seconds in the power off / on, about 
> 7
> seconds before the MOTLOAD monitor visibly starts (probably testing), and a 7
> second delay (that I now see I can change, I’ll lower it to 1) where it is 
> letting
> you hit  to skip the auto-boot.
> 
> >
> > >> Testing time : 0:09:28.171711
> > >> Traceback (most recent call last):
> > >>  File "../rtems-tools/tester/rt/cmd-test.py", line 42, in 
> > >>test.run(sys.argv[1:], command_path = base)  File
> > >> "/home/dufault/development/rtems/rtems-tools/tester/rt/test.py", line
> 455, in run
> > >>for report_format in report_formats:
> > >> TypeError: 'NoneType' object is not iterable
> >
> > This is from Kinsey patch where report formats was added
> >
> > https://git.rtems.org/rtems-tools/commit/?id=5fcaf843bdb491e2da14dc1af
> > 61806ac6d20bae5
> >
> >
> > Joel?
> >
> > Sorry I was traveling home today. I have good news to pass along later.
> >
> > I will get Kinsey to look at this. Peter can you email us the configuration 
> > file?
> 
> Here’s the global “.ini” file, 
> rtems-tools/tester/rtems/testing/bsps/beatnik.ini.  I
> notice I should change the reset expressikno to be any error status ("^Error
> Status: " is enough to indicate a problem).
> 
> #
> # This is for the MVME5500 PowerPC VME board running the "beatnik" BSP.
> # - The console is connected to a telnet tty device.
> # - The system is running MOTLoad RTOS Version 2.0,  PAL Version 2.5 RM01 # -
> The system is connected to ethernet and is booted via TFTP.
> #
> [beatnik]
> bsp= beatnik
> arch   = powerpc
> tester = %{_rtscripts}/tftp.cfg
> jobs   = 1
> test_restarts  = 3
> target_reset_regex = ^Error Status: 0081 target_start_regex =
> ^MVME5500>
> requires   = target_on_command, target_off_command,
> target_reset_command, bsp_tty_dev
> 
> Here’s my site “.ini” file.
> - beatnik-mkbin is a shell script that does this: "powerpc-rtems5-objcopy -
> Obinary ${from} ${to}” to create a “.bin” from a “.exe”;
> - power-ctl is a shell script that manipulates a network power switch;
> - The console runs at 9600 baud and uses a raspberry PI named “swlab-term”
> running ser2net at port 2000.
> 
> [beatnik]
> tftp_port  = 3822
> bsp_tty_dev= swlab-term:2000
> target_pretest_command = ./beatnik-mkbin @EXE@
> target_exe_filter  = /\.exe/.bin/
> target_on_command  = ./power-ctl 1 off-on
> target_off_command = ./power-ctl 1 off
> target_reset_command   = ./power-ctl 1 off-on
> 
> Peter
> -
> Peter Dufault
> HD Associates, Inc.  Software and System Engineering


This bug appears to have snuck in when I refactored the patch for the future 
handling of multiple report types. I'll have a patch up shortly.

Kinsey
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[PATCH] Update docs for log mode change and JSON reporting

[Kinsey Moore]

The option --report-mode has been changed to --log-mode to reduce ambiguity
and --report-format has been added along with --report-path for machine
readable test reporting.
---
 user/tools/tester.rst | 29 +
 1 file changed, 21 insertions(+), 8 deletions(-)

diff --git a/user/tools/tester.rst b/user/tools/tester.rst
index 9fb50c7..609384b 100644
--- a/user/tools/tester.rst
+++ b/user/tools/tester.rst
@@ -251,7 +251,7 @@ timeouts and 1 invalid test.
 * ``sparc/erc32`` is the architecture and BSP names.
 * ``hello.exe`` is the executable name.
 
-The test log records all the tests and results. The reporting mode by default
+The test log records all the tests and results. The logging mode by default
 only provides the output history if a test fails, times out, or is invalid. The
 time taken by each test is also recorded.
 
@@ -317,16 +317,16 @@ If no start marker is seen the test is marked as invalid. 
If you are testing on
 real target hardware things can sometimes go wrong and the target may not
 initialize or respond to the debugger in an expected way.
 
-Reporting
--
+Logging
+---
 
-The report written to the log has the following modes:
+The following modes of logging are available:
 
 * All (``all``)
 * Failures (``failures``)
 * None (``none``)
 
-The mode is controlled using the command line option ``--report-mode`` using
+The mode is controlled using the command line option ``--log-mode`` using
 the values listed above.
 
 All
@@ -410,6 +410,17 @@ running on a Coldfire MCF5235 using GDB and a BDM pod:
 * Line starting with ``]`` are from the target's console.
 * The result with the test time.
 
+Reporting
+-
+
+The RTEMS Tester supports output in a machine parsable format. This can be
+enabled using the options "--report-path" and "--report-format". Currently,
+JSON output is supported using these options like so:
+'--report-path="report" --report-format=json'
+
+This will produce a file "report.json" that contains output equivalent to the
+"failure" logging mode.
+
 Running Tests in Parallel
 -
 
@@ -419,8 +430,8 @@ resource contention. Simulators are an example of back-ends 
that can run in
 parallel. A hardware debug tool like a BDM or JTAG pod can manage only a
 single test at once so the tests need to be run one at a time.
 
-The test framework manages the test jobs and orders the output in the report
-log in test order. Output is held for completed tests until the next test to be
+The test framework manages the test jobs and orders the output in the log
+in test order. Output is held for completed tests until the next test to be
 reported has finished.
 
 Command Line Help
@@ -444,7 +455,9 @@ review the available option by the ``--help`` option:
 --macros file[,file] : Macro format files to load after the 
defaults
 --no-clean   : Do not clean up the build tree
 --quiet  : Quiet output (not used)
---report-mode: Reporting modes, failures (default),all,none
+--report-path: Report output base path (file extension 
will be added)
+--report-format  : Formats in which to report test results: 
json
+--log-mode   : Log modes, failures (default),all,none
 --rtems-bsp  : The RTEMS BSP to run the test on
 --rtems-tools: The path to the RTEMS tools
 --target : Set the target triplet
-- 
2.20.1

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[PATCH v3] Add JSON log generation

[Kinsey Moore]

Add log formatter hooks and JSON log formatter to the test infrastructure
for consumption by automated processes or report generators.
---
 tester/rt/test.py | 124 --
 1 file changed, 111 insertions(+), 13 deletions(-)

diff --git a/tester/rt/test.py b/tester/rt/test.py
index da0a11e..d5c7c66 100644
--- a/tester/rt/test.py
+++ b/tester/rt/test.py
@@ -178,7 +178,7 @@ def find_executables(paths, glob):
 executables = [e for e in executables if not norun.match(e)]
 return sorted(executables)
 
-def report_finished(reports, report_mode, reporting, finished, job_trace):
+def report_finished(reports, log_mode, reporting, finished, job_trace):
 processing = True
 while processing:
 processing = False
@@ -192,7 +192,7 @@ def report_finished(reports, report_mode, reporting, 
finished, job_trace):
 'reporting',
 reporting))
 processing = True
-reports.log(tst.executable, report_mode)
+reports.log(tst.executable, log_mode)
 reported += [tst]
 reporting += 1
 finished[:] = [t for t in finished if t not in reported]
@@ -217,6 +217,88 @@ def killall(tests):
 for test in tests:
 test.kill()
 
+
+def generate_json_report(args, reports, start_time, end_time,
+ total, json_file):
+import json
+import sys
+json_log = {}
+json_log['Command Line'] = " ".join(args)
+json_log['Python'] = sys.version.replace('\n', '')
+json_log['test_groups'] = []
+json_log['Host'] = host.label(mode='all')
+json_log['summary'] = {}
+json_log['summary']['passed_count'] = reports.passed
+json_log['summary']['failed_count'] = reports.failed
+json_log['summary']['user-input_count'] = reports.user_input
+json_log['summary']['expected-fail_count'] = reports.expected_fail
+json_log['summary']['indeterminate_count'] = reports.indeterminate
+json_log['summary']['benchmark_count'] = reports.benchmark
+json_log['summary']['timeout_count'] = reports.timeouts
+json_log['summary']['invalid_count'] = reports.invalids
+json_log['summary']['wrong-version_count'] = reports.wrong_version
+json_log['summary']['wrong-build_count'] = reports.wrong_build
+json_log['summary']['wrong-tools_count'] = reports.wrong_tools
+json_log['summary']['total_count'] = reports.total
+time_delta = end_time - start_time
+json_log['summary']['average_test_time'] = str(time_delta / total)
+json_log['summary']['testing_time'] = str(time_delta)
+
+result_types = [
+'failed', 'user-input', 'expected-fail', 'indeterminate',
+'benchmark', 'timeout', 'invalid', 'wrong-version', 'wrong-build',
+'wrong-tools'
+]
+json_results = {}
+for result_type in result_types:
+json_log['summary'][result_type] = []
+
+# collate results for JSON log
+for name in reports.results:
+result_type = reports.results[name]['result']
+test_parts = name.split("/")
+test_category = test_parts[-2]
+test_name = test_parts[-1]
+if result_type != 'passed':
+json_log['summary'][result_type].append(test_name)
+if test_category not in json_results:
+json_results[test_category] = []
+json_result = {}
+# remove the file extension
+json_result["name"] = test_name.split('.')[0]
+json_result["result"] = result_type
+if result_type == "failed" or result_type == "timeout":
+json_result["output"] = reports.results[name]["output"]
+json_results[test_category].append(json_result)
+
+# convert results to a better format for report generation
+sorted_keys = sorted(json_results.keys())
+for i in range(len(sorted_keys)):
+results_log = {}
+results_log["index"] = i + 1
+results_log["name"] = sorted_keys[i]
+results_log["results"] = json_results[sorted_keys[i]]
+json_log["test_groups"].append(results_log)
+
+# write out JSON log
+with open(json_file, 'w') as outfile:
+json.dump(json_log, outfile, sort_keys=True, indent=4)
+
+
+report_formatters = {
+'json': generate_json_report
+}
+
+
+def check_report_formats(report_formats, report_location):
+if report_location is None:
+raise error.general('report base path missing')
+for report_format in report_formats:
+if report_format not in report_formatters:
+raise error.general('invalid RTEMS report formatter: %s'
+% report_format)
+
+
 def run(args, command_path = None):
 import sys
 tests = []
@@ -227,7 +309,9 @@ def run(args, command_path = None):
 optargs = { '--rtems-tools':'The path to the RTEMS tools',
 '--rtems-bsp':