Re: [PATCH] ARM64: ZynqMP: DT: Fix GIC's 'reg' property
Hi,
On 15.12.2015 10:14, Sören Brinkmann wrote:
> On Mon, 2015-12-14 at 05:01PM +, Marc Zyngier wrote:
>> Mark,
>>
>> On 14/12/15 16:46, Mark Rutland wrote:
>>> On Mon, Dec 14, 2015 at 08:31:40AM -0800, Soren Brinkmann wrote:
Signed-off-by: Soren Brinkmann
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 857eda5c7217..b5d1facadf16 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -80,10 +80,10 @@
gic: interrupt-controller@f901 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";
#interrupt-cells = <3>;
- reg = <0x0 0xf901 0x1>,
-<0x0 0xf902f000 0x2000>,
+ reg = <0x0 0xf901 0x1000>,
+<0x0 0xf902 0x2>,
<0x0 0xf904 0x2>,
-<0x0 0xf906f000 0x2000>;
+<0x0 0xf906 0x2>;
>>>
>>> I'm confused. These sizes don't look right for GIC-400. Is this a custom
>>> GIC?
>>
>> Probably an implementation that obey the SBSA requirement of aliasing
>> the first 4kB of the CPU interface on a 64kB page, and the second one on
>> the following 64kB page. See the APM system for an example of such a
>> thing. I'm more concerned about the GICH region (3rd one), which has no
>> reason to be bigger than 4kB.
>
> Xilinx didn't publish the memory map yet (at least I didn't see it in the
> public docs), so, let me give some excerpts:
>
> GICD:
> GICD_CTLR 0xF901 32 rw 0x Distributor
> Control Register
> ...
> GICD_CIDR30xF9010FFC 32 ro 0x00B1 Component ID3
> Register
>
> GICC:
> GICC_CTLR 0xF902 32 rw 0x CPU Interface
> Control Register
> ...
> GICC_DIR 0xF903 32 wo x Deactivate Interrupt
> Register
>
> GICH:
> GICH_HCR 0xF904 32 rw 0x Hypervisor
> Control Register
> ...
> GICH_LR3_Alias7 0xF9050F0C 32 rw 0x List
> Register 3
>
> GICV:
> GICV_CTLR 0xF906 32 rw 0x Virtual Machine
> Control Register
> ...
> GICV_DIR 0xF907 32 wo x VM Deactivate Interrupt
> Register
>
>
> Regarding the GICH area, it looks like it starts at 0xF904 and the
> alias blocks to access the other processor interfaces start at
> 0xF905.
>
>>
>>> Did this ever work wit hteh old offsets and sizes?
>>
>> It probably dies when trying to use EOImode==1.
>
> Without knowing what parts we really exercise, yes, the system comes up
> fine so far, but I recently found Linux boot hanging on QEMU and it
> seemed to be related to time not progressing (fast enough).
> I found a different DT using the values proposed here and that fixed the
> hang for me.
We have discussed this here before with Rob
https://lkml.org/lkml/2015/2/24/371
Not sure if there is any fix. It is probably just broken QEMU not DTS
description in mainline.
Thanks,
Michal
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Re: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller
On 10.12.2015 18:25, Bjorn Helgaas wrote: > On Thu, Dec 10, 2015 at 08:02:05AM +0100, Michal Simek wrote: >> Hi Bjorn, >> >> On 10.12.2015 00:19, Bjorn Helgaas wrote: >>> [+cc Michal, Paul, Thierry, Stephen, Alexandre (see irq_dispose_mapping >>> questions below)] >>> >>> On Sun, Nov 29, 2015 at 05:33:53PM +0530, Bharat Kumar Gogada wrote: >>>> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP. >>>> >>>> Signed-off-by: Bharat Kumar Gogada >>>> Signed-off-by: Ravi Kiran Gummaluri >>>> Acked-by: Rob Herring >>> >>> This needs either a MAINTAINERS update or an ack from Michal (whose >>> MAINTAINERS entry matches anything containing "xilinx"). >> >> We have done it in this way because driver owners are changing time to >> time and my entry cover it that I can pass it to appropriate person who >> is responsible for it. >> >> For this Maintainers part here is my: >> Acked-by: Michal Simek > > Thanks. > > For things under drivers/pci/host, I ask for an ack from the > individual maintainer before applying patches. As-is (without a > MAINTAINERS update) I'll be looking for acks from you, Michal, for all > future changes to pcie-xilinx-nwl.c. If you want something else, we > need a MAINTAINERS change. ok. No problem with it. I will get HW pretty soon and I will be able to do some testing my self when some others changes come. Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller
Hi Bjorn, On 10.12.2015 00:19, Bjorn Helgaas wrote: > [+cc Michal, Paul, Thierry, Stephen, Alexandre (see irq_dispose_mapping > questions below)] > > On Sun, Nov 29, 2015 at 05:33:53PM +0530, Bharat Kumar Gogada wrote: >> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP. >> >> Signed-off-by: Bharat Kumar Gogada >> Signed-off-by: Ravi Kiran Gummaluri >> Acked-by: Rob Herring > > This needs either a MAINTAINERS update or an ack from Michal (whose > MAINTAINERS entry matches anything containing "xilinx"). We have done it in this way because driver owners are changing time to time and my entry cover it that I can pass it to appropriate person who is responsible for it. For this Maintainers part here is my: Acked-by: Michal Simek Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] net/macb: bindings doc: Merge cdns-emac to macb
Merge two bindings for the same driver to together.
Signed-off-by: Michal Simek
---
Documentation/devicetree/bindings/net/cdns-emac.txt | 20
Documentation/devicetree/bindings/net/macb.txt | 3 +++
2 files changed, 3 insertions(+), 20 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/net/cdns-emac.txt
diff --git a/Documentation/devicetree/bindings/net/cdns-emac.txt
b/Documentation/devicetree/bindings/net/cdns-emac.txt
deleted file mode 100644
index 4451ee973223..
--- a/Documentation/devicetree/bindings/net/cdns-emac.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-* Cadence EMAC Ethernet controller
-
-Required properties:
-- compatible: Should be "cdns,[-]{emac}"
- Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
- Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
- Or the generic form: "cdns,emac".
-- reg: Address and length of the register set for the device
-- interrupts: Should contain macb interrupt
-- phy-mode: see ethernet.txt file in the same directory.
-
-Examples:
-
- macb0: ethernet@fffc4000 {
- compatible = "cdns,at91rm9200-emac";
- reg = <0xfffc4000 0x4000>;
- interrupts = <21>;
- phy-mode = "rmii";
- local-mac-address = [3a 0e 03 04 05 06];
- };
diff --git a/Documentation/devicetree/bindings/net/macb.txt
b/Documentation/devicetree/bindings/net/macb.txt
index b5d79761ac97..1361a6daf63f 100644
--- a/Documentation/devicetree/bindings/net/macb.txt
+++ b/Documentation/devicetree/bindings/net/macb.txt
@@ -2,6 +2,7 @@
Required properties:
- compatible: Should be "cdns,[-]{macb|gem}"
+ Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs or the 10/100Mbit IP
available on sama5d3 SoCs.
Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form:
"cdns,macb".
@@ -10,7 +11,9 @@ Required properties:
Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2
SoCs.
Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs.
Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4
SoCs.
+ Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
+ Or the generic form: "cdns,emac".
- reg: Address and length of the register set for the device
- interrupts: Should contain macb interrupt
- phy-mode: See ethernet.txt file in the same directory.
--
1.9.1
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Re: [PATCH] ARM: dt: zynq: Add labels to cpu nodes to allow overriding OPPs.
On 11/09/2015 07:55 PM, Sören Brinkmann wrote: > On Mon, 2015-11-09 at 10:51AM -0800, Moritz Fischer wrote: >> By adding labels to the cpu nodes in the dtsi, a dts that >> includes it can change the OPPs by referencing the cpu0 >> through the label. >> >> Signed-off-by: Moritz Fischer > Reviewed-by: Sören Brinkmann Applied to zynq/dt. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH] ARM: dts: zynq: describe SLCR as simple-mfd rather than simple-bus
On 11/05/2015 09:46 AM, Masahiro Yamada wrote:
> The SLCR (System-Level Control Registers) block is an MFD (Multi
> Function Device) rather than a bus.
>
> "simple-mfd" seems a more suitable compatible string than "simple-bus".
>
> Signed-off-by: Masahiro Yamada
> ---
>
> arch/arm/boot/dts/zynq-7000.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
> b/arch/arm/boot/dts/zynq-7000.dtsi
> index 1a5220e..64ddd4d 100644
> --- a/arch/arm/boot/dts/zynq-7000.dtsi
> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
> @@ -238,7 +238,7 @@
> slcr: slcr@f800 {
> #address-cells = <1>;
> #size-cells = <1>;
> - compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
> + compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
> reg = <0xF800 0x1000>;
> ranges;
> clkc: clkc@100 {
>
Applied.
Thanks,
Michal
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Re: [PATCH 3/3] ARM64: zynqmp: DT: Add interrupt-controller property to GPIO
On 10/23/2015 06:25 PM, Soren Brinkmann wrote: > GPIO can be used as interrupt-controller. Add the missing properties to > the GPIO node. > > Signed-off-by: Soren Brinkmann > --- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index 857eda5c7217..200fb588d0f5 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -133,6 +133,8 @@ > clocks = <&misc_clk>; > interrupt-parent = <&gic>; > interrupts = <0 16 4>; > + interrupt-controller; > + #interrupt-cells = <2>; > reg = <0x0 0xff0a 0x1000>; > }; > > Applied. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [PATCH 19/19] ARM: dts: zynq: replace gpio-key,wakeup with wakeup-source property
On 10/21/2015 12:10 PM, Sudeep Holla wrote:
> Though the keyboard driver for GPIO buttons(gpio-keys) will continue to
> check for/support the legacy "gpio-key,wakeup" boolean property to
> enable gpio buttons as wakeup source, "wakeup-source" is the new
> standard binding.
>
> This patch replaces the legacy "gpio-key,wakeup" with the unified
> "wakeup-source" property in order to avoid any futher copy-paste
> duplication.
>
> Cc: Michal Simek
> Cc: "Sören Brinkmann"
> Signed-off-by: Sudeep Holla
> ---
> arch/arm/boot/dts/zynq-zc702.dts | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/zynq-zc702.dts
> b/arch/arm/boot/dts/zynq-zc702.dts
> index 5df8f81f4217..cb64209bca08 100644
> --- a/arch/arm/boot/dts/zynq-zc702.dts
> +++ b/arch/arm/boot/dts/zynq-zc702.dts
> @@ -43,14 +43,14 @@
> label = "sw14";
> gpios = <&gpio0 12 0>;
> linux,code = <108>; /* down */
> - gpio-key,wakeup;
> + wakeup-source;
> autorepeat;
> };
> sw13 {
> label = "sw13";
> gpios = <&gpio0 14 0>;
> linux,code = <103>; /* up */
> - gpio-key,wakeup;
> + wakeup-source;
> autorepeat;
> };
> };
>
Applied to zynq/dt.
Thanks,
Michal
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Re: [PATCH 2/3] ARM: zynq: DT: Add interrupt-controller property to GPIO
On 10/27/2015 05:04 PM, Linus Walleij wrote: > On Fri, Oct 23, 2015 at 6:25 PM, Soren Brinkmann > wrote: > >> GPIO can be used as interrupt-controller. Add the missing properties to >> the GPIO node. >> >> Signed-off-by: Soren Brinkmann > > Acked-by: Linus Walleij Applied to zynq/dt. Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller
On 10/26/2015 11:26 AM, Bharat Kumar Gogada wrote: >>> + device_type = "pci"; >>> + interrupt-parent = <&gic>; >>> + interrupts = < 0 118 4 >>> + 0 116 4 >>> + 0 115 4 // MSI_1 [63...32] >>> + 0 114 4 >; // MSI_0 [31...0] >> >> Better write these as tuples: >> >> interrupts = <0 118 4>, <0 116 4>, <0 115 4>, <0 114 4>; >> >> And maybe reverse the order? It looks that might be what the soc >> integration person had in mind. >> >> Also, what is interrupt <0 117 4>? Is that connected here as well? >> Better list it as well then, even if you don't use it. >> > We have it but not using it, we will list it. > >>> + interrupt-map-mask = <0x0 0x0 0x0 0x7>; >>> + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1 >>> +0x0 0x0 0x0 0x2 &pcie_intc 0x2 >>> +0x0 0x0 0x0 0x3 &pcie_intc 0x3 >>> +0x0 0x0 0x0 0x4 &pcie_intc 0x4>; >> >>> + msi-parent = <&nwl_pcie>; >>> + reg = <0x0 0xfd0e 0x1000 >>> + 0x0 0xfd48 0x1000 >>> + 0x0 0xE000 0x100>; >> >> Same grouping for reg and interrupt-map as above for interrupts. > > Grouping reg and interrupt-map as tuples will make lengthy line and reduces > readability, is it compulsory ? FYI: Just this. reg = <0x0 0xfd0e 0x1000>, <0x0 0xfd48 0x1000>, <0x0 0xe000 0x100>; Also please make sure that you are using the same case for addresses. That 0xE000 case above. Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 2/3] ARM: zynq: dt: Updated devicetree for Zynq 7000 platform.
On 10/19/2015 08:24 PM, Josh Cartwright wrote:
> On Mon, Oct 19, 2015 at 04:09:09PM +0200, Michal Simek wrote:
>> On 10/18/2015 07:53 PM, Josh Cartwright wrote:
>>> On Fri, Oct 16, 2015 at 03:42:29PM -0700, Moritz Fischer wrote:
> [..]
>>>> @@ -294,6 +294,11 @@
>>>>devcfg: devcfg@f8007000 {
>>>>compatible = "xlnx,zynq-devcfg-1.0";
>>>>reg = <0xf8007000 0x100>;
>>>> + interrupt-parent = <&intc>;
>>>
>>> You shouldn't need interrupt-parent here. In fact, I suspect it can be
>>> removed from all sibling nodes as well.
>>
>> Correct. But I tend to do it vice-versa. To remove it from amba node and
>> keep it in every IP here. The reason is simple to let everybody know
>> that setting up right interrupt controller is something what they have
>> to care. If you have more interrupt controllers in the system it can be
>> messy.
>
> If you like that, then you'd like the interrupt-extended properly even
> better (I think).
yep. That works for me too.
Thanks,
Michal
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Re: [PATCHv2 0/3] Adding FPGA Manager support for Xilinx Zynq
On 10/18/2015 09:08 PM, Josh Cartwright wrote: > On Fri, Oct 16, 2015 at 03:42:27PM -0700, Moritz Fischer wrote: >> Hi all, >> >> I've tried to address most of the feedback that was brought up, >> the one thing I haven't looked at was the firmware format part, >> since that was still in discussion. >> So I'm still open to suggestions on how to handle this. > > Was there disagreement? I had thought we settled on limiting the > handling the BIN format explicitly, the rest of the thread was about > userspace tooling for BIT->BIN conversion. yep. Only BIN handling and keep small BIN header with sync word. Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 2/3] ARM: zynq: dt: Updated devicetree for Zynq 7000 platform.
On 10/18/2015 07:53 PM, Josh Cartwright wrote:
> On Fri, Oct 16, 2015 at 03:42:29PM -0700, Moritz Fischer wrote:
>> Added addtional nodes required for FPGA Manager operation
>> of the Xilinx Zynq Devc configuration interface.
>>
>> Reviewed-by: Sören Brinkmann
>> Signed-off-by: Moritz Fischer
>> ---
>>
>> v2: No changes
>>
>> ---
>> arch/arm/boot/dts/zynq-7000.dtsi | 5 +
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
>> b/arch/arm/boot/dts/zynq-7000.dtsi
>> index dc0457e..1a5220e 100644
>> --- a/arch/arm/boot/dts/zynq-7000.dtsi
>> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
>> @@ -294,6 +294,11 @@
>> devcfg: devcfg@f8007000 {
>> compatible = "xlnx,zynq-devcfg-1.0";
>> reg = <0xf8007000 0x100>;
>> +interrupt-parent = <&intc>;
>
> You shouldn't need interrupt-parent here. In fact, I suspect it can be
> removed from all sibling nodes as well.
Correct. But I tend to do it vice-versa. To remove it from amba node and
keep it in every IP here. The reason is simple to let everybody know
that setting up right interrupt controller is something what they have
to care. If you have more interrupt controllers in the system it can be
messy.
But again. Please remove this patch from this series. This will go to
mainline through arm-soc but 1/3 and 3/3 will go through Greg. That's
why please do not include it here.
Thanks,
Michal
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Re: [PATCH 2/3] dts: Updated devicetree bindings for Zynq 7000 platform
On 10/14/2015 04:50 AM, Moritz Fischer wrote:
> Hi Michal,
>
> On Mon, Oct 12, 2015 at 2:32 AM, Michal Simek wrote:
>> On 10/09/2015 12:45 AM, Moritz Fischer wrote:
>>> Added addtional bindings required for FPGA Manager operation
>>> of the Xilinx Zynq Devc configuration interface.
>>>
>>> Signed-off-by: Moritz Fischer
>>> ---
>>> arch/arm/boot/dts/zynq-7000.dtsi | 5 +
>>> 1 file changed, 5 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
>>> b/arch/arm/boot/dts/zynq-7000.dtsi
>>> index dc0457e..1a5220e 100644
>>> --- a/arch/arm/boot/dts/zynq-7000.dtsi
>>> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
>>> @@ -294,6 +294,11 @@
>>> devcfg: devcfg@f8007000 {
>>> compatible = "xlnx,zynq-devcfg-1.0";
>>> reg = <0xf8007000 0x100>;
>>> + interrupt-parent = <&intc>;
>>> + interrupts = <0 8 4>;
>>> + clocks = <&clkc 12>;
>>> + clock-names = "ref_clk";
>>> + syscon = <&slcr>;
>>> };
>>>
>>> global_timer: timer@f8f00200 {
>>>
>>
>> This patch should go via arm-soc tree. That's why please remove it from
>> this patchset.
>
> Just to clarify, you want this as a separate patch?
yes when binding is ACKed.
Thanks,
Michal
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Re: [PATCH 3/3] fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000
On 10/13/2015 07:33 AM, Mike Looijmans wrote:
> On 12-10-15 14:38, Michal Simek wrote:
>> Hi Mike,
>>
>> On 10/12/2015 02:22 PM, Mike Looijmans wrote:
>>> On 12-10-15 13:16, Michal Simek wrote:
>>>>
>>>>>>> +static int zynq_fpga_ops_write(struct fpga_manager *mgr,
>>>>>>> +const char *buf, size_t count)
>>>>>>> +{
>>>>>>> + struct zynq_fpga_priv *priv;
>>>>>>> + int err;
>>>>>>> + char *kbuf;
>>>>>>> + size_t i, in_count;
>>>>>>> + dma_addr_t dma_addr;
>>>>>>> + u32 transfer_length = 0;
>>>>>>> + bool endian_swap = false;
>>>>>>> +
>>>>>>> + in_count = count;
>>>>>>> + priv = mgr->priv;
>>>>>>> +
>>>>>>> + kbuf = dma_alloc_coherent(priv->dev, count, &dma_addr,
>>>>>>> GFP_KERNEL);
>>>>>>> + if (!kbuf)
>>>>>>> + return -ENOMEM;
>>>>>>> +
>>>>>>> + memcpy(kbuf, buf, count);
>>>>>>> +
>>>>>>> + /* look for the sync word */
>>>>>>> + for (i = 0; i < count - 4; i++) {
>>>>>>> + if (memcmp(kbuf + i, "\x66\x55\x99\xAA", 4) == 0) {
>>>>>>> + dev_dbg(priv->dev, "Found normal sync
>>>>>>> word\n");
>>>>>>> + endian_swap = false;
>>>>>>> + break;
>>>>>>> + }
>>>>
>>>> This is bin format
>>>>
>>>>>>> + if (memcmp(kbuf + i, "\xAA\x99\x55\x66", 4) == 0) {
>>>>>>> + dev_dbg(priv->dev, "Found swapped sync
>>>>>>> word\n");
>>>>>>> + endian_swap = true;
>>>>>>> + break;
>>>>>>> + }
>>>>
>>>> This is bit format from header
>>>>
>>>>>>> + }
>>>>>>
>>>>>> How much control do we have over mandating the format of firmware at
>>>>>> this point? It'd be swell if we could just mandate a specific
>>>>>> endianness, and leave this munging to usermode.
>>>>>
>>>>> That's a good question. Personally I do only care about one of both,
>>>>> but that's just because I get to decide for my targets...
>>>>> Opinions from the Xilinx guys?
>>>>
>>>> Don't know full history about this but in past bitstream in BIT format
>>>> was used. Which is header (partially decoding in u-boot for example)
>>>> with data.
>>>> On zynq native format is BIN which is format without header and data is
>>>> swapped.
>>>> This code just detects which format is used. If BIT, header is skipped
>>>> and data is swapped to BIN format.
>>>>
>>>> Back to origin question if this is something what can be handled from
>>>> user space. And answer is - yes it can be handled there.
>>>> But based on my experience it is very useful to be able to handle BIT
>>>> because it is built by tools by default.
>>>> Also with BIN format you are loosing record what this data bitstream
>>>> targets. Header in BIT gives you at least some ideas.
>>>
>>> People should stop using "cat" to program the FPGA and use a userspace
>>> tool instead. I've already released such tools under GPL, so anyone can
>>> pick up on it and extend it as required.
>>
>> Link?
>
> https://github.com/topic-embedded-products/dyplo-utils/blob/master/dyploprogrammer.cpp
>
> https://github.com/topic-embedded-products/libdyplo/blob/master/hardware.cpp#L261
>
>
> Will need some work to combine into a single tool though.
>
>> This is fpga manager based driver where "cat" won't be used.
>
> Haven't looked into it yet, but I guess at some point one will have to
> stream some data from userspace into the device, right?
Currently loading bitstream via firmware interface is used.
>
>>> The header for the "bit" format is completely ignored (you can't even
>>> u
Re: [PATCH 3/3] fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000
Hi Mike,
On 10/12/2015 02:22 PM, Mike Looijmans wrote:
> On 12-10-15 13:16, Michal Simek wrote:
>>
>>>>> +static int zynq_fpga_ops_write(struct fpga_manager *mgr,
>>>>> +const char *buf, size_t count)
>>>>> +{
>>>>> + struct zynq_fpga_priv *priv;
>>>>> + int err;
>>>>> + char *kbuf;
>>>>> + size_t i, in_count;
>>>>> + dma_addr_t dma_addr;
>>>>> + u32 transfer_length = 0;
>>>>> + bool endian_swap = false;
>>>>> +
>>>>> + in_count = count;
>>>>> + priv = mgr->priv;
>>>>> +
>>>>> + kbuf = dma_alloc_coherent(priv->dev, count, &dma_addr,
>>>>> GFP_KERNEL);
>>>>> + if (!kbuf)
>>>>> + return -ENOMEM;
>>>>> +
>>>>> + memcpy(kbuf, buf, count);
>>>>> +
>>>>> + /* look for the sync word */
>>>>> + for (i = 0; i < count - 4; i++) {
>>>>> + if (memcmp(kbuf + i, "\x66\x55\x99\xAA", 4) == 0) {
>>>>> + dev_dbg(priv->dev, "Found normal sync word\n");
>>>>> + endian_swap = false;
>>>>> + break;
>>>>> + }
>>
>> This is bin format
>>
>>>>> + if (memcmp(kbuf + i, "\xAA\x99\x55\x66", 4) == 0) {
>>>>> + dev_dbg(priv->dev, "Found swapped sync word\n");
>>>>> + endian_swap = true;
>>>>> + break;
>>>>> + }
>>
>> This is bit format from header
>>
>>>>> + }
>>>>
>>>> How much control do we have over mandating the format of firmware at
>>>> this point? It'd be swell if we could just mandate a specific
>>>> endianness, and leave this munging to usermode.
>>>
>>> That's a good question. Personally I do only care about one of both,
>>> but that's just because I get to decide for my targets...
>>> Opinions from the Xilinx guys?
>>
>> Don't know full history about this but in past bitstream in BIT format
>> was used. Which is header (partially decoding in u-boot for example)
>> with data.
>> On zynq native format is BIN which is format without header and data is
>> swapped.
>> This code just detects which format is used. If BIT, header is skipped
>> and data is swapped to BIN format.
>>
>> Back to origin question if this is something what can be handled from
>> user space. And answer is - yes it can be handled there.
>> But based on my experience it is very useful to be able to handle BIT
>> because it is built by tools by default.
>> Also with BIN format you are loosing record what this data bitstream
>> targets. Header in BIT gives you at least some ideas.
>
> People should stop using "cat" to program the FPGA and use a userspace
> tool instead. I've already released such tools under GPL, so anyone can
> pick up on it and extend it as required.
Link?
This is fpga manager based driver where "cat" won't be used.
>
> The header for the "bit" format is completely ignored (you can't even
> use it to determine if the bitstream is compatible with the current
> device) so there's no point in carrying it around.
up2you what you want to do with it. If you work with different boards
with different FPGAs it is at least helpful to know if X.bit target this
or that board. Unfortunately I am not aware about any public document
which describe what there is written.
> On the zynq, doing
> the "swap" in userspace was measurably faster than having the driver
> handle it, and that was even without using NEON instructions for byte
> swapping.
>
> I admit that being able to do "cat static.bit > /dev/xdevcfg" has had
> its uses. But it's not something that belongs in mainline Linux.
It is about comfort but I have really not a problem that driver will
handle just BIN format.
> Probably one of the key reasons that the "bit" format is still popular
> is that getting the Vivado tools to create a proper "bin" that will
> actually work on the Zynq is about as easy as nailing jelly to a tree.
> We've been using a simple Python script to do the bit->bin conversion
> for that reason.
In vivado it is one tcl cmd. But truth is that I don't really get why
BIN is not generated by default.
> Using the "bin" format in the driver keeps it simple and singular.
> Userspace tools can add whatever wrappers and headers they feel
> appropriate to it, these checks don't belong in the driver since they
> will be application specific. For example, some users would want to
> verify that a partial bitstream actually matches the static part that's
> currently in the FPGA.
agree.
Thanks,
Michal
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Re: [PATCH 3/3] fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000
>>> +static int zynq_fpga_ops_write(struct fpga_manager *mgr,
>>> +const char *buf, size_t count)
>>> +{
>>> + struct zynq_fpga_priv *priv;
>>> + int err;
>>> + char *kbuf;
>>> + size_t i, in_count;
>>> + dma_addr_t dma_addr;
>>> + u32 transfer_length = 0;
>>> + bool endian_swap = false;
>>> +
>>> + in_count = count;
>>> + priv = mgr->priv;
>>> +
>>> + kbuf = dma_alloc_coherent(priv->dev, count, &dma_addr, GFP_KERNEL);
>>> + if (!kbuf)
>>> + return -ENOMEM;
>>> +
>>> + memcpy(kbuf, buf, count);
>>> +
>>> + /* look for the sync word */
>>> + for (i = 0; i < count - 4; i++) {
>>> + if (memcmp(kbuf + i, "\x66\x55\x99\xAA", 4) == 0) {
>>> + dev_dbg(priv->dev, "Found normal sync word\n");
>>> + endian_swap = false;
>>> + break;
>>> + }
This is bin format
>>> + if (memcmp(kbuf + i, "\xAA\x99\x55\x66", 4) == 0) {
>>> + dev_dbg(priv->dev, "Found swapped sync word\n");
>>> + endian_swap = true;
>>> + break;
>>> + }
This is bit format from header
>>> + }
>>
>> How much control do we have over mandating the format of firmware at
>> this point? It'd be swell if we could just mandate a specific
>> endianness, and leave this munging to usermode.
>
> That's a good question. Personally I do only care about one of both,
> but that's just because I get to decide for my targets...
> Opinions from the Xilinx guys?
Don't know full history about this but in past bitstream in BIT format
was used. Which is header (partially decoding in u-boot for example)
with data.
On zynq native format is BIN which is format without header and data is
swapped.
This code just detects which format is used. If BIT, header is skipped
and data is swapped to BIN format.
Back to origin question if this is something what can be handled from
user space. And answer is - yes it can be handled there.
But based on my experience it is very useful to be able to handle BIT
because it is built by tools by default.
Also with BIN format you are loosing record what this data bitstream
targets. Header in BIT gives you at least some ideas.
Thanks,
Michal
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Re: [PATCH 1/3] doc: dt: fpga: Added Documentation for Xilinx Zynq FPGA manager.
On 10/09/2015 06:04 PM, Josh Cartwright wrote: > On Fri, Oct 09, 2015 at 12:45:05AM +0200, Moritz Fischer wrote: >> Signed-off-by: Moritz Fischer >> --- >> .../bindings/fpga/xilinx-zynq-fpga-mgr.txt | 26 >> ++ >> 1 file changed, 26 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt >> >> diff --git a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt >> b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt >> new file mode 100644 >> index 000..82ffda8 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt >> @@ -0,0 +1,26 @@ >> +Xilinx Zynq FPGA Manager >> + >> +Required properties: >> +- compatible: should contain "xlnx,zynq-devcfg-1.0" >> +- reg: base address and size for memory mapped io >> +- interrupt parent: interrupt source phandle > > I think you mean 'interrupt-parent', with the hyphen. yes. > > Actually, this isn't really a 'required' property of this node, as it > could be specified in a parent node. yes. Normally interrupt-parent is not listed as required property in the binding doc. Some docs listed it as optional property. Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] dts: Updated devicetree bindings for Zynq 7000 platform
On 10/09/2015 12:45 AM, Moritz Fischer wrote:
> Added addtional bindings required for FPGA Manager operation
> of the Xilinx Zynq Devc configuration interface.
>
> Signed-off-by: Moritz Fischer
> ---
> arch/arm/boot/dts/zynq-7000.dtsi | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
> b/arch/arm/boot/dts/zynq-7000.dtsi
> index dc0457e..1a5220e 100644
> --- a/arch/arm/boot/dts/zynq-7000.dtsi
> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
> @@ -294,6 +294,11 @@
> devcfg: devcfg@f8007000 {
> compatible = "xlnx,zynq-devcfg-1.0";
> reg = <0xf8007000 0x100>;
> + interrupt-parent = <&intc>;
> + interrupts = <0 8 4>;
> + clocks = <&clkc 12>;
> + clock-names = "ref_clk";
> + syscon = <&slcr>;
> };
>
> global_timer: timer@f8f00200 {
>
This patch should go via arm-soc tree. That's why please remove it from
this patchset.
Thanks,
Michal
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Re: [PATCH] doc: dt: Add interrupt parent to Xilinx AXI DMA instantation example.
On 08/21/2015 06:32 PM, Moritz Fischer wrote:
> This patch adds 'interrupt-parent' properties to the instantation example in
> the docs for the devicetree bindings of the Xilinx AXI DMA driver.
>
> Signed-off-by: Moritz Fischer
> ---
> Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
> b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
> index 2291c40..7c956e9 100644
> --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
> +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
> @@ -19,6 +19,7 @@ Required child node properties:
> - compatible: It should be either "xlnx,axi-dma-mm2s-channel" or
> "xlnx,axi-dma-s2mm-channel".
> - interrupts: Should contain per channel DMA interrupts.
> +- interrupt-parent: Should contain interrupt parent.
> - xlnx,datawidth: Should contain the stream data width, take values
> {32,64...1024}.
>
> @@ -36,11 +37,13 @@ axi_dma_0: axidma@4040 {
> dma-channel@4040 {
> compatible = "xlnx,axi-dma-mm2s-channel";
> interrupts = < 0 59 4 >;
> + interrupt-parent = <&intc>;
> xlnx,datawidth = <0x40>;
> } ;
> dma-channel@40400030 {
> compatible = "xlnx,axi-dma-s2mm-channel";
> interrupts = < 0 58 4 >;
> + interrupt-parent = <&intc>;
> xlnx,datawidth = <0x40>;
> } ;
> } ;
>
Acked-by: Michal Simek
Thanks,
Michal
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Re: [PATCH v5 1/5] arm/arm64: add smccc ARCH32
On 08/19/2015 06:50 PM, Will Deacon wrote: > On Wed, Aug 19, 2015 at 09:40:25AM +0100, Jens Wiklander wrote: >> Adds helpers to do SMC based on ARM SMC Calling Convention. >> CONFIG_HAVE_SMCCC is enabled for architectures that may support >> the SMC instruction. It's the responsibility of the caller to >> know if the SMC instruction is supported by the platform. > > [...] >> diff --git a/arch/arm64/kernel/smccc-call.S b/arch/arm64/kernel/smccc-call.S >> new file mode 100644 >> index 000..3ce7fe8 >> --- /dev/null >> +++ b/arch/arm64/kernel/smccc-call.S >> @@ -0,0 +1,34 @@ >> +/* >> + * Copyright (c) 2015, Linaro Limited >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License Version 2 as >> + * published by the Free Software Foundation. >> + * >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + */ >> +#include >> + >> +#define SMC_PARAM_W0_OFFS 0 >> +#define SMC_PARAM_W2_OFFS 8 >> +#define SMC_PARAM_W4_OFFS 16 >> +#define SMC_PARAM_W6_OFFS 24 >> + >> +/* void smccc_call32(struct smccc_param32 *param) */ >> +ENTRY(smccc_call32) >> + stp x28, x30, [sp, #-16]! > > Why are you saving lr? > >> + mov x28, x0 >> + ldp w0, w1, [x28, #SMC_PARAM_W0_OFFS] >> + ldp w2, w3, [x28, #SMC_PARAM_W2_OFFS] >> + ldp w4, w5, [x28, #SMC_PARAM_W4_OFFS] >> + ldp w6, w7, [x28, #SMC_PARAM_W6_OFFS] >> + smc #0 >> + stp w0, w1, [x28, #SMC_PARAM_W0_OFFS] >> + stp w2, w3, [x28, #SMC_PARAM_W2_OFFS] >> + ldp x28, x30, [sp], #16 >> + ret >> +ENDPROC(smccc_call32) > > Could we deal with this like we do for PSCI instead? (see > __invoke_psci_fn_smc). We could also then rename psci-call.S to fw-call.S > and stick this in there too. I think that make sense to make smc, hvc calling more generic. Remove psci name from __invoke_psci_fn_smc and just use it in other drivers. Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation
On 08/20/2015 08:18 AM, Vinod Koul wrote: > On Thu, Aug 20, 2015 at 11:41:33AM +0530, punnaiah choudary kalluri wrote: +- interrupts: Should contain DMA channel interrupt >>> channel interrupt or interrupts, former says it is plural >> >> ZynqMP DMA has single interrupt for each channel So, that is the reason >> i have explicitly mentioned it as interrupt ( not interrupts). >> >> Please let me know if you still want it to be plural. > > The example had multiple values so plural sounds right > I expect you are talking about this "interrupts = <0 117 4>;" It is 3 cells format used on ARM based on gic spec which is on SPI interrupt 117 active high level-sensitive Documentation/devicetree/bindings/arm/gic.txt Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH v1] mmc: sdhci-of-arasan: Add the support for sdhci-5.1
+linux-mmc
On 08/11/2015 04:53 PM, Michal Simek wrote:
> On 08/11/2015 09:46 AM, Shawn Lin wrote:
>> This patch adds the compatible string in sdhci-of-arasan.c to
>> support sdhci-arasan5.1 version of controller. No documented
>> controller IP version is found in the TRM, so we use ths version
>> of command queueing engine integrated into this controller by arasan
>> to specify our controller.
>>
>> Signed-off-by: Shawn Lin
>>
>> ---
>>
>> Changes in v1:
>> - Remove redundant SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN for "arasan, sdhci-5.1"
>> since
>> SDHCI will check "host->max_clk == 0" and let driver get it from
>> host->ops->get_max_clock.
>>
>> Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 2 +-
>> drivers/mmc/host/sdhci-of-arasan.c | 1 +
>> 2 files changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
>> b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
>> index 7e94903..da541c3 100644
>> --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
>> +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
>> @@ -9,7 +9,7 @@ Device Tree Bindings for the Arasan SDHCI Controller
>>
>> Required Properties:
>>- compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or
>> -'arasan,sdhci-4.9a'
>> +'arasan,sdhci-4.9a' or 'arasan,sdhci-5.1'
>>- reg: From mmc bindings: Register location and length.
>>- clocks: From clock bindings: Handles to clock inputs.
>>- clock-names: From clock bindings: Tuple including "clk_xin" and
>> "clk_ahb"
>> diff --git a/drivers/mmc/host/sdhci-of-arasan.c
>> b/drivers/mmc/host/sdhci-of-arasan.c
>> index ef5a7d2..75379cb 100644
>> --- a/drivers/mmc/host/sdhci-of-arasan.c
>> +++ b/drivers/mmc/host/sdhci-of-arasan.c
>> @@ -217,6 +217,7 @@ static int sdhci_arasan_remove(struct platform_device
>> *pdev)
>>
>> static const struct of_device_id sdhci_arasan_of_match[] = {
>> { .compatible = "arasan,sdhci-8.9a" },
>> +{ .compatible = "arasan,sdhci-5.1" },
>> { .compatible = "arasan,sdhci-4.9a" },
>> { }
>> };
>>
>
> Acked-by: Michal Simek
>
> Thanks,
> Michal
>
>
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Re: [RFC PATCH v1] mmc: sdhci-of-arasan: Add the support for sdhci-5.1
On 08/11/2015 09:46 AM, Shawn Lin wrote:
> This patch adds the compatible string in sdhci-of-arasan.c to
> support sdhci-arasan5.1 version of controller. No documented
> controller IP version is found in the TRM, so we use ths version
> of command queueing engine integrated into this controller by arasan
> to specify our controller.
>
> Signed-off-by: Shawn Lin
>
> ---
>
> Changes in v1:
> - Remove redundant SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN for "arasan, sdhci-5.1"
> since
> SDHCI will check "host->max_clk == 0" and let driver get it from
> host->ops->get_max_clock.
>
> Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 2 +-
> drivers/mmc/host/sdhci-of-arasan.c | 1 +
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> index 7e94903..da541c3 100644
> --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> @@ -9,7 +9,7 @@ Device Tree Bindings for the Arasan SDHCI Controller
>
> Required Properties:
>- compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or
> -'arasan,sdhci-4.9a'
> +'arasan,sdhci-4.9a' or 'arasan,sdhci-5.1'
>- reg: From mmc bindings: Register location and length.
>- clocks: From clock bindings: Handles to clock inputs.
>- clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
> diff --git a/drivers/mmc/host/sdhci-of-arasan.c
> b/drivers/mmc/host/sdhci-of-arasan.c
> index ef5a7d2..75379cb 100644
> --- a/drivers/mmc/host/sdhci-of-arasan.c
> +++ b/drivers/mmc/host/sdhci-of-arasan.c
> @@ -217,6 +217,7 @@ static int sdhci_arasan_remove(struct platform_device
> *pdev)
>
> static const struct of_device_id sdhci_arasan_of_match[] = {
> { .compatible = "arasan,sdhci-8.9a" },
> + { .compatible = "arasan,sdhci-5.1" },
> { .compatible = "arasan,sdhci-4.9a" },
> { }
> };
>
Acked-by: Michal Simek
Thanks,
Michal
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Re: [RFCv3 1/4] docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.
On 08/05/2015 09:43 PM, Moritz Fischer wrote: > Michal, > > On Tue, Aug 4, 2015 at 8:10 AM, Philipp Zabel wrote: >> Hi Moritz, >> >> Am Dienstag, den 04.08.2015, 08:05 -0700 schrieb Moritz Fischer: >>> Hi Philip, >>> >>> On Tue, Aug 4, 2015 at 1:09 AM, Philipp Zabel >>> wrote: Hi Moritz, Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer: >> [...] > +Required properties: > +- compatible: "xlnx,zynq-reset" > +- reg: SLCR offset and size taken via syscon <0x200 0x48> > +- syscon: <&slcr> > + This should be a phandle to the Zynq's SLCR register. ^ register singular? >>> Do you want me to resend the entire set, or are you cool with just git >>> amending the 's' for registers? >> >> Amended and applied, thanks. > > Will you take 4/4 and 2/4 via your tree? Applied to zynq/dt and zynq/soc. Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFCv3 1/4] docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.
On 08/04/2015 10:09 AM, Philipp Zabel wrote: > Hi Moritz, > > Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer: >> Signed-off-by: Moritz Fischer >> --- >> .../devicetree/bindings/reset/zynq-reset.txt | 68 >> ++ >> 1 file changed, 68 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/reset/zynq-reset.txt >> >> diff --git a/Documentation/devicetree/bindings/reset/zynq-reset.txt >> b/Documentation/devicetree/bindings/reset/zynq-reset.txt >> new file mode 100644 >> index 000..498c037a >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/reset/zynq-reset.txt >> @@ -0,0 +1,68 @@ >> +Xilinx Zynq Reset Manager >> + >> +The Zynq AP-SoC has several different resets. >> + >> +See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq >> resets. >> + >> +Required properties: >> +- compatible: "xlnx,zynq-reset" >> +- reg: SLCR offset and size taken via syscon <0x200 0x48> >> +- syscon: <&slcr> >> + This should be a phandle to the Zynq's SLCR register. > > ^ register singular? > > I still think the syscon phandle property is superfluous, > but I'm fine with keeping it for consistency. > It could always be made optional later. Great. Philipp: I expect you want to take at least 1/4 and 3/4 via your tree. I am fine if you also want to add 2/4 and 4/4 via your tree. If you think that they should go via arm-soc please let me know and I will add them to the queue. Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFCv3 2/4] dts: zynq: Add devicetree entry for Xilinx Zynq reset controller.
On 07/31/2015 03:13 AM, Moritz Fischer wrote:
> Signed-off-by: Moritz Fischer
> ---
> arch/arm/boot/dts/zynq-7000.dtsi | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
> b/arch/arm/boot/dts/zynq-7000.dtsi
> index 0691508..6bebf02 100644
> --- a/arch/arm/boot/dts/zynq-7000.dtsi
> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
> @@ -1,5 +1,6 @@
> /*
> * Copyright (C) 2011 - 2014 Xilinx
> + * Copyright (C) 2015 National Instruments Corp.
> *
> * This software is licensed under the terms of the GNU General Public
> * License version 2, as published by the Free Software Foundation, and
> @@ -258,6 +259,13 @@
> reg = <0x100 0x100>;
> };
>
> + rstc: rstc@200 {
> + compatible = "xlnx,zynq-reset";
> + reg = <0x200 0x48>;
> + #reset-cells = <1>;
> + syscon = <&slcr>;
> + };
> +
> pinctrl0: pinctrl@700 {
> compatible = "xlnx,pinctrl-zynq";
> reg = <0x700 0x200>;
>
Acked-by: Michal Simek
Thanks,
Michal
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Re: [RFCv3 4/4] ARM: zynq: Select ARCH_HAS_RESET_CONTROLLER
On 07/31/2015 03:13 AM, Moritz Fischer wrote: > Signed-off-by: Moritz Fischer > --- > arch/arm/mach-zynq/Kconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig > index 78e5e00..77d7df7 100644 > --- a/arch/arm/mach-zynq/Kconfig > +++ b/arch/arm/mach-zynq/Kconfig > @@ -1,5 +1,6 @@ > config ARCH_ZYNQ > bool "Xilinx Zynq ARM Cortex A9 Platform" if ARCH_MULTI_V7 > + select ARCH_HAS_RESET_CONTROLLER > select ARCH_SUPPORTS_BIG_ENDIAN > select ARM_AMBA > select ARM_GIC > Reviewed-by: Michal Simek Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFCv2 1/3] docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.
On 07/29/2015 07:38 PM, Sören Brinkmann wrote:
> On Tue, 2015-07-28 at 11:14PM -0700, Moritz Fischer wrote:
>> Hi Sören,
>>
>> On Tue, Jul 28, 2015 at 3:53 PM, Sören Brinkmann
>> wrote:
>>> On Mon, 2015-07-27 at 09:52PM -0700, Moritz Fischer wrote:
Hi Sören,
thanks for your feedback.
On Mon, Jul 27, 2015 at 7:58 PM, Sören Brinkmann
wrote:
> Hi Moritz,
>
> On Fri, 2015-07-24 at 05:21PM -0700, Moritz Fischer wrote:
>> Signed-off-by: Moritz Fischer
>> ---
>> Documentation/devicetree/bindings/reset/zynq-reset-pl.txt | 13
>> +
>> 1 file changed, 13 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/reset/zynq-reset-pl.txt
>>
>> diff --git a/Documentation/devicetree/bindings/reset/zynq-reset-pl.txt
>> b/Documentation/devicetree/bindings/reset/zynq-reset-pl.txt
>> new file mode 100644
>> index 000..ac4499e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/reset/zynq-reset-pl.txt
>> @@ -0,0 +1,13 @@
>> +Xilinx Zynq PL Reset Manager
>> +
>> +Required properties:
>> +- compatible: "xlnx,zynq-reset-pl"
>> +- syscon <&slcr>;
>> +- #reset-cells: 1
>> +
>> +Example:
>> + rstc: rstc@240 {
>> + #reset-cells = <1>;
>> + compatible = "xlnx,zynq-reset-pl";
>> + syscon = <&slcr>;
>> + };
>
> I think you also have to add the outputs and make them part of the
> binding. Otherwise you'd have to read the implementation to find
> out what device should be hooked up to which output of the
> reset-controller.
Is something like this what you had in mind? I had that prepared for
the next round of patches:
Reset outputs:
0 : soft reset
32 : ddr reset
64 : topsw reset
96 : dmac reset
128: usb0 reset
129: usb1 reset
160: gem0 reset
161: gem1 reset
164: gem0 rx reset
165: gem1 rx reset
166: gem0 ref reset
167: gem1 ref reset
192: sdio0 reset
193: sdio1 reset
196: sdio0 ref reset
197: sdio1 ref reset
224: spi0 reset
225: spi1 reset
226: spi0 ref reset
227: spi1 ref reset
256: can0 reset
257: can1 reset
258: can0 ref reset
259: can1 ref reset
288: i2c0 reset
289: i2c1 reset
320: uart0 reset
321: uart1 reset
322: uart0 ref reset
323: uart1 ref reset
352: gpio reset
384: lqspi reset
385: qspi ref reset
416: smc reset
417: smc ref reset
448: ocm reset
512: fpga0 out reset
513: fpga1 out reset
514: fpga2 out reset
515: fpga3 out reset
544: a9 reset 0
545: a9 reset 1
552: peri reset
>>>
>>> Basically, yes. I guess the gaps are due to directly mapping this number
>>> to bank and bit instead of doing some more complex mapping in between?
>>> I'm not sure whether I like this :) I guess if a number is off the
>>> driver would still toggle the addressed bit?
>>
>> My assumption was that people would use a #include
>> in their dts. Assuming I got the
>> numbers in there right this makes it hard to misuse by accident.
>> I'm not saying it's perfect ...
>
> Michal always turned down the #include patches with the argument of
> re-using the dts files outside of the Linux sources where those includes
> etc may not be available in this form.
yes. All these includes end up in more work when you want to generate
them or move to any other project.
I don't think that make sense to caused another problem just because of
that. Simple add these values to reset binding doc and then you <&rstc
number> in nodes.
Because we agreed that it has to be done on driver basis this is just
copy that macros from one file to another.
Thanks,
Michal
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[PATCH v2] ARM64: zynqmp: Add eeprom memories on i2c bus
Add i2c eeprom memories on i2c bus.
Signed-off-by: Michal Simek
---
Changes in v2:
- Change eeprom max freq from 100k to 400k
---
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
index c5cc8dbd0968..3b1011169756 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -50,6 +50,24 @@
status = "okay";
};
+&i2c0 {
+ status = "okay";
+ clock-frequency = <40>;
+ eeprom@54 {
+ compatible = "at,24c64";
+ reg = <0x54>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <40>;
+ eeprom@55 {
+ compatible = "at,24c64";
+ reg = <0x55>;
+ };
+};
+
&sata {
status = "okay";
ceva,broken-gen2;
--
2.3.5
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Re: [PATCH 7/7] ARM64: zynqmp: Add eeprom memories on i2c bus
On 07/27/2015 12:01 PM, Shubhrajyoti Datta wrote:
> Hi,
>
> On Mon, Jul 27, 2015 at 3:18 PM, Michal Simek wrote:
>> Add i2c eeprom memories on i2c bus.
>>
>> Signed-off-by: Michal Simek
>> ---
>>
>> arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 18 ++
>> 1 file changed, 18 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
>> b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
>> index 206e18eca2fb..47debdcbefbf 100644
>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
>> @@ -36,6 +36,24 @@
>> status = "okay";
>> };
>>
>> +&i2c0 {
>> + status = "okay";
>> + clock-frequency = <10>;
> If I am not wrong eeprom could work at 400k Could we make that as the speed.
I was retesting that and 400k works on this emulation platform too. I
will send v2.
Thanks,
Michal
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Re: [RFCv2 1/3] docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.
On 07/28/2015 10:05 AM, Philipp Zabel wrote:
> Am Freitag, den 24.07.2015, 17:21 -0700 schrieb Moritz Fischer:
>> Signed-off-by: Moritz Fischer
>> ---
>> Documentation/devicetree/bindings/reset/zynq-reset-pl.txt | 13 +
>> 1 file changed, 13 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/reset/zynq-reset-pl.txt
>>
>> diff --git a/Documentation/devicetree/bindings/reset/zynq-reset-pl.txt
>> b/Documentation/devicetree/bindings/reset/zynq-reset-pl.txt
>> new file mode 100644
>> index 000..ac4499e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/reset/zynq-reset-pl.txt
>> @@ -0,0 +1,13 @@
>> +Xilinx Zynq PL Reset Manager
>> +
>> +Required properties:
>> +- compatible: "xlnx,zynq-reset-pl"
>> +- syscon <&slcr>;
>> +- #reset-cells: 1
>> +
>> +Example:
>> +rstc: rstc@240 {
>> +#reset-cells = <1>;
>> +compatible = "xlnx,zynq-reset-pl";
>> +syscon = <&slcr>;
>
> Why the syscon phandle if rstc always is the child of slcr? Why not just
> request the syscon for the rstc's parent node.
We are using this description for pincntrl which was properly reviewed
that's why I expect Moritz just use the same style.
But yes also referencing parent should work.
TBH I don't have strong preference but having unified style is something
what I would prefer.
Also I see that using parent is used by others and it looks like that
having something like syscon_regmap_lookup_parent will be worth to have.
Thanks,
Michal
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Re: [RFCv2 2/3] dts: zynq: Add devicetree entry for Xilinx Zynq reset controller.
On 07/28/2015 08:59 AM, Nicolas Ferre wrote: > Le 28/07/2015 07:03, Moritz Fischer a écrit : >> Hi Michal, >> >> I agree we need to be careful with changing the bindings. >> >> On Sun, Jul 26, 2015 at 11:56 PM, Michal Simek wrote: >>> Hi Moritz, >>> >>> On 07/25/2015 02:21 AM, Moritz Fischer wrote: >>>> Signed-off-by: Moritz Fischer >>>> --- >>>> arch/arm/boot/dts/zynq-7000.dtsi| 43 - >>> >>> This patch is nice in general but every change in binding should be >>> discussed separately. There is also necessary to wire them up in the >>> driver to do action. That's why I think that will be the best just to >>> add the code to slcr and keep others untouched. >> >> Ok, just to clarify: You'd suggest to just add the rstc as child node >> to the slcr, >> and leave the other nodes untouched? >> >>> >>> For example MACB/GEM is one example. Adding names to this node and >>> extending driver to work properly with reset means that all others MACB >>> users will be affected. Definitely this patch should be ACKed by Nicolas. > > Actually, I don't know why a reset property should be added to the macb > driver... I expect resetting IP core can solve something. But as I said it is questionable if IP should be reset when driver is probed. Definitely on Zynq there is a support for it. I am not aware about any problem which requires IP to be reset. Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFCv2 3/3] reset: reset-zynq: Adding support for Xilinx Zynq reset controller.
On 07/28/2015 06:59 AM, Moritz Fischer wrote:
> Hi Michal,
>
> On Mon, Jul 27, 2015 at 12:12 AM, Michal Simek wrote:
>> On 07/25/2015 02:21 AM, Moritz Fischer wrote:
>>> This adds a reset controller driver to control the Xilinx Zynq
>>> SoC's various resets.
>>>
>>> Signed-off-by: Moritz Fischer
>>> ---
>>> drivers/reset/Makefile | 1 +
>>> drivers/reset/reset-zynq.c | 142
>>> +
>>> 2 files changed, 143 insertions(+)
>>> create mode 100644 drivers/reset/reset-zynq.c
>>>
>>> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
>>> index 157d421..3fe50e7 100644
>>> --- a/drivers/reset/Makefile
>>> +++ b/drivers/reset/Makefile
>>> @@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
>>> obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
>>> obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
>>> obj-$(CONFIG_ARCH_STI) += sti/
>>> +obj-$(CONFIG_ARCH_ZYNQ) += reset-zynq.o
>>> diff --git a/drivers/reset/reset-zynq.c b/drivers/reset/reset-zynq.c
>>> new file mode 100644
>>> index 000..05e37f8
>>> --- /dev/null
>>> +++ b/drivers/reset/reset-zynq.c
>>> @@ -0,0 +1,142 @@
>>> +/*
>>> + * Copyright (c) 2015, National Instruments Corp.
>>> + *
>>> + * Xilinx Zynq Reset controller driver
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License as published by
>>> + * the Free Software Foundation; version 2 of the License.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>> + * GNU General Public License for more details.
>>> + */
>>> +
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +
>>> +/* Offsets into SLCR regmap */
>>> +#define SLCR_RST_CTRL_OFFSET 0x200 /* FPGA Software Reset Control */
>>> +
>>> +#define NBANKS 18
>>> +
>>> +struct zynq_reset_data {
>>> + struct regmap *slcr;
>>> + struct reset_controller_dev rcdev;
>>> +};
>>> +
>>> +#define to_zynq_reset_data(p)\
>>> + container_of((p), struct zynq_reset_data, rcdev)
>>> +
>>> +static int zynq_reset_assert(struct reset_controller_dev *rcdev,
>>> + unsigned long id)
>>> +{
>>> + struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
>>> +
>>> + int bank = id / BITS_PER_LONG;
>>> + int offset = id % BITS_PER_LONG;
>>> +
>>
>> Personally me I would also add debug message here to be simply enabled
>> for easier tracking.
> See below
>>
>>> + regmap_update_bits(priv->slcr,
>>> +SLCR_RST_CTRL_OFFSET + (bank * 4),
>>> +BIT(offset),
>>> +BIT(offset));
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int zynq_reset_deassert(struct reset_controller_dev *rcdev,
>>> +unsigned long id)
>>> +{
>>> + struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
>>> +
>>> + int bank = id / BITS_PER_LONG;
>>> + int offset = id % BITS_PER_LONG;
>>> +
>>
>> debug message here too.
> is:
> pr_debug("%s: bank: %u offset %u\n", __func__, bank, offset);
> accetable? Otherwise I'd have to carry around a struct dev* to use dev_dbg()
It is fine for me.
Thanks,
Michal
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Re: [RFCv2 2/3] dts: zynq: Add devicetree entry for Xilinx Zynq reset controller.
On 07/28/2015 07:03 AM, Moritz Fischer wrote: > Hi Michal, > > I agree we need to be careful with changing the bindings. > > On Sun, Jul 26, 2015 at 11:56 PM, Michal Simek wrote: >> Hi Moritz, >> >> On 07/25/2015 02:21 AM, Moritz Fischer wrote: >>> Signed-off-by: Moritz Fischer >>> --- >>> arch/arm/boot/dts/zynq-7000.dtsi| 43 - >> >> This patch is nice in general but every change in binding should be >> discussed separately. There is also necessary to wire them up in the >> driver to do action. That's why I think that will be the best just to >> add the code to slcr and keep others untouched. > > Ok, just to clarify: You'd suggest to just add the rstc as child node > to the slcr, > and leave the other nodes untouched? yes and then add it on case-by-case basis. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [RFCv2 1/3] docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.
On 07/28/2015 06:55 AM, Moritz Fischer wrote:
> Hi Michal,
>
> On Sun, Jul 26, 2015 at 10:09 PM, Michal Simek wrote:
>> On 07/25/2015 02:21 AM, Moritz Fischer wrote:
>>> Signed-off-by: Moritz Fischer
>>> ---
>>> Documentation/devicetree/bindings/reset/zynq-reset-pl.txt | 13
>>> +
>>> 1 file changed, 13 insertions(+)
>>> create mode 100644
>>> Documentation/devicetree/bindings/reset/zynq-reset-pl.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/reset/zynq-reset-pl.txt
>>> b/Documentation/devicetree/bindings/reset/zynq-reset-pl.txt
>>> new file mode 100644
>>> index 000..ac4499e
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/reset/zynq-reset-pl.txt
>>> @@ -0,0 +1,13 @@
>>> +Xilinx Zynq PL Reset Manager
>>
>> here
>>
>>> +
>>> +Required properties:
>>> +- compatible: "xlnx,zynq-reset-pl"
>>
>> Currently it is not just PL reset controller.
>>
>>> +- syscon <&slcr>;
>>
>>
>> missing : and please be more descriptive here.
>>
>>> +- #reset-cells: 1
>>> +
>>> +Example:
>>> + rstc: rstc@240 {
>>> + #reset-cells = <1>;
>>> + compatible = "xlnx,zynq-reset-pl";
>>
>> Compatible property should go first.
>>
>> I am missing that reg property
>>
>>> + syscon = <&slcr>;
>>> + };
>>>
>>
> Would something like this work:
>
> Xilinx Zynq Reset Manager
>
> The Zynq AP-SoC has several different resets.
>
> See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
>
> Required properties:
> - compatible: "xlnx,zynq-reset"
> - reg: SLCR offset and size taken via syscon <0x200 0x50>
> - syscon: <&slcr>
> This should be a phandle to the Zynq's SLCR register.
> - #reset-cells: Must be 1
>
> The Zynq Reset Manager needs to be a child node of the SLCR.
>
> Example:
> rstc: rstc@200 {
> compatible = "xlnx,zynq-reset";
> reg = <0x200 0x50>;
> #reset-cells = <1>;
> syscon = <&slcr>;
> };
Looks good to me.
Thanks,
Michal
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[PATCH] ARM64: zynqmp: Enable spi flashes on ep108
Enable spi flashes on ep108.
Signed-off-by: Michal Simek
---
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 34 +
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
index 47debdcbefbf..279a992ce70e 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -81,6 +81,40 @@
status = "okay";
};
+&spi0 {
+ status = "okay";
+ num-cs = <1>;
+ spi0_flash0: spi0_flash0@0 {
+ compatible = "m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <5000>;
+ reg = <0>;
+
+ spi0_flash0@ {
+ label = "spi0_flash0";
+ reg = <0x0 0x10>;
+ };
+ };
+};
+
+&spi1 {
+ status = "okay";
+ num-cs = <1>;
+ spi1_flash0: spi1_flash0@0 {
+ compatible = "m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <5000>;
+ reg = <0>;
+
+ spi1_flash0@ {
+ label = "spi1_flash0";
+ reg = <0x0 0x10>;
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
--
2.3.5
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[PATCH 1/7] ARM64: zynqmp: Use zynqmp specific compatible string for gpio
The patch:
"gpio: Added support to Zynq Ultrascale+ MPSoC"
(sha1: bdf7a4ae371894b4dc10b5820006b0a82d484929)
added zynqmp specific features. This patch is switching the driver to
use the zynqmp compatible string.
Also enable the driver for ep108 platform.
Signed-off-by: Michal Simek
---
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 4
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
index 02b5d76c33f7..82deb24dddeb 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -42,6 +42,10 @@
};
};
+&gpio {
+ status = "okay";
+};
+
&sata0 {
status = "okay";
ceva,broken-gen2;
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index e7545edf6179..bd9ba0cab504 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -163,7 +163,7 @@
};
gpio: gpio@ff0a {
- compatible = "xlnx,zynq-gpio-1.0";
+ compatible = "xlnx,zynqmp-gpio-1.0";
status = "disabled";
#gpio-cells = <0x2>;
clocks = <&misc_clk>;
--
2.3.5
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[PATCH 3/7] ARM64: zynqmp: Add SMMU support
Add SMMU DT node to DTSI.
Signed-off-by: Michal Simek
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index d58c9689c82a..7617722cc969 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -244,6 +244,18 @@
#size-cells = <0>;
};
+ smmu0: smmu0@fd80 {
+ compatible = "arm,mmu-500";
+ reg = <0x0 0xfd80 0x2>;
+ #global-interrupts = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 157 4>,
+ <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
+ <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
+ <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
+ <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>;
+ };
+
spi0: spi@ff04 {
compatible = "cdns,spi-r1p6";
status = "disabled";
--
2.3.5
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[PATCH 4/7] ARM64: zynqmp: Add DWC3 usb support
Add usb nodes to DTSI and enable both of them on ep108.
Signed-off-by: Michal Simek
---
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 12
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 20
2 files changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
index 3aebc3f5d02a..d6cc4b583587 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -58,3 +58,15 @@
&uart0 {
status = "okay";
};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 7617722cc969..9cf364dc4890 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -343,6 +343,26 @@
clocks = <&misc_clk>, <&misc_clk>;
};
+ usb0: usb@fe20 {
+ compatible = "snps,dwc3";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 65 4>;
+ reg = <0x0 0xfe20 0x4>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&misc_clk>, <&misc_clk>;
+ };
+
+ usb1: usb@fe30 {
+ compatible = "snps,dwc3";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 70 4>;
+ reg = <0x0 0xfe30 0x4>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&misc_clk>, <&misc_clk>;
+ };
+
watchdog0: watchdog@fd4d {
compatible = "cdns,wdt-r1p2";
status = "disabled";
--
2.3.5
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[PATCH 7/7] ARM64: zynqmp: Add eeprom memories on i2c bus
Add i2c eeprom memories on i2c bus.
Signed-off-by: Michal Simek
---
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
index 206e18eca2fb..47debdcbefbf 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -36,6 +36,24 @@
status = "okay";
};
+&i2c0 {
+ status = "okay";
+ clock-frequency = <10>;
+ eeprom@54 {
+ compatible = "at,24c64";
+ reg = <0x54>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <10>;
+ eeprom@55 {
+ compatible = "at,24c64";
+ reg = <0x55>;
+ };
+};
+
&gem0 {
status = "okay";
phy-handle = <&phy0>;
--
2.3.5
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[PATCH 6/7] ARM64: zynqmp: Enable sdhci on ep108
Enable both sdhcis on ep108.
Signed-off-by: Michal Simek
---
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
index faee1617ab16..206e18eca2fb 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -55,6 +55,14 @@
ceva,broken-gen2;
};
+&sdhci0 {
+ status = "okay";
+};
+
+&sdhci1 {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
--
2.3.5
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[PATCH 5/7] ARM64: zynqmp: Enable watchdog on ep108
Enable watchdog on ep108.
Signed-off-by: Michal Simek
---
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
index d6cc4b583587..faee1617ab16 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -70,3 +70,7 @@
dr_mode = "host";
maximum-speed = "high-speed";
};
+
+&watchdog0 {
+ status = "okay";
+};
--
2.3.5
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[PATCH 2/7] ARM64: zynqmp: Add CANs node for platform
Also enable can0 for ep108.
Signed-off-by: Michal Simek
---
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 4
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 24
2 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
index 82deb24dddeb..3aebc3f5d02a 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -32,6 +32,10 @@
};
};
+&can0 {
+ status = "okay";
+};
+
&gem0 {
status = "okay";
phy-handle = <&phy0>;
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index bd9ba0cab504..d58c9689c82a 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -96,6 +96,30 @@
#size-cells = <1>;
ranges;
+ can0: can@ff06 {
+ compatible = "xlnx,zynq-can-1.0";
+ status = "disabled";
+ clocks = <&misc_clk &misc_clk>;
+ clock-names = "can_clk", "pclk";
+ reg = <0x0 0xff06 0x1000>;
+ interrupts = <0 23 4>;
+ interrupt-parent = <&gic>;
+ tx-fifo-depth = <0x40>;
+ rx-fifo-depth = <0x40>;
+ };
+
+ can1: can@ff07 {
+ compatible = "xlnx,zynq-can-1.0";
+ status = "disabled";
+ clocks = <&misc_clk &misc_clk>;
+ clock-names = "can_clk", "pclk";
+ reg = <0x0 0xff07 0x1000>;
+ interrupts = <0 24 4>;
+ interrupt-parent = <&gic>;
+ tx-fifo-depth = <0x40>;
+ rx-fifo-depth = <0x40>;
+ };
+
misc_clk: misc_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
--
2.3.5
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Re: [RFCv2 3/3] reset: reset-zynq: Adding support for Xilinx Zynq reset controller.
_ops;
> + priv->rcdev.of_node = pdev->dev.of_node;
> + reset_controller_register(&priv->rcdev);
> +
> + return 0;
> +}
> +
> +static int zynq_reset_remove(struct platform_device *pdev)
> +{
> + struct zynq_reset_data *priv = platform_get_drvdata(pdev);
> +
> + reset_controller_unregister(&priv->rcdev);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id zynq_reset_dt_ids[] = {
> + { .compatible = "xlnx,zynq-reset", },
> + { /* sentinel */ },
> +};
> +
> +static struct platform_driver zynq_reset_driver = {
> + .probe = zynq_reset_probe,
> + .remove = zynq_reset_remove,
> + .driver = {
> + .name = "zynq-pl-reset",
> + .of_match_table = zynq_reset_dt_ids,
> + },
> +};
> +module_platform_driver(zynq_reset_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Moritz Fischer ");
> +MODULE_DESCRIPTION("Zynq Reset Controller Driver");
>
Also I am missing enabling reset controller in the arch.
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 78e5e007f52d..02a84fdee1bd 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -1,6 +1,7 @@
config ARCH_ZYNQ
bool "Xilinx Zynq ARM Cortex A9 Platform" if ARCH_MULTI_V7
select ARCH_SUPPORTS_BIG_ENDIAN
+ select ARCH_HAS_RESET_CONTROLLER
select ARM_AMBA
select ARM_GIC
select ARM_GLOBAL_TIMER if !CPU_FREQ
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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Re: [RFCv2 2/3] dts: zynq: Add devicetree entry for Xilinx Zynq reset controller.
Hi Moritz, On 07/25/2015 02:21 AM, Moritz Fischer wrote: > Signed-off-by: Moritz Fischer > --- > arch/arm/boot/dts/zynq-7000.dtsi| 43 - This patch is nice in general but every change in binding should be discussed separately. There is also necessary to wire them up in the driver to do action. That's why I think that will be the best just to add the code to slcr and keep others untouched. For example MACB/GEM is one example. Adding names to this node and extending driver to work properly with reset means that all others MACB users will be affected. Definitely this patch should be ACKed by Nicolas. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
Re: [RFCv2 3/3] reset: reset-zynq: Adding support for Xilinx Zynq reset controller.
turn 0;
> +}
> +
> +static int zynq_reset_remove(struct platform_device *pdev)
> +{
> + struct zynq_reset_data *priv = platform_get_drvdata(pdev);
> +
> + reset_controller_unregister(&priv->rcdev);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id zynq_reset_dt_ids[] = {
> + { .compatible = "xlnx,zynq-reset", },
> + { /* sentinel */ },
> +};
> +
> +static struct platform_driver zynq_reset_driver = {
> + .probe = zynq_reset_probe,
> + .remove = zynq_reset_remove,
> + .driver = {
> + .name = "zynq-pl-reset",
PL in name.
BTW: Don't you want to use KBUILD_MODNAME here?
> + .of_match_table = zynq_reset_dt_ids,
> + },
> +};
> +module_platform_driver(zynq_reset_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Moritz Fischer ");
> +MODULE_DESCRIPTION("Zynq Reset Controller Driver");
>
The rest looks good - will test it.
Thanks,
Michal
--
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w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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Re: [RFCv2 1/3] docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.
On 07/25/2015 02:21 AM, Moritz Fischer wrote:
> Signed-off-by: Moritz Fischer
> ---
> Documentation/devicetree/bindings/reset/zynq-reset-pl.txt | 13 +
> 1 file changed, 13 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/zynq-reset-pl.txt
>
> diff --git a/Documentation/devicetree/bindings/reset/zynq-reset-pl.txt
> b/Documentation/devicetree/bindings/reset/zynq-reset-pl.txt
> new file mode 100644
> index 000..ac4499e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/zynq-reset-pl.txt
> @@ -0,0 +1,13 @@
> +Xilinx Zynq PL Reset Manager
here
> +
> +Required properties:
> +- compatible: "xlnx,zynq-reset-pl"
Currently it is not just PL reset controller.
> +- syscon <&slcr>;
missing : and please be more descriptive here.
> +- #reset-cells: 1
> +
> +Example:
> + rstc: rstc@240 {
> + #reset-cells = <1>;
> + compatible = "xlnx,zynq-reset-pl";
Compatible property should go first.
I am missing that reg property
> + syscon = <&slcr>;
> + };
>
Thanks,
Michal
--
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w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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Re: [PATCH v7 0/3] Add arm pl353 smc nand driver for xilinx zynq soc
On 07/08/2015 09:40 PM, Josh Cartwright wrote: > On Mon, Jun 08, 2015 at 11:38:35PM +0530, Punnaiah Choudary Kalluri wrote: >> The following patches add arm pl353 static memory controller driver for >> xilinx zynq soc. The arm pl353 smc supports two interfaces i.e nand and >> nor/sram memory interfaces. The current implementation supports only a >> single SMC instance and nand specific configuration. > > What's the integration plan for this guy? Looks like we missed 4.2. > It'd be swell to get have NAND support land for Zynq in 4.3. > > Assuming there is nothing else holding it back: > > Brian- I'm assuming you'll want to take this through your tree. > > It looks like most of the stuff in drivers/memory have historically gone > through arm-soc/drivers, Michal- does it make sense for you to pick up > http://lkml.kernel.org/r/1433786857-32575-1-git-send-email-punn...@xilinx.com? I am happy to take this via zynq tree and arm-soc tree if this is the right way. Josh: Also none can stop you to give us you ACK or Tested-by line. Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv5 2/2] mailbox: Adding driver for Xilinx LogiCORE IP mailbox.
On 06/25/2015 11:35 AM, Paul Bolle wrote: > On Thu, 2015-06-25 at 09:47 +0200, Michal Simek wrote: >> It has to be platform_device somewhere for sure. >> In past we had folder in arch/microblaze/platform folder. >> Currently you can add this code to for example >> arch/microblaze/kernel/platform.c >> >> But as I said I don't think it is really important. There will be a >> lot >> of others drivers in the kernel which can be used as platform drivers >> but you are not able to find out platform_device for it. > > Because, like probably happens with this driver, the OF infrastructure > makes sure the .probe and .remove functions will eventually called? > >> The important part is that driver can work as is. > > Sure. > > But I was talking about the MODULE_ALIAS() macro. Trivial as it is, > since I still don't see where a "MODALIAS=platform:xilinx-mailbox" > uevent could come from I still don't see the point of this line. As I > asked in my first message: what breaks if this line is dropped? TBH probably nothing because all will just use OF because it is just common for a long time on all xilinx platforms. > >> Also it is quite common that users create own BSP for their custom >> boards but they don't push it to mainline. > > I can't recall what BSP means. Anyhow, why should we care about boards > not pushed into mainline? I am not the right person to answer this in general. For SoC tree I maintain I tend to accept these patches if they are useful and definitely don't want to have support for various platforms. But having shared drivers is fine. For this case if Moritz tested OF and platform device probes and both work I am fine to keep it there. If only OF part is tested then I would remove this line. Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv5 2/2] mailbox: Adding driver for Xilinx LogiCORE IP mailbox.
On 06/25/2015 09:31 AM, Paul Bolle wrote:
> On Thu, 2015-06-25 at 08:55 +0200, Michal Simek wrote:
>> On 06/24/2015 10:36 PM, Paul Bolle wrote:
>>> On Tue, 2015-06-23 at 11:00 -0700, Moritz Fischer wrote:
>>>> +MODULE_ALIAS("platform:xilinx-mailbox");
>>>
>>> So I think this MODULE_ALIAS() is only useful if, in short, there's
>>> a corresponding platform_device created. Ie, a platform_device with
>>> a name "xilinx-mailbox" that will fire of a "MODALIAS=platform:xili
>>> nx-mailbox" when it's created.
>>>
>>> I couldn't spot such a platform_device. Provided git grep didn't
>>> let me down here: what breaks if this line is dropped?
>>
>> IRC you don't need to have this platform_device in the kernel
>> present. Only one thing which should be check is that this driver can
>> be used as platform device driver.
>>
>> The only one problematic part is devm_clk_get() and this should be
>> checked if you can use this as platform driver. From the first look
>> it looks like that this will break it.
>>
>> Anyway if Moritz is able to use this a platform driver he can keep
>> this line there. If not, it should be removed.
>
> But, assuming this works as a platform driver, where does the "xilinx
> -mailbox" platform device originate?
It has to be platform_device somewhere for sure.
In past we had folder in arch/microblaze/platform folder.
Currently you can add this code to for example
arch/microblaze/kernel/platform.c
But as I said I don't think it is really important. There will be a lot
of others drivers in the kernel which can be used as platform drivers
but you are not able to find out platform_device for it.
The important part is that driver can work as is.
Also it is quite common that users create own BSP for their custom
boards but they don't push it to mainline.
Thanks,
Michal
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Re: [PATCHv5 2/2] mailbox: Adding driver for Xilinx LogiCORE IP mailbox.
On 06/24/2015 10:36 PM, Paul Bolle wrote:
> On Tue, 2015-06-23 at 11:00 -0700, Moritz Fischer wrote:
>> +MODULE_ALIAS("platform:xilinx-mailbox");
>
> So I think this MODULE_ALIAS() is only useful if, in short, there's a
> corresponding platform_device created. Ie, a platform_device with a
> name "xilinx-mailbox" that will fire of a "MODALIAS=platform:xilinx
> -mailbox" when it's created.
>
> I couldn't spot such a platform_device. Provided git grep didn't let me
> down here: what breaks if this line is dropped?
IRC you don't need to have this platform_device in the kernel present.
Only one thing which should be check is that this driver can be used as
platform device driver.
The only one problematic part is devm_clk_get() and this should be
checked if you can use this as platform driver. From the first look it
looks like that this will break it.
Anyway if Moritz is able to use this a platform driver he can keep this
line there. If not, it should be removed.
Thanks,
Michal
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Re: [PATCHv5 2/2] mailbox: Adding driver for Xilinx LogiCORE IP mailbox.
On 06/23/2015 08:00 PM, Moritz Fischer wrote: > The Xilinx LogiCORE IP mailbox is a FPGA core that allows for > interprocessor communication via AXI4 memory mapped / AXI4 stream > interfaces. > > It is single channel per core and allows for transmit and receive. > > Changes from v4: > - Have separate mbox_ops structs for polling / irq mode > - Moved clk handling to startup / shutdown > - Embedded struct mbox_chan in struct xilinx_mbox > - Misc stylistic issues > > Changes from v3: > - Stylistic > > Changes from v2: > - Fixed error handling for IRQ from >= 0 to > 0 > - Fixed error handling for clock enabling > - Addressed Michal's stylistic comments > > Changes from v1: > - Added common clock framework support > - Deal with IRQs that happend before driver load, > since HW will not let us know about them when we enable IRQs > > Changes from v0: > - Several stylistic issues > - Dropped superfluous intr_mode member > - Really masking the IRQs on mailbox_shutdown > - No longer using polling by accident in non-IRQ mode > - Swapped doc and driver commits BTW: These change logs shouldn't be the part of commit. Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] devicetree: xilinx: zynqmp: add sata node
On 06/10/2015 12:16 PM, Suneel Garapati wrote:
> add sata node with sata fixed clock nodes in dtsi file.
> enable sata in zynqmp-ep108.dts with broken-gen2.
>
> Signed-off-by: Suneel Garapati
> ---
> Note -
> Driver and bindings are added via libata/for-4.2 tree
> bindings is found in Documentation/devicetree/bindings/ata/ahci-ceva.txt
> ---
> arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 5 +
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 15 +++
> 2 files changed, 20 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
> b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
> index 0a3f40e..981e594 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
> @@ -42,6 +42,11 @@
> };
> };
>
> +&sata {
> + status = "okay";
> + ceva,broken-gen2;
> +};
> +
> &uart0 {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index 11e0b00..e7545ed 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -272,6 +272,21 @@
> #size-cells = <0>;
> };
>
> + sata_clk: sata_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <7500>;
> + };
> +
> + sata0: ahci@fd0c {
> + compatible = "ceva,ahci-1v84";
> + status = "disabled";
> + reg = <0x0 0xfd0c 0x2000>;
> + interrupt-parent = <&gic>;
> + interrupts = <0 133 4>;
> + clocks = <&sata_clk>;
> + };
> +
> sdhci0: sdhci@ff16 {
> compatible = "arasan,sdhci-8.9a";
> status = "disabled";
> --
> 2.1.2
>
Reviewed-by: Michal Simek
Thanks,
Michal
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Re: [PATCH v2 2/2] drivers: ata: add support for Ceva sata host controller
)
> +#define PORT_SCTL_IPM(0x3 << 8)
> +
> +#define PORT_BASE0x100
> +#define PORT_OFFSET 0x80
> +#define NR_PORTS 2
> +#define DRV_NAME "ahci-ceva"
> +#define CEVA_FLAG_BROKEN_GEN21
> +
> +struct ceva_ahci_priv {
> + struct platform_device *ahci_pdev;
> + int flags;
> +};
> +
> +static struct ata_port_operations ahci_ceva_ops = {
> + .inherits = &ahci_platform_ops,
> +};
> +
> +static const struct ata_port_info ahci_ceva_port_info = {
> + .flags = AHCI_FLAG_COMMON,
> + .pio_mask = ATA_PIO4,
> + .udma_mask = ATA_UDMA6,
> + .port_ops = &ahci_ceva_ops,
> +};
> +
> +static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
> +{
> + void __iomem *mmio = hpriv->mmio;
> + struct ceva_ahci_priv *cevapriv = hpriv->plat_data;
> + u32 tmp;
> + int i;
> +
> + /*
> + * AXI Data bus width to 64
> + * Set Mem Addr Read, Write ID for data transfers
> + * Transfer limit to 72 DWord
> + */
> + tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
> + writel(tmp, mmio + AHCI_VEND_PAXIC);
> +
> + /* Set AHCI Enable */
> + tmp = readl(mmio + HOST_CTL);
> + tmp |= HOST_AHCI_EN;
> + writel(tmp, mmio + HOST_CTL);
> +
> + for (i = 0; i < NR_PORTS; i++) {
> + /* TPSS TPRS scalars, CISE and Port Addr */
> + tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
> + writel(tmp, mmio + AHCI_VEND_PCFG);
> +
> + /* Port Phy Cfg register enables */
> + tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
> + writel(tmp, mmio + AHCI_VEND_PPCFG);
> +
> + /* Phy Control OOB timing parameters COMINIT */
> + tmp = PP2C_CIBGMN | PP2C_CIBGMX | PP2C_CIBGN | PP2C_CINMP;
> + writel(tmp, mmio + AHCI_VEND_PP2C);
> +
> + /* Phy Control OOB timing parameters COMWAKE */
> + tmp = PP3C_CWBGMN | PP3C_CWBGMX | PP3C_CWBGN | PP3C_CWNMP;
> + writel(tmp, mmio + AHCI_VEND_PP3C);
> +
> + /* Phy Control Burst timing setting */
> + tmp = PP4C_BMX | PP4C_BNM | PP4C_SFD | PP4C_PTST;
> + writel(tmp, mmio + AHCI_VEND_PP4C);
> +
> + /* Rate Change Timer and Retry Interval Timer setting */
> + tmp = PP5C_RIT | PP5C_RCT;
> + writel(tmp, mmio + AHCI_VEND_PP5C);
> +
> + /* Rx Watermark setting */
> + tmp = PTC_RX_WM_VAL | PTC_RSVD;
> + writel(tmp, mmio + AHCI_VEND_PTC);
> +
> + /* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */
> + tmp = PORT_SCTL_SPD_GEN2 | PORT_SCTL_IPM;
> + if (cevapriv->flags & CEVA_FLAG_BROKEN_GEN2)
> + tmp = PORT_SCTL_SPD_GEN1 | PORT_SCTL_IPM;
> + writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
> + }
> +}
> +
> +static struct scsi_host_template ahci_platform_sht = {
> + AHCI_SHT(DRV_NAME),
> +};
> +
> +static int ceva_ahci_probe(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct device *dev = &pdev->dev;
> + struct ahci_host_priv *hpriv;
> + struct ceva_ahci_priv *cevapriv;
> +
> + cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL);
> + if (!cevapriv)
> + return -ENOMEM;
> +
> + cevapriv->ahci_pdev = pdev;
> +
> + hpriv = ahci_platform_get_resources(pdev);
> + if (IS_ERR(hpriv))
> + return PTR_ERR(hpriv);
> +
> + if (of_property_read_bool(np, "ceva,broken-gen2"))
> + cevapriv->flags = CEVA_FLAG_BROKEN_GEN2;
> +
> + hpriv->plat_data = cevapriv;
> +
> + /* CEVA specific initialization */
> + ahci_ceva_setup(hpriv);
> +
> + return ahci_platform_init_host(pdev, hpriv, &ahci_ceva_port_info,
> + &ahci_platform_sht);
> +}
> +
> +static int __maybe_unused ceva_ahci_suspend(struct device *dev)
> +{
> + return ahci_platform_suspend_host(dev);
> +}
> +
> +static int __maybe_unused ceva_ahci_resume(struct device *dev)
> +{
> + return ahci_platform_resume_host(dev);
> +}
> +
> +static SIMPLE_DEV_PM_OPS(ahci_ceva_pm_ops, ceva_ahci_suspend,
> ceva_ahci_resume);
> +
> +static const struct of_device_id ceva_ahci_of_match[] = {
> + { .compatible = "ceva,ahci-1v84" },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, ceva_ahci_of_match);
> +
> +static struct platform_driver ceva_ahci_driver = {
> + .probe = ceva_ahci_probe,
> + .remove = ata_platform_remove_one,
> + .driver = {
> + .name = DRV_NAME,
> + .of_match_table = ceva_ahci_of_match,
> + .pm = &ahci_ceva_pm_ops,
> + },
> +};
> +module_platform_driver(ceva_ahci_driver);
> +
> +MODULE_DESCRIPTION("CEVA AHCI SATA platform driver");
> +MODULE_AUTHOR("Xilinx Inc.");
> +MODULE_LICENSE("GPL v2");
> --
> 2.1.2
Tested-by: Michal Simek
Thanks,
Michal
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Maintainer of Linux kernel - Xilinx Zynq ARM architecture
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Re: [PATCH v2 1/2] devicetree:bindings: add devicetree bindings for ceva ahci
On 06/05/2015 08:02 AM, Suneel Garapati wrote:
> adds bindings for CEVA AHCI SATA controller. optional property
> broken-gen2 is useful incase of hardware speed limitation.
>
> Signed-off-by: Suneel Garapati
> ---
> Documentation/devicetree/bindings/ata/ahci-ceva.txt | 20
> 1 file changed, 20 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/ata/ahci-ceva.txt
>
> diff --git a/Documentation/devicetree/bindings/ata/ahci-ceva.txt
> b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
> new file mode 100644
> index 000..7ca8b97
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
> @@ -0,0 +1,20 @@
> +Binding for CEVA AHCI SATA Controller
> +
> +Required properties:
> + - reg: Physical base address and size of the controller's register area.
> + - compatible: Compatibility string. Must be 'ceva,ahci-1v84'.
> + - clocks: Input clock specifier. Refer to common clock bindings.
> + - interrupts: Interrupt specifier. Refer to interrupt binding.
> +
> +Optional properties:
> + - ceva,broken-gen2: limit to gen1 speed instead of gen2.
> +
> +Examples:
> + ahci@fd0c {
> + compatible = "ceva,ahci-1v84";
> + reg = <0xfd0c 0x200>;
> + interrupt-parent = <&gic>;
> + interrupts = <0 133 4>;
> + clocks = <&clkc SATA_CLK_ID>;
> + ceva,broken-gen2;
> + };
> --
> 2.1.2
Acked-by: Michal Simek
FYI: Adding ceva prefix to vendor-prefixes is already in arm-soc tree.
And
ceva,broken-gen2 targets hardware limitation.
Thanks,
Michal
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Re: [PATCH v2] gpio: Added GPIO support to Zynq Ultrascale+ MPSoC
K1_PIN_MIN(MP),
> + .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
> + .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
> + .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
> + .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
> + .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
> + .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
> + .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
> + .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
> + .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
> +};
> +
> +static const struct zynq_platform_data zynq_gpio_def = {
> + .label = "zynq_gpio",
> + .ngpio = ZYNQ_GPIO_NR_GPIOS,
> + .max_bank = ZYNQ_GPIO_MAX_BANK,
> + .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
> + .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
> + .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
> + .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
> + .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
> + .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
> + .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
> + .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
> +};
> +
> +static const struct of_device_id zynq_gpio_of_match[] = {
> + { .compatible = "xlnx,zynq-gpio-1.0", .data = (void *)&zynq_gpio_def },
> + { .compatible = "xlnx,zynqmp-gpio-1.0",
> + .data = (void *)&zynqmp_gpio_def },
> + { /* end of table */ }
> +};
> +MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
> +
> /**
> * zynq_gpio_probe - Initialization method for a zynq_gpio device
> * @pdev:platform device instance
> @@ -599,11 +657,18 @@ static int zynq_gpio_probe(struct platform_device *pdev)
> struct zynq_gpio *gpio;
> struct gpio_chip *chip;
> struct resource *res;
> + const struct of_device_id *match;
>
> gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
> if (!gpio)
> return -ENOMEM;
>
> + match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
> + if (!match) {
> + dev_err(&pdev->dev, "of_match_node() failed\n");
> + return -EINVAL;
> + }
> + gpio->p_data = match->data;
> platform_set_drvdata(pdev, gpio);
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> @@ -619,7 +684,7 @@ static int zynq_gpio_probe(struct platform_device *pdev)
>
> /* configure the gpio chip */
> chip = &gpio->chip;
> - chip->label = "zynq_gpio";
> + chip->label = gpio->p_data->label;
> chip->owner = THIS_MODULE;
> chip->dev = &pdev->dev;
> chip->get = zynq_gpio_get_value;
> @@ -629,7 +694,7 @@ static int zynq_gpio_probe(struct platform_device *pdev)
> chip->direction_input = zynq_gpio_dir_in;
> chip->direction_output = zynq_gpio_dir_out;
> chip->base = -1;
> - chip->ngpio = ZYNQ_GPIO_NR_GPIOS;
> + chip->ngpio = gpio->p_data->ngpio;
>
> /* Enable GPIO clock */
> gpio->clk = devm_clk_get(&pdev->dev, NULL);
> @@ -651,7 +716,7 @@ static int zynq_gpio_probe(struct platform_device *pdev)
> }
>
> /* disable interrupts for all banks */
> - for (bank_num = 0; bank_num < ZYNQ_GPIO_MAX_BANK; bank_num++)
> + for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)
> writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
> ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
>
> @@ -695,12 +760,6 @@ static int zynq_gpio_remove(struct platform_device *pdev)
> return 0;
> }
>
> -static struct of_device_id zynq_gpio_of_match[] = {
> - { .compatible = "xlnx,zynq-gpio-1.0", },
> - { /* end of table */ }
> -};
> -MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
> -
> static struct platform_driver zynq_gpio_driver = {
> .driver = {
> .name = DRIVER_NAME,
>
Acked-by: Michal Simek
Thanks,
Michal
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Re: [PATCH v2] ARM: l2c: Add support for the "arm, shared-override" property
On 05/15/2015 03:55 PM, Catalin Marinas wrote:
> On Fri, May 15, 2015 at 11:10:28AM +0100, Russell King - ARM Linux wrote:
>> On Thu, May 07, 2015 at 05:02:57PM +0100, Catalin Marinas wrote:
>>> On Thu, May 07, 2015 at 11:27:11AM +0200, Geert Uytterhoeven wrote:
>>>> diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt
>>>> b/Documentation/devicetree/bindings/arm/l2cc.txt
>>>> index 0dbabe9a6b0abb91..2484aed78c86546d 100644
>>>> --- a/Documentation/devicetree/bindings/arm/l2cc.txt
>>>> +++ b/Documentation/devicetree/bindings/arm/l2cc.txt
>>>> @@ -67,6 +67,12 @@ Optional properties:
>>>>disable if zero.
>>>> - arm,prefetch-offset : Override prefetch offset value. Valid values are
>>>>0-7, 15, 23, and 31.
>>>> +- arm,shared-override : The default behavior of the pl310 cache
>>>> controller with
>>>> + respect to the shareable attribute is to transform "normal memory
>>>> + non-cacheable transactions" into "cacheable no allocate" (for reads) or
>>>> + "write through no write allocate" (for writes).
>>>> + On systems where this may cause DMA buffer corruption, this property
>>>> must be
>>>> + specified to indicate that such transforms are precluded.
>>>>
>>>> Example:
>>>>
>>>> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
>>>> index e309c8f35af5af61..86d0e7461e5b0b18 100644
>>>> --- a/arch/arm/mm/cache-l2x0.c
>>>> +++ b/arch/arm/mm/cache-l2x0.c
>>>> @@ -1149,6 +1149,11 @@ static void __init l2c310_of_parse(const struct
>>>> device_node *np,
>>>>}
>>>>}
>>>>
>>>> + if (of_property_read_bool(np, "arm,shared-override")) {
>>>> + *aux_val |= L2C_AUX_CTRL_SHARED_OVERRIDE;
>>>> + *aux_mask &= ~L2C_AUX_CTRL_SHARED_OVERRIDE;
>>>> + }
>>>> +
>>>>prefetch = l2x0_saved_regs.prefetch_ctrl;
>>>>
>>>>ret = of_property_read_u32(np, "arm,double-linefill", &val);
>>>
>>> It looks fine to me.
>>>
>>> Acked-by: Catalin Marinas
>>>
>>> (even better if a subsequent patch adds this property to all the dts
>>> files containing "arm,pl310" ;))
>>
>> Even better would be for the boot loader/firmware to set the bit.
>
> In an ideal world, I agree. But, arguably, we already set other bits in
> the PL310 AUXCTRL register (and related cache controllers, just look at
> the l2cc.txt bindings).
>
> If you want to rely on firmware, can we at least check this bit and
> print a warning? Or go a step further and refuse to enable PL310 when
> this bit is clear? Otherwise coherent (non-cacheable) DMA operations are
> not safe.
>
Any update on this one? I have the patch for Zynq pending and I want to
have any resolution on this in this generic way or simply by enabling it
via aux_mask as is here.
https://lkml.org/lkml/2015/5/12/51
This patch can be reverted when this generic solution reach mainline.
Thanks,
Michal
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Re: [PATCHv3 2/2] mailbox: Adding driver for Xilinx LogiCORE IP mailbox.
;
> + u32 *udata = (u32 *)data;
> +
> + if (!mbox || !data)
> + return -EINVAL;
> +
> + if (xilinx_mbox_full(mbox))
> + return -EBUSY;
> +
> + /* enable interrupt before send */
> + if (mbox->irq >= 0)
> + xilinx_mbox_tx_intmask(mbox, true);
> +
> + writel_relaxed(*udata, mbox->mbox_base + MAILBOX_REG_WRDATA);
> +
> + return 0;
> +}
> +
> +static bool xilinx_mbox_last_tx_done(struct mbox_chan *chan)
> +{
> + struct xilinx_mbox *mbox = mbox_chan_to_xilinx_mbox(chan);
> +
> + /* return false if mailbox is full */
> + return !xilinx_mbox_full(mbox);
> +}
> +
> +static bool xilinx_mbox_peek_data(struct mbox_chan *chan)
> +{
> + struct xilinx_mbox *mbox = mbox_chan_to_xilinx_mbox(chan);
> +
> + return xilinx_mbox_pending(mbox);
> +}
> +
> +static void xilinx_mbox_shutdown(struct mbox_chan *chan)
> +{
> + struct xilinx_mbox *mbox = mbox_chan_to_xilinx_mbox(chan);
> +
> + if (mbox->irq > 0) {
> + /* mask all interrupts */
> + writel_relaxed(0, mbox->mbox_base + MAILBOX_REG_IE);
> + free_irq(mbox->irq, chan);
> + } else {
> + del_timer_sync(&mbox->rxpoll_timer);
> + }
> +}
> +
> +static struct mbox_chan_ops xilinx_mbox_ops = {
> + .send_data = xilinx_mbox_send_data,
> + .startup = xilinx_mbox_startup,
> + .shutdown = xilinx_mbox_shutdown,
> + .last_tx_done = xilinx_mbox_last_tx_done,
> + .peek_data = xilinx_mbox_peek_data,
> +};
> +
> +static int xilinx_mbox_probe(struct platform_device *pdev)
> +{
> + struct xilinx_mbox *mbox;
> + struct resource *regs;
> + struct mbox_chan *chans;
> + int ret;
> +
> + mbox = devm_kzalloc(&pdev->dev, sizeof(*mbox), GFP_KERNEL);
> + if (!mbox)
> + return -ENOMEM;
> +
> + /* get clk and enable */
> + mbox->clk = devm_clk_get(&pdev->dev, "mbox");
> + if (IS_ERR(mbox->clk)) {
> + dev_err(&pdev->dev, "Couldn't get clk.\n");
> + return PTR_ERR(mbox->clk);
> + }
> +
> + /* allocated one channel */
> + chans = devm_kzalloc(&pdev->dev, sizeof(*chans), GFP_KERNEL);
> + if (!chans)
> + return -ENOMEM;
> +
> + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +
> + mbox->mbox_base = devm_ioremap_resource(&pdev->dev, regs);
> + if (IS_ERR(mbox->mbox_base))
> + return PTR_ERR(mbox->mbox_base);
> +
> + mbox->irq = platform_get_irq(pdev, 0);
> + /* if irq is present, we can use it, otherwise, poll */
> + if (mbox->irq > 0) {
> + mbox->controller.txdone_irq = true;
> + } else {
> + dev_info(&pdev->dev, "IRQ not found, fallback to polling.\n");
> + mbox->controller.txdone_poll = true;
> + mbox->controller.txpoll_period = MBOX_POLLING_MS;
> + }
> +
> + mbox->dev = &pdev->dev;
> +
> + /* hardware supports only one channel. */
> + chans[0].con_priv = mbox;
> + mbox->controller.dev = mbox->dev;
> + mbox->controller.num_chans = 1;
> + mbox->controller.chans = chans;
> + mbox->controller.ops = &xilinx_mbox_ops;
> +
> +
only one empty line here but otherwise
Acked-by: Michal Simek
Thanks,
Michal
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Re: [PATCHv3 1/2] dts: Adding docs for Xilinx LogiCORE IP mailbox driver.
On 05/28/2015 11:52 PM, Moritz Fischer wrote:
> Changes from v2:
> - Addressed Michal's stylistic comments
> - Fixed typo in compatible string
>
> Changes from v1:
> - Added common clock framework support
>
> Changes from v0:
> - Fixed example bindings
>
> Signed-off-by: Moritz Fischer
> ---
> .../bindings/mailbox/xilinx-mailbox.txt | 44
> 1 file changed, 44 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mailbox/xilinx-mailbox.txt
> b/Documentation/devicetree/bindings/mailbox/xilinx-mailbox.txt
> new file mode 100644
> index 000..ca76efd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/xilinx-mailbox.txt
> @@ -0,0 +1,44 @@
> +Xilinx Mailbox Driver
> +=
> +
> +Required properties:
> +- compatible : "xlnx,mailbox-2.1".
> +- reg : physical base address of the mailbox and length of
> + memory mapped region.
> +- #mbox-cells : common mailbox binding property to identify the number
> + of cells required for the mailbox specifier, should be
> 1
> +- clocks : phandle to clock provider
> +- clock-names : must be 'mbox'
> +
> +Optional properties:
> +- interrupt-parent : interrupt source phandle
> +- interrupts : interrupt number, The interrupt specifier format
> + depends on the interrupt controller parent.
> +
> +Example:
> + mbox: mailbox@4040 {
> + compatible = "xlnx,mailbox-2.1";
> + reg = <0x4040 0x3c>;
> + interrupt-parent = <&intc>;
> + interrupts = <5>;
> + #mbox-cells = <1>;
> + clocks = <&clkc 15>;
> + clock-names = "mbox";
> + };
> +
> +Mailbox client
> +===
> +"mboxes" and the optional "mbox-names" (please see
> +Documentation/devicetree/bindings/mailbox/mailbox.txt for details). Each
> value
> +of the mboxes property should contain a phandle to the mailbox controller
> +device node and second argument is the channel index. It must be 0 (hardware
> +support only one channel). The equivalent "mbox-names" property value can be
> +used to give a name to the communication channel to be used by the client
> user.
> +
> +Example:
> + mclient0: mclient0@400 {
> + compatible = "client-1.0";
> + reg = <0x400 0x10>;
> + mbox-names = "mbox";
> + mboxes = <&mbox 0>;
> + };
>
I see you still keep there 0x3c but that's minor detail.
Acked-by: Michal Simek
Thanks,
Michal
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Re: [PATCHv2 2/2] mailbox: Adding driver for Xilinx LogiCORE IP mailbox.
On 05/28/2015 07:35 PM, Moritz Fischer wrote: > On Wed, May 27, 2015 at 10:45 PM, Michal Simek > wrote: >> On 05/27/2015 08:35 PM, Moritz Fischer wrote: >>> The Xilinx LogiCORE IP mailbox is a FPGA core that allows for >>> interprocessor communication via AXI4 memory mapped / AXI4 stream >>> interfaces. >>> >>> It is single channel per core and allows for transmit and receive. >>> >>> Changes from v1: >>> - Added common clock framework support >>> - Deal with IRQs that happend before driver load, >>> since HW will not let us know about them when we enable IRQs >>> >>> Changes from v0: >>> - Several stylistic issues >>> - Dropped superfluous intr_mode member >>> - Really masking the IRQs on mailbox_shutdown >>> - No longer using polling by accident in non-IRQ mode >>> - Swapped doc and driver commits >>> >>> Signed-off-by: Moritz Fischer >>> --- >>> MAINTAINERS | 7 + >>> drivers/mailbox/Kconfig | 8 + >>> drivers/mailbox/Makefile | 2 + >>> drivers/mailbox/mailbox-xilinx.c | 349 ++ >>> 4 files changed, 366 insertions(+) >>> >>> diff --git a/MAINTAINERS b/MAINTAINERS >>> index f8e0afb..f1f0d10 100644 >>> --- a/MAINTAINERS >>> +++ b/MAINTAINERS >>> @@ -10986,6 +10986,13 @@ M: John Linn >>> S: Maintained >>> F: drivers/net/ethernet/xilinx/xilinx_axienet* >>> >>> +XILINX MAILBOX DRIVER >>> +M: Moritz Fischer >>> +L: linux-ker...@vger.kernel.org >>> +S: Maintained >>> +F: drivers/mailbox/mailbox-xilinx.c >>> +F: Documentation/devicetree/bindings/mailbox/xilinx-mailbox.txt >>> + >>> XILINX UARTLITE SERIAL DRIVER >>> M: Peter Korsgaard >>> L: linux-ser...@vger.kernel.org >>> diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig >>> index 84b0a2d..e11e4b2 100644 >>> --- a/drivers/mailbox/Kconfig >>> +++ b/drivers/mailbox/Kconfig >>> @@ -60,4 +60,12 @@ config ALTERA_MBOX >>> An implementation of the Altera Mailbox soft core. It is used >>> to send message between processors. Say Y here if you want to use >>> the >>> Altera mailbox support. >>> + >>> +config XILINX_MBOX >>> + tristate "Xilinx Mailbox" >>> + help >>> + An implementation of the Xilinx Mailbox soft core. It is used >>> + to send message between processors. Say Y here if you want to use >>> the >>> + Xilinx mailbox support. >>> + >>> endif >>> diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile >>> index b18201e..d28a028 100644 >>> --- a/drivers/mailbox/Makefile >>> +++ b/drivers/mailbox/Makefile >>> @@ -11,3 +11,5 @@ obj-$(CONFIG_OMAP2PLUS_MBOX)+= omap-mailbox.o >>> obj-$(CONFIG_PCC)+= pcc.o >>> >>> obj-$(CONFIG_ALTERA_MBOX)+= mailbox-altera.o >>> + >>> +obj-$(CONFIG_XILINX_MBOX)+= mailbox-xilinx.o >>> diff --git a/drivers/mailbox/mailbox-xilinx.c >>> b/drivers/mailbox/mailbox-xilinx.c >>> new file mode 100644 >>> index 000..fd1cdf2 >>> --- /dev/null >>> +++ b/drivers/mailbox/mailbox-xilinx.c >>> @@ -0,0 +1,349 @@ >>> +/* >>> + * Copyright (c) 2015, National Instruments Corp. All rights reserved. >>> + * >>> + * Driver for the Xilinx LogiCORE mailbox IP block >>> + * >>> + * This program is free software; you can redistribute it and/or modify >>> + * it under the terms of the GNU General Public License as published by >>> + * the Free Software Foundation; version 2 of the License. >>> + * >>> + * This program is distributed in the hope that it will be useful, >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >>> + * GNU General Public License for more details. >>> + */ >>> + >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> + >>> +#define DRIVER_NAME "xilinx-mailbox" >>> + >>> +/* register offsets */ >>> +#define MAILBOX_REG_WRDATA 0x00 >>> +#define
Re: [PATCH v3] ARM: zynq: DT: Use the zynq binding with macb
On 05/27/2015 10:52 PM, Sören Brinkmann wrote: > On Wed, 2015-05-27 at 03:00PM -0500, Nathan Sullivan wrote: >> Use the new zynq binding for macb ethernet, since it will disable half >> duplex gigabit like the Zynq TRM says to do. Also allow the compatible >> cadence gem binding that won't disable half duplex but works otherwise. >> >> Signed-off-by: Nathan Sullivan > > Assuming that the corresponding patch(es) for the driver and DT docs > went through: > Acked-by: Sören Brinkmann > >> --- > > For future reference, please include a changelog here documenting what > changes between patch iterations. Applied and send in my PR. Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 2/2] mailbox: Adding driver for Xilinx LogiCORE IP mailbox.
On 05/27/2015 08:35 PM, Moritz Fischer wrote:
> The Xilinx LogiCORE IP mailbox is a FPGA core that allows for
> interprocessor communication via AXI4 memory mapped / AXI4 stream
> interfaces.
>
> It is single channel per core and allows for transmit and receive.
>
> Changes from v1:
> - Added common clock framework support
> - Deal with IRQs that happend before driver load,
> since HW will not let us know about them when we enable IRQs
>
> Changes from v0:
> - Several stylistic issues
> - Dropped superfluous intr_mode member
> - Really masking the IRQs on mailbox_shutdown
> - No longer using polling by accident in non-IRQ mode
> - Swapped doc and driver commits
>
> Signed-off-by: Moritz Fischer
> ---
> MAINTAINERS | 7 +
> drivers/mailbox/Kconfig | 8 +
> drivers/mailbox/Makefile | 2 +
> drivers/mailbox/mailbox-xilinx.c | 349 ++
> 4 files changed, 366 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index f8e0afb..f1f0d10 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -10986,6 +10986,13 @@ M: John Linn
> S: Maintained
> F: drivers/net/ethernet/xilinx/xilinx_axienet*
>
> +XILINX MAILBOX DRIVER
> +M: Moritz Fischer
> +L: linux-ker...@vger.kernel.org
> +S: Maintained
> +F: drivers/mailbox/mailbox-xilinx.c
> +F: Documentation/devicetree/bindings/mailbox/xilinx-mailbox.txt
> +
> XILINX UARTLITE SERIAL DRIVER
> M: Peter Korsgaard
> L: linux-ser...@vger.kernel.org
> diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
> index 84b0a2d..e11e4b2 100644
> --- a/drivers/mailbox/Kconfig
> +++ b/drivers/mailbox/Kconfig
> @@ -60,4 +60,12 @@ config ALTERA_MBOX
> An implementation of the Altera Mailbox soft core. It is used
> to send message between processors. Say Y here if you want to use the
> Altera mailbox support.
> +
> +config XILINX_MBOX
> + tristate "Xilinx Mailbox"
> + help
> + An implementation of the Xilinx Mailbox soft core. It is used
> + to send message between processors. Say Y here if you want to use the
> + Xilinx mailbox support.
> +
> endif
> diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
> index b18201e..d28a028 100644
> --- a/drivers/mailbox/Makefile
> +++ b/drivers/mailbox/Makefile
> @@ -11,3 +11,5 @@ obj-$(CONFIG_OMAP2PLUS_MBOX)+= omap-mailbox.o
> obj-$(CONFIG_PCC)+= pcc.o
>
> obj-$(CONFIG_ALTERA_MBOX)+= mailbox-altera.o
> +
> +obj-$(CONFIG_XILINX_MBOX)+= mailbox-xilinx.o
> diff --git a/drivers/mailbox/mailbox-xilinx.c
> b/drivers/mailbox/mailbox-xilinx.c
> new file mode 100644
> index 000..fd1cdf2
> --- /dev/null
> +++ b/drivers/mailbox/mailbox-xilinx.c
> @@ -0,0 +1,349 @@
> +/*
> + * Copyright (c) 2015, National Instruments Corp. All rights reserved.
> + *
> + * Driver for the Xilinx LogiCORE mailbox IP block
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define DRIVER_NAME "xilinx-mailbox"
> +
> +/* register offsets */
> +#define MAILBOX_REG_WRDATA 0x00
> +#define MAILBOX_REG_RDDATA 0x08
> +#define MAILBOX_REG_STATUS 0x10
> +#define MAILBOX_REG_ERROR0x14
> +#define MAILBOX_REG_SIT 0x18
> +#define MAILBOX_REG_RIT 0x1c
> +#define MAILBOX_REG_IS 0x20
> +#define MAILBOX_REG_IE 0x24
> +#define MAILBOX_REG_IP 0x28
> +
> +/* status register */
> +#define STS_RTA BIT(3)
> +#define STS_STA BIT(2)
> +#define STS_FULL BIT(1)
> +#define STS_EMPTYBIT(0)
> +
> +/* error register */
> +#define ERR_FULL BIT(1)
> +#define ERR_EMPTYBIT(0)
> +
> +/* mailbox interrupt status register */
> +#define INT_STATUS_ERR BIT(2)
> +#define INT_STATUS_RTI BIT(1)
> +#define INT_STATUS_STI BIT(0)
> +
> +/* mailbox interrupt enable register */
> +#define INT_ENABLE_ERR BIT(2)
> +#define INT_ENABLE_RTI BIT(1)
> +#define INT_ENABLE_STI BIT(0)
> +
> +#define MBOX_POLLING_MS 5 /* polling interval 5ms */
> +
> +struct xilinx_mbox {
> + int irq;
> + void __iomem *mbox_base;
> + struct clk *clk;
> + struct device *dev;
> + struct mbox_controller controller;
> +
> + /* if the controller supports only RX polling mode */
> + struct timer_list rxpoll_timer;
> +};
> +
> +static struct xilinx_mbox *mbox_chan_to_xilinx_mbox(struct mbox_chan *chan)
> +{
> + if (!chan || !chan->con_priv)
> +
Re: [PATCHv2 1/2] dts: Adding docs for Xilinx LogiCORE IP mailbox driver.
On 05/27/2015 08:35 PM, Moritz Fischer wrote:
> Changes from v1:
> - Added common clock framework support
>
> Changes from v0:
> - Fixed example bindings
>
> Signed-off-by: Moritz Fischer
> ---
> .../bindings/mailbox/xilinx-mailbox.txt | 44
> 1 file changed, 44 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mailbox/xilinx-mailbox.txt
> b/Documentation/devicetree/bindings/mailbox/xilinx-mailbox.txt
> new file mode 100644
> index 000..50d0e5c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/xilinx-mailbox.txt
> @@ -0,0 +1,44 @@
> +Xilinx Mailbox Driver
> +=
> +
> +Required properties:
> +- compatible : "xlnx,mailbox-2.1".
> +- reg : physical base address of the mailbox and length of
> + memory mapped region.
remove dot at the end - it is not a sentence.
> +- #mbox-cells : Common mailbox binding property to identify the number
> + of cells required for the mailbox specifier. Should be
> 1.
use small letters as you use in the whole description and remove dots.
> +- clocks : phandle to clock provider
> +- clock-names : must be 'mbox'
> +
> +Optional properties:
> +- interrupt-parent : interrupt source phandle.
> +- interrupts : interrupt number. The interrupt specifier format
> + depends on the interrupt controller parent.
> +
> +Example:
> + mbox: mailbox@4040 {
> + compatible = "xlnx,axi-mailbox-2.1";
> + reg = <0x4040 0x3c>;
It is just example but I don't think that you can select in vivado size
only 0x3c. That's actual size of regs right?
Thanks,
Michal
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Re: [PATCHv1 0/2] Adding driver for Xilinx LogiCORE IP mailbox.
On 05/26/2015 06:12 PM, Moritz Fischer wrote: > On Mon, May 25, 2015 at 6:56 AM, Jingoo Han wrote: >> On Monday, May 25, 2015 3:05 PM, Michal Simek wrote: >>> On 05/22/2015 08:03 PM, Moritz Fischer wrote: >>>> This patchset adds mailbox framework integration for the Xilinx LogiCORE IP >>>> mailbox. The Xilinx LogiCORE IP mailbox is a fpga softcore that allows >>>> interprocessor communication between AXI4 stream / memory mapped >>>> processors. >>>> >>>> Changes from v0: >>>> - >>>> >>>> - Several stylistic issues >>>> - Dropped superfluous intr_mode member >>>> - Really masking the IRQs on mailbox_shutdown >>>> - No longer using polling by accident in non-IRQ mode >>>> - Swapped doc and driver commits >>> >>> Changes update should be in every particular patch. >>> Also v1 is used to the first version that's why this one should be v2. > > > Thanks for the feedback. I guess making the next round v2 would be > less confusing, > than restarting the entire patchset from v1? yep. v2 make sense. Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv1 0/2] Adding driver for Xilinx LogiCORE IP mailbox.
On 05/22/2015 08:03 PM, Moritz Fischer wrote: > This patchset adds mailbox framework integration for the Xilinx LogiCORE IP > mailbox. The Xilinx LogiCORE IP mailbox is a fpga softcore that allows > interprocessor communication between AXI4 stream / memory mapped > processors. > > Changes from v0: > - > > - Several stylistic issues > - Dropped superfluous intr_mode member > - Really masking the IRQs on mailbox_shutdown > - No longer using polling by accident in non-IRQ mode > - Swapped doc and driver commits Changes update should be in every particular patch. Also v1 is used to the first version that's why this one should be v2. Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] mailbox: Adding driver for Xilinx LogiCORE IP mailbox.
On 05/22/2015 01:37 AM, Moritz Fischer wrote:
> The Xilinx LogiCORE IP mailbox is a FPGA core that allows for
> interprocessor communication via AXI4 memory mapped / AXI4 stream
> interfaces.
>
> It is single channel per core and allows for transmit and receive.
>
> Signed-off-by: Moritz Fischer
> ---
> drivers/mailbox/Kconfig | 8 +
> drivers/mailbox/Makefile | 2 +
> drivers/mailbox/mailbox-xilinx.c | 339 ++
> 3 files changed, 349 insertions(+)
>
> diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
> index 84b0a2d..e11e4b2 100644
> --- a/drivers/mailbox/Kconfig
> +++ b/drivers/mailbox/Kconfig
> @@ -60,4 +60,12 @@ config ALTERA_MBOX
> An implementation of the Altera Mailbox soft core. It is used
> to send message between processors. Say Y here if you want to use the
> Altera mailbox support.
> +
> +config XILINX_MBOX
> + tristate "Xilinx Mailbox"
> + help
> + An implementation of the Xilinx Mailbox soft core. It is used
> + to send message between processors. Say Y here if you want to use the
> + Xilinx mailbox support.
> +
> endif
> diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
> index b18201e..d28a028 100644
> --- a/drivers/mailbox/Makefile
> +++ b/drivers/mailbox/Makefile
> @@ -11,3 +11,5 @@ obj-$(CONFIG_OMAP2PLUS_MBOX)+= omap-mailbox.o
> obj-$(CONFIG_PCC)+= pcc.o
>
> obj-$(CONFIG_ALTERA_MBOX)+= mailbox-altera.o
> +
> +obj-$(CONFIG_XILINX_MBOX)+= mailbox-xilinx.o
> diff --git a/drivers/mailbox/mailbox-xilinx.c
> b/drivers/mailbox/mailbox-xilinx.c
> new file mode 100644
> index 000..8d8aa17
> --- /dev/null
> +++ b/drivers/mailbox/mailbox-xilinx.c
> @@ -0,0 +1,339 @@
> +/*
> + * Copyright (c) 2015, National Instruments Corp. All rights reserved.
> + *
> + * Driver for the Xilinx Logicore mailbox IP block
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define DRIVER_NAME "xilinx-mailbox"
> +
> +/* register offsets */
> +#define MAILBOX_REG_WRDATA 0x00
I prefer to use #definemacro_namevalue
but up to you.
> +#define MAILBOX_REG_RDDATA 0x08
> +#define MAILBOX_REG_STATUS 0x10
> +#define MAILBOX_REG_ERROR 0x14
> +#define MAILBOX_REG_SIT 0x18
> +#define MAILBOX_REG_RIT 0x1c
> +#define MAILBOX_REG_IS 0x20
> +#define MAILBOX_REG_IE 0x24
> +#define MAILBOX_REG_IP 0x28
> +
> +/* status register */
> +#define STS_RTA BIT(3)
> +#define STS_STA BIT(2)
> +#define STS_FULL BIT(1)
> +#define STS_EMPTY BIT(0)
> +
> +/* error register */
> +#define ERR_FULL BIT(1)
> +#define ERR_EMPTY BIT(0)
> +
> +/* mailbox interrupt status register */
> +#define INT_STATUS_ERR BIT(2)
> +#define INT_STATUS_RTI BIT(1)
> +#define INT_STATUS_STI BIT(0)
> +
> +/* mailbox interrupt enable register */
> +#define INT_ENABLE_ERR BIT(2)
> +#define INT_ENABLE_RTI BIT(1)
> +#define INT_ENABLE_STI BIT(0)
> +
> +#define MBOX_POLLING_MS 5 /* polling interval 5ms */
and you are using tab here - it looks like c&p from somewhere. :-)
> +
> +struct xilinx_mbox {
> + bool intr_mode;
look below.
> + int irq;
> + void __iomem *mbox_base;
> + struct device *dev;
> + struct mbox_controller controller;
> +
> + /* if the controller supports only RX polling mode */
> + struct timer_list rxpoll_timer;
> +};
> +
> +static struct xilinx_mbox *mbox_chan_to_xilinx_mbox(struct mbox_chan *chan)
> +{
> + if (!chan || !chan->con_priv)
> + return NULL;
> +
> + return (struct xilinx_mbox *)chan->con_priv;
> +}
> +
> +static inline int xilinx_mbox_full(struct xilinx_mbox *mbox)
> +{
> + u32 status;
> +
> + status = readl_relaxed(mbox->mbox_base + MAILBOX_REG_STATUS);
empty line here please for easier reading.
> + return status & STS_FULL;
> +}
> +
> +static inline int xilinx_mbox_pending(struct xilinx_mbox *mbox)
> +{
> + u32 status;
> +
> + status = readl_relaxed(mbox->mbox_base + MAILBOX_REG_STATUS);
ditto.
> + return !(status & STS_EMPTY);
> +}
> +
> +static void xilinx_mbox_rx_intmask(struct xilinx_mbox *mbox, bool enable)
> +{
> + u32 mask;
> +
> + mask = readl_relaxed(mbox->mbox_base + MAILBOX_REG_IE);
> + if (enable)
> + mask |= INT_ENABLE_RTI;
> + else
> + mask &= ~INT_ENABLE_RTI;
> + writel_relaxed(mask, mbox->mbox_base + MAILBOX_REG_IE);
> +}
> +
> +static void xilinx_mbox_tx_intmask(struct xilinx_mbox
Re: [PATCH 2/3] dts: Adding docs for Xilinx LogiCORE IP mailbox driver.
On 05/22/2015 01:37 AM, Moritz Fischer wrote:
> Signed-off-by: Moritz Fischer
> ---
> .../bindings/mailbox/xilinx-mailbox.txt | 40
> 1 file changed, 40 insertions(+)
>
IRC the rule was to send binding first and then the driver.
> diff --git a/Documentation/devicetree/bindings/mailbox/xilinx-mailbox.txt
> b/Documentation/devicetree/bindings/mailbox/xilinx-mailbox.txt
> new file mode 100644
> index 000..e559743
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/xilinx-mailbox.txt
> @@ -0,0 +1,40 @@
> +Xilinx Mailbox Driver
> +=
> +
> +Required properties:
> +- compatible : "xlnx,mailbox-2.1".
> +- reg : physical base address of the mailbox and length of
> + memory mapped region.
> +- #mbox-cells: Common mailbox binding property to identify the number
> + of cells required for the mailbox specifier. Should be 1.
> +
> +Optional properties:
> +- interrupt-parent : interrupt source phandle.
> +- interrupts : interrupt number. The interrupt specifier format
please be consistent with spacing around :. It doesn't look nice.
> + depends on the interrupt controller parent.
> +
> +Example:
> + mbox: mailbox@0x4040 {
remove 0x prefix here.
> + compatible = "xlnx,axi-mailbox-2.1";
> + reg = <0x100 0x3c>;
This is weird - it should start with 4040.
Or is your physical address 0x100?
> + interrupt-parent = <&intc>;
> + interrupts = <5>;
> + #mbox-cells = <1>;
> + };
> +
> +Mailbox client
> +===
> +"mboxes" and the optional "mbox-names" (please see
> +Documentation/devicetree/bindings/mailbox/mailbox.txt for details). Each
> value
> +of the mboxes property should contain a phandle to the mailbox controller
> +device node and second argument is the channel index. It must be 0 (hardware
> +support only one channel).The equivalent "mbox-names" property value can be
.The
> +used to give a name to the communication channel to be used by the client
> user.
> +
> +Example:
> + mclient0: mclient0@0x400 {
ditto.
> + compatible = "client-1.0";
> + reg = <0x400 0x10>;
> + mbox-names = "mbox", "mbox-rx";
> + mboxes = <&mbox 0>;
> + };
>
Thanks,
Michal
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Re: [PATCH 3/3] MAINTAINERS: Add entry for xilinx mailbox driver.
On 05/22/2015 01:37 AM, Moritz Fischer wrote: > Signed-off-by: Moritz Fischer > --- > MAINTAINERS | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index f8e0afb..f1f0d10 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -10986,6 +10986,13 @@ M: John Linn > S: Maintained > F: drivers/net/ethernet/xilinx/xilinx_axienet* > > +XILINX MAILBOX DRIVER > +M: Moritz Fischer > +L: linux-ker...@vger.kernel.org > +S: Maintained > +F: drivers/mailbox/mailbox-xilinx.c > +F: Documentation/devicetree/bindings/mailbox/xilinx-mailbox.txt > + > XILINX UARTLITE SERIAL DRIVER > M: Peter Korsgaard > L: linux-ser...@vger.kernel.org > Add it directly to the driver patch. Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] mtd: nand: Add support for Arasan Nand Flash Controller
On 04/16/2015 03:56 PM, Punnaiah Choudary Kalluri wrote: > Added the basic driver for Arasan Nand Flash Controller used in > Zynq UltraScale+ MPSoC. It supports only Hw Ecc and upto 24bit > correction. > > Signed-off-by: Punnaiah Choudary Kalluri > --- > drivers/mtd/nand/Kconfig |7 + > drivers/mtd/nand/Makefile |1 + > drivers/mtd/nand/arasan_nfc.c | 861 > + > 3 files changed, 869 insertions(+), 0 deletions(-) > create mode 100644 drivers/mtd/nand/arasan_nfc.c > > diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig > index 5897d8d..64e497c 100644 > --- a/drivers/mtd/nand/Kconfig > +++ b/drivers/mtd/nand/Kconfig > @@ -530,4 +530,11 @@ config MTD_NAND_HISI504 > help > Enables support for NAND controller on Hisilicon SoC Hip04. > > +config MTD_NAND_ARASAN > + tristate "Support for Arasan Nand Flash controller" > + depends on MTD_NAND > + help > + Enables the driver for the Arasan Nand Flash controller on > + Zynq UltraScale+ MPSoC. > + > endif # MTD_NAND > diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile > index 582bbd05..fd863ea 100644 > --- a/drivers/mtd/nand/Makefile > +++ b/drivers/mtd/nand/Makefile > @@ -52,5 +52,6 @@ obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o > obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/ > obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o > obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o > +obj-$(CONFIG_MTD_NAND_ARASAN)+= arasan_nfc.o > > nand-objs := nand_base.o nand_bbt.o nand_timings.o > diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c > new file mode 100644 > index 000..a4b407b > --- /dev/null > +++ b/drivers/mtd/nand/arasan_nfc.c > @@ -0,0 +1,861 @@ > +/* > + * Arasan Nand Flash Controller Driver > + * > + * Copyright (C) 2014 - 2015 Xilinx, Inc. > + * > + * This program is free software; you can redistribute it and/or modify it > under > + * the terms of the GNU General Public License version 2 as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include For !CONFIG_OF_MTD here should be also. Kbuild system just reported this problem. #include For the rest Tested-by: Michal Simek Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
[PATCH] of: Add vendor prefix for Ceva
Signed-off-by: Michal Simek --- http://www.ceva-dsp.com/Company-Overview --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index fae26d014aaf..b1db8076e683 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -36,6 +36,7 @@ calxeda Calxeda capellaCapella Microsystems, Inc cavium Cavium, Inc. cdns Cadence Design Systems Inc. +ceva Ceva, Inc. chipidea Chipidea, Inc chipspark ChipSPARK chrp Common Hardware Reference Platform -- 2.3.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3] ARM64: Add new Xilinx ZynqMP SoC
Initial version of device tree for Xilinx ZynqMP SoC.
Signed-off-by: Michal Simek
Acked-by: Sören Brinkmann
---
Changes in v3:
- Add the missing GIC maintenance interrupt
Reported-by Marc Zyngier
- Fix PPI interrupt mask to reflect 4 cores
- Remove cortex-a9-gic compatible string and add arm,gic-400 one
Reported-by Mark Rutland
Changes in v2:
- move timer out of amba_apu bus because it is not on bus
Reported by Mark
- FIC GICC and GICV addresses - Reported by Rob
- Fix copyright
- Enable cadence IP in defconfig
- Add support for macb multiqueue
arch/arm64/Kconfig | 5 +
arch/arm64/boot/dts/Makefile| 1 +
arch/arm64/boot/dts/xilinx/Makefile | 5 +
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 47 +
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 305
arch/arm64/configs/defconfig| 3 +
6 files changed, 366 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/Makefile
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp.dtsi
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 1b8e97331ffb..9f805cf2e0b0 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -228,6 +228,11 @@ config ARCH_XGENE
help
This enables support for AppliedMicro X-Gene SOC Family
+config ARCH_ZYNQMP
+ bool "Xilinx ZynqMP Family"
+ help
+ This enables support for Xilinx ZynqMP Family
+
endmenu
menu "Bus support"
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index e0350caf049e..ff088ec6ca5f 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -5,5 +5,6 @@ dts-dirs += cavium
dts-dirs += exynos
dts-dirs += freescale
dts-dirs += mediatek
+dts-dirs += xilinx
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/xilinx/Makefile
b/arch/arm64/boot/dts/xilinx/Makefile
new file mode 100644
index ..ae16427f6a4a
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
new file mode 100644
index ..0a3f40ecd06d
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -0,0 +1,47 @@
+/*
+ * dts file for Xilinx ZynqMP ep108 development board
+ *
+ * (C) Copyright 2014 - 2015, Xilinx, Inc.
+ *
+ * Michal Simek
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+
+/include/ "zynqmp.dtsi"
+
+/ {
+ model = "ZynqMP EP108";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x4000>;
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@0{
+ reg = <0>;
+ max-speed = <100>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
new file mode 100644
index ..11e0b00045cf
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -0,0 +1,305 @@
+/*
+ * dts file for Xilinx ZynqMP
+ *
+ * (C) Copyright 2014 - 2015, Xilinx, Inc.
+ *
+ * Michal Simek
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/ {
+ compatible = "xlnx,zynqmp";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x1>;
+ };
+
+
Re: [PATCH v2] ARM64: Add new Xilinx ZynqMP SoC
Hi Marc,
On 03/05/2015 03:05 PM, Marc Zyngier wrote:
> Hi Michal,
>
> On 05/03/15 13:53, Michal Simek wrote:
>> Initial version of device tree for Xilinx ZynqMP SoC.
>>
>> Signed-off-by: Michal Simek
>> Acked-by: Sören Brinkmann
>> ---
>>
>> Changes in v2:
>> - move timer out of amba_apu bus because it is not on bus
>>Reported by Mark
>> - FIC GICC and GICV addresses - Reported by Rob
>> - Fix copyright
>> - Enable cadence IP in defconfig
>> - Add support for macb multiqueue
>>
>> arch/arm64/Kconfig | 5 +
>> arch/arm64/boot/dts/Makefile| 1 +
>> arch/arm64/boot/dts/xilinx/Makefile | 5 +
>> arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 47 +
>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 303
>>
>> arch/arm64/configs/defconfig| 3 +
>> 6 files changed, 364 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/xilinx/Makefile
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>
> [...]
>
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
>> b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
>> new file mode 100644
>> index ..0a3f40ecd06d
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
>
> [...]
>
>> +gic: interrupt-controller@f901 {
>> +compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
>> +#interrupt-cells = <3>;
>> +reg = <0x0 0xf901 0x1>,
>> + <0x0 0xf902f000 0x2000>,
>> + <0x0 0xf904 0x2>,
>> + <0x0 0xf906f000 0x2000>;
>> +interrupt-controller;
>
> Please add the missing GIC maintenance interrupt.
Ok. Will add interrupts = <1 9 0xf04>;
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
signature.asc
Description: OpenPGP digital signature
Re: [PATCH v2] ARM64: Add new Xilinx ZynqMP SoC
Hi Thomas,
On 03/05/2015 03:03 PM, Thomas Petazzoni wrote:
> Dear Michal Simek,
>
> On Thu, 5 Mar 2015 14:53:34 +0100, Michal Simek wrote:
>
>> +pmu {
>> +compatible = "arm,armv8-pmuv3";
>> +interrupts = <0 143 4>,
>> + <0 144 4>,
>> + <0 145 4>,
>> + <0 146 4>;
>
> Any reason not to use
>
> #include
> #include
>
> in order to write the more descriptive:
>
> interrupts = ,
>,
>,
>;
>
> And ditto for all other interrupts properties?
I tend to not to use them because it is just hassle when I want
to move DTSes to different project.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
signature.asc
Description: OpenPGP digital signature
[PATCH v2] ARM64: Add new Xilinx ZynqMP SoC
Initial version of device tree for Xilinx ZynqMP SoC.
Signed-off-by: Michal Simek
Acked-by: Sören Brinkmann
---
Changes in v2:
- move timer out of amba_apu bus because it is not on bus
Reported by Mark
- FIC GICC and GICV addresses - Reported by Rob
- Fix copyright
- Enable cadence IP in defconfig
- Add support for macb multiqueue
arch/arm64/Kconfig | 5 +
arch/arm64/boot/dts/Makefile| 1 +
arch/arm64/boot/dts/xilinx/Makefile | 5 +
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 47 +
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 303
arch/arm64/configs/defconfig| 3 +
6 files changed, 364 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/Makefile
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp.dtsi
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 1b8e97331ffb..9f805cf2e0b0 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -228,6 +228,11 @@ config ARCH_XGENE
help
This enables support for AppliedMicro X-Gene SOC Family
+config ARCH_ZYNQMP
+ bool "Xilinx ZynqMP Family"
+ help
+ This enables support for Xilinx ZynqMP Family
+
endmenu
menu "Bus support"
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index e0350caf049e..ff088ec6ca5f 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -5,5 +5,6 @@ dts-dirs += cavium
dts-dirs += exynos
dts-dirs += freescale
dts-dirs += mediatek
+dts-dirs += xilinx
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/xilinx/Makefile
b/arch/arm64/boot/dts/xilinx/Makefile
new file mode 100644
index ..ae16427f6a4a
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
new file mode 100644
index ..0a3f40ecd06d
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -0,0 +1,47 @@
+/*
+ * dts file for Xilinx ZynqMP ep108 development board
+ *
+ * (C) Copyright 2014 - 2015, Xilinx, Inc.
+ *
+ * Michal Simek
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+
+/include/ "zynqmp.dtsi"
+
+/ {
+ model = "ZynqMP EP108";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x4000>;
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@0{
+ reg = <0>;
+ max-speed = <100>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
new file mode 100644
index ..c5f140a34856
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -0,0 +1,303 @@
+/*
+ * dts file for Xilinx ZynqMP
+ *
+ * (C) Copyright 2014 - 2015, Xilinx, Inc.
+ *
+ * Michal Simek
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/ {
+ compatible = "xlnx,zynqmp";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x1>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method =
[PATCH v2] devicetree: cadence_ttc: Document binding for timer width
From: Peter Crosthwaite
Modern TTC implementations can extend the timer width to 32 bit. This
feature is not self identifying so the driver needs to be made aware
via device tree.
Signed-off-by: Peter Crosthwaite
Signed-off-by: Michal Simek
---
Changes in v2:
- Change timer-width description based on my discussion with
Mark Rutland. https://lkml.org/lkml/2014/9/17/277
- Code change is already applied to the mainline kernel tree
Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
index 993695c659e1..6cd51e5c 100644
--- a/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
+++ b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
@@ -6,6 +6,9 @@ Required properties:
- interrupts : A list of 3 interrupts; one per timer channel.
- clocks: phandle to the source clock
+Optional properties:
+- timer-width: Bit width of the timer, necessary if not 16.
+
Example:
ttc0: ttc0@f8001000 {
@@ -14,4 +17,5 @@ ttc0: ttc0@f8001000 {
compatible = "cdns,ttc";
reg = <0xF8001000 0x1000>;
clocks = <&cpu_clk 3>;
+ timer-width = <32>;
};
--
1.8.2.3
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Re: [PATCH] ARM64: Add new Xilinx ZynqMP SoC
Hi Mark,
On 02/24/2015 07:38 PM, Mark Rutland wrote:
> Hi Michal,
>
> I have a few minor comments below, but generally this is looking like
> one of the best dts submissions I've seen!
thanks appreciate it.
>
> [...]
>
>> +/ {
>> + model = "ZynqMP EP108";
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>
> Thanks for using stdout-path with the full parameters.
>
> Does your UART have earlycon support?
yes earlycon support is already in the kernel.
btw: I found that only stdout-path has different behavior
compare to console=ttyPS0,115200 passed via bootargs.
But I have to look at details to be accurate.
>> +/ {
>> + compatible = "xlnx,zynqmp";
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>
> I guess this is fine, though to me it feels more natural to use
> #size-cells = <2> in case we need to describe larger ranges for some bus
> later.
I can fix it when it is needed.
>
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu@0 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + enable-method = "psci";
>> + reg = <0x0>;
>> + };
>> +
>> + cpu@1 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + enable-method = "psci";
>> + reg = <0x1>;
>> + };
>> +
>> + cpu@2 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + enable-method = "psci";
>> + reg = <0x2>;
>> + };
>> +
>> + cpu@3 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + enable-method = "psci";
>> + reg = <0x3>;
>> + };
>> + };
>
> These look fine.
good
>> +
>> + psci {
>> + compatible = "arm,psci-0.2";
>> + method = "smc";
>> + };
>
> Neat!
>
> What are you using as your implementation? Are all the mandatory
> PSCIv0.2 features implemented (e.g. MIGRATE_INFO_TYPE)?
ATF.
>
> I take it this boots at EL2 on all CPUs?
yep.
>
> Does CPU0 hotplug work?
cpu shutdown is working fine with the current firmware.
I didn't try anything else.
>
> Do you need to keep a CPU online or do you require MIGRATE? e.g. does
> MIGRATE_INFO_TYPE return something other than 2 ("MP or not present")?
We are not require migrate and we don't need to keep CPU online now.
Migrate should return -1.
>
> [...]
>
>> + amba_apu {
>> + compatible = "simple-bus";
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupt-parent = <&gic>;
>> + interrupts = <1 13 0xff01>,
>> +<1 14 0xff01>,
>> +<1 11 0xff01>,
>> +<1 10 0xff01>;
>> + };
>
> The architected timer should just be under the root node, given it's a
> component of the CPU -- it doesn't live on any bus.
Fair enough - will add it there.
>
> I take it CNTFRQ is configured appropriately on all CPUs?
I believe so. :-)
> [...]
>
>> + i2c_clk: i2c_clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0x0>;
>> + clock-frequency = <1>;
>> + };
>
> That clock-frequency looks a little odd. Is that right?
why is it odd? Is value too high?
It is exactly what we need to get to get i2c working.
>
> I haven't taken an in-depth look at the other nodes. They look sane at a
> high-level, and assuming they are all already documented and supported
> they look fine to me.
I was checking that and hopefully I didn't miss anything.
Thanks,
Michal
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Re: [PATCH] ARM64: Add new Xilinx ZynqMP SoC
On 02/24/2015 05:29 PM, Rob Herring wrote:
> On Tue, Feb 24, 2015 at 8:58 AM, Michal Simek wrote:
>> On 02/24/2015 03:42 PM, Rob Herring wrote:
>>> On Tue, Feb 24, 2015 at 1:56 AM, Michal Simek
>>> wrote:
>>>> Initial version of device tree for Xilinx ZynqMP SoC.
>>>>
>>>> Signed-off-by: Michal Simek
>>>> Acked-by: Sören Brinkmann
>>>> ---
>>>
>>> [...]
>>>
>>>> + gic: interrupt-controller@f901 {
>>>> + compatible = "arm,cortex-a15-gic",
>>>> "arm,cortex-a9-gic";
>>>
>>> gic-400, right?
>>
>> yep
>>
>>>
>>>> + #interrupt-cells = <3>;
>>>> + reg = <0x0 0xf901 0x1>,
>>>> + <0x0 0xf902 0x2>,
>>>> + <0x0 0xf904 0x2>,
>>>> + <0x0 0xf906 0x2>;
>>>
>>> These addresses are wrong if you are doing address swizzling to do 64K
>>> offsets. We don't really have an answer yet as to what is the right
>>> way. See the XGene GIC discussion[1].
>>
>> Is this better for GICC?
>> <0x0 0xf902f000 0x2000>
>
> Yes, and the VCPU interface needs this as well. As far as sizes, we're
> still discussing that.
ok. Will test and fix. What about the rest of DT description?
Thanks,
Michal
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Re: [PATCH] ARM64: Add new Xilinx ZynqMP SoC
On 02/24/2015 03:42 PM, Rob Herring wrote:
> On Tue, Feb 24, 2015 at 1:56 AM, Michal Simek wrote:
>> Initial version of device tree for Xilinx ZynqMP SoC.
>>
>> Signed-off-by: Michal Simek
>> Acked-by: Sören Brinkmann
>> ---
>
> [...]
>
>> + gic: interrupt-controller@f901 {
>> + compatible = "arm,cortex-a15-gic",
>> "arm,cortex-a9-gic";
>
> gic-400, right?
yep
>
>> + #interrupt-cells = <3>;
>> + reg = <0x0 0xf901 0x1>,
>> + <0x0 0xf902 0x2>,
>> + <0x0 0xf904 0x2>,
>> + <0x0 0xf906 0x2>;
>
> These addresses are wrong if you are doing address swizzling to do 64K
> offsets. We don't really have an answer yet as to what is the right
> way. See the XGene GIC discussion[1].
Is this better for GICC?
<0x0 0xf902f000 0x2000>
Thanks,
Michal
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[PATCH] ARM64: Add new Xilinx ZynqMP SoC
Initial version of device tree for Xilinx ZynqMP SoC.
Signed-off-by: Michal Simek
Acked-by: Sören Brinkmann
---
arch/arm64/Kconfig | 5 +
arch/arm64/boot/dts/Makefile| 1 +
arch/arm64/boot/dts/xilinx/Makefile | 5 +
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 46 +
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 301
arch/arm64/configs/defconfig| 1 +
6 files changed, 359 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/Makefile
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp.dtsi
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 1b8e97331ffb..9f805cf2e0b0 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -228,6 +228,11 @@ config ARCH_XGENE
help
This enables support for AppliedMicro X-Gene SOC Family
+config ARCH_ZYNQMP
+ bool "Xilinx ZynqMP Family"
+ help
+ This enables support for Xilinx ZynqMP Family
+
endmenu
menu "Bus support"
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index e0350caf049e..ff088ec6ca5f 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -5,5 +5,6 @@ dts-dirs += cavium
dts-dirs += exynos
dts-dirs += freescale
dts-dirs += mediatek
+dts-dirs += xilinx
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/xilinx/Makefile
b/arch/arm64/boot/dts/xilinx/Makefile
new file mode 100644
index ..ae16427f6a4a
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
new file mode 100644
index ..121a47fb4043
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -0,0 +1,46 @@
+/*
+ * dts file for Xilinx ZynqMP ep108 development board
+ *
+ * (c) Copyright 2014 - 2015, Xilinx, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+
+/include/ "zynqmp.dtsi"
+
+/ {
+ model = "ZynqMP EP108";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x4000>;
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@0{
+ reg = <0>;
+ max-speed = <100>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
new file mode 100644
index ..d8402fd2dffa
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -0,0 +1,301 @@
+/*
+ * dts file for Xilinx ZynqMP
+ *
+ * (c) Copyright 2014 - 2015, Xilinx, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/ {
+ compatible = "xlnx,zynqmp";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x1>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enabl
[PATCH v2 1/2] remoteproc: microblaze: Document device tree bindings
Add device tree binding documentation for the Microblaze remoteproc
on Xilinx Zynq.
Signed-off-by: Michal Simek
---
Changes in v2:
- Applied changed reported by Mark Rutland here
https://lkml.org/lkml/2015/1/19/198
.../bindings/remoteproc/mb_remoteproc.txt | 45 ++
1 file changed, 45 insertions(+)
create mode 100644
Documentation/devicetree/bindings/remoteproc/mb_remoteproc.txt
diff --git a/Documentation/devicetree/bindings/remoteproc/mb_remoteproc.txt
b/Documentation/devicetree/bindings/remoteproc/mb_remoteproc.txt
new file mode 100644
index ..3a454f01f5f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/mb_remoteproc.txt
@@ -0,0 +1,45 @@
+Xilinx ARM-Microblaze remoteproc driver
+
+A Microblaze is added to the programmable logic on Xilinx Zynq.
+The Microblaze is connected with PS block via axi bus connected to PS HP port
+to ensure access to PS DDR.
+Communication channels are done via soft GPIO IP connected to PS block
+and to Microblaze. There are also 2 gpio control signals reset and debug
+which are used for resetting Microblaze.
+
+Required properties:
+- compatible : Should be "xlnx,mb-remoteproc"
+- reg : Address and length of the ddr address space
+- bram: Phandle to bram controller which can access Microblaze BRAM
+- bram-firmware : Microblaze BRAM bootloader name
+- firmware : Default firmware name which can be override by
+"firmware" module parameter
+- reset-gpio : Gpio phandle which reset Microblaze remoteproc
+- debug-gpio : Gpio phandle which setup Microblaze to debug state
+- ipino-gpio : Gpio phandle for Microblaze to ARM communication
+- vring0-gpio : Gpio phandle for ARM to Microblaze communication vring 0
+- vring1-gpio : Gpio phandle for ARM to Microblaze communication vring 1
+
+Microblaze SoC can be also connected to the PS block via an axi bus.
+That's why there is the option to allocate interrupts for Microblaze use only.
+The driver will allocate interrupts to itself and Microblaze sw has to ensure
+that interrupts are properly enabled and handled by Microblaze interrupt
+controller.
+
+Optional properties:
+ - interrupts : Interrupt mapping for remoteproc
+ - interrupt-parent : Phandle for the interrupt controller
+
+Example:
+mb_remoteproc@80 {
+ compatible = "xlnx,mb-remoteproc";
+ reg = < 0x800 0x800 >;
+ bram = <&axi_bram_ctrl_0>;
+ bram-firmware = "mb.bin";
+ firmware = "image.elf";
+ reset-gpio = <&zynq_gpio_reset 1 0>;
+ debug-gpio = <&zynq_gpio_reset 0 0>;
+ ipino-gpio = <&zynq_gpio_vring 0 0>;
+ vring0-gpio = <&zynq_gpio_vring 1 0>;
+ vring1-gpio = <&zynq_gpio_vring 2 0>;
+};
--
1.8.2.3
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Re: [PATCH v4] dma: Add Xilinx AXI Direct Memory Access Engine driver support
Hi Vinod, On 02/20/2015 07:29 AM, Vinod Koul wrote: > On Sat, Feb 14, 2015 at 02:21:52PM +, Appana Durga Kedareswara Rao wrote: >> Hi Vinod, >> >> >>> -Original Message- >>> From: Vinod Koul [mailto:vinod.k...@intel.com] >>> Sent: Thursday, February 12, 2015 3:05 PM >>> To: Appana Durga Kedareswara Rao >>> Cc: Arnd Bergmann; linux-arm-ker...@lists.infradead.org; >>> devicetree@vger.kernel.org; Srikanth Vemula; linux- >>> ker...@vger.kernel.org; Srikanth Thokala; dmaeng...@vger.kernel.org; >>> robh...@kernel.org; Michal Simek; Anirudha Sarangi; >>> grant.lik...@linaro.org; dan.j.willi...@intel.com >>> Subject: Re: [PATCH v4] dma: Add Xilinx AXI Direct Memory Access Engine >>> driver support >>> >>> On Thu, Jan 29, 2015 at 11:24:41AM +, Appana Durga Kedareswara Rao >>> wrote: >>>>> Earlier in the driver we are embedding dma_slave_config into custom >>>>> structs But Lars suggested to modify it. please refer to the below >>>>> thread for more details. >>>>> http://www.spinics.net/lists/dmaengine/msg00010.html >>>>> >>>>> And later we thought of creating a separate private member in >>>>> dma_slave_config for sharing additional configuration between slave >>>>> device and dma engine Or a new dma_ctrl_cmd like >>>>> >>> FSLDMA_EXTERNAL_START(http://www.kernelhub.org/?msg=405535&p=2 ) >>>>> >>>>> Finally Vinod was ok with the existing suggestion so we dropped the >>>>> above thought. >>>>> >>>>> @Vinod : Could you please comment on this. >>> FSLDMA_EXTERNAL_START has been removed, and you cna use the removal >>> as a guidance of how to solve your issue >>> >> > Please limit you mailer to set wrap at 80 chars, otherwise it becomes > unreadable > >> The current VDMA driver that got merged in the open source and the >> current patch (dma: xilinx dma v4) Srikanth T submitted both contains the >> Similar implementation that you pointed as above(I mean similar to the >> free scale dma driver). >> >> The discussion starts here is why we need the header file(Xilinx_dma.h) in >> the include/linux/amba/Xilinx_dma.h folder. >> >> Like for FSL DMA it is got defined (fsl_dma_external_start) as a function >> prototype in include/linux/fsldma.h And it is being getting used in the >> drivers/misc/carma/carma-fpga-program.c >> >> Similarly in the Xilinx VDMA driver(xilinx_vdma_channel_set_config ) >> defined as a function prototype in the include/linux/amba/xilinx_dma.h And >> is being used by Xilinx videos drivers. Those video driver need to use >> the (xilinx_vdma_channel_set_config) which requires this global header >> file. >> >> Could you please suggest us whether that header file (Xilinx_dma.h) should >> be there in include/linux/amba or we should move it to include/linux? >> And any functional comments for this v4 patch? > Let me ask you a question, what is the relation of xilinx_dma with amba? > > If none then only include/linux/ seems to be the right choice. If not then > amba maybe okay but you need to provide justfication why it should be in amba? I see your point. I think there is real reason to have this header in amba. The reason for that was that xilinx_dma.h was added there. Anyway there is include/linux/dma/ folder. Is it ok to move xilinx_dma.h there too? The same with this dma one. Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v8 2/4] fpga manager: add sysfs interface document
On 02/17/2015 08:17 PM, Pavel Machek wrote: > On Tue 2015-02-17 11:07:53, Rob Landley wrote: >> >> >> On 02/15/2015 04:40 PM, Pavel Machek wrote: >>> On Wed 2015-01-21 13:27:00, Jason Gunthorpe wrote: On Wed, Jan 21, 2015 at 06:33:12PM +0200, Pantelis Antoniou wrote: My point is that the current firmware layer is overly cautious and FPGAs are very big. My current project on small Xilinx device has a 10MB programming file. The biggest Xilinx device today has a max bitfile size around 122MB. So keeping that much memory pinned in the kernel when I can prove it is uncessary for my system (either because there is no suspend/resume possibility, or because I know the CPU can always access the filesytem) is very undesirable. >>> >>> Well, your current device aalso has 1GB RAM, no? >> >> Unnecessarily pinning 10% of your ram is a good solution? > > Never said that. But I'd rather have _some_ API proposed, then try to > design in everthing including kitchen sink and do nothing. +1 on this. Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] ARM: dts: zynq: Add OCM node
On 02/12/2015 04:07 PM, Mark Rutland wrote:
> On Thu, Feb 12, 2015 at 02:58:36PM +, Sören Brinkmann wrote:
>> On Thu, 2015-02-12 at 12:01PM +0100, Michal Simek wrote:
>>> On 02/12/2015 11:54 AM, Mark Rutland wrote:
>>>> On Thu, Feb 12, 2015 at 10:42:47AM +, Michal Simek wrote:
>>>>> Add OCM node for all zynq boards. OCM location
>>>>> can changed but for all current boards this
>>>>> is the location where OCM is.`
>>>>>
>>>>> Signed-off-by: Michal Simek
>>>>> ---
>>>>>
>>>>> Changes in v2:
>>>>> - Move node to board file suggested by Mark
>>>>>
>>>>> This patch is done based on discussion here.
>>>>> https://lkml.org/lkml/2014/12/1/396
>>>>>
>>>>> Mark: I expect you won't like amba bus reference or
>>>>> am I wrong?
>>>>
>>>> I'm fine with dropping things onto a bus in this way. If we're happy to
>>>> do it for other nodes I don't see why busses should be special.
>>>
>>> Wonderful. I will give people some time to comment this style.
>>
>> Given that the location is discoverable, wouldn't it make sense to let
>> 'reg' point to the ctrl/cfg registers in the SLCR and let the driver
>> handle the whereabouts of the OCM location? (but I guess this is going
>> in circles now, such a proposal was on the table at some point, IIRC).
>> But I'd prefer:
>> memory-controller@0xfffc { /* the address here would of course not
>> match all configurations */
>
> I'd really prefer that we keep the unit-address and reg consistent.
>
> Given that the address may change on a per-board basis, it simply has to
> live in the board file.
>
> However, given that all boards are currently the same it could be
> dropped in the SoC file for now, with a comment saying it should be
> factored out to boards when the first board with a different address
> comes along.
Soren is talking about different solution which I have tried to push to mainline
in that thread above. OCM configuration is discoverable through system
controller
to find out which configuration is used.
>From this simple sram block it looks like that it is 64k of memory but
it is just one block which can live in low or high address (at 0x0 or
0xfffc)
based on controller configuration.
In total there are 4 blocks with low and high locations.
Thanks,
Michal
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Re: [PATCH v2] ARM: dts: zynq: Add OCM node
On 02/12/2015 03:58 PM, Sören Brinkmann wrote:
> On Thu, 2015-02-12 at 12:01PM +0100, Michal Simek wrote:
>> On 02/12/2015 11:54 AM, Mark Rutland wrote:
>>> On Thu, Feb 12, 2015 at 10:42:47AM +, Michal Simek wrote:
>>>> Add OCM node for all zynq boards. OCM location
>>>> can changed but for all current boards this
>>>> is the location where OCM is.`
>>>>
>>>> Signed-off-by: Michal Simek
>>>> ---
>>>>
>>>> Changes in v2:
>>>> - Move node to board file suggested by Mark
>>>>
>>>> This patch is done based on discussion here.
>>>> https://lkml.org/lkml/2014/12/1/396
>>>>
>>>> Mark: I expect you won't like amba bus reference or
>>>> am I wrong?
>>>
>>> I'm fine with dropping things onto a bus in this way. If we're happy to
>>> do it for other nodes I don't see why busses should be special.
>>
>> Wonderful. I will give people some time to comment this style.
>
> Given that the location is discoverable, wouldn't it make sense to let
> 'reg' point to the ctrl/cfg registers in the SLCR and let the driver
> handle the whereabouts of the OCM location? (but I guess this is going
> in circles now, such a proposal was on the table at some point, IIRC).
> But I'd prefer:
> memory-controller@0xfffc { /* the address here would of course not
> match all configurations */
> interrupts = ...;
> syscon = &slcr;
> };
That was discussed with Arnd at that link above.
Thanks,
Michal
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Re: [PATCH v2] ARM: dts: zynq: Add OCM node
On 02/12/2015 11:54 AM, Mark Rutland wrote: > On Thu, Feb 12, 2015 at 10:42:47AM +0000, Michal Simek wrote: >> Add OCM node for all zynq boards. OCM location >> can changed but for all current boards this >> is the location where OCM is.` >> >> Signed-off-by: Michal Simek >> --- >> >> Changes in v2: >> - Move node to board file suggested by Mark >> >> This patch is done based on discussion here. >> https://lkml.org/lkml/2014/12/1/396 >> >> Mark: I expect you won't like amba bus reference or >> am I wrong? > > I'm fine with dropping things onto a bus in this way. If we're happy to > do it for other nodes I don't see why busses should be special. Wonderful. I will give people some time to comment this style. Thanks for your comments, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: zynq: Add OCM node
Hi Mark, On 02/12/2015 11:26 AM, Mark Rutland wrote: > On Thu, Feb 12, 2015 at 10:22:07AM +0000, Michal Simek wrote: >> Add OCM node for all zynq boards. OCM location >> can changed but for all current boards this >> is the location where OCM is.` >> >> Signed-off-by: Michal Simek >> --- >> >> This patch is done based on discussion here. >> https://lkml.org/lkml/2014/12/1/396 >> >> There are some ways how to do it. >> OCM location can be changed but board DTS files >> can easily rewrite it. >> The problem which there is that node has address >> in it but maybe someone can suggest better solution. > > Given that the node is so simple, can't this be pushed down into the > board files? So long as the label is consistent anything else that's > referring to it should still work. ok. Let me send v2 with moving stuff to board file and reference bus. (I expect you will want to use different solution but will see). Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2] ARM: dts: zynq: Add OCM node
Add OCM node for all zynq boards. OCM location
can changed but for all current boards this
is the location where OCM is.`
Signed-off-by: Michal Simek
---
Changes in v2:
- Move node to board file suggested by Mark
This patch is done based on discussion here.
https://lkml.org/lkml/2014/12/1/396
Mark: I expect you won't like amba bus reference or
am I wrong?
---
arch/arm/boot/dts/zynq-7000.dtsi | 2 +-
arch/arm/boot/dts/zynq-zc702.dts | 7 +++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index a5cd2eda3edf..acca3c180324 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -57,7 +57,7 @@
regulator-always-on;
};
- amba {
+ amba: amba {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index fb59d34e8ee6..79077c5ac60e 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -50,6 +50,13 @@
};
};
+&amba {
+ ocm: sram@fffc {
+ compatible = "mmio-sram";
+ reg = <0xfffc 0x1>;
+ };
+};
+
&can0 {
status = "okay";
pinctrl-names = "default";
--
1.8.2.3
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[PATCH] ARM: dts: zynq: Add OCM node
Add OCM node for all zynq boards. OCM location
can changed but for all current boards this
is the location where OCM is.`
Signed-off-by: Michal Simek
---
This patch is done based on discussion here.
https://lkml.org/lkml/2014/12/1/396
There are some ways how to do it.
OCM location can be changed but board DTS files
can easily rewrite it.
The problem which there is that node has address
in it but maybe someone can suggest better solution.
---
arch/arm/boot/dts/zynq-7000.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index a5cd2eda3edf..d55a8b365a6c 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -150,6 +150,11 @@
reg = <0xf8006000 0x1000>;
};
+ ocm: sram@fffc {
+ compatible = "mmio-sram";
+ reg = <0xfffc 0x1>;
+ };
+
uart0: serial@e000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
--
1.8.2.3
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Re: [PATCH 2/2] ARM: dts: zynq: Add linux,stdout-path and stdout-path
Hi Mark and Simon,
On 02/11/2015 03:25 PM, Michal Simek wrote:
> On 02/11/2015 01:40 PM, Mark Rutland wrote:
>> On Wed, Feb 11, 2015 at 12:29:02PM +0000, Michal Simek wrote:
>>> parallella - Use reference instead of hardcoded path
>>> (linux,stdout-path)
>>>
>>> stdout-path is used by bootloader to identify console.
>>>
>>> Signed-off-by: Michal Simek
>>> ---
>>>
>>> U-Boot driver model requires stdout-path.
>>> ---
>>> arch/arm/boot/dts/zynq-parallella.dts | 3 ++-
>>> arch/arm/boot/dts/zynq-zc702.dts | 2 ++
>>> arch/arm/boot/dts/zynq-zc706.dts | 2 ++
>>> arch/arm/boot/dts/zynq-zed.dts| 2 ++
>>> arch/arm/boot/dts/zynq-zybo.dts | 2 ++
>>> 5 files changed, 10 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/boot/dts/zynq-parallella.dts
>>> b/arch/arm/boot/dts/zynq-parallella.dts
>>> index 6a5f51daa708..45228a427006 100644
>>> --- a/arch/arm/boot/dts/zynq-parallella.dts
>>> +++ b/arch/arm/boot/dts/zynq-parallella.dts
>>> @@ -35,7 +35,8 @@
>>>
>>> chosen {
>>> bootargs = "console=ttyPS0,115200 earlyprintk
>>> root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
>>> - linux,stdout-path = "/amba/serial@e0001000";
>>> + linux,stdout-path = &uart1;
>>> + stdout-path = &uart1;
>>
>> Given that you added aliases in the last patch, you can use that to
>> refer to the serial:
>>
>> stdout-path - "serial0:115200n8";
>>
>> With or without the alias you can encode the UART configuration here
>> too:
>>
>> stdout-path = "/amba/serial@e0001000:115200n8"
>
> let me check this configuration if it is supported by u-boot.
I have converted Linux DTSes to this style and it is working fine.
For U-Boot DM this description is not supported.
Simon: Do you have any plan to support this new description?
Thanks,
Michal
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[PATCH v2] ARM: dts: zynq: Fix stdout-path and bootargs
parallella - Remove linux,stdout-path.
Use stdout-path to identify kernel console
Signed-off-by: Michal Simek
---
Changes in v2:
- Remove linux,stdout-path reported by Mark Rutland
- Use stdout-path new console description with setting
- Change patch subject from "ARM: dts: zynq: Add linux,stdout-path and
stdout-path"
- Do not add 1/2 patch which added aliases node to zybo and parallella
arch/arm/boot/dts/zynq-parallella.dts | 4 ++--
arch/arm/boot/dts/zynq-zc702.dts | 3 ++-
arch/arm/boot/dts/zynq-zc706.dts | 3 ++-
arch/arm/boot/dts/zynq-zed.dts| 3 ++-
arch/arm/boot/dts/zynq-zybo.dts | 3 ++-
5 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/zynq-parallella.dts
b/arch/arm/boot/dts/zynq-parallella.dts
index 6a5f51daa708..e1e5b2423d26 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -34,8 +34,8 @@
};
chosen {
- bootargs = "console=ttyPS0,115200 earlyprintk
root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
- linux,stdout-path = "/amba/serial@e0001000";
+ bootargs = "earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw
rootwait";
+ stdout-path = "serial0:115200n8";
};
};
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 1fc1d3911e9b..fb59d34e8ee6 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -30,7 +30,8 @@
};
chosen {
- bootargs = "console=ttyPS0,115200 earlyprintk";
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
};
leds {
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
index 850518d9b8ac..abf5d238ae04 100644
--- a/arch/arm/boot/dts/zynq-zc706.dts
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -30,7 +30,8 @@
};
chosen {
- bootargs = "console=ttyPS0,115200 earlyprintk";
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
};
usb_phy0: phy0 {
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
index 5658bc8434de..b9f2522012e8 100644
--- a/arch/arm/boot/dts/zynq-zed.dts
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -29,7 +29,8 @@
};
chosen {
- bootargs = "console=ttyPS0,115200 earlyprintk";
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
};
usb_phy0: phy0 {
diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/zynq-zybo.dts
index 935a561f6aa6..16c9cacd668d 100644
--- a/arch/arm/boot/dts/zynq-zybo.dts
+++ b/arch/arm/boot/dts/zynq-zybo.dts
@@ -29,7 +29,8 @@
};
chosen {
- bootargs = "console=ttyPS0,115200 earlyprintk";
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
};
};
--
1.8.2.3
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Re: [PATCH 2/2] ARM: dts: zynq: Add linux, stdout-path and stdout-path
On 02/11/2015 07:18 PM, Andreas Färber wrote:
> Am 11.02.2015 um 15:25 schrieb Michal Simek:
>> On 02/11/2015 01:40 PM, Mark Rutland wrote:
>>> On Wed, Feb 11, 2015 at 12:29:02PM +, Michal Simek wrote:
>>>> parallella - Use reference instead of hardcoded path
>>>> (linux,stdout-path)
>>>>
>>>> stdout-path is used by bootloader to identify console.
>>>>
>>>> Signed-off-by: Michal Simek
>>>> ---
>>>>
>>>> U-Boot driver model requires stdout-path.
>>>> ---
>>>> arch/arm/boot/dts/zynq-parallella.dts | 3 ++-
>>>> arch/arm/boot/dts/zynq-zc702.dts | 2 ++
>>>> arch/arm/boot/dts/zynq-zc706.dts | 2 ++
>>>> arch/arm/boot/dts/zynq-zed.dts| 2 ++
>>>> arch/arm/boot/dts/zynq-zybo.dts | 2 ++
>>>> 5 files changed, 10 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/zynq-parallella.dts
>>>> b/arch/arm/boot/dts/zynq-parallella.dts
>>>> index 6a5f51daa708..45228a427006 100644
>>>> --- a/arch/arm/boot/dts/zynq-parallella.dts
>>>> +++ b/arch/arm/boot/dts/zynq-parallella.dts
>>>> @@ -35,7 +35,8 @@
>>>>
>>>>chosen {
>>>>bootargs = "console=ttyPS0,115200 earlyprintk
>>>> root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
>>>> - linux,stdout-path = "/amba/serial@e0001000";
>>>> + linux,stdout-path = &uart1;
>>>> + stdout-path = &uart1;
>>>
>>> Given that you added aliases in the last patch, you can use that to
>>> refer to the serial:
>>>
>>> stdout-path - "serial0:115200n8";
>>>
>>> With or without the alias you can encode the UART configuration here
>>> too:
>>>
>>> stdout-path = "/amba/serial@e0001000:115200n8"
>>
>> let me check this configuration if it is supported by u-boot.
>
> I would be surprised if either is supported - my Parallella ships:
> U-Boot 2012.10-3-g792c31c (Jan 03 2014 - 12:24:08)
> and upstream U-Boot still doesn't have support for the Parallella.
Ancient u-boot versions are not using this features. Zynq hasn't been
switched to DM anyway.
>>> Which makes the expected configuration explicit without relying on the
>>> Linux-specific bootargs.
>>>
>>> Is there any reason to keep linux,stdout-path?
>>
>> Agree when stdout-patch is defined there is no reason to use
>> linux,stdout-patch.
>
> It's not used, it was added on reviewers' request at the time. Feel free
> to drop. But again, we are bound for patch conflict here.
I will solved that conflicts - it is easy one.
Thanks,
Michal
signature.asc
Description: OpenPGP digital signature
[PATCH] of: Add vendor prefix for Arasan
PATA(pata_arasan_cf.c) and SDHCI(sdhci-of-arasan.c) drivers are already using this prefix. Signed-off-by: Michal Simek --- https://arasan.com/contact/ --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index b1df0ad1306c..7da04260a680 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -18,6 +18,7 @@ amlogic Amlogic, Inc. amsAMS AG amstaosAMS-Taos Inc. apmApplied Micro Circuits Corporation (APM) +arasan Arasan Chip Systems armARM Ltd. armadeus ARMadeus Systems SARL atmel Atmel Corporation -- 1.8.2.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] ARM: dts: zynq: Add linux,stdout-path and stdout-path
On 02/11/2015 01:40 PM, Mark Rutland wrote:
> On Wed, Feb 11, 2015 at 12:29:02PM +0000, Michal Simek wrote:
>> parallella - Use reference instead of hardcoded path
>> (linux,stdout-path)
>>
>> stdout-path is used by bootloader to identify console.
>>
>> Signed-off-by: Michal Simek
>> ---
>>
>> U-Boot driver model requires stdout-path.
>> ---
>> arch/arm/boot/dts/zynq-parallella.dts | 3 ++-
>> arch/arm/boot/dts/zynq-zc702.dts | 2 ++
>> arch/arm/boot/dts/zynq-zc706.dts | 2 ++
>> arch/arm/boot/dts/zynq-zed.dts| 2 ++
>> arch/arm/boot/dts/zynq-zybo.dts | 2 ++
>> 5 files changed, 10 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/zynq-parallella.dts
>> b/arch/arm/boot/dts/zynq-parallella.dts
>> index 6a5f51daa708..45228a427006 100644
>> --- a/arch/arm/boot/dts/zynq-parallella.dts
>> +++ b/arch/arm/boot/dts/zynq-parallella.dts
>> @@ -35,7 +35,8 @@
>>
>> chosen {
>> bootargs = "console=ttyPS0,115200 earlyprintk
>> root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
>> -linux,stdout-path = "/amba/serial@e0001000";
>> +linux,stdout-path = &uart1;
>> +stdout-path = &uart1;
>
> Given that you added aliases in the last patch, you can use that to
> refer to the serial:
>
> stdout-path - "serial0:115200n8";
>
> With or without the alias you can encode the UART configuration here
> too:
>
> stdout-path = "/amba/serial@e0001000:115200n8"
let me check this configuration if it is supported by u-boot.
>
> Which makes the expected configuration explicit without relying on the
> Linux-specific bootargs.
>
> Is there any reason to keep linux,stdout-path?
Agree when stdout-patch is defined there is no reason to use linux,stdout-patch.
Thanks,
Michal
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[PATCH 2/2] ARM: dts: zynq: Add linux,stdout-path and stdout-path
parallella - Use reference instead of hardcoded path
(linux,stdout-path)
stdout-path is used by bootloader to identify console.
Signed-off-by: Michal Simek
---
U-Boot driver model requires stdout-path.
---
arch/arm/boot/dts/zynq-parallella.dts | 3 ++-
arch/arm/boot/dts/zynq-zc702.dts | 2 ++
arch/arm/boot/dts/zynq-zc706.dts | 2 ++
arch/arm/boot/dts/zynq-zed.dts| 2 ++
arch/arm/boot/dts/zynq-zybo.dts | 2 ++
5 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/zynq-parallella.dts
b/arch/arm/boot/dts/zynq-parallella.dts
index 6a5f51daa708..45228a427006 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -35,7 +35,8 @@
chosen {
bootargs = "console=ttyPS0,115200 earlyprintk
root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
- linux,stdout-path = "/amba/serial@e0001000";
+ linux,stdout-path = &uart1;
+ stdout-path = &uart1;
};
};
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 1fc1d3911e9b..205c7c472bac 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -31,6 +31,8 @@
chosen {
bootargs = "console=ttyPS0,115200 earlyprintk";
+ linux,stdout-path = &uart1;
+ stdout-path = &uart1;
};
leds {
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
index 850518d9b8ac..f624747719dd 100644
--- a/arch/arm/boot/dts/zynq-zc706.dts
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -31,6 +31,8 @@
chosen {
bootargs = "console=ttyPS0,115200 earlyprintk";
+ linux,stdout-path = &uart1;
+ stdout-path = &uart1;
};
usb_phy0: phy0 {
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
index 5658bc8434de..a957159104ea 100644
--- a/arch/arm/boot/dts/zynq-zed.dts
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -30,6 +30,8 @@
chosen {
bootargs = "console=ttyPS0,115200 earlyprintk";
+ linux,stdout-path = &uart1;
+ stdout-path = &uart1;
};
usb_phy0: phy0 {
diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/zynq-zybo.dts
index 935a561f6aa6..e51f889f7fc7 100644
--- a/arch/arm/boot/dts/zynq-zybo.dts
+++ b/arch/arm/boot/dts/zynq-zybo.dts
@@ -30,6 +30,8 @@
chosen {
bootargs = "console=ttyPS0,115200 earlyprintk";
+ linux,stdout-path = &uart1;
+ stdout-path = &uart1;
};
};
--
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[PATCH 1/2] ARM: dts: zynq: Add missing alias node for zybo and parallella
Add missing alias node.
Signed-off-by: Michal Simek
---
arch/arm/boot/dts/zynq-parallella.dts | 5 +
arch/arm/boot/dts/zynq-zybo.dts | 5 +
2 files changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/zynq-parallella.dts
b/arch/arm/boot/dts/zynq-parallella.dts
index ab1dc0a56cdd..6a5f51daa708 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -23,6 +23,11 @@
model = "Adapteva Parallella Board";
compatible = "adapteva,parallella", "xlnx,zynq-7000";
+ aliases {
+ ethernet0 = &gem0;
+ serial0 = &uart1;
+ };
+
memory {
device_type = "memory";
reg = <0x0 0x4000>;
diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/zynq-zybo.dts
index a9a12ce5023b..935a561f6aa6 100644
--- a/arch/arm/boot/dts/zynq-zybo.dts
+++ b/arch/arm/boot/dts/zynq-zybo.dts
@@ -18,6 +18,11 @@
model = "Zynq ZYBO Development Board";
compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
+ aliases {
+ ethernet0 = &gem0;
+ serial0 = &uart1;
+ };
+
memory {
device_type = "memory";
reg = <0x0 0x2000>;
--
1.8.2.3
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Re: [PATCH 1/2] ARM: zynq: Remove bogus value from 'bias-disable' property
On 01/28/2015 04:41 PM, Sören Brinkmann wrote: > On Wed, 2015-01-28 at 03:21PM +0100, Michal Simek wrote: >> On 01/27/2015 01:38 AM, Andreas Färber wrote: >>> Am 26.01.2015 um 20:49 schrieb Soren Brinkmann: >>>> In one pinctrl node, a 'bias-disable' property is erroneously assigned a >>>> value. >>>> >>>> Fixes: ARM: zynq: DT: Add pinctrl information >>>> Signed-off-by: Soren Brinkmann >>> >>> Reviewed-by: Andreas Färber >>> >>> Andreas >>> >> >> Applied both. > > Thanks. Given how the branch looks now, you could squash 'ARM: zynq: DT: > Remove bogus value from 'bias-disable' property' and 'ARM: zynq: DT: Add > pinctrl information to USB nodes' into 'ARM: zynq: DT: Add pinctrl > information'. Then we have it all in one patch and spare everybody the > intermittent, partly broken commits. That's not a problem. I have sent pull request with current state. Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 6/7] ARM: zynq: DT: Add pinctrl information
On 01/27/2015 01:00 AM, Andreas Färber wrote: > Am 12.01.2015 um 08:27 schrieb Michal Simek: >> On 01/11/2015 10:38 PM, Linus Walleij wrote: >>> On Fri, Jan 9, 2015 at 4:43 PM, Soren Brinkmann >>> wrote: >>> >>>> Add pinctrl descriptions to the zc702 and zc706 device trees. >>>> >>>> Signed-off-by: Soren Brinkmann >>>> Tested-by: Andreas Färber >>> >>> Reviewed-by: Linus Walleij >>> >>> Beautiful and in line with how I want things to look. >>> >>> Yours, >>> Linus Walleij >>> >> >> Applied to zynq/dt. > > Did you maybe forget to push? > > https://github.com/Xilinx/linux-xlnx/commits/zynq/dt doesn't have it. Ah sorry - I have pushed it now. Thanks, Michal signature.asc Description: OpenPGP digital signature
Re: [PATCH 1/2] ARM: zynq: Remove bogus value from 'bias-disable' property
On 01/27/2015 01:38 AM, Andreas Färber wrote: > Am 26.01.2015 um 20:49 schrieb Soren Brinkmann: >> In one pinctrl node, a 'bias-disable' property is erroneously assigned a >> value. >> >> Fixes: ARM: zynq: DT: Add pinctrl information >> Signed-off-by: Soren Brinkmann > > Reviewed-by: Andreas Färber > > Andreas > Applied both. Thanks, Michal signature.asc Description: OpenPGP digital signature
Re: [PATCH v3] ARM: zynq: DT: Add USB to device tree
On 01/26/2015 09:19 AM, Andreas Färber wrote: > Hi Michal, > > Am 03.12.2014 um 09:39 schrieb Michal Simek: >> On 12/02/2014 05:07 PM, Soren Brinkmann wrote: >>> Add USB nodes to zc702, zc706 and zed device trees. >>> >>> Signed-off-by: Soren Brinkmann >>> --- >>> v3: >>> - rename phy nodes: usb_phy -> phy0 >>> - rebased onto zynq/dt >>> v2: >>> - remove '@0' from phy node name >>> - don't add bogus space >>> --- >>> arch/arm/boot/dts/zynq-7000.dtsi | 20 >>> arch/arm/boot/dts/zynq-zc702.dts | 11 +++ >>> arch/arm/boot/dts/zynq-zc706.dts | 10 ++ >>> arch/arm/boot/dts/zynq-zed.dts | 10 ++ >>> 4 files changed, 51 insertions(+) > [...] >> >> Applied to zynq/dt. > > Hm, I don't see this patch in linux-next next-20150123... > > And if I apply it to my -next based tree, adding corresponding nodes to > zynq-parallella.dts, I get repeatedly: > > [ +0,012242] ci_hdrc ci_hdrc.0: no of_node; not parsing pinctrl DT > [ +0,000157] ci_hdrc ci_hdrc.0: ChipIdea HDRC found, lpm: 0; cap: > f090e100 op: f090e140 > [ +0,81] platform ci_hdrc.0: Driver ci_hdrc requests probe deferral > [ +0,005360] ci_hdrc ci_hdrc.1: no of_node; not parsing pinctrl DT > [ +0,000120] ci_hdrc ci_hdrc.1: ChipIdea HDRC found, lpm: 0; cap: > f0910100 op: f0910140 > [ +0,001810] platform ci_hdrc.1: Driver ci_hdrc requests probe deferral > > Am I missing any other patches or config options? > (I do notice that the pinctrl v3 patch that got merged has a trivial bug > for usb0, for which I'll send a patch later on.) Why is it deferred? Is it because of pinmuxing stuff? Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform signature.asc Description: OpenPGP digital signature
