[Discuss-gnuradio] TVRX LNA

2007-12-21 Thread Nirali Patel
Hi,

Does the TVRX board have a front-end gain stage before the signal is 
downconverted to IF? I will be using the TVRX and the USRP to capture over the 
air HDTV signals in a mobile field test. I looked at the schematic for the TVRX 
board and it looks there isn't a discrete LNA on the board. Does the MT4937 
chip have an integrated LNA before the down conversion to IF? I've looked at 
the tuner datasheet but couldn't tell for sure if there was an LNA.

Thanks for any help and information. 

Nirali


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[Discuss-gnuradio] TVRX

2007-11-27 Thread Nirali Patel
Matt,

Is the TVRX daughter board expected to change anytime in near future?

Thanks,
Nirali Patel


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RE: [Discuss-gnuradio] I and Q samples out of FPGA receive chain

2007-11-06 Thread Nirali Patel
Jonathan,

Thanks for your response. I can see the ch0rx signal toggling on my Basic RX
in slot A using the following command
u = usrp.source_c(0,decim_rate=8,fpga_filename="mytestfile.rbf")
u._write_oe(0,0x,ox)# for enabling A side Basic RX
u._write_fpga_reg(FR_DEBUG_EN, bmFR_DEBUG_EN_RX_A)

How do I modify the _write_oe command in order to output enable a Basic TX
also on side A? 

If I use 

u._write_fpga_reg(FR_DEBUG_EN, bmFR_DEBUG_EN_RX_A | bmFR_DEBUG_EN_TX_A)

it does not enable the Basic TX on side A. 

Thanks again for the help!
Nirali
> -Original Message-
> From: Johnathan Corgan [mailto:[EMAIL PROTECTED]
> Sent: Monday, November 05, 2007 10:46 AM
> To: Nirali Patel
> Cc: discuss-gnuradio@gnu.org
> Subject: Re: [Discuss-gnuradio] I and Q samples out of FPGA receive chain
> 
> On 11/2/07, Nirali Patel <[EMAIL PROTECTED]> wrote:
> 
> > In the usrp_std.v file what signals do you recommend to look at the 16
> bits
> > I and Q out of the HB filter of the receive_chain?
> > Thanks again for you time and help.
> > Nirali
> 
> Use the ch0rx and ch1rx signals that go into the rx_buffer.
> 
> --
> Johnathan Corgan
> Corgan Enteprises LLC
> http://corganenterprises.com/




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RE: [Discuss-gnuradio] I and Q samples out of FPGA receive chain

2007-11-02 Thread Nirali Patel
I believe I am enabling the appropriate oe registers using the following
commands
u = usrp.source_c(0,decim_rate=8,fpga_filename="mytestfile.rbf")
subdev = usrp.selected_subdev(u,(1,0))  # for getting signals from slot B
TV_RX
u._write_oe(0,0x,ox)# for enabling A side Basic RX
u._write_fpga_reg(FR_DEBUG_EN, bmFR_DEBUG_EN_RX_A)

However, I am perplexed as to why bb_rx_i0 or bb_rx_q0 do not seem to
toggle. When I connect ddc0_in_i signals I can see them toggling. I must be
doing something really stupid because the rbf file I generated works well
with a standard example like usrp_fft.py. So the data path from the ADC to
the USB is working well. But somehow I am not able to tap into the I and Q
signals out of the receive_chain and see them toggling. 

In the usrp_std.v file what signals do you recommend to look at the 16 bits
I and Q out of the HB filter of the receive_chain? 
Thanks again for you time and help.
Nirali 

> -Original Message-
> From: Johnathan Corgan [mailto:[EMAIL PROTECTED]
> Sent: Friday, November 02, 2007 11:56 AM
> To: Nirali Patel
> Cc: discuss-gnuradio@gnu.org
> Subject: Re: [Discuss-gnuradio] I and Q samples out of FPGA receive chain
> 
> Nirali Patel wrote:
> 
> > However I do not see any outputs when I connect these signals to the
> > debug pins using debug_0(bb_rx_q0),.debug_1(bb_rx_i0).
> 
> When routing signals through the master_controller debug ports, you'll
> need to (on the host at runtime) enable the debug output register, and
> set the IO pins as outputs.
> 
> HOWEVER--don't EVER do this unless you are using a BasicRX/TX or LFRX/TX
> board in the slots.  You can damage the daughterboard, USRP FPGA, or
> both otherwise.
> 
> --
> Johnathan Corgan
> Corgan Enterprises LLC
> http://corganenterprises.com




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[Discuss-gnuradio] I and Q samples out of FPGA receive chain

2007-11-01 Thread Nirali Patel
Hi,

 

I am using the USRP and TV_RX in slot B to capture over the air signals. I
understand the receive chain processing inside of the FPGA and was trying to
get the complex 16-bit I and Q samples out at the debug IO pins. As a dry
run I tried connecting 12-bit the rx_a_b input to the debug IO pins and
could do so successfully by enabling appropriate registers and modifying
usrp_std.v. However, in the usrp_std.v I am unable to pinpoint the signals
that carry I and Q channels that come out of the receive chain. I tried
routing the bb_rx_i0 and bb_rx_q0 signals that come out of the rx_chain_0
block. Since I am running 1rx and 1tx configuration only rx_chain_0 is
enabled, I guess. However I do not see any outputs when I connect these
signals to the debug pins using debug_0(bb_rx_q0),.debug_1(bb_rx_i0). I have
a Basic RX and Basic TX in A slots to look at the outputs. I also tried
routing the signals labeled ch0rx, ch1rx to debug pins but still no outputs.
Then in my desperation I tried routing the rest of ch2rx to ch7rx to debug
pins with a new rbf file everytime but still no outputs. I could verify that
the ddc0_in_i signals are toggling but the bb_rx_i0 and bb_rx_q0 do not seem
to toggle. I would like to look at individual I Q signals and then
eventually connect the interleaved I and Q that go to the USB. 

Any help/guidelines appreciated.

 

Thanks,

Nirali Patel

 

   assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 :
bb_rx_i0;

   assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0
: bb_rx_q0;

   assign ch2rx = bb_rx_i1;

   assign ch3rx = bb_rx_q1;

   assign ch4rx = bb_rx_i2;

   assign ch5rx = bb_rx_q2;

   assign ch6rx = bb_rx_i3;

   assign ch7rx = bb_rx_q3;

 

   wire [15:0]
ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_i
n_q;

   wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3;

   

   adc_interface
adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),

 
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_st
robe),

 
.rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b),

 
.rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3),

 .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q),

 .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),

 .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),

 
.ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) );

 

`ifdef RX_EN_0

   rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0

 ( .clock(clk64),.reset(1'b0),.enable(enable_rx),

 
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(s
trobe_decim),.hb_strobe(hb_strobe),

 
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_st
robe),

 
.i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugda
ta(debugdata),.debugctrl(debugctrl));

 `else

   assign  bb_rx_i0=16'd0;

   assign  bb_rx_q0=16'd0;

 `endif 

 

 

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Re: [Discuss-gnuradio] CIC passband compensation

2007-10-25 Thread Nirali Patel
Hi Firas,

Thanks for your response. In an earlier thread you had posted a matlab script 
called usrpddc.m that calculates the overall frequency response of the usrp rx 
chain and plots it. This would be very useful to me however, when I try to run 
it I find it is missing mfilt.cicdecim() function. If you still have this and 
could make it available it will be a great help.

Thanks
Nirali

Hi Patel,

No [CIC non flat response] compensation filter is available.

Firas

Nirali Patel wrote:
> 
> Hi,
> 
> I am trying to understand the USRP receive chain response and referred to
> earlier posts that gave me almost all the information that I needed.
> However, I am unsure whether the HB filter compensates for the passband
> droop that occurs in the CIC. 


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[Discuss-gnuradio] CIC passband compensation

2007-10-25 Thread Nirali Patel
Hi,

I am trying to understand the USRP receive chain response and referred to 
earlier posts that gave me almost all the information that I needed. However, I 
am unsure whether the HB filter compensates for the passband droop that occurs 
in the CIC. My understanding of the CIC was that the frequency response has a 
sinc like function and is typically followed by a FIR which compensates for the 
sinx/x shape in the passband. Does the HB filter response compensate for the 
non-flat passband of the CIC? 

Thanks,
Nirali 


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RE: [Discuss-gnuradio] Decimate by 2 possible?

2007-10-22 Thread Nirali Patel
Brian,

Thanks for your response. 

> What is your target symbol rate?  

My target symbol rate is 10.76 MHZ (8-vsb ATSC symbol rate). I need only 2x
of this symbol rate, i.e 21.52 Mhz to do down stream processing. 

>Is there a reason you want to play directly with 32Msps?  
Only for troubleshooting interpolation-algorithm problems on the downstream
board. 
If I send a lower rate e.g 8Msps then there is a need for interpolation
first and it appears that there is a bug in the algorithm for cubic
interpolation method on the downstream board that causes sampling offsets.
So it would be nice if there was only downsampling involved in getting to
21.52 Mhz. 
 
> Maybe it would be better if you decimated to 1x or 2x the symbol rate
> and then processed that data on your other board?
Yes, you are right. Ultimately I should only send the decimated data.
If I use both the CIC and HBF then the lowest combined decimation rate is 8,
which gives me 8 Msps output. I might avoid the HBF for now and get a
decimation of 4 in the CIC. I found from an earlier post that the file
4rx_0tx.rbf has only CIC and no HBF. Do you know how this file can be
generated? I need to start at the toplevel in order to make connections to
the debug IO pins. 

> What do you think?  Is this more plausible of a scenario for you?
This definitely makes good sense. Thanks for the suggestions!

Nirali Patel





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[Discuss-gnuradio] Decimate by 2 possible?

2007-10-22 Thread Nirali Patel
Hi,

 

I am using the TV_RX and USRP to capture the 64 Msps data from the A/D
converter and send that to another downstream board for processing. I am
connecting the signal from the ADC to the debug IO pins of the FPGA to get
to the 16 io_rx[] pins of Basic RX. However, my board-to-board
interconnection turned out to have a bandwidth limitation of 50 MHz so I can
no longer hope to send 64 Msps raw data from the ADC over the interconnect
bus. The next best thing would be to decimate by a factor of 2 and then
route the 32 Msps data to the debug pins. I understand the the CIC has a
decimation range of [4,5,6,.128] and the HBF decimates by a factor of 2. Is
there a way to get an overall decimation of just 2 by possibly bypassing the
CIC and using only the HBF? If this sounds like a dumb question then, what
would be the best way to get 32 Msps over to the Basic RX card using what's
already in the FPGA? 

Thanks in advance for any suggestions. 

 

Nirali

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[Discuss-gnuradio] 64Mhz Crystal Oscillator part number

2007-10-19 Thread Nirali Patel
Hi,

 

I have a USRP Rev 4.5 and I was trying to find stability information on the
64 Mhz crystal oscillator. However, I am unable to cross-reference it to a
manufacturer's part number. The part number on the BOM says X2 is a digikey
CTX286LVCT-ND. However the part populated on the 

USRP is from Ecliptek and the number stamped on the part itself just tells
about the frequency and the year/week of  production. I am also unsure if
this is a TCXO or not. Any help and information appreciated.

 

Thanks,

Nirali

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RE: [Discuss-gnuradio] Unable to find field sync for over the air HDTV signal

2007-10-12 Thread Nirali Patel
Hello Eric,

> [In looking at interp.py, it could be modified to run something like
> 4x faster by using gr.interp_fir_filter_ccf instead of what's in
> there.  Also, decimating by 10 seems a bit agressive.  By 8 would give
> you more usable signal, though would require changes in the interp.py
> code.]

I have gotten a set of RAID 0 drives installed and now I can write with a
decimation factor of 8 without any overruns. I would like to modify
interp.py to appropriately interpolate and lowpass filter the 8 Msps signal
from the USRP. Would it be sufficient if I interpolate by 2? Or do I need a
higher, maybe fractional interpolation rate? I am also unsure of what the
filter cut-off frequency would need to be after the proper interpolation. If
you have any suggestions it would be a great help! 

Thanks,
Nirali






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RE: [Discuss-gnuradio] TVRX Kit - A Few Queries

2007-10-12 Thread Nirali Patel
>>I ordered Tvrx module and expect it to arrive at my place soon. Hope it
will have a manual or imp guidelines on usage. 

The TVRX will not come with a manual or guidelines on usage. You can find
the schematics at http://gnuradio.org/trac/browser/usrp-hw/trunk/tvrx
The TVRX module has a Microtune 4937 Tuner Module and here is a link to the
datasheet for that
http://www.comsec.com/usrp/microtune/4937-DI5-3x8899-2.pdf

>>1) What is range of the IF I can set its output to?
It has a fixed IF at 44Mhz I believe. A different version of the same tuner
module comes with 5.75Mhz IF. Matt, please correct me if I am wrong.

>>2) Can I use it for HDTV reception?
Yes you can use it for HDTV reception. I am trying to do the same thing and
am halfway there. I suggest you start with FM reception or something pretty
basic using examples in gnuradio-examples directory.

>>3) What is the max voltage swing in the output? Is there a DC offset in
it?
Ref datasheet mentioned above.


Nirali Patel





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[Discuss-gnuradio] Unable to find field sync for over the air HDTV signal

2007-10-10 Thread Nirali Patel
Hello everyone,

I am trying to capture a few seconds of over the air HDTV on a file and then
decode using the files in gr-atsc module according to the instructions in
the README at gr-atsc/src/python. I am using the following command to
capture the signals off the air: /usrp_rx_cfile.py -R B -d 10 -f 587M -g 75
test_file, where 587MHz is the center of the 584-590 MHZ UHF band. I can
successfully capture about 20 seconds of data without any overruns. After I
set up the pipes and start the equalizer, it is unable to find field syncs.
At some gain settings it initially detects field sync but loses it later on.
Am I lacking enough gain/sensitivity in the front-end of the TV_RX? If so
would an lna at the antenna help? Or could I be doing something else that
prevents the equalizer to find field sync? I believe a number of folks must
have decoded over the air hdtv signals using the TV_RX and USRP. Any
suggestions and help appreciated.

Thanks,
Nirali




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RE: [Discuss-gnuradio] Default FPGA I/O standard

2007-10-02 Thread Nirali Patel
Thanks everyone for the help and information. I also discovered that if you
want to increase the drive strength for any IO standard for the FPGA IO pins
it is possible through the Assignment Editor in Quartus II under Logic
Options by setting current_strength_new to 

Thanks again for all the information.
Nirali
-Original Message-
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On Behalf
Of Bahn William L Civ USAFA/DFCS
Sent: Tuesday, October 02, 2007 5:15 PM
To: discuss-gnuradio@gnu.org
Subject: RE: [Discuss-gnuradio] Default FPGA I/O standard


> -Original Message-
> From: [EMAIL PROTECTED]
> [mailto:[EMAIL PROTECTED] On Behalf
> Of Brian Padalino
> Sent: Monday, October 01, 2007 5:53 PM
> To: Matt Ettus
> Cc: discuss-gnuradio@gnu.org
> Subject: Re: [Discuss-gnuradio] Default FPGA I/O standard
>
> On 10/1/07, Matt Ettus <[EMAIL PROTECTED]> wrote:
> > I think 3.3V LVTTL and LVCMOS are really the same.
> >
> > Matt
>
> According to this:
>
> http://www.interfacebus.com/voltage_LV_threshold.html
>
> They are, indeed, basically the same.
>
> Brian

They're the same only different.

For most purposes, the differences don't matter too much. The biggest
difference is in the output drive capability. LVTTL outputs are required to
be able to source/sink 2mA while remaining compliant while LVCMOS outputs
are only required to source/sink 100uA.

For those interested in the "official" word, refer to the actual JEDEC
standard:

http://www.jedec.org/download/search/jesd8c.pdf




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RE: [Discuss-gnuradio] Default FPGA I/O standard

2007-10-01 Thread Nirali Patel
Hi Matt,

I modified the usrp_std.v file to make connections to the debug IO pins and
then on my PC tried to compile the project using Quartus II software. The
compile went successfully, but later when I opened the Pin-Out file under
Compilation Report all the signals showed at 3.3V-LVTTL. I had only clicked
on the play button after opening the .qpf project. 
I would like to know if the default settings are still all 3.3V LVCMOS and I
inadvertently changed something. If not, I would like to set the 16-bit
debug pins to LVCMOS since I am trying to attach a CMOS cable to the pins on
basic RX. Could you recommend a way to do this? Do I have to look at IO
banking rules etc.? I have some FPGA background but not a whole lot.

Thanks,
Nirali Patel

-Original Message-
From: Matt Ettus [mailto:[EMAIL PROTECTED] 
Sent: Wednesday, September 26, 2007 5:01 PM
To: Nirali Patel
Cc: discuss-gnuradio@gnu.org
Subject: Re: [Discuss-gnuradio] Default FPGA I/O standard

Nirali Patel wrote:
> Hi all,
>
> I am trying to find out the default I/O standard e.g LVTTL, LVCMOS that is
set on the FPGA general purpose debug pins (16-bits available on the
daughter card connectors). I don't have Quartus II installed yet. Is there a
way to find out or set this through Python?
>   

3.3V LVCMOS




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[Discuss-gnuradio] No horizontal sync with ntsc tv reception

2007-10-01 Thread Nirali Patel
Hi,

 

I am working on ntsc tv reception as a precursor to hdtv reception. I am
using usrp_rx_cfile.py to capture samples to a file from the TV_RX board and
then playing back using usrp_tv_rcv_nogui.py. The picture displayed does not
seem to have horizontal sync (picture keeps moving from left to right). I
have tried setting different decimation factors, the best I can use without
overruns is a factor of 8 and the picture still rolls in horizontal
direction. My understanding was that the decimation factor would only affect
the horizontal resolution not the ability to sync, but I could be wrong. The
commands that I use for capture and playback are:

./usrp_rx_cfile.py -R B -d 16 -f 531.25M -s tv1.out 

./usrp_tv_rcv_nogui.py -f 531.23M -n -i tv1.out sdl

 

where 531.25 Mhz is the picture carrier of the ntsc channel with lower band
edge at 530Mhz.

I have also tried using -f 533M to set the tuning frequency to centre of the
band but no significant change in picture sync.

If anyone has experienced similar problem I would appreciate the guidance.
Does the antenna setting have any influence on h-sync? My office is in the
interior of the building so would it help to move towards the exterior?

 

Thanks in advance for any help.

 

Nirali Patel

 

 

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[Discuss-gnuradio] Cautions with _write_oe

2007-09-27 Thread Nirali Patel
Hi, 

 

I have the TV_RX board in slot B and Basic RX in slot A of the USRP. I am
trying to get the raw A/D data that comes into the FPGA, out on the daughter
card connector. I would like to use the 16-bit general purpose debug pins
from the FPGA on the connector on Basic RX. However, I'd like to be careful
before I write to the direction register using the _write_oe given that an
improper setting can cause damage. My question is whether I can have both
TV_RX and Basic RX boards plugged in, while I use the _write_oe? If yes,
what is the precaution that I have to follow?  Any suggestions appreciated. 

 

Thanks,

Nirali Patel

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[Discuss-gnuradio] Default FPGA I/O standard

2007-09-26 Thread Nirali Patel
Hi all,

I am trying to find out the default I/O standard e.g LVTTL, LVCMOS that is set 
on the FPGA general purpose debug pins (16-bits available on the daughter card 
connectors). I don't have Quartus II installed yet. Is there a way to find out 
or set this through Python?

Thanks,
Nirali Patel
DSP Application Engineer
Coherent Logix


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[Discuss-gnuradio] TV_RX anti-aliasing filter

2007-09-26 Thread Nirali Patel
Hello everyone,

I am a new user and recently set up the USRP and TV_RX boards to receive FM 
radio and now trying to take the dive into capturing HDTV. I had a basic, maybe 
dumb question on the presence of a low pass filter before the A/D converter. 
Does anyone know if the TV_RX board has an anti-aliasing low pass filter on it? 
Or within the Microtune 4937 tuner module? I looked at the schematic for the 
daughter board and the data sheet for 4937 but I am not sure if there is one. 
The TV_RX I got has an IF frequency of 44MHz and I understand that 
undersampling it at 64 Msps with the A/D converter causes it to fold to 20 MHz. 
I wanted to know whether there is or there needs to be a low pass filter before 
the A/D converter to suppress any energy in the lower frequencies before 
sampling.

Thanks,
Nirali Patel
DSP Application Engineer
Coherent Logix, Inc



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