RE: need help writing driver for SiS m650

2005-06-12 Thread Vladimir Dergachev



On Sun, 12 Jun 2005, Matt Sealey wrote:



Someone explain to me why an organised boycott of SiS graphics chips
would somehow ENCOURAGE them to help?


If all other things have been tried why not ?

At least the boycott also makes sure that people who follow it don't have 
hardware we can't write drivers for.


 best

   Vladimir Dergachev

PS Is ODW fanless ? Just curious..



Reducing their sales means they have a vat of new excuses for not
supporting you.

--
Matt Sealey <[EMAIL PROTECTED]>
Manager, Genesi, Developer Relations



-Original Message-
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On Behalf Of
[EMAIL PROTECTED]
Sent: Monday, July 11, 2005 11:54 AM
To: Dri-devel@lists.sourceforge.net
Cc: [EMAIL PROTECTED]
Subject: Re: need help writing driver for SiS m650

I'm rather interested in starting a project to reverse
engineer these blasted chips, but I'm somewhat more inclined
to start a boycott of them instead.

For reverse engineering, I *think* the DLL has an EULA that
doesn't let you do any sort of peeking into it, so for legal
reasons, we might not be able to go that way.  If anyone has
more insight into that, it would be welcomed.

If there is no easier option, then I was considering just
making a FreeDOS-based system and hitting the hardware
directly.  I used to do that with old video chips, long long
ago when I programmed for DOS in Pascal...


Hey Benjamin,

I have one of these myself and I have tried looking up on reverse
engineering the windows xp driver. However I have found it

very hard

to do so. The driver dll is stripped of all opengl function

symbols,

and exports only symbols necessary to comply with the ICD

architecture.


OpenGL drivers on windows are written accordingly to the ICD
architecture, which has no open documentation out there.

After hearing

with microsoft a license for a ICD development kit costs

5000 dollars,

and one must have a valid need for it!

Do have any plans on making an effort reversing the SiS315?


/Cenk

On Mon, Jul 11, 2005 at 12:14:55PM -0400,

[EMAIL PROTECTED] wrote:

I've found myself in the unfortunate ownership of many of these
pitiful SiS315-based cards and boards with onboard SiS

video.  I may

be interested in reverse-engineering, as I rather like

that sort of

tedious work.
however, after seeing as much as I have seen from these

short-sighted

companies, I think an organized boycott of SiS would be more
effective for getting our hands on specs, or even a closed-source
driver.

their chipset quality is already extremely lacking, and they will
have a really hard time beating VIA on, well,

anything...and VIA is

starting to release their stuff open-source!  SiS doesn't

have much to bargain with.


I will help how I can...

-Benjamin Vander Jagt







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Re: [R300] radeon 9800 lockup & RADEON_LATENCY

2005-06-12 Thread Vladimir Dergachev



On Sun, 12 Jun 2005, Rune Petersen wrote:


Jerome Glisse wrote:

On 6/12/05, Rune Petersen <[EMAIL PROTECTED]> wrote:


Jerome Glisse wrote:


Does the following differences means that the
fglrx driver load another microcode ?


Last I checked, Yes.



But when reloading r300 (radeon module) the fglrx
microcode is overwritten no ?

yes.


Strictly speaking it is overwritten each time Xserver is restarted, but I 
guess this has the same effect :)


   best

Vladimir Dergachev



Rune Petersen


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Re: [R300] radeon 9800 lockup & RADEON_LATENCY

2005-06-12 Thread Dave Airlie

> Does the following differences means that the
> fglrx driver load another microcode ?

I've written a hw_script that reads back the microcode from fglrx,

I've already replaced my microcode to see if my issues were with it (they
weren't..)

I've added a hw_scripts directory to r300_driver with 3 scripts in it, two
are PCI express readbacks and the third is a microcode reader, it dumps
the current microcode in C format for sticking into the driver..

Dave.

-- 
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http://www.skynet.ie/~airlied / airlied at skynet.ie
Linux kernel - DRI, VAX / pam_smb / ILUG



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[Bug 2241] implement GL_ARB_texture_cube_map in radeon driver

2005-06-12 Thread bugzilla-daemon
Please do not reply to this email: if you want to comment on the bug, go to
   
the URL shown below and enter yourcomments there. 
   
https://bugs.freedesktop.org/show_bug.cgi?id=2241  
 

[EMAIL PROTECTED] changed:

   What|Removed |Added

Attachment #2830 is|0   |1
   obsolete||




--- Additional Comments From [EMAIL PROTECTED]  2005-06-12 12:23 ---
Created an attachment (id=2881)
 --> (https://bugs.freedesktop.org/attachment.cgi?id=2881&action=view)
mesa_radeon_cubemap_20050612.diff.txt

cubemap demo works, even if using new packets and maos_arrays.
projtex (still) works.
ut2003_demo antalus looks ok, at least better than before ;)
ut2003_demo citadel looks ok in sw-tnl mode only.

I don't know if the change is a real fix or only partially working:
ut2003_demo seems to send 3 texcoords when 2d texturing and so a 0 was written
to the q-coord.
Could this (submitting 3 texcoords) be the trigger for a tcl-fallback in the
radeon driver?

Is ctx->Texture.Unit[x]._ReallyEnabled up to date when radeonSetVertexFormat()
is called ?
  
 
 
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Re: [R300] radeon 9800 lockup & RADEON_LATENCY

2005-06-12 Thread Rune Petersen

Jerome Glisse wrote:

On 6/12/05, Rune Petersen <[EMAIL PROTECTED]> wrote:


Jerome Glisse wrote:


Does the following differences means that the
fglrx driver load another microcode ?


Last I checked, Yes.



But when reloading r300 (radeon module) the fglrx
microcode is overwritten no ?

yes.

Rune Petersen


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Re: [R300] radeon 9800 lockup & RADEON_LATENCY

2005-06-12 Thread Jerome Glisse
On 6/12/05, Rune Petersen <[EMAIL PROTECTED]> wrote:
> Jerome Glisse wrote:
> > Does the following differences means that the
> > fglrx driver load another microcode ?
> Last I checked, Yes.

But when reloading r300 (radeon module) the fglrx
microcode is overwritten no ?

Jerome Glisse


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RE: need help writing driver for SiS m650

2005-06-12 Thread Matt Sealey

Someone explain to me why an organised boycott of SiS graphics chips
would somehow ENCOURAGE them to help?

Reducing their sales means they have a vat of new excuses for not
supporting you.

-- 
Matt Sealey <[EMAIL PROTECTED]>
Manager, Genesi, Developer Relations
 

> -Original Message-
> From: [EMAIL PROTECTED] 
> [mailto:[EMAIL PROTECTED] On Behalf Of 
> [EMAIL PROTECTED]
> Sent: Monday, July 11, 2005 11:54 AM
> To: Dri-devel@lists.sourceforge.net
> Cc: [EMAIL PROTECTED]
> Subject: Re: need help writing driver for SiS m650
> 
> I'm rather interested in starting a project to reverse 
> engineer these blasted chips, but I'm somewhat more inclined 
> to start a boycott of them instead.
> 
> For reverse engineering, I *think* the DLL has an EULA that 
> doesn't let you do any sort of peeking into it, so for legal 
> reasons, we might not be able to go that way.  If anyone has 
> more insight into that, it would be welcomed.
> 
> If there is no easier option, then I was considering just 
> making a FreeDOS-based system and hitting the hardware 
> directly.  I used to do that with old video chips, long long 
> ago when I programmed for DOS in Pascal...
> 
> > Hey Benjamin,
> >
> > I have one of these myself and I have tried looking up on reverse 
> > engineering the windows xp driver. However I have found it 
> very hard 
> > to do so. The driver dll is stripped of all opengl function 
> symbols, 
> > and exports only symbols necessary to comply with the ICD 
> architecture.
> >
> > OpenGL drivers on windows are written accordingly to the ICD 
> > architecture, which has no open documentation out there. 
> After hearing 
> > with microsoft a license for a ICD development kit costs 
> 5000 dollars, 
> > and one must have a valid need for it!
> >
> > Do have any plans on making an effort reversing the SiS315?
> >
> >
> > /Cenk
> >
> > On Mon, Jul 11, 2005 at 12:14:55PM -0400, 
> [EMAIL PROTECTED] wrote:
> >> I've found myself in the unfortunate ownership of many of these 
> >> pitiful SiS315-based cards and boards with onboard SiS 
> video.  I may 
> >> be interested in reverse-engineering, as I rather like 
> that sort of 
> >> tedious work.
> >> however, after seeing as much as I have seen from these 
> short-sighted 
> >> companies, I think an organized boycott of SiS would be more 
> >> effective for getting our hands on specs, or even a closed-source 
> >> driver.
> >>
> >> their chipset quality is already extremely lacking, and they will 
> >> have a really hard time beating VIA on, well, 
> anything...and VIA is 
> >> starting to release their stuff open-source!  SiS doesn't 
> have much to bargain with.
> >>
> >> I will help how I can...
> >>
> >> -Benjamin Vander Jagt
> >>
> >
> 
> 
> 
> ---
> This SF.Net email is sponsored by: NEC IT Guy Games.  How far 
> can you shotput a projector? How fast can you ride your desk 
> chair down the office luge track?
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Re: [R300] radeon 9800 lockup & RADEON_LATENCY

2005-06-12 Thread Rune Petersen

Jerome Glisse wrote:

Does the following differences means that the
fglrx driver load another microcode ?

Last I checked, Yes.


Rune Petersen



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Re: need help writing driver for SiS m650

2005-06-12 Thread benjamin
I'm rather interested in starting a project to reverse engineer these
blasted chips, but I'm somewhat more inclined to start a boycott of them
instead.

For reverse engineering, I *think* the DLL has an EULA that doesn't let
you do any sort of peeking into it, so for legal reasons, we might not be
able to go that way.  If anyone has more insight into that, it would be
welcomed.

If there is no easier option, then I was considering just making a
FreeDOS-based system and hitting the hardware directly.  I used to do that
with old video chips, long long ago when I programmed for DOS in Pascal...

> Hey Benjamin,
>
> I have one of these myself and I have tried looking up on reverse
> engineering the windows xp driver. However I have found it very hard to do
> so. The driver dll is stripped of all opengl function symbols, and exports
> only symbols necessary to comply with the ICD architecture.
>
> OpenGL drivers on windows are written accordingly to the ICD architecture,
> which has no open documentation out there. After hearing with microsoft a
> license for a ICD development kit costs 5000 dollars, and one must have a
> valid need for it!
>
> Do have any plans on making an effort reversing the SiS315?
>
>
> /Cenk
>
> On Mon, Jul 11, 2005 at 12:14:55PM -0400, [EMAIL PROTECTED] wrote:
>> I've found myself in the unfortunate ownership of many of these pitiful
>> SiS315-based cards and boards with onboard SiS video.  I may be
>> interested
>> in reverse-engineering, as I rather like that sort of tedious work.
>> however, after seeing as much as I have seen from these short-sighted
>> companies, I think an organized boycott of SiS would be more effective
>> for
>> getting our hands on specs, or even a closed-source driver.
>>
>> their chipset quality is already extremely lacking, and they will have a
>> really hard time beating VIA on, well, anything...and VIA is starting to
>> release their stuff open-source!  SiS doesn't have much to bargain with.
>>
>> I will help how I can...
>>
>> -Benjamin Vander Jagt
>>
>



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Re: [R300] radeon 9800 lockup & RADEON_LATENCY

2005-06-12 Thread Jerome Glisse
It's not only RADEON_LATENCY if i set PCI latency to 0xff
i still got the lockup i am pretty disappointed as it seemed
to be the winning register. Anyway here is a longer list of
reg that may play role (i will try to find a place on the web
to put the dump thus anyone interested could look at them
too).

The palette register seems to be setup to safe default
values :
RADEON_PALETTE_DATA 0x00b4
RADEON_PALETTE_30_DATA  0x00b8
RADEON_PALETTE_INDEX0x00b0

The CRTC status is different too (restarting xorg r300
after fglrx keep the change)
RADEON_CRTC_STATUS

Does the following differences means that the
fglrx driver load another microcode ?
RADEON_CP_ME_RAM_ADDR   0x07d4
RADEON_CP_ME_RAM_DATAL  0x07e0

The 0x180 and 0x154 are setups

And the radeon :
RADEON_BUS_CNTL

There are others regs but they change from one
run to another and don't seems to follow any rules
(look random).

The following reg cause a hardlockup when i try to read
them :
0x0574
0x0d68 to 0x0f00

Jerome


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Re: need help writing driver for SiS m650

2005-06-12 Thread benjamin
I've found myself in the unfortunate ownership of many of these pitiful
SiS315-based cards and boards with onboard SiS video.  I may be interested
in reverse-engineering, as I rather like that sort of tedious work. 
however, after seeing as much as I have seen from these short-sighted
companies, I think an organized boycott of SiS would be more effective for
getting our hands on specs, or even a closed-source driver.

their chipset quality is already extremely lacking, and they will have a
really hard time beating VIA on, well, anything...and VIA is starting to
release their stuff open-source!  SiS doesn't have much to bargain with.

I will help how I can...

-Benjamin Vander Jagt

need help writing driver for SiS m650
The Slash
 Mon, 02 May 2005 10:33:05 -0700
well since there is no DRI support for the SiS m650, and according to
what I heard there never will be, I have decided to write my own. I
have never written my own driver before, and I'm a little confused as
to where to begin. I know that SiS does not normally distribute there
hardware specs, so i might end up having to reverse-engineer the
windows drivers. any advice on where to start for this sort of thing?
and if i were able to get the info from SiS, what exactly would I
need?
-- 
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Re: [R300] radeon 9800 lockup & RADEON_LATENCY

2005-06-12 Thread Jerome Glisse
Btw Daniels suggest me that this could be a mirror of
the latency reg register(0xd) of PCI. If it is should i expect
it to change overtime or should it keeps its value ?

Jerome Glisse


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Re: [R300] radeon 9800 lockup & RADEON_LATENCY

2005-06-12 Thread Jerome Glisse
Thx for the info but seems that the most important (at least to me :))
RADEON_LATENCY have no specs ?

I really think, nearly convinced that this the key register to solve the
lockup. I dump the reg after a cold boot with xorg & r300, then
i quit xorg & r300 and launch x with fglrx don't launch anythings (just Xserver)
dump the reg, then quit an relaunch r300 & xorg dump the reg.

After all this i can play to ut2004demo and launch all other program
that used to lockup the 9800 without any lockups.

After diffing many dumps i have bunch of few register that i suspect to
play a role. And i really think that this is the RADEON_LATENCY the key
one...

Jerome Glisse


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Re: [R300] radeon 9800 lockup & RADEON_LATENCY

2005-06-12 Thread Alex Deucher
On 6/12/05, Vladimir Dergachev <[EMAIL PROTECTED]> wrote:
> 
> 
> On Sun, 12 Jun 2005, Jerome Glisse wrote:
> 
> > Hi,
> >
> > After many tests and reboot i have a set of register that
> > may influence 9800 lockups. Unfortunetly i don't know
> > how to play with this register as they doesn't seems to be
> > used anywhere (nor X driver, dri, drm if i trust my grep :))
> >
> > RADEON_LATENCY the most likely to help to resolve the
> > lockup. After a cold reboot i read 0x40 in it. I would like to
> > read 0xff but it seems to be read only and after writing to
> > some random place near it i can't figure out how to setup
> > it.
> >
> > What does this regs do  :
> > RADEON_BIOS_6_SCRATCH
> 
> This is a scratch register - basically just a 32 bit piece of memory. It
> is used by video BIOS during startup, since BIOS cannot be certain
> whether main memory have been properly initialized and it is certain that
> video memory was not.
> 
> Also, AFAIK, it is used by video BIOS to store some values (perhaps mode
> information ?)

This reg is exactly what the name implies.  It's a bios scratch
register.  I don't know that anyone has any documentation to to
exactly what these regs do (and it may vary from oem to oem), but they
are generally concerned with things like seeing which outputs are
active or if acpi hotkeys are allowed to switch the modes or outputs.
take a look at the bottom of RADEONInitFPRegisters() in
radeon_driver.c

Alex

> 
> > RADEON_MDGPIO_Y_REG
> 
> On R300 this is a VIP bus register, should have nothing to do with 3d.
> 
> Also, I would generally suggest to not play with any register with GPIO in
> the name, unless you have very good reason to. A wrong value written could
> damage your card.
> 
> The reason is that GPIO often refers to general purpose input. So if you
> accidentally enable an output that is used as an input pulled low and then
> write 1 there you will get a short circuit.
> 
>   best
> 
>  Vladimir Dergachev
> 
> >
> > As this regs appear in radeon reg i hope that some one
> > with the radeon specs on it could give me anyclue on
> > how to play or what is there meanings.
> >
> > Thx
> >
> > Jerome Glisse
> >
> >
> > ---
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Re: [R300] radeon 9800 lockup & RADEON_LATENCY

2005-06-12 Thread Vladimir Dergachev



On Sun, 12 Jun 2005, Jerome Glisse wrote:


Hi,

After many tests and reboot i have a set of register that
may influence 9800 lockups. Unfortunetly i don't know
how to play with this register as they doesn't seems to be
used anywhere (nor X driver, dri, drm if i trust my grep :))

RADEON_LATENCY the most likely to help to resolve the
lockup. After a cold reboot i read 0x40 in it. I would like to
read 0xff but it seems to be read only and after writing to
some random place near it i can't figure out how to setup
it.

What does this regs do  :
RADEON_BIOS_6_SCRATCH


This is a scratch register - basically just a 32 bit piece of memory. It 
is used by video BIOS during startup, since BIOS cannot be certain 
whether main memory have been properly initialized and it is certain that 
video memory was not.


Also, AFAIK, it is used by video BIOS to store some values (perhaps mode 
information ?)



RADEON_MDGPIO_Y_REG


On R300 this is a VIP bus register, should have nothing to do with 3d.

Also, I would generally suggest to not play with any register with GPIO in 
the name, unless you have very good reason to. A wrong value written could 
damage your card.


The reason is that GPIO often refers to general purpose input. So if you 
accidentally enable an output that is used as an input pulled low and then 
write 1 there you will get a short circuit.


 best

Vladimir Dergachev



As this regs appear in radeon reg i hope that some one
with the radeon specs on it could give me anyclue on
how to play or what is there meanings.

Thx

Jerome Glisse


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Re: [R300] new snapshot ?

2005-06-12 Thread Vladimir Dergachev



On Sun, 12 Jun 2005, Nicolai Haehnle wrote:


On Friday 10 June 2005 18:10, Vladimir Dergachev wrote:


On Fri, 10 Jun 2005, Aapo Tahkola wrote:


Someone, I believe it was Aapo, said that they see white lines across

the

screen when the framerate is fairly high. I didn't see this up until

yesterday

when I had to change from my 9600pro to a 9600XT (I killed the card

moving

it between machines somehow).


Are you using SiS based motherboard by any chance?
Following patch should fix this at the cost of some speed...


I just committed the following patch to r300_reg.h:


Thanks. By the way, I confirmed that fglrx sets those bits in 0x180 on the
following cards:
- 0x4E44 (R300)
- 0x4E50 (RV350)
- 0x4A49 (R420)
... i.e. pretty much across the board. However, there are many other
registers that it touches, and I couldn't test how it affects lockups yet.


How very interesting :) I wonder whether this would fix the apparent 
tendency of the driver to spend a lot of time in the kernel waiting for 
something on rv350..


Or, at least, that's what top says.


+#  define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT24
+#  define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT24


Is the last 24 supposed to be a 28?


+#  define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT0


Is the last 0 supposed to be a 28?


Yes, to both. Sorry for hasty typing I was about to leave when I read 
Aapo's e-mail.


Fixed version is in CVS.

  best

Vladimir Dergachev



cu,
Nicolai




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Re: [R300] new snapshot ?

2005-06-12 Thread Jerome Glisse
On 6/12/05, Nicolai Haehnle <[EMAIL PROTECTED]> wrote:
> On Friday 10 June 2005 18:10, Vladimir Dergachev wrote:
> >
> > On Fri, 10 Jun 2005, Aapo Tahkola wrote:
> >
> > >> Someone, I believe it was Aapo, said that they see white lines across
> the
> > >> screen when the framerate is fairly high. I didn't see this up until
> yesterday
> > >> when I had to change from my 9600pro to a 9600XT (I killed the card
> moving
> > >> it between machines somehow).
> > >
> > > Are you using SiS based motherboard by any chance?
> > > Following patch should fix this at the cost of some speed...
> >
> > I just committed the following patch to r300_reg.h:
> 
> Thanks. By the way, I confirmed that fglrx sets those bits in 0x180 on the
> following cards:
> - 0x4E44 (R300)
> - 0x4E50 (RV350)
> - 0x4A49 (R420)
> ... i.e. pretty much across the board. However, there are many other
> registers that it touches, and I couldn't test how it affects lockups yet.

It sets it too on 0x4e4a (RV350 NJ). For the lockups see my other mail,
i am pretty sure that once we get the proper reported value in 0x0f0d
(RADEON_LATENCY) the lockup will go...

> > +#define R300_MC_INIT_MISC_LAT_TIMER0x180
> > +#  define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT  0
> > +#  define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT   4
> > +#  define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT   8
> > +#  define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT   12
> > +#  define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT16
> > +#  define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT  20
> > +#  define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT24
> > +#  define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT24
> 
> Is the last 24 supposed to be a 28?
> 
> > +
> > +
> > +#define R300_MC_INIT_GFX_LAT_TIMER 0x154
> > +#  define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT0
> > +#  define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT4
> > +#  define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT8
> > +#  define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT12
> > +#  define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16
> > +#  define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20
> > +#  define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT24
> > +#  define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT0
> 
> Is the last 0 supposed to be a 28?
> 

Jerome


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Re: [R300] new snapshot ?

2005-06-12 Thread Nicolai Haehnle
On Friday 10 June 2005 18:10, Vladimir Dergachev wrote:
> 
> On Fri, 10 Jun 2005, Aapo Tahkola wrote:
> 
> >> Someone, I believe it was Aapo, said that they see white lines across 
the
> >> screen when the framerate is fairly high. I didn't see this up until 
yesterday
> >> when I had to change from my 9600pro to a 9600XT (I killed the card 
moving
> >> it between machines somehow).
> >
> > Are you using SiS based motherboard by any chance?
> > Following patch should fix this at the cost of some speed...
> 
> I just committed the following patch to r300_reg.h:

Thanks. By the way, I confirmed that fglrx sets those bits in 0x180 on the 
following cards:
- 0x4E44 (R300)
- 0x4E50 (RV350)
- 0x4A49 (R420)
... i.e. pretty much across the board. However, there are many other 
registers that it touches, and I couldn't test how it affects lockups yet.

> ===
> RCS file: /cvsroot/r300/r300_driver/r300/r300_reg.h,v
> retrieving revision 1.41
> diff -u -r1.41 r300_reg.h
> --- r300_reg.h  8 Jun 2005 15:05:24 -   1.41
> +++ r300_reg.h  10 Jun 2005 16:09:22 -
> @@ -1,6 +1,27 @@
>   #ifndef _R300_REG_H
>   #define _R300_REG_H
> 
> +#define R300_MC_INIT_MISC_LAT_TIMER0x180
> +#  define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT  0
> +#  define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT   4
> +#  define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT   8
> +#  define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT   12
> +#  define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT16
> +#  define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT  20
> +#  define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT24
> +#  define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT24

Is the last 24 supposed to be a 28?

> +
> +
> +#define R300_MC_INIT_GFX_LAT_TIMER 0x154
> +#  define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT0
> +#  define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT4
> +#  define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT8
> +#  define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT12
> +#  define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16
> +#  define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20
> +#  define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT24
> +#  define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT0

Is the last 0 supposed to be a 28?

cu,
Nicolai


pgp7aXAA21s8A.pgp
Description: PGP signature


[R300] radeon 9800 lockup & RADEON_LATENCY

2005-06-12 Thread Jerome Glisse
Hi,

After many tests and reboot i have a set of register that
may influence 9800 lockups. Unfortunetly i don't know
how to play with this register as they doesn't seems to be
used anywhere (nor X driver, dri, drm if i trust my grep :))

RADEON_LATENCY the most likely to help to resolve the
lockup. After a cold reboot i read 0x40 in it. I would like to
read 0xff but it seems to be read only and after writing to
some random place near it i can't figure out how to setup
it.

What does this regs do  :
RADEON_BIOS_6_SCRATCH
RADEON_MDGPIO_Y_REG

As this regs appear in radeon reg i hope that some one
with the radeon specs on it could give me anyclue on
how to play or what is there meanings.

Thx

Jerome Glisse


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