Bad entries in the in-kernel tree pci ids list

2007-01-25 Thread Xavier Bachelot
Hi all,

While comparing the pci ids list in the drm tree and in 2.6.19.2 kernel, 
I've spotted 2 entries in the kernel that are most probably not GPUs but 
hostbridges.

from shared-core/drm_pciids.txt in drm tree :

0x1106 0x3022 0 VIA CLE266 3022
0x1106 0x3118 VIA_PRO_GROUP_A VIA CN400 / PM8X0
0x1106 0x3122 0 VIA CLE266
0x1106 0x7205 0 VIA KM400
0x1106 0x3108 0 VIA K8M800
0x1106 0x3344 0 VIA CN700 / VM800 / P4M800Pro
0x1106 0x3343 0 VIA P4M890
0x1106 0x3230 VIA_DX9_0 VIA K8M890

from drivers/char/drm/drm_pciids.h in 2.6.19.2 kernel source :

#define viadrv_PCI_IDS \
 {0x1106, 0x3022, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
 {0x1106, 0x3118, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_PRO_GROUP_A}, \
 {0x1106, 0x3122, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
 {0x1106, 0x7205, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
 {0x1106, 0x3108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
 {0x1106, 0x3304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
 {0x1106, 0x3157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
 {0x1106, 0x3344, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
 {0x1106, 0x7204, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
 {0, 0, 0}


To my knowledge, 0x3304 and 0x7204 are not valid VIA integrated graphic 
chipsets ids. At least 0x7204 is listed as a hostbridge at pciids.sf.net 
(http://pci-ids.ucw.cz/iii/?i=11067204)

Also, 0x3157 is in kernel but not in drm, but that is less of a pb as it 
is a actually a graphic chipset.

Should I bugzilla this, or did I miss something ?

Regards,
Xavier

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Current state

2007-01-25 Thread Dave Brown
Hi there,
 
I've recently become interested in the Nouveau project.  Specifically I'm 
considering looking at porting it to a relatively unknown operating system 
called RISC OS that is based on the ARM processor.  The platform I would be 
targeting currently has uses either a GeForce 2 MX 400 (NV14?) or GeForce 5200 
(NV34) .  I was wondering what the state of support for these chips currently 
is.  Unfortunately the processor in use (XScale IOP80321) doesn't have any form 
of floating point hardware so any support for HW TL/Vertex shaders would be 
seriously beneficial.
 
Thanks for your time,
 
Dave
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Re: Current state

2007-01-25 Thread Stephane Marchesin
Dave Brown wrote:
 Hi there,
  
 I've recently become interested in the Nouveau project.  Specifically 
 I'm considering looking at porting it to a relatively unknown 
 operating system called RISC OS that is based on the ARM processor.  
 The platform I would be targeting currently has uses either a GeForce 
 2 MX 400 (NV14?) or GeForce 5200 (NV34) .  I was wondering what the 
 state of support for these chips currently is.  Unfortunately the 
 processor in use (XScale IOP80321) doesn't have any form of floating 
 point hardware so any support for HW TL/Vertex shaders would be 
 seriously beneficial.

Hello,

Don't expect much for now, we're still working on DRI support. For now 
we can only run a couple of applications (glxgears and some other simple 
tests) and only on some NV40 cards. NV11/NV34 support is still a work in 
progress (but might work any day now :). The current code uses software 
TCL, but with a bit of work we could add hardware TCL (we have the 
required information for that).

Feel free to ask if you have any other questions !

Stephane


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Re: drm: Branch 'master'

2007-01-25 Thread Michel Dänzer
On Thu, 2007-01-25 at 14:06 -0800, Patrice Mandin wrote:
  shared-core/nouveau_fifo.c |   48 
 +++--
  1 files changed, 21 insertions(+), 27 deletions(-)
 
 New commits:
 diff-tree 6d9ef1a960a76410e816425d8a53fb96cf2b871d (from 
 582637641abbadc75795ac7e0671e1a5e3b41880)
 Author: Patrice Mandin [EMAIL PROTECTED]
 Date:   Thu Jan 25 23:06:48 2007 +0100
 
 nouveau: simplify and fix BIG_ENDIAN flags
 
 diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c
 index e80ba76..b035ed0 100644
 --- a/shared-core/nouveau_fifo.c
 +++ b/shared-core/nouveau_fifo.c
 @@ -182,16 +182,15 @@ int nouveau_fifo_init(drm_device_t *dev)
   NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x);
   NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x);
   NV_WRITE(NV_PFIFO_CACH1_ENG, 0x);
 -#ifdef __BIG_ENDIAN
 +
   NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
 NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
 NV_PFIFO_CACH1_DMAF_MAX_REQS_4 |
 -   NV_PFIFO_CACH1_BIG_ENDIAN);
 -#else
 - NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
 -   NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES | 
 -   NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
 -#endif
 +#ifdef __BIG_ENDIAN

Note that __BIG/LITTLE_ENDIAN on their own don't indicate the native
byte order; e.g. on ppc they're both defined. You should probably use
MESA_BIG_ENDIAN or _mesa_little_endian().


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Libre software enthusiast |  Debian, X and DRI developer


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