date:20180708

imaging

2018-07-08 Thread Julie Allen


We would like to introduce our image editing services for you.

We would appreciate if you can reply with your requirements and can give us
a chance to serve you.

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. Cut out, masking, clipping path, deep etching, transparent background
. Colour correction, black and white, light and shadows etc.
. Dust cleaning, spot cleaning
. Beauty retouching, skin retouching, face retouching, body retouching
. Fashion/Beauty Image Retouching
. Product image Retouching
. Real estate image Retouching
. Wedding & Event Album Design.
. Vector Conversion
. Portrait image Retouching

We deliver the work within 24-48 hours.
We can give you editing test on your photos.

Please reply if you have interests.

Thanks,
Julie

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you need photos

2018-07-08 Thread Julie Allen


We would like to introduce our image editing services for you.

We would appreciate if you can reply with your requirements and can give us
a chance to serve you.

Our mainly services are:

. Cut out, masking, clipping path, deep etching, transparent background
. Colour correction, black and white, light and shadows etc.
. Dust cleaning, spot cleaning
. Beauty retouching, skin retouching, face retouching, body retouching
. Fashion/Beauty Image Retouching
. Product image Retouching
. Real estate image Retouching
. Wedding & Event Album Design.
. Vector Conversion
. Portrait image Retouching

We deliver the work within 24-48 hours.
We can give you editing test on your photos.

Please reply if you have interests.

Thanks,
Julie

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[PATCH 1/6] staging: rtl8723bs: replace while with shorter for loop

2018-07-08 Thread Michael Straube

Simplify rtw_get_rateset_len() by replacing the while loop
with a shorter for loop.

Signed-off-by: Michael Straube 
---
 drivers/staging/rtl8723bs/core/rtw_ieee80211.c | 12 +++-
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/staging/rtl8723bs/core/rtw_ieee80211.c 
b/drivers/staging/rtl8723bs/core/rtw_ieee80211.c
index 8e0025e1ff14..9b60e0214bd8 100644
--- a/drivers/staging/rtl8723bs/core/rtw_ieee80211.c
+++ b/drivers/staging/rtl8723bs/core/rtw_ieee80211.c
@@ -298,17 +298,11 @@ void rtw_set_supported_rate(u8 *SupportedRates, uint mode)
 
 uint   rtw_get_rateset_len(u8 *rateset)
 {
-   uint i = 0;
+   uint i;
 
-   while (1) {
-   if ((rateset[i]) == 0)
-   break;
-
-   if (i > 12)
+   for (i = 0; i < 13; i++)
+   if (rateset[i] == 0)
break;
-
-   i++;
-   }
return i;
 }
 
-- 
2.18.0

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[PATCH 2/6] staging: rtl8723bs: replace tab with space

2018-07-08 Thread Michael Straube

Replace tabs with spaces in some function definitions.

Signed-off-by: Michael Straube 
---
 drivers/staging/rtl8723bs/core/rtw_ieee80211.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/staging/rtl8723bs/core/rtw_ieee80211.c 
b/drivers/staging/rtl8723bs/core/rtw_ieee80211.c
index 9b60e0214bd8..429ec929fa1a 100644
--- a/drivers/staging/rtl8723bs/core/rtw_ieee80211.c
+++ b/drivers/staging/rtl8723bs/core/rtw_ieee80211.c
@@ -67,7 +67,7 @@ int rtw_get_bit_value_from_ieee_value(u8 val)
return 0;
 }
 
-uint   rtw_is_cckrates_included(u8 *rate)
+uint rtw_is_cckrates_included(u8 *rate)
 {
u32 i = 0;
 
@@ -81,7 +81,7 @@ uint  rtw_is_cckrates_included(u8 *rate)
return false;
 }
 
-uint   rtw_is_cckratesonly_included(u8 *rate)
+uint rtw_is_cckratesonly_included(u8 *rate)
 {
u32 i = 0;
 
@@ -296,7 +296,7 @@ void rtw_set_supported_rate(u8 *SupportedRates, uint mode)
}
 }
 
-uint   rtw_get_rateset_len(u8 *rateset)
+uint rtw_get_rateset_len(u8 *rateset)
 {
uint i;
 
-- 
2.18.0

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[PATCH 4/6] staging: rtl8723bs: remove blank lines

2018-07-08 Thread Michael Straube

Remove unrequired blank lines as reported by checkpatch.

Signed-off-by: Michael Straube 
---
 .../staging/rtl8723bs/core/rtw_ieee80211.c| 31 ---
 1 file changed, 31 deletions(-)

diff --git a/drivers/staging/rtl8723bs/core/rtw_ieee80211.c 
b/drivers/staging/rtl8723bs/core/rtw_ieee80211.c
index adf216de113b..ab1174f7c83a 100644
--- a/drivers/staging/rtl8723bs/core/rtw_ieee80211.c
+++ b/drivers/staging/rtl8723bs/core/rtw_ieee80211.c
@@ -53,11 +53,9 @@ static u8 WIFI_OFDMRATES[] = {
IEEE80211_OFDM_RATE_54MB
 };
 
-
 int rtw_get_bit_value_from_ieee_value(u8 val)
 {
unsigned char dot11_rate_table[] = {2, 4, 11, 22, 12, 18, 24, 36, 48, 
72, 96, 108, 0}; /*  last element must be zero!! */
-
int i = 0;
while (dot11_rate_table[i] != 0) {
if (dot11_rate_table[i] == val)
@@ -85,7 +83,6 @@ uint rtw_is_cckratesonly_included(u8 *rate)
 {
u32 i = 0;
 
-
while (rate[i] != 0) {
if  rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) &&
 (((rate[i]) & 0x7f) != 11)  && (((rate[i]) & 0x7f) != 22))
@@ -111,7 +108,6 @@ int rtw_check_network_type(unsigned char *rate, int 
ratelen, int channel)
else
return WIRELESS_11G;
}
-
 }
 
 u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char 
*source,
@@ -191,7 +187,6 @@ u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, 
u8 oui_len, u8 *ie, u
uint cnt;
u8 *target_ie = NULL;
 
-
if (ielen)
*ielen = 0;
 
@@ -215,7 +210,6 @@ u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, 
u8 oui_len, u8 *ie, u
} else{
cnt += in_ie[cnt+1]+2; /* goto next */
}
-
}
 
return target_ie;
@@ -292,7 +286,6 @@ void rtw_set_supported_rate(u8 *SupportedRates, uint mode)
memcpy(SupportedRates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN);
memcpy(SupportedRates + IEEE80211_CCK_RATE_LEN, WIFI_OFDMRATES, 
IEEE80211_NUM_OFDM_RATESLEN);
break;
-
}
 }
 
@@ -363,7 +356,6 @@ int rtw_generate_ie(struct registry_priv *pregistrypriv)
/* DS parameter set */
ie = rtw_set_ie(ie, _DSSET_IE_, 1, (u8 
*)&(pdev_network->Configuration.DSConfig), &sz);
 
-
/* IBSS Parameter Set */
 
ie = rtw_set_ie(ie, _IBSS_PARA_IE_, 2, (u8 
*)&(pdev_network->Configuration.ATIMWindow), &sz);
@@ -398,10 +390,8 @@ unsigned char *rtw_get_wpa_ie(unsigned char *pie, int 
*wpa_ie_len, int limit)
pbuf = rtw_get_ie(pbuf, _WPA_IE_ID_, &len, limit_new);
 
if (pbuf) {
-
/* check if oui matches... */
if (memcmp((pbuf + 2), wpa_oui_type, 
sizeof(wpa_oui_type))) {
-
goto check_next_ie;
}
 
@@ -417,7 +407,6 @@ unsigned char *rtw_get_wpa_ie(unsigned char *pie, int 
*wpa_ie_len, int limit)
return pbuf;
 
} else{
-
*wpa_ie_len = 0;
return NULL;
}
@@ -430,20 +419,16 @@ unsigned char *rtw_get_wpa_ie(unsigned char *pie, int 
*wpa_ie_len, int limit)
break;
 
pbuf += (2 + len);
-
}
 
*wpa_ie_len = 0;
 
return NULL;
-
 }
 
 unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit)
 {
-
return rtw_get_ie(pie, _WPA2_IE_ID_, rsn_ie_len, limit);
-
 }
 
 int rtw_get_wpa_cipher_suite(u8 *s)
@@ -478,7 +463,6 @@ int rtw_get_wpa2_cipher_suite(u8 *s)
return 0;
 }
 
-
 int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int 
*pairwise_cipher, int *is_8021x)
 {
int i, ret = _SUCCESS;
@@ -491,7 +475,6 @@ int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int 
*group_cipher, int *pairwis
return _FAIL;
}
 
-
if ((*wpa_ie != _WPA_IE_ID_) || (*(wpa_ie+1) != (u8)(wpa_ie_len - 2)) ||
   (memcmp(wpa_ie+2, RTW_WPA_OUI_TYPE, WPA_SELECTOR_LEN))) {
return _FAIL;
@@ -502,10 +485,8 @@ int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int 
*group_cipher, int *pairwis
pos += 8;
left = wpa_ie_len - 8;
 
-
/* group_cipher */
if (left >= WPA_SELECTOR_LEN) {
-
*group_cipher = rtw_get_wpa_cipher_suite(pos);
 
pos += WPA_SELECTOR_LEN;
@@ -517,7 +498,6 @@ int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int 
*group_cipher, int *pairwis
return _FAIL;
}
 
-
/* pairwise_cipher */
if (left >= 2) {
/* count = le16_to_cpu(*(u16*)pos); */
@@ -554,7 +534,6 @@ int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int 
*group_cipher, int *pairwis
}
 
return ret;
-
 }
 
 int rtw_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher, int 
*pairwise_cipher, int *is_8021x)
@

[PATCH 6/6] staging: rtl8723bs: remove braces from single if statement

2018-07-08 Thread Michael Straube

Remove braces from single if statement to follow kernel coding style.

Signed-off-by: Michael Straube 
---
 drivers/staging/rtl8723bs/core/rtw_ieee80211.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/staging/rtl8723bs/core/rtw_ieee80211.c 
b/drivers/staging/rtl8723bs/core/rtw_ieee80211.c
index a4f9e2b90b08..3f1c7bb0eb9f 100644
--- a/drivers/staging/rtl8723bs/core/rtw_ieee80211.c
+++ b/drivers/staging/rtl8723bs/core/rtw_ieee80211.c
@@ -149,9 +149,8 @@ u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit)
sint tmp, i;
u8 *p;
 
-   if (limit < 1) {
+   if (limit < 1)
return NULL;
-   }
 
p = pbuf;
i = 0;
-- 
2.18.0

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[PATCH 5/6] staging: rtl8723bs: add missing blank lines

2018-07-08 Thread Michael Straube

Add missing blank lines after declarations as reported by checkpatch.

Signed-off-by: Michael Straube 
---
 drivers/staging/rtl8723bs/core/rtw_ieee80211.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/staging/rtl8723bs/core/rtw_ieee80211.c 
b/drivers/staging/rtl8723bs/core/rtw_ieee80211.c
index ab1174f7c83a..a4f9e2b90b08 100644
--- a/drivers/staging/rtl8723bs/core/rtw_ieee80211.c
+++ b/drivers/staging/rtl8723bs/core/rtw_ieee80211.c
@@ -57,6 +57,7 @@ int rtw_get_bit_value_from_ieee_value(u8 val)
 {
unsigned char dot11_rate_table[] = {2, 4, 11, 22, 12, 18, 24, 36, 48, 
72, 96, 108, 0}; /*  last element must be zero!! */
int i = 0;
+
while (dot11_rate_table[i] != 0) {
if (dot11_rate_table[i] == val)
return BIT(i);
@@ -1139,6 +1140,7 @@ static int rtw_get_cipher_info(struct wlan_network 
*pnetwork)
unsigned char *pbuf;
int group_cipher = 0, pairwise_cipher = 0, is8021x = 0;
int ret = _FAIL;
+
pbuf = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &wpa_ielen, 
pnetwork->network.IELength-12);
 
if (pbuf && (wpa_ielen > 0)) {
-- 
2.18.0

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[PATCH 3/6] staging: rtl8723bs: fix indentation

2018-07-08 Thread Michael Straube

Remove unrequired extra indentations.

Signed-off-by: Michael Straube 
---
 drivers/staging/rtl8723bs/core/rtw_ieee80211.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/staging/rtl8723bs/core/rtw_ieee80211.c 
b/drivers/staging/rtl8723bs/core/rtw_ieee80211.c
index 429ec929fa1a..adf216de113b 100644
--- a/drivers/staging/rtl8723bs/core/rtw_ieee80211.c
+++ b/drivers/staging/rtl8723bs/core/rtw_ieee80211.c
@@ -69,16 +69,16 @@ int rtw_get_bit_value_from_ieee_value(u8 val)
 
 uint rtw_is_cckrates_included(u8 *rate)
 {
-   u32 i = 0;
+   u32 i = 0;
 
-   while (rate[i] !=  0) {
-   if  rate[i]) & 0x7f) == 2)  || (((rate[i]) & 0x7f) 
== 4) ||
-(((rate[i]) & 0x7f) == 11)  || (((rate[i]) & 0x7f) 
== 22))
-   return true;
-   i++;
-   }
+   while (rate[i] !=  0) {
+   if  rate[i]) & 0x7f) == 2)  || (((rate[i]) & 0x7f) == 4) ||
+(((rate[i]) & 0x7f) == 11)  || (((rate[i]) & 0x7f) == 22))
+   return true;
+   i++;
+   }
 
-   return false;
+   return false;
 }
 
 uint rtw_is_cckratesonly_included(u8 *rate)
-- 
2.18.0

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[PATCH 1/2] staging: rtl8188eu: refactor rtw_macaddr_cfg()

2018-07-08 Thread Michael Straube

Use ether_addr_copy() instead of memcpy() to copy the mac address.

Using is_broadcast_ether_addr() and is_zero_ether_addr() instead of
testing each byte of the mac[] array for 0xff and 0x00 shortens the
code and improves readability.

Instead of a fixed default mac address use a random one to reduce the
likelihood of mac address collision.

Signed-off-by: Michael Straube 
---
 .../staging/rtl8188eu/core/rtw_ieee80211.c| 20 +--
 1 file changed, 5 insertions(+), 15 deletions(-)

diff --git a/drivers/staging/rtl8188eu/core/rtw_ieee80211.c 
b/drivers/staging/rtl8188eu/core/rtw_ieee80211.c
index 711ebb0ad640..e6dff44e00fd 100644
--- a/drivers/staging/rtl8188eu/core/rtw_ieee80211.c
+++ b/drivers/staging/rtl8188eu/core/rtw_ieee80211.c
@@ -917,25 +917,15 @@ void rtw_macaddr_cfg(u8 *mac_addr)
 
if (rtw_initmac && mac_pton(rtw_initmac, mac)) {
/* Users specify the mac address */
-   memcpy(mac_addr, mac, ETH_ALEN);
+   ether_addr_copy(mac_addr, mac);
} else {
/* Use the mac address stored in the Efuse */
-   memcpy(mac, mac_addr, ETH_ALEN);
+   ether_addr_copy(mac, mac_addr);
}
 
-   if (((mac[0] == 0xff) && (mac[1] == 0xff) && (mac[2] == 0xff) &&
-(mac[3] == 0xff) && (mac[4] == 0xff) && (mac[5] == 0xff)) ||
-   ((mac[0] == 0x0) && (mac[1] == 0x0) && (mac[2] == 0x0) &&
-(mac[3] == 0x0) && (mac[4] == 0x0) && (mac[5] == 0x0))) {
-   mac[0] = 0x00;
-   mac[1] = 0xe0;
-   mac[2] = 0x4c;
-   mac[3] = 0x87;
-   mac[4] = 0x00;
-   mac[5] = 0x00;
-   /*  use default mac address */
-   memcpy(mac_addr, mac, ETH_ALEN);
-   DBG_88E("MAC Address from efuse error, assign default one 
!!!\n");
+   if (is_broadcast_ether_addr(mac) || is_zero_ether_addr(mac)) {
+   eth_random_addr(mac_addr);
+   DBG_88E("MAC Address from efuse error, assign random one 
!!!\n");
}
 
DBG_88E("%s MAC Address  = %pM\n", __func__, (mac_addr));
-- 
2.18.0

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[PATCH 2/2] staging: rtl8188eu: replace tabs with spaces

2018-07-08 Thread Michael Straube

Replace tabs with spaces in some function definitions and variable
declarations.

Signed-off-by: Michael Straube 
---
 drivers/staging/rtl8188eu/core/rtw_ieee80211.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/staging/rtl8188eu/core/rtw_ieee80211.c 
b/drivers/staging/rtl8188eu/core/rtw_ieee80211.c
index e6dff44e00fd..fed33d9acf60 100644
--- a/drivers/staging/rtl8188eu/core/rtw_ieee80211.c
+++ b/drivers/staging/rtl8188eu/core/rtw_ieee80211.c
@@ -73,9 +73,9 @@ int rtw_get_bit_value_from_ieee_value(u8 val)
return 0;
 }
 
-uint   rtw_is_cckrates_included(u8 *rate)
+uint rtw_is_cckrates_included(u8 *rate)
 {
-   u32 i = 0;
+   u32 i = 0;
 
while (rate[i] != 0) {
if  rate[i]) & 0x7f) == 2) || (((rate[i]) & 0x7f) == 4) ||
@@ -86,7 +86,7 @@ uint  rtw_is_cckrates_included(u8 *rate)
return false;
 }
 
-uint   rtw_is_cckratesonly_included(u8 *rate)
+uint rtw_is_cckratesonly_included(u8 *rate)
 {
u32 i = 0;
 
@@ -212,9 +212,9 @@ uint rtw_get_rateset_len(u8 *rateset)
 
 int rtw_generate_ie(struct registry_priv *pregistrypriv)
 {
-   u8  wireless_mode;
-   int rateLen;
-   uintsz = 0;
+   u8 wireless_mode;
+   int rateLen;
+   uint sz = 0;
struct wlan_bssid_ex *pdev_network = &pregistrypriv->dev_network;
u8 *ie = pdev_network->ies;
 
-- 
2.18.0

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[PATCH v2 09/18] staging: mt7621-pci: minor refactor in duplicated code

2018-07-08 Thread Sergio Paracuellos

Use a for loop to check pci port N_FTS in each controller.

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 12 
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 7a8b97a..f882d41 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -490,14 +490,10 @@ static int mt7621_pci_probe(struct platform_device *pdev)
bypass_pipe_rst();
set_phy_for_ssc();
 
-   val = read_config(0, 0x70c);
-   printk("Port 0 N_FTS = %x\n", val);
-
-   val= read_config(1, 0x70c);
-   printk("Port 1 N_FTS = %x\n", val);
-
-   val = read_config(2, 0x70c);
-   printk("Port 2 N_FTS = %x\n", val);
+   for (i = 0; i < PCI_MAX_CONTROLLERS; i++) {
+   val = read_config(0, 0x70c);
+   printk("Port %d N_FTS = %x\n", i, val);
+   }
 
rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
-- 
2.7.4

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[PATCH v2 17/18] staging: mt7621-pci: factor out mt7621_pci_init_gpios function

2018-07-08 Thread Sergio Paracuellos

In driver probe function there are some ugly initialization to
use gpios. Factor out to mt7621_pci_init_gpios function making
use of readl and writel to read and write memory.

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 35 +++--
 1 file changed, 25 insertions(+), 10 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 87c8df4..b4e049a 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -462,6 +462,26 @@ static void mt7621_pci_configure(u8 controller)
write_config(controller, 0x70c, val);
 }
 
+static void mt7621_pci_init_gpios(void)
+{
+   u32 val = readl((u32 *)0xbe60);
+
+   val &= ~(0x3 << 10 | 0x3 << 3);
+   val |= (0x1 << 10 | 0x1 << 3);
+   writel(val, (u32 *)0xbe60);
+   mdelay(100);
+   val = readl((u32 *)0xbe000600);
+   /* use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3) */
+   val |= (0x1 << 19 | 0x1 << 8 | 0x1 << 7);
+   writel(val, (u32 *)0xbe000600);
+   mdelay(100);
+   val = readl((u32 *)0xbe000620);
+   /* clear DATA */
+   val &= ~(0x1 << 19 | 0x1 << 8 | 0x1 << 7);
+   writel(val, (u32 *)0xbe000620);
+   mdelay(100);
+}
+
 static int mt7621_pci_probe(struct platform_device *pdev)
 {
int i;
@@ -477,14 +497,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
val = (RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
mt7621_pcie_assert_sysrst(val);
 
-   *(unsigned int *)(0xbe60) &= ~(0x3<<10 | 0x3<<3);
-   *(unsigned int *)(0xbe60) |= 0x1<<10 | 0x1<<3;
-   mdelay(100);
-   *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use 
GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
-   mdelay(100);
-   *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7);  
// clear DATA
-
-   mdelay(100);
+   mt7621_pci_init_gpios();
 
val = (RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
mt7621_pcie_deassert_sysrst(val);
@@ -509,10 +522,12 @@ static int mt7621_pci_probe(struct platform_device *pdev)
rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL);
 
/* Use GPIO control instead of PERST_N */
-   *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; 
// set DATA
+   val = readl((u32 *)0xbe000620);
+   /* set DATA */
+   val |= (0x1 << 19 | 0x1 << 8 | 0x1 << 7);
+   writel(val, (u32 *)0xbe000620);
mdelay(1000);
 
-
for (i = 0; i < PCI_MAX_CONTROLLERS; i++)
mt7621_pci_enable_irqs(i);
 
-- 
2.7.4

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[PATCH v2 00/18] Some cleanups

2018-07-08 Thread Sergio Paracuellos

This patch series clean up a bit mt7621-pci driver.

Changes from v2:
- It includes new 17 patches from PATCH 2 to PATCH 18
- PATCH 1 was send before alone and is being included
  as it is in this new series.

Hope this helps.

Best regards,
Sergio Paracuellos

Sergio Paracuellos (18):
  staging: mt7621-pci: refactor pci related read and writes functions
  staging: mt7621-pci: simplify pci dependant registers arithmetics
  staging: mt7621-pci: avoid pointer arithmetics in some macros
  staging: mt7621-pci: use BIT macro in definitions
  staging: mt7621-pci: use read and writes in set_pcie_phy function
  staging: mt7621-pci: make ASSERT_SYSRST_PCIE and DEASSERT_SYSRST_PCIE
inline functions
  staging: mt7621-pci: rewrite [read|write]_config functions
  staging: mt7621-pci: factor out mt7621_pci_enable_irqs and
mt7621_pci_disable
  staging: mt7621-pci: minor refactor in duplicated code
  staging: mt7621-pci: factor out mt7621_pci_enable function
  staging: mt7621-pci: factor out mt7621_pci_configure function
  staging: mt7621-pci: add blank line between declarations and code
statements
  staging: mt7621-pci: remove unused preprocessor defines
  staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG
definition
  staging: mt7621-pci: add some common calculations to
mt7621_pci_get_cfgaddr
  staging: mt7621-pci: fix and remove some comments
  staging: mt7621-pci: factor out mt7621_pci_init_gpios function
  staging: mt7621-pci: add SPDX identifier

 drivers/staging/mt7621-pci/pci-mt7621.c | 706 ++--
 1 file changed, 305 insertions(+), 401 deletions(-)

-- 
2.7.4

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[PATCH v2 02/18] staging: mt7621-pci: simplify pci dependant registers arithmetics

2018-07-08 Thread Sergio Paracuellos

PCI controller dependant register was handled with different
custom macros including very ugly pointer aritmethics. Simplify
them adding an array of offset per controller and a macro to get
the relative offset for each register for the controller. To avoid
arithmetics add two simple mt7621_pci_reg_[read|write] functions
where the base is neing taking into account to get and do the correct
operations. Register useds along the code modified to use the new
approach.

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 81 -
 1 file changed, 39 insertions(+), 42 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index dabe5c4..32c37e8 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -79,36 +79,20 @@
 #define RALINK_PCI_BASE0xBE14
 
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
-#define RT6855_PCIE0_OFFSET0x2000
-#define RT6855_PCIE1_OFFSET0x3000
-#define RT6855_PCIE2_OFFSET0x4000
-
-#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE0_OFFSET + 0x0010)
-#define RALINK_PCI0_IMBASEBAR0_ADDR*(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE0_OFFSET + 0x0018)
-#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE0_OFFSET + 0x0030)
-#define RALINK_PCI0_CLASS  *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE0_OFFSET + 0x0034)
-#define RALINK_PCI0_SUBID  *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE0_OFFSET + 0x0038)
-#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE0_OFFSET + 0x0050)
-#define RALINK_PCI0_DERR   *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE0_OFFSET + 0x0060)
-#define RALINK_PCI0_ECRC   *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE0_OFFSET + 0x0064)
-
-#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE1_OFFSET + 0x0010)
-#define RALINK_PCI1_IMBASEBAR0_ADDR*(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE1_OFFSET + 0x0018)
-#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE1_OFFSET + 0x0030)
-#define RALINK_PCI1_CLASS  *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE1_OFFSET + 0x0034)
-#define RALINK_PCI1_SUBID  *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE1_OFFSET + 0x0038)
-#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE1_OFFSET + 0x0050)
-#define RALINK_PCI1_DERR   *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE1_OFFSET + 0x0060)
-#define RALINK_PCI1_ECRC   *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE1_OFFSET + 0x0064)
-
-#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE2_OFFSET + 0x0010)
-#define RALINK_PCI2_IMBASEBAR0_ADDR*(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE2_OFFSET + 0x0018)
-#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE2_OFFSET + 0x0030)
-#define RALINK_PCI2_CLASS  *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE2_OFFSET + 0x0034)
-#define RALINK_PCI2_SUBID  *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE2_OFFSET + 0x0038)
-#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE2_OFFSET + 0x0050)
-#define RALINK_PCI2_DERR   *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE2_OFFSET + 0x0060)
-#define RALINK_PCI2_ECRC   *(volatile u32 *)(RALINK_PCI_BASE + 
RT6855_PCIE2_OFFSET + 0x0064)
+
+static u16 pcie_controller_offsets[] = {
+   0x2000, 0x3000, 0x4000,
+};
+
+#define RALINK_PCI_BAR0SETUP_ADDR(dev) (pcie_controller_offsets[(dev)] + 
0x0010)
+#define RALINK_PCI_IMBASEBAR0_ADDR(dev)(pcie_controller_offsets[(dev)] 
+ 0x0018)
+#define RALINK_PCI_ID(dev) (pcie_controller_offsets[(dev)] + 
0x0030)
+#define RALINK_PCI_CLASS(dev)  (pcie_controller_offsets[(dev)] + 
0x0034)
+#define RALINK_PCI_SUBID(dev)  (pcie_controller_offsets[(dev)] + 
0x0038)
+#define RALINK_PCI_STATUS(dev) (pcie_controller_offsets[(dev)] + 
0x0050)
+#define RALINK_PCI_DERR(dev)   (pcie_controller_offsets[(dev)] + 
0x0060)
+#define RALINK_PCI_ECRC(dev)   (pcie_controller_offsets[(dev)] + 
0x0064)
+
 
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
 #define RALINK_PCIEPHY_P2_CTL_OFFSET   (RALINK_PCI_BASE + 0xA000)
@@ -158,6 +142,16 @@ static int pcie_link_status = 0;
 
 static void __iomem *mt7621_pci_base;
 
+static u32 mt7621_pci_reg_read(u32 reg)
+{
+   return readl(mt7621_pci_base + reg);
+}
+
+static void mt7621_pci_reg_write(u32 val, u32 reg)
+{
+   writel(val, mt7621_pci_base + reg);
+}
+
 static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,

[PATCH v2 16/18] staging: mt7621-pci: fix and remove some comments

2018-07-08 Thread Sergio Paracuellos

There are some comments not needed at all. Remove them.
Adjust one comment to follow kernel style.

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 6286762..87c8df4 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -130,7 +130,6 @@ static struct pcie_controller_data pcie_controllers[] = {
 #define RALINK_PCIE_CLK_GEN0x7c
 #define RALINK_PCIE_CLK_GEN1   0x80
 
-//RALINK_RSTCTRL bit
 #define RALINK_PCIE_RSTBIT(23)
 
 #define MEMORY_BASE 0x0
@@ -282,8 +281,8 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
printk("BAR0 at slot %d = %x\n", slot, val);
}
 
-   pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  //configure 
cache line size 0x14
-   pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);  //configure 
latency timer 0x10
+   pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);
+   pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);
pci_read_config_word(dev, PCI_COMMAND, &cmd);
cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
pci_write_config_word(dev, PCI_COMMAND, cmd);
@@ -404,9 +403,11 @@ void setup_cm_memory_region(struct resource *mem_resource)
resource_size_t mask;
 
if (mips_cps_numiocu(0)) {
-   /* FIXME: hardware doesn't accept mask values with 1s after
+   /*
+* FIXME: hardware doesn't accept mask values with 1s after
 * 0s (e.g. 0xffef), so it would be great to warn if that's
-* about to happen */
+* about to happen
+*/
mask = ~(mem_resource->end - mem_resource->start);
 
write_gcr_reg1_base(mem_resource->start);
-- 
2.7.4

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[PATCH v2 10/18] staging: mt7621-pci: factor out mt7621_pci_enable function

2018-07-08 Thread Sergio Paracuellos

Factor out mt7621_pci_enable function to avoid duplicate code
in driver probe function. This increase readability.

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 36 ++---
 1 file changed, 15 insertions(+), 21 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index f882d41..c41fc18 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -459,6 +459,15 @@ static void mt7621_pci_enable_irqs(u8 controller)
mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
 }
 
+static void mt7621_pci_enable(u8 controller)
+{
+   /* open 7FFF:2G; ENABLE */
+   mt7621_pci_reg_write(0x7FFF0001, RALINK_PCI_BAR0SETUP_ADDR(controller));
+   mt7621_pci_reg_write(MEMORY_BASE, 
RALINK_PCI_IMBASEBAR0_ADDR(controller));
+   mt7621_pci_reg_write(0x06040001, RALINK_PCI_CLASS(controller));
+   printk("PCIE%d enabled\n", controller);
+}
+
 static int mt7621_pci_probe(struct platform_device *pdev)
 {
int i;
@@ -546,31 +555,16 @@ pcie(2/1/0) link status   pcie2_num   pcie1_num   
pcie0_num
mt7621_pci_reg_write(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
 
//PCIe0
-   if ((pcie_link_status & 0x1) != 0) {
-   /* open 7FFF:2G; ENABLE */
-   mt7621_pci_reg_write(0x7FFF0001, RALINK_PCI_BAR0SETUP_ADDR(0));
-   mt7621_pci_reg_write(MEMORY_BASE, 
RALINK_PCI_IMBASEBAR0_ADDR(0));
-   mt7621_pci_reg_write(0x06040001, RALINK_PCI_CLASS(0));
-   printk("PCIE0 enabled\n");
-   }
+   if ((pcie_link_status & 0x1) != 0)
+   mt7621_pci_enable(0);
 
//PCIe1
-   if ((pcie_link_status & 0x2) != 0) {
-   /* open 7FFF:2G; ENABLE */
-   mt7621_pci_reg_write(0x7FFF0001, RALINK_PCI_BAR0SETUP_ADDR(1));
-   mt7621_pci_reg_write(MEMORY_BASE, 
RALINK_PCI_IMBASEBAR0_ADDR(1));
-   mt7621_pci_reg_write(0x06040001, RALINK_PCI_CLASS(1));
-   printk("PCIE1 enabled\n");
-   }
+   if ((pcie_link_status & 0x2) != 0)
+   mt7621_pci_enable(1);
 
//PCIe2
-   if ((pcie_link_status & 0x4) != 0) {
-   /* open 7FFF:2G; ENABLE */
-   mt7621_pci_reg_write(0x7FFF0001, RALINK_PCI_BAR0SETUP_ADDR(2));
-   mt7621_pci_reg_write(MEMORY_BASE, 
RALINK_PCI_IMBASEBAR0_ADDR(2));
-   mt7621_pci_reg_write(0x06040001, RALINK_PCI_CLASS(2));
-   printk("PCIE2 enabled\n");
-   }
+   if ((pcie_link_status & 0x4) != 0)
+   mt7621_pci_enable(2);
 
switch (pcie_link_status) {
case 7:
-- 
2.7.4

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[PATCH v2 06/18] staging: mt7621-pci: make ASSERT_SYSRST_PCIE and DEASSERT_SYSRST_PCIE inline functions

2018-07-08 Thread Sergio Paracuellos

ASSERT_SYSRST_PCIE and DEASSERT_SYSRST_PCIE are defined as preprocessor
macros and can be defined as inline functions instead which are preferred.
Do it and rename to mt7621_pcie_assert_sysrst and mt7621_pcie_deassert_sysrst
respectively.

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 41 +
 1 file changed, 21 insertions(+), 20 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 897485a..afbd278 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -93,27 +93,12 @@ static u16 pcie_controller_offsets[] = {
 #define RALINK_PCI_DERR(dev)   (pcie_controller_offsets[(dev)] + 
0x0060)
 #define RALINK_PCI_ECRC(dev)   (pcie_controller_offsets[(dev)] + 
0x0064)
 
-
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET 0x9000
 #define RALINK_PCIEPHY_P2_CTL_OFFSET   0xA000
 
 #define RALINK_PCI_MM_MAP_BASE 0x6000
 #define RALINK_PCI_IO_MAP_BASE 0x1e16
 
-#define ASSERT_SYSRST_PCIE(val)\
-   do {\
-   if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101)   \
-   rt_sysc_m32(0, val, RALINK_RSTCTRL);\
-   else\
-   rt_sysc_m32(val, 0, RALINK_RSTCTRL);\
-   } while (0)
-#define DEASSERT_SYSRST_PCIE(val)  \
-   do {\
-   if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101)   \
-   rt_sysc_m32(val, 0, RALINK_RSTCTRL);\
-   else\
-   rt_sysc_m32(0, val, RALINK_RSTCTRL);\
-   } while (0)
 #define RALINK_CLKCFG1 0x30
 #define RALINK_RSTCTRL 0x34
 #define RALINK_GPIOMODE0x60
@@ -142,6 +127,22 @@ static int pcie_link_status = 0;
 
 static void __iomem *mt7621_pci_base;
 
+static inline void mt7621_pcie_assert_sysrst(u32 val)
+{
+   if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101)
+   rt_sysc_m32(0, val, RALINK_RSTCTRL);
+   else
+   rt_sysc_m32(val, 0, RALINK_RSTCTRL);
+}
+
+static inline void mt7621_pcie_deassert_sysrst(u32 val)
+{
+   if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101)
+   rt_sysc_m32(val, 0, RALINK_RSTCTRL);
+   else
+   rt_sysc_m32(0, val, RALINK_RSTCTRL);
+}
+
 static u32 mt7621_pci_reg_read(u32 reg)
 {
return readl(mt7621_pci_base + reg);
@@ -424,7 +425,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
val |= RALINK_PCIE1_RST;
val |= RALINK_PCIE2_RST;
 
-   ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | 
RALINK_PCIE2_RST);
+   mt7621_pcie_assert_sysrst(RALINK_PCIE0_RST | RALINK_PCIE1_RST | 
RALINK_PCIE2_RST);
 
*(unsigned int *)(0xbe60) &= ~(0x3<<10 | 0x3<<3);
*(unsigned int *)(0xbe60) |= 0x1<<10 | 0x1<<3;
@@ -439,7 +440,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
val |= RALINK_PCIE1_RST;
val |= RALINK_PCIE2_RST;
 
-   DEASSERT_SYSRST_PCIE(val);
+   mt7621_pcie_deassert_sysrst(val);
 
if ((*(unsigned int *)(0xbe0c)&0x) == 0x0101) // MT7621 E2
bypass_pipe_rst();
@@ -470,7 +471,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 
if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(0)) & 0x1) == 0) {
printk("PCIE0 no card, disable it(RST&CLK)\n");
-   ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
+   mt7621_pcie_assert_sysrst(RALINK_PCIE0_RST);
rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
pcie_link_status &= ~(1<<0);
} else {
@@ -482,7 +483,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 
if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(1)) & 0x1) == 0) {
printk("PCIE1 no card, disable it(RST&CLK)\n");
-   ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
+   mt7621_pcie_assert_sysrst(RALINK_PCIE1_RST);
rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1);
pcie_link_status &= ~(1<<1);
} else {
@@ -494,7 +495,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 
if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(2)) & 0x1) == 0) {
printk("PCIE2 no card, disable it(RST&CLK)\n");
-   ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
+   mt7621_pcie_assert_sysrst(RALINK_PCIE2_RST);
rt_sysc_m32(RALINK_PCIE2_CLK_EN, 0, RALINK_CLKCFG1);
pcie_link_status &= ~(1<<2);
} else {
-- 
2.7.4

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[PATCH v2 03/18] staging: mt7621-pci: avoid pointer arithmetics in some macros

2018-07-08 Thread Sergio Paracuellos

RALINK_PCI_MEMBASE, RALINK_PCI_IOBASE, RALINK_PCI_PCICFG_ADDR and
RALINK_PCI_PCIMSK_ADDR are using very ugly pointer arithmetics to
read and write along the code. Instead of doing this, use the
mt7621_pci_reg_read and mt7621_pci_reg_write functions making
this a bit cleaner.

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 59 ++---
 1 file changed, 25 insertions(+), 34 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 32c37e8..f7defa7 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -68,14 +68,14 @@
 
 #define RALINK_PCI_CONFIG_ADDR 0x20
 #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
-#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 
0x0028)
-#define RALINK_PCI_IOBASE  *(volatile u32 *)(RALINK_PCI_BASE + 
0x002C)
+#define RALINK_PCI_MEMBASE 0x0028
+#define RALINK_PCI_IOBASE  0x002C
 #define RALINK_PCIE0_RST   (1<<24)
 #define RALINK_PCIE1_RST   (1<<25)
 #define RALINK_PCIE2_RST   (1<<26)
 
-#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 
0x)
-#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 
0x000C)
+#define RALINK_PCI_PCICFG_ADDR 0x
+#define RALINK_PCI_PCIMSK_ADDR 0x000C
 #define RALINK_PCI_BASE0xBE14
 
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
@@ -408,6 +408,7 @@ void setup_cm_memory_region(struct resource *mem_resource)
 
 static int mt7621_pci_probe(struct platform_device *pdev)
 {
+   u32 mask;
unsigned long val = 0;
 
mt7621_pci_base = (void __iomem *)RALINK_PCI_BASE;
@@ -471,7 +472,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
pcie_link_status &= ~(1<<0);
} else {
pcie_link_status |= 1<<0;
-   RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
+   mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
+   mask |= (1<<20); // enable pcie1 interrupt
+   mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
}
 
if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(1)) & 0x1) == 0) {
@@ -481,7 +484,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
pcie_link_status &= ~(1<<1);
} else {
pcie_link_status |= 1<<1;
-   RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
+   mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
+   mask |= (1<<21); // enable pcie1 interrupt
+   mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
}
 
if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(2)) & 0x1) == 0) {
@@ -491,7 +496,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
pcie_link_status &= ~(1<<2);
} else {
pcie_link_status |= 1<<2;
-   RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
+   mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
+   mask |= (1<<22); // enable pcie2 interrupt
+   mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
}
 
if (pcie_link_status == 0)
@@ -508,39 +515,23 @@ pcie(2/1/0) link status   pcie2_num   pcie1_num   
pcie0_num
 3'b110 1   0   x
 3'b111 2   1   0
 */
-   switch (pcie_link_status) {
-   case 2:
-   RALINK_PCI_PCICFG_ADDR &= ~0x00ff;
-   RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;//port0
-   RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;//port1
-   break;
-   case 4:
-   RALINK_PCI_PCICFG_ADDR &= ~0x0fff;
-   RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;//port0
-   RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;//port1
-   RALINK_PCI_PCICFG_ADDR |= 0x0 << 24;//port2
-   break;
-   case 5:
-   RALINK_PCI_PCICFG_ADDR &= ~0x0fff;
-   RALINK_PCI_PCICFG_ADDR |= 0x0 << 16;//port0
-   RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;//port1
-   RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;//port2
-   break;
-   case 6:
-   RALINK_PCI_PCICFG_ADDR &= ~0x0fff;
-   RALINK_PCI_PCICFG_ADDR |= 0x2 << 16;//port0
-   RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;//port1
-   RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;//port2
-   break;
-   }
+   mask = mt7621_pci_reg_read(RALINK_PCI_PCICFG_ADDR);
+   mask &= ~0x00ff;
+   mask |= (0x1 << 16); // port0
+   mask |= (0x0 << 20); // port1
+
+   if (pcie_link_status != 2)
+   mask |= (0x1 << 24); // port2
+
+   mt7621

[PATCH v2 18/18] staging: mt7621-pci: add SPDX identifier

2018-07-08 Thread Sergio Paracuellos

It's good to have SPDX identifiers in driver files to make it easier to
audit the kernel tree for correct licenses.

Fix up the one of staging pci-mt7621.c file to have a proper SPDX
identifier, based on the license text in the file itself. The SPDX
identifier is a legally binding shorthand, which can be used instead of
the full boiler plate text.

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 28 ++--
 1 file changed, 2 insertions(+), 26 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index b4e049a..d92df91 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -1,32 +1,10 @@
-/**
- *
+// SPDX-License-Identifier: GPL-2.0
+/*
  *  BRIEF MODULE DESCRIPTION
  * PCI init for Ralink RT2880 solution
  *
  *  Copyright 2007 Ralink Inc. (bruce_ch...@ralinktech.com.tw)
  *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BELIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *
- **
  * May 2007 Bruce Chang
  * Initial Release
  *
@@ -35,8 +13,6 @@
  *
  * May 2011 Bruce Chang
  * support RT6855/MT7620 PCIe
- *
- **
  */
 
 #include 
-- 
2.7.4

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[PATCH v2 04/18] staging: mt7621-pci: use BIT macro in definitions

2018-07-08 Thread Sergio Paracuellos

There are some definitions which are using its custom
implementation of BIT macro. Just just BIT macro instead.

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 31 ---
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index f7defa7..904181c 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -39,6 +39,7 @@
  **
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -62,17 +63,17 @@
  * devices.
  */
 
-#define RALINK_PCIE0_CLK_EN(1<<24)
-#define RALINK_PCIE1_CLK_EN(1<<25)
-#define RALINK_PCIE2_CLK_EN(1<<26)
+#define RALINK_PCIE0_CLK_ENBIT(24)
+#define RALINK_PCIE1_CLK_ENBIT(25)
+#define RALINK_PCIE2_CLK_ENBIT(26)
 
 #define RALINK_PCI_CONFIG_ADDR 0x20
 #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
 #define RALINK_PCI_MEMBASE 0x0028
 #define RALINK_PCI_IOBASE  0x002C
-#define RALINK_PCIE0_RST   (1<<24)
-#define RALINK_PCIE1_RST   (1<<25)
-#define RALINK_PCIE2_RST   (1<<26)
+#define RALINK_PCIE0_RST   BIT(24)
+#define RALINK_PCIE1_RST   BIT(25)
+#define RALINK_PCIE2_RST   BIT(26)
 
 #define RALINK_PCI_PCICFG_ADDR 0x
 #define RALINK_PCI_PCIMSK_ADDR 0x000C
@@ -122,20 +123,20 @@ static u16 pcie_controller_offsets[] = {
 #define PPLL_CFG1  0x9c
 #define PPLL_DRV   0xa0
 /* SYSC_REG_SYSTEM_CONFIG1 bits */
-#define RALINK_PCI_HOST_MODE_EN(1<<7)
-#define RALINK_PCIE_RC_MODE_EN (1<<8)
+#define RALINK_PCI_HOST_MODE_ENBIT(7)
+#define RALINK_PCIE_RC_MODE_EN BIT(8)
 //RALINK_RSTCTRL bit
-#define RALINK_PCIE_RST(1<<23)
-#define RALINK_PCI_RST (1<<24)
+#define RALINK_PCIE_RSTBIT(23)
+#define RALINK_PCI_RST BIT(24)
 //RALINK_CLKCFG1 bit
-#define RALINK_PCI_CLK_EN  (1<<19)
-#define RALINK_PCIE_CLK_EN (1<<21)
+#define RALINK_PCI_CLK_EN  BIT(19)
+#define RALINK_PCIE_CLK_EN BIT(21)
 //RALINK_GPIOMODE bit
-#define PCI_SLOTx2 (1<<11)
+#define PCI_SLOTx2 BIT(11)
 #define PCI_SLOTx1 (2<<11)
 //MTK PCIE PLL bit
-#define PDRV_SW_SET(1<<31)
-#define LC_CKDRVPD_(1<<19)
+#define PDRV_SW_SETBIT(31)
+#define LC_CKDRVPD_BIT(19)
 
 #define MEMORY_BASE 0x0
 static int pcie_link_status = 0;
-- 
2.7.4

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[PATCH v2 12/18] staging: mt7621-pci: add blank line between declarations and code statements

2018-07-08 Thread Sergio Paracuellos

There was a missing line between declarations and code statements in function
setup_cm_memory_region. this improves readability.

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 5d56f84..5871e32 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -422,6 +422,7 @@ set_phy_for_ssc(void)
 void setup_cm_memory_region(struct resource *mem_resource)
 {
resource_size_t mask;
+
if (mips_cps_numiocu(0)) {
/* FIXME: hardware doesn't accept mask values with 1s after
 * 0s (e.g. 0xffef), so it would be great to warn if that's
-- 
2.7.4

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[PATCH v2 01/18] staging: mt7621-pci: refactor pci related read and writes functions

2018-07-08 Thread Sergio Paracuellos

This commit simplifies and clean a lot of stuff related with pci
reads and writes. It deletes a lot of not needed at all functions
and use kernel arch operations read[b,w,l] and write[b,w,l] instead
of use custom macros. It also include one function helper called
'mt7621_pci_get_cfgaddr' to easily obtain config address. Also to
get pci base address a global 'mt7621_pci_base' variable has been
included and initialized as a pointer to RALINK_PCI_BASE in driver
probe function. With this changes LOC is clearly decreased and
readability is increased.

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 178 +++-
 1 file changed, 58 insertions(+), 120 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index c12447d..dabe5c4 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -113,23 +113,6 @@
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
 #define RALINK_PCIEPHY_P2_CTL_OFFSET   (RALINK_PCI_BASE + 0xA000)
 
-#define MV_WRITE(ofs, data)\
-   *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
-#define MV_READ(ofs, data) \
-   *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
-#define MV_READ_DATA(ofs)  \
-   le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
-
-#define MV_WRITE_16(ofs, data) \
-   *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
-#define MV_READ_16(ofs, data)  \
-   *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
-
-#define MV_WRITE_8(ofs, data)  \
-   *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
-#define MV_READ_8(ofs, data)   \
-   *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
-
 #define RALINK_PCI_MM_MAP_BASE 0x6000
 #define RALINK_PCI_IO_MAP_BASE 0x1e16
 
@@ -173,123 +156,75 @@
 #define MEMORY_BASE 0x0
 static int pcie_link_status = 0;
 
-#define PCI_ACCESS_READ_1  0
-#define PCI_ACCESS_READ_2  1
-#define PCI_ACCESS_READ_4  2
-#define PCI_ACCESS_WRITE_1 3
-#define PCI_ACCESS_WRITE_2 4
-#define PCI_ACCESS_WRITE_4 5
+static void __iomem *mt7621_pci_base;
 
-static int config_access(unsigned char access_type, struct pci_bus *bus,
-   unsigned int devfn, unsigned int where, u32 *data)
+static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
+unsigned int func, unsigned int where)
 {
-   unsigned int slot = PCI_SLOT(devfn);
-   u8 func = PCI_FUNC(devfn);
-   uint32_t address_reg, data_reg;
-   unsigned int address;
+   return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
+   0x8000);
+}
+
+static int
+pci_config_read(struct pci_bus *bus, unsigned int devfn,
+   int where, int size, u32 *val)
+{
+   u32 address_reg, data_reg;
+   u32 address;
 
address_reg = RALINK_PCI_CONFIG_ADDR;
data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
 
-   address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) |
-   (func << 8) | (where & 0xfc) | 0x8000;
-   MV_WRITE(address_reg, address);
+   address = (((where & 0xF00) >> 8) << 24) |
+  mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+ PCI_FUNC(devfn), where);
 
-   switch (access_type) {
-   case PCI_ACCESS_WRITE_1:
-   MV_WRITE_8(data_reg+(where&0x3), *data);
-   break;
-   case PCI_ACCESS_WRITE_2:
-   MV_WRITE_16(data_reg+(where&0x3), *data);
-   break;
-   case PCI_ACCESS_WRITE_4:
-   MV_WRITE(data_reg, *data);
-   break;
-   case PCI_ACCESS_READ_1:
-   MV_READ_8(data_reg+(where&0x3), data);
-   break;
-   case PCI_ACCESS_READ_2:
-   MV_READ_16(data_reg+(where&0x3), data);
+   writel(address, mt7621_pci_base + address_reg);
+
+   switch (size) {
+   case 1:
+   *val = readb(mt7621_pci_base + data_reg + (where & 0x3));
break;
-   case PCI_ACCESS_READ_4:
-   MV_READ(data_reg, data);
+   case 2:
+   *val = readw(mt7621_pci_base + data_reg + (where & 0x3));
break;
-   default:
-   printk("no specify access type\n");
+   case 4:
+   *val = readl(mt7621_pci_base + data_reg);
break;
}
-   return 0;
-}
-
-static int
-read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 *val)
-{
-   return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned 
int)where, (u32 *)val);
-}
-
-static int
-read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 *val)
-{
-   return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned 
int)where, (u32 *)val);
-}
-
-static int
-read_config_

[PATCH v2 08/18] staging: mt7621-pci: factor out mt7621_pci_enable_irqs and mt7621_pci_disable

2018-07-08 Thread Sergio Paracuellos

Driver probe function is a mess and need a very big refactor.
Factor out mt7621_pci_enable_irqs and mt7621_pci_disable to
handle interrupts if pci status is as expected. To get the correct
bits for each controller define a new 'pcie_controller_data'
including clk_en, rst, irq and offset fields. Controller number
will be the array index 'pcie_controllers' which subs the 'offsets'
array.

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 120 ++--
 1 file changed, 67 insertions(+), 53 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 39efde1..7a8b97a 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -63,6 +63,8 @@
  * devices.
  */
 
+#define PCI_MAX_CONTROLLERS3
+
 #define RALINK_PCIE0_CLK_ENBIT(24)
 #define RALINK_PCIE1_CLK_ENBIT(25)
 #define RALINK_PCIE2_CLK_ENBIT(26)
@@ -74,24 +76,50 @@
 #define RALINK_PCIE0_RST   BIT(24)
 #define RALINK_PCIE1_RST   BIT(25)
 #define RALINK_PCIE2_RST   BIT(26)
+#define RALINK_PCIE0_IRQ   BIT(20)
+#define RALINK_PCIE1_IRQ   BIT(21)
+#define RALINK_PCIE2_IRQ   BIT(22)
 
 #define RALINK_PCI_PCICFG_ADDR 0x
 #define RALINK_PCI_PCIMSK_ADDR 0x000C
 #define RALINK_PCI_BASE0xBE14
 
+struct pcie_controller_data {
+   u32 offset;
+   u32 clk_en;
+   u32 rst;
+   u32 irq;
+};
 
-static u16 pcie_controller_offsets[] = {
-   0x2000, 0x3000, 0x4000,
+static struct pcie_controller_data pcie_controllers[] = {
+   {
+   .offset = 0x2000,
+   .clk_en = RALINK_PCIE0_CLK_EN,
+   .rst = RALINK_PCIE0_RST,
+   .irq = RALINK_PCIE0_IRQ,
+   },
+   {
+   .offset = 0x3000,
+   .clk_en = RALINK_PCIE1_CLK_EN,
+   .rst = RALINK_PCIE1_RST,
+   .irq = RALINK_PCIE1_IRQ,
+   },
+   {
+   .offset = 0x4000,
+   .clk_en = RALINK_PCIE2_CLK_EN,
+   .rst = RALINK_PCIE2_RST,
+   .irq = RALINK_PCIE2_IRQ,
+   },
 };
 
-#define RALINK_PCI_BAR0SETUP_ADDR(dev) (pcie_controller_offsets[(dev)] + 
0x0010)
-#define RALINK_PCI_IMBASEBAR0_ADDR(dev)(pcie_controller_offsets[(dev)] 
+ 0x0018)
-#define RALINK_PCI_ID(dev) (pcie_controller_offsets[(dev)] + 
0x0030)
-#define RALINK_PCI_CLASS(dev)  (pcie_controller_offsets[(dev)] + 
0x0034)
-#define RALINK_PCI_SUBID(dev)  (pcie_controller_offsets[(dev)] + 
0x0038)
-#define RALINK_PCI_STATUS(dev) (pcie_controller_offsets[(dev)] + 
0x0050)
-#define RALINK_PCI_DERR(dev)   (pcie_controller_offsets[(dev)] + 
0x0060)
-#define RALINK_PCI_ECRC(dev)   (pcie_controller_offsets[(dev)] + 
0x0064)
+#define RALINK_PCI_BAR0SETUP_ADDR(dev) (pcie_controllers[(dev)].offset + 
0x0010)
+#define RALINK_PCI_IMBASEBAR0_ADDR(dev)(pcie_controllers[(dev)].offset 
+ 0x0018)
+#define RALINK_PCI_ID(dev) (pcie_controllers[(dev)].offset + 
0x0030)
+#define RALINK_PCI_CLASS(dev)  (pcie_controllers[(dev)].offset + 
0x0034)
+#define RALINK_PCI_SUBID(dev)  (pcie_controllers[(dev)].offset + 
0x0038)
+#define RALINK_PCI_STATUS(dev) (pcie_controllers[(dev)].offset + 
0x0050)
+#define RALINK_PCI_DERR(dev)   (pcie_controllers[(dev)].offset + 
0x0060)
+#define RALINK_PCI_ECRC(dev)   (pcie_controllers[(dev)].offset + 
0x0064)
 
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET 0x9000
 #define RALINK_PCIEPHY_P2_CTL_OFFSET   0xA000
@@ -408,8 +436,32 @@ void setup_cm_memory_region(struct resource *mem_resource)
}
 }
 
+static void mt7621_pci_disable(u8 controller)
+{
+   mt7621_pcie_assert_sysrst(pcie_controllers[controller].rst);
+   rt_sysc_m32(pcie_controllers[controller].clk_en, 0, RALINK_CLKCFG1);
+   pcie_link_status &= ~(1 << controller);
+}
+
+static void mt7621_pci_enable_irqs(u8 controller)
+{
+   u32 mask;
+
+   if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(controller)) & 0x1) == 0) {
+   printk("PCIE0 no card, disable it(RST&CLK)\n");
+   mt7621_pci_disable(controller);
+   return;
+   }
+
+   pcie_link_status |= (1 << controller);
+   mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
+   mask |= pcie_controllers[controller].irq;
+   mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
+}
+
 static int mt7621_pci_probe(struct platform_device *pdev)
 {
+   int i;
u32 mask;
u32 val;
 
@@ -419,11 +471,8 @@ static int mt7621_pci_probe(struct platform_device *pdev)
ioport_resource.start = 0;
ioport_resource.end = ~0;
 
-   val = RALINK_PCIE0_RST;
-   val |= RALINK_PCIE1_RST;
-   val |= RALINK_PCIE2_RST;
-
-   mt7621_pcie_assert_sysrst(RALINK_PCIE0_RST | RALINK_PCIE1_RST |

[PATCH v2 15/18] staging: mt7621-pci: add some common calculations to mt7621_pci_get_cfgaddr

2018-07-08 Thread Sergio Paracuellos

In places where function mt7621_pci_get_cfgaddr is being used, there
is a common pattern that could be included inside mt7621_pci_get_cfgaddr.
Include it improving readability.

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 20 
 1 file changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 55b9342..6286762 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -168,8 +168,8 @@ static void mt7621_pci_reg_write(u32 val, u32 reg)
 static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
 unsigned int func, unsigned int where)
 {
-   return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
-   0x8000);
+   return where & 0xF00) >> 8) << 24) | (bus << 16) | (slot << 11) |
+   (func << 8) | (where & 0xfc) | 0x8000);
 }
 
 static int
@@ -182,9 +182,8 @@ pci_config_read(struct pci_bus *bus, unsigned int devfn,
address_reg = RALINK_PCI_CONFIG_ADDR;
data_reg = RALINK_PCI_CONFIG_DATA;
 
-   address = (((where & 0xF00) >> 8) << 24) |
-  mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
- PCI_FUNC(devfn), where);
+   address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+PCI_FUNC(devfn), where);
 
writel(address, mt7621_pci_base + address_reg);
 
@@ -213,9 +212,8 @@ pci_config_write(struct pci_bus *bus, unsigned int devfn,
address_reg = RALINK_PCI_CONFIG_ADDR;
data_reg = RALINK_PCI_CONFIG_DATA;
 
-   address = (((where & 0xF00) >> 8) << 24) |
-  mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
- PCI_FUNC(devfn), where);
+   address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+PCI_FUNC(devfn), where);
 
writel(address, mt7621_pci_base + address_reg);
 
@@ -254,8 +252,7 @@ read_config(unsigned int dev, u32 reg)
 
address_reg = RALINK_PCI_CONFIG_ADDR;
data_reg = RALINK_PCI_CONFIG_DATA;
-   address = (((reg & 0xF00) >> 8) << 24) |
-  mt7621_pci_get_cfgaddr(0, dev, 0, reg);
+   address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
writel(address, mt7621_pci_base + address_reg);
return readl(mt7621_pci_base + data_reg);
 }
@@ -267,8 +264,7 @@ write_config(unsigned int dev, u32 reg, u32 val)
 
address_reg = RALINK_PCI_CONFIG_ADDR;
data_reg = RALINK_PCI_CONFIG_DATA;
-   address = (((reg & 0xF00) >> 8) << 24) |
-  mt7621_pci_get_cfgaddr(0, dev, 0, reg);
+   address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
writel(address, mt7621_pci_base + address_reg);
writel(val, mt7621_pci_base + data_reg);
 }
-- 
2.7.4

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[PATCH v2 05/18] staging: mt7621-pci: use read and writes in set_pcie_phy function

2018-07-08 Thread Sergio Paracuellos

set_pcie_phy can be refactor to use mt7621_pci_reg_write and
mt7621_pci_reg_read functions intead of use pointer arithmetics.
Use them and simplify implicated calls and definitions along the
code.

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 122 
 1 file changed, 62 insertions(+), 60 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 904181c..897485a 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -79,7 +79,6 @@
 #define RALINK_PCI_PCIMSK_ADDR 0x000C
 #define RALINK_PCI_BASE0xBE14
 
-#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
 
 static u16 pcie_controller_offsets[] = {
0x2000, 0x3000, 0x4000,
@@ -95,8 +94,8 @@ static u16 pcie_controller_offsets[] = {
 #define RALINK_PCI_ECRC(dev)   (pcie_controller_offsets[(dev)] + 
0x0064)
 
 
-#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
-#define RALINK_PCIEPHY_P2_CTL_OFFSET   (RALINK_PCI_BASE + 0xA000)
+#define RALINK_PCIEPHY_P0P1_CTL_OFFSET 0x9000
+#define RALINK_PCIEPHY_P2_CTL_OFFSET   0xA000
 
 #define RALINK_PCI_MM_MAP_BASE 0x6000
 #define RALINK_PCI_IO_MAP_BASE 0x1e16
@@ -289,24 +288,27 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 
pin)
 }
 
 void
-set_pcie_phy(u32 *addr, int start_b, int bits, int val)
+set_pcie_phy(u32 offset, int start_b, int bits, int val)
 {
-   *(unsigned int *)(addr) &= ~(((1<> 6) & 0x7;
/* Set PCIe Port0 & Port1 PHY to disable SSC */
/* Debug Xtal Type */
-   set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  8, 1, 
0x01); // rg_pe1_frc_h_xtal_type
-   set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  9, 2, 
0x00); // rg_pe1_h_xtal_type
-   set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 
0x01); // rg_pe1_frc_phy_en//Force Port 0 enable control
-   set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 
0x01); // rg_pe1_frc_phy_en//Force Port 1 enable control
-   set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 
0x00); // rg_pe1_phy_en//Port 0 disable
-   set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 
0x00); // rg_pe1_phy_en//Port 1 disable
+   set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  8, 1, 0x01);
// rg_pe1_frc_h_xtal_type
+   set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  9, 2, 0x00);
// rg_pe1_h_xtal_type
+   set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x01);
// rg_pe1_frc_phy_en//Force Port 0 enable control
+   set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x01);
// rg_pe1_frc_phy_en//Force Port 1 enable control
+   set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x00);
// rg_pe1_phy_en//Port 0 disable
+   set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x00);
// rg_pe1_phy_en//Port 1 disable
if (reg <= 5 && reg >= 3) { // 40MHz Xtal
-   set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  
6, 2, 0x01); // RG_PE1_H_PLL_PREDIV  //Pre-divider ratio (for host mode)
+   set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 
0x01);// RG_PE1_H_PLL_PREDIV  //Pre-divider ratio (for host mode)
printk("* Xtal 40MHz *\n");
} else {// 25MHz | 20MHz Xtal
-   set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  
6, 2, 0x00); // RG_PE1_H_PLL_PREDIV  //Pre-divider ratio (for host mode)
+   set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 
0x00);// RG_PE1_H_PLL_PREDIV  //Pre-divider ratio (for host mode)
if (reg >= 6) {
printk("* Xtal 25MHz *\n");
-   set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 
0x4bc),  4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL  //Feedback clock select
-   set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 
0x49c),  0, 31, 0x1800);  // RG_PE1_H_LCDDS_PCW_NCPO  //DDS NCPO 
PCW (for host mode)
-   set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 
0x4a4),  0, 16, 0x18d);   // RG_PE1_H_LCDDS_SSC_PRD   //DDS SSC dither 
period control
-   set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 
0x4a8),  0, 12, 0x4a);// RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither 
amplitude control
-   set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 
0x4a8), 16, 12, 0x4a);// RG_PE1_H_LCDDS_SSC_DELTA1//DDS SSC dither 
amplitude control for initial
+   set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc),  
4, 2, 0x01);// RG_P

[PATCH v2 07/18] staging: mt7621-pci: rewrite [read|write]_config functions

2018-07-08 Thread Sergio Paracuellos

This two functions are called with bus and func being always 0.
Remove non sensense 'bus' and 'func' parameters and pass '0' to
other calls inside the function. Review return and parameter types
also to be more proper with the rest of the code. Adapt properly
calls to those function to match the new prototypes.

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 56 -
 1 file changed, 27 insertions(+), 29 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index afbd278..39efde1 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -235,30 +235,28 @@ static struct pci_controller mt7621_controller = {
.io_resource= &mt7621_res_pci_io1,
 };
 
-static void
-read_config(unsigned long bus, unsigned long dev, unsigned long func,
-   unsigned long reg, unsigned long *val)
+static u32
+read_config(unsigned int dev, u32 reg)
 {
u32 address_reg, data_reg, address;
 
address_reg = RALINK_PCI_CONFIG_ADDR;
data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
address = (((reg & 0xF00) >> 8) << 24) |
-  mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+  mt7621_pci_get_cfgaddr(0, dev, 0, reg);
writel(address, mt7621_pci_base + address_reg);
-   *val = readl(mt7621_pci_base + data_reg);
+   return readl(mt7621_pci_base + data_reg);
 }
 
 static void
-write_config(unsigned long bus, unsigned long dev, unsigned long func,
-unsigned long reg, unsigned long val)
+write_config(unsigned int dev, u32 reg, u32 val)
 {
u32 address_reg, data_reg, address;
 
address_reg = RALINK_PCI_CONFIG_ADDR;
data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
address = (((reg & 0xF00) >> 8) << 24) |
-  mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+  mt7621_pci_get_cfgaddr(0, dev, 0, reg);
writel(address, mt7621_pci_base + address_reg);
writel(val, mt7621_pci_base + data_reg);
 }
@@ -271,8 +269,8 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
int irq;
 
if (dev->bus->number == 0) {
-   write_config(0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
-   read_config(0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long 
*)&val);
+   write_config(slot, PCI_BASE_ADDRESS_0, MEMORY_BASE);
+   val = read_config(slot, PCI_BASE_ADDRESS_0);
printk("BAR0 at slot %d = %x\n", slot, val);
}
 
@@ -413,7 +411,7 @@ void setup_cm_memory_region(struct resource *mem_resource)
 static int mt7621_pci_probe(struct platform_device *pdev)
 {
u32 mask;
-   unsigned long val = 0;
+   u32 val;
 
mt7621_pci_base = (void __iomem *)RALINK_PCI_BASE;
iomem_resource.start = 0;
@@ -446,14 +444,14 @@ static int mt7621_pci_probe(struct platform_device *pdev)
bypass_pipe_rst();
set_phy_for_ssc();
 
-   read_config(0, 0, 0, 0x70c, &val);
-   printk("Port 0 N_FTS = %x\n", (unsigned int)val);
+   val = read_config(0, 0x70c);
+   printk("Port 0 N_FTS = %x\n", val);
 
-   read_config(0, 1, 0, 0x70c, &val);
-   printk("Port 1 N_FTS = %x\n", (unsigned int)val);
+   val= read_config(1, 0x70c);
+   printk("Port 1 N_FTS = %x\n", val);
 
-   read_config(0, 2, 0, 0x70c, &val);
-   printk("Port 2 N_FTS = %x\n", (unsigned int)val);
+   val = read_config(2, 0x70c);
+   printk("Port 2 N_FTS = %x\n", val);
 
rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
@@ -566,28 +564,28 @@ pcie(2/1/0) link status   pcie2_num   pcie1_num   
pcie0_num
 
switch (pcie_link_status) {
case 7:
-   read_config(0, 2, 0, 0x4, &val);
-   write_config(0, 2, 0, 0x4, val|0x4);
-   read_config(0, 2, 0, 0x70c, &val);
+   val = read_config(2, 0x4);
+   write_config(2, 0x4, (val | 0x4));
+   val = read_config(2, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
-   write_config(0, 2, 0, 0x70c, val);
+   write_config(2, 0x70c, val);
case 3:
case 5:
case 6:
-   read_config(0, 1, 0, 0x4, &val);
-   write_config(0, 1, 0, 0x4, val|0x4);
-   read_config(0, 1, 0, 0x70c, &val);
+   val = read_config(1, 0x4);
+   write_config(1, 0x4, (val | 0x4));
+   val = read_config(1, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
-   write_config(0, 1, 0, 0x70c, val);
+   write_config(1, 0x70c, val);
default:
-   read_config(0, 0, 0, 0x4, &val);
-   write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
-   read_config(0

[PATCH v2 13/18] staging: mt7621-pci: remove unused preprocessor defines

2018-07-08 Thread Sergio Paracuellos

There are a lot of definitions that are not being used at all.
Just remove them cleaning the code a bit.

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 20 ++--
 1 file changed, 2 insertions(+), 18 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 5871e32..114e831 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -116,10 +116,7 @@ static struct pcie_controller_data pcie_controllers[] = {
 #define RALINK_PCI_IMBASEBAR0_ADDR(dev)(pcie_controllers[(dev)].offset 
+ 0x0018)
 #define RALINK_PCI_ID(dev) (pcie_controllers[(dev)].offset + 
0x0030)
 #define RALINK_PCI_CLASS(dev)  (pcie_controllers[(dev)].offset + 
0x0034)
-#define RALINK_PCI_SUBID(dev)  (pcie_controllers[(dev)].offset + 
0x0038)
 #define RALINK_PCI_STATUS(dev) (pcie_controllers[(dev)].offset + 
0x0050)
-#define RALINK_PCI_DERR(dev)   (pcie_controllers[(dev)].offset + 
0x0060)
-#define RALINK_PCI_ECRC(dev)   (pcie_controllers[(dev)].offset + 
0x0064)
 
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET 0x9000
 #define RALINK_PCIEPHY_P2_CTL_OFFSET   0xA000
@@ -132,25 +129,12 @@ static struct pcie_controller_data pcie_controllers[] = {
 #define RALINK_GPIOMODE0x60
 #define RALINK_PCIE_CLK_GEN0x7c
 #define RALINK_PCIE_CLK_GEN1   0x80
-#define PPLL_CFG1  0x9c
-#define PPLL_DRV   0xa0
-/* SYSC_REG_SYSTEM_CONFIG1 bits */
-#define RALINK_PCI_HOST_MODE_ENBIT(7)
-#define RALINK_PCIE_RC_MODE_EN BIT(8)
+
 //RALINK_RSTCTRL bit
 #define RALINK_PCIE_RSTBIT(23)
-#define RALINK_PCI_RST BIT(24)
-//RALINK_CLKCFG1 bit
-#define RALINK_PCI_CLK_EN  BIT(19)
-#define RALINK_PCIE_CLK_EN BIT(21)
-//RALINK_GPIOMODE bit
-#define PCI_SLOTx2 BIT(11)
-#define PCI_SLOTx1 (2<<11)
-//MTK PCIE PLL bit
-#define PDRV_SW_SETBIT(31)
-#define LC_CKDRVPD_BIT(19)
 
 #define MEMORY_BASE 0x0
+
 static int pcie_link_status = 0;
 
 static void __iomem *mt7621_pci_base;
-- 
2.7.4

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[PATCH v2 14/18] staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG definition

2018-07-08 Thread Sergio Paracuellos

RALINK_PCI_CONFIG_DATA_VIRTUAL_REG is a very long name and makes
lines to be very long when it is used. Rename it to a shorter one
RALINK_PCI_CONFIG_DATA.

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 114e831..55b9342 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -70,7 +70,7 @@
 #define RALINK_PCIE2_CLK_ENBIT(26)
 
 #define RALINK_PCI_CONFIG_ADDR 0x20
-#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
+#define RALINK_PCI_CONFIG_DATA 0x24
 #define RALINK_PCI_MEMBASE 0x0028
 #define RALINK_PCI_IOBASE  0x002C
 #define RALINK_PCIE0_RST   BIT(24)
@@ -180,7 +180,7 @@ pci_config_read(struct pci_bus *bus, unsigned int devfn,
u32 address;
 
address_reg = RALINK_PCI_CONFIG_ADDR;
-   data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
+   data_reg = RALINK_PCI_CONFIG_DATA;
 
address = (((where & 0xF00) >> 8) << 24) |
   mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
@@ -211,7 +211,7 @@ pci_config_write(struct pci_bus *bus, unsigned int devfn,
u32 address;
 
address_reg = RALINK_PCI_CONFIG_ADDR;
-   data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
+   data_reg = RALINK_PCI_CONFIG_DATA;
 
address = (((where & 0xF00) >> 8) << 24) |
   mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
@@ -253,7 +253,7 @@ read_config(unsigned int dev, u32 reg)
u32 address_reg, data_reg, address;
 
address_reg = RALINK_PCI_CONFIG_ADDR;
-   data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
+   data_reg = RALINK_PCI_CONFIG_DATA;
address = (((reg & 0xF00) >> 8) << 24) |
   mt7621_pci_get_cfgaddr(0, dev, 0, reg);
writel(address, mt7621_pci_base + address_reg);
@@ -266,7 +266,7 @@ write_config(unsigned int dev, u32 reg, u32 val)
u32 address_reg, data_reg, address;
 
address_reg = RALINK_PCI_CONFIG_ADDR;
-   data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
+   data_reg = RALINK_PCI_CONFIG_DATA;
address = (((reg & 0xF00) >> 8) << 24) |
   mt7621_pci_get_cfgaddr(0, dev, 0, reg);
writel(address, mt7621_pci_base + address_reg);
-- 
2.7.4

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[PATCH v2 11/18] staging: mt7621-pci: factor out mt7621_pci_configure function

2018-07-08 Thread Sergio Paracuellos

Factor out mt7621_pci_configure function to avoid a lot of
duplicated code in driver probe function.

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 35 -
 1 file changed, 17 insertions(+), 18 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
b/drivers/staging/mt7621-pci/pci-mt7621.c
index c41fc18..5d56f84 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -468,6 +468,18 @@ static void mt7621_pci_enable(u8 controller)
printk("PCIE%d enabled\n", controller);
 }
 
+static void mt7621_pci_configure(u8 controller)
+{
+   u32 val;
+
+   val = read_config(controller, 0x4);
+   write_config(controller, 0x4, (val | 0x4));
+   val = read_config(controller, 0x70c);
+   val &= ~(0xff) << 8;
+   val |= 0x50 << 8;
+   write_config(controller, 0x70c, val);
+}
+
 static int mt7621_pci_probe(struct platform_device *pdev)
 {
int i;
@@ -568,28 +580,15 @@ pcie(2/1/0) link status   pcie2_num   pcie1_num   
pcie0_num
 
switch (pcie_link_status) {
case 7:
-   val = read_config(2, 0x4);
-   write_config(2, 0x4, (val | 0x4));
-   val = read_config(2, 0x70c);
-   val &= ~(0xff)<<8;
-   val |= 0x50<<8;
-   write_config(2, 0x70c, val);
+   mt7621_pci_configure(2);
+   break;
case 3:
case 5:
case 6:
-   val = read_config(1, 0x4);
-   write_config(1, 0x4, (val | 0x4));
-   val = read_config(1, 0x70c);
-   val &= ~(0xff)<<8;
-   val |= 0x50<<8;
-   write_config(1, 0x70c, val);
+   mt7621_pci_configure(1);
+   break;
default:
-   val = read_config(0, 0x4);
-   write_config(0, 0x4, (val | 0x4)); //bus master enable
-   val = read_config(0, 0x70c);
-   val &= ~(0xff)<<8;
-   val |= 0x50<<8;
-   write_config(0, 0x70c, val);
+   mt7621_pci_configure(0);
}
 
pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
-- 
2.7.4

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Re: [PATCH v2 00/18] Some cleanups

2018-07-08 Thread Greg KH

On Sun, Jul 08, 2018 at 02:57:08PM +0200, Sergio Paracuellos wrote:
> This patch series clean up a bit mt7621-pci driver.

Your subject line for the 00/XX email needs some work (like putting what
driver and subsystem it is for in it please...)

For future patch series.

thanks,

greg k-h
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Re: [PATCH v2 18/18] staging: mt7621-pci: add SPDX identifier

2018-07-08 Thread Greg KH

On Sun, Jul 08, 2018 at 02:57:26PM +0200, Sergio Paracuellos wrote:
> It's good to have SPDX identifiers in driver files to make it easier to
> audit the kernel tree for correct licenses.
> 
> Fix up the one of staging pci-mt7621.c file to have a proper SPDX
> identifier, based on the license text in the file itself. The SPDX
> identifier is a legally binding shorthand, which can be used instead of
> the full boiler plate text.
> 
> Signed-off-by: Sergio Paracuellos 
> ---
>  drivers/staging/mt7621-pci/pci-mt7621.c | 28 ++--
>  1 file changed, 2 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
> b/drivers/staging/mt7621-pci/pci-mt7621.c
> index b4e049a..d92df91 100644
> --- a/drivers/staging/mt7621-pci/pci-mt7621.c
> +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
> @@ -1,32 +1,10 @@
> -/**
> - *
> +// SPDX-License-Identifier: GPL-2.0

Ok, but:

> - *  This program is free software; you can redistribute  it and/or modify it
> - *  under  the terms of  the GNU General  Public License as published by the
> - *  Free Software Foundation;  either version 2 of the  License, or (at your
> - *  option) any later version.

You used the wrong license for the SPDX line :(

PLEASE be careful about this, it matters as it is a legal thing you are
dealing with.

If you don't know how to read licenses, just leave it all alone and do
not guess.

greg k-h
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[no subject]

2018-07-08 Thread Fang

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--
Esta mensagem foi verificada pelo sistema de antivírus e
acredita-se estar livre de perigo.

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Re: [RFC PATCH v1] Xilinx AXI-Stream FIFO v4.1 IP core driver

2018-07-08 Thread Greg KH

On Sat, Jul 07, 2018 at 10:19:40PM -0400, Jacob Feder wrote:
> Hi all,
> I have developed this driver for a Xilinx-provided IP block for their Zynq
> SoC. I fixed all of the checkpatch.pl problems I knew how to. If someone
> could chime in on how to fix the remaining few it would be appreciated.
> 
> Also looking for feedback on general structure. It's my first driver (and
> patch submission) so I'm sure there are plenty of things to be improved on
> :).
> 
> Functionally everything works OK except the performance isn't as good as I
> was hoping for. I have been testing it by operating the FIFO in loopback
> mode (AXI-Stream TX interface feeding back into RX interface) running on
> the XC7Z020 (7000 series) Zynq device. I am getting anything between
> 3-16MB/s depending on the amount of data transferred. The performance
> claimed by the PG080 datasheet is ~65MB/s. The CPU isn't under significant
> load (~12%) as reported by top so I don't think that's the bottleneck.
> 
> Please +CC in responses as I'm not on the mailing list.
> 
> Cheers
> 
> 
> This IP core has read and write AXI-Stream FIFOs, the contents of which can
> be accessed from the AXI4 memory-mapped interface. This is useful for
> transferring data from a processor into the FPGA fabric. The driver creates
> a character device that can be read/written to with standard
> open/read/write/close.

Why not use the uio api, which allows userspace to mmap the memory of
the device and access it directly from userspace?  That should make
things a lot faster, right?

Or if that doesn't work, what about the fpga API the kernel now has?
Would that work for this hardware?


> 
> See Xilinx PG080 document for IP details.

Do you have a link to that?  If so, can you put it in here?

> 
> Currently supports only store-forward mode with a 32-bit
> AXI4-Lite interface. DOES NOT support:
>   - cut-through mode
>   - AXI4 (non-lite)
> 
> Signed-off-by: Jacob Feder 
> ---
>  drivers/staging/axisfifo/axis-fifo.c | 1296 
> ++
>  drivers/staging/axisfifo/axis-fifo.h |  119 
>  2 files changed, 1415 insertions(+)
>  create mode 100644 drivers/staging/axisfifo/axis-fifo.c
>  create mode 100644 drivers/staging/axisfifo/axis-fifo.h

Why does a single .c file need a .h file?

I'll be glad to take this driver, as others can clean it up in-tree (I
think your locking is crazy and is probably causing a lot of performance
issues), but I need a TODO file for it listing what you think is needed
to do in order to get this out of the staging tree?

Or, if you thin it should use the fpga or uio interface instead, maybe
it's just easier to redo it based on that?

thanks,

greg k-h
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Re: [PATCH v2 00/18] Some cleanups

2018-07-08 Thread Sergio Paracuellos

On Sun, Jul 8, 2018 at 3:14 PM, Greg KH  wrote:
> On Sun, Jul 08, 2018 at 02:57:08PM +0200, Sergio Paracuellos wrote:
>> This patch series clean up a bit mt7621-pci driver.
>
> Your subject line for the 00/XX email needs some work (like putting what
> driver and subsystem it is for in it please...)

Sorry Greg, I miss that in the cover letter :-(.

>
> For future patch series.

I'll be more careful from now.
>
> thanks,
>
> greg k-h


Best regards,
Sergio Paracuellos
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Re: [PATCH v2 18/18] staging: mt7621-pci: add SPDX identifier

2018-07-08 Thread Sergio Paracuellos

On Sun, Jul 8, 2018 at 3:16 PM, Greg KH  wrote:
> On Sun, Jul 08, 2018 at 02:57:26PM +0200, Sergio Paracuellos wrote:
>> It's good to have SPDX identifiers in driver files to make it easier to
>> audit the kernel tree for correct licenses.
>>
>> Fix up the one of staging pci-mt7621.c file to have a proper SPDX
>> identifier, based on the license text in the file itself. The SPDX
>> identifier is a legally binding shorthand, which can be used instead of
>> the full boiler plate text.
>>
>> Signed-off-by: Sergio Paracuellos 
>> ---
>>  drivers/staging/mt7621-pci/pci-mt7621.c | 28 ++--
>>  1 file changed, 2 insertions(+), 26 deletions(-)
>>
>> diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
>> b/drivers/staging/mt7621-pci/pci-mt7621.c
>> index b4e049a..d92df91 100644
>> --- a/drivers/staging/mt7621-pci/pci-mt7621.c
>> +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
>> @@ -1,32 +1,10 @@
>> -/**
>> - *
>> +// SPDX-License-Identifier: GPL-2.0
>
> Ok, but:
>
>> - *  This program is free software; you can redistribute  it and/or modify it
>> - *  under  the terms of  the GNU General  Public License as published by the
>> - *  Free Software Foundation;  either version 2 of the  License, or (at your
>> - *  option) any later version.
>
> You used the wrong license for the SPDX line :(
>
> PLEASE be careful about this, it matters as it is a legal thing you are
> dealing with.

I see. Sorry I misunderstood the "any later version" part. So I
suppose the correct
line should be GPL-2.0+.

>
> If you don't know how to read licenses, just leave it all alone and do
> not guess.

Skip this in the series, please. I will send the proper one in next cleanups.

>
> greg k-h

Best regards,
Sergio Paracuellos
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Re: [PATCH v2 18/18] staging: mt7621-pci: add SPDX identifier

2018-07-08 Thread Greg KH

On Sun, Jul 08, 2018 at 04:06:08PM +0200, Sergio Paracuellos wrote:
> On Sun, Jul 8, 2018 at 3:16 PM, Greg KH  wrote:
> > On Sun, Jul 08, 2018 at 02:57:26PM +0200, Sergio Paracuellos wrote:
> >> It's good to have SPDX identifiers in driver files to make it easier to
> >> audit the kernel tree for correct licenses.
> >>
> >> Fix up the one of staging pci-mt7621.c file to have a proper SPDX
> >> identifier, based on the license text in the file itself. The SPDX
> >> identifier is a legally binding shorthand, which can be used instead of
> >> the full boiler plate text.
> >>
> >> Signed-off-by: Sergio Paracuellos 
> >> ---
> >>  drivers/staging/mt7621-pci/pci-mt7621.c | 28 ++--
> >>  1 file changed, 2 insertions(+), 26 deletions(-)
> >>
> >> diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
> >> b/drivers/staging/mt7621-pci/pci-mt7621.c
> >> index b4e049a..d92df91 100644
> >> --- a/drivers/staging/mt7621-pci/pci-mt7621.c
> >> +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
> >> @@ -1,32 +1,10 @@
> >> -/**
> >> - *
> >> +// SPDX-License-Identifier: GPL-2.0
> >
> > Ok, but:
> >
> >> - *  This program is free software; you can redistribute  it and/or modify 
> >> it
> >> - *  under  the terms of  the GNU General  Public License as published by 
> >> the
> >> - *  Free Software Foundation;  either version 2 of the  License, or (at 
> >> your
> >> - *  option) any later version.
> >
> > You used the wrong license for the SPDX line :(
> >
> > PLEASE be careful about this, it matters as it is a legal thing you are
> > dealing with.
> 
> I see. Sorry I misunderstood the "any later version" part. So I
> suppose the correct line should be GPL-2.0+.

Don't "suppose" when dealing with legal issues.  Please leave these
types of changes to the type of people who know licenses and the issues
surrounding them.

thanks,

greg k-h
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Re: [PATCH v2 18/18] staging: mt7621-pci: add SPDX identifier

2018-07-08 Thread Sergio Paracuellos

On Sun, Jul 8, 2018 at 4:22 PM, Greg KH  wrote:
> On Sun, Jul 08, 2018 at 04:06:08PM +0200, Sergio Paracuellos wrote:
>> On Sun, Jul 8, 2018 at 3:16 PM, Greg KH  wrote:
>> > On Sun, Jul 08, 2018 at 02:57:26PM +0200, Sergio Paracuellos wrote:
>> >> It's good to have SPDX identifiers in driver files to make it easier to
>> >> audit the kernel tree for correct licenses.
>> >>
>> >> Fix up the one of staging pci-mt7621.c file to have a proper SPDX
>> >> identifier, based on the license text in the file itself. The SPDX
>> >> identifier is a legally binding shorthand, which can be used instead of
>> >> the full boiler plate text.
>> >>
>> >> Signed-off-by: Sergio Paracuellos 
>> >> ---
>> >>  drivers/staging/mt7621-pci/pci-mt7621.c | 28 ++--
>> >>  1 file changed, 2 insertions(+), 26 deletions(-)
>> >>
>> >> diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
>> >> b/drivers/staging/mt7621-pci/pci-mt7621.c
>> >> index b4e049a..d92df91 100644
>> >> --- a/drivers/staging/mt7621-pci/pci-mt7621.c
>> >> +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
>> >> @@ -1,32 +1,10 @@
>> >> -/**
>> >> - *
>> >> +// SPDX-License-Identifier: GPL-2.0
>> >
>> > Ok, but:
>> >
>> >> - *  This program is free software; you can redistribute  it and/or 
>> >> modify it
>> >> - *  under  the terms of  the GNU General  Public License as published by 
>> >> the
>> >> - *  Free Software Foundation;  either version 2 of the  License, or (at 
>> >> your
>> >> - *  option) any later version.
>> >
>> > You used the wrong license for the SPDX line :(
>> >
>> > PLEASE be careful about this, it matters as it is a legal thing you are
>> > dealing with.
>>
>> I see. Sorry I misunderstood the "any later version" part. So I
>> suppose the correct line should be GPL-2.0+.
>
> Don't "suppose" when dealing with legal issues.  Please leave these
> types of changes to the type of people who know licenses and the issues
> surrounding them.

Ok, I will. Thanks for pointing this out. Sorry for inconvenience and noise.

>
> thanks,
>
> greg k-h

Best regards,
Sergio Paracuellos
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Re: [PATCH] staging: mt7621-pci: refactor pci related read and writes functions

2018-07-08 Thread Greg KH

On Sat, Jul 07, 2018 at 09:48:37PM +0200, Sergio Paracuellos wrote:
> This commit simplifies and clean a lot of stuff related with pci
> reads and writes. It deletes a lot of not needed at all functions
> and use kernel arch operations read[b,w,l] and write[b,w,l] instead
> of use custom macros. It also include one function helper called
> 'mt7621_pci_get_cfgaddr' to easily obtain config address. Also to
> get pci base address a global 'mt7621_pci_base' variable has been
> included and initialized as a pointer to RALINK_PCI_BASE in driver
> probe function. With this changes LOC is clearly decreased and
> readability is increased.

A lot of different things are happening here in this patch, making it
hard to review.  Any chance to split this up into smaller, easier to
review, parts?

And you adding mt7621_pci_base is a nice start, but that really should
be a device-specific variable, not a global one.  I can't belive this
driver works with a hard-coded base address, that's crazy...  Shouldn't
that value be read from the PCI device itself instead?

thanks,

greg k-h
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Re: [PATCH 03/12] staging:rtl8192u: Remove blank lines before '}' and after '{' characters

2018-07-08 Thread Greg KH

On Sat, Jul 07, 2018 at 03:55:04PM +0100, John Whitmore wrote:
> Coding style change to simply remove the unrequired spaces before a closing
> brace or before an opening brace.

That would be good, but that's not what this patch does :(

It removes lines, not spaces, as the subject line said.  You also fix up
an indentation as well.

thanks,

greg k-h
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Re: [PATCH 03/12] staging:rtl8192u: Remove blank lines before '}' and after '{' characters

2018-07-08 Thread John Whitmore

On Sun, Jul 08, 2018 at 05:38:11PM +0200, Greg KH wrote:
> On Sat, Jul 07, 2018 at 03:55:04PM +0100, John Whitmore wrote:
> > Coding style change to simply remove the unrequired spaces before a closing
> > brace or before an opening brace.
> 
> That would be good, but that's not what this patch does :(
> 
> It removes lines, not spaces, as the subject line said.  You also fix up
> an indentation as well.
> 
> thanks,
> 
> greg k-h

Oops sorry. I'll fix it up in another pass.
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Re: [PATCH] staging: mt7621-pci: refactor pci related read and writes functions

2018-07-08 Thread Sergio Paracuellos

On Sun, Jul 8, 2018 at 5:36 PM, Greg KH  wrote:
> On Sat, Jul 07, 2018 at 09:48:37PM +0200, Sergio Paracuellos wrote:
>> This commit simplifies and clean a lot of stuff related with pci
>> reads and writes. It deletes a lot of not needed at all functions
>> and use kernel arch operations read[b,w,l] and write[b,w,l] instead
>> of use custom macros. It also include one function helper called
>> 'mt7621_pci_get_cfgaddr' to easily obtain config address. Also to
>> get pci base address a global 'mt7621_pci_base' variable has been
>> included and initialized as a pointer to RALINK_PCI_BASE in driver
>> probe function. With this changes LOC is clearly decreased and
>> readability is increased.
>
> A lot of different things are happening here in this patch, making it
> hard to review.  Any chance to split this up into smaller, easier to
> review, parts?

It can be but all changes are really related and this just delete all of those
crazy read and write functions and adding some helpers in the way to
make easier the rewrite of real read and write.

>
> And you adding mt7621_pci_base is a nice start, but that really should
> be a device-specific variable, not a global one.  I can't belive this
> driver works with a hard-coded base address, that's crazy...  Shouldn't
> that value be read from the PCI device itself instead?

I know this shouldn't be a global variable but, as you said, is a nice start to
make this driver a little cleaner for be able to do a better cleanups
series. Also
all of a lot of hardcoded values should be read from device tree in
next cleanups
in order to have a cleaner driver.

Also this patch is the first in my next series and as you can see it
contains very ugly hacks, so
I though to do a first simple cleanups first for finally end up with
easier real cleans. Maybe that
is not the best approach.

I can try to split this a bit but I don't really know how to do atomic
changes because
of the related things included here.

>
> thanks,
>
> greg k-h

Best regards,
Sergio Paracuellos
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[PATCH] staging: gasket: Add descriptions for module parameters

2018-07-08 Thread Kamal Heib

This patch add description for the module parameters and remove the task
to do it from the TODO file.

Signed-off-by: Kamal Heib 
---
 drivers/staging/gasket/TODO  | 1 -
 drivers/staging/gasket/apex_driver.c | 8 
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/staging/gasket/TODO b/drivers/staging/gasket/TODO
index 0d8ee9602c80..c524dba7945f 100644
--- a/drivers/staging/gasket/TODO
+++ b/drivers/staging/gasket/TODO
@@ -5,7 +5,6 @@ staging directory.
 - Remove static function declarations.
 - Document sysfs files with Documentation/ABI/ entries.
 - Use misc interface instead of major number for driver version description.
-- Add descriptions of module_param's
 - Remove gasket-specific logging functions.
 - apex_get_status() should actually check status.
 - Static functions don't need kernel doc formatting, can be simplified.
diff --git a/drivers/staging/gasket/apex_driver.c 
b/drivers/staging/gasket/apex_driver.c
index 395256704428..21deef38807a 100644
--- a/drivers/staging/gasket/apex_driver.c
+++ b/drivers/staging/gasket/apex_driver.c
@@ -329,9 +329,17 @@ static int allow_hw_clock_gating = 1;
 static int bypass_top_level;
 
 module_param(allow_power_save, int, 0644);
+MODULE_PARM_DESC(allow_power_save,
+"Allows device to enter power save upon driver close()");
+
 module_param(allow_sw_clock_gating, int, 0644);
+MODULE_PARM_DESC(allow_sw_clock_gating, "Allows SW based clock gating");
+
 module_param(allow_hw_clock_gating, int, 0644);
+MODULE_PARM_DESC(allow_hw_clock_gating, "Allows HW based clock gating");
+
 module_param(bypass_top_level, int, 0644);
+MODULE_PARM_DESC(bypass_top_level, "Act as if only GCB is instantiated");
 
 static int __init apex_init(void)
 {
-- 
2.14.4

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Re: [PATCH 3/6] staging: rtl8723bs: fix indentation

2018-07-08 Thread Michael Straube


On 07/08/18 18:46, Joe Perches wrote:

On Sun, 2018-07-08 at 12:38 +0200, Michael Straube wrote:

Remove unrequired extra indentations.

[]

diff --git a/drivers/staging/rtl8723bs/core/rtw_ieee80211.c 
b/drivers/staging/rtl8723bs/core/rtw_ieee80211.c

[]

@@ -69,16 +69,16 @@ int rtw_get_bit_value_from_ieee_value(u8 val)
  
  uint rtw_is_cckrates_included(u8 *rate)

  {
-   u32 i = 0;
+   u32 i = 0;
  
-		while (rate[i] !=  0) {

-   if  rate[i]) & 0x7f) == 2)  || (((rate[i]) & 
0x7f) == 4) ||
-(((rate[i]) & 0x7f) == 11)  || (((rate[i]) & 0x7f) 
== 22))
-   return true;
-   i++;
-   }
+   while (rate[i] !=  0) {
+   if  rate[i]) & 0x7f) == 2)  || (((rate[i]) & 0x7f) == 
4) ||
+(((rate[i]) & 0x7f) == 11)  || (((rate[i]) & 0x7f) == 22))
+   return true;
+   i++;
+   }
  
-		return false;

+   return false;
  }


Hi Michael.

Please try to improve the code for human readers and/or
reduce overall object size over merely shutting up checkpatch
style warnings.



Hi Joe,

I agree that it's better to improve the code than just silence
warnings.

Thanks for your advice.


For instance:

You could reduce object size a little by eliminating the
multiple use of 0x7f and index and dereferencing the
pointer instead.

$ size drivers/staging/rtl8723bs/core/rtw_ieee80211.o*
text   data bss dec hex filename
   10085 76   0   1016127b1 
drivers/staging/rtl8723bs/core/rtw_ieee80211.o.new
   10149 76   0   1022527f1 
drivers/staging/rtl8723bs/core/rtw_ieee80211.o.old

Something like:

uint rtw_is_cckrates_included(u8 *rate)
{
while (*rate) {
u8 r = *rate & 0x7f;

if (r == 2 || r == 4 || r == 11 || r == 22)
return true;
rate++;
}

return false;
}

uint rtw_is_cckratesonly_included(u8 *rate)
{
while (*rate) {
u8 r = *rate & 0x7f;

if (r != 2 && r != 4 && r != 11 && r != 22)
return false;
rate++;
}

return true;
}



The patch has been added to staging-testing already.
I will send patches with your suggestions the next days.

Thanks again.

Michael
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Re: [PATCH v6 2/4] resource: Use list_head to link sibling resource

2018-07-08 Thread Andy Shevchenko

On Sun, Jul 8, 2018 at 5:59 AM, Baoquan He  wrote:
> On 07/05/18 at 01:00am, kbuild test robot wrote:

> However, I didn't find below branch. And tried to open it in web
> broswer, also failed.

While this is kinda valid point...

> Could you help have a look at this?

...isn't obvious that you didn't change the file mentioned in a report?
Just take latest linux-next and you will see.


>> All error/warnings (new ones prefixed by >>):
>>
>> >> arch/mips/pci/pci-rc32434.c:57:11: error: initialization from 
>> >> incompatible pointer type [-Werror=incompatible-pointer-types]
>>  .child = &rc32434_res_pci_mem2
>>   ^
>>arch/mips/pci/pci-rc32434.c:57:11: note: (near initialization for 
>> 'rc32434_res_pci_mem1.child.next')
>> >> arch/mips/pci/pci-rc32434.c:51:47: warning: missing braces around 
>> >> initializer [-Wmissing-braces]
>> static struct resource rc32434_res_pci_mem1 = {
>>   ^
>>arch/mips/pci/pci-rc32434.c:60:47: warning: missing braces around 
>> initializer [-Wmissing-braces]
>> static struct resource rc32434_res_pci_mem2 = {
>>   ^
>>cc1: some warnings being treated as errors
>>
>> vim +57 arch/mips/pci/pci-rc32434.c
>>
>> 73b4390f Ralf Baechle 2008-07-16  50
>> 73b4390f Ralf Baechle 2008-07-16 @51  static struct resource 
>> rc32434_res_pci_mem1 = {
>> 73b4390f Ralf Baechle 2008-07-16  52  .name = "PCI MEM1",
>> 73b4390f Ralf Baechle 2008-07-16  53  .start = 0x5000,
>> 73b4390f Ralf Baechle 2008-07-16  54  .end = 0x5FFF,
>> 73b4390f Ralf Baechle 2008-07-16  55  .flags = IORESOURCE_MEM,
>> 73b4390f Ralf Baechle 2008-07-16  56  .sibling = NULL,
>> 73b4390f Ralf Baechle 2008-07-16 @57  .child = &rc32434_res_pci_mem2
>> 73b4390f Ralf Baechle 2008-07-16  58  };
>> 73b4390f Ralf Baechle 2008-07-16  59
>>
>> :: The code at line 57 was first introduced by commit
>> :: 73b4390fb23456964201abda79f1210fe337d01a [MIPS] Routerboard 532: 
>> Support for base system
>>
>> :: TO: Ralf Baechle 
>> :: CC: Ralf Baechle 
>>
>> ---
>> 0-DAY kernel test infrastructureOpen Source Technology Center
>> https://lists.01.org/pipermail/kbuild-all   Intel Corporation
>
>



-- 
With Best Regards,
Andy Shevchenko
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Re: [RFC PATCH v1] Xilinx AXI-Stream FIFO v4.1 IP core driver

2018-07-08 Thread Jacob Feder

On Sun, Jul 08, 2018 at 03:28:16PM +0200, Greg KH wrote:
> On Sat, Jul 07, 2018 at 10:19:40PM -0400, Jacob Feder wrote:
> > Hi all,
> > I have developed this driver for a Xilinx-provided IP block for their Zynq
> > SoC. I fixed all of the checkpatch.pl problems I knew how to. If someone
> > could chime in on how to fix the remaining few it would be appreciated.
> > 
> > Also looking for feedback on general structure. It's my first driver (and
> > patch submission) so I'm sure there are plenty of things to be improved on
> > :).
> > 
> > Functionally everything works OK except the performance isn't as good as I
> > was hoping for. I have been testing it by operating the FIFO in loopback
> > mode (AXI-Stream TX interface feeding back into RX interface) running on
> > the XC7Z020 (7000 series) Zynq device. I am getting anything between
> > 3-16MB/s depending on the amount of data transferred. The performance
> > claimed by the PG080 datasheet is ~65MB/s. The CPU isn't under significant
> > load (~12%) as reported by top so I don't think that's the bottleneck.
> > 
> > Please +CC in responses as I'm not on the mailing list.
> > 
> > Cheers
> > 
> > 
> > This IP core has read and write AXI-Stream FIFOs, the contents of which can
> > be accessed from the AXI4 memory-mapped interface. This is useful for
> > transferring data from a processor into the FPGA fabric. The driver creates
> > a character device that can be read/written to with standard
> > open/read/write/close.
> 
> Why not use the uio api, which allows userspace to mmap the memory of
> the device and access it directly from userspace?  That should make
> things a lot faster, right?

I thought about the UIO method but based on what I read it seemed like
more of a hack (and also doesn't expose interrupts?). Whether it would
make things faster I have no idea.

> 
> Or if that doesn't work, what about the fpga API the kernel now has?
> Would that work for this hardware?
> 

I'm not totally sure what you're referring to here, but I think the FPGA
kernel drivers are for downloading bitstreams to the FPGA (bitstream is
equivalent to asm for fpgas), which isn't what I'm trying to do. 

> 
> > 
> > See Xilinx PG080 document for IP details.
> 
> Do you have a link to that?  If so, can you put it in here?
> 

https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf

> > 
> > Currently supports only store-forward mode with a 32-bit
> > AXI4-Lite interface. DOES NOT support:
> > - cut-through mode
> > - AXI4 (non-lite)
> > 
> > Signed-off-by: Jacob Feder 
> > ---
> >  drivers/staging/axisfifo/axis-fifo.c | 1296 
> > ++
> >  drivers/staging/axisfifo/axis-fifo.h |  119 
> >  2 files changed, 1415 insertions(+)
> >  create mode 100644 drivers/staging/axisfifo/axis-fifo.c
> >  create mode 100644 drivers/staging/axisfifo/axis-fifo.h
> 
> Why does a single .c file need a .h file?

Good point... this can be consolidated :)

> 
> I'll be glad to take this driver, as others can clean it up in-tree (I
> think your locking is crazy and is probably causing a lot of performance
> issues), but I need a TODO file for it listing what you think is needed
> to do in order to get this out of the staging tree?

I'm confused about why you don't like the locking - all I'm doing is
locking on open() calls to prevent multiple userspace apps from
reading/writing to the fifo simultaneously. This shouldn't reduce
performance because the mutexes are only tested on open() not on read()
or write(). Presumably the user is only opening once.

I think locking is necessary - if the hardware registers are accessed in
the wrong order it goes into an unknown state and must be reset (and will
probably cause a kernel panic).

> 
> Or, if you thin it should use the fpga or uio interface instead, maybe
> it's just easier to redo it based on that?
> 
> thanks,
> 
> greg k-h

I have made some slight modifications today. Let me know if there are any
other things you think I should change. I can integrate those then
resubmit a v2 for you to bring into the tree.

In terms of TODO it's all ok as far as I'm concerned unless someone wants
to look into the performance. (actually see below - I think this could
explain why performance of my system is lower - xilinx is using some sort
of DMA driver instead of io_remap)
https://forums.xilinx.com/xlnx/attachments/xlnx/ELINUX/13011/2/Linux-DMA-In-Device-Drivers.pdf

Thanks!!

Cheers,
Jacob 

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Re: [PATCH] staging: mt7621-pci: refactor pci related read and writes functions

2018-07-08 Thread NeilBrown

On Sun, Jul 08 2018, Sergio Paracuellos wrote:
>
> I can try to split this a bit but I don't really know how to do atomic
> changes because
> of the related things included here.

Some suggestions:

1/ MV_READ_DATA is not used.  Discard that any anything else that is
   not used.

2/ MV_WRITE is replaced with writel(), MV_READ() with readl().  Make that
   one patch.

3/ unsigned int becomes u32.  That is a patch by itself. (maybe this has
   to go before 2.

4/ Introduce mt7621_pci_get_cfgaddr() and use it where it is a drop-in
   replacement.

5/ Introduce new implementations of pci_config_read() and
   pci_config_write.

6/ discard any newly dead code (e.g write_config_* ??)

Now if there is anything left in the patch is should be clear if it
could benefit from being broken up.

Thanks for working on this.

NeilBrown

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Re: [PATCH 13/18] staging: mt7621-pinctrl: make use of pinctrl_utils_reserve_map

2018-07-08 Thread NeilBrown

On Thu, Jun 07 2018, Sergio Paracuellos wrote:

> Function rt2880_pinctrl_dt_node_to_map was using 'kzalloc' to
> reserve map memory. There is a 'pinctrl_utils_reserve_map' to
> do this function. Just use it.
>
> Signed-off-by: Sergio Paracuellos 
> ---
>  drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c | 12 +---
>  1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c 
> b/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c
> index a172b68..84494a1 100644
> --- a/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c
> +++ b/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c
> @@ -113,7 +113,10 @@ static int rt2880_pinctrl_dt_node_to_map(struct 
> pinctrl_dev *pctrldev,
>struct pinctrl_map **map,
>unsigned int *num_maps)
>  {
> + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
> + int ret;
>   int max_maps = 0;
> + unsigned int reserved_maps = 0;
>   struct pinctrl_map *tmp;
>   struct device_node *np;
>  
> @@ -127,9 +130,12 @@ static int rt2880_pinctrl_dt_node_to_map(struct 
> pinctrl_dev *pctrldev,
>   if (!max_maps)
>   return max_maps;
>  
> - *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
> - if (!*map)
> - return -ENOMEM;
> + ret = pinctrl_utils_reserve_map(pctrldev, map, &reserved_maps,
> + num_maps, max_maps);

Unfortunately this is buggy.
pinctrl_utils_reserve_map() calls krealloc() on *map.
So we need to initialise
*map = NULL;

before calling it.

Thanks,
NeilBrown


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Re: [PATCH v2 03/18] staging: mt7621-pci: avoid pointer arithmetics in some macros

2018-07-08 Thread NeilBrown

On Sun, Jul 08 2018, Sergio Paracuellos wrote:

> RALINK_PCI_MEMBASE, RALINK_PCI_IOBASE, RALINK_PCI_PCICFG_ADDR and
> RALINK_PCI_PCIMSK_ADDR are using very ugly pointer arithmetics to
> read and write along the code. Instead of doing this, use the
> mt7621_pci_reg_read and mt7621_pci_reg_write functions making
> this a bit cleaner.
>
> Signed-off-by: Sergio Paracuellos 
> ---
>  drivers/staging/mt7621-pci/pci-mt7621.c | 59 
> ++---
>  1 file changed, 25 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
> b/drivers/staging/mt7621-pci/pci-mt7621.c
> index 32c37e8..f7defa7 100644
> --- a/drivers/staging/mt7621-pci/pci-mt7621.c
> +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
> @@ -68,14 +68,14 @@
>  
>  #define RALINK_PCI_CONFIG_ADDR   0x20
>  #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG   0x24
> -#define RALINK_PCI_MEMBASE   *(volatile u32 *)(RALINK_PCI_BASE + 
> 0x0028)
> -#define RALINK_PCI_IOBASE*(volatile u32 *)(RALINK_PCI_BASE + 
> 0x002C)
> +#define RALINK_PCI_MEMBASE   0x0028
> +#define RALINK_PCI_IOBASE0x002C
>  #define RALINK_PCIE0_RST (1<<24)
>  #define RALINK_PCIE1_RST (1<<25)
>  #define RALINK_PCIE2_RST (1<<26)
>  
> -#define RALINK_PCI_PCICFG_ADDR   *(volatile u32 
> *)(RALINK_PCI_BASE + 0x)
> -#define RALINK_PCI_PCIMSK_ADDR   *(volatile u32 
> *)(RALINK_PCI_BASE + 0x000C)
> +#define RALINK_PCI_PCICFG_ADDR   0x
> +#define RALINK_PCI_PCIMSK_ADDR   0x000C
>  #define RALINK_PCI_BASE  0xBE14
>  
>  #define RALINK_PCIEPHY_P0P1_CTL_OFFSET   (RALINK_PCI_BASE + 0x9000)
> @@ -408,6 +408,7 @@ void setup_cm_memory_region(struct resource *mem_resource)
>  
>  static int mt7621_pci_probe(struct platform_device *pdev)
>  {
> + u32 mask;
>   unsigned long val = 0;
>  
>   mt7621_pci_base = (void __iomem *)RALINK_PCI_BASE;
> @@ -471,7 +472,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
>   pcie_link_status &= ~(1<<0);
>   } else {
>   pcie_link_status |= 1<<0;
> - RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
> + mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
> + mask |= (1<<20); // enable pcie1 interrupt
> + mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
>   }
>  
>   if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(1)) & 0x1) == 0) {
> @@ -481,7 +484,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
>   pcie_link_status &= ~(1<<1);
>   } else {
>   pcie_link_status |= 1<<1;
> - RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
> + mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
> + mask |= (1<<21); // enable pcie1 interrupt
> + mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
>   }
>  
>   if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(2)) & 0x1) == 0) {
> @@ -491,7 +496,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
>   pcie_link_status &= ~(1<<2);
>   } else {
>   pcie_link_status |= 1<<2;
> - RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
> + mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
> + mask |= (1<<22); // enable pcie2 interrupt
> + mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
>   }
>  
>   if (pcie_link_status == 0)
> @@ -508,39 +515,23 @@ pcie(2/1/0) link status pcie2_num   pcie1_num   
> pcie0_num
>  3'b110   1   0   x
>  3'b111   2   1   0
>  */
> - switch (pcie_link_status) {
> - case 2:
> - RALINK_PCI_PCICFG_ADDR &= ~0x00ff;
> - RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;//port0
> - RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;//port1
> - break;
> - case 4:
> - RALINK_PCI_PCICFG_ADDR &= ~0x0fff;
> - RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;//port0
> - RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;//port1
> - RALINK_PCI_PCICFG_ADDR |= 0x0 << 24;//port2
> - break;
> - case 5:
> - RALINK_PCI_PCICFG_ADDR &= ~0x0fff;
> - RALINK_PCI_PCICFG_ADDR |= 0x0 << 16;//port0
> - RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;//port1
> - RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;//port2
> - break;
> - case 6:
> - RALINK_PCI_PCICFG_ADDR &= ~0x0fff;
> - RALINK_PCI_PCICFG_ADDR |= 0x2 << 16;//port0
> - RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;//port1
> - RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;//port2
> - break;
> - }
> + mask = mt7621_pci_reg_read(RALINK_PCI_PCICFG_ADDR);
> + mask &= ~

Re: [PATCH 13/13] staging: mt7621-pinctrl: replace core_initcall_sync with builtin_platform_driver

2018-07-08 Thread NeilBrown

On Thu, Jun 28 2018, Sergio Paracuellos wrote:

> We don't really need initialization of this at such an early stage.
> Just use builtin_platform_driver to initialize this driver.
>
> Signed-off-by: Sergio Paracuellos 
> ---
>  drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c | 7 +--
>  1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c 
> b/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c
> index 2cce212..7025942 100644
> --- a/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c
> +++ b/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c
> @@ -422,9 +422,4 @@ static struct platform_driver rt2880_pinmux_driver = {
>   },
>  };
>  
> -int __init rt2880_pinmux_init(void)
> -{
> - return platform_driver_register(&rt2880_pinmux_driver);
> -}
> -
> -core_initcall_sync(rt2880_pinmux_init);
> +builtin_platform_driver(rt2880_pinmux_driver);
> -- 
> 2.7.4

This patch causes the network interface on my device to stop working.
device_initcall() is called much later than core_initcall_sync() and
that seem to be a problem.
I think this needs to be reverted - at least until it is understood.

Thanks,
NeilBrown


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Re: [PATCH 3/6] staging: rtl8723bs: fix indentation

2018-07-08 Thread Joe Perches

On Sun, 2018-07-08 at 12:38 +0200, Michael Straube wrote:
> Remove unrequired extra indentations.
[]
> diff --git a/drivers/staging/rtl8723bs/core/rtw_ieee80211.c 
> b/drivers/staging/rtl8723bs/core/rtw_ieee80211.c
[]
> @@ -69,16 +69,16 @@ int rtw_get_bit_value_from_ieee_value(u8 val)
>  
>  uint rtw_is_cckrates_included(u8 *rate)
>  {
> - u32 i = 0;
> + u32 i = 0;
>  
> - while (rate[i] !=  0) {
> - if  rate[i]) & 0x7f) == 2)  || (((rate[i]) & 0x7f) 
> == 4) ||
> -  (((rate[i]) & 0x7f) == 11)  || (((rate[i]) & 0x7f) 
> == 22))
> - return true;
> - i++;
> - }
> + while (rate[i] !=  0) {
> + if  rate[i]) & 0x7f) == 2)  || (((rate[i]) & 0x7f) == 4) ||
> +  (((rate[i]) & 0x7f) == 11)  || (((rate[i]) & 0x7f) == 22))
> + return true;
> + i++;
> + }
>  
> - return false;
> + return false;
>  }

Hi Michael.

Please try to improve the code for human readers and/or
reduce overall object size over merely shutting up checkpatch
style warnings.

For instance:

You could reduce object size a little by eliminating the
multiple use of 0x7f and index and dereferencing the
pointer instead.

$ size drivers/staging/rtl8723bs/core/rtw_ieee80211.o*
   textdata bss dec hex filename
  10085  76   0   1016127b1 
drivers/staging/rtl8723bs/core/rtw_ieee80211.o.new
  10149  76   0   1022527f1 
drivers/staging/rtl8723bs/core/rtw_ieee80211.o.old

Something like:

uint rtw_is_cckrates_included(u8 *rate)
{
while (*rate) {
u8 r = *rate & 0x7f;

if (r == 2 || r == 4 || r == 11 || r == 22)
return true;
rate++;
}

return false;
}

uint rtw_is_cckratesonly_included(u8 *rate)
{
while (*rate) {
u8 r = *rate & 0x7f;

if (r != 2 && r != 4 && r != 11 && r != 22)
return false;
rate++;
}

return true;
}

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Re: [PATCH v2 00/18] Some cleanups

2018-07-08 Thread NeilBrown

On Sun, Jul 08 2018, Sergio Paracuellos wrote:

> This patch series clean up a bit mt7621-pci driver.
>
> Changes from v2:
> - It includes new 17 patches from PATCH 2 to PATCH 18
> - PATCH 1 was send before alone and is being included
>   as it is in this new series.
>
> Hope this helps.

Thanks,
I haven't looked though the patches yet, only tested them.
With the two fixed to pinctrl that I posted together
with the change to "avoid pointer arithmetics in some macros"
in this series, they appear to work.  So

  Tested-by: NeilBrown 

I may actually look a them later.

Thanks,
NeilBrown

>
> Best regards,
> Sergio Paracuellos
>
> Sergio Paracuellos (18):
>   staging: mt7621-pci: refactor pci related read and writes functions
>   staging: mt7621-pci: simplify pci dependant registers arithmetics
>   staging: mt7621-pci: avoid pointer arithmetics in some macros
>   staging: mt7621-pci: use BIT macro in definitions
>   staging: mt7621-pci: use read and writes in set_pcie_phy function
>   staging: mt7621-pci: make ASSERT_SYSRST_PCIE and DEASSERT_SYSRST_PCIE
> inline functions
>   staging: mt7621-pci: rewrite [read|write]_config functions
>   staging: mt7621-pci: factor out mt7621_pci_enable_irqs and
> mt7621_pci_disable
>   staging: mt7621-pci: minor refactor in duplicated code
>   staging: mt7621-pci: factor out mt7621_pci_enable function
>   staging: mt7621-pci: factor out mt7621_pci_configure function
>   staging: mt7621-pci: add blank line between declarations and code
> statements
>   staging: mt7621-pci: remove unused preprocessor defines
>   staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG
> definition
>   staging: mt7621-pci: add some common calculations to
> mt7621_pci_get_cfgaddr
>   staging: mt7621-pci: fix and remove some comments
>   staging: mt7621-pci: factor out mt7621_pci_init_gpios function
>   staging: mt7621-pci: add SPDX identifier
>
>  drivers/staging/mt7621-pci/pci-mt7621.c | 706 
> ++--
>  1 file changed, 305 insertions(+), 401 deletions(-)
>
> -- 
> 2.7.4


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[PATCH] ANDROID: binder: Latelimit binder_debug().

2018-07-08 Thread Tetsuo Handa

>From 62ddef96020cb397dcbf4b8574f1859b32f983de Mon Sep 17 00:00:00 2001
From: Tetsuo Handa 
Date: Mon, 9 Jul 2018 09:54:01 +0900
Subject: [PATCH] ANDROID: binder: Latelimit binder_debug().

syzbot is reporting hung tasks [1] [2]. This might be due to flooding of
printk() messages from binder subsystem, for NMI backtrace says the CPU
was busy doing printk() from binder subsystem. Since the kernel log buffer
is trivially spammed by debug messages, let's latelimit binder_debug().

While at it, let's add cond_resched() to binder_thread_write(),
binder_transaction() and binder_release_work() loops because they might
take long time.

[1] 
https://syzkaller.appspot.com/bug?id=0e75779a6f0faac461510c6330514e8f0e893038
[2] 
https://syzkaller.appspot.com/bug?id=aa11d2d767f3750ef9a40d156a149e9cfa735b73

Signed-off-by: Tetsuo Handa 
Reported-by: syzbot+e38306788a2e7102a...@syzkaller.appspotmail.com
Reported-by: syzbot+4417a2fa149da3802...@syzkaller.appspotmail.com
---
 drivers/android/binder.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/android/binder.c b/drivers/android/binder.c
index 95283f3..c136fce 100644
--- a/drivers/android/binder.c
+++ b/drivers/android/binder.c
@@ -161,7 +161,7 @@ static int binder_set_stop_on_user_error(const char *val,
 #define binder_debug(mask, x...) \
do { \
if (binder_debug_mask & mask) \
-   pr_info(x); \
+   pr_info_ratelimited(x); \
} while (0)
 
 #define binder_user_error(x...) \
@@ -3016,7 +3016,7 @@ static void binder_transaction(struct binder_proc *proc,
sg_bufp = (u8 *)(PTR_ALIGN(off_end, sizeof(void *)));
sg_buf_end = sg_bufp + extra_buffers_size;
off_min = 0;
-   for (; offp < off_end; offp++) {
+   for (; offp < off_end; cond_resched(), offp++) {
struct binder_object_header *hdr;
size_t object_size = binder_validate_object(t->buffer, *offp);
 
@@ -3307,6 +3307,7 @@ static int binder_thread_write(struct binder_proc *proc,
 
if (get_user(cmd, (uint32_t __user *)ptr))
return -EFAULT;
+   cond_resched();
ptr += sizeof(uint32_t);
trace_binder_command(cmd);
if (_IOC_NR(cmd) < ARRAY_SIZE(binder_stats.bc)) {
@@ -4193,6 +4194,7 @@ static void binder_release_work(struct binder_proc *proc,
struct binder_work *w;
 
while (1) {
+   cond_resched();
w = binder_dequeue_work_head(proc, list);
if (!w)
return;
-- 
1.8.3.1

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Re: [PATCH v6 2/4] resource: Use list_head to link sibling resource

2018-07-08 Thread Baoquan He

On 07/08/18 at 08:48pm, Andy Shevchenko wrote:
> On Sun, Jul 8, 2018 at 5:59 AM, Baoquan He  wrote:
> > On 07/05/18 at 01:00am, kbuild test robot wrote:
> 
> > However, I didn't find below branch. And tried to open it in web
> > broswer, also failed.
> 
> While this is kinda valid point...
> 
> > Could you help have a look at this?
> 
> ...isn't obvious that you didn't change the file mentioned in a report?
> Just take latest linux-next and you will see.

Yes, it's clear to me. Just want to use the way to cross compile them on
ia64 and mips, hope I can find out all missed places on these ARCHes.
Now I think I can apply patches on linux-next, and use the config
attached to compile. Thanks.

> 
> 
> >> All error/warnings (new ones prefixed by >>):
> >>
> >> >> arch/mips/pci/pci-rc32434.c:57:11: error: initialization from 
> >> >> incompatible pointer type [-Werror=incompatible-pointer-types]
> >>  .child = &rc32434_res_pci_mem2
> >>   ^
> >>arch/mips/pci/pci-rc32434.c:57:11: note: (near initialization for 
> >> 'rc32434_res_pci_mem1.child.next')
> >> >> arch/mips/pci/pci-rc32434.c:51:47: warning: missing braces around 
> >> >> initializer [-Wmissing-braces]
> >> static struct resource rc32434_res_pci_mem1 = {
> >>   ^
> >>arch/mips/pci/pci-rc32434.c:60:47: warning: missing braces around 
> >> initializer [-Wmissing-braces]
> >> static struct resource rc32434_res_pci_mem2 = {
> >>   ^
> >>cc1: some warnings being treated as errors
> >>
> >> vim +57 arch/mips/pci/pci-rc32434.c
> >>
> >> 73b4390f Ralf Baechle 2008-07-16  50
> >> 73b4390f Ralf Baechle 2008-07-16 @51  static struct resource 
> >> rc32434_res_pci_mem1 = {
> >> 73b4390f Ralf Baechle 2008-07-16  52  .name = "PCI MEM1",
> >> 73b4390f Ralf Baechle 2008-07-16  53  .start = 0x5000,
> >> 73b4390f Ralf Baechle 2008-07-16  54  .end = 0x5FFF,
> >> 73b4390f Ralf Baechle 2008-07-16  55  .flags = IORESOURCE_MEM,
> >> 73b4390f Ralf Baechle 2008-07-16  56  .sibling = NULL,
> >> 73b4390f Ralf Baechle 2008-07-16 @57  .child = 
> >> &rc32434_res_pci_mem2
> >> 73b4390f Ralf Baechle 2008-07-16  58  };
> >> 73b4390f Ralf Baechle 2008-07-16  59
> >>
> >> :: The code at line 57 was first introduced by commit
> >> :: 73b4390fb23456964201abda79f1210fe337d01a [MIPS] Routerboard 532: 
> >> Support for base system
> >>
> >> :: TO: Ralf Baechle 
> >> :: CC: Ralf Baechle 
> >>
> >> ---
> >> 0-DAY kernel test infrastructureOpen Source Technology 
> >> Center
> >> https://lists.01.org/pipermail/kbuild-all   Intel 
> >> Corporation
> >
> >
> 
> 
> 
> -- 
> With Best Regards,
> Andy Shevchenko
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Re: [PATCH 13/18] staging: mt7621-pinctrl: make use of pinctrl_utils_reserve_map

2018-07-08 Thread Sergio Paracuellos

On Mon, Jul 09, 2018 at 08:48:14AM +1000, NeilBrown wrote:
> On Thu, Jun 07 2018, Sergio Paracuellos wrote:
> 
> > Function rt2880_pinctrl_dt_node_to_map was using 'kzalloc' to
> > reserve map memory. There is a 'pinctrl_utils_reserve_map' to
> > do this function. Just use it.
> >
> > Signed-off-by: Sergio Paracuellos 
> > ---
> >  drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c | 12 +---
> >  1 file changed, 9 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c 
> > b/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c
> > index a172b68..84494a1 100644
> > --- a/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c
> > +++ b/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c
> > @@ -113,7 +113,10 @@ static int rt2880_pinctrl_dt_node_to_map(struct 
> > pinctrl_dev *pctrldev,
> >  struct pinctrl_map **map,
> >  unsigned int *num_maps)
> >  {
> > +   struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
> > +   int ret;
> > int max_maps = 0;
> > +   unsigned int reserved_maps = 0;
> > struct pinctrl_map *tmp;
> > struct device_node *np;
> >  
> > @@ -127,9 +130,12 @@ static int rt2880_pinctrl_dt_node_to_map(struct 
> > pinctrl_dev *pctrldev,
> > if (!max_maps)
> > return max_maps;
> >  
> > -   *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
> > -   if (!*map)
> > -   return -ENOMEM;
> > +   ret = pinctrl_utils_reserve_map(pctrldev, map, &reserved_maps,
> > +   num_maps, max_maps);
> 
> Unfortunately this is buggy.
> pinctrl_utils_reserve_map() calls krealloc() on *map.
> So we need to initialise
>   *map = NULL;
> 
> before calling it.

Thanks for testing this. I'll send a patch with that initialization.

> 
> Thanks,
> NeilBrown

Best regards,
Sergio Paracuellos


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Re: [PATCH 13/13] staging: mt7621-pinctrl: replace core_initcall_sync with builtin_platform_driver

2018-07-08 Thread Sergio Paracuellos

On Mon, Jul 09, 2018 at 09:40:18AM +1000, NeilBrown wrote:
> On Thu, Jun 28 2018, Sergio Paracuellos wrote:
> 
> > We don't really need initialization of this at such an early stage.
> > Just use builtin_platform_driver to initialize this driver.
> >
> > Signed-off-by: Sergio Paracuellos 
> > ---
> >  drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c | 7 +--
> >  1 file changed, 1 insertion(+), 6 deletions(-)
> >
> > diff --git a/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c 
> > b/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c
> > index 2cce212..7025942 100644
> > --- a/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c
> > +++ b/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c
> > @@ -422,9 +422,4 @@ static struct platform_driver rt2880_pinmux_driver = {
> > },
> >  };
> >  
> > -int __init rt2880_pinmux_init(void)
> > -{
> > -   return platform_driver_register(&rt2880_pinmux_driver);
> > -}
> > -
> > -core_initcall_sync(rt2880_pinmux_init);
> > +builtin_platform_driver(rt2880_pinmux_driver);
> > -- 
> > 2.7.4
> 
> This patch causes the network interface on my device to stop working.
> device_initcall() is called much later than core_initcall_sync() and
> that seem to be a problem.
> I think this needs to be reverted - at least until it is understood.

Ok, if that is the case, Greg, please revert this commit.

Thanks in advance.

> 
> Thanks,
> NeilBrown

Best regards,
Sergio Paracuellos
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Re: [PATCH] staging: mt7621-pci: refactor pci related read and writes functions

2018-07-08 Thread Sergio Paracuellos

On Mon, Jul 09, 2018 at 07:16:41AM +1000, NeilBrown wrote:
> On Sun, Jul 08 2018, Sergio Paracuellos wrote:
> >
> > I can try to split this a bit but I don't really know how to do atomic
> > changes because
> > of the related things included here.
> 
> Some suggestions:
> 
> 1/ MV_READ_DATA is not used.  Discard that any anything else that is
>not used.
> 
> 2/ MV_WRITE is replaced with writel(), MV_READ() with readl().  Make that
>one patch.
> 
> 3/ unsigned int becomes u32.  That is a patch by itself. (maybe this has
>to go before 2.
> 
> 4/ Introduce mt7621_pci_get_cfgaddr() and use it where it is a drop-in
>replacement.
> 
> 5/ Introduce new implementations of pci_config_read() and
>pci_config_write.
> 
> 6/ discard any newly dead code (e.g write_config_* ??)
> 
> Now if there is anything left in the patch is should be clear if it
> could benefit from being broken up.
> 
> Thanks for working on this.

Thanks to you for this advices. I'll try to split this in the way you are
pointing out here.

> 
> NeilBrown

Best regards,
Sergio Paracuellos

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Re: [PATCH v2 03/18] staging: mt7621-pci: avoid pointer arithmetics in some macros

2018-07-08 Thread Sergio Paracuellos

On Mon, Jul 09, 2018 at 09:13:02AM +1000, NeilBrown wrote:
> On Sun, Jul 08 2018, Sergio Paracuellos wrote:
> 
> > RALINK_PCI_MEMBASE, RALINK_PCI_IOBASE, RALINK_PCI_PCICFG_ADDR and
> > RALINK_PCI_PCIMSK_ADDR are using very ugly pointer arithmetics to
> > read and write along the code. Instead of doing this, use the
> > mt7621_pci_reg_read and mt7621_pci_reg_write functions making
> > this a bit cleaner.
> >
> > Signed-off-by: Sergio Paracuellos 
> > ---
> >  drivers/staging/mt7621-pci/pci-mt7621.c | 59 
> > ++---
> >  1 file changed, 25 insertions(+), 34 deletions(-)
> >
> > diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c 
> > b/drivers/staging/mt7621-pci/pci-mt7621.c
> > index 32c37e8..f7defa7 100644
> > --- a/drivers/staging/mt7621-pci/pci-mt7621.c
> > +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
> > @@ -68,14 +68,14 @@
> >  
> >  #define RALINK_PCI_CONFIG_ADDR 0x20
> >  #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
> > -#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 
> > 0x0028)
> > -#define RALINK_PCI_IOBASE  *(volatile u32 *)(RALINK_PCI_BASE + 
> > 0x002C)
> > +#define RALINK_PCI_MEMBASE 0x0028
> > +#define RALINK_PCI_IOBASE  0x002C
> >  #define RALINK_PCIE0_RST   (1<<24)
> >  #define RALINK_PCIE1_RST   (1<<25)
> >  #define RALINK_PCIE2_RST   (1<<26)
> >  
> > -#define RALINK_PCI_PCICFG_ADDR *(volatile u32 
> > *)(RALINK_PCI_BASE + 0x)
> > -#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 
> > *)(RALINK_PCI_BASE + 0x000C)
> > +#define RALINK_PCI_PCICFG_ADDR 0x
> > +#define RALINK_PCI_PCIMSK_ADDR 0x000C
> >  #define RALINK_PCI_BASE0xBE14
> >  
> >  #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
> > @@ -408,6 +408,7 @@ void setup_cm_memory_region(struct resource 
> > *mem_resource)
> >  
> >  static int mt7621_pci_probe(struct platform_device *pdev)
> >  {
> > +   u32 mask;
> > unsigned long val = 0;
> >  
> > mt7621_pci_base = (void __iomem *)RALINK_PCI_BASE;
> > @@ -471,7 +472,9 @@ static int mt7621_pci_probe(struct platform_device 
> > *pdev)
> > pcie_link_status &= ~(1<<0);
> > } else {
> > pcie_link_status |= 1<<0;
> > -   RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
> > +   mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
> > +   mask |= (1<<20); // enable pcie1 interrupt
> > +   mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
> > }
> >  
> > if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(1)) & 0x1) == 0) {
> > @@ -481,7 +484,9 @@ static int mt7621_pci_probe(struct platform_device 
> > *pdev)
> > pcie_link_status &= ~(1<<1);
> > } else {
> > pcie_link_status |= 1<<1;
> > -   RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
> > +   mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
> > +   mask |= (1<<21); // enable pcie1 interrupt
> > +   mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
> > }
> >  
> > if ((mt7621_pci_reg_read(RALINK_PCI_STATUS(2)) & 0x1) == 0) {
> > @@ -491,7 +496,9 @@ static int mt7621_pci_probe(struct platform_device 
> > *pdev)
> > pcie_link_status &= ~(1<<2);
> > } else {
> > pcie_link_status |= 1<<2;
> > -   RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
> > +   mask = mt7621_pci_reg_read(RALINK_PCI_PCIMSK_ADDR);
> > +   mask |= (1<<22); // enable pcie2 interrupt
> > +   mt7621_pci_reg_write(mask, RALINK_PCI_PCIMSK_ADDR);
> > }
> >  
> > if (pcie_link_status == 0)
> > @@ -508,39 +515,23 @@ pcie(2/1/0) link status   pcie2_num   
> > pcie1_num   pcie0_num
> >  3'b110 1   0   x
> >  3'b111 2   1   0
> >  */
> > -   switch (pcie_link_status) {
> > -   case 2:
> > -   RALINK_PCI_PCICFG_ADDR &= ~0x00ff;
> > -   RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;//port0
> > -   RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;//port1
> > -   break;
> > -   case 4:
> > -   RALINK_PCI_PCICFG_ADDR &= ~0x0fff;
> > -   RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;//port0
> > -   RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;//port1
> > -   RALINK_PCI_PCICFG_ADDR |= 0x0 << 24;//port2
> > -   break;
> > -   case 5:
> > -   RALINK_PCI_PCICFG_ADDR &= ~0x0fff;
> > -   RALINK_PCI_PCICFG_ADDR |= 0x0 << 16;//port0
> > -   RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;//port1
> > -   RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;//port2
> > -   break;
> > -   case 6:
> > -   RALINK_PCI_PCICFG_ADDR &= ~0x0fff;
> > -   RALINK_PCI_PCICFG_ADDR |= 0x2 << 16;//port0
> > -   RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;//port1
> > -

Re: [PATCH v2 00/18] Some cleanups

2018-07-08 Thread Sergio Paracuellos

On Mon, Jul 09, 2018 at 11:08:58AM +1000, NeilBrown wrote:
> On Sun, Jul 08 2018, Sergio Paracuellos wrote:
> 
> > This patch series clean up a bit mt7621-pci driver.
> >
> > Changes from v2:
> > - It includes new 17 patches from PATCH 2 to PATCH 18
> > - PATCH 1 was send before alone and is being included
> >   as it is in this new series.
> >
> > Hope this helps.
> 
> Thanks,
> I haven't looked though the patches yet, only tested them.
> With the two fixed to pinctrl that I posted together
> with the change to "avoid pointer arithmetics in some macros"
> in this series, they appear to work.  So
> 
>   Tested-by: NeilBrown 
> 
> I may actually look a them later.

Thanks for testing this. Greg, I think is still neccessary to split up
patch 1 for better reviewing. If not, please let me know. I'll
try to do that hopefully tonight.

> 
> Thanks,
> NeilBrown

Thanks for your effort and support, Neil.

Best regards,
Sergio Paracuellos
> 
> >
> > Best regards,
> > Sergio Paracuellos
> >
> > Sergio Paracuellos (18):
> >   staging: mt7621-pci: refactor pci related read and writes functions
> >   staging: mt7621-pci: simplify pci dependant registers arithmetics
> >   staging: mt7621-pci: avoid pointer arithmetics in some macros
> >   staging: mt7621-pci: use BIT macro in definitions
> >   staging: mt7621-pci: use read and writes in set_pcie_phy function
> >   staging: mt7621-pci: make ASSERT_SYSRST_PCIE and DEASSERT_SYSRST_PCIE
> > inline functions
> >   staging: mt7621-pci: rewrite [read|write]_config functions
> >   staging: mt7621-pci: factor out mt7621_pci_enable_irqs and
> > mt7621_pci_disable
> >   staging: mt7621-pci: minor refactor in duplicated code
> >   staging: mt7621-pci: factor out mt7621_pci_enable function
> >   staging: mt7621-pci: factor out mt7621_pci_configure function
> >   staging: mt7621-pci: add blank line between declarations and code
> > statements
> >   staging: mt7621-pci: remove unused preprocessor defines
> >   staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG
> > definition
> >   staging: mt7621-pci: add some common calculations to
> > mt7621_pci_get_cfgaddr
> >   staging: mt7621-pci: fix and remove some comments
> >   staging: mt7621-pci: factor out mt7621_pci_init_gpios function
> >   staging: mt7621-pci: add SPDX identifier
> >
> >  drivers/staging/mt7621-pci/pci-mt7621.c | 706 
> > ++--
> >  1 file changed, 305 insertions(+), 401 deletions(-)
> >
> > -- 
> > 2.7.4


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[PATCH] staging: mt7621-pinctrl: init *map to NULL for correct memory assignation

2018-07-08 Thread Sergio Paracuellos

pinctrl_utils_reserve_map() calls krealloc() on *map. Because of this
*map need to be initialized to NULL before calling it.

Fixes: 62b6215c11ea ("staging: mt7621-pinctrl: make use of
pinctrl_utils_reserve_map")

Signed-off-by: Sergio Paracuellos 
---
 drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c 
b/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c
index 7025942..c223ecb 100644
--- a/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c
+++ b/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c
@@ -88,6 +88,7 @@ static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev 
*pctrldev,
for_each_node_with_property(np_config, "group")
ngroups++;
 
+   *map = NULL;
ret = pinctrl_utils_reserve_map(pctrldev, map, &reserved_maps,
num_maps, ngroups);
if (ret) {
-- 
2.7.4

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[PATCH] Staging:fwserial Move LINUX_VENDOR_ID to firewire.h

2018-07-08 Thread Janani Sankara Babu

This driver uses the same unregistered vendor id that the
firewire core does (0xd00d1e). Hence it is exposed as a
define in firewire.h.

Signed-off-by:Janani Sankara Babu 
---
 drivers/staging/fwserial/fwserial.c | 1 -
 include/linux/firewire.h| 2 ++
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/staging/fwserial/fwserial.c 
b/drivers/staging/fwserial/fwserial.c
index e8bfe55..f2966f2 100644
--- a/drivers/staging/fwserial/fwserial.c
+++ b/drivers/staging/fwserial/fwserial.c
@@ -21,0 +21,0 @@

 #define be32_to_u64(hi, lo)  ((u64)be32_to_cpu(hi) << 32 | be32_to_cpu(lo))

-#define LINUX_VENDOR_ID   0xd00d1eU  /* same id used in card root directory   
*/
 #define FWSERIAL_VERSION  0x00e81cU  /* must be unique within LINUX_VENDOR_ID 
*/

 /* configurable options */
diff --git a/include/linux/firewire.h b/include/linux/firewire.h
index aec8f30..62cdff1 100644
--- a/include/linux/firewire.h
+++ b/include/linux/firewire.h
@@ -66,2 +66,2 @@
 #define CSR_MODEL  0x17
 #define CSR_DIRECTORY_ID   0x20

+#define LINUX_VENDOR_ID   0xd00d1eU  /* same id used in card root directory   
*/
+
 struct fw_csr_iterator {
const u32 *p;
const u32 *end;
--
1.9.1
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