Re: Fwd: [Bug debug/53754] [4.8 Regression][lto] ICE in lhd_decl_printable_name, at langhooks.c:222 (with -g)
On Thu, 28 Jun 2012, Cary Coutant wrote: [resending in plain text. Sorry, gmail defaulted to HTML.] Ping. I'm not looking for commit approval yet, just advice on how thorough we need to be to support -g and LTO together. (What's the right way to send a patch to fix a PR? I'm not even sure whether you were cc'ed on my response.) The right way to send a patch to fix a PR is to send it to gcc-patches ;) You can't delay producing pubnames this way with LTO. Please fix. The obvious problem is that we're calling langhooks.dwarf_name (in gen_namespace_die) for an anonymous namespace, even with the default -gno-pubnames. I can fix that by adding a check for want_pubnames just before the call to add_pubname_string, as in the patch below. But this is still going That's sensible anyways - you avoid useless work. So the patch is ok. But still ... to ICE if you turn on -gpubnames with -lto. The only way I can think of to fix that is relax the assert in lhd_decl_printable_name, and just have it return an empty string in the DECL_NAMELESS case. That will not produce the right results for an anonmyous namespace, but without front-end langhooks available to us (and until we implement the lazy debug plan), how can we do better? ... produce the pubnames early. I mean, each object you want to have its pubname appear in .pubnames at dwarf2out.c time has to have the pubname created by the frontend. As far as I can quickly decipher the pubname is what lang_hooks.dwarf_name () returns, right? I'd say we have to bite the bullet at some point (this point?) and add a pointer to debug-format specific data to each tree node we eventually emit debug information for (that is types and decls I presume, both at most those that have the lang_specific pointer - in fact we might re-use that pointer, initially hang off the debug-info ptr from lang_specific data and at free-lang-data time re-link it as gimple-lang-specific). How much is expected to work today with LTO and -g? Aren't we still stuck with calling langhooks from dwarf2out.c back-end routines? I can understand that we don't want to ICE, but what guarantees do we make about debug info Well, LTO and -g is expected to work as to not ICE and produce reasonable debug information up to the point where we cannot create language specific info late. That's what you broke (the not-ICE part). In practice LTO with -g works quite well - you can even debug things. It's of course not perfect, but today only because of lang-hooks used in debug output and because of the issue we have with early inline transforms (BLOCK trees get slightly hosed there, there is a bug about this). Richard.
Commit: LM32: Fix typo in
Hi Sebastien, Hi Steven
I am applying the patch below as obvious fix for a typo in lm32.c.
Cheers
Nick
gcc/ChangeLog
2012-06-29 Nick Clifton ni...@redhat.com
* config/lm32/lm32.c (lm32_compute_frame_size): Fix typo.
Index: lm32.c
===
--- lm32.c (revision 189064)
+++ lm32.c (working copy)
@@ -460,7 +460,7 @@
callee_size += UNITS_PER_WORD;
}
}
- if (df_regs_ever_live_p (RA_REGNUM) || crtl-is_leaf!
+ if (df_regs_ever_live_p (RA_REGNUM) || ! crtl-is_leaf
|| !optimize)
{
reg_save_mask |= 1 RA_REGNUM;
RFA: MEP: Fix use of delete_insn.
Hi DJ,
The delete_insn() function no longer returns the insn after the one
that has been deleted, so gcc/config/mep/mep.c:mep_reorg_regmove() no
longer compiles. The patch below is a simple fix for the problem, but
I was not sure whether it would be better to use
next_nonnote_nondebug_insn() instead. What do you think ?
Cheers
Nick
gcc/ChangeLog
2012-06-29 Nick Clifton ni...@redhat.com
* config/mep/mep.c (mep_reorg_regmove): Get next insn before
calling delete_insn.
Index: gcc/config/mep/mep.c
===
--- gcc/config/mep/mep.c(revision 189064)
+++ gcc/config/mep/mep.c(working copy)
@@ -5096,7 +5096,8 @@
follow, where))
{
count ++;
- next = delete_insn (insn);
+ next = NEXT_INSN (insn);
+ delete_insn (insn);
if (dump_file)
{
fprintf (dump_file, \n- Success! new insn:\n\n);
RFA: MN10300: Replace REG_SAVE_BYTES macro with calls to mn10300_get_live_callee_saved_regs
Hi Jeff, Hi Alex,
I recently encountered a problem with the REG_SAVE_BYTES macro in the
mn10300 backend. When compiling some code in -fPID mode it was
producing a different result to the mask computed by
mn10300_get_live_callee_saved_regs. The problem turned out to be that
the macro was not checking the call_really_saved_regs array. Rather
than update the macro, it seemed to me that it would be better to just
make this computation in one place - the
mn10300_get_live_callee_saved_regs function - and avoid problems like
this in the future.
So attached is a patch that does this. Tested with no regressions on
an mn10300-elf and an am33_2.0-linux-gnu toolchain. OK to apply ?
Cheers
Nick
gcc/ChangeLog
2012-06-29 Nick Clifton ni...@redhat.com
* config/mn10300/mn10300.c (REG_SAVE_BYTES): Delete.
(mn10300_get_live_callee_saved_regs): If requested return a count
of the number of bytes in the mask.
(mn10300_expand_prologue): Add argument to invocation of
mn10300_get_live_callee_regs.
(mn10300_expand_epilogue): Compute reg_save_bytes by calling
mn10300_get_live_callee_saved_regs.
(mn10300_initial_offset): Likewise.
* config/mn10300/mn10300-protos.h (mn10300_get_live_callee_saved_regs):
Update prototype.
* config/mn10300/mn10300.md (return_ret): Add argument to
invocation of mn10300_get_live_callee_saved_regs.
Index: gcc/config/mn10300/mn10300.md
===
--- gcc/config/mn10300/mn10300.md (revision 189067)
+++ gcc/config/mn10300/mn10300.md (working copy)
@@ -2048,7 +2048,7 @@
{
/* The RETF insn is up to 3 cycles faster than RET. */
fputs ((mn10300_can_use_retf_insn () ? \tretf : \tret ), asm_out_file);
- mn10300_print_reg_list (asm_out_file, mn10300_get_live_callee_saved_regs ());
+ mn10300_print_reg_list (asm_out_file, mn10300_get_live_callee_saved_regs
(NULL));
fprintf (asm_out_file, ,%d\n, (int) INTVAL (operands[0]));
return ;
})
Index: gcc/config/mn10300/mn10300-protos.h
===
--- gcc/config/mn10300/mn10300-protos.h (revision 189067)
+++ gcc/config/mn10300/mn10300-protos.h (working copy)
@@ -25,7 +25,7 @@
extern rtx mn10300_legitimize_reload_address (rtx, enum machine_mode,
int, int, int);
extern bool mn10300_function_value_regno_p (const unsigned int);
-extern int mn10300_get_live_callee_saved_regs (void);
+extern unsigned int mn10300_get_live_callee_saved_regs (unsigned int *);
extern bool mn10300_hard_regno_mode_ok (unsigned int, enum machine_mode);
extern bool mn10300_modes_tieable (enum machine_mode, enum machine_mode);
extern const char *mn10300_output_add (rtx[3], bool);
Index: gcc/config/mn10300/mn10300.c
===
--- gcc/config/mn10300/mn10300.c(revision 189067)
+++ gcc/config/mn10300/mn10300.c(working copy)
@@ -56,18 +56,6 @@
/* Selected processor type for tuning. */
enum processor_type mn10300_tune_cpu = PROCESSOR_DEFAULT;
-/* The size of the callee register save area. Right now we save everything
- on entry since it costs us nothing in code size. It does cost us from a
- speed standpoint, so we want to optimize this sooner or later. */
-#define REG_SAVE_BYTES (4 * df_regs_ever_live_p (2)\
- + 4 * df_regs_ever_live_p (3) \
- + 4 * df_regs_ever_live_p (6) \
- + 4 * df_regs_ever_live_p (7) \
- + 16 * (df_regs_ever_live_p (14)\
- || df_regs_ever_live_p (15) \
- || df_regs_ever_live_p (16) \
- || df_regs_ever_live_p (17)))
-
#define CC_FLAG_Z 1
#define CC_FLAG_N 2
#define CC_FLAG_C 4
@@ -634,21 +622,36 @@
/* Returns the set of live, callee-saved registers as a bitmask. The
callee-saved extended registers cannot be stored individually, so
- all of them will be included in the mask if any one of them is used. */
+ Also returns the number of bytes in the registers in the mask if
+ BYTES_SAVED is not NULL. */
-int
-mn10300_get_live_callee_saved_regs (void)
+unsigned int
+mn10300_get_live_callee_saved_regs (unsigned int * bytes_saved)
{
int mask;
int i;
+ unsigned int count;
- mask = 0;
+ count = mask = 0;
for (i = 0; i = LAST_EXTENDED_REGNUM; i++)
if (df_regs_ever_live_p (i) ! call_really_used_regs[i])
- mask |= (1 i);
+ {
+ mask |= (1 i);
+ ++ count;
+ }
+
if ((mask 0x3c000) != 0)
-mask |= 0x3c000;
+{
+ for (i = 0x04000; i 0x4; i = 1)
+ if ((mask i) == 0)
+ ++ count;
+
+ mask |= 0x3c000;
+}
+ if (bytes_saved)
+
Re: [PATCH] Add MULT_HIGHPART_EXPR
On Fri, Jun 29, 2012 at 11:00:14AM +0200, Richard Guenther wrote: Indeed - the lack of cross-sub-128bit-word operations makes it very much expensive for some vectorizations. Initially we added the patterns for vectorization of the hi/lo and interleave stuff because we didn't want regressions for vectorizing with 256bit vectors vs. 128bit vectors in the vectorizer testsuite. But now as we have support for vectorizing with both sizes we could consider not advertising the really not existing intstructions for 256bit vectors. Or at least properly model their cost. The pr51581-3.c (f2) generated code is only shorter with -O3 -mavx when using hi/lo over even/odd, with -O3 -mavx2 even/odd sequence is shorter than hi/lo. $ ~/timing ./pr51581-3-evenodd Strip out best and worst realtime result minimum: 0.110145575 sec real / 0.71177 sec CPU maximum: 0.134790162 sec real / 0.000140234 sec CPU average: 0.113982306 sec real / 0.000113236 sec CPU stdev : 0.002545680 sec real / 0.09365 sec CPU $ ~/timing ./pr51581-3-hilo Strip out best and worst realtime result minimum: 0.098651474 sec real / 0.69318 sec CPU maximum: 0.102126514 sec real / 0.000129507 sec CPU average: 0.100120802 sec real / 0.000104589 sec CPU stdev : 0.001008010 sec real / 0.13241 sec CPU Can't benchmark -mavx2 though... Jakub
[Patch ARM] Backport fix for off-by-one vrev error.
Hi, This backports the off-by-one fix for vrev to the ARM port as mentioned in my post earlier here. Since I've heard no objections from the release branch maintainers or anyone else , and given I've not seen any fallout from the auto-testers I'm backporting this to the FSF 4.7 branch. http://gcc.gnu.org/ml/gcc-patches/2012-05/msg01962.html regards, Ramana 2012-06-29 Ramana Radhakrishnan ramana.radhakrish...@linaro.org Backport from mainline. 2012-05-30 Ramana Radhakrishnan ramana.radhakrish...@linaro.org * config/arm/arm.c (arm_evpc_neon_vrev): Adjust off by one error. 2012-06-29 Ramana Radhakrishnan ramana.radhakrish...@linaro.org Backport from mainline. 2012-05-30 Ramana Radhakrishnan ramana.radhakrish...@linaro.org * gcc.target/arm/neon-vrev.c: New. final-neon-vrev-47 Description: Binary data
[Patch ARM] Backport fix for gnu_unique_object to 4.7 branch
Hi,
Taking Richi's statement here
http://gcc.gnu.org/ml/gcc-patches/2012-06/msg01399.html as an approval
- I've backported the comment character fix for gnu_unique_object on
ARM to the FSF 4.7 branch.
regards,
Ramana
2012-06-29 Ramana Radhakrishnan ramana.radhakrish...@linaro.org
* configure: Regenerate.
Backport from mainline.
2012-03-15 Ramana Radhakrishnan ramana.radhakrish...@linaro.org
* config.gcc (target_type_format_char): New. Document it. Set it for
arm*-*-* .
* configure.ac (gnu_unique_option): Use target_type_format_char
in test. Comment rationale.
Index: gcc/configure
===
--- gcc/configure (revision 189069)
+++ gcc/configure (revision 189071)
@@ -26179,7 +26179,7 @@
then gcc_cv_as_gnu_unique_object=yes
fi
elif test x$gcc_cv_as != x; then
-$as_echo '.type foo, @gnu_unique_object' conftest.s
+$as_echo '.type foo, '$target_type_format_char'gnu_unique_object'
conftest.s
if { ac_try='$gcc_cv_as $gcc_cv_as_flags -o conftest.o conftest.s 5'
{ { eval echo \\$as_me\:${as_lineno-$LINENO}: \$ac_try\; } 5
(eval $ac_try) 25
@@ -26198,7 +26198,8 @@
{ $as_echo $as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_gnu_unique_object
5
$as_echo $gcc_cv_as_gnu_unique_object 6; }
if test $gcc_cv_as_gnu_unique_object = yes; then
- # Also check for ld.so support, i.e. glibc 2.11 or higher.
+ # We need to unquote above to to use the definition from config.gcc.
+# Also check for ld.so support, i.e. glibc 2.11 or higher.
if test x$host = x$build -a x$host = x$target
ldd --version 2/dev/null
glibcver=`ldd --version 2/dev/null | sed 's/.* //;q'`; then
Index: gcc/configure.ac
===
--- gcc/configure.ac(revision 189069)
+++ gcc/configure.ac(revision 189071)
@@ -4188,7 +4188,8 @@
esac],
[gcc_GAS_CHECK_FEATURE([gnu_unique_object], gcc_cv_as_gnu_unique_object,
[elf,2,19,52],,
- [.type foo, @gnu_unique_object],,
+ [.type foo, '$target_type_format_char'gnu_unique_object],,
+# We need to unquote above to to use the definition from config.gcc.
# Also check for ld.so support, i.e. glibc 2.11 or higher.
[[if test x$host = x$build -a x$host = x$target
ldd --version 2/dev/null
Index: gcc/config.gcc
===
--- gcc/config.gcc (revision 189069)
+++ gcc/config.gcc (revision 189071)
@@ -184,6 +184,11 @@
# the --with-sysroot configure option or the
# --sysroot command line option is used this
# will be relative to the sysroot.
+# target_type_format_char
+# The default character to be used for formatting
+# the attribute in a
+# .type symbol_name, ${t_t_f_c}property
+# directive.
# The following variables are used in each case-construct to build up the
# outgoing variables:
@@ -235,6 +240,7 @@
need_64bit_hwint=
need_64bit_isa=
native_system_header_dir=/usr/include
+target_type_format_char='@'
# Don't carry these over build-host-target. Please.
xm_file=
@@ -321,6 +327,7 @@
arm*-*-*)
cpu_type=arm
extra_headers=mmintrin.h arm_neon.h
+ target_type_format_char='%'
c_target_objs=arm-c.o
cxx_target_objs=arm-c.o
extra_options=${extra_options} arm/arm-tables.opt
Property changes on: .
___
Modified: svn:mergeinfo
Merged /trunk:r185428
Re: [onlinedocs]: No more automatic rebuilt?
Next problem: libiberty. This looks reasonably well in dvi and pdf. OK? That should really be the last error. Andreas. * copying-lib.texi (Library Copying): Don't use @heading inside @enumerate. diff --git a/libiberty/copying-lib.texi b/libiberty/copying-lib.texi index 79e1038..31ef68b 100644 --- a/libiberty/copying-lib.texi +++ b/libiberty/copying-lib.texi @@ -476,12 +476,7 @@ decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally. -@iftex -@heading NO WARRANTY -@end iftex -@ifinfo @center NO WARRANTY -@end ifinfo @item BECAUSE THE LIBRARY IS LICENSED FREE OF CHARGE, THERE IS NO -- 1.7.11.1 -- Andreas Schwab, sch...@linux-m68k.org GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5 And now for something completely different.
Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant
Hi
So the following is updated patch. Tested on qemu with arm/thumb modes
without regression.
thanks
Carrot
2012-06-29 Wei Guozhi car...@google.com
PR target/53447
* gcc.target/arm/pr53447-1.c: New testcase.
* gcc.target/arm/pr53447-2.c: New testcase.
2012-06-29 Wei Guozhi car...@google.com
PR target/53447
* config/arm/arm-protos.h (const_ok_for_dimode_op): New prototype.
* config/arm/arm.c (const_ok_for_dimode_op): New function.
* config/arm/constraints.md (Dd): New constraint.
* config/arm/predicates.md (arm_adddi_operand): New predicate.
* config/arm/arm.md (adddi3): Extend it to handle constants.
(arm_adddi3): Likewise.
(addsi3_carryin_optab): Extend it to handle sbc case.
* config/arm/neon.md (adddi3_neon): Extend it to handle constants.
Index: testsuite/gcc.target/arm/pr53447-1.c
===
--- testsuite/gcc.target/arm/pr53447-1.c(revision 0)
+++ testsuite/gcc.target/arm/pr53447-1.c(revision 0)
@@ -0,0 +1,8 @@
+/* { dg-options -O2 } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-final { scan-assembler-not mov } } */
+
+void t0p(long long * p)
+{
+ *p += 0x10001;
+}
Index: testsuite/gcc.target/arm/pr53447-2.c
===
--- testsuite/gcc.target/arm/pr53447-2.c(revision 0)
+++ testsuite/gcc.target/arm/pr53447-2.c(revision 0)
@@ -0,0 +1,8 @@
+/* { dg-options -O2 } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-final { scan-assembler-not mov } } */
+
+void t0p(long long * p)
+{
+ *p -= 0x10008;
+}
Index: config/arm/arm.c
===
--- config/arm/arm.c(revision 187751)
+++ config/arm/arm.c(working copy)
@@ -2497,6 +2497,28 @@
}
}
+/* Return true if I is a valid di mode constant for the operation CODE. */
+int
+const_ok_for_dimode_op (HOST_WIDE_INT i, enum rtx_code code)
+{
+ HOST_WIDE_INT hi_val = (i 32) 0x;
+ HOST_WIDE_INT lo_val = i 0x;
+ rtx hi = GEN_INT (hi_val);
+ rtx lo = GEN_INT (lo_val);
+
+ if (TARGET_THUMB1)
+return 0;
+
+ switch (code)
+{
+case PLUS:
+ return arm_not_operand (hi, SImode) arm_add_operand (lo, SImode);
+
+default:
+ return 0;
+}
+}
+
/* Emit a sequence of insns to handle a large constant.
CODE is the code of the operation required, it can be any of SET, PLUS,
IOR, AND, XOR, MINUS;
Index: config/arm/arm-protos.h
===
--- config/arm/arm-protos.h (revision 187751)
+++ config/arm/arm-protos.h (working copy)
@@ -49,6 +49,7 @@
extern bool arm_modes_tieable_p (enum machine_mode, enum machine_mode);
extern int const_ok_for_arm (HOST_WIDE_INT);
extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
+extern int const_ok_for_dimode_op (HOST_WIDE_INT, enum rtx_code);
extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx,
HOST_WIDE_INT, rtx, rtx, int);
extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, rtx *, rtx *);
Index: config/arm/neon.md
===
--- config/arm/neon.md (revision 187751)
+++ config/arm/neon.md (working copy)
@@ -588,9 +588,9 @@
)
(define_insn adddi3_neon
- [(set (match_operand:DI 0 s_register_operand =w,?r,?r,?w)
-(plus:DI (match_operand:DI 1 s_register_operand %w,0,0,w)
- (match_operand:DI 2 s_register_operand w,r,0,w)))
+ [(set (match_operand:DI 0 s_register_operand =w,?r,?r,?w,?r,?r,?r)
+(plus:DI (match_operand:DI 1 s_register_operand %w,0,0,w,r,0,r)
+ (match_operand:DI 2 arm_adddi_operand
w,r,0,w,r,Dd,Dd)))
(clobber (reg:CC CC_REGNUM))]
TARGET_NEON
{
@@ -600,13 +600,16 @@
case 3: return vadd.i64\t%P0, %P1, %P2;
case 1: return #;
case 2: return #;
+case 4: return #;
+case 5: return #;
+case 6: return #;
default: gcc_unreachable ();
}
}
- [(set_attr neon_type neon_int_1,*,*,neon_int_1)
- (set_attr conds *,clob,clob,*)
- (set_attr length *,8,8,*)
- (set_attr arch nota8,*,*,onlya8)]
+ [(set_attr neon_type neon_int_1,*,*,neon_int_1,*,*,*)
+ (set_attr conds *,clob,clob,*,clob,clob,clob)
+ (set_attr length *,8,8,*,8,8,8)
+ (set_attr arch nota8,*,*,onlya8,*,*,*)]
)
(define_insn *submode3_neon
Index: config/arm/constraints.md
===
--- config/arm/constraints.md (revision 187751)
+++ config/arm/constraints.md (working copy)
@@ -29,7 +29,7 @@
;; in Thumb-1 state: I, J, K, L, M, N, O
;; The following multi-letter normal constraints have been used:
-;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dt, Dz
+;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, Dl, DL, Dv, Dy, Di, Dt, Dz
;; in
Re: [PATCH][RFC, Reload]. Reload bug?
Tejas Belagod wrote: Therefore strict_memory_address_addr_space_P () thinks that (mem:OI (reg sp)) is a valid target address and lets it pass as a subreg and does not narrow the subreg into a narrower memref. find_reloads_toplev () should have infact given strict_memory_address_addr_space_P () (mem:OI (plus:DI (reg sp) (const_int 16))) which will be returned as false as base+offset is invalid for NEON addressing modes and this will be reloaded into a narrower memref. Huh. I would have expected the offsettable_memref_p check -(reg_equiv_address (regno) != 0 - || (reg_equiv_mem (regno) != 0 -(! strict_memory_address_addr_space_p - (GET_MODE (x), XEXP (reg_equiv_mem (regno), 0), -MEM_ADDR_SPACE (reg_equiv_mem (regno))) - || ! offsettable_memref_p (reg_equiv_mem (regno)) ^^^ here - || num_not_at_initial_offset to fail, which should cause find_reloads_subreg_address to get called. Why is that not happening for you? Bye, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com
Re: Ping: [RFA:] Caveat for ARM in gcc-4.7/changes.html: unaligned accesses, take 2
From: Hans-Peter Nilsson h...@axis.com Date: Fri, 22 Jun 2012 04:24:01 +0200 From: Hans-Peter Nilsson h...@axis.com Date: Fri, 15 Jun 2012 04:07:23 +0200 A ping. And another ping, now CCing ARM maintainers, http://gcc.gnu.org/ml/gcc-patches/2012-06/msg00983.html. Y is 28 for introduction of the quoted code in arch/arm/mm/alignment.c, AFAICT, so how about this one, ok now? Index: changes.html === RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v retrieving revision 1.113 diff -p -u -r1.113 changes.html --- changes.html5 Jun 2012 11:03:53 - 1.113 +++ changes.html15 Jun 2012 02:04:46 - @@ -43,6 +43,19 @@ /li +liOn ARM, when compiling for ARMv6 (but not ARMv6-M), ARMv7-A, +ARMv7-R, or ARMv7-M, the new option +code-munaligned-access/code is active by default, which for +some source codes generates code that accesses memory on unaligned +adresses. This will require the kernel of those systems to enable +such accesses (controlled by CP15 register codec1/code, refer +to ARM documentation). Alternatively or for compatibility with +kernels where unaligned accesses are not supported, all code has +to be compiled with code-mno-unaligned-access/code. +Linux/ARM in official releases has automatically and +unconditionally supported unaligned accesses as emitted by GCC due +to this option being active since Linux version 2.6.28./li + liSupport on ARM for the legacy floating-point accelerator (FPA) and the mixed-endian floating-point format that it used has been obsoleted. The ports that still use this format have been obsoleted as well.
[PATCH] Testcase for fixed PR52589
Tested on x86_64-unknown-linux-gnu, applied.
Richard.
2012-06-29 Richard Guenther rguent...@suse.de
PR tree-optimization/52589
* gcc.dg/tree-ssa/vrp70.c: New testcase.
Index: testsuite/gcc.dg/tree-ssa/vrp70.c
===
--- testsuite/gcc.dg/tree-ssa/vrp70.c (revision 0)
+++ testsuite/gcc.dg/tree-ssa/vrp70.c (working copy)
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options -O2 -fdump-tree-vrp1 } */
+
+extern void link_error (void);
+
+void
+foo (unsigned int s)
+{
+ if (s + 0x7000 0xf000U)
+{
+ if (s = 0x8000U s 0x9000U)
+ link_error ();
+}
+}
+
+void
+bar (unsigned int s)
+{
+ if (s + 0x7000 = 0xf000U)
+{
+ if (s 0x8000U || s = 0x9000U)
+ link_error ();
+}
+}
+
+/* { dg-final { scan-tree-dump-not link_error vrp1 } } */
+/* { dg-final { cleanup-tree-dump vrp1 } } */
Re: [PATCH][RFC, Reload]. Reload bug?
Ulrich Weigand wrote: Tejas Belagod wrote: Therefore strict_memory_address_addr_space_P () thinks that (mem:OI (reg sp)) is a valid target address and lets it pass as a subreg and does not narrow the subreg into a narrower memref. find_reloads_toplev () should have infact given strict_memory_address_addr_space_P () (mem:OI (plus:DI (reg sp) (const_int 16))) which will be returned as false as base+offset is invalid for NEON addressing modes and this will be reloaded into a narrower memref. Huh. I would have expected the offsettable_memref_p check - (reg_equiv_address (regno) != 0 - || (reg_equiv_mem (regno) != 0 - (! strict_memory_address_addr_space_p - (GET_MODE (x), XEXP (reg_equiv_mem (regno), 0), - MEM_ADDR_SPACE (reg_equiv_mem (regno))) - || ! offsettable_memref_p (reg_equiv_mem (regno)) ^^^ here - || num_not_at_initial_offset to fail, which should cause find_reloads_subreg_address to get called. Why is that not happening for you? This is because offsettable_address_addr_space_p () gets as far as calling strict_memory_address_addr_space_p () with a QImode and (mode_sz - 1) which returns true. The only way I see offsettable_address_addr_space_p () returning false would be mode_dependent_address_p () to return true for addr expression (PLUS (reg) (16)) which partly makes sense to me because PLUS is a mode-dependent address in that it cannot be allowed for NEON addressing modes, but it seems very generic for mode_dependent_address_p () to return true for PLUS in general instead of making a special case for vector modes. This distinction cannot be made in the target's mode_dependent_address_p() as 'mode' is not supplied to it. Thanks, Tejas Belagod. ARM.
[PATCH] Adjust gcc.dg/tree-ssa/pr37508.c for PR37541
Tested on x86_64-unknown-linux-gnu, applied.
Richard.
2012-06-29 Richard Guenther rguent...@suse.de
PR tree-optimization/37541
* gcc.dg/tree-ssa/pr37508.c: Adjust and un-XFAIL.
Index: gcc/testsuite/gcc.dg/tree-ssa/pr37508.c
===
--- gcc/testsuite/gcc.dg/tree-ssa/pr37508.c (revision 189072)
+++ gcc/testsuite/gcc.dg/tree-ssa/pr37508.c (working copy)
@@ -30,7 +30,7 @@ int test3 (struct foo1 *x)
{
if (x-i == 0)
return 1;
- else if (x-i == 1)
+ else if (x-i == 1) /* This test is already folded to false by fold. */
return 1;
return 0;
}
@@ -44,5 +44,5 @@ int test4 (struct foo2 *x)
return 0;
}
-/* { dg-final { scan-tree-dump-times Folding 4 vrp1 { xfail *-*-* } } } */
+/* { dg-final { scan-tree-dump-times Folding 3 vrp1 } } */
/* { dg-final { cleanup-tree-dump vrp1 } } */
Re: [ARM Patch 1/n] PR53447: optimizations of 64bit ALU operation with constant
On 29 June 2012 12:23, Carrot Wei car...@google.com wrote:
Hi
So the following is updated patch. Tested on qemu with arm/thumb modes
Assuming this testing was with and without neon ? Because the patterns
changed are different whether you use Neon or not.
without regression.
Can you add some tests for all 4 cases ? See comments inline below for
some changes ?
Ok with those changes if no regressions for above mentioned testing.
thanks
Carrot
2012-06-29 Wei Guozhi car...@google.com
PR target/53447
* gcc.target/arm/pr53447-1.c: New testcase.
* gcc.target/arm/pr53447-2.c: New testcase.
2012-06-29 Wei Guozhi car...@google.com
PR target/53447
* config/arm/arm-protos.h (const_ok_for_dimode_op): New prototype.
* config/arm/arm.c (const_ok_for_dimode_op): New function.
* config/arm/constraints.md (Dd): New constraint.
* config/arm/predicates.md (arm_adddi_operand): New predicate.
* config/arm/arm.md (adddi3): Extend it to handle constants.
(arm_adddi3): Likewise.
(addsi3_carryin_optab): Extend it to handle sbc case.
* config/arm/neon.md (adddi3_neon): Extend it to handle constants.
Index: testsuite/gcc.target/arm/pr53447-1.c
===
--- testsuite/gcc.target/arm/pr53447-1.c (revision 0)
+++ testsuite/gcc.target/arm/pr53447-1.c (revision 0)
@@ -0,0 +1,8 @@
+/* { dg-options -O2 } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-final { scan-assembler-not mov } } */
+
+void t0p(long long * p)
+{
+ *p += 0x10001;
+}
Index: testsuite/gcc.target/arm/pr53447-2.c
===
--- testsuite/gcc.target/arm/pr53447-2.c (revision 0)
+++ testsuite/gcc.target/arm/pr53447-2.c (revision 0)
@@ -0,0 +1,8 @@
+/* { dg-options -O2 } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-final { scan-assembler-not mov } } */
+
+void t0p(long long * p)
+{
+ *p -= 0x10008;
+}
Index: config/arm/arm.c
===
--- config/arm/arm.c (revision 187751)
+++ config/arm/arm.c (working copy)
@@ -2497,6 +2497,28 @@
}
}
+/* Return true if I is a valid di mode constant for the operation CODE. */
+int
+const_ok_for_dimode_op (HOST_WIDE_INT i, enum rtx_code code)
+{
+ HOST_WIDE_INT hi_val = (i 32) 0x;
+ HOST_WIDE_INT lo_val = i 0x;
+ rtx hi = GEN_INT (hi_val);
+ rtx lo = GEN_INT (lo_val);
+
+ if (TARGET_THUMB1)
+ return 0;
+
+ switch (code)
+ {
+ case PLUS:
+ return arm_not_operand (hi, SImode) arm_add_operand (lo, SImode);
+
+ default:
+ return 0;
+ }
+}
+
/* Emit a sequence of insns to handle a large constant.
CODE is the code of the operation required, it can be any of SET, PLUS,
IOR, AND, XOR, MINUS;
Index: config/arm/arm-protos.h
===
--- config/arm/arm-protos.h (revision 187751)
+++ config/arm/arm-protos.h (working copy)
@@ -49,6 +49,7 @@
extern bool arm_modes_tieable_p (enum machine_mode, enum machine_mode);
extern int const_ok_for_arm (HOST_WIDE_INT);
extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
+extern int const_ok_for_dimode_op (HOST_WIDE_INT, enum rtx_code);
extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx,
HOST_WIDE_INT, rtx, rtx, int);
extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, rtx *, rtx *);
Index: config/arm/neon.md
===
--- config/arm/neon.md (revision 187751)
+++ config/arm/neon.md (working copy)
@@ -588,9 +588,9 @@
)
(define_insn adddi3_neon
- [(set (match_operand:DI 0 s_register_operand =w,?r,?r,?w)
- (plus:DI (match_operand:DI 1 s_register_operand %w,0,0,w)
- (match_operand:DI 2 s_register_operand w,r,0,w)))
+ [(set (match_operand:DI 0 s_register_operand =w,?r,?r,?w,?r,?r,?r)
+ (plus:DI (match_operand:DI 1 s_register_operand %w,0,0,w,r,0,r)
+ (match_operand:DI 2 arm_adddi_operand
w,r,0,w,r,Dd,Dd)))
(clobber (reg:CC CC_REGNUM))]
TARGET_NEON
{
@@ -600,13 +600,16 @@
case 3: return vadd.i64\t%P0, %P1, %P2;
case 1: return #;
case 2: return #;
+ case 4: return #;
+ case 5: return #;
+ case 6: return #;
default: gcc_unreachable ();
}
}
- [(set_attr neon_type neon_int_1,*,*,neon_int_1)
- (set_attr conds *,clob,clob,*)
- (set_attr length *,8,8,*)
- (set_attr arch nota8,*,*,onlya8)]
+ [(set_attr neon_type neon_int_1,*,*,neon_int_1,*,*,*)
+ (set_attr conds *,clob,clob,*,clob,clob,clob)
+ (set_attr length *,8,8,*,8,8,8)
+ (set_attr arch nota8,*,*,onlya8,*,*,*)]
)
(define_insn *submode3_neon
Index:
[trunk, 4.7, PR 38474] Avoid unnecessary vdef walks in compute_known_type_jump_func
Hi, PR 38474 testcase revealed what we can do a lot of entirely unnecessary vdef walking only to throw away the result later because of a much cheaper check. This patch fixes that. The patch applies to both trunk and the 4.7 branch, I have bootstrapped and tested it on both on an x86_64-linux without any problems. Because of Richi's comment #63 in bugzilla, I assume it is approved for both trunk and the branch too and will commit it on Monday, unless someone objects. Thanks, Martin 2012-06-27 Martin Jambor mjam...@suse.cz PR middle-end/38474 * ipa-prop.c (compute_known_type_jump_func): Put BINFO check before a dynamic type change check. Index: src/gcc/ipa-prop.c === --- src.orig/gcc/ipa-prop.c +++ src/gcc/ipa-prop.c @@ -912,8 +912,8 @@ compute_known_type_jump_func (tree op, s || is_global_var (base)) return; - if (detect_type_change (op, base, call, jfunc, offset) - || !TYPE_BINFO (TREE_TYPE (base))) + if (!TYPE_BINFO (TREE_TYPE (base)) + || detect_type_change (op, base, call, jfunc, offset)) return; ipa_set_jf_known_type (jfunc, offset, TREE_TYPE (base), TREE_TYPE (op));
[4.6, PR 38474] Avoid unnecessary vdef walks in compute_known_type_jump_func
Hi,
PR 38474 testcase revealed what we can do a lot of entirely
unnecessary vdef walking only to throw away the result later because
of a much cheaper check. I have posted a patch for trunk and 4.7 just
a moment ago. this is a version for 4.6, doing essentially the same
thing.
I am about to bootstrap and test it on x86_64-linux and if no-one
objects, I will commit it to the branch on Monday because it is also
rather obvious and quite like the approved patch for newer code.
Thanks,
Martin
2012-06-29 Martin Jambor mjam...@suse.cz
pr middle-end/38474
* ipa-prop.c (compute_known_type_jump_func): Check for a BINFO before
checking for a dynamic type change.
Index: gcc/ipa-prop.c
===
--- gcc/ipa-prop.c (revision 189050)
+++ gcc/ipa-prop.c (working copy)
@@ -704,12 +704,11 @@ compute_known_type_jump_func (tree op, s
|| is_global_var (base))
return;
- if (detect_type_change (op, base, call, jfunc, offset))
-return;
-
binfo = TYPE_BINFO (TREE_TYPE (base));
- if (!binfo)
+ if (!binfo
+ || detect_type_change (op, base, call, jfunc, offset))
return;
+
binfo = get_binfo_at_offset (binfo, offset, TREE_TYPE (op));
if (binfo)
{
[PATCH] Testcase for PR47061
Tested on x86_64-unknown-linux-gnu, applied.
Richard.
2012-06-29 Richard Guenther rguent...@suse.de
PR tree-optimization/47061
* gcc.dg/tree-ssa/vrp71.c: New testcase.
Index: gcc/testsuite/gcc.dg/tree-ssa/vrp71.c
===
--- gcc/testsuite/gcc.dg/tree-ssa/vrp71.c (revision 0)
+++ gcc/testsuite/gcc.dg/tree-ssa/vrp71.c (working copy)
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options -O2 -fdump-tree-vrp1 } */
+
+int foo(int *p)
+{
+ int x = -10;
+ if (p[0]) x++;
+ if (p[1]) x++;
+ if (p[2]) x++;
+ if (p[3]) x++;
+ x = 2;
+ return (x 0);
+}
+
+int bar(char c)
+{
+ int i = c 1;
+ return i 1000;
+}
+
+/* { dg-final { scan-tree-dump-times return 0; 2 vrp1 } } */
+/* { dg-final { cleanup-tree-dump vrp1 } } */
Re: Ping: Reorganized documentation for warnings -- attempt 2
Try CC:ing Gerald as the most likely maintainer to review this. -- Joseph S. Myers jos...@codesourcery.com
Re: [RFC, ARM] later split of symbol_refs
+;; Split symbol_refs at the later stage (after cprop), instead of generating +;; movt/movw pair directly at expand. Otherwise corresponding high_sum +;; and lo_sum would be merged back into memory load at cprop. However, I would rewrite part of your comment as +;; movt/movw is preferable, because it usually executes faster than a load However if the default is to prefer to use movw/movt rather than the constant pool use that. instead of a load from the constant pool. regards, Ramana -- Best regards, Dmitry
Re: [RFC, ARM] later split of symbol_refs
On 29 June 2012 14:48, Dmitry Melnik d...@ispras.ru wrote: On 06/27/2012 07:55 PM, Ramana Radhakrishnan wrote: I must admit that I had been suggesting to Zhenqiang about turning this off by tightening the movsi_insn predicates rather than adding a split, but given that it appears to produce enough benefit in this case I don't have any reasons to object ... However it's interesting that this doesn't seem to help vpr We retested vpr, but it just seems to be unstable: Unfortunate but ok. Ramana
[patch] Remove CASE_USE_BIT_TESTS target macro
Hello,
This patch removes the CASE_USE_BIT_TESTS target macro. The default
value of the macro is defined in stmt.c, where the only user of the
macro is also. No target re-defines the macro.
(I wonder if the test is necessary at all. AFAICT all targets support
shifts in word_mode. The macro was originally written to test for
ashlsi3, which is _not_ supported on all targets -- but word_mode
shifts are. Oh well, another day perhaps...)
Bootstrapped and tested on powerpc64-unknown-linux-gnu. OK for trunk?
Ciao!
Steven
* stmt.c (CASE_USE_BIT_TESTS): Fold away into its only user ...
(expand_switch_using_bit_tests_p): ...here.
* doc/tm.texi.in (CASE_USE_BIT_TESTS): Remove documentation.
* doc/tm.texi (CASE_USE_BIT_TESTS): Regenerate.
Index: stmt.c
===
--- stmt.c (revision 189073)
+++ stmt.c (working copy)
@@ -1722,13 +1722,6 @@ add_case_node (struct case_node *head, tree type,
/* Maximum number of case bit tests. */
#define MAX_CASE_BIT_TESTS 3
-/* By default, enable case bit tests on targets with ashlsi3. */
-#ifndef CASE_USE_BIT_TESTS
-#define CASE_USE_BIT_TESTS (optab_handler (ashl_optab, word_mode) \
-!= CODE_FOR_nothing)
-#endif
-
-
/* A case_bit_test represents a set of case nodes that may be
selected from using a bit-wise comparison. HI and LO hold
the integer to be tested against, LABEL contains the label
@@ -1888,8 +1881,10 @@ bool
expand_switch_using_bit_tests_p (tree index_expr, tree range,
unsigned int uniq, unsigned int count)
{
- return (CASE_USE_BIT_TESTS
- ! TREE_CONSTANT (index_expr)
+ if (optab_handler (ashl_optab, word_mode) == CODE_FOR_nothing)
+return false;
+
+ return (! TREE_CONSTANT (index_expr)
compare_tree_int (range, GET_MODE_BITSIZE (word_mode)) 0
compare_tree_int (range, 0) 0
lshift_cheap_p ()
Index: doc/tm.texi
===
--- doc/tm.texi (revision 189074)
+++ doc/tm.texi (working copy)
@@ -10306,16 +10306,6 @@ The default is four for machines with a @code{case
five otherwise. This is best for most machines.
@end deftypefn
-@defmac CASE_USE_BIT_TESTS
-Define this macro to be a C expression to indicate whether C switch
-statements may be implemented by a sequence of bit tests. This is
-advantageous on processors that can efficiently implement left shift
-of 1 by the number of bits held in a register, but inappropriate on
-targets that would require a loop. By default, this macro returns
-@code{true} if the target defines an @code{ashlsi3} pattern, and
-@code{false} otherwise.
-@end defmac
-
@defmac WORD_REGISTER_OPERATIONS
Define this macro if operations between registers with integral mode
smaller than a word are always performed on the entire register.
Index: doc/tm.texi.in
===
--- doc/tm.texi.in (revision 189074)
+++ doc/tm.texi.in (working copy)
@@ -10180,16 +10180,6 @@ The default is four for machines with a @code{case
five otherwise. This is best for most machines.
@end deftypefn
-@defmac CASE_USE_BIT_TESTS
-Define this macro to be a C expression to indicate whether C switch
-statements may be implemented by a sequence of bit tests. This is
-advantageous on processors that can efficiently implement left shift
-of 1 by the number of bits held in a register, but inappropriate on
-targets that would require a loop. By default, this macro returns
-@code{true} if the target defines an @code{ashlsi3} pattern, and
-@code{false} otherwise.
-@end defmac
-
@defmac WORD_REGISTER_OPERATIONS
Define this macro if operations between registers with integral mode
smaller than a word are always performed on the entire register.
Re: [patch] Remove CASE_USE_BIT_TESTS target macro
On Fri, Jun 29, 2012 at 4:35 PM, Steven Bosscher stevenb@gmail.com wrote:
Hello,
This patch removes the CASE_USE_BIT_TESTS target macro. The default
value of the macro is defined in stmt.c, where the only user of the
macro is also. No target re-defines the macro.
(I wonder if the test is necessary at all. AFAICT all targets support
shifts in word_mode. The macro was originally written to test for
ashlsi3, which is _not_ supported on all targets -- but word_mode
shifts are. Oh well, another day perhaps...)
Bootstrapped and tested on powerpc64-unknown-linux-gnu. OK for trunk?
Ok. (poison CASE_USE_BIT_TESTS?)
Thanks,
Richard.
Ciao!
Steven
* stmt.c (CASE_USE_BIT_TESTS): Fold away into its only user ...
(expand_switch_using_bit_tests_p): ...here.
* doc/tm.texi.in (CASE_USE_BIT_TESTS): Remove documentation.
* doc/tm.texi (CASE_USE_BIT_TESTS): Regenerate.
Index: stmt.c
===
--- stmt.c (revision 189073)
+++ stmt.c (working copy)
@@ -1722,13 +1722,6 @@ add_case_node (struct case_node *head, tree type,
/* Maximum number of case bit tests. */
#define MAX_CASE_BIT_TESTS 3
-/* By default, enable case bit tests on targets with ashlsi3. */
-#ifndef CASE_USE_BIT_TESTS
-#define CASE_USE_BIT_TESTS (optab_handler (ashl_optab, word_mode) \
- != CODE_FOR_nothing)
-#endif
-
-
/* A case_bit_test represents a set of case nodes that may be
selected from using a bit-wise comparison. HI and LO hold
the integer to be tested against, LABEL contains the label
@@ -1888,8 +1881,10 @@ bool
expand_switch_using_bit_tests_p (tree index_expr, tree range,
unsigned int uniq, unsigned int count)
{
- return (CASE_USE_BIT_TESTS
- ! TREE_CONSTANT (index_expr)
+ if (optab_handler (ashl_optab, word_mode) == CODE_FOR_nothing)
+ return false;
+
+ return (! TREE_CONSTANT (index_expr)
compare_tree_int (range, GET_MODE_BITSIZE (word_mode)) 0
compare_tree_int (range, 0) 0
lshift_cheap_p ()
Index: doc/tm.texi
===
--- doc/tm.texi (revision 189074)
+++ doc/tm.texi (working copy)
@@ -10306,16 +10306,6 @@ The default is four for machines with a @code{case
five otherwise. This is best for most machines.
@end deftypefn
-@defmac CASE_USE_BIT_TESTS
-Define this macro to be a C expression to indicate whether C switch
-statements may be implemented by a sequence of bit tests. This is
-advantageous on processors that can efficiently implement left shift
-of 1 by the number of bits held in a register, but inappropriate on
-targets that would require a loop. By default, this macro returns
-@code{true} if the target defines an @code{ashlsi3} pattern, and
-@code{false} otherwise.
-@end defmac
-
@defmac WORD_REGISTER_OPERATIONS
Define this macro if operations between registers with integral mode
smaller than a word are always performed on the entire register.
Index: doc/tm.texi.in
===
--- doc/tm.texi.in (revision 189074)
+++ doc/tm.texi.in (working copy)
@@ -10180,16 +10180,6 @@ The default is four for machines with a @code{case
five otherwise. This is best for most machines.
@end deftypefn
-@defmac CASE_USE_BIT_TESTS
-Define this macro to be a C expression to indicate whether C switch
-statements may be implemented by a sequence of bit tests. This is
-advantageous on processors that can efficiently implement left shift
-of 1 by the number of bits held in a register, but inappropriate on
-targets that would require a loop. By default, this macro returns
-@code{true} if the target defines an @code{ashlsi3} pattern, and
-@code{false} otherwise.
-@end defmac
-
@defmac WORD_REGISTER_OPERATIONS
Define this macro if operations between registers with integral mode
smaller than a word are always performed on the entire register.
Re: [patch] Remove CASE_USE_BIT_TESTS target macro
On Fri, Jun 29, 2012 at 4:42 PM, Richard Guenther richard.guent...@gmail.com wrote: On Fri, Jun 29, 2012 at 4:35 PM, Steven Bosscher stevenb@gmail.com wrote: Hello, This patch removes the CASE_USE_BIT_TESTS target macro. ... Ok. (poison CASE_USE_BIT_TESTS?) Right, I've done that in the patch I commited. Ciao! Steven
Re: [testsuite] gcc.dg/vect/vect-50.c: combine two scans
On 06/28/2012 08:02 PM, Mike Stump wrote:
On Jun 28, 2012, at 10:26 AM, Janis Johnson wrote:
No, there is no way to combine target and xfail,
Ah... Grrr I hate non-composability. Given that, I think the original
patch is fine, subject of course to the wants and wishes of vect people.
I should have said that *currently* there is no way to combine them.
We override dg-process-target and can come up with a way to provide
both target and xfail in the target-selector. Something like:
target { selector } xfail { selector }
where target is the first argument, xfail is the third.
Selectors can be lists of target triplets, but those can be within
braces making them a single argument. What do you think?
Janis
Use builtin_widen_mult_even/odd in expand_vector_divmod
We use it everywhere else, but it got forgotten here. Saves two shuffles on
Altivec.
Although with all of this duplication it makes me wonder if we shouldn't just
give up
on the idea of auto-generating MULT_HIGHPART from other operations
(particularly given
the extra type frobbing involved). In some sense it'd be easier to just add a
couple
of lines to the backends to implement the operation and be done with it.
Thoughts?
That said, tested on ppc64-linux. Committed.
r~
* tree-vect-generic.c: Include target.h.
(expand_vector_divmod): Use builtin_mul_widen_even/odd if supported.
* Makefile.in (tree-vect-generic.o): Update.
diff --git a/gcc/Makefile.in b/gcc/Makefile.in
index afea4f3..9955fd7 100644
--- a/gcc/Makefile.in
+++ b/gcc/Makefile.in
@@ -3036,7 +3036,7 @@ tree-vect-generic.o : tree-vect-generic.c $(CONFIG_H)
$(SYSTEM_H) $(TREE_H) \
$(TM_H) $(TREE_FLOW_H) $(GIMPLE_H) tree-iterator.h $(TREE_PASS_H) \
$(FLAGS_H) $(OPTABS_H) $(MACHMODE_H) $(EXPR_H) \
langhooks.h $(FLAGS_H) $(DIAGNOSTIC_H) gt-tree-vect-generic.h $(GGC_H) \
-coretypes.h insn-codes.h $(DIAGNOSTIC_H)
+coretypes.h insn-codes.h $(DIAGNOSTIC_H) $(TARGET_H)
df-core.o : df-core.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) \
insn-config.h $(RECOG_H) $(FUNCTION_H) $(REGS_H) alloc-pool.h \
hard-reg-set.h $(BASIC_BLOCK_H) $(DF_H) $(BITMAP_H) sbitmap.h $(TIMEVAR_H) \
diff --git a/gcc/tree-vect-generic.c b/gcc/tree-vect-generic.c
index c83db5e..89d8bae 100644
--- a/gcc/tree-vect-generic.c
+++ b/gcc/tree-vect-generic.c
@@ -31,6 +31,7 @@ along with GCC; see the file COPYING3. If not see
#include flags.h
#include ggc.h
#include diagnostic.h
+#include target.h
/* Need to include rtl.h, expr.h, etc. for optabs. */
#include expr.h
@@ -456,7 +457,7 @@ expand_vector_divmod (gimple_stmt_iterator *gsi, tree type,
tree op0,
optab op;
tree *vec;
unsigned char *sel = NULL;
- tree cur_op, mhi, mlo, mulcst, perm_mask, wider_type, tem;
+ tree cur_op, mhi, mlo, mulcst, perm_mask, wider_type, tem, decl_e, decl_o;
if (prec HOST_BITS_PER_WIDE_INT)
return NULL_TREE;
@@ -745,32 +746,52 @@ expand_vector_divmod (gimple_stmt_iterator *gsi, tree
type, tree op0,
return NULL_TREE;
op = optab_for_tree_code (MULT_HIGHPART_EXPR, type, optab_default);
- if (op != NULL
- optab_handler (op, TYPE_MODE (type)) != CODE_FOR_nothing)
-wider_type = NULL_TREE;
+ if (op != NULL optab_handler (op, TYPE_MODE (type)) != CODE_FOR_nothing)
+wider_type = decl_e = decl_o = NULL_TREE;
else
{
- op = optab_for_tree_code (VEC_WIDEN_MULT_LO_EXPR, type, optab_default);
- if (op == NULL
- || optab_handler (op, TYPE_MODE (type)) == CODE_FOR_nothing)
- return NULL_TREE;
- op = optab_for_tree_code (VEC_WIDEN_MULT_HI_EXPR, type, optab_default);
- if (op == NULL
- || optab_handler (op, TYPE_MODE (type)) == CODE_FOR_nothing)
- return NULL_TREE;
- sel = XALLOCAVEC (unsigned char, nunits);
- for (i = 0; i nunits; i++)
- sel[i] = 2 * i + (BYTES_BIG_ENDIAN ? 0 : 1);
- if (!can_vec_perm_p (TYPE_MODE (type), false, sel))
- return NULL_TREE;
- wider_type
- = build_vector_type (build_nonstandard_integer_type (prec * 2,
-unsignedp),
-nunits / 2);
+ wider_type = build_nonstandard_integer_type (prec * 2, unsignedp),
+ wider_type = build_vector_type (wider_type, nunits / 2);
if (GET_MODE_CLASS (TYPE_MODE (wider_type)) != MODE_VECTOR_INT
|| GET_MODE_BITSIZE (TYPE_MODE (wider_type))
!= GET_MODE_BITSIZE (TYPE_MODE (type)))
return NULL_TREE;
+
+ sel = XALLOCAVEC (unsigned char, nunits);
+
+ if (targetm.vectorize.builtin_mul_widen_even
+ targetm.vectorize.builtin_mul_widen_odd
+ (decl_e = targetm.vectorize.builtin_mul_widen_even (type))
+ (decl_o = targetm.vectorize.builtin_mul_widen_odd (type))
+ (TYPE_MODE (TREE_TYPE (TREE_TYPE (decl_e)))
+ == TYPE_MODE (wider_type)))
+ {
+ for (i = 0; i nunits; i++)
+ sel[i] = !BYTES_BIG_ENDIAN + (i ~1) + ((i 1) ? nunits : 0);
+ if (!can_vec_perm_p (TYPE_MODE (wider_type), false, sel))
+ decl_e = decl_o = NULL_TREE;
+ }
+ else
+ decl_e = decl_o = NULL_TREE;
+
+ if (decl_e == NULL_TREE)
+ {
+ op = optab_for_tree_code (VEC_WIDEN_MULT_LO_EXPR,
+ type, optab_default);
+ if (op == NULL
+ || optab_handler (op, TYPE_MODE (type)) == CODE_FOR_nothing)
+ return NULL_TREE;
+ op = optab_for_tree_code (VEC_WIDEN_MULT_HI_EXPR,
+ type, optab_default);
+ if (op == NULL
+ || optab_handler (op, TYPE_MODE (type)) == CODE_FOR_nothing)
+ return NULL_TREE;
+
+ for (i =
[lra] patch to fix ia64 bootstrap
The following patch fixes IA64 bootstrap after the last merge.
The patch was sucessfully bootstrapped on ia64 and x86/x86-64.
Committed as rev. 189079.
2012-06-29 Vladimir Makarov vmaka...@redhat.com
* lra-constraints.c (get_op_class): Don't process SUBREG.
(check_and_process_move): Simplify the code.
Index: lra-constraints.c
===
--- lra-constraints.c (revision 189051)
+++ lra-constraints.c (working copy)
@@ -1006,15 +1006,14 @@ get_final_hard_regno (int hard_regno, in
/* Return register class of OP. That is a class of the hard register
itself (if OP is a hard register), or class of assigned hard
- register to the pseudo (if OP is pseudo or its subregister), or
- class of unassigned pseudo (if OP is reload pseudo or its
- subregister). Return NO_REGS otherwise. */
+ register to the pseudo (if OP is pseudo), or class of unassigned
+ pseudo (if OP is reload pseudo). Return NO_REGS otherwise. */
static enum reg_class
get_op_class (rtx op)
{
int regno, hard_regno, offset;
- if (! REG_P (op) (GET_CODE (op) != SUBREG || ! REG_P (SUBREG_REG (op
+ if (! REG_P (op))
return NO_REGS;
lra_get_hard_regno_and_offset (op, hard_regno, offset);
if (hard_regno = 0)
@@ -1022,8 +1021,6 @@ get_op_class (rtx op)
hard_regno = get_final_hard_regno (hard_regno, offset);
return REGNO_REG_CLASS (hard_regno);
}
- if (GET_CODE (op) == SUBREG)
-op = SUBREG_REG (op);
/* Reload pseudo will get a hard register in any case. */
if ((regno = REGNO (op)) = new_regno_start)
return lra_get_allocno_class (regno);
@@ -1088,14 +1085,10 @@ check_and_process_move (bool *change_p,
sreg = src = SET_SRC (set);
/* Quick check on the right move insn which does not need
reloads. */
- dclass = get_op_class (dest);
- if (dclass != NO_REGS)
-{
- sclass = get_op_class (src);
- if (sclass != NO_REGS
- targetm.register_move_cost (GET_MODE (src), dclass, sclass) == 2)
- return true;
-}
+ if ((dclass = get_op_class (dest)) != NO_REGS
+ (sclass = get_op_class (src)) != NO_REGS
+ targetm.register_move_cost (GET_MODE (src), dclass, sclass) == 2)
+return true;
if (GET_CODE (dest) == SUBREG)
dreg = SUBREG_REG (dest);
if (GET_CODE (src) == SUBREG)
Re: Fwd: [Bug debug/53754] [4.8 Regression][lto] ICE in lhd_decl_printable_name, at langhooks.c:222 (with -g)
(What's the right way to send a patch to fix a PR? I'm not even sure whether you were cc'ed on my response.) The right way to send a patch to fix a PR is to send it to gcc-patches ;) Well, yeah, but in this case I was just proposing a patch for discussion, and using the bugzilla mechanism didn't seem to be working. I guess it's gcc-patches even for discussion. You can't delay producing pubnames this way with LTO. Please fix. The obvious problem is that we're calling langhooks.dwarf_name (in gen_namespace_die) for an anonymous namespace, even with the default -gno-pubnames. I can fix that by adding a check for want_pubnames just before the call to add_pubname_string, as in the patch below. But this is still going That's sensible anyways - you avoid useless work. So the patch is ok. OK, I'll submit this patch, but leave the PR open and follow up with something to fix the underlying problem as you suggest. -cary
Re: [testsuite] gcc.dg/vect/vect-50.c: combine two scans
On Jun 29, 2012, at 8:45 AM, Janis Johnson wrote:
Something like:
target { selector } xfail { selector }
where target is the first argument, xfail is the third.
Forcing (requiring) an ordering would be bad.
Selectors can be lists of target triplets, but those can be within
braces making them a single argument. What do you think?
I love composability. The exact syntax I think falls out from the
implementation... I'd leave that to the implementor.
Re: PATCH: PR target/53539: Different __WCHAR_TYPE__/wchar_t for gcc -m32 on Linux/i386 and Linux/x86-64
On Thu, May 31, 2012 at 7:10 AM, H.J. Lu hjl.to...@gmail.com wrote: On Thu, May 31, 2012 at 6:50 AM, Jakub Jelinek ja...@redhat.com wrote: On Thu, May 31, 2012 at 06:35:19AM -0700, H.J. Lu wrote: This patch makes __WCHAR_TYPE__/wchar_t the same for gcc -m32 on Linux/i386 and Linux/x86-64. OK for trunk? That looks wrong. For Linux/i386, the 32-bit only compiler should be the standard, rather than x86_64 -m32 if they differ. So, IMHO you should keep gnu-user.h as is, and just use #define WCHAR_TYPE (TARGET_64BIT ? int : long int) in gcc/config/i386/x86-64.h. You are right on Linux/i386. But we should change config/i386/gnu-user64.h, not x86-64.h since most of other i386 OSes use int for wchar. Also we should check TARGET_LP64 to keep x32 as close to i386 as possible. OK for trunk? Thanks. -- H.J. 2012-05-31 H.J. Lu hongjiu...@intel.com PR target/53539 * config/i386/gnu-user64.h (WCHAR_TYPE): Use int only for TARGET_LP64. diff --git a/gcc/config/i386/gnu-user64.h b/gcc/config/i386/gnu-user64.h index 0e66d26..2941332 100644 --- a/gcc/config/i386/gnu-user64.h +++ b/gcc/config/i386/gnu-user64.h @@ -91,3 +91,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If n ot, see #define TARGET_THREAD_SPLIT_STACK_OFFSET \ (TARGET_64BIT ? (TARGET_X32 ? 0x40 : 0x70) : 0x30) #endif + +#undef WCHAR_TYPE +#define WCHAR_TYPE (TARGET_LP64 ? int : long int) Hi Richard, Is this patch OK for trunk? Thanks. -- H.J.
Re: [wwwdocs] Update coding conventions for C++
Resend, as I replied to a message that didn't have the usual suspects
on the cc line.
On 6/27/12, Lawrence Crowl cr...@google.com wrote:
..., does anyone object to removing the permission to use C++
streams?
Having heard no objection, I removed the permission.
The following patch is the current state of the changes. Since the
discussion appears to have died down, can I commit this patch?
BTW, as before, I have removed the html tags from this patch,
as they cause the mail server to reject the patch.
Index: htdocs/codingconventions.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/codingconventions.html,v
retrieving revision 1.66
diff -u -u -r1.66 codingconventions.html
--- htdocs/codingconventions.html 19 Feb 2012 00:45:34 - 1.66
+++ htdocs/codingconventions.html 28 Jun 2012 22:03:38 -
@@ -15,8 +19,73 @@
code to follow these conventions, it is best to send changes to follow
the conventions separately from any other changes to the code./p
+ul
+lia href=#DocumentationDocumentation/a/li
+lia href=#ChangeLogsChangeLogs/a/li
+lia href=#PortabilityPortability/a/li
+lia href=#MakefilesMakefiles/a/li
+lia href=#TestsuiteTestsuite Conventions/a/li
+lia href=#DiagnosticsDiagnostics Conventions/a/li
+lia href=#SpellingSpelling, terminology and markup/a/li
+lia href=#CandCxxC and C++ Language Conventions/a
+ul
+lia href=#C_OptionsCompiler Options/a/li
+lia href=#C_LanguageLanguage Use/a
+ul
+lia href=#AssertionsAssertions/a/li
+lia href=#CharacterCharacter Testing/a/li
+lia href=#ErrorError Node Testing/a/li
+lia href=#GeneratedParameters Affecting Generated
Code/a/li
+lia href=#C_InliningInlining Functions/a/li
+/ul
+/li
+lia href=#C_FormattingFormatting Conventions/a
+ul
+lia href=#LineLine Length/a/li
+lia href=#C_NamesNames/a/li
+lia href=#ExpressionsExpressions/a/li
+/ul
+/li
+/ul
+/li
+lia href=#Cxx_ConventionsC++ Language Conventions/a
+ul
+lia href=#Cxx_LanguageLanguage Use/a
+ul
+lia href=#VariableVariable Definitions/a/li
+lia href=#Struct_UseStruct Definitions/a/li
+lia href=#Class_UseClass Definitions/a/li
+lia href=#ConstructorsConstructors and Destructors/a/li
+lia href=#ConversionsConversions/a/li
+lia href=#Over_FuncOverloading Functions/a/li
+lia href=#Over_OperOverloading Operators/a/li
+lia href=#DefaultDefault Arguments/a/li
+lia href=#Cxx_InliningInlining Functions/a/li
+lia href=#Template_UseTemplates/a/li
+lia href=#Namespace_UseNamespaces/a/li
+lia href=#RTTIRTTI and codedynamic_cast/code/a/li
+lia href=#CastsOther Casts/a/li
+lia href=#ExceptionsExceptions/a/li
+lia href=#Standard_LibraryThe Standard Library/a/li
+/ul
+/li
+lia href=#Cxx_FormattingFormatting Conventions/a
+ul
+lia href=#Cxx_NamesNames/a/li
+lia href=#Struct_FormStruct Definitions/a/li
+lia href=#Class_FormClass Definitions/a/li
+lia href=#Member_FormClass Member Definitions/a/li
+lia href=#Template_FormTemplates/a/li
+lia href=#ExternCExtern C/a/li
+lia href=#Namespace_FormNamespaces/a/li
+/ul
+/li
+/ul
+/li
+/ul
-h2Documentation/h2
+
+h2a name=DocumentationDocumentation/a/h2
pDocumentation, both of user interfaces and of internals, must be
maintained and kept up to date. In particular:/p
@@ -43,7 +112,7 @@
/ul
-h2ChangeLogs/h2
+h2a name=ChangeLogsChangeLogs/a/h2
pGCC requires ChangeLog entries for documentation changes; for the web
pages (apart from codejava//code and codelibstdc++//code) the CVS
@@ -71,20 +140,40 @@
codejava/58/code is the actual number of the PR) at the top
of the ChangeLog entry./p
-h2Portability/h2
+h2a name=PortabilityPortability/a/h2
pThere are strict requirements for portability of code in GCC to
-older systems whose compilers do not implement all of the ISO C standard.
-GCC requires at least an ANSI C89 or ISO C90 host compiler, and code
-should avoid pre-standard style function definitions, unnecessary
-function prototypes and use of the now deprecated @code{PARAMS} macro.
+older systems whose compilers do not implement all of the
+latest ISO C and C++ standards.
+/p
+
+p
+The directories
+codegcc/code, codelibcpp/code and codefixincludes/code
+may use C++03.
+They may also use the codelong long/code type
+if the host C++ compiler supports it.
+These directories should use reasonably portable parts of C++03,
+so that it is possible to build GCC with C++ compilers other than GCC
itself.
+If testing reveals that
+reasonably recent versions of non-GCC C++ compilers cannot compile GCC,
+then GCC code should be adjusted accordingly.
+(Avoiding unusual language constructs helps immensely.)
+Furthermore,
+these directories emshould/em also be
Re: Use builtin_widen_mult_even/odd in expand_vector_divmod
On Fri, Jun 29, 2012 at 9:50 AM, Richard Henderson r...@redhat.com wrote: We use it everywhere else, but it got forgotten here. Saves two shuffles on Altivec. Although with all of this duplication it makes me wonder if we shouldn't just give up on the idea of auto-generating MULT_HIGHPART from other operations (particularly given the extra type frobbing involved). In some sense it'd be easier to just add a couple of lines to the backends to implement the operation and be done with it. Thoughts? That said, tested on ppc64-linux. Committed. It caused: FAIL: gcc.c-torture/execute/pr53645.c execution, -O1 FAIL: gcc.c-torture/execute/pr53645.c execution, -O2 FAIL: gcc.c-torture/execute/pr53645.c execution, -O2 -flto -fno-use-linker-plugin -flto-partition=none FAIL: gcc.c-torture/execute/pr53645.c execution, -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects FAIL: gcc.c-torture/execute/pr53645.c execution, -O3 -fomit-frame-pointer FAIL: gcc.c-torture/execute/pr53645.c execution, -O3 -fomit-frame-pointer -funroll-all-loops -finline-functions FAIL: gcc.c-torture/execute/pr53645.c execution, -O3 -fomit-frame-pointer -funroll-loops FAIL: gcc.c-torture/execute/pr53645.c execution, -O3 -g FAIL: gcc.c-torture/execute/pr53645.c execution, -Os on Linux/ia32 configured with --with-arch=corei7 --with-cpu=corei7 --with-fpmath=sse -- H.J.
[PATCH] Fix up mksysinfo.sh
Hi!
The recent mksysinfo.sh change for glibc 2.16 bits/resource.h unfortunately
doesn't work, because the sed invocation two lines earlier removes the {}s
this sed command is looking for.
The following makes gcc 4.7 as well as trunk build in Fedora rawhide.
--- libgo/mksysinfo.sh 2012-06-29 14:23:30.684708901 +0200
+++ libgo/mksysinfo.sh 2012-06-29 14:23:20.782761973 +0200
@@ -522,10 +522,10 @@ grep '^const _DT_' gen-sysinfo.go |
# The rusage struct.
rusage=`grep '^type _rusage struct' gen-sysinfo.go`
if test $rusage != ; then
- rusage=`echo $rusage | sed -e 's/type _rusage struct //' -e 's/[{}]//g'`
- rusage=`echo $rusage | sed -e 's/^ *//'`
# Remove anonymous unions from GNU/Linux bits/resource.h.
rusage=`echo $rusage | sed -e 's/Godump_[0-9]* struct {\([^}]*\)};/\1/g'`
+ rusage=`echo $rusage | sed -e 's/type _rusage struct //' -e 's/[{}]//g'`
+ rusage=`echo $rusage | sed -e 's/^ *//'`
nrusage=
while test -n $rusage; do
field=`echo $rusage | sed -e 's/^\([^;]*\);.*$/\1/'`
Jakub
Re: PATCH: PR target/53539: Different __WCHAR_TYPE__/wchar_t for gcc -m32 on Linux/i386 and Linux/x86-64
On 06/29/2012 11:10 AM, H.J. Lu wrote: 2012-05-31 H.J. Lu hongjiu...@intel.com PR target/53539 * config/i386/gnu-user64.h (WCHAR_TYPE): Use int only for TARGET_LP64. diff --git a/gcc/config/i386/gnu-user64.h b/gcc/config/i386/gnu-user64.h index 0e66d26..2941332 100644 --- a/gcc/config/i386/gnu-user64.h +++ b/gcc/config/i386/gnu-user64.h @@ -91,3 +91,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If n ot, see #define TARGET_THREAD_SPLIT_STACK_OFFSET \ (TARGET_64BIT ? (TARGET_X32 ? 0x40 : 0x70) : 0x30) #endif + +#undef WCHAR_TYPE +#define WCHAR_TYPE (TARGET_LP64 ? int : long int) Hi Richard, Is this patch OK for trunk? Thanks. Yes, this is fine. r~
[Obvious] Add previously approved comment
Enclosed is a patch that fixes indention and adds an already-approved comment that I missed when porting the previous patch. I have checked it in under the obvious rule. Sterling obvious.patch Description: Binary data
Fix oversight during try-finally lowering
It pertains to the source location assigned to the finally switch: the comment in lower_try_finally_switch reads: /* The location of the finally is either the last stmt in the finally block or the location of the TRY_FINALLY itself. */ but the code reads: finally_loc = gimple_seq_last_stmt (tf-top_p_seq) != NULL ? gimple_location (gimple_seq_last_stmt (tf-top_p_seq)) : tf_loc; so it uses the location of last stmt of the eval block. Needless to say that this seriously screws up the coverage of the construct: the last stmt of the eval block is always reported as covered! Fixed thusly, tested on x86_64-suse-linux, applied on the mainline as obvious. This isn't a recent regression, but I took the liberty to put it on the 4.7 branch as well. 2012-06-29 Eric Botcazou ebotca...@adacore.com * tree-eh.c (lower_try_finally_switch): Really put the location of the last statement of the finally block onto the switch. -- Eric Botcazou Index: tree-eh.c === --- tree-eh.c (revision 189034) +++ tree-eh.c (working copy) @@ -1320,9 +1320,8 @@ lower_try_finally_switch (struct leh_sta /* The location of the finally is either the last stmt in the finally block or the location of the TRY_FINALLY itself. */ - finally_loc = gimple_seq_last_stmt (tf-top_p_seq) != NULL ? -gimple_location (gimple_seq_last_stmt (tf-top_p_seq)) -: tf_loc; + x = gimple_seq_last_stmt (finally); + finally_loc = x ? gimple_location (x) : tf_loc; /* Lower the finally block itself. */ lower_eh_constructs_1 (state, finally);
Re: Remove obsolete Solaris 8 support
Hi!
On Mon, 12 Mar 2012 18:44:24 +0100, Rainer Orth r...@cebitec.uni-bielefeld.de
wrote:
2012-03-11 Rainer Orth r...@cebitec.uni-bielefeld.de
gcc:
* config.gcc (enable_obsolete): Remove *-*-solaris2.8*.
(*-*-solaris2.[0-8], *-*-solaris2.[0-8].*): Mark unsupported.
(i[34567]86-*-solaris2*, x86_64-*-solaris2.1[0-9]*): Remove
Solaris 8 support.
* configure.ac (gcc_cv_ld_hidden): Remove *-*-solaris2.8*.
(ld_tls_support): Remove Solaris 8 references.
(lwp_dir, lwp_spec): Remove support for alternate thread library.
* acinclude.m4 (gcc_cv_initfini_array): Remove *-*-solaris2.*
tests.
* configure: Regenerate.
* config.in: Regenerate.
--- a/gcc/acinclude.m4
+++ b/gcc/acinclude.m4
@@ -461,23 +461,7 @@ changequote([,])dnl
# error The C library not known to support .init_array/.fini_array
# endif
#endif
-])],[
-case ${target} in
- *-*-solaris2.8*)
- # .init_array/.fini_array support was introduced in Solaris 8
- # patches 109147-08 (sparc) and 109148-08 (x86). Since ld.so.1 and
- # ld are guaranteed to be updated in lockstep, we can check ld -V
- # instead. Unfortunately, proper ld version numbers were only
- # introduced in rev. -14, so we check for that.
- if test $gcc_cv_sun_ld_vers_minor -lt 272; then
- gcc_cv_initfini_array=no
- fi
- ;;
- *-*-solaris2.9* | *-*-solaris2.1[[0-9]]*)
-# .init_array/.fini_array support is present since Solaris 9 FCS.
-;;
-esac
-], [gcc_cv_initfini_array=no]);;
+])],, [gcc_cv_initfini_array=no]);;
esac
else
AC_MSG_CHECKING(cross compile... guessing)
It seems to me that gcc_cv_sun_ld_ver* isn't used anywhere anymore, so
what about applying the following cleanup (completely untested):
gcc/
* acinclude.m4 (gcc_AC_INITFINI_ARRAY): Don't require
gcc_SUN_LD_VERSION.
(gcc_SUN_LD_VERSION): Remove, preserving some comments...
* configure.ac: ... here.
diff --git a/gcc/acinclude.m4 b/gcc/acinclude.m4
index c24464b..6410f2c 100644
--- a/gcc/acinclude.m4
+++ b/gcc/acinclude.m4
@@ -278,8 +278,7 @@ fi
fi])
AC_DEFUN([gcc_AC_INITFINI_ARRAY],
-[AC_REQUIRE([gcc_SUN_LD_VERSION])dnl
-AC_ARG_ENABLE(initfini-array,
+[AC_ARG_ENABLE(initfini-array,
[ --enable-initfini-array use .init_array/.fini_array sections],
[], [
AC_CACHE_CHECK(for .preinit_array/.init_array/.fini_array support,
@@ -488,43 +487,6 @@ if test $[$2] = yes; then
$7
fi])])
-dnl gcc_SUN_LD_VERSION
-dnl
-dnl Determines Sun linker version numbers, setting gcc_cv_sun_ld_vers to
-dnl the complete version number and gcc_cv_sun_ld_vers_{major, minor} to
-dnl the corresponding fields.
-dnl
-dnl ld and ld.so.1 are guaranteed to be updated in lockstep, so ld version
-dnl numbers can be used in ld.so.1 feature checks even if a different
-dnl linker is configured.
-dnl
-AC_DEFUN([gcc_SUN_LD_VERSION],
-[changequote(,)dnl
-if test x${build} = x${target} test x${build} = x${host}; then
- case ${target} in
-*-*-solaris2*)
- #
- # Solaris 2 ld -V output looks like this for a regular version:
- #
- # ld: Software Generation Utilities - Solaris Link Editors: 5.11-1.1699
- #
- # but test versions add stuff at the end:
- #
- # ld: Software Generation Utilities - Solaris Link Editors:
5.11-1.1701:onnv-ab196087-6931056-03/25/10
- #
- gcc_cv_sun_ld_ver=`/usr/ccs/bin/ld -V 21`
- if echo $gcc_cv_sun_ld_ver | grep 'Solaris Link Editors' /dev/null;
then
- gcc_cv_sun_ld_vers=`echo $gcc_cv_sun_ld_ver | sed -n \
- -e 's,^.*: 5\.[0-9][0-9]*-\([0-9]\.[0-9][0-9]*\).*$,\1,p'`
- gcc_cv_sun_ld_vers_major=`expr $gcc_cv_sun_ld_vers : '\([0-9]*\)'`
- gcc_cv_sun_ld_vers_minor=`expr $gcc_cv_sun_ld_vers :
'[0-9]*\.\([0-9]*\)'`
- fi
- ;;
- esac
-fi
-changequote([,])dnl
-])
-
dnl GCC_TARGET_TEMPLATE(KEY)
dnl
dnl Define KEY as a valid configure key on the target machine.
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 7891fcc..4ea2f9c 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -2290,11 +2290,21 @@ if test $in_tree_ld != yes ; then
else
case ${target} in
*-*-solaris2*)
- # See acinclude.m4 (gcc_SUN_LD_VERSION) for the version number
- # format.
+ # Determines Sun linker version numbers, setting gcc_cv_sun_ld_vers to
+ # the complete version number and gcc_cv_sun_ld_vers_{major, minor} to
+ # the corresponding fields.
#
- # Don't reuse gcc_gv_sun_ld_vers_* in case a linker other than
- # /usr/ccs/bin/ld has been configured.
+ # ld and ld.so.1 are guaranteed to be updated in lockstep, so ld
+ # version numbers can be used in ld.so.1 feature checks even if a
+ # different linker is configured.
+ #
+ # Solaris 2 ld -V output looks like this for a regular version:
+ #
+
