RE: [PATCH,testsuite] Add check_effective_target_rdynamic and use it in g++.dg/lto/pr69589_0.C.
Thanks, Rainer. Committed as r248916. Thanks for suggesting a backport, Renlin. Regards, Toma
RE: [PATCH,testsuite] Add check_effective_target_rdynamic and use it in g++.dg/lto/pr69589_0.C.
Hi Renlin,
>
> Thanks for fixing this! Do you have plan to backport the fix to gcc-6 branch?
>
I am happy to backport it.
I've rebased the patch on top of the gcc-6 branch and attached it below.
Rainer, is this OK for gcc-6?
Regards,
Toma Tabacu
gcc/ChangeLog:
Backported from mainline
2017-03-09 Toma Tabacu <toma.tab...@imgtec.com>
* doc/sourcebuild.texi (Effective-Target Keywords, Other attributes):
Document rdynamic.
gcc/testsuite/ChangeLog:
Backported from mainline
2017-03-09 Toma Tabacu <toma.tab...@imgtec.com>
* g++.dg/lto/pr69589_0.C: Add dg-require-effective-target for
rdynamic.
* lib/target-supports.exp (check_effective_target_rdynamic):
New proc.
Index: gcc/doc/sourcebuild.texi
===
--- gcc/doc/sourcebuild.texi(revision 248876)
+++ gcc/doc/sourcebuild.texi(working copy)
@@ -1950,6 +1950,9 @@
@item pie
Target supports @option{-pie}, @option{-fpie} and @option{-fPIE}.
+@item rdynamic
+Target supports @option{-rdynamic}.
+
@item section_anchors
Target supports section anchors.
Index: gcc/testsuite/lib/target-supports.exp
===
--- gcc/testsuite/lib/target-supports.exp (revision 248876)
+++ gcc/testsuite/lib/target-supports.exp (working copy)
@@ -1424,6 +1424,14 @@
} "-static"]
}
+# Return 1 if we can use the -rdynamic option, 0 otherwise.
+
+proc check_effective_target_rdynamic { } {
+ return [check_no_compiler_messages rdynamic executable {
+ int main() { return 0; }
+ } "-rdynamic"]
+}
+
# Return 1 if cilk-plus is supported by the target, 0 otherwise.
proc check_effective_target_cilkplus { } {
Index: gcc/testsuite/g++.dg/lto/pr69589_0.C
===
--- gcc/testsuite/g++.dg/lto/pr69589_0.C(revision 248876)
+++ gcc/testsuite/g++.dg/lto/pr69589_0.C(working copy)
@@ -1,6 +1,7 @@
// { dg-lto-do link }
// { dg-lto-options "-O2 -rdynamic" }
// { dg-extra-ld-options "-r -nostdlib" }
+// { dg-require-effective-target rdynamic }
#pragma GCC visibility push(hidden)
struct A { int [] (long); };
template struct B;
RE: Fix minor reorg.c bug affecting MIPS targets
From: Jeff Law > On 05/16/2017 10:01 AM, Toma Tabacu wrote: >> Hello Paul, >> >> You're seeing this problem because mips.exp can't handle -O* in dg-options. >> The other tests in gcc.target/mips use a dg-skip-if to skip for -O0 and -O1 >> instead of having -O2 in dg-options. >> This is supposed to ensure that the tests are run for as many optimization >> levels as possible. >> >> I believe that Matthew can confirm this. > Feel free to remove the -O2. The most important bits are -mips2 and > -msoft-float. If nobody does it shortly, I'll take care of it myself. > >jeff Sorry, I won't be able to commit the fix until tomorrow. Thanks for taking care of this issue, though. Regards, Toma Tabacu
RE: Fix minor reorg.c bug affecting MIPS targets
Hello Paul,
You're seeing this problem because mips.exp can't handle -O* in dg-options.
The other tests in gcc.target/mips use a dg-skip-if to skip for -O0 and -O1
instead of having -O2 in dg-options.
This is supposed to ensure that the tests are run for as many optimization
levels as possible.
I believe that Matthew can confirm this.
Regards,
Toma Tabacu
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On
> Behalf Of Paul Hua
> Sent: 16 May 2017 10:11
> To: Jeff Law
> Cc: gcc-patches
> Subject: Re: Fix minor reorg.c bug affecting MIPS targets
>
> Hi:
>
> There are new failures between r248067 and r248036 on
> mips64el-unknown-linux-gnu.
>
> ERROR: gcc.target/mips/reorgbug-1.c -O0 : Unrecognised option: -O2
> for " dg-options 1 "-O2 -msoft-float -mips2" "
> UNRESOLVED: gcc.target/mips/reorgbug-1.c -O0 : Unrecognised
> option: -O2 for " dg-options 1 "-O2 -msoft-float -mips2" "
> ERROR: gcc.target/mips/reorgbug-1.c -O1 : Unrecognised option: -O2
> for " dg-options 1 "-O2 -msoft-float -mips2" "
> UNRESOLVED: gcc.target/mips/reorgbug-1.c -O1 : Unrecognised
> option: -O2 for " dg-options 1 "-O2 -msoft-float -mips2" "
> ERROR: gcc.target/mips/reorgbug-1.c -O2 -flto
> -fno-use-linker-plugin -flto-partition=none : Unrecognised option: -O2
> for " dg-options 1 "-O2 -msoft-float -mips2" "
> UNRESOLVED: gcc.target/mips/reorgbug-1.c -O2 -flto
> -fno-use-linker-plugin -flto-partition=none : Unrecognised option: -O2
> for " dg-options 1 "-O2 -msoft-float -mips2" "
> ERROR: gcc.target/mips/reorgbug-1.c -O2 -flto -fuse-linker-plugin
> -fno-fat-lto-objects : Unrecognised option: -O2 for " dg-options 1
> "-O2 -msoft-float -mips2" "
> UNRESOLVED: gcc.target/mips/reorgbug-1.c -O2 -flto
> -fuse-linker-plugin -fno-fat-lto-objects : Unrecognised option: -O2
> for " dg-options 1 "-O2 -msoft-float -mips2" "
> ERROR: gcc.target/mips/reorgbug-1.c -O2 : Unrecognised option: -O2
> for " dg-options 1 "-O2 -msoft-float -mips2" "
> UNRESOLVED: gcc.target/mips/reorgbug-1.c -O2 : Unrecognised
> option: -O2 for " dg-options 1 "-O2 -msoft-float -mips2" "
> ERROR: gcc.target/mips/reorgbug-1.c -O3 -g : Unrecognised option:
> -O2 for " dg-options 1 "-O2 -msoft-float -mips2" "
> UNRESOLVED: gcc.target/mips/reorgbug-1.c -O3 -g : Unrecognised
> option: -O2 for " dg-options 1 "-O2 -msoft-float -mips2" "
> ERROR: gcc.target/mips/reorgbug-1.c -Os : Unrecognised option: -O2
> for " dg-options 1 "-O2 -msoft-float -mips2" "
> UNRESOLVED: gcc.target/mips/reorgbug-1.c -Os : Unrecognised
> option: -O2 for " dg-options 1 "-O2 -msoft-float -mips2" "
>
> I don't know why? just delete the "-O2" options in dg-options, then
> the test passed.
>
> diff --git a/gcc/testsuite/gcc.target/mips/reorgbug-1.c
> b/gcc/testsuite/gcc.target/mips/reorgbug-1.c
> index b820a2b..9537d21 100644
> --- a/gcc/testsuite/gcc.target/mips/reorgbug-1.c
> +++ b/gcc/testsuite/gcc.target/mips/reorgbug-1.c
> @@ -1,4 +1,4 @@
> -/* { dg-options "-O2 -msoft-float -mips2" } */
> +/* { dg-options "-msoft-float -mips2" } */
>
> typedef long int __int32_t;
> typedef long unsigned int __uint32_t;
>
> config info:Compiler version: 8.0.0 20170515 (experimental) (gcc trunk
> r248067 mips64el o32 n32 n64)
> Platform: mips64el-unknown-linux-gnu
> configure flags: --prefix=/home/xuchenghua/toolchain/gcc-trunk-r248067
> --enable-bootstrap --enable-shared --enable-threads=posix
> --enable-checking=release --enable-multilib--with-system-zlib
> --enable-__cxa_atexit --disable-libunwind-exceptions
> --enable-gnu-unique-object --enable-linker-build-id
> --enable-languages=c,c++,fortran --enable-plugin
> --enable-initfini-array --disable-libgcj --with-arch=mips64r2
> --with-abi=64 --with-multilib-list=32,n32,64
> --enable-gnu-indirect-function --with-long-double-128
> --build=mips64el-unknown-linux --target=mips64el-unknown-linux
> --with-pkgversion='gcc trunk r248067 mips64el o32 n32 n64'
> --disable-werror
>
>
> paul
>
> On Tue, May 16, 2017 at 1:22 AM, Jeff Law <l...@redhat.com> wrote:
> >
> >
> > There's a subtle bug in reorg.c's relax_delay_slots that my tester tripped
> > this weekend. Not sure what changed code generation wise as the affected
> > port built just fine last week. But it is what is is.
> >
> >
> >
> > Assume before this code we've set TARGET_LABEL to
[PATCH] Fix PR target/66015 for MIPS.
Hi,
The gcc.dg/ipa/iinline-attr.c test has been failing for MIPS when using the n32
and n64 ABIs.
These two ABIs imply a 64-bit target, which means that the align_loops,
align_jumps, and align_functions flags are set to 8 by default.
Because the MIPS backend doesn't use the TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
hook,
those default values will not be propagated through the __optimize__ attribute.
This was a known issue (PR target/66015) and was fixed for other architectures.
This patch implements the TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE for MIPS
and uses it to properly preserve the alignment flags.
Tested with mips-mti-elf.
Because we are in stage 4, we could temporarily xfail iinline-attr.c for MIPS
instead.
Regards,
Toma
gcc/
* config/mips/mips.c (mips_default_align): New function.
(mips_set_compression_mode): Use mips_default_align to set alignment
flags.
(mips_override_options_after_change): New function for the new hook.
(TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE): New hook.
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index d1deb52..65e105b 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -19360,6 +19360,21 @@ mips_output_mi_thunk (FILE *file, tree thunk_fndecl
ATTRIBUTE_UNUSED,
reload_completed = 0;
}
+/* Provide default values for align_* for 64-bit targets. */
+
+static void
+mips_default_align (struct gcc_options *opts)
+{
+ if (TARGET_64BIT)
+{
+ if (opts->x_align_loops == 0)
+ opts->x_align_loops = 8;
+ if (opts->x_align_jumps == 0)
+ opts->x_align_jumps = 8;
+ if (opts->x_align_functions == 0)
+ opts->x_align_functions = 8;
+}
+}
/* The last argument passed to mips_set_compression_mode,
or negative if the function hasn't been called yet. */
@@ -19450,15 +19465,7 @@ mips_set_compression_mode (unsigned int
compression_mode)
target_flags &= ~MASK_BRANCHLIKELY;
/* Provide default values for align_* for 64-bit targets. */
- if (TARGET_64BIT)
- {
- if (align_loops == 0)
- align_loops = 8;
- if (align_jumps == 0)
- align_jumps = 8;
- if (align_functions == 0)
- align_functions = 8;
- }
+ mips_default_align (_options);
targetm.min_anchor_offset = -32768;
targetm.max_anchor_offset = 32767;
@@ -19598,6 +19605,14 @@ mips_set_tune (const struct mips_cpu_info *info)
}
}
+/* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
+
+static void
+mips_override_options_after_change (void)
+{
+ mips_default_align (_options);
+}
+
/* Implement TARGET_OPTION_OVERRIDE. */
static void
@@ -22292,6 +22307,8 @@ mips_promote_function_mode (const_tree type
ATTRIBUTE_UNUSED,
#undef TARGET_OPTION_OVERRIDE
#define TARGET_OPTION_OVERRIDE mips_option_override
+#undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
+#define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE mips_override_options_after_change
#undef TARGET_LEGITIMIZE_ADDRESS
#define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
RE: [PATCH,testsuite] Skip pic-3,4.c and pie-3,4.c for mips*-*-linux-*.
> From: Matthew Fortune > > Given the acceptance that MIPS PIC behaviour is semi-unique then checking > MIPS > complies with the rules around pre-processor behaviour doesn't add much > value. > I'm happy to skip these tests on the basis that software can't make the same > assumptions about MIPS and __PIC__ as other architectures do. > > OK to commit. > > Thanks, > Matthew Committed as r246533. Thanks, Toma
[PATCH,testsuite] Skip pic-3,4.c and pie-3,4.c for mips*-*-linux-*.
Hi,
The pic-3,4.c and pie-3,4.c tests are failing for some configurations of
mips*-*-linux-*.
This is because PIC is always on for MIPS Linux by default, except when the
compiler is built with --with-mips-plt, in which case PIC is on by default only
for the n64 ABI, because in this case -mplt "has no effect without '-msym32'",
to quote the documentation, so -mplt is not passed by default.
Richard Sandiford also talked about this in the summary of a patch which was
skipping a test for mips*-*-linux-* because of PIC:
https://gcc.gnu.org/ml/gcc-patches/2009-01/msg00801.html
Therefore, I think the most reasonable solution would be to just skip these
tests for mips*-*-linux-*. The patch below does so.
Tested with mips-mti-linux-gnu.
Catherine, Matthew what do you think ?
Regards,
Toma
gcc/testsuite/
* gcc.dg/pic-3.c: Skip for mips*-*-linux-*.
* gcc.dg/pic-4.c: Likewise.
* gcc.dg/pie-3.c: Likewise.
* gcc.dg/pie-4.c: Likewise.
diff --git a/gcc/testsuite/gcc.dg/pic-3.c b/gcc/testsuite/gcc.dg/pic-3.c
index 23ce999..c56f06f 100644
--- a/gcc/testsuite/gcc.dg/pic-3.c
+++ b/gcc/testsuite/gcc.dg/pic-3.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { ! { *-*-darwin* hppa*64*-*-* } } } } */
+/* { dg-do compile { target { ! { *-*-darwin* hppa*64*-*-* mips*-*-linux-* } }
} } */
/* { dg-options "-fno-pic" } */
#ifdef __PIC__
diff --git a/gcc/testsuite/gcc.dg/pic-4.c b/gcc/testsuite/gcc.dg/pic-4.c
index 8e14714..2afdd99 100644
--- a/gcc/testsuite/gcc.dg/pic-4.c
+++ b/gcc/testsuite/gcc.dg/pic-4.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { ! { *-*-darwin* hppa*64*-*-* } } } } */
+/* { dg-do compile { target { ! { *-*-darwin* hppa*64*-*-* mips*-*-linux-* } }
} } */
/* { dg-options "-fno-PIC" } */
#ifdef __PIC__
diff --git a/gcc/testsuite/gcc.dg/pie-3.c b/gcc/testsuite/gcc.dg/pie-3.c
index a7201c0..5577437 100644
--- a/gcc/testsuite/gcc.dg/pie-3.c
+++ b/gcc/testsuite/gcc.dg/pie-3.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { ! { *-*-darwin* hppa*64*-*-* } } } } */
+/* { dg-do compile { target { ! { *-*-darwin* hppa*64*-*-* mips*-*-linux-* } }
} } */
/* { dg-options "-fno-pie" } */
#ifdef __PIC__
diff --git a/gcc/testsuite/gcc.dg/pie-4.c b/gcc/testsuite/gcc.dg/pie-4.c
index b24eb8c..4134676 100644
--- a/gcc/testsuite/gcc.dg/pie-4.c
+++ b/gcc/testsuite/gcc.dg/pie-4.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { ! { *-*-darwin* hppa*64*-*-* } } } } */
+/* { dg-do compile { target { ! { *-*-darwin* hppa*64*-*-* mips*-*-linux-* } }
} } */
/* { dg-options "-fno-PIE" } */
#ifdef __PIC__
RE: [PATCH] Fix MIPS-specific ICE in gcc.dg/pr77834.c (PR rtl-optimization/79150).
Hi, > From: Segher Boessenkool > On Mon, Mar 20, 2017 at 10:08:25PM +, Moore, Catherine wrote: > > I'm okay with the workaround for stage 4, but would like to see the pr > > remain > open until a proper fix is installed on trunk. > > Yeah. > Sure, I'll keep it open. > > Toma, would you be able to pursue the original patch that you attached to > > the > bug report? Yes, I intend to work on it after stage 4 ends. The temporary fix was committed as r246320. Thanks, Toma
RE: [PATCH,testsuite] Skip gcc.dg/pic-2.c and gcc.dg/pie-2.c for MIPS.
> > From: Matthew Fortune > > > > I think the skip is OK here. I'd like to get Catherine's opinion on > > this though too. I don't think we should change the definition of __PIC__ > > for -fPIC on MIPS as multi-got solves 'most' issues. If we start trying to > > figure out what __PIC__ should mean on MIPS then we will get into a big > > mess with -mxgot as that is arguably __PIC__==2 but I expect there will > > be several differing opinions. > > > From: Catherine Moore > > I think the skip is the right way to go as well. The patch is OK with me. > Catherine > Committed as r246311. Thanks, Toma
[PATCH,testsuite] Skip gcc.dg/pic-2.c and gcc.dg/pie-2.c for MIPS.
Hi,
The gcc.dg/pic-2.c and gcc.dg/pie-2.c tests are failing for MIPS targets
because __PIC__ is always set to 1 for MIPS.
This patch makes the testsuite skip those two tests for all MIPS targets.
Tested with mips-mti-elf and mips-mti-linux-gnu.
Should I have fixed this in target-supports.exp instead ?
I was worried that doing so would complicate the fpic and pie effective target
checks too much.
Regards,
Toma
gcc/testsuite/
* gcc.dg/pic-2.c: Skip for MIPS.
* gcc.dg/pie-2.c: Skip for MIPS.
diff --git a/gcc/testsuite/gcc.dg/pic-2.c b/gcc/testsuite/gcc.dg/pic-2.c
index 59ce8e2..bccec13 100644
--- a/gcc/testsuite/gcc.dg/pic-2.c
+++ b/gcc/testsuite/gcc.dg/pic-2.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
/* { dg-require-effective-target fpic } */
/* { dg-options "-fPIC" } */
+/* { dg-skip-if "__PIC__ is always 1 for MIPS" { mips*-*-* } } */
#if __PIC__ != 2
# error __PIC__ is not 2!
diff --git a/gcc/testsuite/gcc.dg/pie-2.c b/gcc/testsuite/gcc.dg/pie-2.c
index 7bdc4ac..1838745 100644
--- a/gcc/testsuite/gcc.dg/pie-2.c
+++ b/gcc/testsuite/gcc.dg/pie-2.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-fPIE" } */
/* { dg-require-effective-target pie } */
+/* { dg-skip-if "__PIC__ is always 1 for MIPS" { mips*-*-* } } */
#if __PIC__ != 2
# error __PIC__ is not 2!
RE: [PATCH 1/5] testsuite: attr-alloc_size-11.c (PR79356)
> > I just noticed that nothing has happened at all in a month, so anything > is better than the tests XPASSing on a number of targets. > > So the patch is ok for mainline with sparc*-*-* added to the target > lists and a reference to PR testsuite/79356 in the comment. > > I'd still be very grateful if Martin could have a look what's really > going on here, though. > > Thanks. > Rainer > Hi, This test has also been XPASS-ing for mips-mti-elf and mips-mti-linux-gnu, so I think you could also add mips*-*-* to the xfail targets. Regards, Toma
RE: [PATCH,testsuite] Add check_effective_target_rdynamic and use it in g++.dg/lto/pr69589_0.C.
> > Ok for mainline with that fixed. > > Thanks. > Rainer > Committed as r246004. Thanks, Toma
[PATCH] Fix MIPS-specific ICE in gcc.dg/pr77834.c (PR rtl-optimization/79150).
Hi,
This ICE is caused by "gcc_assert (!JUMP_P (last))" in
commit_one_edge_insertion (gcc/cfgrtl.c):
if (returnjump_p (last))
{
/* ??? Remove all outgoing edges from BB and add one for EXIT.
This is not currently a problem because this only happens
for the (single) epilogue, which already has a fallthru edge
to EXIT. */
e = single_succ_edge (bb);
gcc_assert (e->dest == EXIT_BLOCK_PTR_FOR_FN (cfun)
&& single_succ_p (bb) && (e->flags & EDGE_FALLTHRU));
e->flags &= ~EDGE_FALLTHRU;
emit_barrier_after (last);
if (before)
delete_insn (before);
}
else
gcc_assert (!JUMP_P (last));
The assert is triggered because we're removing an edge which ends on
a conditional jump, which is part of a loop.
The reason for the existence of this loop is the size of the vector used in
gcc.dg/pr77834.c.
When compiling code which uses vectors for MIPS, a looping memcpy is generated
if the vectors are big enough (>32 bytes for MIPS32 or >64 bytes for MIPS64).
This takes place in mips_expand_block_move (gcc/config/mips.c).
In our case, a looping memcpy gets generated for a partition copy which is
inserted on an edge (in insert_partition_copy_on_edge, gcc/tree-outof-ssa.c).
This happens during PHI node elimination, which is done by eliminate_phi
(gcc/tree-outof-ssa.c), as a part of expand_phi_nodes, which is called by the
expand pass (gcc/cfgexpand.c).
My original fix was to update the CFG by calling find_many_sub_basic_blocks
with an all-one block bitmap (which also happens in cfgexpand.c, after edge
removal) whenever an edge contains an insn which satisfies control_flow_insn_p.
However, Segher Boessenkool said that this would be too risky for stage 4
and suggested inserting a NOP after the conditional jump in order to fool the
assert. This assumes that it is safe to delay the CFG update for this
particular case.
This patch changes mips_block_move_loop to emit a NOP after the conditional
jump, if the jump is the last insn of the loop. This prevents
"gcc_assert (!JUMP_P (last))" from triggering.
The NOP will never make it into the final assembly code because it is removed
during the cse1 pass through DCE for -O1, -O2, and -O3, and it's not even
emitted for -O0 and -Os because looping memcpy's are not generated for those
optimization levels, as can be seen in mips_expand_block_move from mips.c:
if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
{
mips_block_move_straight (dest, src, INTVAL (length));
return true;
}
else if (optimize)
{
mips_block_move_loop (dest, src, INTVAL (length),
MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
return true;
}
Tested with mips-mti-elf.
Regards,
Toma Tabacu
gcc/
* config/mips/mips.c (mips_block_move_loop): Emit a NOP after the
conditional jump, if the jump is the last insn of the loop.
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 4e13fbe..43e719f 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -8098,6 +8098,9 @@ mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT
length,
/* Mop up any left-over bytes. */
if (leftover)
mips_block_move_straight (dest, src, leftover);
+ else
+/* Temporary fix for PR79150. */
+emit_insn (gen_nop ());
}
/* Expand a movmemsi instruction, which copies LENGTH bytes from
[PATCH,testsuite] Add check_effective_target_rdynamic and use it in g++.dg/lto/pr69589_0.C.
Hi,
g++.dg/lto/pr69589_0.C is currently failing for mips-mti-elf with the following
error:
xg++: error: unrecognized command line option '-rdynamic'
However, it passes just fine for mips-mti-linux-gnu.
I think that we should skip this test for mips-mti-elf.
This patch achieves this by adding support for check_effective_target_rdynamic
and then using it in g++.dg/lto/pr69589_0.C.
This patch also removes the existing dg-skip-if, as it is made redundant by the
effective target check. The latter is also more convenient, as we won't have to
keep tweaking the dg-skip-if for failing targets anymore.
This is similar to my recent check_effective_target_gettimeofday patch,
which was greatly improved by Rainer Orth's review.
Tested with mips-mti-elf and mips-mti-linux-gnu.
Does this look good ?
Regards,
Toma
gcc/
* doc/sourcebuild.texi (Effective-Target Keywords, Other attributes):
Document rdynamic.
gcc/testsuite/
* g++.dg/lto/pr69589_0.C: Add dg-require-effective-target for
rdynamic. Remove dg-skip-if for targets which don't support -rdynamic.
* lib/target-supports.exp (check_effective_target_rdynamic):
New proc.
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 0dc4348..d75e078 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2065,6 +2065,9 @@ Target supports @option{-mpe-aligned-commons}.
@item pie
Target supports @option{-pie}, @option{-fpie} and @option{-fPIE}.
+@item rdynamic
+Target supports @option{-rdynamic}.
+
@item section_anchors
Target supports section anchors.
diff --git a/gcc/testsuite/g++.dg/lto/pr69589_0.C
b/gcc/testsuite/g++.dg/lto/pr69589_0.C
index 11766f1..599d5d4 100644
--- a/gcc/testsuite/g++.dg/lto/pr69589_0.C
+++ b/gcc/testsuite/g++.dg/lto/pr69589_0.C
@@ -1,7 +1,7 @@
// { dg-lto-do link }
// { dg-lto-options "-O2 -rdynamic" }
// { dg-extra-ld-options "-r -nostdlib" }
-// { dg-skip-if "Skip targets without -rdynamic support" { arm*-none-eabi
aarch64*-*-elf nios2-*-elf } { "*" } { "" } }
+// { dg-require-effective-target rdynamic }
#pragma GCC visibility push(hidden)
struct A { int [] (long); };
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 2766af4..f46f0ba 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -1484,6 +1484,16 @@ proc check_effective_target_static_libgfortran { } {
} "-static"]
}
+# Return 1 if we can use the -rdynamic option, 0 otherwise.
+#
+# When the target name changes, replace the cached result.
+
+proc check_effective_target_rdynamic { } {
+ return [check_no_compiler_messages rdynamic executable {
+ int main() { return 0; }
+ } "-rdynamic"]
+}
+
# Return 1 if cilk-plus is supported by the target, 0 otherwise.
proc check_effective_target_cilkplus { } {
RE: [PATCH,testsuite] Skip gcc.dg/lto/pr60449_0.c for mips*-*-elf* targets.
> From: Catherine Moore > > This patch fixes my original objection. Thanks. > Committed as r245921. Thanks, Toma
RE: [PATCH,testsuite] MIPS: Force O32 ABI for inline-memcpy-3.c.
> From: Matthew Fortune > > Toma Tabacu writes: > > gcc/testsuite/ > > > > * gcc.target/mips/inline-memcpy-3.c (dg-options): Add -mabi=32. > > OK, thanks. Sorry for the slow reply. > > Matthew Committed as r245914. Thanks, Toma
RE: [PATCH,testsuite] MIPS: Fix register mode checking for n64 in pr68273.c.
> From: Matthew Fortune > > > > gcc/testsuite/ > > > > * gcc.target/mips/pr68273.c (dg-final): Match SImode registers only for > > ilp32 targets and match DImode registers for lp64 targets. > > OK, thanks. > > Matthew Committed as r245874. Thanks, Toma
[PATCH,testsuite] MIPS: Fix register mode checking for n64 in pr68273.c.
Hi,
pr68273.c currently fails when targeting MIPS64 with the n64 ABI.
This is because it is checking for some registers in SImode, but, because of
n64, they will actually be in DImode.
This patch restricts matching for SImode registers to ilp32 targets and adds
matching for DImode registers for lp64 targets.
This makes sure that the test is run on as many targets as possible, compared
to the alternative of adding -mabi=32 to the test options.
I haven't checked to see what happens with eabi or o64, though.
Does this approach work ? Or should I just make separate tests for o32, n32 and
n64, each one using -mabi=* as a test option to force an ABI ?
Tested with mips-mti-elf.
Regards,
Toma
gcc/testsuite/
* gcc.target/mips/pr68273.c (dg-final): Match SImode registers only for
ilp32 targets and match DImode registers for lp64 targets.
diff --git a/gcc/testsuite/gcc.target/mips/pr68273.c
b/gcc/testsuite/gcc.target/mips/pr68273.c
index cbe81e1..ce8ca93 100644
--- a/gcc/testsuite/gcc.target/mips/pr68273.c
+++ b/gcc/testsuite/gcc.target/mips/pr68273.c
@@ -75,5 +75,8 @@ op (Node q)
}
-/* { dg-final { scan-rtl-dump-times "\\\(set \\\(reg:SI 5 \\\$5\\\)" 2
"expand" } } */
-/* { dg-final { scan-rtl-dump-times "\\\(set \\\(reg:SI 6 \\\$6\\\)" 1
"expand" } } */
+/* { dg-final { scan-rtl-dump-times "\\\(set \\\(reg:SI 5 \\\$5\\\)" 2
"expand" { target { ilp32 } } } } */
+/* { dg-final { scan-rtl-dump-times "\\\(set \\\(reg:SI 6 \\\$6\\\)" 1
"expand" { target { ilp32 } } } } */
+
+/* { dg-final { scan-rtl-dump-times "\\\(set \\\(reg:DI 5 \\\$5\\\)" 2
"expand" { target { lp64 } } } } */
+/* { dg-final { scan-rtl-dump-times "\\\(set \\\(reg:DI 6 \\\$6\\\)" 1
"expand" { target { lp64 } } } } */
RE: [PATCH,testsuite] Skip gcc.dg/lto/pr60449_0.c for mips*-*-elf* targets.
Hi,
> From: Rainer Orth
> >
> > gcc/testsuite/
> >
> > * gcc.dg/lto/pr60449_0.c: Add dg-require-effective-target for
> > gettimeofday. Remove dg-skip-if for AVR.
>
> Two spaces after period.
>
Fixed.
> > * lib/target-supports.exp (check_effective_target_gettimeofday): New.
>
> Better say "New proc." or something like this.
>
Fixed.
>
> Thanks for your patience.
>
> Rainer
No problem.
Thanks for the review.
Below is the version with the updated ChangeLog entries.
Catherine, Matthew, what do you think ?
Regards,
Toma
gcc/
* doc/sourcebuild.texi (Effective-Target Keywords, Environment
attributes): Document gettimeofday.
gcc/testsuite/
* gcc.dg/lto/pr60449_0.c: Add dg-require-effective-target for
gettimeofday. Remove dg-skip-if for AVR.
* lib/target-supports.exp (check_effective_target_gettimeofday):
New proc.
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 0dc4348..da17ff6 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -1914,6 +1914,9 @@ Target is @samp{freestanding} as defined in section 4 of
the C99 standard.
Effectively, it is a target which supports no extra headers or libraries
other than what is considered essential.
+@item gettimeofday
+Target supports @code{gettimeofday}.
+
@item init_priority
Target supports constructors with initialization priority arguments.
diff --git a/gcc/testsuite/gcc.dg/lto/pr60449_0.c
b/gcc/testsuite/gcc.dg/lto/pr60449_0.c
index 5b878a6..e6c3166 100644
--- a/gcc/testsuite/gcc.dg/lto/pr60449_0.c
+++ b/gcc/testsuite/gcc.dg/lto/pr60449_0.c
@@ -1,5 +1,5 @@
/* { dg-lto-do link } */
-/* { dg-skip-if "Needs gettimeofday" { "avr-*-*" } } */
+/* { dg-require-effective-target gettimeofday } */
extern int printf (const char *__restrict __format, ...);
typedef long int __time_t;
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 2766af4..d1639dc 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -968,6 +968,11 @@ proc check_effective_target_setrlimit {} {
return [check_function_available "setrlimit"]
}
+# Return 1 if the target supports gettimeofday, 0 otherwise.
+proc check_effective_target_gettimeofday {} {
+return [check_function_available "gettimeofday"]
+}
+
# Return 1 if the target supports swapcontext, 0 otherwise.
proc check_effective_target_swapcontext {} {
return [check_no_compiler_messages swapcontext executable {
RE: [PATCH,testsuite] Skip gcc.dg/lto/pr60449_0.c for mips*-*-elf* targets.
Hi,
> From: Rainer Orth
>
> that's not what I suggested (or at least meant to suggest): having
> gettimeofday as an effective-target keyword (like setrlimit, mmap, and
> others) is the way to go, just your previous implementation of
> check_effective_target_gettimeofday was problematic/unreliable.
>
> If you go this route, there's no need to modify target-supports-dg.exp
> at all.
>
I see now. The dg-require-* directives are the predecessors to the
dg-require-effective-target directives.
I've changed it to be a dg-require-effective-target for gettimeofday instead.
Tested it and it works just as well as before.
>
> Besides: I forget to mention that new effective-target keywords need to
> be documented in sourcebuild.texi.
>
Done. Thanks for pointing this out.
There were 2 existing ways of describing this sort of effective-target; I chose
the more succinct one.
Regards,
Toma
gcc/
* doc/sourcebuild.texi (Effective-Target Keywords, Environment
attributes): Document gettimeofday.
gcc/testsuite/
* gcc.dg/lto/pr60449_0.c: Add dg-require-effective-target for
gettimeofday. Remove dg-skip-if for AVR.
* lib/target-supports.exp (check_effective_target_gettimeofday): New.
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 0dc4348..da17ff6 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -1914,6 +1914,9 @@ Target is @samp{freestanding} as defined in section 4 of
the C99 standard.
Effectively, it is a target which supports no extra headers or libraries
other than what is considered essential.
+@item gettimeofday
+Target supports @code{gettimeofday}.
+
@item init_priority
Target supports constructors with initialization priority arguments.
diff --git a/gcc/testsuite/gcc.dg/lto/pr60449_0.c
b/gcc/testsuite/gcc.dg/lto/pr60449_0.c
index 5b878a6..e6c3166 100644
--- a/gcc/testsuite/gcc.dg/lto/pr60449_0.c
+++ b/gcc/testsuite/gcc.dg/lto/pr60449_0.c
@@ -1,5 +1,5 @@
/* { dg-lto-do link } */
-/* { dg-skip-if "Needs gettimeofday" { "avr-*-*" } } */
+/* { dg-require-effective-target gettimeofday } */
extern int printf (const char *__restrict __format, ...);
typedef long int __time_t;
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 2766af4..d1639dc 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -968,6 +968,11 @@ proc check_effective_target_setrlimit {} {
return [check_function_available "setrlimit"]
}
+# Return 1 if the target supports gettimeofday, 0 otherwise.
+proc check_effective_target_gettimeofday {} {
+return [check_function_available "gettimeofday"]
+}
+
# Return 1 if the target supports swapcontext, 0 otherwise.
proc check_effective_target_swapcontext {} {
return [check_no_compiler_messages swapcontext executable {
RE: [PATCH,testsuite] Skip gcc.dg/lto/pr60449_0.c for mips*-*-elf* targets.
Hi Rainer,
Thank you for the feedback.
As you suggested, I have added a check_gettimeofday_available proc in
target-supports.exp and a dg-require-gettimeofday proc in target-supports-dg.exp
which check for gettimeofday using the existing check_function_available proc.
The test still runs and passes on mips-mti-linux-gnu, which has support for
gettimeofday, but it is now skipped for mips-mti-elf, which doesn't support it
(in my configuration, at least).
I have also removed the dg-skip-if for AVR from the test (haven't tested it on
AVR, though).
What do you think ?
Catherine, would this interfere with the MIPS ELF targets which do support
gettimeofday ?
Regards,
Toma
gcc/testsuite/
* gcc.dg/lto/pr60449_0.c: Add dg-require-gettimeofday. Remove
dg-skip-if for AVR.
* lib/target-supports-dg.exp (dg-require-gettimeofday): New function.
* lib/target-supports.exp (check_gettimeofday_available): Likewise.
diff --git a/gcc/testsuite/gcc.dg/lto/pr60449_0.c
b/gcc/testsuite/gcc.dg/lto/pr60449_0.c
index 5b878a6..2d3a900 100644
--- a/gcc/testsuite/gcc.dg/lto/pr60449_0.c
+++ b/gcc/testsuite/gcc.dg/lto/pr60449_0.c
@@ -1,5 +1,5 @@
/* { dg-lto-do link } */
-/* { dg-skip-if "Needs gettimeofday" { "avr-*-*" } } */
+/* { dg-require-gettimeofday "" } */
extern int printf (const char *__restrict __format, ...);
typedef long int __time_t;
diff --git a/gcc/testsuite/lib/target-supports-dg.exp
b/gcc/testsuite/lib/target-supports-dg.exp
index 6400d64..41369aa 100644
--- a/gcc/testsuite/lib/target-supports-dg.exp
+++ b/gcc/testsuite/lib/target-supports-dg.exp
@@ -236,6 +236,15 @@ proc dg-require-mkfifo { args } {
}
}
+# If this target does not have gettimeofday, skip this test.
+
+proc dg-require-gettimeofday { args } {
+if { ![check_gettimeofday_available] } {
+ upvar dg-do-what dg-do-what
+set dg-do-what [list [lindex ${dg-do-what} 0] "N" "P"]
+}
+}
+
# If this target does not use __cxa_atexit, skip this test.
proc dg-require-cxa-atexit { args } {
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 2766af4..9794383 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2287,6 +2287,12 @@ proc check_mkfifo_available {} {
return [check_function_available "mkfifo"]
}
+# Returns true iff "gettimeofday" is available on the target system.
+
+proc check_gettimeofday_available {} {
+return [check_function_available "gettimeofday"]
+}
+
# Returns true iff "__cxa_atexit" is used on the target system.
proc check_cxa_atexit_available { } {
[PATCH,testsuite] MIPS: Force O32 ABI for inline-memcpy-3.c.
Hi,
inline-memcpy-3.c fails when using -mabi=n64 and -mabi=n32 as a test-run option
because it does not impose a specific ABI in its test options.
As there already are variants of this test which force a specific ABI (N64 in
inline-memcpy-4.c and N32 in inline-memcpy-5.c), inline-memcpy-3.c should also
do so with the O32 ABI.
This patch forces the O32 ABI for this test by adding "-mabi=32" to the test
options.
Regards,
Toma
gcc/testsuite/
* gcc.target/mips/inline-memcpy-3.c (dg-options): Add -mabi=32.
diff --git a/gcc/testsuite/gcc.target/mips/inline-memcpy-3.c
b/gcc/testsuite/gcc.target/mips/inline-memcpy-3.c
index 3bdb28b..a449107 100644
--- a/gcc/testsuite/gcc.target/mips/inline-memcpy-3.c
+++ b/gcc/testsuite/gcc.target/mips/inline-memcpy-3.c
@@ -1,4 +1,4 @@
-/* { dg-options "-fno-common isa_rev<=5 (REQUIRES_STDLIB)" } */
+/* { dg-options "-fno-common isa_rev<=5 -mabi=32 (REQUIRES_STDLIB)" } */
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" "-Os"} { "" } } */
/* { dg-final { scan-assembler-not "\tmemcpy" } } */
/* { dg-final { scan-assembler-times "swl" 8 } } */
RE: [PATCH,testsuite] Skip gcc.dg/lto/pr60449_0.c for mips*-*-elf* targets.
> From: Catherine Moore
>
> Hi Toma,
> There are some MIPS ELF targets that do support gettimeofday. Perhaps you
> could handle this with a dg_require_effective_target entry for gettimeofday.
> Thanks,
> Catherine
>
Hi,
Thank you for your quick reply.
The patch below adds a dg_require_effective_target for gettimeofday.
Does it look good ? I'm having some doubts about the new directive's name.
Also, this patch makes the dg-skip-if for AVR redundant. Should I remove it ?
Regards,
Toma
gcc/testsuite/
* gcc.dg/lto/pr60449_0.c: Require gettimeofday support.
* lib/target-supports.exp (check_effective_target_gettimeofday): New.
diff --git a/gcc/testsuite/gcc.dg/lto/pr60449_0.c
b/gcc/testsuite/gcc.dg/lto/pr60449_0.c
index 5b878a6..ad83938 100644
--- a/gcc/testsuite/gcc.dg/lto/pr60449_0.c
+++ b/gcc/testsuite/gcc.dg/lto/pr60449_0.c
@@ -1,5 +1,6 @@
/* { dg-lto-do link } */
/* { dg-skip-if "Needs gettimeofday" { "avr-*-*" } } */
+/* { dg-require-effective-target gettimeofday } */
extern int printf (const char *__restrict __format, ...);
typedef long int __time_t;
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 2766af4..29d61ca 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -4342,6 +4342,32 @@ proc check_effective_target_mips_nanlegacy { } {
} "-mnan=legacy"]
}
+proc check_effective_target_gettimeofday { } {
+ return [check_no_compiler_messages gettimeofday executable {
+struct timeval
+ {
+ long int tv_sec;
+ long int tv_usec;
+ };
+
+struct timezone
+ {
+ int tz_minuteswest;
+ int tz_dsttime;
+ };
+
+extern int gettimeofday (struct timeval * __tv, struct timezone * __tz);
+
+int main ()
+{
+ struct timeval tv;
+ struct timezone tz;
+ gettimeofday (, );
+ return 0;
+}
+}]
+}
+
# Return 1 if an MSA program can be compiled to object
proc check_effective_target_mips_msa { } {
[PATCH,testsuite] Skip gcc.dg/lto/pr60449_0.c for mips*-*-elf* targets.
Hi,
The gcc.dg/lto/pr60449_0.c is failing for mips*-*-elf* targets because they do
not support gettimeofday, which is used in this test case.
This patch changes the test so that it is skipped for mips*-*-elf* targets.
Regards,
Toma
gcc/testsuite/
* gcc.dg/lto/pr60449_0.c (dg-skip-if): Skip for mips*-*-elf*.
diff --git a/gcc/testsuite/gcc.dg/lto/pr60449_0.c
b/gcc/testsuite/gcc.dg/lto/pr60449_0.c
index 5b878a6..6f3eccb 100644
--- a/gcc/testsuite/gcc.dg/lto/pr60449_0.c
+++ b/gcc/testsuite/gcc.dg/lto/pr60449_0.c
@@ -1,5 +1,5 @@
/* { dg-lto-do link } */
-/* { dg-skip-if "Needs gettimeofday" { "avr-*-*" } } */
+/* { dg-skip-if "Needs gettimeofday" { "avr-*-*" mips*-*-elf* } } */
extern int printf (const char *__restrict __format, ...);
typedef long int __time_t;
RE: [PATCH,testsuite] Use logical_op_short_circuit to skip targets in ssa-thread-14.c.
> From: Jeff Law > > I don't think using !logical_op_short_circuit is too heavy handed here. > > We get good coverage from the x86 target, so I don't mind losing > coverage from avr/s390 as the target selector is a lot more likely to be > correct after your change for the various targets now and in the future. > > OK for the trunk. > > Thanks, > > jeff > Thank you for the prompt review. Committed as r245711. Regards, Toma
[PATCH,testsuite] Use logical_op_short_circuit to skip targets in ssa-thread-14.c.
Hi,
The ssa-thread-14.c test has been failing for MIPS for a while.
According to Patrick Palka, who modified this test's target selector in the fix
for PR71314, this test fails on targets which don't use non-short-circuit
logical ops and should be skipped for such targets.
In the case of MIPS, LOGICAL_OP_NON_SHORT_CIRCUIT is set to 0, so the test
should be skipped for MIPS targets.
This patch adds the !logical_op_short_circuit requirement (defined in
testsuite/lib/target-supports.exp:7965) to ssa-thread-14.c's dg-options, which
will exclude MIPS targets. It also removes the "-mbranch-cost" options from
being passed to targets which will be skipped because of the newly added
!logical_op_short_circuit requirement.
This makes ssa-thread-14.c's target selector more similar the one from
ssa-thread-11.c (which was mentioned as a solution to PR71314 in the Bugzilla
thread).
Here are some links, for your convenience:
PR71314 on Bugzilla:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71314
The patch submission for fixing PR71314:
https://gcc.gnu.org/ml/gcc-patches/2016-05/msg02359.html
Does this look OK ?
Is the !logical_op_short_circuit too heavy-handed here ?
Regards,
Toma Tabacu
gcc/testsuite/
* gcc.dg/tree-ssa/ssa-thread-14.c (dg-options): Use
logical_op_short_circuit to skip targets.
(dg-additional-options): Don't pass -mbranch-cost=2 for MIPS, AVR
and s390.
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-thread-14.c
b/gcc/testsuite/gcc.dg/tree-ssa/ssa-thread-14.c
index c754b5b..aa1323a 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-thread-14.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-thread-14.c
@@ -1,6 +1,6 @@
-/* { dg-do compile { target { ! { m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-*
v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-*
xtensa*-*-* hppa*-*-* nios2*-*-* } } } } */
+/* { dg-do compile { target { ! { logical_op_short_circuit || { m68k*-*-*
mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-*
mcore*-*-* powerpc*-*-* xtensa*-*-* hppa*-*-* nios2*-*-* } } } } } */
/* { dg-additional-options "-O2 -fdump-tree-vrp-details" } */
-/* { dg-additional-options "-mbranch-cost=2" { target mips*-*-* avr-*-*
s390*-*-* i?86-*-* x86_64-*-* } } */
+/* { dg-additional-options "-mbranch-cost=2" { target i?86-*-* x86_64-*-* } }
*/
/* { dg-final { scan-tree-dump-times "Threaded jump" 8 "vrp1" } } */
void foo (void);
RE: [PATCH] MIPS: Fix mode mismatch error between Loongson builtin arguments and insn operands.
Matthew Fortune writes: > > Almost but not quite. There is a force_reg helper that takes care of > this i.e. can get rid of the qireg local and the whole if statement. > > emit_insn (gen_zero_extendqisi2 (sireg, force_reg (ops[2].value))); > > OK with that change. > > Thanks, > Matthew Committed as r245243. Thanks, Toma
RE: [PATCH] MIPS: Fix mode mismatch error between Loongson builtin arguments and insn operands.
Matthew Fortune writes:
>
> That's not what I hoped but is what I was concerned about as I believe it
> means we have a change of behaviour. It boils down to simply ignoring the
> argument type of unsigned char. My guess is that a zero extension is
> created but then immediately eliminated because of the paradoxical subreg.
>
> I think you need to create a temporary and perform the zero extension to
> ensure we honour the unsigned char operand:
>
> rtx new_dst = gen_reg_rtx (SImode);
> emit_insn (gen_zero_extendqisi2 (new_dst, ops[2].value));
> ops[2].value = foo;
>
> This should mean that the testcase I sent always has a zero extension but if
> you change the type of 'amount' to be unsigned char then there should not be
> a zero extension as the argument will be assumed to be correctly zero extended
> already and the explicitly introduced zero_extend will be eliminated.
>
I have made it generate a zero_extend instead of a SUBREG.
However, the pattern associated with gen_zero_extendqisi2 does not work with
immediate operands, so I had to add an extra step in which the argument is put
into a QImode register before being passed to gen_zero_extendqisi2.
Is this OK ?
Regards,
Toma
gcc/
* config/mips/mips.c (mips_expand_builtin_insn): Convert the QImode
argument of the pshufh, psllh, psllw, psrah, psraw, psrlh, psrlw
builtins to SImode and emit a zero-extend, if necessary.
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index da7fa8f..bab5b93 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -16571,9 +16571,35 @@ mips_expand_builtin_insn (enum insn_code icode,
unsigned int nops,
{
machine_mode imode;
int rangelo = 0, rangehi = 0, error_opno = 0;
+ rtx qireg, sireg;
switch (icode)
{
+/* The third operand of these instructions is in SImode, so we need to
+ bring the corresponding builtin argument from QImode into SImode. */
+case CODE_FOR_loongson_pshufh:
+case CODE_FOR_loongson_psllh:
+case CODE_FOR_loongson_psllw:
+case CODE_FOR_loongson_psrah:
+case CODE_FOR_loongson_psraw:
+case CODE_FOR_loongson_psrlh:
+case CODE_FOR_loongson_psrlw:
+ gcc_assert (has_target_p && nops == 3 && ops[2].mode == QImode);
+ sireg = gen_reg_rtx (SImode);
+ /* We need to put the immediate in a register because
+gen_zero_extendqisi2 does not accept immediate operands. */
+ if (CONST_INT_P (ops[2].value))
+ {
+ qireg = gen_reg_rtx (QImode);
+ emit_insn (gen_rtx_SET (qireg, ops[2].value));
+ emit_insn (gen_zero_extendqisi2 (sireg, qireg));
+ } else {
+ emit_insn (gen_zero_extendqisi2 (sireg, ops[2].value));
+ }
+ ops[2].value = sireg;
+ ops[2].mode = SImode;
+ break;
+
case CODE_FOR_msa_addvi_b:
case CODE_FOR_msa_addvi_h:
case CODE_FOR_msa_addvi_w:
RE: [PATCH] MIPS: Fix mode mismatch error between Loongson builtin arguments and insn operands.
> From: Matthew Fortune
> > +/* The third argument needs to be in SImode in order to succesfully
> > match
> > + the operand from the insn definition. */
>
> Please refer to operand here not argument as it is the second argument
> to the builtin but third operand of the instruction. Also double ss in
> successfully.
>
I have rewritten the comment to address these mistakes.
> > +case CODE_FOR_loongson_pshufh:
> > +case CODE_FOR_loongson_psllh:
> > +case CODE_FOR_loongson_psllw:
> > +case CODE_FOR_loongson_psrah:
> > +case CODE_FOR_loongson_psraw:
> > +case CODE_FOR_loongson_psrlh:
> > +case CODE_FOR_loongson_psrlw:
> > + gcc_assert (has_target_p && nops == 3 && ops[2].mode == QImode);
> > + ops[2].value = lowpart_subreg (SImode, ops[2].value, QImode);
> > + ops[2].mode = SImode;
> > + break;
> > +
> > case CODE_FOR_msa_addvi_b:
> > case CODE_FOR_msa_addvi_h:
> > case CODE_FOR_msa_addvi_w:
>
> For the record, given paradoxical subregs are a headache...
> I am OK with this on the basis that the argument to psllh etc is actually
> a uint8_t which means that bits 8 upwards are guaranteed to be zero so
> the subreg can be eliminated without any explicit sign or zero extension
> inserted. This is the same kind of optimisation that combine would
> perform when eliminating zero extension.
>
> Please can you check that a zero extension is inserted for the following
> case with -O2 or above:
>
> int16x4_t testme(int16x4_t s, int amount)
> {
> return psllh_s (s, amount);
> }
>
> If my understanding is correct there should be an ANDI 0xff inserted
> or similar.
>
The ANDI 0xff is present for -O0, after the first time the value is loaded
from memory, but it is not generated for -O1 and -O2.
I'm not seeing any zero extension happening for -O1 and -O2.
The only change in the patch below is the fixed comment.
Regards,
Toma
gcc/
* config/mips/mips.c (mips_expand_builtin_insn): Put the QImode
argument of the pshufh, psllh, psllw, psrah, psraw, psrlh, psrlw
builtins into an SImode paradoxical SUBREG.
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index da7fa8f..e5b2d9a 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -16574,6 +16574,20 @@ mips_expand_builtin_insn (enum insn_code icode,
unsigned int nops,
switch (icode)
{
+/* The third operand of these instructions is in SImode, so we need to
+ bring the corresponding builtin argument from QImode into SImode. */
+case CODE_FOR_loongson_pshufh:
+case CODE_FOR_loongson_psllh:
+case CODE_FOR_loongson_psllw:
+case CODE_FOR_loongson_psrah:
+case CODE_FOR_loongson_psraw:
+case CODE_FOR_loongson_psrlh:
+case CODE_FOR_loongson_psrlw:
+ gcc_assert (has_target_p && nops == 3 && ops[2].mode == QImode);
+ ops[2].value = lowpart_subreg (SImode, ops[2].value, QImode);
+ ops[2].mode = SImode;
+ break;
+
case CODE_FOR_msa_addvi_b:
case CODE_FOR_msa_addvi_h:
case CODE_FOR_msa_addvi_w:
[PATCH] MIPS: Fix mode mismatch error between Loongson builtin arguments and insn operands.
Hi,
The builtins for the pshufh, psllh, psllw, psrah, psraw, psrlh, psrlw Loongson
instructions have the third argument's type set to UQI while its corresponding
insn operand is in SImode.
This results in the following error when matching insn operands:
../gcc/gcc/include/loongson.h: In function 'test_psllw_s':
../gcc/gcc/include/loongson.h:483:10: error: invalid argument to built-in
function
return __builtin_loongson_psllw_s (s, amount);
^~
This causes the loongson-simd.c and loongson-shift-count-truncated-1.c tests
to fail.
This patch fixes this by wrapping the QImode builtin argument inside a
paradoxical SUBREG with SImode, which will successfully match against the insn
operand.
Tested with mips-mti-elf.
Regards,
Toma
gcc/
* config/mips/mips.c (mips_expand_builtin_insn): Put the QImode
argument of the pshufh, psllh, psllw, psrah, psraw, psrlh, psrlw
builtins into an SImode paradoxical SUBREG.
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index da7fa8f..f1ca6e2 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -16574,6 +16574,20 @@ mips_expand_builtin_insn (enum insn_code icode,
unsigned int nops,
switch (icode)
{
+/* The third argument needs to be in SImode in order to succesfully match
+ the operand from the insn definition. */
+case CODE_FOR_loongson_pshufh:
+case CODE_FOR_loongson_psllh:
+case CODE_FOR_loongson_psllw:
+case CODE_FOR_loongson_psrah:
+case CODE_FOR_loongson_psraw:
+case CODE_FOR_loongson_psrlh:
+case CODE_FOR_loongson_psrlw:
+ gcc_assert (has_target_p && nops == 3 && ops[2].mode == QImode);
+ ops[2].value = lowpart_subreg (SImode, ops[2].value, QImode);
+ ops[2].mode = SImode;
+ break;
+
case CODE_FOR_msa_addvi_b:
case CODE_FOR_msa_addvi_h:
case CODE_FOR_msa_addvi_w:
RE: [PATCH] MIPS: Fix generation of DIV.G and MOD.G for Loongson targets.
> From: Matthew Fortune > > Apart from those changes this looks OK to me. > > Matthew Thanks. Committed as r244570. Regards, Toma
RE: [PATCH] MIPS: Fix generation of DIV.G and MOD.G for Loongson targets.
> Maciej Rozycki writes:
> > This ought to be handled then, likely by adding Loongson-specific RTL
> > insns matching the `divmod4' and `udivmod4' expanders. It
> > may be as simple as say (conceptually, untested):
> >
> > (define_insn "divmod4_loongson"
> > [(set (match_operand:GPR 0 "register_operand" "=d")
> > (any_div:GPR (match_operand:GPR 1 "register_operand" "d")
> > (match_operand:GPR 2 "register_operand" "d")))
> >(set (match_operand:GPR 3 "register_operand" "=d")
> > (any_mod:GPR (match_dup 1)
> > (match_dup 2)))]
> > "TARGET_LOONGSON_2EF"
> > {
> > return mips_output_division
> > ("div.g\t%0,%1,%2\;mod.g\t%3,%1,%2",
> operands);
> > }
> > [(set_attr "type" "idiv")
> >(set_attr "mode" "")])
> >
> > although any final fix will have to take an instruction count adjustment
> > into account too, as `mips_idiv_insns' won't as it stands handle the new
> > case.
Thanks for the tip Maciej!
I will tackle that issue in a separate patch.
Matthew Fortune writes:
>
> Sounds good. I'd prefer to get the testsuite clean first then improve the
> code quality as a later step since it is not a regression and we are
> a few days off stage 4.
>
> In terms of the patch then the ISA_HAS_DIV3 macro is not currently used so
> I suggest that instead it is renamed to ISA_AVOID_DIV_HILO and then use
> that macro in the definition of ISA_HAS_DIV and ISA_HAS_DDIV to turn
> off the DIV/DDIV instructions.
>
> The ISA_HAS_DIV3 should have been cleaned up when R6 was added as it is
> ambiguous and could refer to multiple variants of 3-reg operand DIV now
> rather than just Loongson's.
>
> Thanks,
> Matthew
I believe the patch below fits the description.
I've also added a (too?) succinct explanation for the ISA_AVOID_DIV_HILO macro.
Tested with mips-mti-elf.
Regards,
Toma
gcc/ChangeLog:
* config/mips/mips.h: Add macro to prevent generation of regular
(D)DIV(U) instructions for Loongson.
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index f91b43d..e21e7d8 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -967,19 +967,24 @@ struct mips_cpu_info {
/* ISA supports instructions DMUL, DMULU, DMUH, DMUHU. */
#define ISA_HAS_R6DMUL (TARGET_64BIT && mips_isa_rev >= 6)
+/* For Loongson, it is preferable to use the Loongson-specific division and
+ modulo instructions instead of the regular (D)DIV(U) instruction, because
+ the former are faster and also have the effect of reducing code size. */
+#define ISA_AVOID_DIV_HILO ((TARGET_LOONGSON_2EF \
+ || TARGET_LOONGSON_3A)\
+&& !TARGET_MIPS16)
+
/* ISA supports instructions DDIV and DDIVU. */
#define ISA_HAS_DDIV (TARGET_64BIT \
&& !TARGET_MIPS5900\
+&& !ISA_AVOID_DIV_HILO \
&& mips_isa_rev <= 5)
/* ISA supports instructions DIV and DIVU.
This is always true, but the macro is needed for ISA_HAS_DIV
in mips.md. */
-#define ISA_HAS_DIV(mips_isa_rev <= 5)
-
-#define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \
- || TARGET_LOONGSON_3A)\
-&& !TARGET_MIPS16)
+#define ISA_HAS_DIV(!ISA_AVOID_DIV_HILO\
+&& mips_isa_rev <= 5)
/* ISA supports instructions DIV, DIVU, MOD and MODU. */
#define ISA_HAS_R6DIV (mips_isa_rev >= 6)
RE: [PATCH] MIPS: Fix generation of DIV.G and MOD.G for Loongson targets.
After searching through the archives, I have found an interesting bit of information about DIV.G/MOD.G in the original submission thread: > > Ruan Beihong 23 July 2008: > > > > I've seen the Loongson 2F manual carefully. The (d)div(u) is > > internally splited into one (d)div(u).g and one (d)mod(u).g. So I said > > before was wrong. The truth is that, (d)div(u).g and (d)mod(u).g are > > always faster than (d)div(u), at least the time spend on mflo/mfhi is > > saved. > > > > James Ruan > > Richard Sandiford 24 July 2008: > > OK, great. In that case, it should simply be a case of disabling > the divmod-related insns for Loongson, in addition to your patch. > (Probably stating the obvious there, sorry.) > > Richard Here's the link for part 1 of the submission thread (has the quotes from above): https://gcc.gnu.org/ml/gcc-patches/2008-07/msg01529.html and here's part 2: https://gcc.gnu.org/ml/gcc-patches/2008-11/msg00273.html If DIV.G/MOD.G are faster, according to Ruan Beihong, and also smaller than DIV (or the same size [1]), as pointed out by Maciej, then I am led to the same conclusion as Richard Sandiford: that only DIV.G/MOD.G should be generated for Loongson. I think it would still be a good idea to add a test for separated DIV.G/MOD.G, though. What are your thoughts on this ? Have I misunderstood something in the context of the submission thread ? Regards, Toma [1] I've noticed that GCC generates the same TEQ instruction twice if both DIV.G and MOD.G are needed, which makes the sequence just as big as DIV + TEQ + MFHI + MFLO; this seems unnecessary to me.
RE: [PATCH] MIPS: Fix generation of DIV.G and MOD.G for Loongson targets.
> Maciej Rozycki writes: > > > > > Unfortunately, this interferes with the generation of DIV.G and MOD.G > > (the div3 and mod3 patterns) for Loongson targets, > which > > causes test failures. > > What test failures? Details please. > It's gcc.target/mips/loongson-muldiv-1.c gcc.target/mips/loongson-muldiv-2.c gcc.target/mips/loongson3a-muldiv-1.c gcc.target/mips/loongson3a-muldiv-2.c on O2, O3, and Os. They are also checking for the Loongson-specific multiply instruction, but there are no failures for that. > > > This solution might be excessive, however, as it effectively forbids the > > generation of the old DIV instruction for Loongson targets, which actually > > do > > support it. > > What's the purpose of this change other than "fixing test failures"? > Can you please demonstrate a technical justification of this change? Has > there been a code quality regression which this patch addresses for > example? What about source code which did emit `divmod4' and > `udivmod4' patterns on Loongson targets before r241660? > > Given that the DIV.G, MOD.G and accumulator DIV instructions (and their > unsigned counterparts) are all available the compiler should have freedom > to choose whichever hardware operation is the most suitable for the > calculations required according to code generation options selected and > artificially disabling some hardware instructions does not appear to be a > move in that direction to me. > > Maciej I'll be honest here: I don't know when the compiler should generate the Loongson-specific division and modulo instructions, I don't have access to Loongson hardware, and I wasn't even specifically trying to fix Loongson-related issues. I admit that the patch was submitted in haste, and I now realize that my proposal was unfounded and that I don't have the means to find a satisfactory solution. Too much wishful thinking on my part. However, there is a legitimate underlying issue here and I felt it had to be brought up, but this should have been a bug report, not a patch submission. Anyway, thank you for the feedback. Regards, Toma
[PATCH] MIPS: Fix generation of DIV.G and MOD.G for Loongson targets.
Hi,
The expand_DIVMOD function, introduced in r241660, will pick the divmod4
(or the udivmod4) pattern when it checks for the presence of hardware
div/mod instructions, which results in the generation of the old DIV
instruction.
Unfortunately, this interferes with the generation of DIV.G and MOD.G
(the div3 and mod3 patterns) for Loongson targets, which
causes test failures.
This patch prevents the selection of divmod4 and udivmod4 when
targeting Loongson by adding !ISA_HAS_DIV3 to the match condition.
ISA_HAS_DIV3 checks for the presence of the 3-operand Loongson-specific DIV.G
and MOD.G instructions.
Tested with mips-mti-elf.
This solution might be excessive, however, as it effectively forbids the
generation of the old DIV instruction for Loongson targets, which actually do
support it.
Is this OK ?
Regards,
Toma
gcc/ChangeLog:
* config/mips/mips.md (divmod4): Add check for !ISA_HAS_DIV3.
(udivmod4): Likewise.
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 076cde6..f2fedcc 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -2851,7 +2851,7 @@
(set (match_operand:GPR 3 "register_operand")
(mod:GPR (match_dup 1)
(match_dup 2)))])]
- "ISA_HAS_DIV && !TARGET_FIX_VR4120"
+ "ISA_HAS_DIV && !TARGET_FIX_VR4120 && !ISA_HAS_DIV3"
{
if (TARGET_MIPS16)
{
@@ -2916,7 +2916,7 @@
(set (match_operand:GPR 3 "register_operand")
(umod:GPR (match_dup 1)
(match_dup 2)))])]
- "ISA_HAS_DIV && !TARGET_FIX_VR4120"
+ "ISA_HAS_DIV && !TARGET_FIX_VR4120 && !ISA_HAS_DIV3"
{
if (TARGET_MIPS16)
{
RE: [PATCH, testsuite] MIPS: Cleanup the forcing of assembly output in error tests.
> From: Catherine Moore > > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/mips/oddspreg-2.c (dg-options): Remove dg-skip-if > > for > > -fno-fat-lto-objects and add the -ffat-lto-objects option, along > > with > > an explanation for its purpose. > > * gcc.target/mips/oddspreg-3.c (dg-options): Likewise. > > * gcc.target/mips/oddspreg-6.c (dg-options): Likewise. > > * gcc.target/mips/no-dsp-1.c: Add an explanation for the > > purpose of > > -ffat-lto-objects. > > * gcc.target/mips/pr54240.c: Likewise. > > * gcc.target/mips/r10k-cache-barrier-14.c: Likewise. > > * gcc.target/mips/soft-float-1.c: Likewise. > > > > This is OK. Thank you for reviewing this so close to the holidays. Committed as r243908. Regards, Toma
RE: [PATCH, testsuite] MIPS: Relax instruction order check in msa-builtins.c.
> Catherine Moore writes: > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/mips/msa-builtins.c (dg-final): Tweak regex for the > > 32-bit > > insert.d case. > > Please change to: > * gcc.target/mips-msa-builtins.c (msa_insert_d): Tweak expected > output. > > Okay with that change. > Thanks, > Catherine > Committed as r243848. Regards, Toma
[PATCH, testsuite] MIPS: Relax instruction order check in msa-builtins.c.
Hi,
The 32-bit insert.d case in msa-builtins.c is failing with O2 and Os because
the order of the emitted instructions is slightly different compared to the
other optimization levels.
This patch tweaks the regular expression for 32-bit insert.d to accept the
alternate instruction order.
Tested with mips-mti-elf.
Regards,
Toma
gcc/testsuite/ChangeLog:
* gcc.target/mips/msa-builtins.c (dg-final): Tweak regex for the 32-bit
insert.d case.
diff --git a/gcc/testsuite/gcc.target/mips/msa-builtins.c
b/gcc/testsuite/gcc.target/mips/msa-builtins.c
index 6db3d66..a679f06 100644
--- a/gcc/testsuite/gcc.target/mips/msa-builtins.c
+++ b/gcc/testsuite/gcc.target/mips/msa-builtins.c
@@ -481,7 +481,7 @@
/* { dg-final { scan-assembler-times "msa_insert_h:.*insert\\.h.*msa_insert_h"
1 } } */
/* { dg-final { scan-assembler-times "msa_insert_w:.*insert\\.w.*msa_insert_w"
1 } } */
/* { dg-final { scan-assembler-times "msa_insert_d:.*insert\\.d.*msa_insert_d"
1 { target mips64 } } } */
-/* { dg-final { scan-assembler-times
"msa_insert_d:.*sra.*insert.w.*insert.w.*msa_insert_d" 1 { target {! mips64 } }
} } */
+/* { dg-final { scan-assembler
"msa_insert_d:.*(sra.*insert.w.*insert.w|insert.w.*sra.*insert.w).*msa_insert_d"
{ target {! mips64 } } } } */
/* { dg-final { scan-assembler-times "msa_insve_b:.*insve\\.b.*msa_insve_b" 1
} } */
/* { dg-final { scan-assembler-times "msa_insve_h:.*insve\\.h.*msa_insve_h" 1
} } */
/* { dg-final { scan-assembler-times "msa_insve_w:.*insve\\.w.*msa_insve_w" 1
} } */
RE: [PATCH, testsuite] MIPS: Upgrade to R2 for -mmicromips.
Committed as r243687. Regards, Toma > Toma Tabacu writes: > > microMIPS is not supported on pre-R2 architectures, but the testsuite allows > > it to be used on pre-R2 architectures, which results in test failures. > > > > This patch makes the testsuite upgrade to R2 if -mmicromips is used in a > > test. > > > > Tested with mips-mti-elf. > > > > Regards, > > Toma > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/mips/mips.exp (mips-dg-options): Upgrade to R2 for > > -mmicromips. > > OK, thanks. > > Matthew
[PATCH, testsuite] MIPS: Cleanup the forcing of assembly output in error tests.
Hi,
Some error tests were forcing assembly output incorrectly, and none of them had
an explanation for why they were using -ffat-lto-objects.
This patch removes dg-skip-if's for -fno-fat-lto-objects and
adds -ffat-lto-objects to the test options instead.
It also adds an explanation for the purpose of -ffat-lto-objects in each test.
Tested with mips-mti-elf.
Regards,
Toma
gcc/testsuite/ChangeLog:
* gcc.target/mips/oddspreg-2.c (dg-options): Remove dg-skip-if for
-fno-fat-lto-objects and add the -ffat-lto-objects option, along with
an explanation for its purpose.
* gcc.target/mips/oddspreg-3.c (dg-options): Likewise.
* gcc.target/mips/oddspreg-6.c (dg-options): Likewise.
* gcc.target/mips/no-dsp-1.c: Add an explanation for the purpose of
-ffat-lto-objects.
* gcc.target/mips/pr54240.c: Likewise.
* gcc.target/mips/r10k-cache-barrier-14.c: Likewise.
* gcc.target/mips/soft-float-1.c: Likewise.
diff --git a/gcc/testsuite/gcc.target/mips/no-dsp-1.c
b/gcc/testsuite/gcc.target/mips/no-dsp-1.c
index c4a7b0a..f03f239 100644
--- a/gcc/testsuite/gcc.target/mips/no-dsp-1.c
+++ b/gcc/testsuite/gcc.target/mips/no-dsp-1.c
@@ -1,4 +1,7 @@
/* { dg-options "-mno-dsp -ffat-lto-objects" } */
+/* This is testing for errors which can only happen in assembly generation.
+ dg-error does not guarantee assembly generation, so we need to do it
+ manually by using -ffat-lto-objects. */
void
foo (void)
diff --git a/gcc/testsuite/gcc.target/mips/oddspreg-2.c
b/gcc/testsuite/gcc.target/mips/oddspreg-2.c
index efeb0af..1a85737 100644
--- a/gcc/testsuite/gcc.target/mips/oddspreg-2.c
+++ b/gcc/testsuite/gcc.target/mips/oddspreg-2.c
@@ -1,6 +1,8 @@
/* Check that we disable odd-numbered single precision registers. */
-/* { dg-skip-if "needs asm output" { *-*-* } { "-fno-fat-lto-objects" } { "" }
} */
-/* { dg-options "-mabi=32 -mno-odd-spreg -mhard-float" } */
+/* { dg-options "-mabi=32 -mno-odd-spreg -mhard-float -ffat-lto-objects" } */
+/* This is testing for errors which can only happen in assembly generation.
+ dg-error does not guarantee assembly generation, so we need to do it
+ manually by using -ffat-lto-objects. */
NOMIPS16 void
foo ()
diff --git a/gcc/testsuite/gcc.target/mips/oddspreg-3.c
b/gcc/testsuite/gcc.target/mips/oddspreg-3.c
index 8a0d85c..16a2f03 100644
--- a/gcc/testsuite/gcc.target/mips/oddspreg-3.c
+++ b/gcc/testsuite/gcc.target/mips/oddspreg-3.c
@@ -1,6 +1,8 @@
/* Check that we disable odd-numbered single precision registers. */
-/* { dg-skip-if "needs asm output" { *-*-* } { "-fno-fat-lto-objects" } { "" }
} */
-/* { dg-options "-mabi=32 -mfp32 -march=loongson3a -mhard-float" } */
+/* { dg-options "-mabi=32 -mfp32 -march=loongson3a -mhard-float
-ffat-lto-objects" } */
+/* This is testing for errors which can only happen in assembly generation.
+ dg-error does not guarantee assembly generation, so we need to do it
+ manually by using -ffat-lto-objects. */
NOMIPS16 void
foo ()
diff --git a/gcc/testsuite/gcc.target/mips/oddspreg-6.c
b/gcc/testsuite/gcc.target/mips/oddspreg-6.c
index eb376c6..53ac076 100644
--- a/gcc/testsuite/gcc.target/mips/oddspreg-6.c
+++ b/gcc/testsuite/gcc.target/mips/oddspreg-6.c
@@ -1,6 +1,8 @@
/* Check that we disable odd-numbered single precision registers for FPXX. */
-/* { dg-skip-if "needs asm output" { *-*-* } { "-fno-fat-lto-objects" } { "" }
} */
-/* { dg-options "-mabi=32 -mfpxx -mhard-float" } */
+/* { dg-options "-mabi=32 -mfpxx -mhard-float -ffat-lto-objects" } */
+/* This is testing for errors which can only happen in assembly generation.
+ dg-error does not guarantee assembly generation, so we need to do it
+ manually by using -ffat-lto-objects. */
NOMIPS16 void
foo ()
diff --git a/gcc/testsuite/gcc.target/mips/pr54240.c
b/gcc/testsuite/gcc.target/mips/pr54240.c
index 2d55b82..d3976f6 100644
--- a/gcc/testsuite/gcc.target/mips/pr54240.c
+++ b/gcc/testsuite/gcc.target/mips/pr54240.c
@@ -1,6 +1,9 @@
/* { dg-do compile } */
/* { dg-options "-fdump-tree-phiopt-details -ffat-lto-objects isa>=4" } */
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" "-O1" } { "" } } */
+/* This is testing for errors which can only happen in assembly generation.
+ dg-error does not guarantee assembly generation, so we need to do it
+ manually by using -ffat-lto-objects. */
typedef struct s {
int v;
diff --git a/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-14.c
b/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-14.c
index 92c37f4..ecb4158 100644
--- a/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-14.c
+++ b/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-14.c
@@ -1,5 +1,8 @@
/* { dg-options "(-mips16) -mr10k-cache-barrier=store -ffat-lto-objects" } */
/* Test that indirect calls are protected. */
+/* This is testing for errors which can only happen in assembly generation.
+ dg-error does not guarantee assembly generation, so we need to do
RE: [PATCH, testsuite] MIPS: Remove redundant dg-skip-if from mips16-attributes.c.
Committed as r243649. Regards, Toma > Toma Tabacu writes: > > In the case of mips16-attributes.c, even though the (-mips16) option ensures > > that -mmicromips will be overriden, there still is a dg-skip-if for > > -mmicromips. > > > > I think that it is not necessary and it actually decreases test coverage, > > because it will cause the testsuite to skip this test instead of letting > > (-mips16) do its job of overriding the global options. > > > > This patch removes the dg-skip-if for -mmicromips. > > > > Tested with mips-mti-elf. > > > > Regards, > > Toma > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/mips/mips16-attributes.c: Remove dg-skip-if for > > -mmicromips. > > OK, thanks. > > Matthew
[PATCH, testsuite] MIPS: Upgrade to R2 for -mmicromips.
Hi,
microMIPS is not supported on pre-R2 architectures, but the testsuite allows
it to be used on pre-R2 architectures, which results in test failures.
This patch makes the testsuite upgrade to R2 if -mmicromips is used in a test.
Tested with mips-mti-elf.
Regards,
Toma
gcc/testsuite/ChangeLog:
* gcc.target/mips/mips.exp (mips-dg-options): Upgrade to R2 for
-mmicromips.
diff --git a/gcc/testsuite/gcc.target/mips/mips.exp
b/gcc/testsuite/gcc.target/mips/mips.exp
index 3d04d2f..d0f4037 100644
--- a/gcc/testsuite/gcc.target/mips/mips.exp
+++ b/gcc/testsuite/gcc.target/mips/mips.exp
@@ -1147,7 +1147,8 @@ proc mips-dg-options { args } {
|| [mips_have_test_option_p options "HAS_MADDPS"]
|| [mips_have_test_option_p options "-mdspr2"]
|| [mips_have_test_option_p options "-mnan=2008"]
-|| [mips_have_test_option_p options "-mabs=2008"]) } {
+|| [mips_have_test_option_p options "-mabs=2008"]
+|| [mips_have_test_option_p options "-mmicromips"]) } {
if { $gp_size == 32 } {
mips_make_test_option options "-mips32r2"
} else {
[PATCH, testsuite] MIPS: Remove redundant dg-skip-if from mips16-attributes.c.
Hi,
In the case of mips16-attributes.c, even though the (-mips16) option ensures
that -mmicromips will be overriden, there still is a dg-skip-if for -mmicromips.
I think that it is not necessary and it actually decreases test coverage,
because it will cause the testsuite to skip this test instead of letting
(-mips16) do its job of overriding the global options.
This patch removes the dg-skip-if for -mmicromips.
Tested with mips-mti-elf.
Regards,
Toma
gcc/testsuite/ChangeLog:
* gcc.target/mips/mips16-attributes.c: Remove dg-skip-if for
-mmicromips.
diff --git a/gcc/testsuite/gcc.target/mips/mips16-attributes.c
b/gcc/testsuite/gcc.target/mips/mips16-attributes.c
index e1497c0..421aa77 100644
--- a/gcc/testsuite/gcc.target/mips/mips16-attributes.c
+++ b/gcc/testsuite/gcc.target/mips/mips16-attributes.c
@@ -3,7 +3,6 @@
function. */
/* { dg-do run } */
/* { dg-options "(-mips16) (REQUIRES_STDLIB)" } */
-/* { dg-skip-if "" { *-*-* } { "-mmicromips" } { "" } } */
#include
RE: [PATCH, testsuite] MIPS: Skip msa-builtins-err.c if there is no assembly output.
Committed as r243639. Regards, Toma > -Original Message- > From: Matthew Fortune > Sent: 13 December 2016 13:46 > To: Toma Tabacu; gcc-patches@gcc.gnu.org > Cc: catherine_mo...@mentor.com > Subject: RE: [PATCH, testsuite] MIPS: Skip msa-builtins-err.c if there is no > assembly output. > > Toma Tabacu <toma.tab...@imgtec.com> writes: > > > > > > It's a shame this is the only way to deal with this but I see aarch64 > > > have to resort to the same thing for error checking tests. > > > > > > > I have looked into this some more and I 've found that the solution I > > proposed is incomplete. > > > > The problem is that if no linker plugin is found, -fno-fat-lto-objects > > is not passed on, so the test isn't skipped and it will fail because - > > flto doesn't do assembly generation by default and the errors will not > > be triggered. > > > > This can be fixed by adding -ffat-lto-objects as a test option for error > > tests, as shown in the patch below. > > > > The thing is, this already happens for scan-assembler & friends behind- > > the-scenes, but not for dg-error, because the former are run through > > force_conventional_output, while the latter is not. > > > > A nicer solution would be to have a new directive which would do nothing > > except for the force_conventional_output part, thus forcing assembly > > generation, but this may be overkill. > > > > Regards, > > Toma > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/mips/msa-builtins-err.c (dg-options): Use > > -ffat-lto-objects to guarantee assembly generation. > > OK, thanks for investigating. Slight tweak to the changelog we just say > what changed in the changelog not why. You covered 'why' in the code > comment. This is just: > > (dg-options): Add -ffat-lto-objects option. > > Thanks, > Matthew
RE: [PATCH, testsuite] MIPS: Skip msa-builtins-err.c if there is no assembly output.
>
> It's a shame this is the only way to deal with this but I see aarch64 have
> to resort to the same thing for error checking tests.
>
I have looked into this some more and I 've found that the solution I proposed
is incomplete.
The problem is that if no linker plugin is found, -fno-fat-lto-objects is not
passed on, so the test isn't skipped and it will fail because -flto doesn't do
assembly generation by default and the errors will not be triggered.
This can be fixed by adding -ffat-lto-objects as a test option for error tests,
as shown in the patch below.
The thing is, this already happens for scan-assembler & friends
behind-the-scenes, but not for dg-error, because the former are run through
force_conventional_output, while the latter is not.
A nicer solution would be to have a new directive which would do nothing except
for the force_conventional_output part, thus forcing assembly generation,
but this may be overkill.
Regards,
Toma
gcc/testsuite/ChangeLog:
* gcc.target/mips/msa-builtins-err.c (dg-options): Use
-ffat-lto-objects to guarantee assembly generation.
diff --git a/gcc/testsuite/gcc.target/mips/msa-builtins-err.c
b/gcc/testsuite/gcc.target/mips/msa-builtins-err.c
index 041b7f5..68244d6 100644
--- a/gcc/testsuite/gcc.target/mips/msa-builtins-err.c
+++ b/gcc/testsuite/gcc.target/mips/msa-builtins-err.c
@@ -1,6 +1,8 @@
/* Test builtins for MIPS MSA ASE instructions */
/* { dg-do compile } */
-/* { dg-options "-mfp64 -mhard-float -mmsa" } */
+/* { dg-options "-mfp64 -mhard-float -mmsa -ffat-lto-objects" } */
+/* Because this test only uses dg-error, we need to guarantee assembly
+ generation ourselves by using -ffat-lto-objects. */
#include
RE: [PATCH, testsuite] MIPS: Upgrade to R2 for -mnan=2008 and -mabs=2008.
> > The -mnan=2008 and -mabs=2008 options are not supported on pre-R2 > targets. > > This results in failures for tests which use these options, such as > > nan-2008.c, > > fabs-2008.c etc. > > > > This patch makes the testsuite upgrade to R2 if -mnan=2008 and -mabs=2008 > are > > used as test options. > > > > Tested with mips-mti-elf. > > > > Regards, > > Toma Tabacu > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/mips/mips.exp (mips-dg-options): Upgrade to R2 for > > -mnan=2008 and -mabs=2008. > > OK, thanks. > > Matthew Committed as r243542. Regards, Toma
[PATCH, testsuite] MIPS: Upgrade to R2 for -mnan=2008 and -mabs=2008.
Hi,
The -mnan=2008 and -mabs=2008 options are not supported on pre-R2 targets.
This results in failures for tests which use these options, such as nan-2008.c,
fabs-2008.c etc.
This patch makes the testsuite upgrade to R2 if -mnan=2008 and -mabs=2008 are
used as test options.
Tested with mips-mti-elf.
Regards,
Toma Tabacu
gcc/testsuite/ChangeLog:
* gcc.target/mips/mips.exp (mips-dg-options): Upgrade to R2 for
-mnan=2008 and -mabs=2008.
diff --git a/gcc/testsuite/gcc.target/mips/mips.exp
b/gcc/testsuite/gcc.target/mips/mips.exp
index c0b9680..3d04d2f 100644
--- a/gcc/testsuite/gcc.target/mips/mips.exp
+++ b/gcc/testsuite/gcc.target/mips/mips.exp
@@ -1145,7 +1145,9 @@ proc mips-dg-options { args } {
|| [mips_have_test_option_p options "HAS_INS"]
|| [mips_have_test_option_p options "HAS_MADD"]
|| [mips_have_test_option_p options "HAS_MADDPS"]
-|| [mips_have_test_option_p options "-mdspr2"]) } {
+|| [mips_have_test_option_p options "-mdspr2"]
+|| [mips_have_test_option_p options "-mnan=2008"]
+|| [mips_have_test_option_p options "-mabs=2008"]) } {
if { $gp_size == 32 } {
mips_make_test_option options "-mips32r2"
} else {
[PATCH, testsuite] MIPS: Skip msa-builtins-err.c if there is no assembly output.
Hi,
The msa-builtins-err.c test is failing in the following configuration:
-O2 -flto -fuse-linker-plugin -fno-fat-lto-objects
This is because the errors it is checking for are triggered by assembly
generation, which is prevented by -fno-fat-lto-objects.
This patch fixes this by adding a dg-skip-if for -fno-fat-lto-objects.
Tested with mips-mti-elf.
Regards,
Toma Tabacu
gcc/testsuite/ChangeLog:
* gcc.target/mips/msa-builtins-err.c (dg-skip-if): Do not run the test
if -fno-fat-lto-objects is present.
diff --git a/gcc/testsuite/gcc.target/mips/msa-builtins-err.c
b/gcc/testsuite/gcc.target/mips/msa-builtins-err.c
index 041b7f5..57acee0 100644
--- a/gcc/testsuite/gcc.target/mips/msa-builtins-err.c
+++ b/gcc/testsuite/gcc.target/mips/msa-builtins-err.c
@@ -1,6 +1,7 @@
/* Test builtins for MIPS MSA ASE instructions */
/* { dg-do compile } */
/* { dg-options "-mfp64 -mhard-float -mmsa" } */
+/* { dg-skip-if "needs asm output" { *-*-* } { "-fno-fat-lto-objects" } { "" }
} */
#include
[PATCH, testsuite] MIPS: Add isa>=2 option to interrupt_handler-bug-1.c.
Hi,
Currently, the interrupt_handler-bug-1.c test will fail on pre-R2 targets
because the "interrupt" function attribute requires at least an R2 target and
the test does not enforce this requirement.
This patch fixes this by adding the isa_rev>=2 option to the test's dg-options.
Tested with mips-mti-elf.
Regards,
Toma Tabacu
gcc/testsuite/ChangeLog:
2016-11-21 Toma Tabacu <toma.tab...@imgtec.com>
* gcc.target/mips/interrupt_handler-bug-1.c (dg-options): Add
isa_rev>=2.
diff --git a/gcc/testsuite/gcc.target/mips/interrupt_handler-bug-1.c
b/gcc/testsuite/gcc.target/mips/interrupt_handler-bug-1.c
index 2784705..083e152 100644
--- a/gcc/testsuite/gcc.target/mips/interrupt_handler-bug-1.c
+++ b/gcc/testsuite/gcc.target/mips/interrupt_handler-bug-1.c
@@ -1,4 +1,4 @@
-/* { dg-options "-funroll-loops" } */
+/* { dg-options "-funroll-loops isa_rev>=2" } */
int foo;
int bar;
[COMMITTED] Add myself to MAINTAINERS (Write After Approval).
Committed as r242595. Thanks, Toma Tabacu Index: ChangeLog === --- ChangeLog (revision 242594) +++ ChangeLog (working copy) @@ -1,3 +1,7 @@ +2016-11-18 Toma Tabacu <toma.tab...@imgtec.com> + + * MAINTAINERS (Write After Approval): Add myself. + 2016-11-15 Matthias Klose <d...@ubuntu.com> * Makefile.def: Remove references to GCJ. Index: MAINTAINERS === --- MAINTAINERS (revision 242594) +++ MAINTAINERS (working copy) @@ -587,6 +587,7 @@ Robert Suchanek <robert.sucha...@imgtec.com> Andrew Sutton <andrew.n.sut...@gmail.com> Gabriele Svelto<gabriele.sve...@st.com> +Toma Tabacu<toma.tab...@imgtec.com> Sriraman Tallam<tmsri...@google.com> Chung-Lin Tang <clt...@codesourcery.com> Samuel Tardieu <s...@rfc1149.net>
RE: [PATCH] MIPS: If a test in the MIPS testsuite requires standard library support check the sysroot supports the required test options.
> From: Moore, Catherine [mailto:catherine_mo...@mentor.com]
> Sent: 17 November 2016 21:53
> To: Matthew Fortune; Toma Tabacu; Andrew Bennett; 'gcc-
> patc...@gcc.gnu.org'
> Cc: Moore, Catherine
> Subject: RE: [PATCH] MIPS: If a test in the MIPS testsuite requires standard
> library support check the sysroot supports the required test options.
>
>
>
> > -Original Message-
> > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> > ow...@gcc.gnu.org] On Behalf Of Matthew Fortune
> > Sent: Thursday, November 17, 2016 8:47 AM
> > To: Toma Tabacu <toma.tab...@imgtec.com>; Andrew Bennett
> > <andrew.benn...@imgtec.com>; Moore, Catherine
> > <catherine_mo...@mentor.com>; 'gcc-patches@gcc.gnu.org' > patc...@gcc.gnu.org>
> > Subject: RE: [PATCH] MIPS: If a test in the MIPS testsuite requires
> > standard library support check the sysroot supports the required test
> > options.
> >
> > Toma Tabacu <toma.tab...@imgtec.com> writes:
> > > Hi,
> > >
> > > The patch below is a rebased version of Andrew's patch plus a few
> > more changes
> > > to test options.
> > >
> > > I have tested Andrew's patch by passing -msoft-float to the testsuite
> > without
> > > having a soft-float library available, and saw that the inline-memcpy-
> > {1,2,3,4,5}.c
> > > and memcpy-1.c tests were also failing to find standard library
> > headers.
> > > In the version below, I have added (REQUIRES_STDLIB) to them as
> > well.
> > >
> > > However, I believe that the memcpy-1.c test was removed from the
> > first version
> > > of Andrew's patch in response to Matthew's comments, but I don't
> > think it
> > > should be.
> > >
> > > Tested with mips-img-linux-gnu and mips-mti-linux-gnu.
> >
> > This looks OK to me but I then again I helped with the design for this.
> >
> > I'd like to give Catherine a chance to take a look though as the feature
> > is unusual.
> >
> > One comment below.
> >
> > > diff --git a/gcc/testsuite/gcc.target/mips/mips.exp
> > > b/gcc/testsuite/gcc.target/mips/mips.exp
> > > index e22d782..ccd4ecb 100644
> > > --- a/gcc/testsuite/gcc.target/mips/mips.exp
> > > +++ b/gcc/testsuite/gcc.target/mips/mips.exp
> > > @@ -1420,6 +1426,22 @@ proc mips-dg-options { args } {
> > > }
> > > }
> > >
> > > +# If the test is marked as requiring standard libraries check
> > > +# that the sysroot has support for the current set of test options.
> > > +if { [mips_have_test_option_p options "REQUIRES_STDLIB"] } {
> > > + mips_push_test_options saved_options $extra_tool_flags
> > > + set output [mips_preprocess "" {
> > > + #include
> > > + } 1]
> > > + mips_pop_test_options saved_options
> > > +
> > > + # If the preprocessing of the stdlib.h file produced errors mark
> > > + # the test as unsupported.
> > > + if { ![string equal $output ""] } {
> > > + set do_what [lreplace $do_what 1 1 "N"]
> >
> > We should describe what we expect the format of do_what to be at
> > the time
> > of writing in case it ever changes. i.e. a comment to say what the
> > second
> > character means and therefore make it clear that setting it to 'n' makes
> > the test unsupported.
> >
>
> This patch looks okay to me after updating the comment as Matthew suggested.
The version below has a more detailed comment about marking tests as
unsupported.
Matthew, does it look good to you ?
Also, should we document our expectations for the rest of do_what's format
(elements 0 and 2) ?
Regards,
Toma Tabacu
gcc/testsuite/ChangeLog:
* gcc.target/mips/inline-memcpy-1.c (dg-options): Add
(REQUIRES_STDLIB).
* gcc.target/mips/inline-memcpy-2.c: Ditto.
* gcc.target/mips/inline-memcpy-3.c: Ditto.
* gcc.target/mips/inline-memcpy-4.c: Ditto.
* gcc.target/mips/inline-memcpy-5.c: Ditto.
* gcc.target/mips/loongson-shift-count-truncated-1.c: Ditto.
* gcc.target/mips/loongson-simd.c: Ditto.
* gcc.target/mips/memcpy-1.c: Ditto.
* gcc.target/mips/mips-3d-1.c: Ditto.
* gcc.target/mips/mips-3d-2.c: Ditto.
* gcc.target/mips/mips-3d-3.c: Ditto.
* gcc.target/mips/mips-3d-4.c: Ditto.
* gcc.target/mips/mips-3d-5.c: Ditto.
* gcc.target/mips/mips-3d-6.c: Ditto.
* gcc.target/mips/mips-3d-7.c: Ditto.
* gcc.target/mips/mips-3d-8.c: Ditto.
* gcc.t
RE: [PATCH] MIPS: If a test in the MIPS testsuite requires standard library support check the sysroot supports the required test options.
t; >
> > # Preprocess CODE using target_compile options OPTIONS. Return the
> > # compiler output.
> > -proc mips_preprocess { options code } {
> > +proc mips_preprocess { options code ignore_output } {
> > global tool
> >
> > set src dummy[pid].c
> > set f [open $src "w"]
> > puts $f $code
> > close $f
> > -set output [${tool}_target_compile $src "" preprocess $options]
> > +if { $ignore_output } {
> > + set output [${tool}_target_compile $src dummy[pid].i preprocess
> > $options]
> > + file delete dummy[pid].i
> > +} else {
> > + set output [${tool}_target_compile $src "" preprocess $options]
> > +}
> > file delete $src
> >
> > return $output
> > @@ -463,7 +469,7 @@ proc mips_arch_info { arch prop } {
> > #else
> > int isa_rev = 0;
> > #endif
> > - }]
> > + } 0]
> > foreach lhs { isa isa_rev } {
> > regsub ".*$lhs = (\[^;\]*).*" $output {\1} rhs
> > verbose -log "Architecture $arch has $lhs $rhs"
> > @@ -816,7 +822,7 @@ proc mips-dg-init {} {
> >
> > 0
> > };
> > -}]
> > +} 0]
> > foreach line [split $output "\r\n"] {
> > # Poor man's string concatenation.
> > regsub -all {" "} $line "" line
> > @@ -1390,6 +1396,22 @@ proc mips-dg-options { args } {
> > }
> > }
> >
> > +# If the test is marked as requiring standard libraries check
> > +# that the sysroot has support for the current set of test options.
> > +if { [mips_have_test_option_p options "REQUIRES_STDLIB"] } {
> > + mips_push_test_options saved_options $extra_tool_flags
> > + set output [mips_preprocess "" {
> > + #include
> > + } 1]
> > + mips_pop_test_options saved_options
> > +
> > + # If the preprocessing of the stdlib.h file produced errors mark
> > + # the test as unsupported.
> > + if { ![string equal $output ""] } {
> > + set do_what [lreplace $do_what 1 1 "N"]
> > + }
> > + }
> > +
> > # If the test is MIPS16-compatible, provide a counterpart to the
> > # NOMIPS16 convenience macro.
> > if { [mips_have_test_option_p options "-mips16"] } {
> > diff --git a/gcc/testsuite/gcc.target/mips/mips16-attributes.c
> > b/gcc/testsuite/gcc.target/mips/mips16-attributes.c
> > index 28bb9aa..421aa77 100644
> > --- a/gcc/testsuite/gcc.target/mips/mips16-attributes.c
> > +++ b/gcc/testsuite/gcc.target/mips/mips16-attributes.c
> > @@ -2,7 +2,7 @@
> > of calling a nomips16/mips16/default function from a
> > nomips16/mips16/default
> > function. */
> > /* { dg-do run } */
> > -/* { dg-options "(-mips16)" } */
> > +/* { dg-options "(-mips16) (REQUIRES_STDLIB)" } */
> >
> > #include
> >
> > diff --git a/gcc/testsuite/gcc.target/mips/mips32-dsp-run.c
> > b/gcc/testsuite/gcc.target/mips/mips32-dsp-run.c
> > index ccd9d38..ca12d04 100644
> > --- a/gcc/testsuite/gcc.target/mips/mips32-dsp-run.c
> > +++ b/gcc/testsuite/gcc.target/mips/mips32-dsp-run.c
> > @@ -1,6 +1,6 @@
> > /* Test MIPS32 DSP instructions */
> > /* { dg-do run } */
> > -/* { dg-options "-mdsp" } */
> > +/* { dg-options "-mdsp (REQUIRES_STDLIB)" } */
> >
> > #include
> > #include
> > diff --git a/gcc/testsuite/gcc.target/mips/mips32-dsp.c
> > b/gcc/testsuite/gcc.target/mips/mips32-dsp.c
> > index 9aaf120..d212bcf 100644
> > --- a/gcc/testsuite/gcc.target/mips/mips32-dsp.c
> > +++ b/gcc/testsuite/gcc.target/mips/mips32-dsp.c
> > @@ -1,6 +1,6 @@
> > /* Test MIPS32 DSP instructions */
> > /* { dg-do compile } */
> > -/* { dg-options "-mgp32 -mdsp" } */
> > +/* { dg-options "-mgp32 -mdsp (REQUIRES_STDLIB)" } */
> > /* { dg-final { scan-assembler "\taddq.ph\t" } } */
> > /* { dg-final { scan-assembler "\taddq_s.ph\t" } } */
> > /* { dg-final { scan-assembler "\taddq_s.w\t" } } */
> > diff --git a/gcc/testsuite/gcc.target/mips/save-restore-1.c
> > b/gcc/testsuite/gcc.target/mips/save-restore-1.c
> > index b3ce1b1..5e1e838 100644
> > --- a/gcc/testsuite/gcc.target/mips/save-restore-1.c
> > +++ b/gcc/testsuite/gcc.target/mips/save-restore-1.c
> > @@ -1,5 +1,5 @@
> > /* Check that we can use the save instructi
RE: [PATCH,testsuite] MIPS: Downgrade from R6 to R5 to prevent redundant testing of branch-cost-1.c.
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Toma Tabacu
> Sent: 15 November 2016 14:00
> To: gcc-patches@gcc.gnu.org
> Cc: Matthew Fortune; catherine_mo...@mentor.com
> Subject: [PATCH,testsuite] MIPS: Downgrade from R6 to R5 to prevent
> redundant testing of branch-cost-1.c.
>
> Hi,
>
> The branch-cost-1.c test uses the isa>=4 option to ensure the existence of the
> MOVN/MOVZ instructions. This, however, does not take into account R6
> targets,
> which are accepted by the isa>=4 option but do not support MOVN/MOVZ.
>
> This particular test does not fail on R6, because it is checking for the
> absence of MOVN/MOVZ, but it is redundant.
>
> This patch fixes this by replacing isa>=4 with (HAS_MOVN), which will only
> accept targets in the [MIPS IV, R5] interval.
>
> Tested with mips-img-linux-gnu.
>
> Regards,
> Toma Tabacu
>
> gcc/testsuite/ChangeLog:
>
> 2016-11-15 Toma Tabacu <toma.tab...@imgtec.com>
>
> * gcc.target/mips/branch-cost-1.c: Use (HAS_MOVN) instead of isa>=4,
> in order to downgrade to R5.
>
> diff --git a/gcc/testsuite/gcc.target/mips/branch-cost-1.c
> b/gcc/testsuite/gcc.target/mips/branch-cost-1.c
> index 61c3029..7f7ebbe 100644
> --- a/gcc/testsuite/gcc.target/mips/branch-cost-1.c
> +++ b/gcc/testsuite/gcc.target/mips/branch-cost-1.c
> @@ -1,4 +1,4 @@
> -/* { dg-options "-mbranch-cost=1 isa>=4" } */
> +/* { dg-options "-mbranch-cost=1 (HAS_MOVN)" } */
> /* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
> NOMIPS16 int
> foo (int x, int y, int z, int k)
The version below has a slightly more precise ChangeLog entry.
Regards,
Toma Tabacu
gcc/testsuite/ChangeLog:
2016-11-15 Toma Tabacu <toma.tab...@imgtec.com>
* gcc.target/mips/branch-cost-1.c (dg-options): Use (HAS_MOVN) instead
of isa>=4, in order to downgrade to R5.
diff --git a/gcc/testsuite/gcc.target/mips/branch-cost-1.c
b/gcc/testsuite/gcc.target/mips/branch-cost-1.c
index 61c3029..7f7ebbe 100644
--- a/gcc/testsuite/gcc.target/mips/branch-cost-1.c
+++ b/gcc/testsuite/gcc.target/mips/branch-cost-1.c
@@ -1,4 +1,4 @@
-/* { dg-options "-mbranch-cost=1 isa>=4" } */
+/* { dg-options "-mbranch-cost=1 (HAS_MOVN)" } */
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
NOMIPS16 int
foo (int x, int y, int z, int k)
[PATCH,testsuite] MIPS: Downgrade from R6 to R5 to prevent redundant testing of branch-cost-1.c.
Hi,
The branch-cost-1.c test uses the isa>=4 option to ensure the existence of the
MOVN/MOVZ instructions. This, however, does not take into account R6 targets,
which are accepted by the isa>=4 option but do not support MOVN/MOVZ.
This particular test does not fail on R6, because it is checking for the
absence of MOVN/MOVZ, but it is redundant.
This patch fixes this by replacing isa>=4 with (HAS_MOVN), which will only
accept targets in the [MIPS IV, R5] interval.
Tested with mips-img-linux-gnu.
Regards,
Toma Tabacu
gcc/testsuite/ChangeLog:
2016-11-15 Toma Tabacu <toma.tab...@imgtec.com>
* gcc.target/mips/branch-cost-1.c: Use (HAS_MOVN) instead of isa>=4,
in order to downgrade to R5.
diff --git a/gcc/testsuite/gcc.target/mips/branch-cost-1.c
b/gcc/testsuite/gcc.target/mips/branch-cost-1.c
index 61c3029..7f7ebbe 100644
--- a/gcc/testsuite/gcc.target/mips/branch-cost-1.c
+++ b/gcc/testsuite/gcc.target/mips/branch-cost-1.c
@@ -1,4 +1,4 @@
-/* { dg-options "-mbranch-cost=1 isa>=4" } */
+/* { dg-options "-mbranch-cost=1 (HAS_MOVN)" } */
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
NOMIPS16 int
foo (int x, int y, int z, int k)
RE: [PATCH,testsuite] MIPS: Upgrade to MIPS IV if using (HAS_MOVN) with MIPS III.
> From: Moore, Catherine [mailto:catherine_mo...@mentor.com]
> Sent: 08 November 2016 20:47
> To: Toma Tabacu; gcc-patches@gcc.gnu.org
> Cc: Matthew Fortune
> Subject: RE: [PATCH,testsuite] MIPS: Upgrade to MIPS IV if using (HAS_MOVN)
> with MIPS III.
>
>
>
> > -Original Message-
> > From: Toma Tabacu [mailto:toma.tab...@imgtec.com]
> > Sent: Monday, November 7, 2016 11:21 AM
> > gcc/testsuite/ChangeLog:
> >
> > 2016-11-07 Toma Tabacu <toma.tab...@imgtec.com>
> >
> > * gcc.target/mips/mips.exp (mips-dg-options): Upgrade to MIPS IV if
> using
> > (HAS_MOVN) with MIPS III.
> >
> > diff --git a/gcc/testsuite/gcc.target/mips/mips.exp
> > b/gcc/testsuite/gcc.target/mips/mips.exp
> > index 39f44ff..e22d782 100644
> > --- a/gcc/testsuite/gcc.target/mips/mips.exp
> > +++ b/gcc/testsuite/gcc.target/mips/mips.exp
> > @@ -1129,7 +1129,7 @@ proc mips-dg-options { args } {
> > # We need MIPS IV or higher for:
> > #
> > #
> > - } elseif { $isa < 3
> > + } elseif { $isa < 4
> >&& [mips_have_test_option_p options "HAS_MOVN"] }
> > {
> > mips_make_test_option options "-mips4"
> > # We need MIPS III or higher for:
>
> Hi Toma,
>
> The patch itself is OK, but the ChangeLog entry line length is greater than
> 80.
>
Yes, sorry. The version below fixes this.
> Do you have write access to the repository? Please let me know if you would
> like me to commit this for you?
>
> Thanks,
> Catherine
No, I don't have write access.
I would be grateful if you could commit the patch for me, if you think it
would be OK with Matthew.
To be clear, I am not in a rush to get this committed.
Thanks,
Toma Tabacu
gcc/testsuite/ChangeLog:
2016-11-09 Toma Tabacu <toma.tab...@imgtec.com>
* gcc.target/mips/mips.exp (mips-dg-options): Upgrade to MIPS IV if
using (HAS_MOVN) with MIPS III.
diff --git a/gcc/testsuite/gcc.target/mips/mips.exp
b/gcc/testsuite/gcc.target/mips/mips.exp
index 39f44ff..e22d782 100644
--- a/gcc/testsuite/gcc.target/mips/mips.exp
+++ b/gcc/testsuite/gcc.target/mips/mips.exp
@@ -1129,7 +1129,7 @@ proc mips-dg-options { args } {
# We need MIPS IV or higher for:
#
#
- } elseif { $isa < 3
+ } elseif { $isa < 4
&& [mips_have_test_option_p options "HAS_MOVN"] } {
mips_make_test_option options "-mips4"
# We need MIPS III or higher for:
[PATCH,testsuite] MIPS: Upgrade to MIPS IV if using (HAS_MOVN) with MIPS III.
Hi,
The (HAS_MOVN) option should cause an upgrade to MIPS IV if the target is
pre-MIPS IV. However, the upgrade condition checks for "$isa < 3", which means
that we won't upgrade if we're targeting MIPS III.
This results in failures for the movcc-{1,2,3}.c and branch-cost-2.c tests
when the target is MIPS III.
This patch fixes the condition to include MIPS III.
Tested with mips-mti-elf.
Regards,
Toma Tabacu
gcc/testsuite/ChangeLog:
2016-11-07 Toma Tabacu <toma.tab...@imgtec.com>
* gcc.target/mips/mips.exp (mips-dg-options): Upgrade to MIPS IV if
using
(HAS_MOVN) with MIPS III.
diff --git a/gcc/testsuite/gcc.target/mips/mips.exp
b/gcc/testsuite/gcc.target/mips/mips.exp
index 39f44ff..e22d782 100644
--- a/gcc/testsuite/gcc.target/mips/mips.exp
+++ b/gcc/testsuite/gcc.target/mips/mips.exp
@@ -1129,7 +1129,7 @@ proc mips-dg-options { args } {
# We need MIPS IV or higher for:
#
#
- } elseif { $isa < 3
+ } elseif { $isa < 4
&& [mips_have_test_option_p options "HAS_MOVN"] } {
mips_make_test_option options "-mips4"
# We need MIPS III or higher for:
RE: [PATCH,testsuite] MIPS: Downgrade R6 to R5 if tests need branch-likely instructions.
> From: Matthew Fortune
> Sent: 04 November 2016 16:49
> To: Toma Tabacu; gcc-patches@gcc.gnu.org
> Cc: catherine_mo...@mentor.com
> Subject: RE: [PATCH,testsuite] MIPS: Downgrade R6 to R5 if tests need branch-
> likely instructions.
>
> Toma Tabacu <toma.tab...@imgtec.com> writes:
> > > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> > > ow...@gcc.gnu.org] On Behalf Of Toma Tabacu
> > > Sent: 04 November 2016 15:25
> > > To: Matthew Fortune; gcc-patches@gcc.gnu.org
> > > Cc: catherine_mo...@mentor.com
> > > Subject: RE: [PATCH,testsuite] MIPS: Downgrade R6 to R5 if tests need
> > > branch- likely instructions.
> > >
> > > > From: Matthew Fortune
> > > > Sent: 03 November 2016 13:07
> > > > To: Toma Tabacu; gcc-patches@gcc.gnu.org
> > > > Cc: catherine_mo...@mentor.com
> > > > Subject: RE: [PATCH,testsuite] MIPS: Downgrade R6 to R5 if tests
> > > > need branch-likely instructions.
> > > >
> > > > Toma Tabacu <toma.tab...@imgtec.com> writes:
> > > > > The gcc.target/mips/wrap-delay.c test was failing on mips-img-*
> > > > > toolchains because it was using -mbranch-likely with an R6 target,
> > > > > and
> > > > > branch- likely instructions were removed in R6.
> > > > >
> > > > > This patch makes the testsuite downgrade to R5 if the
> > > > > -mbranch-likely option is present and we're targeting R6.
> > > > >
> > > > > Tested with mips-img-elf and mips-img-linux-gnu.
> > > >
> > > > Hi Toma,
> > > >
> > > > Welcome to GCC development, thanks for your first patch. As you can
> > > > see from Catherine's reply the change looks good. I'll just cover
> > > > some housekeeping issues...
> > > >
> > > > > gcc/testsuite/
> > > > > * gcc.target/mips/mips.exp: Add check for -mbranch-likely
> > in
> > > > > condition for R5 downgrade.
> > > >
> > > > Changelogs are an art form which will take some getting used to.
> > > > This is almost there but needs to reference the function affected.
> > > >
> > > > * gcc.target/mips/mips.exp (mips-dg-options): Downgrade to R5
> > > > for -mbranch-likely and infer -mno-branch-likely for R6.
> > > >
> > > > I have extended the comment as well as there is an additional change
> > > > needed for this patch ideally.
> > > >
> > > > > diff --git a/gcc/testsuite/gcc.target/mips/mips.exp
> > > > > b/gcc/testsuite/gcc.target/mips/mips.exp
> > > > > index 7c24140..382d69c 100644
> > > > > --- a/gcc/testsuite/gcc.target/mips/mips.exp
> > > > > +++ b/gcc/testsuite/gcc.target/mips/mips.exp
> > > > > @@ -1176,7 +1176,8 @@ proc mips-dg-options { args } {
> > > > >|| [mips_have_test_option_p options
> > > > > "-mpaired- single"]
> > > > >|| [mips_have_test_option_p options "-
> > > > > mnan=legacy"]
> > > > >|| [mips_have_test_option_p options "-
> > > > > mabs=legacy"]
> > > > > - || [mips_have_test_option_p options
> > "!HAS_LSA"])
> > > > > } {
> > > > > + || [mips_have_test_option_p options
> > "!HAS_LSA"]
> > > > > + || [mips_have_test_option_p options
> > > > > + "-mbranch-
> > > > > likely"]) } {
> > > > > if { $gp_size == 32 } {
> > > > > mips_make_test_option options "-mips32r5"
> > > > > } else {
> > > >
> > > > Please can you make sure to retain the original patch formatting
> > > > when posting. I suspect you have copied this out of a putty session
> > > > or similar and have therefore lost the tabs.
> > > >
> > > > The extra change is that in the post-arch option processing we will
> > > > need to infer -mno-branch-likely for the $isa_rev > 5 case much like
> > > > we infer -
> > > > mnan=2008 and -mabs=2008. This is so that when running the testsuite
> > > > using
> > > > -mips32r5 or earlier, with -mbranch-likely as part of the
> > > > user-supplied test flags, then a test which is upgraded to
> > > > mips32r6 does not attempt to use -mbranch-likely.
> > > >
> > > > Hope that wasn't too cryptic!
> > > >
> > > > Thanks,
> > > > Matthew
> > >
> > > The updated patch below includes the improved ChangeLog comment,
> > > correct formatting, and the post-arch enforcing of -mno-branch-likely
> > for R6.
>
> Thanks, committed as r241850.
>
> Matthew
I've noticed that there is a typo in my surname in the ChangeLog entry (in the
name and in the email address).
Regards,
Toma Tabacu
RE: [PATCH,testsuite] MIPS: Downgrade R6 to R5 if tests need branch-likely instructions.
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Toma Tabacu
> Sent: 04 November 2016 15:25
> To: Matthew Fortune; gcc-patches@gcc.gnu.org
> Cc: catherine_mo...@mentor.com
> Subject: RE: [PATCH,testsuite] MIPS: Downgrade R6 to R5 if tests need branch-
> likely instructions.
>
> > From: Matthew Fortune
> > Sent: 03 November 2016 13:07
> > To: Toma Tabacu; gcc-patches@gcc.gnu.org
> > Cc: catherine_mo...@mentor.com
> > Subject: RE: [PATCH,testsuite] MIPS: Downgrade R6 to R5 if tests need
> > branch-likely instructions.
> >
> > Toma Tabacu <toma.tab...@imgtec.com> writes:
> > > The gcc.target/mips/wrap-delay.c test was failing on mips-img-*
> > > toolchains because it was using -mbranch-likely with an R6 target, and
> > > branch- likely instructions were removed in R6.
> > >
> > > This patch makes the testsuite downgrade to R5 if the -mbranch-likely
> > > option is present and we're targeting R6.
> > >
> > > Tested with mips-img-elf and mips-img-linux-gnu.
> >
> > Hi Toma,
> >
> > Welcome to GCC development, thanks for your first patch. As you can see
> > from Catherine's reply the change looks good. I'll just cover some
> > housekeeping issues...
> >
> > > gcc/testsuite/
> > > * gcc.target/mips/mips.exp: Add check for -mbranch-likely in
> > > condition for R5 downgrade.
> >
> > Changelogs are an art form which will take some getting used to. This is
> > almost there but needs to reference the function affected.
> >
> > * gcc.target/mips/mips.exp (mips-dg-options): Downgrade to R5
> > for -mbranch-likely and infer -mno-branch-likely for R6.
> >
> > I have extended the comment as well as there is an additional change
> > needed for this patch ideally.
> >
> > > diff --git a/gcc/testsuite/gcc.target/mips/mips.exp
> > > b/gcc/testsuite/gcc.target/mips/mips.exp
> > > index 7c24140..382d69c 100644
> > > --- a/gcc/testsuite/gcc.target/mips/mips.exp
> > > +++ b/gcc/testsuite/gcc.target/mips/mips.exp
> > > @@ -1176,7 +1176,8 @@ proc mips-dg-options { args } {
> > >|| [mips_have_test_option_p options "-mpaired-
> > > single"]
> > >|| [mips_have_test_option_p options "-
> > > mnan=legacy"]
> > >|| [mips_have_test_option_p options "-
> > > mabs=legacy"]
> > > - || [mips_have_test_option_p options "!HAS_LSA"])
> > > } {
> > > + || [mips_have_test_option_p options "!HAS_LSA"]
> > > + || [mips_have_test_option_p options "-mbranch-
> > > likely"]) } {
> > > if { $gp_size == 32 } {
> > > mips_make_test_option options "-mips32r5"
> > > } else {
> >
> > Please can you make sure to retain the original patch formatting when
> > posting. I suspect you have copied this out of a putty session or similar
> > and
> > have therefore lost the tabs.
> >
> > The extra change is that in the post-arch option processing we will need to
> > infer -mno-branch-likely for the $isa_rev > 5 case much like we infer -
> > mnan=2008 and -mabs=2008. This is so that when running the testsuite using
> > -mips32r5 or earlier, with -mbranch-likely as part of the user-supplied test
> > flags, then a test which is upgraded to
> > mips32r6 does not attempt to use -mbranch-likely.
> >
> > Hope that wasn't too cryptic!
> >
> > Thanks,
> > Matthew
>
> The updated patch below includes the improved ChangeLog comment, correct
> formatting, and the post-arch enforcing of -mno-branch-likely for R6.
>
> Regards,
> Toma
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/mips/mips.exp (mips-dg-options): Downgrade to R5
> for -mbranch-likely and infer -mno-branch-likely for R6.
>
> diff --git a/gcc/testsuite/gcc.target/mips/mips.exp
> b/gcc/testsuite/gcc.target/mips/mips.exp
> index 7c24140..6b7c46f 100644
> --- a/gcc/testsuite/gcc.target/mips/mips.exp
> +++ b/gcc/testsuite/gcc.target/mips/mips.exp
> @@ -1176,7 +1176,8 @@ proc mips-dg-options { args } {
> || [mips_have_test_option_p options "-mpaired-single"]
> || [mips_have_test_option_p options "-mnan=legacy"]
> || [mips_have_test_option_p options "-mabs=legacy"]
> -
RE: [PATCH,testsuite] MIPS: Downgrade R6 to R5 if tests need branch-likely instructions.
> From: Matthew Fortune
> Sent: 03 November 2016 13:07
> To: Toma Tabacu; gcc-patches@gcc.gnu.org
> Cc: catherine_mo...@mentor.com
> Subject: RE: [PATCH,testsuite] MIPS: Downgrade R6 to R5 if tests need
> branch-likely instructions.
>
> Toma Tabacu <toma.tab...@imgtec.com> writes:
> > The gcc.target/mips/wrap-delay.c test was failing on mips-img-*
> > toolchains because it was using -mbranch-likely with an R6 target, and
> > branch- likely instructions were removed in R6.
> >
> > This patch makes the testsuite downgrade to R5 if the -mbranch-likely
> > option is present and we're targeting R6.
> >
> > Tested with mips-img-elf and mips-img-linux-gnu.
>
> Hi Toma,
>
> Welcome to GCC development, thanks for your first patch. As you can see
> from Catherine's reply the change looks good. I'll just cover some
> housekeeping issues...
>
> > gcc/testsuite/
> > * gcc.target/mips/mips.exp: Add check for -mbranch-likely in
> > condition for R5 downgrade.
>
> Changelogs are an art form which will take some getting used to. This is
> almost there but needs to reference the function affected.
>
> * gcc.target/mips/mips.exp (mips-dg-options): Downgrade to R5
> for -mbranch-likely and infer -mno-branch-likely for R6.
>
> I have extended the comment as well as there is an additional change
> needed for this patch ideally.
>
> > diff --git a/gcc/testsuite/gcc.target/mips/mips.exp
> > b/gcc/testsuite/gcc.target/mips/mips.exp
> > index 7c24140..382d69c 100644
> > --- a/gcc/testsuite/gcc.target/mips/mips.exp
> > +++ b/gcc/testsuite/gcc.target/mips/mips.exp
> > @@ -1176,7 +1176,8 @@ proc mips-dg-options { args } {
> >|| [mips_have_test_option_p options "-mpaired-
> > single"]
> >|| [mips_have_test_option_p options "-
> > mnan=legacy"]
> >|| [mips_have_test_option_p options "-
> > mabs=legacy"]
> > - || [mips_have_test_option_p options "!HAS_LSA"])
> > } {
> > + || [mips_have_test_option_p options "!HAS_LSA"]
> > + || [mips_have_test_option_p options "-mbranch-
> > likely"]) } {
> > if { $gp_size == 32 } {
> > mips_make_test_option options "-mips32r5"
> > } else {
>
> Please can you make sure to retain the original patch formatting when
> posting. I suspect you have copied this out of a putty session or similar and
> have therefore lost the tabs.
>
> The extra change is that in the post-arch option processing we will need to
> infer -mno-branch-likely for the $isa_rev > 5 case much like we infer -
> mnan=2008 and -mabs=2008. This is so that when running the testsuite using
> -mips32r5 or earlier, with -mbranch-likely as part of the user-supplied test
> flags, then a test which is upgraded to
> mips32r6 does not attempt to use -mbranch-likely.
>
> Hope that wasn't too cryptic!
>
> Thanks,
> Matthew
The updated patch below includes the improved ChangeLog comment, correct
formatting, and the post-arch enforcing of -mno-branch-likely for R6.
Regards,
Toma
gcc/testsuite/ChangeLog:
* gcc.target/mips/mips.exp (mips-dg-options): Downgrade to R5
for -mbranch-likely and infer -mno-branch-likely for R6.
diff --git a/gcc/testsuite/gcc.target/mips/mips.exp
b/gcc/testsuite/gcc.target/mips/mips.exp
index 7c24140..6b7c46f 100644
--- a/gcc/testsuite/gcc.target/mips/mips.exp
+++ b/gcc/testsuite/gcc.target/mips/mips.exp
@@ -1176,7 +1176,8 @@ proc mips-dg-options { args } {
|| [mips_have_test_option_p options "-mpaired-single"]
|| [mips_have_test_option_p options "-mnan=legacy"]
|| [mips_have_test_option_p options "-mabs=legacy"]
- || [mips_have_test_option_p options "!HAS_LSA"]) } {
+ || [mips_have_test_option_p options "!HAS_LSA"])
+ || [mips_have_test_option_p options "-mbranch-likely"])
} {
if { $gp_size == 32 } {
mips_make_test_option options "-mips32r5"
} else {
@@ -1345,6 +1346,7 @@ proc mips-dg-options { args } {
mips_make_test_option options "-mno-paired-single"
mips_make_test_option options "-mnan=2008"
mips_make_test_option options "-mabs=2008"
+ mips_make_test_option options "-mno-branch-likely"
}
if { [regexp {^-march=(octeon|loongson)} $arch] } {
mips_make_test_option options "-mno-micromips"
RE: [PATCH] MIPS: If a test in the MIPS testsuite requires standard library support check the sysroot supports the required test options.
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Andrew Bennett
> Sent: 03 November 2016 11:33
> To: Matthew Fortune; 'Moore, Catherine'; 'gcc-patches@gcc.gnu.org'
> Subject: RE: [PATCH] MIPS: If a test in the MIPS testsuite requires standard
> library support check the sysroot supports the required test options.
>
> Ping.
>
>
> Regards,
>
>
>
> Andrew
>
Hi Andrew,
I believe the inline-memcpy-{1,2,3,4,5}.c tests also qualify for the
(REQUIRES_STDLIB) option.
Regards,
Toma Tabacu
> > -Original Message-
> > From: Andrew Bennett
> > Sent: 28 August 2015 16:50
> > To: Matthew Fortune; Moore, Catherine; gcc-patches@gcc.gnu.org
> > Subject: RE: [PATCH] MIPS: If a test in the MIPS testsuite requires
> > standard library support check the sysroot supports the required test
> options.
> >
> > > I had some comments on this that I hadn't got round to posting. The
> > > fix in this patch is not general enough as the missing header
> > > problem comes in two (related) forms:
> > >
> > > 1) Using the new MTI and IMG sysroot layout we can end up with GCC
> looking
> > >for headers in a sysroot that simply does not exist. The current patch
> > >handles this.
> > > 2) Using any sysroot layout (i.e. a simple mips-linux-gnu) it is possible
> > >for the stdlib.h header to be found but the ABI dependent gnu-stubs
> > >header may not be installed depending on soft/hard nan1985/nan2008.
> > >
> > > The test for stdlib.h needs to therefore verify that preprocessing
> > > succeeds rather than just testing for an error relating to stdlib.h.
> > > This could be done by adding a further option to mips_preprocess to
> > > indicate the processor output should go to a file and that the
> > > caller wants the messages emitted by the compiler instead.
> > >
> > > A second issue is that you have added (REQUIRES_STDLIB) to too many
> tests.
> > > You only need to add it to tests that request a compiler option (via
> > > dg-options) that could potentially lead to forcing soft/hard
> > > nan1985/nan2008 directly or indirectly. So -mips32r6 implies nan2008
> > > so you need it -
> > mips32r5
> > > implies nan1985 so you need it. There are at least two tests which
> > > don't need the option but you need to check them all so we don't run
> > > the check needlessly.
> >
> > The updated patch and ChangeLog that addresses Matthew's comments is
> below.
> >
> > Ok to commit?
> >
> > Regards,
> >
> >
> > Andrew
> >
> >
> > testsuite/
> >
> > * gcc.target/mips/loongson-simd.c (dg-options): Add
> > (REQUIRES_STDLIB).
> > * gcc.target/mips/loongson-shift-count-truncated-1.c: Ditto
> > * gcc.target/mips/mips-3d-1.c: Ditto
> > * gcc.target/mips/mips-3d-2.c: Ditto
> > * gcc.target/mips/mips-3d-3.c: Ditto
> > * gcc.target/mips/mips-3d-4.c: Ditto
> > * gcc.target/mips/mips-3d-5.c: Ditto
> > * gcc.target/mips/mips-3d-6.c: Ditto
> > * gcc.target/mips/mips-3d-7.c: Ditto
> > * gcc.target/mips/mips-3d-8.c: Ditto
> > * gcc.target/mips/mips-3d-9.c: Ditto
> > * gcc.target/mips/mips-ps-1.c: Ditto
> > * gcc.target/mips/mips-ps-2.c: Ditto
> > * gcc.target/mips/mips-ps-3.c: Ditto
> > * gcc.target/mips/mips-ps-4.c: Ditto
> > * gcc.target/mips/mips-ps-6.c: Ditto
> > * gcc.target/mips/mips16-attributes.c: Ditto
> > * gcc.target/mips/mips32-dsp-run.c: Ditto
> > * gcc.target/mips/mips32-dsp.c: Ditto
> > * gcc.target/mips/save-restore-1.c: Ditto
> > * gcc.target/mips/mips.exp (mips_option_groups): Add stdlib.
> > (mips_preprocess): Add ignore_output argument that when set
> > will not return the pre-processed output.
> > (mips_arch_info): Update arguments for the call to
> > mips_preprocess.
> > (mips-dg-init): Ditto.
> > (mips-dg-options): Check if a test having test option
> > (REQUIRES_STDLIB) has the required sysroot support for
> > the current test options.
> >
> >
> >
> > diff --git
> > a/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c
> > b/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c
> > index f57a18c..baed48c 100644
> > --- a/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c
> > +++ b/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c
>
