[PATCH v5] RISC-V: Rewrite some instructions using ASM targethook

[Jun Sha (Joshua)]

There are some xtheadvector instructions that differ from RVV1.0
apart from simply adding "th." prefix. For example, RVV1.0
load/store instructions will have SEW while xtheadvector not;
RVV1.0 will have "o" for indexed-ordered store instructions while
xtheadvecotr not; xtheadvector and RVV1.0 have different
vnsrl/vnsra/vfncvt suffix (vv/vx/vi vs wv/wx/wi).

To address this issue without duplicating patterns, we use ASM
targethook to rewrite the whole string of the instructions. We
identify different instructions from the corresponding attribute.

gcc/ChangeLog:

* config/riscv/thead.cc
(th_asm_output_opcode): Rewrite some instructions.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config/riscv/thead.cc | 215 +-
 1 file changed, 213 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc
index dc3aed3904d..fb088ebff02 100644
--- a/gcc/config/riscv/thead.cc
+++ b/gcc/config/riscv/thead.cc
@@ -27,6 +27,7 @@
 #include "backend.h"
 #include "tree.h"
 #include "rtl.h"
+#include "insn-attr.h"
 #include "explow.h"
 #include "memmodel.h"
 #include "emit-rtl.h"
@@ -890,8 +891,218 @@ th_asm_output_opcode (FILE *asm_out_file, const char *p)
 {
   /* We need to add th. prefix to all the xtheadvector
  instructions here.*/
-  if (current_output_insn != NULL && p[0] == 'v')
-fputs ("th.", asm_out_file);
+  if (current_output_insn != NULL)
+{
+  if (get_attr_type (current_output_insn) == TYPE_VLDE ||
+ get_attr_type (current_output_insn) == TYPE_VSTE ||
+ get_attr_type (current_output_insn) == TYPE_VLDFF)
+   {
+ if (strstr (p, "e8") || strstr (p, "e16") ||
+ strstr (p, "e32") || strstr (p, "e64"))
+   {
+ get_attr_type (current_output_insn) == TYPE_VSTE
+ ? fputs ("th.vse", asm_out_file)
+ : fputs ("th.vle", asm_out_file);
+ if (strstr (p, "e8"))
+   return p+4;
+ else
+   return p+5;
+   }
+   }
+
+  if (get_attr_type (current_output_insn) == TYPE_VLDS ||
+ get_attr_type (current_output_insn) == TYPE_VSTS)
+   {
+ if (strstr (p, "vle8") || strstr (p, "vse8") ||
+ strstr (p, "vle16") || strstr (p, "vse16") ||
+ strstr (p, "vle32") || strstr (p, "vse32") ||
+ strstr (p, "vle64") || strstr (p, "vse64"))
+   {
+ get_attr_type (current_output_insn) == TYPE_VSTS
+ ? fputs ("th.vse", asm_out_file)
+ : fputs ("th.vle", asm_out_file);
+ if (strstr (p, "e8"))
+   return p+4;
+ else
+   return p+5;
+   }
+ else if (strstr (p, "vlse8") || strstr (p, "vsse8") ||
+  strstr (p, "vlse16") || strstr (p, "vsse16") ||
+  strstr (p, "vlse32") || strstr (p, "vsse32") ||
+  strstr (p, "vlse64") || strstr (p, "vsse64"))
+   {
+ get_attr_type (current_output_insn) == TYPE_VSTS
+ ? fputs ("th.vsse", asm_out_file)
+ : fputs ("th.vlse", asm_out_file);
+ if (strstr (p, "e8"))
+   return p+5;
+ else
+   return p+6;
+   }
+   }
+
+  if (get_attr_type (current_output_insn) == TYPE_VLDUX ||
+ get_attr_type (current_output_insn) == TYPE_VLDOX)
+   {
+ if (strstr (p, "ei"))
+   {
+ fputs ("th.vlxe", asm_out_file);
+ if (strstr (p, "ei8"))
+   return p+7;
+ else
+   return p+8;
+   }
+   }
+
+  if (get_attr_type (current_output_insn) == TYPE_VSTUX ||
+ get_attr_type (current_output_insn) == TYPE_VSTOX)
+   {
+ if (strstr (p, "ei"))
+   {
+ get_attr_type (current_output_insn) == TYPE_VSTUX
+   ? fputs ("th.vsuxe", asm_out_file)
+   : fputs ("th.vsxe", asm_out_file);
+ if (strstr (p, "ei8"))
+   return p+7;
+ else
+   return p+8;
+   }
+   }
+
+  if (get_attr_type (current_output_insn) == TYPE_VLSEGDE ||
+ get_attr_type (current_output_insn) == TYPE_VSSEGTE ||
+ get_attr_type (current_output_insn) == TYPE_VLSEGDFF)
+   {
+ get_attr_type (current_output_insn) == TYPE_VSSEGTE
+   ? fputs ("th.vsseg", asm_out_file)
+   : fputs ("th.vlseg", asm_out_file);
+ asm_fprintf (asm_out_file, "%c", p[5]);
+ fputs ("e", asm_out_file);
+ if (strstr (p, "e8"))
+   return p+8;
+ else
+   return p+9;
+   }
+
+  if (get_attr_type 

[PATCH v6] RISC-V: Fix register overlap issue for some xtheadvector instructions

[Jun Sha (Joshua)]

For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions
and floating-point compare instructions, an illegal instruction
exception will be raised if the destination vector register overlaps
a source vector register group.

To handle this issue, we add an attribute "spec_restriction" to disable
some alternatives for xtheadvector.

gcc/ChangeLog:

* config/riscv/riscv.md (none,thv,rvv):
(no,yes): Add an attribute to disable alternative
for xtheadvector or RVV1.0.
* config/riscv/vector.md: 
Disable alternatives that destination register overlaps
source register group for xtheadvector.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config/riscv/riscv.md  |  22 +++
 gcc/config/riscv/vector.md | 314 +
 2 files changed, 202 insertions(+), 134 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 84212430dc0..23fc32d5cb2 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -579,6 +579,25 @@
 ]
(const_string "yes")))
 
+;; This attribute marks the alternatives not matching the constraints
+;; described in spec as disabled.
+(define_attr "spec_restriction" "none,thv,rvv"
+  (const_string "none"))
+
+(define_attr "spec_restriction_disabled" "no,yes"
+  (cond [(eq_attr "spec_restriction" "none")
+(const_string "no")
+
+(and (eq_attr "spec_restriction" "thv")
+ (match_test "TARGET_XTHEADVECTOR"))
+(const_string "yes")
+
+(and (eq_attr "spec_restriction" "rvv")
+ (match_test "TARGET_VECTOR && !TARGET_XTHEADVECTOR"))
+(const_string "yes")
+   ]
+   (const_string "no")))
+
 ;; Attribute to control enable or disable instructions.
 (define_attr "enabled" "no,yes"
   (cond [
@@ -590,6 +609,9 @@
 
 (eq_attr "group_overlap_valid" "no")
 (const_string "no")
+
+(eq_attr "spec_restriction_disabled" "yes")
+(const_string "no")
   ]
   (const_string "yes")))
 
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 3eb6daafbc2..c79416cf0d3 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -3260,7 +3260,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "spec_restriction" "thv,none,none")])
 
 (define_insn "@pred_msbc"
   [(set (match_operand: 0 "register_operand""=vr, vr, ")
@@ -3279,7 +3280,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "spec_restriction" "thv,thv,none")])
 
 (define_insn "@pred_madc_scalar"
   [(set (match_operand: 0 "register_operand" "=vr, ")
@@ -3299,7 +3301,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "spec_restriction" "thv,none")])
 
 (define_insn "@pred_msbc_scalar"
   [(set (match_operand: 0 "register_operand" "=vr, ")
@@ -3319,7 +3322,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "spec_restriction" "thv,none")])
 
 (define_expand "@pred_madc_scalar"
   [(set (match_operand: 0 "register_operand")
@@ -3368,7 +3372,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "spec_restriction" "thv,none")])
 
 (define_insn "*pred_madc_extended_scalar"
   [(set (match_operand: 0 "register_operand" "=vr, ")
@@ -3389,7 +3394,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "spec_restriction" "thv,none")])
 
 (define_expand "@pred_msbc_scalar"
   [(set (match_operand: 0 "register_operand")
@@ -3438,7 +3444,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "spec_restriction" "thv,none")])
 
 (define_insn "*pred_msbc_extended_scalar"
   [(set (match_operand: 0 "register_operand"  "=vr, ")
@@ -3459,7 +3466,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "spec_restriction" "thv,none")])
 
 (define_insn "@pred_madc_overflow"
   [(set 

[PATCH v6] RISC-V: Add support for xtheadvector-specific intrinsics.

[Jun Sha (Joshua)]

This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(class th_extract): Define new builtin bases.
(BASE): Define new builtin bases.
* config/riscv/riscv-vector-builtins-bases.h:
Define new builtin class.
* config/riscv/riscv-vector-builtins-shapes.cc
(struct th_loadstore_width_def): Define new builtin shapes.
(struct th_indexed_loadstore_width_def):
Define new builtin shapes.
(struct th_extract_def): Define new builtin shapes.
(SHAPE): Define new builtin shapes.
* config/riscv/riscv-vector-builtins-shapes.h:
Define new builtin shapes.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
* config/riscv/riscv-vector-builtins.h 
(enum required_ext): Add new XTheadVector member.
(struct function_group_info): Likewise.
* config/riscv/t-riscv: 
Add thead-vector-builtins-functions.def
* config/riscv/thead-vector.md
(@pred_mov_width): Add new patterns.
(*pred_mov_width): Likewise.
(@pred_store_width): Likewise.
(@pred_strided_load_width): Likewise.
(@pred_strided_store_width): Likewise.
(@pred_indexed_load_width): Likewise.
(@pred_th_extract): Likewise.
(*pred_th_extract): Likewise.
* config/riscv/thead-vector-builtins-functions.def: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c: New test.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 .../riscv/riscv-vector-builtins-bases.cc  | 139 ++
 .../riscv/riscv-vector-builtins-bases.h   |  31 +++
 .../riscv/riscv-vector-builtins-shapes.cc | 160 +++
 .../riscv/riscv-vector-builtins-shapes.h  |   3 +
 gcc/config/riscv/riscv-vector-builtins.cc |  70 +
 gcc/config/riscv/riscv-vector-builtins.h  |   3 +
 gcc/config/riscv/t-riscv  |   1 +
 .../riscv/thead-vector-builtins-functions.def |  39 +++
 gcc/config/riscv/thead-vector.md  | 250 ++
 .../riscv/rvv/xtheadvector/vlb-vsb.c  |  68 +
 .../riscv/rvv/xtheadvector/vlbu-vsb.c |  68 +
 .../riscv/rvv/xtheadvector/vlh-vsh.c  |  68 +
 .../riscv/rvv/xtheadvector/vlhu-vsh.c |  68 +
 .../riscv/rvv/xtheadvector/vlw-vsw.c  |  68 +
 .../riscv/rvv/xtheadvector/vlwu-vsw.c |  68 +
 15 files changed, 1104 insertions(+)
 create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 1aa6e3c6665..b6f6e4ff37e 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2141,6 +2141,83 @@ public:
   }
 };
 
+/* Implements
+ * th.vl(b/h/w)[u].v/th.vs(b/h/w)[u].v/th.vls(b/h/w)[u].v/th.vss(b/h/w)[u].v/
+ * th.vlx(b/h/w)[u].v/th.vs[u]x(b/h/w).v
+ * codegen.  */
+template
+class th_loadstore_width : public function_base
+{
+public:
+  bool apply_tail_policy_p () const override { return !STORE_P; }
+  bool apply_mask_policy_p () const override { return !STORE_P; }
+
+  unsigned int call_properties (const function_instance &) const override
+  {
+if (STORE_P)
+  return CP_WRITE_MEMORY;
+else
+  return CP_READ_MEMORY;
+  }
+
+  bool can_be_overloaded_p (enum predication_type_index pred) const override
+  {
+if (STORE_P || LST_TYPE == LST_INDEXED)
+  return true;
+return pred != PRED_TYPE_none;
+  }
+
+  rtx expand (function_expander ) const override
+  {
+gcc_assert (TARGET_XTHEADVECTOR);
+if (LST_TYPE == LST_INDEXED)
+  {
+   if (STORE_P)
+ return e.use_exact_insn (
+   code_for_pred_indexed_store_width (UNSPEC, UNSPEC,
+  e.vector_mode ()));
+  

[PATCH v6] RISC-V: Handle differences between XTheadvector and Vector

[Jun Sha (Joshua)]

This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 

For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r.

gcc/ChangeLog:

* config.gcc:  Add files for XTheadVector intrinsics.
* config/riscv/autovec.md: Guard XTheadVector.
* config/riscv/predicates.md: Disable immediate vl
for XTheadVector.
* config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
Add pragma for XTheadVector.
* config/riscv/riscv-string.cc (riscv_expand_block_move):
Guard XTheadVector.
* config/riscv/riscv-v.cc (vls_mode_valid_p): 
Avoid autovec.
* config/riscv/riscv-vector-builtins-bases.cc:
Do not normalize vsetvl instructions for XTheadVector.
* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
(build_one): New check type function.
* config/riscv/riscv-vector-switch.def (ENTRY):
Disable fractional mode for the XTheadVector extension.
(TUPLE_ENTRY): Likewise.
* config/riscv/riscv.cc (riscv_v_adjust_bytesize):
Guard XTheadVector.
(riscv_preferred_simd_mode): Likewsie.
(riscv_autovectorize_vector_modes): Likewise.
(riscv_vector_mode_supported_any_target_p): Likewise.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
* config/riscv/thead.cc (th_asm_output_opcode):
Rewrite vsetvl instructions.
* config/riscv/vector.md: 
Include thead-vector.md and change fractional LMUL
into 1 for vbool.
* config/riscv/riscv_th_vector.h: New file.
* config/riscv/thead-vector.md: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector.
* gcc.target/riscv/rvv/base/abi-1.c: Exclude XTheadVector.
* lib/target-supports.exp: Add target for XTheadVector.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/autovec.md   |   2 +-
 gcc/config/riscv/predicates.md|   4 +-
 gcc/config/riscv/riscv-c.cc   |   3 +-
 gcc/config/riscv/riscv-string.cc  |   3 +-
 gcc/config/riscv/riscv-v.cc   |   2 +-
 .../riscv/riscv-vector-builtins-bases.cc  |  48 --
 .../riscv/riscv-vector-builtins-shapes.cc |  23 +++
 gcc/config/riscv/riscv-vector-switch.def  | 150 +-
 gcc/config/riscv/riscv.cc |  20 ++-
 gcc/config/riscv/riscv_th_vector.h|  49 ++
 gcc/config/riscv/thead-vector.md  | 102 
 gcc/config/riscv/thead.cc |  23 ++-
 gcc/config/riscv/vector.md|  43 -
 .../gcc.target/riscv/rvv/base/abi-1.c |   2 +-
 .../gcc.target/riscv/rvv/base/pragma-1.c  |   2 +-
 gcc/testsuite/lib/target-supports.exp |  12 ++
 17 files changed, 380 insertions(+), 110 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_th_vector.h
 create mode 100644 gcc/config/riscv/thead-vector.md

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 7e583390024..047e4c02cf4 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,7 +549,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_th_vector.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 775eaa825b0..0477781cabe 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2579,7 +2579,7 @@
   [(match_operand  0 "register_operand")
(match_operand  1 "memory_operand")
(match_operand:ANYI 2 "const_int_operand")]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   {
 riscv_vector::expand_rawmemchr(mode, operands[0], operands[1],
   operands[2]);
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index b1a79cae50a..0337da88284 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -428,7 +428,9 @@
 

[PATCH v5] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

[Jun Sha (Joshua)]

This patch adds th. prefix to all XTheadVector instructions by
implementing new assembly output functions. We only check the
prefix is 'v', so that no extra attribute is needed.

gcc/ChangeLog:

* config/riscv/riscv-protos.h (riscv_asm_output_opcode):
Add new function to add assembler insn code prefix/suffix.
(th_asm_output_opcode):
Add Thead function to add assembler insn code prefix/suffix.
* config/riscv/riscv.cc (riscv_asm_output_opcode): 
Implement function to add assembler insn code prefix/suffix.
* config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
Add new function to add assembler insn code prefix/suffix.
* config/riscv/thead.cc (th_asm_output_opcode):
Implement Thead function to add assembler insn code
prefix/suffix.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/prefix.c: New test.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config/riscv/riscv-protos.h |  2 ++
 gcc/config/riscv/riscv.cc   | 11 +++
 gcc/config/riscv/riscv.h|  4 
 gcc/config/riscv/thead.cc   | 13 +
 .../gcc.target/riscv/rvv/xtheadvector/prefix.c  | 12 
 5 files changed, 42 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 31049ef7523..71724dabdb5 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -102,6 +102,7 @@ struct riscv_address_info {
 };
 
 /* Routines implemented in riscv.cc.  */
+extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
 extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
 extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
 extern int riscv_float_const_rtx_index_for_fli (rtx);
@@ -717,6 +718,7 @@ extern void th_mempair_prepare_save_restore_operands 
(rtx[4], bool,
  int, HOST_WIDE_INT,
  int, HOST_WIDE_INT);
 extern void th_mempair_save_restore_regs (rtx[4], bool, machine_mode);
+extern const char *th_asm_output_opcode (FILE *asm_out_file, const char *p);
 #ifdef RTX_CODE
 extern const char*
 th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0d1cbc5cb5f..51878797287 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5636,6 +5636,17 @@ riscv_get_v_regno_alignment (machine_mode mode)
   return lmul;
 }
 
+/* Define ASM_OUTPUT_OPCODE to do anything special before
+   emitting an opcode.  */
+const char *
+riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
+{
+  if (TARGET_XTHEADVECTOR)
+return th_asm_output_opcode (asm_out_file, p);
+
+  return p;
+}
+
 /* Implement TARGET_PRINT_OPERAND.  The RISCV-specific operand codes are:
 
'h' Print the high-part relocation associated with OP, after stripping
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 6df9ec73c5e..c33361a254d 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -826,6 +826,10 @@ extern enum riscv_cc get_riscv_cc (const rtx use);
   asm_fprintf ((FILE), "%U%s", (NAME));\
   } while (0)
 
+#undef ASM_OUTPUT_OPCODE
+#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
+  (PTR) = riscv_asm_output_opcode(STREAM, PTR)
+
 #define JUMP_TABLES_IN_TEXT_SECTION 0
 #define CASE_VECTOR_MODE SImode
 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc
index 20353995931..dc3aed3904d 100644
--- a/gcc/config/riscv/thead.cc
+++ b/gcc/config/riscv/thead.cc
@@ -883,6 +883,19 @@ th_output_move (rtx dest, rtx src)
   return NULL;
 }
 
+/* Define ASM_OUTPUT_OPCODE to do anything special before
+   emitting an opcode.  */
+const char *
+th_asm_output_opcode (FILE *asm_out_file, const char *p)
+{
+  /* We need to add th. prefix to all the xtheadvector
+ instructions here.*/
+  if (current_output_insn != NULL && p[0] == 'v')
+fputs ("th.", asm_out_file);
+
+  return p;
+}
+
 /* Implement TARGET_PRINT_OPERAND_ADDRESS for XTheadMemIdx.  */
 
 bool
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
new file mode 100644
index 000..eee727ef6b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadvector -mabi=ilp32 -O0" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+prefix (vint32m1_t vx, vint32m1_t vy, size_t vl)
+{
+  return __riscv_vadd_vv_i32m1 (vx, vy, vl);
+}
+
+/* { dg-final { scan-assembler {\mth\.v\M} } } 

[PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0

[Jun Sha (Joshua)]

This patch is to introduce basic XTheadVector support
(march string parsing and a test for __riscv_xtheadvector)
according to https://github.com/T-head-Semi/thead-extension-spec/

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_subset_list::parse): Add new vendor extension.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
Add test marco.
* config/riscv/riscv.opt:  Add new mask.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-__riscv_th_v_intrinsic.c: New test.
* gcc.target/riscv/rvv/xtheadvector.c: New test.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/common/config/riscv/riscv-common.cc   | 23 +++
 gcc/config/riscv/riscv-c.cc   |  8 +--
 gcc/config/riscv/riscv.opt|  2 ++
 .../riscv/predef-__riscv_th_v_intrinsic.c | 11 +
 .../gcc.target/riscv/rvv/xtheadvector.c   | 13 +++
 5 files changed, 55 insertions(+), 2 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 0301d170a41..449722070d4 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -368,6 +368,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadvector", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
 
@@ -1251,6 +1252,15 @@ riscv_subset_list::check_conflict_ext ()
   if (lookup ("zcmp"))
error_at (m_loc, "%<-march=%s%>: zcd conflicts with zcmp", m_arch);
 }
+
+  if ((lookup ("v") || lookup ("zve32x")
+|| lookup ("zve64x") || lookup ("zve32f")
+|| lookup ("zve64f") || lookup ("zve64d")
+|| lookup ("zvl32b") || lookup ("zvl64b")
+|| lookup ("zvl128b") || lookup ("zvfh"))
+&& lookup ("xtheadvector"))
+error_at (m_loc, "%<-march=%s%>: xtheadvector conflicts with vector "
+  "extension or its sub-extensions", m_arch);
 }
 
 /* Parsing function for multi-letter extensions.
@@ -1743,6 +1753,19 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"xtheadmemidx",  _options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
   {"xtheadmempair", _options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
   {"xtheadsync",_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
+  {"xtheadvector",  _options::x_riscv_xthead_subext, MASK_XTHEADVECTOR},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_32},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_64},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_32},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_64},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_16},
+  {"xtheadvector",  _options::x_riscv_zvl_flags, MASK_ZVL32B},
+  {"xtheadvector",  _options::x_riscv_zvl_flags, MASK_ZVL64B},
+  {"xtheadvector",  _options::x_riscv_zvl_flags, MASK_ZVL128B},
+  {"xtheadvector",  _options::x_riscv_zf_subext, MASK_ZVFHMIN},
+  {"xtheadvector",  _options::x_riscv_zf_subext, MASK_ZVFH},
+  {"xtheadvector",  _options::x_target_flags, MASK_FULL_V},
+  {"xtheadvector",  _options::x_target_flags, MASK_VECTOR},
 
   {"xventanacondops", _options::x_riscv_xventana_subext, 
MASK_XVENTANACONDOPS},
 
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index ba60cd8b555..422ddc2c308 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -142,6 +142,10 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
 riscv_ext_version_value (0, 11));
 }
 
+   if (TARGET_XTHEADVECTOR)
+ builtin_define_with_int_value ("__riscv_th_v_intrinsic",
+riscv_ext_version_value (0, 11));
+
   /* Define architecture extension test macros.  */
   builtin_define_with_int_value ("__riscv_arch_test", 1);
 
@@ -195,8 +199,8 @@ riscv_pragma_intrinsic (cpp_reader *)
 {
   if (!TARGET_VECTOR)
{
- error ("%<#pragma riscv intrinsic%> option %qs needs 'V' extension "
-"enabled",
+ error ("%<#pragma riscv intrinsic%> option %qs needs 'V' or "
+"'XTHEADVECTOR' extension enabled",
 name);
  return;
}
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 44ed6d69da2..bb18a22b693 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -452,6 +452,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext)
 
 Mask(XTHEADSYNC)

[PATCH v5] RISC-V: Support XTheadVector extension

[Jun Sha (Joshua)]

This patch series presents gcc implementation of the XTheadVector
extension [1].

[1] https://github.com/T-head-Semi/thead-extension-spec/

For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in order not to
generate instructions that xtheadvector does not support,
causing 10 changes in vector.md.

For the th. prefix issue, we use current_output_insn and
the ASM_OUTPUT_OPCODE hook instead of directly modifying
patterns in vector.md.

We have run the GCC test suite and can confirm that there
are no regressions.

Furthermore, we have run the tests in 
https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples, 
and all the tests passed.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 

[PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0
[PATCH v5] RISC-V: Adds the prefix "th." for the instructions of XTheadVector
[PATCH v6] RISC-V: Handle differences between XTheadvector and Vector
[PATCH v6] RISC-V: Add support for xtheadvector-specific intrinsics
[PATCH v6] RISC-V: Fix register overlap issue for some xtheadvector instructions
[PATCH v5] RISC-V: Rewrite some instructions using ASM targethook

Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[joshua]

Is the patch with !TARGET_XTHEADVECTOR for sext/zext
patterns removed OK to commit?
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642657.html




--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 18:56
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


Yes.


juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2024-01-11 18:54
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

Do you mean removing TARGET_XTHEADVECTOR for sext/zext patterns
and then resending the  "RISC-V: Handle differences between XTheadvector
and Vector" patch?
 
 
 
 
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 17:57
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主　题：Re: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
 
LGTM. Could you resend the patch "RISC-V: Handle differences between 
XTheadvector and Vector
 
 
Thanks.
juzhe.zh...@rivai.ai
 
 
From: Jun Sha (Joshua)
Date: 2024-01-11 17:52
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.
 
gcc/ChangeLog:
 
* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(class th_extract): Define new builtin bases.
(BASE): Define new builtin bases.
* config/riscv/riscv-vector-builtins-bases.h:
Define new builtin class.
* config/riscv/riscv-vector-builtins-shapes.cc
(struct th_loadstore_width_def): Define new builtin shapes.
(struct th_indexed_loadstore_width_def):
Define new builtin shapes.
(struct th_extract_def): Define new builtin shapes.
(SHAPE): Define new builtin shapes.
* config/riscv/riscv-vector-builtins-shapes.h:
Define new builtin shapes.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
* config/riscv/riscv-vector-builtins.h (enum required_ext):
(struct function_group_info):
* config/riscv/t-riscv: Add thead-vector-builtins-functions.def
* config/riscv/thead-vector.md
(@pred_mov_width): Add new patterns.
(*pred_mov_width): Likewise.
(@pred_store_width): Likewise.
(@pred_strided_load_width): Likewise.
(@pred_strided_store_width): Likewise.
(@pred_indexed_load_width): Likewise.
(@pred_indexed_store_width):
(@pred_th_extract): Likewise.
(*pred_th_extract): Likewise.
* config/riscv/thead-vector-builtins-functions.def: New file.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c: New test.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 .../riscv/riscv-vector-builtins-bases.cc  | 139 ++
 .../riscv/riscv-vector-builtins-bases.h   |  31 +++
 .../riscv/riscv-vector-builtins-shapes.cc | 160 +++
 .../riscv/riscv-vector-builtins-shapes.h  |   3 +
 gcc/config/riscv/riscv-vector-builtins.cc |  70 +
 gcc/config/riscv/riscv-vector-builtins.h  |   3 +
 gcc/config/riscv/t-riscv  |   1 +
 .../riscv/thead-vector-builtins-functions.def |  39 +++
 gcc/config/riscv/thead-vector.md  | 250 ++
 .../riscv/rvv/xtheadvector/vlb-vsb.c  |  68 +
 .../riscv/rvv/xtheadvector/vlbu-vsb.c |  68 +
 .../riscv/rvv/xtheadvector/vlh-vsh.c  |  68 +
 .../riscv/rvv/xtheadvector/vlhu-vsh.c |  68 +
 .../riscv/rvv/xtheadvector/vlw-vsw.c  |  68 +
 .../riscv/rvv/xtheadvector/vlwu-vsw.c |  68 +
 15 files changed, 1104 insertions(+)
 create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/

Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[joshua]

Perhaps not. I suggest that is the limitation of rvv 0.7.1.
I will consult my colleagues who are familiar with using rvv 0.7.1 tomorrow.






--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 20:33
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


Does theadvector has extension instructions ?
Show me the pattern.


juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2024-01-11 20:31
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

Yes.
 
 
(insn 14 13 15 2 (set (reg:QI 147)
        (const_int 1 [0x1]))   {*movqi_internal}
 
     (nil))
 
 
 
 
 
 
 
 
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发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 20:28
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
 
(vec_duplicate:RVVM1QI (reg:QI 147
 
 
Find the RTL define pseudo 147 to me.
 
 
I guess it is 1.
juzhe.zh...@rivai.ai
 
 
发件人： joshua
发送时间： 2024-01-11 20:18
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
No, we have debugged and the code won't enter this autovec pattern.
The root cause is CSE, in a very early pass.
 
What I sent to you just now is the dump result which shows the difference.
 
 
 
 
 
 
 
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发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 20:13
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
 
I guess it is because of patterns from autovectorization pattern:
 
 
;; Use define_insn_and_split to define vsext.vf2/vzext.vf2 will help
;; to combine instructions as below:
;;   vsext.vf2 + vsext.vf2 + vadd.vv ==> vwadd.vv
(define_insn_and_split "2"
  [(set (match_operand:VWEXTI 0 "register_operand" "=")
    (any_extend:VWEXTI
     (match_operand: 1 "register_operand" "vr")))]
  "TARGET_VECTOR && can_create_pseudo_p ()"
  "#"
  "&& 1"
  [(const_int 0)]
{
  insn_code icode = code_for_pred_vf2 (, mode);
  riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
  DONE;
}
  [(set_attr "type" "vext")
   (set_attr "mode" "")])
 
 
 
juzhe.zh...@rivai.ai
 
 
发件人： joshua
发送时间： 2024-01-11 20:05
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
without CSE:
(insn 16 15 17 2 (set (reg/v:RVVM2HI 137 [ output_var_0 ])
    (if_then_else:RVVM2HI (unspec:RVVMF8BI [
    (const_vector:RVVMF8BI repeat [
    (const_int 1 [0x1])
    ])
    (reg:DI 146)
    (const_int 2 [0x2]) repeated x2
    (const_int 0 [0])
    (reg:SI 66 vl)
    (reg:SI 67 vtype)
    ] UNSPEC_VPREDICATE)
    (mult:RVVM2HI (sign_extend:RVVM2HI (reg/v:RVVM1QI 136 [ op1 ]))
    (sign_extend:RVVM2HI (vec_duplicate:RVVM1QI (reg:QI 147
    (unspec:RVVM2HI [
    (reg:SI 0 zero)
    ] UNSPEC_VUNDEF))) {pred_dual_widen_mulsrvvm2hi_scalar}
 
with CSE:
(insn 16 15 17 2 (set (reg/v:RVVM2HI 137 [ output_var_0 ])
    (if_then_else:RVVM2HI (unspec:RVVMF8BI [
    (const_vector:RVVMF8BI repeat [
    (const_int 1 [0x1])
    ])
    (reg:DI 146)
    (const_int 2 [0x2]) repeated x2
    (const_int 0 [0])
    (reg:SI 66 vl)
    (reg:SI 67 vtype)
    ] UNSPEC_VPREDICATE)
    (sign_extend:RVVM2HI (reg/v:RVVM1QI 136 [ op1 ]))
    (unspec:RVVM2HI [
    (reg:SI 0 zero)
    ] UNSPEC_VUNDEF))) {pred_extendrvvm2hi_vf2}
 
 
 
 
 
 
--

Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[joshua]

Yes.


(insn 14 13 15 2 (set (reg:QI 147)
        (const_int 1 [0x1]))   {*movqi_internal}

     (nil))








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发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 20:28
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
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jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


(vec_duplicate:RVVM1QI (reg:QI 147


Find the RTL define pseudo 147 to me.


I guess it is 1.
juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2024-01-11 20:18
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

No, we have debugged and the code won't enter this autovec pattern.
The root cause is CSE, in a very early pass.
 
What I sent to you just now is the dump result which shows the difference.
 
 
 
 
 
 
 
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发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 20:13
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
 
I guess it is because of patterns from autovectorization pattern:
 
 
;; Use define_insn_and_split to define vsext.vf2/vzext.vf2 will help
;; to combine instructions as below:
;;   vsext.vf2 + vsext.vf2 + vadd.vv ==> vwadd.vv
(define_insn_and_split "2"
  [(set (match_operand:VWEXTI 0 "register_operand" "=")
    (any_extend:VWEXTI
     (match_operand: 1 "register_operand" "vr")))]
  "TARGET_VECTOR && can_create_pseudo_p ()"
  "#"
  "&& 1"
  [(const_int 0)]
{
  insn_code icode = code_for_pred_vf2 (, mode);
  riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
  DONE;
}
  [(set_attr "type" "vext")
   (set_attr "mode" "")])
 
 
 
juzhe.zh...@rivai.ai
 
 
发件人： joshua
发送时间： 2024-01-11 20:05
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
without CSE:
(insn 16 15 17 2 (set (reg/v:RVVM2HI 137 [ output_var_0 ])
    (if_then_else:RVVM2HI (unspec:RVVMF8BI [
    (const_vector:RVVMF8BI repeat [
    (const_int 1 [0x1])
    ])
    (reg:DI 146)
    (const_int 2 [0x2]) repeated x2
    (const_int 0 [0])
    (reg:SI 66 vl)
    (reg:SI 67 vtype)
    ] UNSPEC_VPREDICATE)
    (mult:RVVM2HI (sign_extend:RVVM2HI (reg/v:RVVM1QI 136 [ op1 ]))
    (sign_extend:RVVM2HI (vec_duplicate:RVVM1QI (reg:QI 147
    (unspec:RVVM2HI [
    (reg:SI 0 zero)
    ] UNSPEC_VUNDEF))) {pred_dual_widen_mulsrvvm2hi_scalar}
 
with CSE:
(insn 16 15 17 2 (set (reg/v:RVVM2HI 137 [ output_var_0 ])
    (if_then_else:RVVM2HI (unspec:RVVMF8BI [
    (const_vector:RVVMF8BI repeat [
    (const_int 1 [0x1])
    ])
    (reg:DI 146)
    (const_int 2 [0x2]) repeated x2
    (const_int 0 [0])
    (reg:SI 66 vl)
    (reg:SI 67 vtype)
    ] UNSPEC_VPREDICATE)
    (sign_extend:RVVM2HI (reg/v:RVVM1QI 136 [ op1 ]))
    (unspec:RVVM2HI [
    (reg:SI 0 zero)
    ] UNSPEC_VUNDEF))) {pred_extendrvvm2hi_vf2}
 
 
 
 
 
 
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发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 17:32
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
 
Ok.  Let's hold on "RISC-V: Handle differences between XTheadvector and Vector" 
patch
until you can reproduce the issue for me.
 
 
juzhe.zh...@rivai.ai
 
 
发件人： joshua
发送时间： 2024-01-11 17:29
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
The sext/zext issue is not related to xtheadvector-special patterns.
I added !TARGET_XTHEADVECTOR to sext/zext patterns in
"RISC-V: Handle d

Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[joshua]

No, we have debugged and the code won't enter this autovec pattern.
The root cause is CSE, in a very early pass.

What I sent to you just now is the dump result which shows the difference.







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发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 20:13
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


I guess it is because of patterns from autovectorization pattern:


;; Use define_insn_and_split to define vsext.vf2/vzext.vf2 will help
;; to combine instructions as below:
;;   vsext.vf2 + vsext.vf2 + vadd.vv ==> vwadd.vv
(define_insn_and_split "2"
  [(set (match_operand:VWEXTI 0 "register_operand" "=")
    (any_extend:VWEXTI
     (match_operand: 1 "register_operand" "vr")))]
  "TARGET_VECTOR && can_create_pseudo_p ()"
  "#"
  "&& 1"
  [(const_int 0)]
{
  insn_code icode = code_for_pred_vf2 (, mode);
  riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
  DONE;
}
  [(set_attr "type" "vext")
   (set_attr "mode" "")])



juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2024-01-11 20:05
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

without CSE:
(insn 16 15 17 2 (set (reg/v:RVVM2HI 137 [ output_var_0 ])
    (if_then_else:RVVM2HI (unspec:RVVMF8BI [
    (const_vector:RVVMF8BI repeat [
    (const_int 1 [0x1])
    ])
    (reg:DI 146)
    (const_int 2 [0x2]) repeated x2
    (const_int 0 [0])
    (reg:SI 66 vl)
    (reg:SI 67 vtype)
    ] UNSPEC_VPREDICATE)
    (mult:RVVM2HI (sign_extend:RVVM2HI (reg/v:RVVM1QI 136 [ op1 ]))
    (sign_extend:RVVM2HI (vec_duplicate:RVVM1QI (reg:QI 147
    (unspec:RVVM2HI [
    (reg:SI 0 zero)
    ] UNSPEC_VUNDEF))) {pred_dual_widen_mulsrvvm2hi_scalar}
 
with CSE:
(insn 16 15 17 2 (set (reg/v:RVVM2HI 137 [ output_var_0 ])
    (if_then_else:RVVM2HI (unspec:RVVMF8BI [
    (const_vector:RVVMF8BI repeat [
    (const_int 1 [0x1])
    ])
    (reg:DI 146)
    (const_int 2 [0x2]) repeated x2
    (const_int 0 [0])
    (reg:SI 66 vl)
    (reg:SI 67 vtype)
    ] UNSPEC_VPREDICATE)
    (sign_extend:RVVM2HI (reg/v:RVVM1QI 136 [ op1 ]))
    (unspec:RVVM2HI [
    (reg:SI 0 zero)
    ] UNSPEC_VUNDEF))) {pred_extendrvvm2hi_vf2}
 
 
 
 
 
 
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发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 17:32
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
 
Ok.  Let's hold on "RISC-V: Handle differences between XTheadvector and Vector" 
patch
until you can reproduce the issue for me.
 
 
juzhe.zh...@rivai.ai
 
 
发件人： joshua
发送时间： 2024-01-11 17:29
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
The sext/zext issue is not related to xtheadvector-special patterns.
I added !TARGET_XTHEADVECTOR to sext/zext patterns in
"RISC-V: Handle differences between XTheadvector and Vector"
That is caused by the vwmul pattern, but I cannot reproduce it right now.
 
 
 
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 17:24
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
 
I don't see any patterns are possible CSE into sext/zext patterns:
 
 
+(define_expand "@pred_mov_width"
+  [(set (match_operand:V_VLS 0 "nonimmediate_operand")
+    (if_then_else:V_VLS
+  (unspec:
+   [(match_operand: 1 "vector_mask_operand")
+   (match_operand 4 "vector_length_operand")

Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[joshua]

without CSE:
(insn 16 15 17 2 (set (reg/v:RVVM2HI 137 [ output_var_0 ])
(if_then_else:RVVM2HI (unspec:RVVMF8BI [
(const_vector:RVVMF8BI repeat [
(const_int 1 [0x1])
])
(reg:DI 146)
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mult:RVVM2HI (sign_extend:RVVM2HI (reg/v:RVVM1QI 136 [ op1 ]))
(sign_extend:RVVM2HI (vec_duplicate:RVVM1QI (reg:QI 147
(unspec:RVVM2HI [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))) {pred_dual_widen_mulsrvvm2hi_scalar}

with CSE:
(insn 16 15 17 2 (set (reg/v:RVVM2HI 137 [ output_var_0 ])
(if_then_else:RVVM2HI (unspec:RVVMF8BI [
(const_vector:RVVMF8BI repeat [
(const_int 1 [0x1])
])
(reg:DI 146)
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(sign_extend:RVVM2HI (reg/v:RVVM1QI 136 [ op1 ]))
(unspec:RVVM2HI [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))) {pred_extendrvvm2hi_vf2}






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发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 17:32
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


Ok.  Let's hold on "RISC-V: Handle differences between XTheadvector and Vector" 
patch
until you can reproduce the issue for me.


juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2024-01-11 17:29
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

The sext/zext issue is not related to xtheadvector-special patterns.
I added !TARGET_XTHEADVECTOR to sext/zext patterns in
"RISC-V: Handle differences between XTheadvector and Vector"
That is caused by the vwmul pattern, but I cannot reproduce it right now.
 
 
 
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 17:24
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
 
I don't see any patterns are possible CSE into sext/zext patterns:
 
 
+(define_expand "@pred_mov_width"
+  [(set (match_operand:V_VLS 0 "nonimmediate_operand")
+    (if_then_else:V_VLS
+  (unspec:
+   [(match_operand: 1 "vector_mask_operand")
+   (match_operand 4 "vector_length_operand")
+   (match_operand 5 "const_int_operand")
+   (match_operand 6 "const_int_operand")
+   (match_operand 7 "const_int_operand")
+   (reg:SI VL_REGNUM)
+   (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VLMEM_OP)
+  (match_operand:V_VLS 3 "vector_move_operand")
+  (match_operand:V_VLS 2 "vector_merge_operand")))]
+  "TARGET_XTHEADVECTOR"
+  {})
+
+(define_insn_and_split "*pred_mov_width"
+  [(set (match_operand:V_VLS 0 "nonimmediate_operand"      "=vr,    vr,    vd, 
    m,    vr,    vr")
+    (if_then_else:V_VLS
+  (unspec:
+   [(match_operand: 1 "vector_mask_operand"   "vmWc1,   Wc1,    
vm, vmWc1,   Wc1,   Wc1")
+   (match_operand 4 "vector_length_operand"  "   rK,    rK,    
rK,    rK,    rK,    rK")
+   (match_operand 5 "const_int_operand"  "    i, i, i, i,  
   i, i")
+   (match_operand 6 "const_int_operand"  "    i, i, i, i,  
   i, i")
+   (match_operand 7 "const_int_operand"  "    i, i, i, i,  
   i, i")
+   (reg:SI VL_REGNUM)
+   (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VLMEM_OP)
+  (match_operand:V_VLS 3 "reg_or_mem_operand"    "    m, m,
 m,    vr,    vr,    vr")
+  (match_operand:V_VLS 2 "vector_merge_operand"    "    0,    vu,    
vu,    vu,    vu, 0")))]
+  "(TARGET_XTHEADVECTOR
+    && (register_operand (operands[0], mode)
+   || register_operand (operands[3], mode)))&q

[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

[Jun Sha (Joshua)]

This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 

For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r.

gcc/ChangeLog:

* config.gcc:  Add files for XTheadVector intrinsics.
* config/riscv/autovec.md: Guard XTheadVector.
* config/riscv/riscv-c.cc: Add pragma for XTheadVector.
* config/riscv/riscv-string.cc (expand_block_move):
Guard XTheadVector.
* config/riscv/riscv-string.cc (vls_mode_valid_p): 
Avoid autovec.
* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
(build_one): New function.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
(DEF_THEAD_RVV_FUNCTION): Add new marcos.
(check_required_extensions):
(handle_pragma_vector):
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR):
(RVV_REQUIRE_XTHEADVECTOR):
Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR.
(struct function_group_info):
* config/riscv/riscv-vector-switch.def (ENTRY):
Disable fractional mode for the XTheadVector extension.
(TUPLE_ENTRY): Likewise.
* config/riscv/riscv-vsetvl.cc: Add functions for xtheadvector.
* config/riscv/riscv.cc (riscv_v_ext_vls_mode_p):
Guard XTheadVector.
(riscv_v_adjust_bytesize): Likewise.
(riscv_preferred_simd_mode): Likewsie.
(riscv_autovectorize_vector_modes): Likewise.
(riscv_vector_mode_supported_any_target_p): Likewise.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
* config/riscv/vector.md: Include thead-vector.md.
* config/riscv/riscv_th_vector.h: New file.
* config/riscv/thead-vector.md: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector.
* gcc.target/riscv/rvv/base/abi-1.c: Exclude XTheadVector.
* lib/target-supports.exp: Add target for XTheadVector.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/autovec.md   |   2 +-
 gcc/config/riscv/predicates.md|   4 +-
 gcc/config/riscv/riscv-c.cc   |   3 +-
 gcc/config/riscv/riscv-string.cc  |   3 +-
 gcc/config/riscv/riscv-v.cc   |   2 +-
 .../riscv/riscv-vector-builtins-bases.cc  |  48 --
 .../riscv/riscv-vector-builtins-shapes.cc |  23 +++
 gcc/config/riscv/riscv-vector-switch.def  | 150 +-
 gcc/config/riscv/riscv.cc |  20 ++-
 gcc/config/riscv/riscv_th_vector.h|  49 ++
 gcc/config/riscv/thead-vector.md  | 102 
 gcc/config/riscv/thead.cc |  23 ++-
 gcc/config/riscv/vector.md|  43 -
 .../gcc.target/riscv/rvv/base/abi-1.c |   2 +-
 .../gcc.target/riscv/rvv/base/pragma-1.c  |   2 +-
 gcc/testsuite/lib/target-supports.exp |  12 ++
 17 files changed, 380 insertions(+), 110 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_th_vector.h
 create mode 100644 gcc/config/riscv/thead-vector.md

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 7e583390024..047e4c02cf4 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,7 +549,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_th_vector.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 775eaa825b0..0477781cabe 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2579,7 +2579,7 @@
   [(match_operand  0 "register_operand")
(match_operand  1 "memory_operand")
(match_operand:ANYI 2 "const_int_operand")]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   {
 riscv_vector::expand_rawmemchr(mode, operands[0], operands[1],
   operands[2]);
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 

Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[joshua]

Do you mean removing TARGET_XTHEADVECTOR for sext/zext patterns
and then resending the  "RISC-V: Handle differences between XTheadvector
and Vector" patch?





--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 17:57
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主　题：Re: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


LGTM. Could you resend the patch "RISC-V: Handle differences between 
XTheadvector and Vector


Thanks.
juzhe.zh...@rivai.ai

 
From: Jun Sha (Joshua)
Date: 2024-01-11 17:52
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.
 
gcc/ChangeLog:
 
* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(class th_extract): Define new builtin bases.
(BASE): Define new builtin bases.
* config/riscv/riscv-vector-builtins-bases.h:
Define new builtin class.
* config/riscv/riscv-vector-builtins-shapes.cc
(struct th_loadstore_width_def): Define new builtin shapes.
(struct th_indexed_loadstore_width_def):
Define new builtin shapes.
(struct th_extract_def): Define new builtin shapes.
(SHAPE): Define new builtin shapes.
* config/riscv/riscv-vector-builtins-shapes.h:
Define new builtin shapes.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
* config/riscv/riscv-vector-builtins.h (enum required_ext):
(struct function_group_info):
* config/riscv/t-riscv: Add thead-vector-builtins-functions.def
* config/riscv/thead-vector.md
(@pred_mov_width): Add new patterns.
(*pred_mov_width): Likewise.
(@pred_store_width): Likewise.
(@pred_strided_load_width): Likewise.
(@pred_strided_store_width): Likewise.
(@pred_indexed_load_width): Likewise.
(@pred_indexed_store_width):
(@pred_th_extract): Likewise.
(*pred_th_extract): Likewise.
* config/riscv/thead-vector-builtins-functions.def: New file.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c: New test.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 .../riscv/riscv-vector-builtins-bases.cc  | 139 ++
 .../riscv/riscv-vector-builtins-bases.h   |  31 +++
 .../riscv/riscv-vector-builtins-shapes.cc | 160 +++
 .../riscv/riscv-vector-builtins-shapes.h  |   3 +
 gcc/config/riscv/riscv-vector-builtins.cc |  70 +
 gcc/config/riscv/riscv-vector-builtins.h  |   3 +
 gcc/config/riscv/t-riscv  |   1 +
 .../riscv/thead-vector-builtins-functions.def |  39 +++
 gcc/config/riscv/thead-vector.md  | 250 ++
 .../riscv/rvv/xtheadvector/vlb-vsb.c  |  68 +
 .../riscv/rvv/xtheadvector/vlbu-vsb.c |  68 +
 .../riscv/rvv/xtheadvector/vlh-vsh.c  |  68 +
 .../riscv/rvv/xtheadvector/vlhu-vsh.c |  68 +
 .../riscv/rvv/xtheadvector/vlw-vsw.c  |  68 +
 .../riscv/rvv/xtheadvector/vlwu-vsw.c |  68 +
 15 files changed, 1104 insertions(+)
 create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c
 
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 1aa6e3c6665..b6f6e4ff37e 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2141,6 +2141,83 @@ public:
   }
 };
 
+/* Implements
+ * th.vl(b/h/w)[u].v/th.vs(b/h/w)[u].v/th.vls(b/h/w)[u].v/th.vss(b/h/w)[u].v/
+ * th.vlx(b/h/w)[u].v/th.vs

[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[Jun Sha (Joshua)]

This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(class th_extract): Define new builtin bases.
(BASE): Define new builtin bases.
* config/riscv/riscv-vector-builtins-bases.h:
Define new builtin class.
* config/riscv/riscv-vector-builtins-shapes.cc
(struct th_loadstore_width_def): Define new builtin shapes.
(struct th_indexed_loadstore_width_def):
Define new builtin shapes.
(struct th_extract_def): Define new builtin shapes.
(SHAPE): Define new builtin shapes.
* config/riscv/riscv-vector-builtins-shapes.h:
Define new builtin shapes.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
* config/riscv/riscv-vector-builtins.h (enum required_ext):
(struct function_group_info):
* config/riscv/t-riscv: Add thead-vector-builtins-functions.def
* config/riscv/thead-vector.md
(@pred_mov_width): Add new patterns.
(*pred_mov_width): Likewise.
(@pred_store_width): Likewise.
(@pred_strided_load_width): Likewise.
(@pred_strided_store_width): Likewise.
(@pred_indexed_load_width): Likewise.
(@pred_indexed_store_width):
(@pred_th_extract): Likewise.
(*pred_th_extract): Likewise.
* config/riscv/thead-vector-builtins-functions.def: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c: New test.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 .../riscv/riscv-vector-builtins-bases.cc  | 139 ++
 .../riscv/riscv-vector-builtins-bases.h   |  31 +++
 .../riscv/riscv-vector-builtins-shapes.cc | 160 +++
 .../riscv/riscv-vector-builtins-shapes.h  |   3 +
 gcc/config/riscv/riscv-vector-builtins.cc |  70 +
 gcc/config/riscv/riscv-vector-builtins.h  |   3 +
 gcc/config/riscv/t-riscv  |   1 +
 .../riscv/thead-vector-builtins-functions.def |  39 +++
 gcc/config/riscv/thead-vector.md  | 250 ++
 .../riscv/rvv/xtheadvector/vlb-vsb.c  |  68 +
 .../riscv/rvv/xtheadvector/vlbu-vsb.c |  68 +
 .../riscv/rvv/xtheadvector/vlh-vsh.c  |  68 +
 .../riscv/rvv/xtheadvector/vlhu-vsh.c |  68 +
 .../riscv/rvv/xtheadvector/vlw-vsw.c  |  68 +
 .../riscv/rvv/xtheadvector/vlwu-vsw.c |  68 +
 15 files changed, 1104 insertions(+)
 create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 1aa6e3c6665..b6f6e4ff37e 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2141,6 +2141,83 @@ public:
   }
 };
 
+/* Implements
+ * th.vl(b/h/w)[u].v/th.vs(b/h/w)[u].v/th.vls(b/h/w)[u].v/th.vss(b/h/w)[u].v/
+ * th.vlx(b/h/w)[u].v/th.vs[u]x(b/h/w).v
+ * codegen.  */
+template
+class th_loadstore_width : public function_base
+{
+public:
+  bool apply_tail_policy_p () const override { return !STORE_P; }
+  bool apply_mask_policy_p () const override { return !STORE_P; }
+
+  unsigned int call_properties (const function_instance &) const override
+  {
+if (STORE_P)
+  return CP_WRITE_MEMORY;
+else
+  return CP_READ_MEMORY;
+  }
+
+  bool can_be_overloaded_p (enum predication_type_index pred) const override
+  {
+if (STORE_P || LST_TYPE == LST_INDEXED)
+  return true;
+return pred != PRED_TYPE_none;
+  }
+
+  rtx expand (function_expander ) const override
+  {
+gcc_assert (TARGET_XTHEADVECTOR);
+if (LST_TYPE == LST_INDEXED)
+  {
+   if (STORE_P)
+ return e.use_exact_insn (
+   code_for_pred_indexed_store_width (UNSPEC, UNSPEC,
+  e.vector_mode ()));
+   else
+ return e.use_exact_insn (
+   code_for_pred_indexed_load_width 

Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[joshua]

I think removing these changes for the "RISC-V: Handle differences between 
XTheadvector and Vector" patch is better.
This is an extra e issue that can be handled in a seperate patch.




--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 17:32
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


Ok.  Let's hold on "RISC-V: Handle differences between XTheadvector and Vector" 
patch
until you can reproduce the issue for me.


juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2024-01-11 17:29
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

The sext/zext issue is not related to xtheadvector-special patterns.
I added !TARGET_XTHEADVECTOR to sext/zext patterns in
"RISC-V: Handle differences between XTheadvector and Vector"
That is caused by the vwmul pattern, but I cannot reproduce it right now.
 
 
 
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 17:24
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
 
I don't see any patterns are possible CSE into sext/zext patterns:
 
 
+(define_expand "@pred_mov_width"
+  [(set (match_operand:V_VLS 0 "nonimmediate_operand")
+    (if_then_else:V_VLS
+  (unspec:
+   [(match_operand: 1 "vector_mask_operand")
+   (match_operand 4 "vector_length_operand")
+   (match_operand 5 "const_int_operand")
+   (match_operand 6 "const_int_operand")
+   (match_operand 7 "const_int_operand")
+   (reg:SI VL_REGNUM)
+   (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VLMEM_OP)
+  (match_operand:V_VLS 3 "vector_move_operand")
+  (match_operand:V_VLS 2 "vector_merge_operand")))]
+  "TARGET_XTHEADVECTOR"
+  {})
+
+(define_insn_and_split "*pred_mov_width"
+  [(set (match_operand:V_VLS 0 "nonimmediate_operand"      "=vr,    vr,    vd, 
    m,    vr,    vr")
+    (if_then_else:V_VLS
+  (unspec:
+   [(match_operand: 1 "vector_mask_operand"   "vmWc1,   Wc1,    
vm, vmWc1,   Wc1,   Wc1")
+   (match_operand 4 "vector_length_operand"  "   rK,    rK,    
rK,    rK,    rK,    rK")
+   (match_operand 5 "const_int_operand"  "    i, i, i, i,  
   i, i")
+   (match_operand 6 "const_int_operand"  "    i, i, i, i,  
   i, i")
+   (match_operand 7 "const_int_operand"  "    i, i, i, i,  
   i, i")
+   (reg:SI VL_REGNUM)
+   (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VLMEM_OP)
+  (match_operand:V_VLS 3 "reg_or_mem_operand"    "    m, m,
 m,    vr,    vr,    vr")
+  (match_operand:V_VLS 2 "vector_merge_operand"    "    0,    vu,    
vu,    vu,    vu, 0")))]
+  "(TARGET_XTHEADVECTOR
+    && (register_operand (operands[0], mode)
+   || register_operand (operands[3], mode)))"
+  "@
+   vl.v\t%0,%3%p1
+   vl.v\t%0,%3
+   vl.v\t%0,%3,%1.t
+   vs.v\t%3,%0%p1
+   vmv.v.v\t%0,%3
+   vmv.v.v\t%0,%3"
+  "&& register_operand (operands[0], mode)
+   && register_operand (operands[3], mode)
+   && satisfies_constraint_vu (operands[2])
+   && INTVAL (operands[7]) == riscv_vector::VLMAX"
+  [(set (match_dup 0) (match_dup 3))]
+  ""
+  [(set_attr "type" "vlde,vlde,vlde,vste,vimov,vimov")
+   (set_attr "mode" "")])
+
+(define_insn "@pred_store_width"
+  [(set (match_operand:VI 0 "memory_operand"   "+m")
+   (if_then_else:VI
+     (unspec:
+       [(match_operand: 1 "vector_mask_operand" "vmWc1")
+    (match_operand 3 "vector_length_operand"    "   rK")
+    (match_operand 4 "const_int_operand"   "    i")
+    (reg:SI VL_REGNUM)
+    (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VSMEM_OP)
+     (match_operand:VI 2 "register_operand""    vr")
+     (match_dup 0)))]
+  "TARGET_XTHEADVECTOR"
+  "vs.v\t%2,%0%p1"
+  [(set_attr "type" &quo

Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[joshua]

I see. We added ! TARGET_THEADVECTOR initally becasue
we want to provide a patchset version that can work without any
errors both in O0 and O2. Without these changes, we will get "
unrecognized opcode" in O2 during assembly stage.




--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 17:28
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


I prefer you remove those TARGET_THEADVECTOR for now.


And file PR let me see the real problem.


I don't believe this should not fixed by this way.


juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2024-01-11 17:26
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

Maybe the optimization cannot be done in simple cases. We run some complex cases
in O2 and dsicovered it.
 
 
 
 
 
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 17:17
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
 
You mean which pattern optimized sext/vzext pattern?
 
 
I didn't see theadvector-specific extension patterns. Could you show me?
 
 
 
 
juzhe.zh...@rivai.ai
 
 
发件人： joshua
发送时间： 2024-01-11 17:14
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
To be specific, in CSE pass, the initial pattern will be optimized into the 
sext/zext pattern.
 
 
 
 
--
发件人：joshua 
发送时间：2024年1月11日(星期四) 17:11
收件人："juzhe.zh...@rivai.ai"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
 
sext/zext will be generated in O2 even without corresponding intrinsics.
 
 
 
 
 
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 17:07
收件人："cooper.joshua"; 
"gcc-patches"
抄 送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主 题：Re: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
 
enum required_ext
{
   VECTOR_EXT,   /* Vector extension */
+  XTHEADVECTOR_EXT,   /* XTheadVector extension */
   ZVBB_EXT,    /* Cryto vector Zvbb sub-ext */
   ZVBB_OR_ZVKB_EXT, /* Cryto vector Zvbb or zvkb sub-ext */
   ZVBC_EXT,    /* Crypto vector Zvbc sub-ext */
 
 
 
Add theadvector to the end of the enum.
 
 
+      case XTHEADVECTOR_EXT:
+ return TARGET_XTHEADVECTOR;
 
 
 
Same.
 
 
+  "&& register_operand (operands[0], mode)
+   && register_operand (operands[3], mode)
+   && satisfies_constraint_vu (operands[2])
+   && INTVAL (operands[7]) == riscv_vector::VLMAX"
 
 
 
You can use whole_reg_to_reg_move_p
 
 
 
 
Btw, I review again :   RISC-V: Handle differences between XTheadvector and 
Vector
 
 
    (any_extend:VWEXTI      (match_operand: 3 
"register_operand"   "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,   vr,   
vr"))    (match_operand:VWEXTI 2 "vector_merge_operand"           " vu, vu,  0, 
 0, vu, vu,  0,  0, vu, vu,  0,  0,   vu,    0")))]-  "TARGET_VECTOR"+  
"TARGET_VECTOR && !TARGET_XTHEADVECTOR"   "vext.vf2\t%0,%3%p1"   [(set_attr 
"type" "vext")    (set_attr "mode" "")@@ -3713,7 +3744,7 @@    
(any_extend:VQEXTI      (match_operand: 3 "register_operand"   
"W43,W43,W43,W43,W86,W86,W86,W86,   vr,   vr"))    (match_operand:VQEXTI 2 
"vector_merge_operand"         " vu, vu,  0,  0, vu, vu,  0,  0,   vu,    
0")))]-  "TARGET_VECTOR"+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"   
"vext.vf4\t%0,%3%p1"   [(set_attr "type" "vext")    (set_attr "mode" 
"")@@ -3734,7 +3765,7 @@    (any_extend:VOEXTI      
(match_operand: 3 "register_operand"   "W87,W87,W87,W87,   vr,   
vr"))    (match_operand:VOEXTI 2 "vector_merge_operand"   

Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[joshua]

quot;    m, m, m")
+    (match_operand 4 "pmode_reg_or_0_operand"   "   rJ,    rJ,    
rJ")] UNSPEC_TH_VLSMEM_OP)
+     (match_operand:VI 2 "vector_merge_operand"  "    0,    vu,    
vu")))]
+  "TARGET_XTHEADVECTOR"
+  "vls.v\t%0,%3,%z4%p1"
+  [(set_attr "type" "vlds")
+   (set_attr "mode" "")])
+
+(define_insn "@pred_strided_store_width"
+  [(set (match_operand:VI 0 "memory_operand"   "+m")
+   (if_then_else:VI
+     (unspec:
+       [(match_operand: 1 "vector_mask_operand" "vmWc1")
+    (match_operand 4 "vector_length_operand"    "   rK")
+    (match_operand 5 "const_int_operand"   "    i")
+    (reg:SI VL_REGNUM)
+    (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VSSMEM_OP)
+     (unspec:VI
+       [(match_operand 2 "pmode_reg_or_0_operand"   "   rJ")
+    (match_operand:VI 3 "register_operand"   "   vr")] 
UNSPEC_TH_VSSMEM_OP)
+     (match_dup 0)))]
+  "TARGET_XTHEADVECTOR"
+  "vss.v\t%3,%0,%z2%p1"
+  [(set_attr "type" "vsts")
+   (set_attr "mode" "")
+   (set (attr "avl_type_idx") (const_int 5))])
+
+(define_insn "@pred_indexed_load_width"
+  [(set (match_operand:VI 0 "register_operand"  "=vd, vr,vd, vr")
+   (if_then_else:VI
+     (unspec:
+       [(match_operand: 1 "vector_mask_operand"  " vm,Wc1,vm,Wc1")
+    (match_operand 5 "vector_length_operand" " rK, rK,rK, rK")
+    (match_operand 6 "const_int_operand"   "  i,  i, i,  i")
+    (match_operand 7 "const_int_operand"   "  i,  i, i,  i")
+    (match_operand 8 "const_int_operand"   "  i,  i, i,  i")
+    (reg:SI VL_REGNUM)
+    (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VLXMEM_OP)
+     (unspec:VI
+       [(match_operand 3 "pmode_reg_or_0_operand"    " rJ, rJ,rJ, rJ")
+    (mem:BLK (scratch))
+    (match_operand:VI 4 "register_operand" " vr, vr,vr, vr")] 
UNSPEC_TH_VLXMEM_OP)
+     (match_operand:VI 2 "vector_merge_operand"   " vu, vu, 0,  0")))]
+  "TARGET_XTHEADVECTOR"
+  "vlx.v\t%0,(%z3),%4%p1"
+  [(set_attr "type" "vldux")
+   (set_attr "mode" "")])
+
+(define_insn "@pred_indexed_store_width"
+  [(set (mem:BLK (scratch))
+   (unspec:BLK
+     [(unspec:
+       [(match_operand: 0 "vector_mask_operand" "vmWc1")
+    (match_operand 4 "vector_length_operand"    "   rK")
+    (match_operand 5 "const_int_operand"   "    i")
+    (reg:SI VL_REGNUM)
+    (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VSXMEM_OP)
+      (match_operand 1 "pmode_reg_or_0_operand"  "  rJ")
+      (match_operand:VI 2 "register_operand" "  vr")
+      (match_operand:VI 3 "register_operand"  "  vr")] 
UNSPEC_TH_VSXMEM_OP))]
+  "TARGET_XTHEADVECTOR"
+  "vsx.v\t%3,(%z1),%2%p0"
+  [(set_attr "type" "vstux")
+   (set_attr "mode" "")])
+
+(define_expand "@pred_th_extract"
+  [(set (match_operand: 0 "register_operand")
+   (unspec:
+     [(vec_select:
+    (match_operand:V_VLSI 1 "register_operand")
+    (parallel [(match_operand:DI 2 "register_operand" "r")]))
+      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
+  "TARGET_XTHEADVECTOR"
+{})
+
+(define_insn "*pred_th_extract"
+  [(set (match_operand: 0 "register_operand"   "=r")
+  (unspec:
+    [(vec_select:
+   (match_operand:V_VLSI 1 "register_operand" "vr")
+   (parallel [(match_operand:DI 2 "register_operand" "r")]))
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
+  "TARGET_XTHEADVECTOR"
+  "vext.x.v\t%0,%1,%2"
+  [(set_attr "type" "vimovvx")
+   (set_attr "mode" "")])



juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2024-01-11 17:21
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

"I didn't see theadvector-specific extension patterns. Could you show me?"
They are all in the file thead-vector.md.
 
For the sext/zext issue, perhaps I need some time to reproduce that 
o

Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[joshua]

Maybe the optimization cannot be done in simple cases. We run some complex cases
in O2 and dsicovered it.






--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 17:17
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


You mean which pattern optimized sext/vzext pattern?


I didn't see theadvector-specific extension patterns. Could you show me?




juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2024-01-11 17:14
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

To be specific, in CSE pass, the initial pattern will be optimized into the 
sext/zext pattern.
 
 
 
 
------
发件人：joshua 
发送时间：2024年1月11日(星期四) 17:11
收件人："juzhe.zh...@rivai.ai"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
 
sext/zext will be generated in O2 even without corresponding intrinsics.
 
 
 
 
 
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 17:07
收件人："cooper.joshua"; 
"gcc-patches"
抄 送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主 题：Re: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
 
enum required_ext
{
   VECTOR_EXT,   /* Vector extension */
+  XTHEADVECTOR_EXT,   /* XTheadVector extension */
   ZVBB_EXT,    /* Cryto vector Zvbb sub-ext */
   ZVBB_OR_ZVKB_EXT, /* Cryto vector Zvbb or zvkb sub-ext */
   ZVBC_EXT,    /* Crypto vector Zvbc sub-ext */
 
 
 
Add theadvector to the end of the enum.
 
 
+      case XTHEADVECTOR_EXT:
+ return TARGET_XTHEADVECTOR;
 
 
 
Same.
 
 
+  "&& register_operand (operands[0], mode)
+   && register_operand (operands[3], mode)
+   && satisfies_constraint_vu (operands[2])
+   && INTVAL (operands[7]) == riscv_vector::VLMAX"
 
 
 
You can use whole_reg_to_reg_move_p
 
 
 
 
Btw, I review again :   RISC-V: Handle differences between XTheadvector and 
Vector
 
 
    (any_extend:VWEXTI      (match_operand: 3 
"register_operand"   "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,   vr,   
vr"))    (match_operand:VWEXTI 2 "vector_merge_operand"           " vu, vu,  0, 
 0, vu, vu,  0,  0, vu, vu,  0,  0,   vu,    0")))]-  "TARGET_VECTOR"+  
"TARGET_VECTOR && !TARGET_XTHEADVECTOR"   "vext.vf2\t%0,%3%p1"   [(set_attr 
"type" "vext")    (set_attr "mode" "")@@ -3713,7 +3744,7 @@    
(any_extend:VQEXTI      (match_operand: 3 "register_operand"   
"W43,W43,W43,W43,W86,W86,W86,W86,   vr,   vr"))    (match_operand:VQEXTI 2 
"vector_merge_operand"         " vu, vu,  0,  0, vu, vu,  0,  0,   vu,    
0")))]-  "TARGET_VECTOR"+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"   
"vext.vf4\t%0,%3%p1"   [(set_attr "type" "vext")    (set_attr "mode" 
"")@@ -3734,7 +3765,7 @@    (any_extend:VOEXTI      
(match_operand: 3 "register_operand"   "W87,W87,W87,W87,   vr,   
vr"))    (match_operand:VOEXTI 2 "vector_merge_operand"        " vu, vu,  0,  
0,   vu,    0")))]-  "TARGET_VECTOR"+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"  
 "vext.vf8\t%0,%3%p1"   [(set_attr "type" "vext")    (set_attr "mode" 
"")
Why do you add these !TARGERT_XTHEADVECRTOR ?
 
 
juzhe.zh...@rivai.ai
 
 
From: Jun Sha (Joshua)
Date: 2024-01-11 16:46
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.
 
gcc/ChangeLog:
 
 * config/riscv/riscv-vector-builtins-bases.cc
 (class th_loadstore_width): Define new builtin bases.
 (class th_extract): Define new builtin bases.
 (BASE): Define new builtin bases.
 * config/riscv/riscv-vector-builtins-bases.h:
 Define new builtin class.
 * config/riscv/riscv-vector-builtins-shapes.cc
 (struct th_loadstore_width

Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[joshua]

"I didn't see theadvector-specific extension patterns. Could you show me?"
They are all in the file thead-vector.md.

For the sext/zext issue, perhaps I need some time to reproduce that 
optimization,
but I can clearly remember it is related to vwmul.


--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 17:17
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


You mean which pattern optimized sext/vzext pattern?


I didn't see theadvector-specific extension patterns. Could you show me?




juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2024-01-11 17:14
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

To be specific, in CSE pass, the initial pattern will be optimized into the 
sext/zext pattern.
 
 
 
 
------
发件人：joshua 
发送时间：2024年1月11日(星期四) 17:11
收件人："juzhe.zh...@rivai.ai"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
 
sext/zext will be generated in O2 even without corresponding intrinsics.
 
 
 
 
 
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 17:07
收件人："cooper.joshua"; 
"gcc-patches"
抄 送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主 题：Re: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
 
enum required_ext
{
   VECTOR_EXT,   /* Vector extension */
+  XTHEADVECTOR_EXT,   /* XTheadVector extension */
   ZVBB_EXT,    /* Cryto vector Zvbb sub-ext */
   ZVBB_OR_ZVKB_EXT, /* Cryto vector Zvbb or zvkb sub-ext */
   ZVBC_EXT,    /* Crypto vector Zvbc sub-ext */
 
 
 
Add theadvector to the end of the enum.
 
 
+      case XTHEADVECTOR_EXT:
+ return TARGET_XTHEADVECTOR;
 
 
 
Same.
 
 
+  "&& register_operand (operands[0], mode)
+   && register_operand (operands[3], mode)
+   && satisfies_constraint_vu (operands[2])
+   && INTVAL (operands[7]) == riscv_vector::VLMAX"
 
 
 
You can use whole_reg_to_reg_move_p
 
 
 
 
Btw, I review again :   RISC-V: Handle differences between XTheadvector and 
Vector
 
 
    (any_extend:VWEXTI      (match_operand: 3 
"register_operand"   "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,   vr,   
vr"))    (match_operand:VWEXTI 2 "vector_merge_operand"           " vu, vu,  0, 
 0, vu, vu,  0,  0, vu, vu,  0,  0,   vu,    0")))]-  "TARGET_VECTOR"+  
"TARGET_VECTOR && !TARGET_XTHEADVECTOR"   "vext.vf2\t%0,%3%p1"   [(set_attr 
"type" "vext")    (set_attr "mode" "")@@ -3713,7 +3744,7 @@    
(any_extend:VQEXTI      (match_operand: 3 "register_operand"   
"W43,W43,W43,W43,W86,W86,W86,W86,   vr,   vr"))    (match_operand:VQEXTI 2 
"vector_merge_operand"         " vu, vu,  0,  0, vu, vu,  0,  0,   vu,    
0")))]-  "TARGET_VECTOR"+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"   
"vext.vf4\t%0,%3%p1"   [(set_attr "type" "vext")    (set_attr "mode" 
"")@@ -3734,7 +3765,7 @@    (any_extend:VOEXTI      
(match_operand: 3 "register_operand"   "W87,W87,W87,W87,   vr,   
vr"))    (match_operand:VOEXTI 2 "vector_merge_operand"        " vu, vu,  0,  
0,   vu,    0")))]-  "TARGET_VECTOR"+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"  
 "vext.vf8\t%0,%3%p1"   [(set_attr "type" "vext")    (set_attr "mode" 
"")
Why do you add these !TARGERT_XTHEADVECRTOR ?
 
 
juzhe.zh...@rivai.ai
 
 
From: Jun Sha (Joshua)
Date: 2024-01-11 16:46
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.
 
gcc/ChangeLog:
 
 * config/riscv/riscv-vector-builtins-bases.cc
 (class th_loadstore_width): Define new builtin bases.
 (class th_extract): Define new builtin bases.
 (BASE): Define new builtin bases.
 * 

Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[joshua]

To be specific, in CSE pass, the initial pattern will be optimized into the 
sext/zext pattern.




--
发件人：joshua 
发送时间：2024年1月11日(星期四) 17:11
收件人："juzhe.zh...@rivai.ai"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


sext/zext will be generated in O2 even without corresponding intrinsics.






--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 17:07
收件人："cooper.joshua"; 
"gcc-patches"
抄 送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主 题：Re: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


enum required_ext
{
   VECTOR_EXT,   /* Vector extension */
+  XTHEADVECTOR_EXT,   /* XTheadVector extension */
   ZVBB_EXT,    /* Cryto vector Zvbb sub-ext */
   ZVBB_OR_ZVKB_EXT, /* Cryto vector Zvbb or zvkb sub-ext */
   ZVBC_EXT,    /* Crypto vector Zvbc sub-ext */



Add theadvector to the end of the enum.


+      case XTHEADVECTOR_EXT:
+ return TARGET_XTHEADVECTOR;



Same.


+  "&& register_operand (operands[0], mode)
+   && register_operand (operands[3], mode)
+   && satisfies_constraint_vu (operands[2])
+   && INTVAL (operands[7]) == riscv_vector::VLMAX"



You can use whole_reg_to_reg_move_p




Btw, I review again :   RISC-V: Handle differences between XTheadvector and 
Vector


    (any_extend:VWEXTI      (match_operand: 3 
"register_operand"   "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,   vr,   
vr"))    (match_operand:VWEXTI 2 "vector_merge_operand"           " vu, vu,  0, 
 0, vu, vu,  0,  0, vu, vu,  0,  0,   vu,    0")))]-  "TARGET_VECTOR"+  
"TARGET_VECTOR && !TARGET_XTHEADVECTOR"   "vext.vf2\t%0,%3%p1"   [(set_attr 
"type" "vext")    (set_attr "mode" "")@@ -3713,7 +3744,7 @@    
(any_extend:VQEXTI      (match_operand: 3 "register_operand"   
"W43,W43,W43,W43,W86,W86,W86,W86,   vr,   vr"))    (match_operand:VQEXTI 2 
"vector_merge_operand"         " vu, vu,  0,  0, vu, vu,  0,  0,   vu,    
0")))]-  "TARGET_VECTOR"+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"   
"vext.vf4\t%0,%3%p1"   [(set_attr "type" "vext")    (set_attr "mode" 
"")@@ -3734,7 +3765,7 @@    (any_extend:VOEXTI      
(match_operand: 3 "register_operand"   "W87,W87,W87,W87,   vr,   
vr"))    (match_operand:VOEXTI 2 "vector_merge_operand"        " vu, vu,  0,  
0,   vu,    0")))]-  "TARGET_VECTOR"+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"  
 "vext.vf8\t%0,%3%p1"   [(set_attr "type" "vext")    (set_attr "mode" 
"")
Why do you add these !TARGERT_XTHEADVECRTOR ?


juzhe.zh...@rivai.ai

 
From: Jun Sha (Joshua)
Date: 2024-01-11 16:46
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.
 
gcc/ChangeLog:
 
 * config/riscv/riscv-vector-builtins-bases.cc
 (class th_loadstore_width): Define new builtin bases.
 (class th_extract): Define new builtin bases.
 (BASE): Define new builtin bases.
 * config/riscv/riscv-vector-builtins-bases.h:
 Define new builtin class.
 * config/riscv/riscv-vector-builtins-shapes.cc
 (struct th_loadstore_width_def): Define new builtin shapes.
 (struct th_indexed_loadstore_width_def):
 Define new builtin shapes.
 (struct th_extract_def): Define new builtin shapes.
 (SHAPE): Define new builtin shapes.
 * config/riscv/riscv-vector-builtins-shapes.h:
 Define new builtin shapes.
 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
 * config/riscv/riscv-vector-builtins.h (enum required_ext):
 (struct function_group_info):
 * config/riscv/t-riscv: Add thead-vector-builtins-functions.def
 * config/riscv/thead-vector.md
 (@pred_mov_width): Add new patterns.
 (*pred_mov_width): Likewise.
 (@pred_store_width): Likewise.
 (@pred_strided_load_width): Likewise.
 (@pred_strided_store_width): Likewise.
 (@pred_indexed_load_width): Likewise.
 (@pred_indexed_store_width):
 (@pred_th_extract): Likewise.
 (*pred_th_extract): Likewise.
 * config/riscv/thead-vector-builtins-functions.def: New file.
 
gcc/testsuite/ChangeLog:
 
 * gcc.target/riscv/rvv/xtheadvector/vlb-vs

Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[joshua]

sext/zext will be generated in O2 even without corresponding intrinsics.






--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月11日(星期四) 17:07
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主　题：Re: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


enum required_ext
{
   VECTOR_EXT,   /* Vector extension */
+  XTHEADVECTOR_EXT,   /* XTheadVector extension */
   ZVBB_EXT,    /* Cryto vector Zvbb sub-ext */
   ZVBB_OR_ZVKB_EXT, /* Cryto vector Zvbb or zvkb sub-ext */
   ZVBC_EXT,    /* Crypto vector Zvbc sub-ext */



Add theadvector to the end of the enum.


+  case XTHEADVECTOR_EXT:
+   return TARGET_XTHEADVECTOR;



Same.


+  "&& register_operand (operands[0], mode)
+   && register_operand (operands[3], mode)
+   && satisfies_constraint_vu (operands[2])
+   && INTVAL (operands[7]) == riscv_vector::VLMAX"



You can use whole_reg_to_reg_move_p




Btw, I review again :   RISC-V: Handle differences between XTheadvector and 
Vector


  (any_extend:VWEXTI(match_operand: 3 
"register_operand"   "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,   vr,   
vr"))(match_operand:VWEXTI 2 "vector_merge_operand"   " vu, vu, 
 0,  0, vu, vu,  0,  0, vu, vu,  0,  0,   vu,0")))]-  "TARGET_VECTOR"+  
"TARGET_VECTOR && !TARGET_XTHEADVECTOR"   "vext.vf2\t%0,%3%p1"   [(set_attr 
"type" "vext")(set_attr "mode" "")@@ -3713,7 +3744,7 @@
(any_extend:VQEXTI(match_operand: 3 "register_operand"   
"W43,W43,W43,W43,W86,W86,W86,W86,   vr,   vr"))  (match_operand:VQEXTI 
2 "vector_merge_operand" " vu, vu,  0,  0, vu, vu,  0,  0,   vu,
0")))]-  "TARGET_VECTOR"+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"   
"vext.vf4\t%0,%3%p1"   [(set_attr "type" "vext")(set_attr "mode" 
"")@@ -3734,7 +3765,7 @@  (any_extend:VOEXTI
(match_operand: 3 "register_operand"   "W87,W87,W87,W87,   vr,   
vr"))   (match_operand:VOEXTI 2 "vector_merge_operand"" vu, vu, 
 0,  0,   vu,0")))]-  "TARGET_VECTOR"+  "TARGET_VECTOR && 
!TARGET_XTHEADVECTOR"   "vext.vf8\t%0,%3%p1"   [(set_attr "type" "vext")
(set_attr "mode" "")
Why do you add these !TARGERT_XTHEADVECRTOR ?


juzhe.zh...@rivai.ai

 
From: Jun Sha (Joshua)
Date: 2024-01-11 16:46
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.
 
gcc/ChangeLog:
 
* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(class th_extract): Define new builtin bases.
(BASE): Define new builtin bases.
* config/riscv/riscv-vector-builtins-bases.h:
Define new builtin class.
* config/riscv/riscv-vector-builtins-shapes.cc
(struct th_loadstore_width_def): Define new builtin shapes.
(struct th_indexed_loadstore_width_def):
Define new builtin shapes.
(struct th_extract_def): Define new builtin shapes.
(SHAPE): Define new builtin shapes.
* config/riscv/riscv-vector-builtins-shapes.h:
Define new builtin shapes.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
* config/riscv/riscv-vector-builtins.h (enum required_ext):
(struct function_group_info):
* config/riscv/t-riscv: Add thead-vector-builtins-functions.def
* config/riscv/thead-vector.md
(@pred_mov_width): Add new patterns.
(*pred_mov_width): Likewise.
(@pred_store_width): Likewise.
(@pred_strided_load_width): Likewise.
(@pred_strided_store_width): Likewise.
(@pred_indexed_load_width): Likewise.
(@pred_indexed_store_width):
(@pred_th_extract): Likewise.
(*pred_th_extract): Likewise.
* config/riscv/thead-vector-builtins-functions.def: New file.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c: New test.
* gcc.target/

[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[Jun Sha (Joshua)]

This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(class th_extract): Define new builtin bases.
(BASE): Define new builtin bases.
* config/riscv/riscv-vector-builtins-bases.h:
Define new builtin class.
* config/riscv/riscv-vector-builtins-shapes.cc
(struct th_loadstore_width_def): Define new builtin shapes.
(struct th_indexed_loadstore_width_def):
Define new builtin shapes.
(struct th_extract_def): Define new builtin shapes.
(SHAPE): Define new builtin shapes.
* config/riscv/riscv-vector-builtins-shapes.h:
Define new builtin shapes.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
* config/riscv/riscv-vector-builtins.h (enum required_ext):
(struct function_group_info):
* config/riscv/t-riscv: Add thead-vector-builtins-functions.def
* config/riscv/thead-vector.md
(@pred_mov_width): Add new patterns.
(*pred_mov_width): Likewise.
(@pred_store_width): Likewise.
(@pred_strided_load_width): Likewise.
(@pred_strided_store_width): Likewise.
(@pred_indexed_load_width): Likewise.
(@pred_indexed_store_width):
(@pred_th_extract): Likewise.
(*pred_th_extract): Likewise.
* config/riscv/thead-vector-builtins-functions.def: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c: New test.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 .../riscv/riscv-vector-builtins-bases.cc  | 139 ++
 .../riscv/riscv-vector-builtins-bases.h   |  31 +++
 .../riscv/riscv-vector-builtins-shapes.cc | 160 +++
 .../riscv/riscv-vector-builtins-shapes.h  |   3 +
 gcc/config/riscv/riscv-vector-builtins.cc |  70 +
 gcc/config/riscv/riscv-vector-builtins.h  |   3 +
 gcc/config/riscv/t-riscv  |   1 +
 .../riscv/thead-vector-builtins-functions.def |  39 +++
 gcc/config/riscv/thead-vector.md  | 253 ++
 .../riscv/rvv/xtheadvector/vlb-vsb.c  |  68 +
 .../riscv/rvv/xtheadvector/vlbu-vsb.c |  68 +
 .../riscv/rvv/xtheadvector/vlh-vsh.c  |  68 +
 .../riscv/rvv/xtheadvector/vlhu-vsh.c |  68 +
 .../riscv/rvv/xtheadvector/vlw-vsw.c  |  68 +
 .../riscv/rvv/xtheadvector/vlwu-vsw.c |  68 +
 15 files changed, 1107 insertions(+)
 create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 46f1a1da33e..3eba7943757 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2125,6 +2125,83 @@ public:
   }
 };
 
+/* Implements
+ * th.vl(b/h/w)[u].v/th.vs(b/h/w)[u].v/th.vls(b/h/w)[u].v/th.vss(b/h/w)[u].v/
+ * th.vlx(b/h/w)[u].v/th.vs[u]x(b/h/w).v
+ * codegen.  */
+template
+class th_loadstore_width : public function_base
+{
+public:
+  bool apply_tail_policy_p () const override { return !STORE_P; }
+  bool apply_mask_policy_p () const override { return !STORE_P; }
+
+  unsigned int call_properties (const function_instance &) const override
+  {
+if (STORE_P)
+  return CP_WRITE_MEMORY;
+else
+  return CP_READ_MEMORY;
+  }
+
+  bool can_be_overloaded_p (enum predication_type_index pred) const override
+  {
+if (STORE_P || LST_TYPE == LST_INDEXED)
+  return true;
+return pred != PRED_TYPE_none;
+  }
+
+  rtx expand (function_expander ) const override
+  {
+gcc_assert (TARGET_XTHEADVECTOR);
+if (LST_TYPE == LST_INDEXED)
+  {
+   if (STORE_P)
+ return e.use_exact_insn (
+   code_for_pred_indexed_store_width (UNSPEC, UNSPEC,
+  e.vector_mode ()));
+   else
+ return e.use_exact_insn (
+   code_for_pred_indexed_load_width 

Re：Re: [PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

[joshua]

Hi Robin,

Thank you for your suggestions!
The patch has been updated by adding a new attribute to
disable alternative for xtheadvector or RVV1.0 instead of
overlaoding group_overlap.

Joshua






--
发件人：钟居哲 
发送时间：2024年1月10日(星期三) 21:43
收件人："rdapp.gcc"; 
"cooper.joshua"; 
"gcc-patches"
抄　送："rdapp.gcc"; 
"jim.wilson.gcc"; palmer; 
andrew; "philipp.tomsich"; Jeff 
Law; "Christoph Müllner"; 
jinma; Cooper Qu
主　题：Re: Re: [PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector 
instructions


>> For the other insns, I wonder if we could get away with not really
>>disabling the newly added early-clobber alternatives for RVV but
>>just disparaging ("?") them?  That way we could re-use "full" for
>>the thv-disabled alternatives and "none" for the newly added ones.
>>("none" will still be misleading then, though :/)



I prefer to disable those early-clobber alternatives added of theadvector for 
RVV,
since disparage still make RA possible reaches the early clobber alternatives.


>>If this doesn't work or others feel the separation is not strict
>>enough, I'd prefer a separate attribute rather than overloading
>>group_overlap.  Maybe something like "spec_restriction" or similar
>>with two values "rvv" and "thv"?



I like this idea, it makes more sense to me. So I think it's better to add an 
attribute to
disable alternative for theadvector or RVV1.0.


juzhe.zh...@rivai.ai

 
From: Robin Dapp
Date: 2024-01-10 21:36
To: Jun Sha (Joshua); gcc-patches
CC: rdapp.gcc; jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jin Ma; Xianmiao Qu
Subject: Re: [PATCH v5] RISC-V: Fix register overlap issue for some 
xtheadvector instructions

Hi Joshua,
 
> For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions
> and floating-point compare instructions, an illegal instruction
> exception will be raised if the destination vector register overlaps
> a source vector register group.
> 
> To handle this issue, we use "group_overlap" and "enabled" attribute
> to disable some alternatives for xtheadvector.
 
>  ;; Widening instructions have group-overlap constraints.  Those are only
>  ;; valid for certain register-group sizes.  This attribute marks the
>  ;; alternatives not matching the required register-group size as disabled.
> -(define_attr "group_overlap" "none,W21,W42,W84,W43,W86,W87,W0"
> +(define_attr "group_overlap" 
> "none,W21,W42,W84,W43,W86,W87,W0,thv_disabled,rvv_disabled"
>    (const_string "none"))
 
I realize there have been some discussions before but I find the naming
misleading.  The group_overlap attribute is supposed to specify whether
groups overlap (and mark the respective alternatives accepting
only this overlap).
Then we check if the groups overlap and disable all non-matching
alternatives.  "none" i.e. "no overlap" always matches.
 
Your first goal seems to be to disable existing non-early-clobber
alternatives for thv.  For this, maybe "full", "same" (or "any"?) would
work?  Please also add a comment in group_overlap_valid then that we
need not actually check for register equality.
 
For the other insns, I wonder if we could get away with not really
disabling the newly added early-clobber alternatives for RVV but
just disparaging ("?") them?  That way we could re-use "full" for
the thv-disabled alternatives and "none" for the newly added ones.
("none" will still be misleading then, though :/)
 
If this doesn't work or others feel the separation is not strict
enough, I'd prefer a separate attribute rather than overloading
group_overlap.  Maybe something like "spec_restriction" or similar
with two values "rvv" and "thv"?
 
Regards
 Robin
 
 

[PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

[Jun Sha (Joshua)]

For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions
and floating-point compare instructions, an illegal instruction
exception will be raised if the destination vector register overlaps
a source vector register group.

To handle this issue, we add an attribute "spec_restriction" to disable
some alternatives for xtheadvector.

gcc/ChangeLog:

* config/riscv/riscv.md (none,thv,rvv):
(no,yes): Add an attribute to disable alternative
for xtheadvector or RVV1.0.
* config/riscv/vector.md: 
Disable alternatives that destination register overlaps
source register group for xtheadvector.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config/riscv/riscv.md  |  22 +++
 gcc/config/riscv/vector.md | 314 +
 2 files changed, 202 insertions(+), 134 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 84212430dc0..23fc32d5cb2 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -579,6 +579,25 @@
 ]
(const_string "yes")))
 
+;; This attribute marks the alternatives not matching the constraints
+;; described in spec as disabled.
+(define_attr "spec_restriction" "none,thv,rvv"
+  (const_string "none"))
+
+(define_attr "spec_restriction_disabled" "no,yes"
+  (cond [(eq_attr "spec_restriction" "none")
+(const_string "no")
+   
+(and (eq_attr "spec_restriction" "thv")
+ (match_test "TARGET_XTHEADVECTOR"))
+(const_string "yes")
+
+(and (eq_attr "spec_restriction" "rvv")
+ (match_test "TARGET_VECTOR && !TARGET_XTHEADVECTOR"))
+(const_string "yes")
+   ]
+   (const_string "no")))
+
 ;; Attribute to control enable or disable instructions.
 (define_attr "enabled" "no,yes"
   (cond [
@@ -590,6 +609,9 @@
 
 (eq_attr "group_overlap_valid" "no")
 (const_string "no")
+
+(eq_attr "spec_restriction_disabled" "yes")
+(const_string "no")
   ]
   (const_string "yes")))
 
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 3eb6daafbc2..c79416cf0d3 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -3260,7 +3260,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "spec_restriction" "thv,none,none")])
 
 (define_insn "@pred_msbc"
   [(set (match_operand: 0 "register_operand""=vr, vr, ")
@@ -3279,7 +3280,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "spec_restriction" "thv,thv,none")])
 
 (define_insn "@pred_madc_scalar"
   [(set (match_operand: 0 "register_operand" "=vr, ")
@@ -3299,7 +3301,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "spec_restriction" "thv,none")])
 
 (define_insn "@pred_msbc_scalar"
   [(set (match_operand: 0 "register_operand" "=vr, ")
@@ -3319,7 +3322,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "spec_restriction" "thv,none")])
 
 (define_expand "@pred_madc_scalar"
   [(set (match_operand: 0 "register_operand")
@@ -3368,7 +3372,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "spec_restriction" "thv,none")])
 
 (define_insn "*pred_madc_extended_scalar"
   [(set (match_operand: 0 "register_operand" "=vr, ")
@@ -3389,7 +3394,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "spec_restriction" "thv,none")])
 
 (define_expand "@pred_msbc_scalar"
   [(set (match_operand: 0 "register_operand")
@@ -3438,7 +3444,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "spec_restriction" "thv,none")])
 
 (define_insn "*pred_msbc_extended_scalar"
   [(set (match_operand: 0 "register_operand"  "=vr, ")
@@ -3459,7 +3466,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "spec_restriction" "thv,none")])
 
 (define_insn "@pred_madc_overflow"
   

Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[joshua]

vlb can accept sew=8/16/32/64.
vlh can accept sew=16/32/64;
vlw can accept sew=32/64.

vint8m1_t __riscv_th_vlb_v_i8m1 (const int8_t *a, size_t vl);
vint8m2_t __riscv_th_vlb_v_i8m2 (const int8_t *a, size_t vl);
vint8m4_t __riscv_th_vlb_v_i8m4 (const int8_t *a, size_t vl);
vint8m8_t __riscv_th_vlb_v_i8m8 (const int8_t *a, size_t vl);
vint16m1_t __riscv_th_vlb_v_i16m1 (const int16_t *a, size_t vl);
vint16m2_t __riscv_th_vlb_v_i16m2 (const int16_t *a, size_t vl);
vint16m4_t __riscv_th_vlb_v_i16m4 (const int16_t *a, size_t vl);
vint16m8_t __riscv_th_vlb_v_i16m8 (const int16_t *a, size_t vl);
vint32m1_t __riscv_th_vlb_v_i32m1 (const int32_t *a, size_t vl);
vint32m2_t __riscv_th_vlb_v_i32m2 (const int32_t *a, size_t vl);
vint32m4_t __riscv_th_vlb_v_i32m4 (const int32_t *a, size_t vl);
vint32m8_t __riscv_th_vlb_v_i32m8 (const int32_t *a, size_t vl);
vint64m1_t __riscv_th_vlb_v_i64m1 (const int64_t *a, size_t vl);
vint64m2_t __riscv_th_vlb_v_i64m2 (const int64_t *a, size_t vl);
vint64m4_t __riscv_th_vlb_v_i64m4 (const int64_t *a, size_t vl);
vint64m8_t __riscv_th_vlb_v_i64m8 (const int64_t *a, size_t vl);
vint16m1_t __riscv_th_vlh_v_i16m1 (const int16_t *a, size_t vl);
vint16m2_t __riscv_th_vlh_v_i16m2 (const int16_t *a, size_t vl);
vint16m4_t __riscv_th_vlh_v_i16m4 (const int16_t *a, size_t vl);
vint16m8_t __riscv_th_vlh_v_i16m8 (const int16_t *a, size_t vl);
vint32m1_t __riscv_th_vlh_v_i32m1 (const int32_t *a, size_t vl);
vint32m2_t __riscv_th_vlh_v_i32m2 (const int32_t *a, size_t vl);
vint32m4_t __riscv_th_vlh_v_i32m4 (const int32_t *a, size_t vl);
vint32m8_t __riscv_th_vlh_v_i32m8 (const int32_t *a, size_t vl);
vint64m1_t __riscv_th_vlh_v_i64m1 (const int64_t *a, size_t vl);
vint64m2_t __riscv_th_vlh_v_i64m2 (const int64_t *a, size_t vl);
vint64m4_t __riscv_th_vlh_v_i64m4 (const int64_t *a, size_t vl);
vint64m8_t __riscv_th_vlh_v_i64m8 (const int64_t *a, size_t vl);
vint32m1_t __riscv_th_vlw_v_i32m1 (const int32_t *a, size_t vl);
vint32m2_t __riscv_th_vlw_v_i32m2 (const int32_t *a, size_t vl);
vint32m4_t __riscv_th_vlw_v_i32m4 (const int32_t *a, size_t vl);
vint32m8_t __riscv_th_vlw_v_i32m8 (const int32_t *a, size_t vl);
vint64m1_t __riscv_th_vlw_v_i64m1 (const int64_t *a, size_t vl);
vint64m2_t __riscv_th_vlw_v_i64m2 (const int64_t *a, size_t vl);
vint64m4_t __riscv_th_vlw_v_i64m4 (const int64_t *a, size_t vl);
vint64m8_t __riscv_th_vlw_v_i64m8 (const int64_t *a, size_t vl);

With the exisiting framework, I cannot come up with better way to differentiate
between vlb/vlw.vlh.




--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月10日(星期三) 19:09
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


So vlb has not only sew = 8 ?

But why do you add intrinsics as follows ?

+DEF_RVV_FUNCTION (th_vlb, th_loadstore_width, full_preds, 
i8_v_scalar_const_ptr_ops)

Why it is not :

DEF_RVV_FUNCTION (th_vlb, th_loadstore_width, full_preds, 
all_v_scalar_const_ptr_ops)
? 

juzhe.zh...@rivai.ai
 
发件人： joshua
发送时间： 2024-01-10 19:06
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
The key difference between vlb/vlh/vlw is not output type too.
Their difference is the range of datatype, not one specific type.
We have dived into the xtheadvector special intrinsics and are
sure about that.
 
 
 
 
 
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月10日(星期三) 19:00
收件人："cooper.joshua"; 
"gcc-patches"
抄 送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主 题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
 
instance.op_info->args[i].get_tree_type (instance.type.index)  is output type.
 
 
You can use GDB debug it .
 
 
juzhe.zh...@rivai.ai
 
 
发件人： joshua
发送时间： 2024-01-10 18:57
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
Hi Juzhe,
 
Perhaps things are not as simple as imagined.
The differences between vlb/vlh/vlw is not the same
as vle8/vle16/vle32. "8", "16" or "32" in vle8/vle16/vle32
can be appended from "vle" according to input type.
But vlb/vlh/vlw is different not in input type.
 
 
 
 
 
 
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月10日(星期三) 18:03
收件人："cooper.joshua"; 
"gcc-patches"
抄 送：Jim Wilso

Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[joshua]

Can you see the images that I sent to you in the last email？
If not, maybe you can refer to the last chapter in the thead spec.






--
发件人：joshua 
发送时间：2024年1月10日(星期三) 19:06
收件人："juzhe.zh...@rivai.ai"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


The key difference between vlb/vlh/vlw is not output type too.
Their difference is the range of datatype, not one specific type. 
We have dived into the xtheadvector special intrinsics and are
sure about that.






--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月10日(星期三) 19:00
收件人："cooper.joshua"; 
"gcc-patches"
抄 送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主 题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


instance.op_info->args[i].get_tree_type (instance.type.index)  is output type.


You can use GDB debug it .


juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2024-01-10 18:57
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

Hi Juzhe,

Perhaps things are not as simple as imagined. 
The differences between vlb/vlh/vlw is not the same
as vle8/vle16/vle32. "8", "16" or "32" in vle8/vle16/vle32
can be appended from "vle" according to input type.
But vlb/vlh/vlw is different not in input type.







--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月10日(星期三) 18:03
收件人："cooper.joshua"; 
"gcc-patches"
抄 送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主 题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


I mean change these:
+DEF_RVV_FUNCTION (th_vlb, th_loadstore_width, full_preds, 
i8_v_scalar_const_ptr_ops)
+DEF_RVV_FUNCTION (th_vlh, th_loadstore_width, full_preds, 
i16_v_scalar_const_ptr_ops)
+DEF_RVV_FUNCTION (th_vlw, th_loadstore_width, full_preds, 
i32_v_scalar_const_ptr_ops)



into a single:
+DEF_RVV_FUNCTION (th_vl, th_loadstore_width, full_preds, 
all_v_scalar_const_ptr_ops)


and append "h", "w", or"b" according to 
TYPE_UNSIGNED and
GET_MODE_BITSIZE (GET_MODE_INNER (TYPE_MODE 
(instance.op_info->args[i].get_tree_type (instance.type.index



in th_loadstore_width.


It should definitely works, I allow this flexibility in design of the framework.




juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2024-01-10 17:55
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

And revise th_loadstore_width, append the name according TYPE_UNSIGNED and 
GET_MODE_BITSIZE (GET_MODE_INNER (TYPE_MODE 
(instance.op_info->args[i].get_tree_type (instance.type.index
 
What do you mean by it? I'm a bit confused.
 
Changing i8_v_scalar_const_ptr_ops into all_v_scalar_const_ptr_ops
will expand the datatypes that can be used in th_vlb. Can we restrict
again in th_loadstore_width?
 
 
 
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月10日(星期三) 17:35
收件人："cooper.joshua"; 
"gcc-patches"
抄 送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主 题：Re: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
 
+DEF_RVV_FUNCTION (th_vlb, th_loadstore_width, full_preds, 
i8_v_scalar_const_ptr_ops)
+DEF_RVV_FUNCTION (th_vlh, th_loadstore_width, full_preds, 
i16_v_scalar_const_ptr_ops)
+DEF_RVV_FUNCTION (th_vlw, th_loadstore_width, full_preds, 
i32_v_scalar_const_ptr_ops)
 
 
 
I think we should remove those many data structure you added like: 
i8_v_scalar_const_ptr_ops
Instead, you should use all_v_scalar_const_ptr_ops
 
 
And revise th_loadstore_width, append the name according TYPE_UNSIGNED and 
GET_MODE_BITSIZE (GET_MODE_INNER (TYPE_MODE 
(instance.op_info->args[i].get_tree_type (instance.type.index
 
 
 
 
juzhe.zh...@rivai.ai
 
 
From: Jun Sha (Joshua)
Date: 2024-01-10 17:27
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
This patch o

Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[joshua]

The key difference between vlb/vlh/vlw is not output type too.
Their difference is the range of datatype, not one specific type. 
We have dived into the xtheadvector special intrinsics and are
sure about that.






--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月10日(星期三) 19:00
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


instance.op_info->args[i].get_tree_type (instance.type.index)  is output type.


You can use GDB debug it .


juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2024-01-10 18:57
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

Hi Juzhe,

Perhaps things are not as simple as imagined. 
The differences between vlb/vlh/vlw is not the same
as vle8/vle16/vle32. "8", "16" or "32" in vle8/vle16/vle32
can be appended from "vle" according to input type.
But vlb/vlh/vlw is different not in input type.







--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月10日(星期三) 18:03
收件人："cooper.joshua"; 
"gcc-patches"
抄 送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主 题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


I mean change these:
+DEF_RVV_FUNCTION (th_vlb, th_loadstore_width, full_preds, 
i8_v_scalar_const_ptr_ops)
+DEF_RVV_FUNCTION (th_vlh, th_loadstore_width, full_preds, 
i16_v_scalar_const_ptr_ops)
+DEF_RVV_FUNCTION (th_vlw, th_loadstore_width, full_preds, 
i32_v_scalar_const_ptr_ops)



into a single:
+DEF_RVV_FUNCTION (th_vl, th_loadstore_width, full_preds, 
all_v_scalar_const_ptr_ops)


and append "h", "w", or"b" according to 
TYPE_UNSIGNED and
GET_MODE_BITSIZE (GET_MODE_INNER (TYPE_MODE 
(instance.op_info->args[i].get_tree_type (instance.type.index



in th_loadstore_width.


It should definitely works, I allow this flexibility in design of the framework.




juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2024-01-10 17:55
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

And revise th_loadstore_width, append the name according TYPE_UNSIGNED and 
GET_MODE_BITSIZE (GET_MODE_INNER (TYPE_MODE 
(instance.op_info->args[i].get_tree_type (instance.type.index
 
What do you mean by it? I'm a bit confused.
 
Changing i8_v_scalar_const_ptr_ops into all_v_scalar_const_ptr_ops
will expand the datatypes that can be used in th_vlb. Can we restrict
again in th_loadstore_width?
 
 
 
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月10日(星期三) 17:35
收件人："cooper.joshua"; 
"gcc-patches"
抄 送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主 题：Re: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
 
+DEF_RVV_FUNCTION (th_vlb, th_loadstore_width, full_preds, 
i8_v_scalar_const_ptr_ops)
+DEF_RVV_FUNCTION (th_vlh, th_loadstore_width, full_preds, 
i16_v_scalar_const_ptr_ops)
+DEF_RVV_FUNCTION (th_vlw, th_loadstore_width, full_preds, 
i32_v_scalar_const_ptr_ops)
 
 
 
I think we should remove those many data structure you added like: 
i8_v_scalar_const_ptr_ops
Instead, you should use all_v_scalar_const_ptr_ops
 
 
And revise th_loadstore_width, append the name according TYPE_UNSIGNED and 
GET_MODE_BITSIZE (GET_MODE_INNER (TYPE_MODE 
(instance.op_info->args[i].get_tree_type (instance.type.index
 
 
 
 
juzhe.zh...@rivai.ai
 
 
From: Jun Sha (Joshua)
Date: 2024-01-10 17:27
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
 
This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.
 
gcc/ChangeLog:
 
 * config/riscv/riscv-vector-builtins-bases.cc
 (class th_loadstore_width): Define new builtin bases.
 (BASE): Define new builtin bases.
 * config/riscv/riscv-vector-builtins-bases.h:
 Define new builtin class.
 * config/riscv/riscv-vector-builtins-functions.def (vlsegff):
 Include thead-vector-builtins-functions.def.
 * config/riscv/riscv-vector-builtins-shapes.cc
 (struct th_loadstore_width_def): Defin

Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[joshua]

And revise th_loadstore_width, append the name according TYPE_UNSIGNED and 
GET_MODE_BITSIZE (GET_MODE_INNER (TYPE_MODE 
(instance.op_info->args[i].get_tree_type (instance.type.index

What do you mean by it? I'm a bit confused.

Changing i8_v_scalar_const_ptr_ops into all_v_scalar_const_ptr_ops
will expand the datatypes that can be used in th_vlb. Can we restrict
again in th_loadstore_width?




--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月10日(星期三) 17:35
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主　题：Re: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.


+DEF_RVV_FUNCTION (th_vlb, th_loadstore_width, full_preds, 
i8_v_scalar_const_ptr_ops)
+DEF_RVV_FUNCTION (th_vlh, th_loadstore_width, full_preds, 
i16_v_scalar_const_ptr_ops)
+DEF_RVV_FUNCTION (th_vlw, th_loadstore_width, full_preds, 
i32_v_scalar_const_ptr_ops)



I think we should remove those many data structure you added like: 
i8_v_scalar_const_ptr_ops
Instead, you should use all_v_scalar_const_ptr_ops


And revise th_loadstore_width, append the name according TYPE_UNSIGNED and 
GET_MODE_BITSIZE (GET_MODE_INNER (TYPE_MODE 
(instance.op_info->args[i].get_tree_type (instance.type.index




juzhe.zh...@rivai.ai

 
From: Jun Sha (Joshua)
Date: 2024-01-10 17:27
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.
 
gcc/ChangeLog:
 
* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(BASE): Define new builtin bases.
* config/riscv/riscv-vector-builtins-bases.h:
Define new builtin class.
* config/riscv/riscv-vector-builtins-functions.def (vlsegff):
Include thead-vector-builtins-functions.def.
* config/riscv/riscv-vector-builtins-shapes.cc
(struct th_loadstore_width_def): Define new builtin shapes.
(struct th_indexed_loadstore_width_def):
Define new builtin shapes.
(SHAPE): Define new builtin shapes.
* config/riscv/riscv-vector-builtins-shapes.h:
Define new builtin shapes.
* config/riscv/riscv-vector-builtins-types.def
(DEF_RVV_I8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I32_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U32_OPS): Add datatypes for XTheadVector.
(vint8m1_t): Add datatypes for XTheadVector.
(vint8m2_t): Likewise.
(vint8m4_t): Likewise.
(vint8m8_t): Likewise.
(vint16m1_t): Likewise.
(vint16m2_t): Likewise.
(vint16m4_t): Likewise.
(vint16m8_t): Likewise.
(vint32m1_t): Likewise.
(vint32m2_t): Likewise.
(vint32m4_t): Likewise.
(vint32m8_t): Likewise.
(vint64m1_t): Likewise.
(vint64m2_t): Likewise.
(vint64m4_t): Likewise.
(vint64m8_t): Likewise.
(vuint8m1_t): Likewise.
(vuint8m2_t): Likewise.
(vuint8m4_t): Likewise.
(vuint8m8_t): Likewise.
(vuint16m1_t): Likewise.
(vuint16m2_t): Likewise.
(vuint16m4_t): Likewise.
(vuint16m8_t): Likewise.
(vuint32m1_t): Likewise.
(vuint32m2_t): Likewise.
(vuint32m4_t): Likewise.
(vuint32m8_t): Likewise.
(vuint64m1_t): Likewise.
(vuint64m2_t): Likewise.
(vuint64m4_t): Likewise.
(vuint64m8_t): Likewise.
* config/riscv/riscv-vector-builtins.cc
(DEF_RVV_I8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I32_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U32_OPS): Add datatypes for XTheadVector.
* config/riscv/thead-vector-builtins-functions.def: New file.
* config/riscv/thead-vector.md: Add new patterns.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c: New test.

[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[Jun Sha (Joshua)]

This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(BASE): Define new builtin bases.
* config/riscv/riscv-vector-builtins-bases.h:
Define new builtin class.
* config/riscv/riscv-vector-builtins-functions.def (vlsegff):
Include thead-vector-builtins-functions.def.
* config/riscv/riscv-vector-builtins-shapes.cc
(struct th_loadstore_width_def): Define new builtin shapes.
(struct th_indexed_loadstore_width_def):
Define new builtin shapes.
(SHAPE): Define new builtin shapes.
* config/riscv/riscv-vector-builtins-shapes.h:
Define new builtin shapes.
* config/riscv/riscv-vector-builtins-types.def
(DEF_RVV_I8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I32_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U32_OPS): Add datatypes for XTheadVector.
(vint8m1_t): Add datatypes for XTheadVector.
(vint8m2_t): Likewise.
(vint8m4_t): Likewise.
(vint8m8_t): Likewise.
(vint16m1_t): Likewise.
(vint16m2_t): Likewise.
(vint16m4_t): Likewise.
(vint16m8_t): Likewise.
(vint32m1_t): Likewise.
(vint32m2_t): Likewise.
(vint32m4_t): Likewise.
(vint32m8_t): Likewise.
(vint64m1_t): Likewise.
(vint64m2_t): Likewise.
(vint64m4_t): Likewise.
(vint64m8_t): Likewise.
(vuint8m1_t): Likewise.
(vuint8m2_t): Likewise.
(vuint8m4_t): Likewise.
(vuint8m8_t): Likewise.
(vuint16m1_t): Likewise.
(vuint16m2_t): Likewise.
(vuint16m4_t): Likewise.
(vuint16m8_t): Likewise.
(vuint32m1_t): Likewise.
(vuint32m2_t): Likewise.
(vuint32m4_t): Likewise.
(vuint32m8_t): Likewise.
(vuint64m1_t): Likewise.
(vuint64m2_t): Likewise.
(vuint64m4_t): Likewise.
(vuint64m8_t): Likewise.
* config/riscv/riscv-vector-builtins.cc
(DEF_RVV_I8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I32_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U32_OPS): Add datatypes for XTheadVector.
* config/riscv/thead-vector-builtins-functions.def: New file.
* config/riscv/thead-vector.md: Add new patterns.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c: New test.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 .../riscv/riscv-vector-builtins-bases.cc  | 139 
 .../riscv/riscv-vector-builtins-bases.h   |  31 ++
 .../riscv/riscv-vector-builtins-shapes.cc |  98 ++
 .../riscv/riscv-vector-builtins-shapes.h  |   3 +
 .../riscv/riscv-vector-builtins-types.def | 120 +++
 gcc/config/riscv/riscv-vector-builtins.cc | 311 ++
 gcc/config/riscv/riscv-vector-builtins.h  |   3 +
 gcc/config/riscv/t-riscv  |   1 +
 .../riscv/thead-vector-builtins-functions.def |  39 +++
 gcc/config/riscv/thead-vector.md  | 253 ++
 .../riscv/rvv/xtheadvector/vlb-vsb.c  |  68 
 .../riscv/rvv/xtheadvector/vlbu-vsb.c |  68 
 .../riscv/rvv/xtheadvector/vlh-vsh.c  |  68 
 .../riscv/rvv/xtheadvector/vlhu-vsh.c |  68 
 .../riscv/rvv/xtheadvector/vlw-vsw.c  |  68 
 .../riscv/rvv/xtheadvector/vlwu-vsw.c |  68 
 16 files changed, 1406 insertions(+)
 create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 

[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.

[Jun Sha (Joshua)]

This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(BASE): Define new builtin bases.
* config/riscv/riscv-vector-builtins-bases.h:
Define new builtin class.
* config/riscv/riscv-vector-builtins-functions.def (vlsegff):
Include thead-vector-builtins-functions.def.
* config/riscv/riscv-vector-builtins-shapes.cc
(struct th_loadstore_width_def): Define new builtin shapes.
(struct th_indexed_loadstore_width_def):
Define new builtin shapes.
(SHAPE): Define new builtin shapes.
* config/riscv/riscv-vector-builtins-shapes.h:
Define new builtin shapes.
* config/riscv/riscv-vector-builtins-types.def
(DEF_RVV_I8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I32_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U32_OPS): Add datatypes for XTheadVector.
(vint8m1_t): Add datatypes for XTheadVector.
(vint8m2_t): Likewise.
(vint8m4_t): Likewise.
(vint8m8_t): Likewise.
(vint16m1_t): Likewise.
(vint16m2_t): Likewise.
(vint16m4_t): Likewise.
(vint16m8_t): Likewise.
(vint32m1_t): Likewise.
(vint32m2_t): Likewise.
(vint32m4_t): Likewise.
(vint32m8_t): Likewise.
(vint64m1_t): Likewise.
(vint64m2_t): Likewise.
(vint64m4_t): Likewise.
(vint64m8_t): Likewise.
(vuint8m1_t): Likewise.
(vuint8m2_t): Likewise.
(vuint8m4_t): Likewise.
(vuint8m8_t): Likewise.
(vuint16m1_t): Likewise.
(vuint16m2_t): Likewise.
(vuint16m4_t): Likewise.
(vuint16m8_t): Likewise.
(vuint32m1_t): Likewise.
(vuint32m2_t): Likewise.
(vuint32m4_t): Likewise.
(vuint32m8_t): Likewise.
(vuint64m1_t): Likewise.
(vuint64m2_t): Likewise.
(vuint64m4_t): Likewise.
(vuint64m8_t): Likewise.
* config/riscv/riscv-vector-builtins.cc
(DEF_RVV_I8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I32_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U32_OPS): Add datatypes for XTheadVector.
* config/riscv/thead-vector-builtins-functions.def: New file.
* config/riscv/thead-vector.md: Add new patterns.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c: New test.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 .../riscv/riscv-vector-builtins-bases.cc  | 139 
 .../riscv/riscv-vector-builtins-bases.h   |  31 ++
 .../riscv/riscv-vector-builtins-shapes.cc |  98 ++
 .../riscv/riscv-vector-builtins-shapes.h  |   3 +
 .../riscv/riscv-vector-builtins-types.def | 120 +++
 gcc/config/riscv/riscv-vector-builtins.cc | 311 ++
 gcc/config/riscv/riscv-vector-builtins.h  |   3 +
 gcc/config/riscv/t-riscv  |   1 +
 .../riscv/thead-vector-builtins-functions.def |  39 +++
 gcc/config/riscv/thead-vector.md  | 253 ++
 .../riscv/rvv/xtheadvector/vlb-vsb.c  |  68 
 .../riscv/rvv/xtheadvector/vlbu-vsb.c |  68 
 .../riscv/rvv/xtheadvector/vlh-vsh.c  |  68 
 .../riscv/rvv/xtheadvector/vlhu-vsh.c |  68 
 .../riscv/rvv/xtheadvector/vlw-vsw.c  |  68 
 .../riscv/rvv/xtheadvector/vlwu-vsw.c |  68 
 16 files changed, 1406 insertions(+)
 create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 

Re：Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

[joshua]

I'm confused why I cannot add new shapes. I think adding
new shapes is the basic part in implementation for new
intrinsics.







--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月10日(星期三) 15:17
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector


Why do you need to invade existing shapes ?




juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2024-01-10 15:16
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

These xttheadvector speical intrinsics are different from rvv1.0
in determining function name from base name. We cannot directly
reuse the existing shapes.
 
In order not to invade existing shapes, we add new shapes for new
functions. Also, we create new thead-vector-builtins.cc for xtheadvector
function_base implementation.
 
 
 
 
 
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发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月10日(星期三) 15:01
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
 
 
Why do you add theadvector shapes ? I think you can reuse the current existing 
shapes.
 
 
+thead-vector-builtins.o: \+  $(srcdir)/config/riscv/thead-vector-builtins.cc 
\+  $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) $(RTL_H) \+  
$(TM_P_H) memmodel.h insn-codes.h $(OPTABS_H) $(RECOG_H) \+  $(EXPR_H) 
$(BASIC_BLOCK_H) $(FUNCTION_H) fold-const.h $(GIMPLE_H) \+  gimple-iterator.h 
gimplify.h explow.h $(EMIT_RTL_H) tree-vector-builder.h \+  
rtx-vector-builder.h \+  $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h 
\+  $(srcdir)/config/riscv/riscv-vector-builtins-bases.h \+  
$(srcdir)/config/riscv/thead-vector-builtins.h \+  $(RISCV_BUILTINS_H)+   
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \+  
$(srcdir)/config/riscv/thead-vector-builtins.cc+
Why do you rebuild another new object ?
 
 
+   Copyright (C) 2022-2023 Free Software Foundation, Inc.
Incorrect copyright
 
 
 
 
 
 
juzhe.zh...@rivai.ai
 
 
发件人： joshua
发送时间： 2024-01-10 10:57
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
 
Hi Juzhe,
Thank you for so many useful comments for this patch!
 
There are some more patches to support xtheadvector
special instrinsics as well as handle register overlap issue and
rewrite assembly output.
 
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641774.html
 
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641732.html
 
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641733.html
 
Also, there is a precedent patch to refactor riscv-vector-builtins-bases.cc
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641530.html
Jeff has reviewed it, but didn't have LGTM yet.
 
Joshua
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月10日(星期三) 10:34
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主　题：Re: [PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
 
 
Thanks for your patience.
 
 
LGTM from myside.
 
 
I think it's pretty clean now. I can image in the future when some day the 
theadvector is no longer used, we can remove it very easily.
 
 
And also,  the theadvector won't affect our RVV1.0 maintain since it's isolated 
cleanly. 
 
 
But I'd like to wait for a few more days some body want to chime in.
 
 
And you should do more things before commit it:
1. Remember you should run the full coverage RVV1.0 API test, the 
test-generator is downloaded from official intrinsic doc:
https://github.com/riscv-non-isa/rvv-intrinsic-doc 
 
 
2. Also the regression of RV32 an RV64 of GCC testsuite.
 
 
Do you have more patches of theadvector that I didn't review ? plz point them 
to me again.
 
 
Thanks.
juzhe.zh...@rivai.ai
 
 
From: Jun Sha (Joshua)
Date: 2024-01-10 10:22
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
 
This patch is to handle the differences in instruction generation
between Vector

回复：Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

[joshua]

For example

+/* th_loadstore_width_def class.  */
+struct th_loadstore_width_def : public build_base
+{
+  void build (function_builder ,
+ const function_group_info ) const override
+  {
+/* Report an error if there is no xtheadvector.  */
+if (!TARGET_XTHEADVECTOR)
+  return;
+
+build_all (b, group);
+  }
+
+  char *get_name (function_builder , const function_instance ,
+ bool overloaded_p) const override
+  {
+/* Report an error if there is no xtheadvector.  */
+if (!TARGET_XTHEADVECTOR)
+  return nullptr;
+
+/* Return nullptr if it can not be overloaded.  */
+if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred))
+  return nullptr;
+
+b.append_base_name (instance.base_name);
+
+/* vop_v --> vop_v_.  */
+if (!overloaded_p)
+  {
+   /* vop --> vop_v.  */
+   b.append_name (operand_suffixes[instance.op_info->op]);
+   /* vop_v --> vop_v_.  */
+   b.append_name (type_suffixes[instance.type.index].vector);
+  }
+
+/* According to rvv-intrinsic-doc, it does not add "_m" suffix
+   for vop_m C++ overloaded API.  */
+if (overloaded_p && instance.pred == PRED_TYPE_m)
+  return b.finish_name ();
+b.append_name (predication_suffixes[instance.pred]);
+return b.finish_name ();
+  }
+};

I cannot find totally the sam shape that I can reuse.
Maybe loadstore_def? But we do not need to do
vop --> vop for our new intrinsics. If we reuse
this shape, we need to add some logic here.

Also, the shape "th_extract" for "ext" is a new shape that
existing shapes haven't implemented.




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发件人：juzhe.zh...@rivai.ai 
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收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector


Why do you need to invade existing shapes ?




juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2024-01-10 15:16
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

These xttheadvector speical intrinsics are different from rvv1.0
in determining function name from base name. We cannot directly
reuse the existing shapes.
 
In order not to invade existing shapes, we add new shapes for new
functions. Also, we create new thead-vector-builtins.cc for xtheadvector
function_base implementation.
 
 
 
 
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月10日(星期三) 15:01
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
 
 
Why do you add theadvector shapes ? I think you can reuse the current existing 
shapes.
 
 
+thead-vector-builtins.o: \+  $(srcdir)/config/riscv/thead-vector-builtins.cc 
\+  $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) $(RTL_H) \+  
$(TM_P_H) memmodel.h insn-codes.h $(OPTABS_H) $(RECOG_H) \+  $(EXPR_H) 
$(BASIC_BLOCK_H) $(FUNCTION_H) fold-const.h $(GIMPLE_H) \+  gimple-iterator.h 
gimplify.h explow.h $(EMIT_RTL_H) tree-vector-builder.h \+  
rtx-vector-builder.h \+  $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h 
\+  $(srcdir)/config/riscv/riscv-vector-builtins-bases.h \+  
$(srcdir)/config/riscv/thead-vector-builtins.h \+  $(RISCV_BUILTINS_H)+   
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \+  
$(srcdir)/config/riscv/thead-vector-builtins.cc+
Why do you rebuild another new object ?
 
 
+   Copyright (C) 2022-2023 Free Software Foundation, Inc.
Incorrect copyright
 
 
 
 
 
 
juzhe.zh...@rivai.ai
 
 
发件人： joshua
发送时间： 2024-01-10 10:57
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
 
Hi Juzhe,
Thank you for so many useful comments for this patch!
 
There are some more patches to support xtheadvector
special instrinsics as well as handle register overlap issue and
rewrite assembly output.
 
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641774.html
 
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641732.html
 
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641733.html
 
Also, there is a precedent patch to refactor riscv-vector-builtins-bases.cc
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641530.html
Jeff has reviewed it, but didn't have LGTM yet.
 
Josh

Re：Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

[joshua]

These xttheadvector speical intrinsics are different from rvv1.0
in determining function name from base name. We cannot directly
reuse the existing shapes.

In order not to invade existing shapes, we add new shapes for new
functions. Also, we create new thead-vector-builtins.cc for xtheadvector
function_base implementation.





--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月10日(星期三) 15:01
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector


Why do you add theadvector shapes ? I think you can reuse the current existing 
shapes.


+thead-vector-builtins.o: \+  $(srcdir)/config/riscv/thead-vector-builtins.cc 
\+  $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) $(RTL_H) \+  
$(TM_P_H) memmodel.h insn-codes.h $(OPTABS_H) $(RECOG_H) \+  $(EXPR_H) 
$(BASIC_BLOCK_H) $(FUNCTION_H) fold-const.h $(GIMPLE_H) \+  gimple-iterator.h 
gimplify.h explow.h $(EMIT_RTL_H) tree-vector-builder.h \+  
rtx-vector-builder.h \+  $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h 
\+  $(srcdir)/config/riscv/riscv-vector-builtins-bases.h \+  
$(srcdir)/config/riscv/thead-vector-builtins.h \+  $(RISCV_BUILTINS_H)+   
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \+  
$(srcdir)/config/riscv/thead-vector-builtins.cc+
Why do you rebuild another new object ?


+   Copyright (C) 2022-2023 Free Software Foundation, Inc.
Incorrect copyright






juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2024-01-10 10:57
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

Hi Juzhe,
Thank you for so many useful comments for this patch!
 
There are some more patches to support xtheadvector
special instrinsics as well as handle register overlap issue and
rewrite assembly output.
 
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641774.html
 
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641732.html
 
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641733.html
 
Also, there is a precedent patch to refactor riscv-vector-builtins-bases.cc
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641530.html
Jeff has reviewed it, but didn't have LGTM yet.
 
Joshua
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月10日(星期三) 10:34
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主　题：Re: [PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
 
 
Thanks for your patience.
 
 
LGTM from myside.
 
 
I think it's pretty clean now. I can image in the future when some day the 
theadvector is no longer used, we can remove it very easily.
 
 
And also,  the theadvector won't affect our RVV1.0 maintain since it's isolated 
cleanly. 
 
 
But I'd like to wait for a few more days some body want to chime in.
 
 
And you should do more things before commit it:
1. Remember you should run the full coverage RVV1.0 API test, the 
test-generator is downloaded from official intrinsic doc:
https://github.com/riscv-non-isa/rvv-intrinsic-doc 
 
 
2. Also the regression of RV32 an RV64 of GCC testsuite.
 
 
Do you have more patches of theadvector that I didn't review ? plz point them 
to me again.
 
 
Thanks.
juzhe.zh...@rivai.ai
 
 
From: Jun Sha (Joshua)
Date: 2024-01-10 10:22
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
 
This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 
 
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r and vsext.vf2.
 
gcc/ChangeLog:
 
* config.gcc:  Add files for XTheadVector intrinsics.
* config/riscv/autovec.md: Guard XTheadVector.
* config/riscv/riscv-c.cc: Add pragma for XTheadVector.
* config/riscv/riscv-string.cc (expand_block_move):
Guard XTheadVecto

[PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

[Jun Sha (Joshua)]

For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions
and floating-point compare instructions, an illegal instruction
exception will be raised if the destination vector register overlaps
a source vector register group.

To handle this issue, we use "group_overlap" and "enabled" attribute
to disable some alternatives for xtheadvector.

gcc/ChangeLog:

* config/riscv/riscv.md (none,W21,W42,W84,W43,W86,W87,W0):
(none,W21,W42,W84,W43,W86,W87,W0,thv_disabled,rvv_disabled):
Add group-overlap constraint for xtheadvector.
* config/riscv/vector.md: 
Disable alternatives that destination register overlaps
source register group for xtheadvector.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config/riscv/riscv.md  |  12 +-
 gcc/config/riscv/vector.md | 314 +
 2 files changed, 190 insertions(+), 136 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 84212430dc0..411d1d17391 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -537,7 +537,7 @@
 ;; Widening instructions have group-overlap constraints.  Those are only
 ;; valid for certain register-group sizes.  This attribute marks the
 ;; alternatives not matching the required register-group size as disabled.
-(define_attr "group_overlap" "none,W21,W42,W84,W43,W86,W87,W0"
+(define_attr "group_overlap" 
"none,W21,W42,W84,W43,W86,W87,W0,thv_disabled,rvv_disabled"
   (const_string "none"))
 
 (define_attr "group_overlap_valid" "no,yes"
@@ -576,7 +576,15 @@
  (and (eq_attr "group_overlap" "W0")
  (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) 
> 1"))
 (const_string "no")
-]
+
+(and (eq_attr "group_overlap" "thv_disabled")
+ (match_test "TARGET_XTHEADVECTOR"))
+(const_string "no")
+
+(and (eq_attr "group_overlap" "rvv_disabled")
+ (match_test "TARGET_VECTOR && !TARGET_XTHEADVECTOR"))
+(const_string "no")
+   ]
(const_string "yes")))
 
 ;; Attribute to control enable or disable instructions.
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 3eb6daafbc2..4748ddd34a2 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -3260,7 +3260,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "thv_disabled,none,none")])
 
 (define_insn "@pred_msbc"
   [(set (match_operand: 0 "register_operand""=vr, vr, ")
@@ -3279,7 +3280,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "thv_disabled,thv_disabled,none")])
 
 (define_insn "@pred_madc_scalar"
   [(set (match_operand: 0 "register_operand" "=vr, ")
@@ -3299,7 +3301,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "thv_disabled,none")])
 
 (define_insn "@pred_msbc_scalar"
   [(set (match_operand: 0 "register_operand" "=vr, ")
@@ -3319,7 +3322,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "thv_disabled,none")])
 
 (define_expand "@pred_madc_scalar"
   [(set (match_operand: 0 "register_operand")
@@ -3368,7 +3372,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "thv_disabled,none")])
 
 (define_insn "*pred_madc_extended_scalar"
   [(set (match_operand: 0 "register_operand" "=vr, ")
@@ -3389,7 +3394,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "thv_disabled,none")])
 
 (define_expand "@pred_msbc_scalar"
   [(set (match_operand: 0 "register_operand")
@@ -3438,7 +3444,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "thv_disabled,none")])
 
 (define_insn "*pred_msbc_extended_scalar"
   [(set (match_operand: 0 "register_operand"  "=vr, ")
@@ -3459,7 +3466,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") 

[PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

[Jun Sha (Joshua)]

For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions
and floating-point compare instructions, an illegal instruction
exception will be raised if the destination vector register overlaps
a source vector register group.

To handle this issue, we use "group_overlap" and "enabled" attribute
to disable some alternatives for xtheadvector.

gcc/ChangeLog:

* config/riscv/riscv.md (none,W21,W42,W84,W43,W86,W87,W0):
(none,W21,W42,W84,W43,W86,W87,W0,th):
Add group-overlap constraint for xtheadvector.
* config/riscv/vector.md: 
Disable alternatives that destination register overlaps
source register group for xtheadvector.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config/riscv/riscv.md  |  12 +-
 gcc/config/riscv/vector.md | 314 +
 2 files changed, 190 insertions(+), 136 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 84212430dc0..2fe15fd7340 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -537,7 +537,7 @@
 ;; Widening instructions have group-overlap constraints.  Those are only
 ;; valid for certain register-group sizes.  This attribute marks the
 ;; alternatives not matching the required register-group size as disabled.
-(define_attr "group_overlap" "none,W21,W42,W84,W43,W86,W87,W0"
+(define_attr "group_overlap" "none,W21,W42,W84,W43,W86,W87,W0,th,rvv"
   (const_string "none"))
 
 (define_attr "group_overlap_valid" "no,yes"
@@ -576,7 +576,15 @@
  (and (eq_attr "group_overlap" "W0")
  (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) 
> 1"))
 (const_string "no")
-]
+
+(and (eq_attr "group_overlap" "th")
+ (match_test "TARGET_XTHEADVECTOR"))
+(const_string "no")
+
+(and (eq_attr "group_overlap" "rvv")
+ (match_test "TARGET_VECTOR && !TARGET_XTHEADVECTOR"))
+(const_string "no")
+   ]
(const_string "yes")))
 
 ;; Attribute to control enable or disable instructions.
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 3eb6daafbc2..cd83c1f3321 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -3260,7 +3260,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none,none")])
 
 (define_insn "@pred_msbc"
   [(set (match_operand: 0 "register_operand""=vr, vr, ")
@@ -3279,7 +3280,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,th,none")])
 
 (define_insn "@pred_madc_scalar"
   [(set (match_operand: 0 "register_operand" "=vr, ")
@@ -3299,7 +3301,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none")])
 
 (define_insn "@pred_msbc_scalar"
   [(set (match_operand: 0 "register_operand" "=vr, ")
@@ -3319,7 +3322,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none")])
 
 (define_expand "@pred_madc_scalar"
   [(set (match_operand: 0 "register_operand")
@@ -3368,7 +3372,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none")])
 
 (define_insn "*pred_madc_extended_scalar"
   [(set (match_operand: 0 "register_operand" "=vr, ")
@@ -3389,7 +3394,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none")])
 
 (define_expand "@pred_msbc_scalar"
   [(set (match_operand: 0 "register_operand")
@@ -3438,7 +3444,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none")])
 
 (define_insn "*pred_msbc_extended_scalar"
   [(set (match_operand: 0 "register_operand"  "=vr, ")
@@ -3459,7 +3466,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none")])
 
 (define_insn "@pred_madc_overflow"
   

Re：Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

[joshua]

Hi Kito,

Thank you for your support again.
I believe we can get all our xtheadvector patches
ready before the end of Feb.

May I please ping the arch patch again?
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641801.html
This is the patch that all the following patches rely on.

Joshua






--
发件人：Kito Cheng 
发送时间：2024年1月8日(星期一) 11:40
收件人：joshua
抄　送："juzhe.zh...@rivai.ai"; 
jeffreyalaw; "gcc-patches"; Jim 
Wilson; palmer; 
andrew; "philipp.tomsich"; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of 
XTheadVector.


It depends on the timing when you send out the v1 patch to the mailing
list, not the timing of when to merge, but of course it's case by
case, I would say no IF it's still not ready when time is the end of
Feb for this kind of big patch set.

On Mon, Jan 8, 2024 at 11:17 AM joshua  wrote:
>
> Hi Kito,
>
> Thank you for your support.
> So even during stage 4, we can merge this for GCC 14?
>
>
>
>
>
> ------
> 发件人：Kito Cheng 
> 发送时间：2024年1月8日(星期一) 11:06
> 收件人：joshua
> 抄 送："juzhe.zh...@rivai.ai"; 
> jeffreyalaw; "gcc-patches"; 
> Jim Wilson; palmer; 
> andrew; "philipp.tomsich"; 
> "christoph.muellner"; 
> jinma; "cooper.qu"
> 主 题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of 
> XTheadVector.
>
>
> I am ok with merging this for GCC 14, as we discussed several times in
> the RISC-V GCC sync up meeting, I think at least we reach consensus
> among Jeff Law, Palmer Dabbelt and me.
>
> But please be careful: don't break anything for standard vector stuff.
>
> On Mon, Jan 8, 2024 at 10:11 AM joshua  
> wrote:
> >
> > Hi Juzhe,
> >
> > Stage 3 will close today and there are still some patches that
> > haven't been reviewed left.
> > So is it possible to get xtheadvector merged in GCC-14?
> > We emailed Kito regarding this, but haven't got any reply yet.
> >
> > Joshua
> >
> >
> >
> >
> >
> >
> > --
> > 发件人：juzhe.zh...@rivai.ai 
> > 发送时间：2024年1月4日(星期四) 17:18
> > 收件人："cooper.joshua"; 
> > jeffreyalaw; "gcc-patches"
> > 抄 送：Jim Wilson; palmer; 
> > andrew; "philipp.tomsich"; 
> > "christoph.muellner"; 
> > jinma; "cooper.qu"
> > 主 题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions 
> > of XTheadVector.
> >
> >
> > \ No newline at end of file
> > Each file needs newline.
> >
> >
> > I am not able to review arch stuff. This needs kito.
> >
> >
> > Besides, Andrew Pinski want us defer theadvector to GCC-15.
> >
> >
> > I have no strong opinion here.
> >
> >
> > juzhe.zh...@rivai.ai
> >
> >
> > 发件人： joshua
> > 发送时间： 2024-01-04 17:15
> > 收件人： 钟居哲; Jeff Law; gcc-patches
> > 抄送： jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; 
> > jinma; Cooper Qu
> > 主题： Re：Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of 
> > XTheadVector.
> >
> > Hi Juzhe,
> >
> > So is the following patch that this patch relies on OK to commit?
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
> >
> > Joshua
> >
> >
> >
> >
> > --
> > 发件人：钟居哲 
> > 发送时间：2024年1月2日(星期二) 06:57
> > 收件人：Jeff Law; 
> > "cooper.joshua"; 
> > "gcc-patches"
> > 抄 送："jim.wilson.gcc"; palmer; 
> > andrew; "philipp.tomsich"; 
> > "Christoph Müllner"; 
> > jinma; Cooper Qu
> > 主 题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions 
> > of XTheadVector.
> >
> >
> > This is Ok from my side.
> > But before commit this patch, I think we need this patch first:
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
> >
> >
> > I will be back to work so I will take a look at other patches today.
> > juzhe.zh...@rivai.ai
> >
> >
> > From: Jeff Law
> > Date: 2024-01-01 01:43
> > To: Jun Sha (Joshua); gcc-patches
> > CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; 
> > juzhe.zhong; Jin Ma; Xianmiao Qu

Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

[joshua]

Hi Juzhe,
Thank you for so many useful comments for this patch!

There are some more patches to support xtheadvector
special instrinsics as well as handle register overlap issue and
rewrite assembly output.

https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641774.html

https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641732.html

https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641733.html

Also, there is a precedent patch to refactor riscv-vector-builtins-bases.cc
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641530.html
Jeff has reviewed it, but didn't have LGTM yet.

Joshua

--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月10日(星期三) 10:34
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主　题：Re: [PATCH v5] RISC-V: Handle differences between XTheadvector and Vector


Thanks for your patience.


LGTM from myside.


I think it's pretty clean now. I can image in the future when some day the 
theadvector is no longer used, we can remove it very easily.


And also,  the theadvector won't affect our RVV1.0 maintain since it's isolated 
cleanly. 


But I'd like to wait for a few more days some body want to chime in.


And you should do more things before commit it:
1. Remember you should run the full coverage RVV1.0 API test, the 
test-generator is downloaded from official intrinsic doc:
https://github.com/riscv-non-isa/rvv-intrinsic-doc 


2. Also the regression of RV32 an RV64 of GCC testsuite.


Do you have more patches of theadvector that I didn't review ? plz point them 
to me again.


Thanks.
juzhe.zh...@rivai.ai

 
From: Jun Sha (Joshua)
Date: 2024-01-10 10:22
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 
 
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r and vsext.vf2.
 
gcc/ChangeLog:
 
* config.gcc:  Add files for XTheadVector intrinsics.
* config/riscv/autovec.md: Guard XTheadVector.
* config/riscv/riscv-c.cc: Add pragma for XTheadVector.
* config/riscv/riscv-string.cc (expand_block_move):
Guard XTheadVector.
* config/riscv/riscv-string.cc (vls_mode_valid_p): 
Avoid autovec.
* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
(build_one): New function.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
(DEF_THEAD_RVV_FUNCTION): Add new marcos.
(check_required_extensions):
(handle_pragma_vector):
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR):
(RVV_REQUIRE_XTHEADVECTOR):
Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR.
(struct function_group_info):
* config/riscv/riscv-vector-switch.def (ENTRY):
Disable fractional mode for the XTheadVector extension.
(TUPLE_ENTRY): Likewise.
* config/riscv/riscv-vsetvl.cc: Add functions for xtheadvector.
* config/riscv/riscv.cc (riscv_v_ext_vls_mode_p):
Guard XTheadVector.
(riscv_v_adjust_bytesize): Likewise.
(riscv_preferred_simd_mode): Likewsie.
(riscv_autovectorize_vector_modes): Likewise.
(riscv_vector_mode_supported_any_target_p): Likewise.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
* config/riscv/vector.md: Include thead-vector.md.
* config/riscv/riscv_th_vector.h: New file.
* config/riscv/thead-vector.md: New file.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector.
* gcc.target/riscv/rvv/base/abi-1.c: Exclude XTheadVector.
* lib/target-supports.exp: Add target for XTheadVector.
 
Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config.gcc    |   2 +-
 gcc/config/riscv/autovec.md   |   2 +-
 gcc/config/riscv/predicates.md    |   4 +-
 gcc/config/riscv/riscv-c.cc   |   3 +-
 gcc/config/riscv/riscv-string.cc  |   3 +-
 gcc/config/riscv/riscv-v.cc

[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

[Jun Sha (Joshua)]

This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 

For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r and vsext.vf2.

gcc/ChangeLog:

* config.gcc:  Add files for XTheadVector intrinsics.
* config/riscv/autovec.md: Guard XTheadVector.
* config/riscv/riscv-c.cc: Add pragma for XTheadVector.
* config/riscv/riscv-string.cc (expand_block_move):
Guard XTheadVector.
* config/riscv/riscv-string.cc (vls_mode_valid_p): 
Avoid autovec.
* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
(build_one): New function.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
(DEF_THEAD_RVV_FUNCTION): Add new marcos.
(check_required_extensions):
(handle_pragma_vector):
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR):
(RVV_REQUIRE_XTHEADVECTOR):
Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR.
(struct function_group_info):
* config/riscv/riscv-vector-switch.def (ENTRY):
Disable fractional mode for the XTheadVector extension.
(TUPLE_ENTRY): Likewise.
* config/riscv/riscv-vsetvl.cc: Add functions for xtheadvector.
* config/riscv/riscv.cc (riscv_v_ext_vls_mode_p):
Guard XTheadVector.
(riscv_v_adjust_bytesize): Likewise.
(riscv_preferred_simd_mode): Likewsie.
(riscv_autovectorize_vector_modes): Likewise.
(riscv_vector_mode_supported_any_target_p): Likewise.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
* config/riscv/vector.md: Include thead-vector.md.
* config/riscv/riscv_th_vector.h: New file.
* config/riscv/thead-vector.md: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector.
* gcc.target/riscv/rvv/base/abi-1.c: Exclude XTheadVector.
* lib/target-supports.exp: Add target for XTheadVector.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/autovec.md   |   2 +-
 gcc/config/riscv/predicates.md|   4 +-
 gcc/config/riscv/riscv-c.cc   |   3 +-
 gcc/config/riscv/riscv-string.cc  |   3 +-
 gcc/config/riscv/riscv-v.cc   |   2 +-
 .../riscv/riscv-vector-builtins-bases.cc  |  48 --
 .../riscv/riscv-vector-builtins-shapes.cc |  23 +++
 gcc/config/riscv/riscv-vector-switch.def  | 150 +-
 gcc/config/riscv/riscv.cc |  20 ++-
 gcc/config/riscv/riscv_th_vector.h|  49 ++
 gcc/config/riscv/thead-vector.md  | 102 
 gcc/config/riscv/thead.cc |  23 ++-
 gcc/config/riscv/vector.md|  49 --
 .../gcc.target/riscv/rvv/base/abi-1.c |   2 +-
 .../gcc.target/riscv/rvv/base/pragma-1.c  |   2 +-
 gcc/testsuite/lib/target-supports.exp |  12 ++
 17 files changed, 383 insertions(+), 113 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_th_vector.h
 create mode 100644 gcc/config/riscv/thead-vector.md

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 7e583390024..047e4c02cf4 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,7 +549,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_th_vector.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 775eaa825b0..0477781cabe 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2579,7 +2579,7 @@
   [(match_operand  0 "register_operand")
(match_operand  1 "memory_operand")
(match_operand:ANYI 2 "const_int_operand")]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   {
 riscv_vector::expand_rawmemchr(mode, operands[0], operands[1],
   operands[2]);
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 

Re：[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector

[joshua]

It has been updated.
[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector (gnu.org)




--
发件人：钟居哲 
发送时间：2024年1月9日(星期二) 07:08
收件人："cooper.joshua"; 
"gcc-patches"
抄　送："jim.wilson.gcc"; palmer; 
andrew; "philipp.tomsich"; Jeff 
Law; "Christoph Müllner"; 
"cooper.joshua"; 
jinma; Cooper Qu
主　题：Re: [PATCH v4] RISC-V: Handle differences between XTheadvector and Vector


-  return TAIL_ANY;
+  return TARGET_XTHEADVECTOR ? TAIL_AGNOSTIC : TAIL_ANY;



-  return MASK_ANY;
+  return TARGET_XTHEADVECTOR ? MASK_UNDISTURBED : MASK_ANY;



You shouldn't change this.


-  "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"
+  { return TARGET_XTHEADVECTOR ? "vsetvli\t%0,%1,e%2,%m3" : 
"vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"; }

I prefer do it in ASM_OUTPUT


+   Copyright (C) 2022-2023 Free Software Foundation, Inc.


Copyright is not correct.


juzhe.zh...@rivai.ai

 
From: Jun Sha (Joshua)
Date: 2024-01-03 14:15
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v4] RISC-V: Handle differences between XTheadvector and Vector

This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 
 
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r and vsext.vf2.
 
gcc/ChangeLog:
 
* config.gcc:  Add files for XTheadVector intrinsics.
* config/riscv/autovec.md: Guard XTheadVector.
* config/riscv/riscv-c.cc: Add pragma for XTheadVector.
* config/riscv/riscv-string.cc (expand_block_move):
Guard XTheadVector.
(get_prefer_tail_policy): Give specific value for tail.
(get_prefer_mask_policy): Give specific value for mask.
(vls_mode_valid_p): Avoid autovec.
* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
(build_one): New function.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
(DEF_THEAD_RVV_FUNCTION): Add new marcos.
(check_required_extensions):
(handle_pragma_vector):
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR):
(RVV_REQUIRE_XTHEADVECTOR):
Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR.
(struct function_group_info):
* config/riscv/riscv-vector-switch.def (ENTRY):
Disable fractional mode for the XTheadVector extension.
(TUPLE_ENTRY): Likewise.
* config/riscv/riscv-vsetvl.cc: Add functions for xtheadvector.
* config/riscv/riscv.cc (riscv_v_ext_vls_mode_p):
Guard XTheadVector.
(riscv_v_adjust_bytesize): Likewise.
(riscv_preferred_simd_mode): Likewsie.
(riscv_autovectorize_vector_modes): Likewise.
(riscv_vector_mode_supported_any_target_p): Likewise.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
* config/riscv/vector-iterators.md: Remove fractional LMUL.
* config/riscv/vector.md: Include thead-vector.md.
* config/riscv/riscv_th_vector.h: New file.
* config/riscv/thead-vector.md: New file.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector.
* gcc.target/riscv/rvv/base/abi-1.c: Exclude XTheadVector.
* lib/target-supports.exp: Add target for XTheadVector.
 
Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config.gcc    |   2 +-
 gcc/config/riscv/autovec.md   |   2 +-
 gcc/config/riscv/predicates.md    |   4 +-
 gcc/config/riscv/riscv-c.cc   |   3 +-
 gcc/config/riscv/riscv-string.cc  |   3 +-
 gcc/config/riscv/riscv-v.cc   |   6 +-
 .../riscv/riscv-vector-builtins-bases.cc  |  48 +++--
 .../riscv/riscv-vector-builtins-shapes.cc |  23 +++
 gcc/config/riscv/riscv-vector-switch.def  | 150 +++---
 gcc/config/riscv/riscv.cc |  20 +-
 gcc/config/riscv/riscv_th_vector.h    |  49 +
 gcc/config/riscv/thead-vector.md  |  69 +++
 gcc/config/riscv/vector-iterators.md  | 186 +-
 gcc/config/riscv/vector.md    |  55 --
 .../gcc.target/riscv/rvv/base/abi-1.c |   2 +-
 .../gcc.target/riscv/rvv/base/pragma-1.c  |   2 

[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector

[Jun Sha (Joshua)]

This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 

For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r and vsext.vf2.

gcc/ChangeLog:

* config.gcc:  Add files for XTheadVector intrinsics.
* config/riscv/autovec.md: Guard XTheadVector.
* config/riscv/riscv-c.cc: Add pragma for XTheadVector.
* config/riscv/riscv-string.cc (expand_block_move):
Guard XTheadVector.
(get_prefer_tail_policy): Give specific value for tail.
(get_prefer_mask_policy): Give specific value for mask.
(vls_mode_valid_p): Avoid autovec.
* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
(build_one): New function.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
(DEF_THEAD_RVV_FUNCTION): Add new marcos.
(check_required_extensions):
(handle_pragma_vector):
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR):
(RVV_REQUIRE_XTHEADVECTOR):
Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR.
(struct function_group_info):
* config/riscv/riscv-vector-switch.def (ENTRY):
Disable fractional mode for the XTheadVector extension.
(TUPLE_ENTRY): Likewise.
* config/riscv/riscv-vsetvl.cc: Add functions for xtheadvector.
* config/riscv/riscv.cc (riscv_v_ext_vls_mode_p):
Guard XTheadVector.
(riscv_v_adjust_bytesize): Likewise.
(riscv_preferred_simd_mode): Likewsie.
(riscv_autovectorize_vector_modes): Likewise.
(riscv_vector_mode_supported_any_target_p): Likewise.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
* config/riscv/vector-iterators.md: Remove fractional LMUL.
* config/riscv/vector.md: Include thead-vector.md.
* config/riscv/riscv_th_vector.h: New file.
* config/riscv/thead-vector.md: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector.
* gcc.target/riscv/rvv/base/abi-1.c: Exclude XTheadVector.
* lib/target-supports.exp: Add target for XTheadVector.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/autovec.md   |   2 +-
 gcc/config/riscv/predicates.md|   4 +-
 gcc/config/riscv/riscv-c.cc   |   3 +-
 gcc/config/riscv/riscv-string.cc  |   3 +-
 gcc/config/riscv/riscv-v.cc   |   2 +-
 .../riscv/riscv-vector-builtins-bases.cc  |  48 +++--
 .../riscv/riscv-vector-builtins-shapes.cc |  23 +++
 gcc/config/riscv/riscv-vector-switch.def  | 150 +++---
 gcc/config/riscv/riscv.cc |  20 +-
 gcc/config/riscv/riscv_th_vector.h|  49 +
 gcc/config/riscv/thead-vector.md  | 102 ++
 gcc/config/riscv/thead.cc |  23 ++-
 gcc/config/riscv/vector-iterators.md  | 186 +-
 gcc/config/riscv/vector.md|  49 -
 .../gcc.target/riscv/rvv/base/abi-1.c |   2 +-
 .../gcc.target/riscv/rvv/base/pragma-1.c  |   2 +-
 gcc/testsuite/lib/target-supports.exp |  12 ++
 18 files changed, 476 insertions(+), 206 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_th_vector.h
 create mode 100644 gcc/config/riscv/thead-vector.md

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 7e583390024..047e4c02cf4 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,7 +549,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_th_vector.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 775eaa825b0..0477781cabe 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2579,7 +2579,7 @@
   [(match_operand  0 "register_operand")
(match_operand  1 "memory_operand")
(match_operand:ANYI 2 "const_int_operand")]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && 

Re：[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector

[joshua]

For the vsetvl issue, we have discussed last week. 
Maybe riscv_asm_output function cannot return
instructions like riscv_output_move.
The briefest approach may be to add some logic in
the vsetvl patterns. Only 3 patterns need to be modified
and that will not be  too invasive.







--
发件人：钟居哲 
发送时间：2024年1月9日(星期二) 07:08
收件人："cooper.joshua"; 
"gcc-patches"
抄　送："jim.wilson.gcc"; palmer; 
andrew; "philipp.tomsich"; Jeff 
Law; "Christoph Müllner"; 
"cooper.joshua"; 
jinma; Cooper Qu
主　题：Re: [PATCH v4] RISC-V: Handle differences between XTheadvector and Vector


-  return TAIL_ANY;
+  return TARGET_XTHEADVECTOR ? TAIL_AGNOSTIC : TAIL_ANY;



-  return MASK_ANY;
+  return TARGET_XTHEADVECTOR ? MASK_UNDISTURBED : MASK_ANY;



You shouldn't change this.


-  "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"
+  { return TARGET_XTHEADVECTOR ? "vsetvli\t%0,%1,e%2,%m3" : 
"vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"; }

I prefer do it in ASM_OUTPUT


+   Copyright (C) 2022-2023 Free Software Foundation, Inc.


Copyright is not correct.


juzhe.zh...@rivai.ai

 
From: Jun Sha (Joshua)
Date: 2024-01-03 14:15
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v4] RISC-V: Handle differences between XTheadvector and Vector

This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 
 
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r and vsext.vf2.
 
gcc/ChangeLog:
 
* config.gcc:  Add files for XTheadVector intrinsics.
* config/riscv/autovec.md: Guard XTheadVector.
* config/riscv/riscv-c.cc: Add pragma for XTheadVector.
* config/riscv/riscv-string.cc (expand_block_move):
Guard XTheadVector.
(get_prefer_tail_policy): Give specific value for tail.
(get_prefer_mask_policy): Give specific value for mask.
(vls_mode_valid_p): Avoid autovec.
* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
(build_one): New function.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
(DEF_THEAD_RVV_FUNCTION): Add new marcos.
(check_required_extensions):
(handle_pragma_vector):
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR):
(RVV_REQUIRE_XTHEADVECTOR):
Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR.
(struct function_group_info):
* config/riscv/riscv-vector-switch.def (ENTRY):
Disable fractional mode for the XTheadVector extension.
(TUPLE_ENTRY): Likewise.
* config/riscv/riscv-vsetvl.cc: Add functions for xtheadvector.
* config/riscv/riscv.cc (riscv_v_ext_vls_mode_p):
Guard XTheadVector.
(riscv_v_adjust_bytesize): Likewise.
(riscv_preferred_simd_mode): Likewsie.
(riscv_autovectorize_vector_modes): Likewise.
(riscv_vector_mode_supported_any_target_p): Likewise.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
* config/riscv/vector-iterators.md: Remove fractional LMUL.
* config/riscv/vector.md: Include thead-vector.md.
* config/riscv/riscv_th_vector.h: New file.
* config/riscv/thead-vector.md: New file.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector.
* gcc.target/riscv/rvv/base/abi-1.c: Exclude XTheadVector.
* lib/target-supports.exp: Add target for XTheadVector.
 
Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config.gcc    |   2 +-
 gcc/config/riscv/autovec.md   |   2 +-
 gcc/config/riscv/predicates.md    |   4 +-
 gcc/config/riscv/riscv-c.cc   |   3 +-
 gcc/config/riscv/riscv-string.cc  |   3 +-
 gcc/config/riscv/riscv-v.cc   |   6 +-
 .../riscv/riscv-vector-builtins-bases.cc  |  48 +++--
 .../riscv/riscv-vector-builtins-shapes.cc |  23 +++
 gcc/config/riscv/riscv-vector-switch.def  | 150 +++---
 gcc/config/riscv/riscv.cc |  20 +-
 gcc/config/riscv/riscv_th_vector.h    |  49 +
 gcc/config/riscv/thead-vector.md  |  69 +++
 gcc/config/riscv/vector-iterators.md  | 186 +++

Re：Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

[joshua]

Hi Kito,

Thank you for your support.
So even during stage 4, we can merge this for GCC 14?





--
发件人：Kito Cheng 
发送时间：2024年1月8日(星期一) 11:06
收件人：joshua
抄　送："juzhe.zh...@rivai.ai"; 
jeffreyalaw; "gcc-patches"; Jim 
Wilson; palmer; 
andrew; "philipp.tomsich"; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of 
XTheadVector.


I am ok with merging this for GCC 14, as we discussed several times in
the RISC-V GCC sync up meeting, I think at least we reach consensus
among Jeff Law, Palmer Dabbelt and me.

But please be careful: don't break anything for standard vector stuff.

On Mon, Jan 8, 2024 at 10:11 AM joshua  wrote:
>
> Hi Juzhe,
>
> Stage 3 will close today and there are still some patches that
> haven't been reviewed left.
> So is it possible to get xtheadvector merged in GCC-14?
> We emailed Kito regarding this, but haven't got any reply yet.
>
> Joshua
>
>
>
>
>
>
> --
> 发件人：juzhe.zh...@rivai.ai 
> 发送时间：2024年1月4日(星期四) 17:18
> 收件人："cooper.joshua"; 
> jeffreyalaw; "gcc-patches"
> 抄 送：Jim Wilson; palmer; 
> andrew; "philipp.tomsich"; 
> "christoph.muellner"; 
> jinma; "cooper.qu"
> 主 题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of 
> XTheadVector.
>
>
> \ No newline at end of file
> Each file needs newline.
>
>
> I am not able to review arch stuff. This needs kito.
>
>
> Besides, Andrew Pinski want us defer theadvector to GCC-15.
>
>
> I have no strong opinion here.
>
>
> juzhe.zh...@rivai.ai
>
>
> 发件人： joshua
> 发送时间： 2024-01-04 17:15
> 收件人： 钟居哲; Jeff Law; gcc-patches
> 抄送： jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; 
> jinma; Cooper Qu
> 主题： Re：Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of 
> XTheadVector.
>
> Hi Juzhe,
>
> So is the following patch that this patch relies on OK to commit?
> https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
>
> Joshua
>
>
>
>
> --
> 发件人：钟居哲 
> 发送时间：2024年1月2日(星期二) 06:57
> 收件人：Jeff Law; 
> "cooper.joshua"; 
> "gcc-patches"
> 抄 送："jim.wilson.gcc"; palmer; 
> andrew; "philipp.tomsich"; 
> "Christoph Müllner"; 
> jinma; Cooper Qu
> 主 题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of 
> XTheadVector.
>
>
> This is Ok from my side.
> But before commit this patch, I think we need this patch first:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
>
>
> I will be back to work so I will take a look at other patches today.
> juzhe.zh...@rivai.ai
>
>
> From: Jeff Law
> Date: 2024-01-01 01:43
> To: Jun Sha (Joshua); gcc-patches
> CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; 
> juzhe.zhong; Jin Ma; Xianmiao Qu
> Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of 
> XTheadVector.
>
>
>
> On 12/28/23 21:19, Jun Sha (Joshua) wrote:
> > This patch adds th. prefix to all XTheadVector instructions by
> > implementing new assembly output functions. We only check the
> > prefix is 'v', so that no extra attribute is needed.
> >
> > gcc/ChangeLog:
> >
> >       * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
> >       New function to add assembler insn code prefix/suffix.
> >       * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
> >       * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
> >
> > Co-authored-by: Jin Ma 
> > Co-authored-by: Xianmiao Qu 
> > Co-authored-by: Christoph Müllner 
> > ---
> >   gcc/config/riscv/riscv-protos.h                    |  1 +
> >   gcc/config/riscv/riscv.cc                          | 14 ++
> >   gcc/config/riscv/riscv.h                           |  4 
> >   .../gcc.target/riscv/rvv/xtheadvector/prefix.c     | 12 
> >   4 files changed, 31 insertions(+)
> >   create mode 100644 
> > gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
> >
> > diff --git a/gcc/config/riscv/riscv-protos.h 
> > b/gcc/config/riscv/riscv-protos.h
> > index 31049ef7523..5ea54b45703 100644
> > --- a/gcc/config/riscv/riscv-protos.h
> > +++ b/gcc/config/riscv/riscv-protos.h
> > @@ -102,6 +102,7 @@ struct riscv_address_info {
> > 

Re：Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

[joshua]

Hi Juzhe,

Stage 3 will close today and there are still some patches that
haven't been reviewed left. 
So is it possible to get xtheadvector merged in GCC-14?
We emailed Kito regarding this, but haven't got any reply yet.

Joshua






--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月4日(星期四) 17:18
收件人："cooper.joshua"; 
jeffreyalaw; "gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of 
XTheadVector.


\ No newline at end of file
Each file needs newline.


I am not able to review arch stuff. This needs kito.


Besides, Andrew Pinski want us defer theadvector to GCC-15.


I have no strong opinion here.


juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2024-01-04 17:15
收件人： 钟居哲; Jeff Law; gcc-patches
抄送： jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; jinma; 
Cooper Qu
主题： Re：Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of 
XTheadVector.

Hi Juzhe,
 
So is the following patch that this patch relies on OK to commit?
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
 
Joshua
 
 
 
 
--
发件人：钟居哲 
发送时间：2024年1月2日(星期二) 06:57
收件人：Jeff Law; 
"cooper.joshua"; 
"gcc-patches"
抄　送："jim.wilson.gcc"; palmer; 
andrew; "philipp.tomsich"; 
"Christoph Müllner"; 
jinma; Cooper Qu
主　题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of 
XTheadVector.
 
 
This is Ok from my side.
But before commit this patch, I think we need this patch first:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html 
 
 
I will be back to work so I will take a look at other patches today.
juzhe.zh...@rivai.ai
 
 
From: Jeff Law
Date: 2024-01-01 01:43
To: Jun Sha (Joshua); gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; 
juzhe.zhong; Jin Ma; Xianmiao Qu
Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of 
XTheadVector.
 
 
 
On 12/28/23 21:19, Jun Sha (Joshua) wrote:
> This patch adds th. prefix to all XTheadVector instructions by
> implementing new assembly output functions. We only check the
> prefix is 'v', so that no extra attribute is needed.
> 
> gcc/ChangeLog:
> 
>   * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
>   New function to add assembler insn code prefix/suffix.
>   * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
>   * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
> 
> Co-authored-by: Jin Ma 
> Co-authored-by: Xianmiao Qu 
> Co-authored-by: Christoph Müllner 
> ---
>   gcc/config/riscv/riscv-protos.h    |  1 +
>   gcc/config/riscv/riscv.cc  | 14 ++
>   gcc/config/riscv/riscv.h   |  4 
>   .../gcc.target/riscv/rvv/xtheadvector/prefix.c | 12 
>   4 files changed, 31 insertions(+)
>   create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
> 
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 31049ef7523..5ea54b45703 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -102,6 +102,7 @@ struct riscv_address_info {
>   };
>   
>   /* Routines implemented in riscv.cc.  */
> +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char 
> *p);
>   extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
>   extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
>   extern int riscv_float_const_rtx_index_for_fli (rtx);
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 0d1cbc5cb5f..ea1d59d9cf2 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode)
> return lmul;
>   }
>   
> +/* Define ASM_OUTPUT_OPCODE to do anything special before
> +   emitting an opcode.  */
> +const char *
> +riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
> +{
> +  /* We need to add th. prefix to all the xtheadvector
> + insturctions here.*/
> +  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
> +  p[0] == 'v')
> +    fputs ("th.", asm_out_file);
> +
> +  return p;
Just a formatting nit. The GNU standards break lines before the 
operator, not after.  So
   if (TARGET_XTHEADVECTOR
   && current_output_insn != NULL
   && p[0] == 'v')
 
Note that current_output_insn is "extern rtx_insn *", so use NULL, not 
NULL_RTX.
 
Neither of these nits require a new version for review.  Just fix them.
 
If Juzhe is fine with this, so am I.  We can refine it if necessary later.
 
jeff
 
 
 

[PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0

[Jun Sha (Joshua)]

This patch is to introduce basic XTheadVector support
(march string parsing and a test for __riscv_xtheadvector)
according to https://github.com/T-head-Semi/thead-extension-spec/

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_subset_list::parse): Add new vendor extension.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
Add test marco.
* config/riscv/riscv.opt:  Add new mask.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-__riscv_th_v_intrinsic.c: New test.
* gcc.target/riscv/rvv/xtheadvector.c: New test.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/common/config/riscv/riscv-common.cc   | 23 +++
 gcc/config/riscv/riscv-c.cc   |  8 +--
 gcc/config/riscv/riscv.opt|  2 ++
 .../riscv/predef-__riscv_th_v_intrinsic.c | 11 +
 .../gcc.target/riscv/rvv/xtheadvector.c   | 13 +++
 5 files changed, 55 insertions(+), 2 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 0301d170a41..449722070d4 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -368,6 +368,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadvector", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
 
@@ -1251,6 +1252,15 @@ riscv_subset_list::check_conflict_ext ()
   if (lookup ("zcmp"))
error_at (m_loc, "%<-march=%s%>: zcd conflicts with zcmp", m_arch);
 }
+
+  if ((lookup ("v") || lookup ("zve32x")
+|| lookup ("zve64x") || lookup ("zve32f")
+|| lookup ("zve64f") || lookup ("zve64d")
+|| lookup ("zvl32b") || lookup ("zvl64b")
+|| lookup ("zvl128b") || lookup ("zvfh"))
+&& lookup ("xtheadvector"))
+error_at (m_loc, "%<-march=%s%>: xtheadvector conflicts with vector "
+  "extension or its sub-extensions", m_arch);
 }
 
 /* Parsing function for multi-letter extensions.
@@ -1743,6 +1753,19 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"xtheadmemidx",  _options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
   {"xtheadmempair", _options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
   {"xtheadsync",_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
+  {"xtheadvector",  _options::x_riscv_xthead_subext, MASK_XTHEADVECTOR},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_32},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_64},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_32},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_64},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_16},
+  {"xtheadvector",  _options::x_riscv_zvl_flags, MASK_ZVL32B},
+  {"xtheadvector",  _options::x_riscv_zvl_flags, MASK_ZVL64B},
+  {"xtheadvector",  _options::x_riscv_zvl_flags, MASK_ZVL128B},
+  {"xtheadvector",  _options::x_riscv_zf_subext, MASK_ZVFHMIN},
+  {"xtheadvector",  _options::x_riscv_zf_subext, MASK_ZVFH},
+  {"xtheadvector",  _options::x_target_flags, MASK_FULL_V},
+  {"xtheadvector",  _options::x_target_flags, MASK_VECTOR},
 
   {"xventanacondops", _options::x_riscv_xventana_subext, 
MASK_XVENTANACONDOPS},
 
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index ba60cd8b555..422ddc2c308 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -142,6 +142,10 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
 riscv_ext_version_value (0, 11));
 }
 
+   if (TARGET_XTHEADVECTOR)
+ builtin_define_with_int_value ("__riscv_th_v_intrinsic",
+riscv_ext_version_value (0, 11));
+
   /* Define architecture extension test macros.  */
   builtin_define_with_int_value ("__riscv_arch_test", 1);
 
@@ -195,8 +199,8 @@ riscv_pragma_intrinsic (cpp_reader *)
 {
   if (!TARGET_VECTOR)
{
- error ("%<#pragma riscv intrinsic%> option %qs needs 'V' extension "
-"enabled",
+ error ("%<#pragma riscv intrinsic%> option %qs needs 'V' or "
+"'XTHEADVECTOR' extension enabled",
 name);
  return;
}
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 44ed6d69da2..bb18a22b693 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -452,6 +452,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext)
 
 Mask(XTHEADSYNC)

Re：Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

[joshua]

Hi Juzhe,

So is the following patch that this patch relies on OK to commit?
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html

Joshua




--
发件人：钟居哲 
发送时间：2024年1月2日(星期二) 06:57
收件人：Jeff Law; 
"cooper.joshua"; 
"gcc-patches"
抄　送："jim.wilson.gcc"; palmer; 
andrew; "philipp.tomsich"; 
"Christoph Müllner"; 
jinma; Cooper Qu
主　题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of 
XTheadVector.


This is Ok from my side.
But before commit this patch, I think we need this patch first:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html 


I will be back to work so I will take a look at other patches today.
juzhe.zh...@rivai.ai

 
From: Jeff Law
Date: 2024-01-01 01:43
To: Jun Sha (Joshua); gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; 
juzhe.zhong; Jin Ma; Xianmiao Qu
Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of 
XTheadVector.

 
 
On 12/28/23 21:19, Jun Sha (Joshua) wrote:
> This patch adds th. prefix to all XTheadVector instructions by
> implementing new assembly output functions. We only check the
> prefix is 'v', so that no extra attribute is needed.
> 
> gcc/ChangeLog:
> 
>   * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
>   New function to add assembler insn code prefix/suffix.
>   * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
>   * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
> 
> Co-authored-by: Jin Ma 
> Co-authored-by: Xianmiao Qu 
> Co-authored-by: Christoph Müllner 
> ---
>   gcc/config/riscv/riscv-protos.h    |  1 +
>   gcc/config/riscv/riscv.cc  | 14 ++
>   gcc/config/riscv/riscv.h   |  4 
>   .../gcc.target/riscv/rvv/xtheadvector/prefix.c | 12 
>   4 files changed, 31 insertions(+)
>   create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
> 
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 31049ef7523..5ea54b45703 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -102,6 +102,7 @@ struct riscv_address_info {
>   };
>   
>   /* Routines implemented in riscv.cc.  */
> +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char 
> *p);
>   extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
>   extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
>   extern int riscv_float_const_rtx_index_for_fli (rtx);
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 0d1cbc5cb5f..ea1d59d9cf2 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode)
> return lmul;
>   }
>   
> +/* Define ASM_OUTPUT_OPCODE to do anything special before
> +   emitting an opcode.  */
> +const char *
> +riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
> +{
> +  /* We need to add th. prefix to all the xtheadvector
> + insturctions here.*/
> +  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
> +  p[0] == 'v')
> +    fputs ("th.", asm_out_file);
> +
> +  return p;
Just a formatting nit. The GNU standards break lines before the 
operator, not after.  So
   if (TARGET_XTHEADVECTOR
   && current_output_insn != NULL
   && p[0] == 'v')
 
Note that current_output_insn is "extern rtx_insn *", so use NULL, not 
NULL_RTX.
 
Neither of these nits require a new version for review.  Just fix them.
 
If Juzhe is fine with this, so am I.  We can refine it if necessary later.
 
jeff
 

[PATCH v4] RISC-V: Add support for xtheadvector-specific intrinsics.

[Jun Sha (Joshua)]

re_width, none_m_preds, 
iu8_v_scalar_ptr_size_ops)
+DEF_RVV_FUNCTION (th_vssh, th_loadstore_width, none_m_preds, 
iu16_v_scalar_ptr_size_ops)
+DEF_RVV_FUNCTION (th_vssw, th_loadstore_width, none_m_preds, 
iu32_v_scalar_ptr_size_ops)
+DEF_RVV_FUNCTION (th_vlxb, th_indexed_loadstore_width, full_preds, 
i8_v_scalar_const_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vlxh, th_indexed_loadstore_width, full_preds, 
i16_v_scalar_const_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vlxw, th_indexed_loadstore_width, full_preds, 
i32_v_scalar_const_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vlxbu, th_indexed_loadstore_width, full_preds, 
u8_v_scalar_const_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vlxhu, th_indexed_loadstore_width, full_preds, 
u16_v_scalar_const_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vlxwu, th_indexed_loadstore_width, full_preds, 
u32_v_scalar_const_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsxb, th_indexed_loadstore_width, none_m_preds, 
iu8_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsxh, th_indexed_loadstore_width, none_m_preds, 
iu16_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsxw, th_indexed_loadstore_width, none_m_preds, 
iu32_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsuxb, th_indexed_loadstore_width, none_m_preds, 
iu8_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsuxh, th_indexed_loadstore_width, none_m_preds, 
iu16_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsuxw, th_indexed_loadstore_width, none_m_preds, 
iu32_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vext_x_v, th_extract, none_preds, iu_x_s_u_ops)
+#undef REQUIRED_EXTENSIONS
+
+#undef DEF_RVV_FUNCTION
diff --git a/gcc/config/riscv/thead-vector-builtins.cc 
b/gcc/config/riscv/thead-vector-builtins.cc
new file mode 100644
index 000..c0002f255ee
--- /dev/null
+++ b/gcc/config/riscv/thead-vector-builtins.cc
@@ -0,0 +1,200 @@
+/* function_base implementation for RISC-V XTheadVector Extension
+   for GNU compiler.
+   Copyright (C) 2022-2023 Free Software Foundation, Inc.
+   Contributed by Joshua (cooper.jos...@linux.alibaba.com), T-Head
+   Semiconductor Co., Ltd.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "tree.h"
+#include "rtl.h"
+#include "tm_p.h"
+#include "memmodel.h"
+#include "insn-codes.h"
+#include "optabs.h"
+#include "recog.h"
+#include "expr.h"
+#include "basic-block.h"
+#include "function.h"
+#include "fold-const.h"
+#include "gimple.h"
+#include "gimple-iterator.h"
+#include "gimplify.h"
+#include "explow.h"
+#include "emit-rtl.h"
+#include "tree-vector-builder.h"
+#include "rtx-vector-builder.h"
+#include "riscv-vector-builtins.h"
+#include "riscv-vector-builtins-shapes.h"
+#include "riscv-vector-builtins-bases.h"
+#include "thead-vector-builtins.h"
+
+using namespace riscv_vector;
+
+namespace riscv_vector {
+
+/* Implements
+ * th.vl(b/h/w)[u].v/th.vs(b/h/w)[u].v/th.vls(b/h/w)[u].v/th.vss(b/h/w)[u].v/
+ * th.vlx(b/h/w)[u].v/th.vs[u]x(b/h/w).v
+ * codegen.  */
+template
+class th_loadstore_width : public function_base
+{
+public:
+  bool apply_tail_policy_p () const override { return !STORE_P; }
+  bool apply_mask_policy_p () const override { return !STORE_P; }
+
+  unsigned int call_properties (const function_instance &) const override
+  {
+if (STORE_P)
+  return CP_WRITE_MEMORY;
+else
+  return CP_READ_MEMORY;
+  }
+
+  bool can_be_overloaded_p (enum predication_type_index pred) const override
+  {
+if (STORE_P || LST_TYPE == LST_INDEXED)
+  return true;
+return pred != PRED_TYPE_none;
+  }
+
+  rtx expand (function_expander ) const override
+  {
+gcc_assert (TARGET_XTHEADVECTOR);
+if (LST_TYPE == LST_INDEXED)
+  {
+   if (STORE_P)
+ return e.use_exact_insn (
+   code_for_pred_indexed_store_width (UNSPEC, UNSPEC,
+  e.vector_mode ()));
+   else
+ return e.use_exact_insn (
+   code_for_pred_indexed_load_width (UNSPEC, e.vector_mode ()));
+  }
+else if (LST_TYPE == LST_STRIDED)
+  {
+   if (STORE_P)
+ return e.use_contiguous_

[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector

[Jun Sha (Joshua)]

This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 

For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r and vsext.vf2.

gcc/ChangeLog:

* config.gcc:  Add files for XTheadVector intrinsics.
* config/riscv/autovec.md: Guard XTheadVector.
* config/riscv/riscv-c.cc: Add pragma for XTheadVector.
* config/riscv/riscv-string.cc (expand_block_move):
Guard XTheadVector.
(get_prefer_tail_policy): Give specific value for tail.
(get_prefer_mask_policy): Give specific value for mask.
(vls_mode_valid_p): Avoid autovec.
* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
(build_one): New function.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
(DEF_THEAD_RVV_FUNCTION): Add new marcos.
(check_required_extensions):
(handle_pragma_vector):
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR):
(RVV_REQUIRE_XTHEADVECTOR):
Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR.
(struct function_group_info):
* config/riscv/riscv-vector-switch.def (ENTRY):
Disable fractional mode for the XTheadVector extension.
(TUPLE_ENTRY): Likewise.
* config/riscv/riscv-vsetvl.cc: Add functions for xtheadvector.
* config/riscv/riscv.cc (riscv_v_ext_vls_mode_p):
Guard XTheadVector.
(riscv_v_adjust_bytesize): Likewise.
(riscv_preferred_simd_mode): Likewsie.
(riscv_autovectorize_vector_modes): Likewise.
(riscv_vector_mode_supported_any_target_p): Likewise.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
* config/riscv/vector-iterators.md: Remove fractional LMUL.
* config/riscv/vector.md: Include thead-vector.md.
* config/riscv/riscv_th_vector.h: New file.
* config/riscv/thead-vector.md: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector.
* gcc.target/riscv/rvv/base/abi-1.c: Exclude XTheadVector.
* lib/target-supports.exp: Add target for XTheadVector.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/autovec.md   |   2 +-
 gcc/config/riscv/predicates.md|   4 +-
 gcc/config/riscv/riscv-c.cc   |   3 +-
 gcc/config/riscv/riscv-string.cc  |   3 +-
 gcc/config/riscv/riscv-v.cc   |   6 +-
 .../riscv/riscv-vector-builtins-bases.cc  |  48 +++--
 .../riscv/riscv-vector-builtins-shapes.cc |  23 +++
 gcc/config/riscv/riscv-vector-switch.def  | 150 +++---
 gcc/config/riscv/riscv.cc |  20 +-
 gcc/config/riscv/riscv_th_vector.h|  49 +
 gcc/config/riscv/thead-vector.md  | 102 ++
 gcc/config/riscv/vector-iterators.md  | 186 +-
 gcc/config/riscv/vector.md|  43 +++-
 .../gcc.target/riscv/rvv/base/abi-1.c |   2 +-
 .../gcc.target/riscv/rvv/base/pragma-1.c  |   2 +-
 gcc/testsuite/lib/target-supports.exp |  12 ++
 17 files changed, 451 insertions(+), 206 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_th_vector.h
 create mode 100644 gcc/config/riscv/thead-vector.md

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f0676c830e8..1445d98c147 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,7 +549,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_th_vector.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 8b8a92f10a1..1fac56c7095 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2579,7 +2579,7 @@
   [(match_operand  0 "register_operand")
(match_operand  1 "memory_operand")
(match_operand:ANYI 2 "const_int_operand")]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   {
 riscv_vector::expand_rawmemchr(mode, 

[PATCH v4] RISC-V: Rewrite some instructions using ASM targethook

[Jun Sha (Joshua)]

There are some xtheadvector instructions that differ from RVV1.0
apart from simply adding "th." prefix. For example, RVV1.0
load/store instructions will have SEW while xtheadvector not;
RVV1.0 will have "o" for indexed-ordered store instructions while
xtheadvecotr not; xtheadvector and RVV1.0 have different
vnsrl/vnsra/vfncvt suffix (vv/vx/vi vs wv/wx/wi).

To address this issue without duplicating patterns, we use ASM
targethook to rewrite the whole string of the instructions. We
identify different instructions from the corresponding attribute.

gcc/ChangeLog:

* config/riscv/thead.cc
(th_asm_output_opcode): Rewrite some instructions.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config/riscv/thead.cc | 215 +-
 1 file changed, 213 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc
index dc3aed3904d..fb088ebff02 100644
--- a/gcc/config/riscv/thead.cc
+++ b/gcc/config/riscv/thead.cc
@@ -27,6 +27,7 @@
 #include "backend.h"
 #include "tree.h"
 #include "rtl.h"
+#include "insn-attr.h"
 #include "explow.h"
 #include "memmodel.h"
 #include "emit-rtl.h"
@@ -890,8 +891,218 @@ th_asm_output_opcode (FILE *asm_out_file, const char *p)
 {
   /* We need to add th. prefix to all the xtheadvector
  instructions here.*/
-  if (current_output_insn != NULL && p[0] == 'v')
-fputs ("th.", asm_out_file);
+  if (current_output_insn != NULL)
+{
+  if (get_attr_type (current_output_insn) == TYPE_VLDE ||
+ get_attr_type (current_output_insn) == TYPE_VSTE ||
+ get_attr_type (current_output_insn) == TYPE_VLDFF)
+   {
+ if (strstr (p, "e8") || strstr (p, "e16") ||
+ strstr (p, "e32") || strstr (p, "e64"))
+   {
+ get_attr_type (current_output_insn) == TYPE_VSTE
+ ? fputs ("th.vse", asm_out_file)
+ : fputs ("th.vle", asm_out_file);
+ if (strstr (p, "e8"))
+   return p+4;
+ else
+   return p+5;
+   }
+   }
+
+  if (get_attr_type (current_output_insn) == TYPE_VLDS ||
+ get_attr_type (current_output_insn) == TYPE_VSTS)
+   {
+ if (strstr (p, "vle8") || strstr (p, "vse8") ||
+ strstr (p, "vle16") || strstr (p, "vse16") ||
+ strstr (p, "vle32") || strstr (p, "vse32") ||
+ strstr (p, "vle64") || strstr (p, "vse64"))
+   {
+ get_attr_type (current_output_insn) == TYPE_VSTS
+ ? fputs ("th.vse", asm_out_file)
+ : fputs ("th.vle", asm_out_file);
+ if (strstr (p, "e8"))
+   return p+4;
+ else
+   return p+5;
+   }
+ else if (strstr (p, "vlse8") || strstr (p, "vsse8") ||
+  strstr (p, "vlse16") || strstr (p, "vsse16") ||
+  strstr (p, "vlse32") || strstr (p, "vsse32") ||
+  strstr (p, "vlse64") || strstr (p, "vsse64"))
+   {
+ get_attr_type (current_output_insn) == TYPE_VSTS
+ ? fputs ("th.vsse", asm_out_file)
+ : fputs ("th.vlse", asm_out_file);
+ if (strstr (p, "e8"))
+   return p+5;
+ else
+   return p+6;
+   }
+   }
+
+  if (get_attr_type (current_output_insn) == TYPE_VLDUX ||
+ get_attr_type (current_output_insn) == TYPE_VLDOX)
+   {
+ if (strstr (p, "ei"))
+   {
+ fputs ("th.vlxe", asm_out_file);
+ if (strstr (p, "ei8"))
+   return p+7;
+ else
+   return p+8;
+   }
+   }
+
+  if (get_attr_type (current_output_insn) == TYPE_VSTUX ||
+ get_attr_type (current_output_insn) == TYPE_VSTOX)
+   {
+ if (strstr (p, "ei"))
+   {
+ get_attr_type (current_output_insn) == TYPE_VSTUX
+   ? fputs ("th.vsuxe", asm_out_file)
+   : fputs ("th.vsxe", asm_out_file);
+ if (strstr (p, "ei8"))
+   return p+7;
+ else
+   return p+8;
+   }
+   }
+
+  if (get_attr_type (current_output_insn) == TYPE_VLSEGDE ||
+ get_attr_type (current_output_insn) == TYPE_VSSEGTE ||
+ get_attr_type (current_output_insn) == TYPE_VLSEGDFF)
+   {
+ get_attr_type (current_output_insn) == TYPE_VSSEGTE
+   ? fputs ("th.vsseg", asm_out_file)
+   : fputs ("th.vlseg", asm_out_file);
+ asm_fprintf (asm_out_file, "%c", p[5]);
+ fputs ("e", asm_out_file);
+ if (strstr (p, "e8"))
+   return p+8;
+ else
+   return p+9;
+   }
+
+  if (get_attr_type 

[PATCH v4] RISC-V: Fix register overlap issue for some xtheadvector instructions

[Jun Sha (Joshua)]

For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions
and floating-point compare instructions, an illegal instruction
exception will be raised if the destination vector register overlaps
a source vector register group.

To handle this issue, we use "group_overlap" and "enabled" attribute
to disable some alternatives for xtheadvector.

gcc/ChangeLog:

* config/riscv/riscv.md (none,W21,W42,W84,W43,W86,W87,W0):
(none,W21,W42,W84,W43,W86,W87,W0,th):
Add group-overlap constraint for xtheadvector.
* config/riscv/vector.md: 
Disable alternatives that destination register overlaps
source register group for xtheadvector.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config/riscv/riscv.md  |   6 +-
 gcc/config/riscv/vector.md | 314 +
 2 files changed, 185 insertions(+), 135 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 68f7203b676..d736501784d 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -504,7 +504,7 @@
 ;; Widening instructions have group-overlap constraints.  Those are only
 ;; valid for certain register-group sizes.  This attribute marks the
 ;; alternatives not matching the required register-group size as disabled.
-(define_attr "group_overlap" "none,W21,W42,W84,W43,W86,W87,W0"
+(define_attr "group_overlap" "none,W21,W42,W84,W43,W86,W87,W0,th"
   (const_string "none"))
 
 (define_attr "group_overlap_valid" "no,yes"
@@ -543,6 +543,10 @@
  (and (eq_attr "group_overlap" "W0")
  (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) 
> 1"))
 (const_string "no")
+
+ (and (eq_attr "group_overlap" "th")
+ (match_test "TARGET_XTHEADVECTOR"))
+(const_string "no")
 ]
(const_string "yes")))
 
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index cb30c9ae97c..63d0573d4aa 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -3248,7 +3248,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none,none")])
 
 (define_insn "@pred_msbc"
   [(set (match_operand: 0 "register_operand""=vr, vr, ")
@@ -3267,7 +3268,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,th,none")])
 
 (define_insn "@pred_madc_scalar"
   [(set (match_operand: 0 "register_operand" "=vr, ")
@@ -3287,7 +3289,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none")])
 
 (define_insn "@pred_msbc_scalar"
   [(set (match_operand: 0 "register_operand" "=vr, ")
@@ -3307,7 +3310,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none")])
 
 (define_expand "@pred_madc_scalar"
   [(set (match_operand: 0 "register_operand")
@@ -3356,7 +3360,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none")])
 
 (define_insn "*pred_madc_extended_scalar"
   [(set (match_operand: 0 "register_operand" "=vr, ")
@@ -3377,7 +3382,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none")])
 
 (define_expand "@pred_msbc_scalar"
   [(set (match_operand: 0 "register_operand")
@@ -3426,7 +3432,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none")])
 
 (define_insn "*pred_msbc_extended_scalar"
   [(set (match_operand: 0 "register_operand"  "=vr, ")
@@ -3447,7 +3454,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none")])
 
 (define_insn "@pred_madc_overflow"
   [(set (match_operand: 0 "register_operand" "=vr, , ")
@@ -3465,7 +3473,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "3")
-   (set (attr "avl_type_idx") (const_int 

[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector

[Jun Sha (Joshua)]

This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 

For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r and vsext.vf2.

gcc/ChangeLog:

* config.gcc:  Add files for XTheadVector intrinsics.
* config/riscv/autovec.md: Guard XTheadVector.
* config/riscv/riscv-c.cc: Add pragma for XTheadVector.
* config/riscv/riscv-string.cc (expand_block_move):
Guard XTheadVector.
(get_prefer_tail_policy): Give specific value for tail.
(get_prefer_mask_policy): Give specific value for mask.
(vls_mode_valid_p): Avoid autovec.
* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
(build_one): New function.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
(DEF_THEAD_RVV_FUNCTION): Add new marcos.
(check_required_extensions):
(handle_pragma_vector):
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR):
(RVV_REQUIRE_XTHEADVECTOR):
Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR.
(struct function_group_info):
* config/riscv/riscv-vector-switch.def (ENTRY):
Disable fractional mode for the XTheadVector extension.
(TUPLE_ENTRY): Likewise.
* config/riscv/riscv-vsetvl.cc: Add functions for xtheadvector.
* config/riscv/riscv.cc (riscv_v_ext_vls_mode_p):
Guard XTheadVector.
(riscv_v_adjust_bytesize): Likewise.
(riscv_preferred_simd_mode): Likewsie.
(riscv_autovectorize_vector_modes): Likewise.
(riscv_vector_mode_supported_any_target_p): Likewise.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
* config/riscv/vector-iterators.md: Remove fractional LMUL.
* config/riscv/vector.md: Include thead-vector.md.
* config/riscv/riscv_th_vector.h: New file.
* config/riscv/thead-vector.md: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector.
* gcc.target/riscv/rvv/base/abi-1.c: Exclude XTheadVector.
* lib/target-supports.exp: Add target for XTheadVector.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/autovec.md   |   2 +-
 gcc/config/riscv/predicates.md|   4 +-
 gcc/config/riscv/riscv-c.cc   |   3 +-
 gcc/config/riscv/riscv-string.cc  |   3 +-
 gcc/config/riscv/riscv-v.cc   |   6 +-
 .../riscv/riscv-vector-builtins-bases.cc  |  48 +++--
 .../riscv/riscv-vector-builtins-shapes.cc |  23 +++
 gcc/config/riscv/riscv-vector-switch.def  | 150 +++---
 gcc/config/riscv/riscv.cc |  20 +-
 gcc/config/riscv/riscv_th_vector.h|  49 +
 gcc/config/riscv/thead-vector.md  |  69 +++
 gcc/config/riscv/vector-iterators.md  | 186 +-
 gcc/config/riscv/vector.md|  55 --
 .../gcc.target/riscv/rvv/base/abi-1.c |   2 +-
 .../gcc.target/riscv/rvv/base/pragma-1.c  |   2 +-
 gcc/testsuite/lib/target-supports.exp |  12 ++
 17 files changed, 427 insertions(+), 209 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_th_vector.h
 create mode 100644 gcc/config/riscv/thead-vector.md

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f0676c830e8..1445d98c147 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,7 +549,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_th_vector.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 8b8a92f10a1..1fac56c7095 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2579,7 +2579,7 @@
   [(match_operand  0 "register_operand")
(match_operand  1 "memory_operand")
(match_operand:ANYI 2 "const_int_operand")]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   {
 riscv_vector::expand_rawmemchr(mode, 

[PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

[Jun Sha (Joshua)]

This patch adds th. prefix to all XTheadVector instructions by
implementing new assembly output functions. We only check the
prefix is 'v', so that no extra attribute is needed.

gcc/ChangeLog:

* config/riscv/riscv-protos.h (riscv_asm_output_opcode):
New function to add assembler insn code prefix/suffix.
(th_asm_output_opcode):
Thead function to add assembler insn code prefix/suffix.
* config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise
* config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
* config/riscv/thead.cc (th_asm_output_opcode): Likewise

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/prefix.c: New test.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config/riscv/riscv-protos.h |  2 ++
 gcc/config/riscv/riscv.cc   | 11 +++
 gcc/config/riscv/riscv.h|  4 
 gcc/config/riscv/thead.cc   | 13 +
 .../gcc.target/riscv/rvv/xtheadvector/prefix.c  | 12 
 5 files changed, 42 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 31049ef7523..71724dabdb5 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -102,6 +102,7 @@ struct riscv_address_info {
 };
 
 /* Routines implemented in riscv.cc.  */
+extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
 extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
 extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
 extern int riscv_float_const_rtx_index_for_fli (rtx);
@@ -717,6 +718,7 @@ extern void th_mempair_prepare_save_restore_operands 
(rtx[4], bool,
  int, HOST_WIDE_INT,
  int, HOST_WIDE_INT);
 extern void th_mempair_save_restore_regs (rtx[4], bool, machine_mode);
+extern const char *th_asm_output_opcode (FILE *asm_out_file, const char *p);
 #ifdef RTX_CODE
 extern const char*
 th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0d1cbc5cb5f..51878797287 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5636,6 +5636,17 @@ riscv_get_v_regno_alignment (machine_mode mode)
   return lmul;
 }
 
+/* Define ASM_OUTPUT_OPCODE to do anything special before
+   emitting an opcode.  */
+const char *
+riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
+{
+  if (TARGET_XTHEADVECTOR)
+return th_asm_output_opcode (asm_out_file, p);
+
+  return p;
+}
+
 /* Implement TARGET_PRINT_OPERAND.  The RISCV-specific operand codes are:
 
'h' Print the high-part relocation associated with OP, after stripping
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 6df9ec73c5e..c33361a254d 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -826,6 +826,10 @@ extern enum riscv_cc get_riscv_cc (const rtx use);
   asm_fprintf ((FILE), "%U%s", (NAME));\
   } while (0)
 
+#undef ASM_OUTPUT_OPCODE
+#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
+  (PTR) = riscv_asm_output_opcode(STREAM, PTR)
+
 #define JUMP_TABLES_IN_TEXT_SECTION 0
 #define CASE_VECTOR_MODE SImode
 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc
index 20353995931..dc3aed3904d 100644
--- a/gcc/config/riscv/thead.cc
+++ b/gcc/config/riscv/thead.cc
@@ -883,6 +883,19 @@ th_output_move (rtx dest, rtx src)
   return NULL;
 }
 
+/* Define ASM_OUTPUT_OPCODE to do anything special before
+   emitting an opcode.  */
+const char *
+th_asm_output_opcode (FILE *asm_out_file, const char *p)
+{
+  /* We need to add th. prefix to all the xtheadvector
+ instructions here.*/
+  if (current_output_insn != NULL && p[0] == 'v')
+fputs ("th.", asm_out_file);
+
+  return p;
+}
+
 /* Implement TARGET_PRINT_OPERAND_ADDRESS for XTheadMemIdx.  */
 
 bool
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
new file mode 100644
index 000..eee727ef6b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadvector -mabi=ilp32 -O0" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+prefix (vint32m1_t vx, vint32m1_t vy, size_t vl)
+{
+  return __riscv_vadd_vv_i32m1 (vx, vy, vl);
+}
+
+/* { dg-final { scan-assembler {\mth\.v\M} } } */
-- 
2.17.1

[PATCH v4] RISC-V: Rewrite some instructions using ASM targethook

[Jun Sha (Joshua)]

There are some xtheadvector instructions that differ from RVV1.0
apart from simply adding "th." prefix. For example, RVV1.0
load/store instructions will have SEW while xtheadvector not;
RVV1.0 will have "o" for indexed-ordered store instructions while
xtheadvecotr not; xtheadvector and RVV1.0 have different
vnsrl/vnsra/vfncvt suffix (vv/vx/vi vs wv/wx/wi).

To address this issue without duplicating patterns, we use ASM
targethook to rewrite the whole string of the instructions. We
identify different instructions from the corresponding attribute.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_asm_output_opcode):

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config/riscv/riscv.cc | 213 +-
 1 file changed, 210 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index a80bf8d1a74..13cdfc4ee27 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5646,9 +5646,216 @@ riscv_asm_output_opcode (FILE *asm_out_file, const char 
*p)
 {
   /* We need to add th. prefix to all the xtheadvector
  insturctions here.*/
-  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
-  p[0] == 'v')
-fputs ("th.", asm_out_file);
+  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX)
+{
+  if (get_attr_type (current_output_insn) == TYPE_VLDE ||
+ get_attr_type (current_output_insn) == TYPE_VSTE ||
+ get_attr_type (current_output_insn) == TYPE_VLDFF)
+   {
+ if (strstr (p, "e8") || strstr (p, "e16") ||
+ strstr (p, "e32") || strstr (p, "e64"))
+   {
+ get_attr_type (current_output_insn) == TYPE_VSTE
+ ? fputs ("th.vse", asm_out_file)
+ : fputs ("th.vle", asm_out_file);
+ if (strstr (p, "e8"))
+   return p+4;
+ else
+   return p+5;
+   }
+   }
+
+  if (get_attr_type (current_output_insn) == TYPE_VLDS ||
+ get_attr_type (current_output_insn) == TYPE_VSTS)
+   {
+ if (strstr (p, "vle8") || strstr (p, "vse8") ||
+ strstr (p, "vle16") || strstr (p, "vse16") ||
+ strstr (p, "vle32") || strstr (p, "vse32") ||
+ strstr (p, "vle64") || strstr (p, "vse64"))
+   {
+ get_attr_type (current_output_insn) == TYPE_VSTS
+ ? fputs ("th.vse", asm_out_file)
+ : fputs ("th.vle", asm_out_file);
+ if (strstr (p, "e8"))
+   return p+4;
+ else
+   return p+5;
+   }
+ else if (strstr (p, "vlse8") || strstr (p, "vsse8") ||
+  strstr (p, "vlse16") || strstr (p, "vsse16") ||
+  strstr (p, "vlse32") || strstr (p, "vsse32") ||
+  strstr (p, "vlse64") || strstr (p, "vsse64"))
+   {
+ get_attr_type (current_output_insn) == TYPE_VSTS
+ ? fputs ("th.vsse", asm_out_file)
+ : fputs ("th.vlse", asm_out_file);
+ if (strstr (p, "e8"))
+   return p+5;
+ else
+   return p+6;
+   }
+   }
+
+  if (get_attr_type (current_output_insn) == TYPE_VLDUX ||
+ get_attr_type (current_output_insn) == TYPE_VLDOX)
+   {
+ if (strstr (p, "ei"))
+   {
+ fputs ("th.vlxe", asm_out_file);
+ if (strstr (p, "ei8"))
+   return p+7;
+ else
+   return p+8;
+   }
+   }
+
+  if (get_attr_type (current_output_insn) == TYPE_VSTUX ||
+ get_attr_type (current_output_insn) == TYPE_VSTOX)
+   {
+ if (strstr (p, "ei"))
+   {
+ get_attr_type (current_output_insn) == TYPE_VSTUX
+   ? fputs ("th.vsuxe", asm_out_file)
+   : fputs ("th.vsxe", asm_out_file);
+ if (strstr (p, "ei8"))
+   return p+7;
+ else
+   return p+8;
+   }
+   }
+
+  if (get_attr_type (current_output_insn) == TYPE_VLSEGDE ||
+ get_attr_type (current_output_insn) == TYPE_VSSEGTE ||
+ get_attr_type (current_output_insn) == TYPE_VLSEGDFF)
+   {
+ get_attr_type (current_output_insn) == TYPE_VSSEGTE
+   ? fputs ("th.vsseg", asm_out_file)
+   : fputs ("th.vlseg", asm_out_file);
+ asm_fprintf (asm_out_file, "%c", p[5]);
+ fputs ("e", asm_out_file);
+ if (strstr (p, "e8"))
+   return p+8;
+ else
+   return p+9;
+   }
+
+  if (get_attr_type (current_output_insn) == TYPE_VLSEGDS ||
+ get_attr_type (current_output_insn) == TYPE_VSSEGTS)
+   {
+ get_attr_type 

[PATCH v4] RISC-V: Fix register overlap issue for some xtheadvector instructions

[Jun Sha (Joshua)]

For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions
and floating-point compare instructions, an illegal instruction
exception will be raised if the destination vector register overlaps
a source vector register group.

To handle this issue, we use "group_overlap" and "enabled" attribute
to disable some alternatives for xtheadvector.

gcc/ChangeLog:

* config/riscv/riscv.md (none,W21,W42,W84,W43,W86,W87,W0):
(none,W21,W42,W84,W43,W86,W87,W0,th):
* config/riscv/vector.md:

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config/riscv/riscv.md  |   6 +-
 gcc/config/riscv/vector.md | 314 +
 2 files changed, 185 insertions(+), 135 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 68f7203b676..d736501784d 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -504,7 +504,7 @@
 ;; Widening instructions have group-overlap constraints.  Those are only
 ;; valid for certain register-group sizes.  This attribute marks the
 ;; alternatives not matching the required register-group size as disabled.
-(define_attr "group_overlap" "none,W21,W42,W84,W43,W86,W87,W0"
+(define_attr "group_overlap" "none,W21,W42,W84,W43,W86,W87,W0,th"
   (const_string "none"))
 
 (define_attr "group_overlap_valid" "no,yes"
@@ -543,6 +543,10 @@
  (and (eq_attr "group_overlap" "W0")
  (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) 
> 1"))
 (const_string "no")
+
+ (and (eq_attr "group_overlap" "th")
+ (match_test "TARGET_XTHEADVECTOR"))
+(const_string "no")
 ]
(const_string "yes")))
 
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 5fa30716143..77eaba16c97 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -3255,7 +3255,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none,none")])
 
 (define_insn "@pred_msbc"
   [(set (match_operand: 0 "register_operand""=vr, vr, ")
@@ -3274,7 +3275,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,th,none")])
 
 (define_insn "@pred_madc_scalar"
   [(set (match_operand: 0 "register_operand" "=vr, ")
@@ -3294,7 +3296,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none")])
 
 (define_insn "@pred_msbc_scalar"
   [(set (match_operand: 0 "register_operand" "=vr, ")
@@ -3314,7 +3317,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none")])
 
 (define_expand "@pred_madc_scalar"
   [(set (match_operand: 0 "register_operand")
@@ -3363,7 +3367,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none")])
 
 (define_insn "*pred_madc_extended_scalar"
   [(set (match_operand: 0 "register_operand" "=vr, ")
@@ -3384,7 +3389,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none")])
 
 (define_expand "@pred_msbc_scalar"
   [(set (match_operand: 0 "register_operand")
@@ -3433,7 +3439,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none")])
 
 (define_insn "*pred_msbc_extended_scalar"
   [(set (match_operand: 0 "register_operand"  "=vr, ")
@@ -3454,7 +3461,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
-   (set (attr "avl_type_idx") (const_int 5))])
+   (set (attr "avl_type_idx") (const_int 5))
+   (set_attr "group_overlap" "th,none")])
 
 (define_insn "@pred_madc_overflow"
   [(set (match_operand: 0 "register_operand" "=vr, , ")
@@ -3472,7 +3480,8 @@
   [(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "3")
-   (set (attr "avl_type_idx") (const_int 4))])
+   (set (attr "avl_type_idx") (const_int 4))
+   (set_attr "group_overlap" "th,none,none")])
 
 (define_insn "@pred_msbc_overflow"
   [(set (match_operand: 0 

[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector

[Jun Sha (Joshua)]

This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 

For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r and vsext.vf2.

gcc/ChangeLog:

* config.gcc:  Add files for XTheadVector intrinsics.
* config/riscv/autovec.md: Guard XTheadVector.
* config/riscv/riscv-string.cc (expand_block_move):
Guard XTheadVector.
(get_prefer_tail_policy): Give specific value for tail.
(get_prefer_mask_policy): Give specific value for mask.
(vls_mode_valid_p): Avoid autovec.
* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
(build_one): New function.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
(DEF_THEAD_RVV_FUNCTION): Add new marcos.
(check_required_extensions):
(handle_pragma_vector):
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR):
(RVV_REQUIRE_XTHEADVECTOR):
Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR.
(struct function_group_info):
* config/riscv/riscv-vector-switch.def (ENTRY):
Disable fractional mode for the XTheadVector extension.
(TUPLE_ENTRY): Likewise.
* config/riscv/riscv-vsetvl.cc: Add functions for xtheadvector.
* config/riscv/riscv.cc (riscv_v_ext_vls_mode_p):
Guard XTheadVector.
(riscv_v_adjust_bytesize): Likewise.
(riscv_preferred_simd_mode): Likewsie.
(riscv_autovectorize_vector_modes): Likewise.
(riscv_vector_mode_supported_any_target_p): Likewise.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
* config/riscv/vector-iterators.md: Remove fractional LMUL.
* config/riscv/vector.md: Include thead-vector.md.
* config/riscv/riscv_th_vector.h: New file.
* config/riscv/thead-vector.md: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector.
* gcc.target/riscv/rvv/base/abi-1.c: Exclude XTheadVector.
* lib/target-supports.exp: Add target for XTheadVector.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/autovec.md   |   2 +-
 gcc/config/riscv/predicates.md|   4 +-
 gcc/config/riscv/riscv-string.cc  |   3 +-
 gcc/config/riscv/riscv-v.cc   |   6 +-
 .../riscv/riscv-vector-builtins-bases.cc  |  48 +++--
 .../riscv/riscv-vector-builtins-shapes.cc |  23 +++
 gcc/config/riscv/riscv-vector-switch.def  | 150 +++---
 gcc/config/riscv/riscv.cc |  20 +-
 gcc/config/riscv/riscv_th_vector.h|  49 +
 gcc/config/riscv/thead-vector.md  |  69 +++
 gcc/config/riscv/vector-iterators.md  | 186 +-
 gcc/config/riscv/vector.md|  55 --
 .../gcc.target/riscv/rvv/base/abi-1.c |   2 +-
 .../gcc.target/riscv/rvv/base/pragma-1.c  |   2 +-
 gcc/testsuite/lib/target-supports.exp |  12 ++
 16 files changed, 425 insertions(+), 208 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_th_vector.h
 create mode 100644 gcc/config/riscv/thead-vector.md

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f0676c830e8..1445d98c147 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,7 +549,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_th_vector.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 8b8a92f10a1..1fac56c7095 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2579,7 +2579,7 @@
   [(match_operand  0 "register_operand")
(match_operand  1 "memory_operand")
(match_operand:ANYI 2 "const_int_operand")]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   {
 riscv_vector::expand_rawmemchr(mode, operands[0], operands[1],
   operands[2]);
diff --git a/gcc/config/riscv/predicates.md 

Re：[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector

[joshua]

+  if (TARGET_XTHEADVECTOR)
+  {
+ emit_insn (gen_pred_th_whole_mov (mode, dest, src,
+   RVV_VLMAX, GEN_INT(VLMAX)));
+ return true;
+  }

Move it outside legitimize_move
It should be it:

if (TARGET_THEADVECTOR)
emit_th_move...
DONE;
else if (riscv_vector::legitimize_move (operands[0], [1]))
DONE; 

If we move emit_insn (gen_pred_th_whole_mov...) outside legitimize,
we need to modify the patterns which will call  legitimize_move ().
I have tried and that will result in 5 extra changes in vector.md.





--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月2日(星期二) 10:00
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主　题：Re: [PATCH v4] RISC-V: Handle differences between XTheadvector and Vector


+   if (TARGET_XTHEADVECTOR)
+    return false;



Move it to :
  if (TARGET_VECTOR && stringop_strategy & STRATEGY_VECTOR)
    {
      bool ok = riscv_vector::expand_block_move (dest, src, length);
      if (ok)
  return true;
    }





(define_special_predicate "vector_length_operand"
   (ior (match_operand 0 "pmode_register_operand")
-   (match_operand 0 "const_csr_operand")))
+  (and (match_test "!TARGET_XTHEADVECTOR || rtx_equal_p (op, const0_rtx)")
+    (match_operand 0 "const_csr_operand"



It's hard to trace. Change it into :


(ior
1. TARGET_THEADVECTOR && rtx_equal_p (op, const0_rtx) 
2. !TAGEET_THEADVECTOR && const_csr_operand)


+  if (TARGET_XTHEADVECTOR)
+  {
+   emit_insn (gen_pred_th_whole_mov (mode, dest, src,
+     RVV_VLMAX, GEN_INT(VLMAX)));
+   return true;
+  }



Move it outside legitimize_move
It should be it:


if (TARGET_THEADVECTOR)
emit_th_move...
DONE;
else if (riscv_vector::legitimize_move (operands[0], [1]))
    DONE; 




vsetvli issues:
I wonder whether we can use ASM_OUTPUT_OPCODE to recognize 
"ta,ma"/"ta,mu"/"tu,ma"/"tu,mu" and replace these 4 variants
by "". So that we don't have tail policy and mask policy in vsetvli ASM string.


Another alternative approach is we can change vsetlvi ASM rule:


"vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"


if (TARGET_THEADVECTOR)
...
else
        else if (code == CONST_INT)
          {
            /* Tail && Mask policy.  */
            asm_fprintf (file, "%s", IS_AGNOSTIC (UINTVAL (op)) ? "a" : "u");
          }



in riscv.cc.


The benefit is that we can avoid adding all th_vsetvl patterns and invasive 
code changs in VSETVL PASS.




juzhe.zh...@rivai.ai

 
From: Jun Sha (Joshua)
Date: 2023-12-29 12:21
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v4] RISC-V: Handle differences between XTheadvector and Vector

This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 
 
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r and vsext.vf2.
 
gcc/ChangeLog:
 
* config.gcc:  Add files for XTheadVector intrinsics.
* config/riscv/autovec.md: Guard XTheadVector.
* config/riscv/riscv-string.cc (expand_block_move):
Guard XTheadVector.
* config/riscv/riscv-v.cc (legitimize_move):
New expansion.
(get_prefer_tail_policy): Give specific value for tail.
(get_prefer_mask_policy): Give specific value for mask.
(vls_mode_valid_p): Avoid autovec.
* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
(build_one): New function.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
(DEF_THEAD_RVV_FUNCTION): Add new marcos.
(check_required_extensions):
(handle_pragma_vector):
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR):
(RVV_REQUIRE_XTHEADVECTOR):
Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR.
(struct function_group_info):
* config/riscv/riscv-vector-switch.def (ENTRY):
Disable fractional mode for the XTheadVector extension.
(TUPLE_ENTRY): Likewise.
* config/riscv/riscv-vsetvl.cc: Add functions for xtheadvector.
* config/riscv/riscv.cc (ris

Re：Re：[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector

[joshua]

But the riscv_print_operand() function returns void. 
We cannot return instructions like riscv_output_move.
I think the briefest approach is to add some logic in
the vsetvl patterns.

"TARGET_VECTOR"
  { return TARGET_XTHEADVECTOR ? "vsetvli\t%0,%1,e%2,%m3" : 
"vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"; }

Only 3 patterns need to be modified and I don't think
it is too invasive.

--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月2日(星期二) 11:10
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"
主　题：Re: Re：[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector


Like riscv_output_move


if (TARGET_THEADVECTOR)
  return vsetvlino tail policy and mask policy.
else
  return 
juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2024-01-02 11:03
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner
主题： Re：[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector

For vsetvl issues, what we want to do here is to directly
remove "t" and "m". 
 
If we add TARGET_XTHEADVECTOR logic in case "p" in
riscv_print_operand, how can we remove "t" and "m"? If I
use "break", assembly like "th.vsetvli zero,a5,e8,m1,t,m"
will be returned.
 
if (TARGET_THEADVECTOR)
...
else
    else if (code == CONST_INT)
  {
    /* Tail && Mask policy.  */
    asm_fprintf (file, "%s", IS_AGNOSTIC (UINTVAL (op)) ? "a" : "u");
  }
 
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月2日(星期二) 10:00
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主　题：Re: [PATCH v4] RISC-V: Handle differences between XTheadvector and Vector
 
 
+   if (TARGET_XTHEADVECTOR)
+    return false;
 
 
 
Move it to :
  if (TARGET_VECTOR && stringop_strategy & STRATEGY_VECTOR)
    {
      bool ok = riscv_vector::expand_block_move (dest, src, length);
      if (ok)
  return true;
    }
 
 
 
 
 
(define_special_predicate "vector_length_operand"
   (ior (match_operand 0 "pmode_register_operand")
-   (match_operand 0 "const_csr_operand")))
+  (and (match_test "!TARGET_XTHEADVECTOR || rtx_equal_p (op, const0_rtx)")
+    (match_operand 0 "const_csr_operand"
 
 
 
It's hard to trace. Change it into :
 
 
(ior
1. TARGET_THEADVECTOR && rtx_equal_p (op, const0_rtx) 
2. !TAGEET_THEADVECTOR && const_csr_operand)
 
 
+  if (TARGET_XTHEADVECTOR)
+  {
+   emit_insn (gen_pred_th_whole_mov (mode, dest, src,
+     RVV_VLMAX, GEN_INT(VLMAX)));
+   return true;
+  }
 
 
 
Move it outside legitimize_move
It should be it:
 
 
if (TARGET_THEADVECTOR)
emit_th_move...
DONE;
else if (riscv_vector::legitimize_move (operands[0], [1]))
    DONE; 
 
 
 
 
vsetvli issues:
I wonder whether we can use ASM_OUTPUT_OPCODE to recognize 
"ta,ma"/"ta,mu"/"tu,ma"/"tu,mu" and replace these 4 variants
by "". So that we don't have tail policy and mask policy in vsetvli ASM string.
 
 
Another alternative approach is we can change vsetlvi ASM rule:
 
 
"vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"
 
 
if (TARGET_THEADVECTOR)
...
else
        else if (code == CONST_INT)
          {
            /* Tail && Mask policy.  */
            asm_fprintf (file, "%s", IS_AGNOSTIC (UINTVAL (op)) ? "a" : "u");
          }
 
 
 
in riscv.cc.
 
 
The benefit is that we can avoid adding all th_vsetvl patterns and invasive 
code changs in VSETVL PASS.
 
 
 
 
juzhe.zh...@rivai.ai
 
 
From: Jun Sha (Joshua)
Date: 2023-12-29 12:21
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v4] RISC-V: Handle differences between XTheadvector and Vector
 
This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 
 
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
lik

Re：[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector

[joshua]

For vsetvl issues, what we want to do here is to directly
remove "t" and "m". 

If we add TARGET_XTHEADVECTOR logic in case "p" in
riscv_print_operand, how can we remove "t" and "m"? If I
use "break", assembly like "th.vsetvli zero,a5,e8,m1,t,m"
will be returned.

if (TARGET_THEADVECTOR)
...
else
else if (code == CONST_INT)
  {
/* Tail && Mask policy.  */
asm_fprintf (file, "%s", IS_AGNOSTIC (UINTVAL (op)) ? "a" : "u");
  }


--
发件人：juzhe.zh...@rivai.ai 
发送时间：2024年1月2日(星期二) 10:00
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主　题：Re: [PATCH v4] RISC-V: Handle differences between XTheadvector and Vector


+   if (TARGET_XTHEADVECTOR)
+    return false;



Move it to :
  if (TARGET_VECTOR && stringop_strategy & STRATEGY_VECTOR)
    {
      bool ok = riscv_vector::expand_block_move (dest, src, length);
      if (ok)
  return true;
    }





(define_special_predicate "vector_length_operand"
   (ior (match_operand 0 "pmode_register_operand")
-   (match_operand 0 "const_csr_operand")))
+  (and (match_test "!TARGET_XTHEADVECTOR || rtx_equal_p (op, const0_rtx)")
+    (match_operand 0 "const_csr_operand"



It's hard to trace. Change it into :


(ior
1. TARGET_THEADVECTOR && rtx_equal_p (op, const0_rtx) 
2. !TAGEET_THEADVECTOR && const_csr_operand)


+  if (TARGET_XTHEADVECTOR)
+  {
+   emit_insn (gen_pred_th_whole_mov (mode, dest, src,
+     RVV_VLMAX, GEN_INT(VLMAX)));
+   return true;
+  }



Move it outside legitimize_move
It should be it:


if (TARGET_THEADVECTOR)
emit_th_move...
DONE;
else if (riscv_vector::legitimize_move (operands[0], [1]))
    DONE; 




vsetvli issues:
I wonder whether we can use ASM_OUTPUT_OPCODE to recognize 
"ta,ma"/"ta,mu"/"tu,ma"/"tu,mu" and replace these 4 variants
by "". So that we don't have tail policy and mask policy in vsetvli ASM string.


Another alternative approach is we can change vsetlvi ASM rule:


"vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"


if (TARGET_THEADVECTOR)
...
else
        else if (code == CONST_INT)
          {
            /* Tail && Mask policy.  */
            asm_fprintf (file, "%s", IS_AGNOSTIC (UINTVAL (op)) ? "a" : "u");
          }



in riscv.cc.


The benefit is that we can avoid adding all th_vsetvl patterns and invasive 
code changs in VSETVL PASS.




juzhe.zh...@rivai.ai

 
From: Jun Sha (Joshua)
Date: 2023-12-29 12:21
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v4] RISC-V: Handle differences between XTheadvector and Vector

This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 
 
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r and vsext.vf2.
 
gcc/ChangeLog:
 
* config.gcc:  Add files for XTheadVector intrinsics.
* config/riscv/autovec.md: Guard XTheadVector.
* config/riscv/riscv-string.cc (expand_block_move):
Guard XTheadVector.
* config/riscv/riscv-v.cc (legitimize_move):
New expansion.
(get_prefer_tail_policy): Give specific value for tail.
(get_prefer_mask_policy): Give specific value for mask.
(vls_mode_valid_p): Avoid autovec.
* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
(build_one): New function.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
(DEF_THEAD_RVV_FUNCTION): Add new marcos.
(check_required_extensions):
(handle_pragma_vector):
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR):
(RVV_REQUIRE_XTHEADVECTOR):
Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR.
(struct function_group_info):
* config/riscv/riscv-vector-switch.def (ENTRY):
Disable fractional mode for the XTheadVector extension.
(TUPLE_ENTRY): Likewise.
* config/riscv/riscv-vsetvl.cc: Add function

[PATCH v4 6/6] RISC-V: Add support for xtheadvector-specific intrinsics.

[Jun Sha (Joshua)]

re_width, none_m_preds, 
iu8_v_scalar_ptr_size_ops)
+DEF_RVV_FUNCTION (th_vssh, th_loadstore_width, none_m_preds, 
iu16_v_scalar_ptr_size_ops)
+DEF_RVV_FUNCTION (th_vssw, th_loadstore_width, none_m_preds, 
iu32_v_scalar_ptr_size_ops)
+DEF_RVV_FUNCTION (th_vlxb, th_indexed_loadstore_width, full_preds, 
i8_v_scalar_const_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vlxh, th_indexed_loadstore_width, full_preds, 
i16_v_scalar_const_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vlxw, th_indexed_loadstore_width, full_preds, 
i32_v_scalar_const_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vlxbu, th_indexed_loadstore_width, full_preds, 
u8_v_scalar_const_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vlxhu, th_indexed_loadstore_width, full_preds, 
u16_v_scalar_const_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vlxwu, th_indexed_loadstore_width, full_preds, 
u32_v_scalar_const_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsxb, th_indexed_loadstore_width, none_m_preds, 
iu8_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsxh, th_indexed_loadstore_width, none_m_preds, 
iu16_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsxw, th_indexed_loadstore_width, none_m_preds, 
iu32_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsuxb, th_indexed_loadstore_width, none_m_preds, 
iu8_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsuxh, th_indexed_loadstore_width, none_m_preds, 
iu16_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsuxw, th_indexed_loadstore_width, none_m_preds, 
iu32_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vext_x_v, th_extract, none_preds, iu_x_s_u_ops)
+#undef REQUIRED_EXTENSIONS
+
+#undef DEF_RVV_FUNCTION
diff --git a/gcc/config/riscv/thead-vector-builtins.cc 
b/gcc/config/riscv/thead-vector-builtins.cc
new file mode 100644
index 000..c0002f255ee
--- /dev/null
+++ b/gcc/config/riscv/thead-vector-builtins.cc
@@ -0,0 +1,200 @@
+/* function_base implementation for RISC-V XTheadVector Extension
+   for GNU compiler.
+   Copyright (C) 2022-2023 Free Software Foundation, Inc.
+   Contributed by Joshua (cooper.jos...@linux.alibaba.com), T-Head
+   Semiconductor Co., Ltd.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "tree.h"
+#include "rtl.h"
+#include "tm_p.h"
+#include "memmodel.h"
+#include "insn-codes.h"
+#include "optabs.h"
+#include "recog.h"
+#include "expr.h"
+#include "basic-block.h"
+#include "function.h"
+#include "fold-const.h"
+#include "gimple.h"
+#include "gimple-iterator.h"
+#include "gimplify.h"
+#include "explow.h"
+#include "emit-rtl.h"
+#include "tree-vector-builder.h"
+#include "rtx-vector-builder.h"
+#include "riscv-vector-builtins.h"
+#include "riscv-vector-builtins-shapes.h"
+#include "riscv-vector-builtins-bases.h"
+#include "thead-vector-builtins.h"
+
+using namespace riscv_vector;
+
+namespace riscv_vector {
+
+/* Implements
+ * th.vl(b/h/w)[u].v/th.vs(b/h/w)[u].v/th.vls(b/h/w)[u].v/th.vss(b/h/w)[u].v/
+ * th.vlx(b/h/w)[u].v/th.vs[u]x(b/h/w).v
+ * codegen.  */
+template
+class th_loadstore_width : public function_base
+{
+public:
+  bool apply_tail_policy_p () const override { return !STORE_P; }
+  bool apply_mask_policy_p () const override { return !STORE_P; }
+
+  unsigned int call_properties (const function_instance &) const override
+  {
+if (STORE_P)
+  return CP_WRITE_MEMORY;
+else
+  return CP_READ_MEMORY;
+  }
+
+  bool can_be_overloaded_p (enum predication_type_index pred) const override
+  {
+if (STORE_P || LST_TYPE == LST_INDEXED)
+  return true;
+return pred != PRED_TYPE_none;
+  }
+
+  rtx expand (function_expander ) const override
+  {
+gcc_assert (TARGET_XTHEADVECTOR);
+if (LST_TYPE == LST_INDEXED)
+  {
+   if (STORE_P)
+ return e.use_exact_insn (
+   code_for_pred_indexed_store_width (UNSPEC, UNSPEC,
+  e.vector_mode ()));
+   else
+ return e.use_exact_insn (
+   code_for_pred_indexed_load_width (UNSPEC, e.vector_mode ()));
+  }
+else if (LST_TYPE == LST_STRIDED)
+  {
+   if (STORE_P)
+ return e.use_contiguous_

[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector

[Jun Sha (Joshua)]

This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 

For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r and vsext.vf2.

gcc/ChangeLog:

* config.gcc:  Add files for XTheadVector intrinsics.
* config/riscv/autovec.md: Guard XTheadVector.
* config/riscv/riscv-string.cc (expand_block_move):
Guard XTheadVector.
* config/riscv/riscv-v.cc (legitimize_move):
New expansion.
(get_prefer_tail_policy): Give specific value for tail.
(get_prefer_mask_policy): Give specific value for mask.
(vls_mode_valid_p): Avoid autovec.
* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
(build_one): New function.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
(DEF_THEAD_RVV_FUNCTION): Add new marcos.
(check_required_extensions):
(handle_pragma_vector):
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR):
(RVV_REQUIRE_XTHEADVECTOR):
Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR.
(struct function_group_info):
* config/riscv/riscv-vector-switch.def (ENTRY):
Disable fractional mode for the XTheadVector extension.
(TUPLE_ENTRY): Likewise.
* config/riscv/riscv-vsetvl.cc: Add functions for xtheadvector.
* config/riscv/riscv.cc (riscv_v_ext_vls_mode_p):
Guard XTheadVector.
(riscv_v_adjust_bytesize): Likewise.
(riscv_preferred_simd_mode): Likewsie.
(riscv_autovectorize_vector_modes): Likewise.
(riscv_vector_mode_supported_any_target_p): Likewise.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
* config/riscv/vector-iterators.md: Remove fractional LMUL.
* config/riscv/vector.md: Include thead-vector.md.
* config/riscv/riscv_th_vector.h: New file.
* config/riscv/thead-vector.md: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector.
* gcc.target/riscv/rvv/base/abi-1.c: Exclude XTheadVector.
* lib/target-supports.exp: Add target for XTheadVector.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/autovec.md   |   2 +-
 gcc/config/riscv/predicates.md|   3 +-
 gcc/config/riscv/riscv-string.cc  |   3 +
 gcc/config/riscv/riscv-v.cc   |  13 +-
 .../riscv/riscv-vector-builtins-bases.cc  |   3 +
 .../riscv/riscv-vector-builtins-shapes.cc |  23 +++
 gcc/config/riscv/riscv-vector-switch.def  | 150 +++---
 gcc/config/riscv/riscv-vsetvl.cc  |  10 +
 gcc/config/riscv/riscv.cc |  20 +-
 gcc/config/riscv/riscv_th_vector.h|  49 +
 gcc/config/riscv/thead-vector.md  | 142 +
 gcc/config/riscv/vector-iterators.md  | 186 +-
 gcc/config/riscv/vector.md|  36 +++-
 .../gcc.target/riscv/rvv/base/abi-1.c |   2 +-
 .../gcc.target/riscv/rvv/base/pragma-1.c  |   2 +-
 gcc/testsuite/lib/target-supports.exp |  12 ++
 17 files changed, 471 insertions(+), 187 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_th_vector.h
 create mode 100644 gcc/config/riscv/thead-vector.md

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f0676c830e8..1445d98c147 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,7 +549,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_th_vector.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 8b8a92f10a1..1fac56c7095 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2579,7 +2579,7 @@
   [(match_operand  0 "register_operand")
(match_operand  1 "memory_operand")
(match_operand:ANYI 2 "const_int_operand")]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   {
 

[PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

[Jun Sha (Joshua)]

This patch adds th. prefix to all XTheadVector instructions by
implementing new assembly output functions. We only check the
prefix is 'v', so that no extra attribute is needed.

gcc/ChangeLog:

* config/riscv/riscv-protos.h (riscv_asm_output_opcode): 
New function to add assembler insn code prefix/suffix.
* config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
* config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config/riscv/riscv-protos.h|  1 +
 gcc/config/riscv/riscv.cc  | 14 ++
 gcc/config/riscv/riscv.h   |  4 
 .../gcc.target/riscv/rvv/xtheadvector/prefix.c | 12 
 4 files changed, 31 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 31049ef7523..5ea54b45703 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -102,6 +102,7 @@ struct riscv_address_info {
 };
 
 /* Routines implemented in riscv.cc.  */
+extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
 extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
 extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
 extern int riscv_float_const_rtx_index_for_fli (rtx);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0d1cbc5cb5f..ea1d59d9cf2 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode)
   return lmul;
 }
 
+/* Define ASM_OUTPUT_OPCODE to do anything special before
+   emitting an opcode.  */
+const char *
+riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
+{
+  /* We need to add th. prefix to all the xtheadvector
+ insturctions here.*/
+  if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX &&
+  p[0] == 'v')
+fputs ("th.", asm_out_file);
+
+  return p;
+}
+
 /* Implement TARGET_PRINT_OPERAND.  The RISCV-specific operand codes are:
 
'h' Print the high-part relocation associated with OP, after stripping
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 6df9ec73c5e..c33361a254d 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -826,6 +826,10 @@ extern enum riscv_cc get_riscv_cc (const rtx use);
   asm_fprintf ((FILE), "%U%s", (NAME));\
   } while (0)
 
+#undef ASM_OUTPUT_OPCODE
+#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
+  (PTR) = riscv_asm_output_opcode(STREAM, PTR)
+
 #define JUMP_TABLES_IN_TEXT_SECTION 0
 #define CASE_VECTOR_MODE SImode
 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
new file mode 100644
index 000..eee727ef6b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadvector -mabi=ilp32 -O0" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+prefix (vint32m1_t vx, vint32m1_t vy, size_t vl)
+{
+  return __riscv_vadd_vv_i32m1 (vx, vy, vl);
+}
+
+/* { dg-final { scan-assembler {\mth\.v\M} } } */
-- 
2.17.1

[PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0

[Jun Sha (Joshua)]

This patch is to introduce basic XTheadVector support
(march string parsing and a test for __riscv_xtheadvector)
according to https://github.com/T-head-Semi/thead-extension-spec/

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_subset_list::parse): Add new vendor extension.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
Add test marco.
* config/riscv/riscv.opt:  Add new mask.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-__riscv_th_v_intrinsic.c: New test.
* gcc.target/riscv/rvv/xtheadvector.c: New test.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/common/config/riscv/riscv-common.cc   | 23 +++
 gcc/config/riscv/riscv-c.cc   |  8 +--
 gcc/config/riscv/riscv.opt|  2 ++
 .../riscv/predef-__riscv_th_v_intrinsic.c | 11 +
 .../gcc.target/riscv/rvv/xtheadvector.c   | 13 +++
 5 files changed, 55 insertions(+), 2 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index f20d179568d..66b20c154a9 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -368,6 +368,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadvector", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
 
@@ -1251,6 +1252,15 @@ riscv_subset_list::check_conflict_ext ()
   if (lookup ("zcmp"))
error_at (m_loc, "%<-march=%s%>: zcd conflicts with zcmp", m_arch);
 }
+
+  if ((lookup ("v") || lookup ("zve32x")
+|| lookup ("zve64x") || lookup ("zve32f")
+|| lookup ("zve64f") || lookup ("zve64d")
+|| lookup ("zvl32b") || lookup ("zvl64b")
+|| lookup ("zvl128b") || lookup ("zvfh"))
+&& lookup ("xtheadvector"))
+error_at (m_loc, "%<-march=%s%>: xtheadvector conflicts with vector "
+  "extension or its sub-extensions", m_arch);
 }
 
 /* Parsing function for multi-letter extensions.
@@ -1743,6 +1753,19 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"xtheadmemidx",  _options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
   {"xtheadmempair", _options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
   {"xtheadsync",_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
+  {"xtheadvector",  _options::x_riscv_xthead_subext, MASK_XTHEADVECTOR},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_32},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_64},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_32},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_64},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_16},
+  {"xtheadvector",  _options::x_riscv_zvl_flags, MASK_ZVL32B},
+  {"xtheadvector",  _options::x_riscv_zvl_flags, MASK_ZVL64B},
+  {"xtheadvector",  _options::x_riscv_zvl_flags, MASK_ZVL128B},
+  {"xtheadvector",  _options::x_riscv_zf_subext, MASK_ZVFHMIN},
+  {"xtheadvector",  _options::x_riscv_zf_subext, MASK_ZVFH},
+  {"xtheadvector",  _options::x_target_flags, MASK_FULL_V},
+  {"xtheadvector",  _options::x_target_flags, MASK_VECTOR},
 
   {"xventanacondops", _options::x_riscv_xventana_subext, 
MASK_XVENTANACONDOPS},
 
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index d70eb8ed361..d7c63ead147 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -138,6 +138,10 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
 riscv_ext_version_value (0, 11));
 }
 
+   if (TARGET_XTHEADVECTOR)
+ builtin_define_with_int_value ("__riscv_th_v_intrinsic",
+riscv_ext_version_value (0, 11));
+
   /* Define architecture extension test macros.  */
   builtin_define_with_int_value ("__riscv_arch_test", 1);
 
@@ -191,8 +195,8 @@ riscv_pragma_intrinsic (cpp_reader *)
 {
   if (!TARGET_VECTOR)
{
- error ("%<#pragma riscv intrinsic%> option %qs needs 'V' extension "
-"enabled",
+ error ("%<#pragma riscv intrinsic%> option %qs needs 'V' or "
+"'XTHEADVECTOR' extension enabled",
 name);
  return;
}
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index ede2d655e73..7de5f18e11b 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -449,6 +449,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext)
 
 Mask(XTHEADSYNC)

[PATCH v4] RISC-V: Change csr_operand into vector_length_operand for vsetvl patterns.

[Jun Sha (Joshua)]

This patch use vector_length_operand instead of csr_operand for
vsetvl patterns, so that changes for vector will not affect scalar
patterns using csr_operand in riscv.md.

gcc/ChangeLog:

* config/riscv/vector.md:
Use vector_length_operand for vsetvl patterns.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config/riscv/vector.md | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index f607d768b26..b5a9055cdc4 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1496,7 +1496,7 @@
 
 (define_insn "@vsetvl"
   [(set (match_operand:P 0 "register_operand" "=r")
-   (unspec:P [(match_operand:P 1 "csr_operand" "rK")
+   (unspec:P [(match_operand:P 1 "vector_length_operand" "rK")
   (match_operand 2 "const_int_operand" "i")
   (match_operand 3 "const_int_operand" "i")
   (match_operand 4 "const_int_operand" "i")
@@ -1542,7 +1542,7 @@
 ;; in vsetvl instruction pattern.
 (define_insn "@vsetvl_discard_result"
   [(set (reg:SI VL_REGNUM)
-   (unspec:SI [(match_operand:P 0 "csr_operand" "rK")
+   (unspec:SI [(match_operand:P 0 "vector_length_operand" "rK")
(match_operand 1 "const_int_operand" "i")
(match_operand 2 "const_int_operand" "i")] UNSPEC_VSETVL))
(set (reg:SI VTYPE_REGNUM)
@@ -1564,7 +1564,7 @@
 ;; such pattern can allow us gain benefits of these optimizations.
 (define_insn_and_split "@vsetvl_no_side_effects"
   [(set (match_operand:P 0 "register_operand" "=r")
-   (unspec:P [(match_operand:P 1 "csr_operand" "rK")
+   (unspec:P [(match_operand:P 1 "vector_length_operand" "rK")
   (match_operand 2 "const_int_operand" "i")
   (match_operand 3 "const_int_operand" "i")
   (match_operand 4 "const_int_operand" "i")
@@ -1608,7 +1608,7 @@
   [(set (match_operand:DI 0 "register_operand")
 (sign_extend:DI
   (subreg:SI
-   (unspec:DI [(match_operand:P 1 "csr_operand")
+   (unspec:DI [(match_operand:P 1 "vector_length_operand")
(match_operand 2 "const_int_operand")
(match_operand 3 "const_int_operand")
(match_operand 4 "const_int_operand")
-- 
2.17.1

[PATCH v4] RISC-V: Change csr_operand into

[Jun Sha (Joshua)]

This patch use vector_length_operand instead of csr_operand for
vsetvl patterns, so that changes for vector will not affect scalar
patterns using csr_operand in riscv.md.

gcc/ChangeLog:

* config/riscv/vector.md:
Use vector_length_operand for vsetvl patterns.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config/riscv/vector.md | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index f607d768b26..b5a9055cdc4 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1496,7 +1496,7 @@
 
 (define_insn "@vsetvl"
   [(set (match_operand:P 0 "register_operand" "=r")
-   (unspec:P [(match_operand:P 1 "csr_operand" "rK")
+   (unspec:P [(match_operand:P 1 "vector_length_operand" "rK")
   (match_operand 2 "const_int_operand" "i")
   (match_operand 3 "const_int_operand" "i")
   (match_operand 4 "const_int_operand" "i")
@@ -1542,7 +1542,7 @@
 ;; in vsetvl instruction pattern.
 (define_insn "@vsetvl_discard_result"
   [(set (reg:SI VL_REGNUM)
-   (unspec:SI [(match_operand:P 0 "csr_operand" "rK")
+   (unspec:SI [(match_operand:P 0 "vector_length_operand" "rK")
(match_operand 1 "const_int_operand" "i")
(match_operand 2 "const_int_operand" "i")] UNSPEC_VSETVL))
(set (reg:SI VTYPE_REGNUM)
@@ -1564,7 +1564,7 @@
 ;; such pattern can allow us gain benefits of these optimizations.
 (define_insn_and_split "@vsetvl_no_side_effects"
   [(set (match_operand:P 0 "register_operand" "=r")
-   (unspec:P [(match_operand:P 1 "csr_operand" "rK")
+   (unspec:P [(match_operand:P 1 "vector_length_operand" "rK")
   (match_operand 2 "const_int_operand" "i")
   (match_operand 3 "const_int_operand" "i")
   (match_operand 4 "const_int_operand" "i")
@@ -1608,7 +1608,7 @@
   [(set (match_operand:DI 0 "register_operand")
 (sign_extend:DI
   (subreg:SI
-   (unspec:DI [(match_operand:P 1 "csr_operand")
+   (unspec:DI [(match_operand:P 1 "vector_length_operand")
(match_operand 2 "const_int_operand")
(match_operand 3 "const_int_operand")
(match_operand 4 "const_int_operand")
-- 
2.17.1

[PATCH v4] RISC-V: Refactor riscv-vector-builtins-bases.cc

[Jun Sha (Joshua)]

This patch moves the definition of the enums lst_type and
frm_op_type into riscv-vector-builtins-bases.h and removes
the static visibility of fold_fault_load(), so these
can be used in other compile units.

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc (enum lst_type):
(enum frm_op_type): move to riscv-vector-builtins-bases.h
* config/riscv/riscv-vector-builtins-bases.h
(GCC_RISCV_VECTOR_BUILTINS_BASES_H): Add header files.
(enum lst_type): move from
(enum frm_op_type): riscv-vector-builtins-bases.cc
(fold_fault_load): riscv-vector-builtins-bases.cc

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 .../riscv/riscv-vector-builtins-bases.cc  | 18 +-
 .../riscv/riscv-vector-builtins-bases.h   | 19 +++
 2 files changed, 20 insertions(+), 17 deletions(-)

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index d70468542ee..c51affde353 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -48,24 +48,8 @@ using namespace riscv_vector;
 
 namespace riscv_vector {
 
-/* Enumerates types of loads/stores operations.
-   It's only used in here so we don't define it
-   in riscv-vector-builtins-bases.h.  */
-enum lst_type
-{
-  LST_UNIT_STRIDE,
-  LST_STRIDED,
-  LST_INDEXED,
-};
-
-enum frm_op_type
-{
-  NO_FRM,
-  HAS_FRM,
-};
-
 /* Helper function to fold vleff and vlsegff.  */
-static gimple *
+gimple *
 fold_fault_load (gimple_folder )
 {
   /* fold fault_load (const *base, size_t *new_vl, size_t vl)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h 
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 131041ea66f..42d0cd17dc1 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -21,8 +21,27 @@
 #ifndef GCC_RISCV_VECTOR_BUILTINS_BASES_H
 #define GCC_RISCV_VECTOR_BUILTINS_BASES_H
 
+#include "gimple.h"
+#include "riscv-vector-builtins.h"
+
 namespace riscv_vector {
 
+/* Enumerates types of loads/stores operations.  */
+enum lst_type
+{
+  LST_UNIT_STRIDE,
+  LST_STRIDED,
+  LST_INDEXED,
+};
+
+enum frm_op_type
+{
+  NO_FRM,
+  HAS_FRM,
+};
+
+extern gimple *fold_fault_load (gimple_folder );
+
 namespace bases {
 extern const function_base *const vsetvl;
 extern const function_base *const vsetvlmax;
-- 
2.17.1

[PATCH v4] RISC-V: Support XTheadVector extension

[Jun Sha (Joshua)]

This patch series presents gcc implementation of the XTheadVector
extension [1].

[1] https://github.com/T-head-Semi/thead-extension-spec/

For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in order not to
generate instructions that xtheadvector does not support,
causing 36 changes in vector.md.

For the th. prefix issue, we use current_output_insn and
the ASM_OUTPUT_OPCODE hook instead of directly modifying
patterns in vector.md.

We have run the GCC test suite and can confirm that there
are no regressions.

All the test results can be found in the following links,
Run without xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803686.html

Run with xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803687.html

Furthermore, we have run the tests in 
https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples, 
and all the tests passed.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 

RISC-V: Refactor riscv-vector-builtins-bases.cc
RISC-V: Change csr_operand into vector_length_operand for vsetvl patterns
RISC-V: Introduce XTheadVector as a subset of V1.0.0
RISC-V: Adds the prefix "th." for the instructions of XTheadVector
RISC-V: Handle differences between XTheadvector and Vector
RISC-V: Add support for xtheadvector-specific intrinsics
RISC-V: ...

---
 gcc/common/config/riscv/riscv-common.cc   |   23 +
 gcc/config.gcc|4 +-
 gcc/config/riscv/autovec.md   |2 +-
 gcc/config/riscv/predicates.md|8 +-
 gcc/config/riscv/riscv-c.cc   |8 +-
 gcc/config/riscv/riscv-protos.h   |1 +
 gcc/config/riscv/riscv-string.cc  |3 +
 gcc/config/riscv/riscv-v.cc   |   13 +-
 .../riscv/riscv-vector-builtins-bases.cc  |   18 +-
 .../riscv/riscv-vector-builtins-bases.h   |   19 +
 .../riscv/riscv-vector-builtins-shapes.cc |  149 +
 .../riscv/riscv-vector-builtins-shapes.h  |3 +
 .../riscv/riscv-vector-builtins-types.def |  120 +
 gcc/config/riscv/riscv-vector-builtins.cc |  315 +-
 gcc/config/riscv/riscv-vector-builtins.h  |5 +-
 gcc/config/riscv/riscv-vector-switch.def  |  150 +-
 gcc/config/riscv/riscv.cc |   46 +-
 gcc/config/riscv/riscv.h  |4 +
 gcc/config/riscv/riscv.opt|2 +
 gcc/config/riscv/riscv_th_vector.h|   49 +
 gcc/config/riscv/t-riscv  |   16 +
 .../riscv/thead-vector-builtins-functions.def |  659 
 gcc/config/riscv/thead-vector-builtins.cc |  887 ++
 gcc/config/riscv/thead-vector-builtins.h  |  123 +
 gcc/config/riscv/thead-vector.md  | 2827 +
 gcc/config/riscv/vector-iterators.md  |  186 +-
 gcc/config/riscv/vector.md|   44 +-
 .../riscv/predef-__riscv_th_v_intrinsic.c |   11 +
 .../gcc.target/riscv/rvv/base/abi-1.c |2 +-
 .../gcc.target/riscv/rvv/base/pragma-1.c  |2 +-
 .../gcc.target/riscv/rvv/xtheadvector.c   |   13 +
 .../riscv/rvv/xtheadvector/prefix.c   |   12 +
 .../riscv/rvv/xtheadvector/vlb-vsb.c  |   68 +
 .../riscv/rvv/xtheadvector/vlbu-vsb.c |   68 +
 .../riscv/rvv/xtheadvector/vlh-vsh.c  |   68 +
 .../riscv/rvv/xtheadvector/vlhu-vsh.c |   68 +
 .../riscv/rvv/xtheadvector/vlw-vsw.c  |   68 +
 .../riscv/rvv/xtheadvector/vlwu-vsw.c |   68 +
 gcc/testsuite/lib/target-supports.exp |   12 +
 39 files changed, 5931 insertions(+), 213 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_th_vector.h
 create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def
 create mode 100644 gcc/config/riscv/thead-vector-builtins.cc
 create mode 100644 gcc/config/riscv/thead-vector-builtins.h
 create mode 100644 gcc/config/riscv/thead-vector.md
 create mode 100644 
gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c

Re：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector

[joshua]

Hi Juzhe,

These vsetvl patterns were written by you with csr_operand initially.
Are you sure it can be repalced by vector_length_operand?

Joshua






--
发件人：juzhe.zh...@rivai.ai 
发送时间：2023年12月29日(星期五) 10:25
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and 
Vector


Chnage it into vector_length_operand.


juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2023-12-29 10:25
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and 
Vector

We do not have vector_length_operand in vsetvl patterns.
 
(define_insn "@vsetvl"
  [(set (match_operand:P 0 "register_operand" "=r")
(unspec:P [(match_operand:P 1 "vector_csr_operand" "rK")
   (match_operand 2 "const_int_operand" "i")
   (match_operand 3 "const_int_operand" "i")
   (match_operand 4 "const_int_operand" "i")
   (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))
   (set (reg:SI VL_REGNUM)
(unspec:SI [(match_dup 1)
    (match_dup 2)
    (match_dup 3)] UNSPEC_VSETVL))
   (set (reg:SI VTYPE_REGNUM)
(unspec:SI [(match_dup 2)
    (match_dup 3)
    (match_dup 4)
    (match_dup 5)] UNSPEC_VSETVL))]
  "TARGET_VECTOR"
  "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"
  [(set_attr "type" "vsetvl")
   (set_attr "mode" "")
   (set (attr "sew") (symbol_ref "INTVAL (operands[2])"))
   (set (attr "vlmul") (symbol_ref "INTVAL (operands[3])"))
   (set (attr "ta") (symbol_ref "INTVAL (operands[4])"))
   (set (attr "ma") (symbol_ref "INTVAL (operands[5])"))])
 
 
 
 
 
 
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2023年12月29日(星期五) 10:22
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and 
Vector
 
 
Why add vector_csr_operand ?
Why not use vector_length_operand?
 
 
juzhe.zh...@rivai.ai
 
 
发件人： joshua
发送时间： 2023-12-29 10:17
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector
 
Hi Juzhe,
 
For vector_csr_operand, please refer to
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641124.html.
 
Joshua
 
 
 
 
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2023年12月29日(星期五) 10:14
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: 回复：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and 
Vector
 
 
No, we should handle this carefully step by step.
 
 
First, after the the first kind of theadvector is merged, then we can talk 
about second kind of theadvector later.
 
 
I am confused by this patch for example:
 
 
 (define_predicate "vector_csr_operand"-  (ior (match_operand 0 
"const_csr_operand")-   (match_operand 0 "register_operand")))+  (ior (and 
(match_test "!TARGET_XTHEADVECTOR || rtx_equal_p (op, const0_rtx)")+  
(match_operand 0 "const_csr_operand"))+    (match_operand 0 
"register_operand")))
 
 
I just checked upstream code, we don't have vector_csr_operand.
 
 
So, to make me easily review and trace the codes, plz send the patch better 
organized.
 
 
Thanks.
juzhe.zh...@rivai.ai
 
 
发件人： joshua
发送时间： 2023-12-29 10:09
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： 回复：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector
 
H Juzhe,
 
This patch "RISC-V: Handle differences between XTheadvector and
Vector" is addressing some code generation issues for RVV1.0
instructions that xtheadvector does not have, not with intrinsics.
 
BTW, what about the following patch " RISC-V: Add support for
xtheadvector-specific intrinsics"?It adds support new xtheadvect

Re：Re：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector

[joshua]

We do not have vector_length_operand in vsetvl patterns.

(define_insn "@vsetvl"
  [(set (match_operand:P 0 "register_operand" "=r")
(unspec:P [(match_operand:P 1 "vector_csr_operand" "rK")
   (match_operand 2 "const_int_operand" "i")
   (match_operand 3 "const_int_operand" "i")
   (match_operand 4 "const_int_operand" "i")
   (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))
   (set (reg:SI VL_REGNUM)
(unspec:SI [(match_dup 1)
(match_dup 2)
(match_dup 3)] UNSPEC_VSETVL))
   (set (reg:SI VTYPE_REGNUM)
(unspec:SI [(match_dup 2)
(match_dup 3)
(match_dup 4)
(match_dup 5)] UNSPEC_VSETVL))]
  "TARGET_VECTOR"
  "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"
  [(set_attr "type" "vsetvl")
   (set_attr "mode" "")
   (set (attr "sew") (symbol_ref "INTVAL (operands[2])"))
   (set (attr "vlmul") (symbol_ref "INTVAL (operands[3])"))
   (set (attr "ta") (symbol_ref "INTVAL (operands[4])"))
   (set (attr "ma") (symbol_ref "INTVAL (operands[5])"))])







--
发件人：juzhe.zh...@rivai.ai 
发送时间：2023年12月29日(星期五) 10:22
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: Re：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and 
Vector


Why add vector_csr_operand ?
Why not use vector_length_operand?


juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2023-12-29 10:17
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： Re：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector

Hi Juzhe,
 
For vector_csr_operand, please refer to
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641124.html.
 
Joshua
 
 
 
 
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2023年12月29日(星期五) 10:14
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: 回复：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and 
Vector
 
 
No, we should handle this carefully step by step.
 
 
First, after the the first kind of theadvector is merged, then we can talk 
about second kind of theadvector later.
 
 
I am confused by this patch for example:
 
 
 (define_predicate "vector_csr_operand"-  (ior (match_operand 0 
"const_csr_operand")-   (match_operand 0 "register_operand")))+  (ior (and 
(match_test "!TARGET_XTHEADVECTOR || rtx_equal_p (op, const0_rtx)")+  
(match_operand 0 "const_csr_operand"))+    (match_operand 0 
"register_operand")))
 
 
I just checked upstream code, we don't have vector_csr_operand.
 
 
So, to make me easily review and trace the codes, plz send the patch better 
organized.
 
 
Thanks.
juzhe.zh...@rivai.ai
 
 
发件人： joshua
发送时间： 2023-12-29 10:09
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： 回复：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector
 
H Juzhe,
 
This patch "RISC-V: Handle differences between XTheadvector and
Vector" is addressing some code generation issues for RVV1.0
instructions that xtheadvector does not have, not with intrinsics.
 
BTW, what about the following patch " RISC-V: Add support for
xtheadvector-specific intrinsics"?It adds support new xtheadvector
instructions. Is it OK to be merged?
 
Joshua
 
 
 
 
 
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2023年12月29日(星期五) 09:58
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主　题：Re: [PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and 
Vector
 
 
I am confused by the series patches.
 
 
I thought this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641417.html 
is enough to support partial theadvector that can leverage directly RVV1.0 ?
 
 
Could clean up and resend the patches base on patch above (supposed it is 
merged already) ?
 
 
juzhe.zh...@rivai.ai
 
 
From: Jun Sha (Joshua)
Date: 2023-12-29 09:46
To: gcc-patches
CC: jim.wi

Re：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector

[joshua]

Hi Juzhe,

For vector_csr_operand, please refer to
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641124.html.

Joshua





--
发件人：juzhe.zh...@rivai.ai 
发送时间：2023年12月29日(星期五) 10:14
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: 回复：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and 
Vector


No, we should handle this carefully step by step.


First, after the the first kind of theadvector is merged, then we can talk 
about second kind of theadvector later.


I am confused by this patch for example:


 (define_predicate "vector_csr_operand"-  (ior (match_operand 0 
"const_csr_operand")-   (match_operand 0 "register_operand")))+  (ior (and 
(match_test "!TARGET_XTHEADVECTOR || rtx_equal_p (op, const0_rtx)")+  
(match_operand 0 "const_csr_operand"))+(match_operand 0 
"register_operand")))


I just checked upstream code, we don't have vector_csr_operand.


So, to make me easily review and trace the codes, plz send the patch better 
organized.


Thanks.
juzhe.zh...@rivai.ai

 
发件人： joshua
发送时间： 2023-12-29 10:09
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; jinma; cooper.qu
主题： 回复：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector

H Juzhe,
 
This patch "RISC-V: Handle differences between XTheadvector and
Vector" is addressing some code generation issues for RVV1.0
instructions that xtheadvector does not have, not with intrinsics.
 
BTW, what about the following patch " RISC-V: Add support for
xtheadvector-specific intrinsics"?It adds support new xtheadvector
instructions. Is it OK to be merged?
 
Joshua
 
 
 
 
 
 
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2023年12月29日(星期五) 09:58
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主　题：Re: [PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and 
Vector
 
 
I am confused by the series patches.
 
 
I thought this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641417.html 
is enough to support partial theadvector that can leverage directly RVV1.0 ?
 
 
Could clean up and resend the patches base on patch above (supposed it is 
merged already) ?
 
 
juzhe.zh...@rivai.ai
 
 
From: Jun Sha (Joshua)
Date: 2023-12-29 09:46
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and 
Vector
 
This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 
 
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r and vsext.vf2.
 
gcc/ChangeLog:
 
* config.gcc:  Add files for XTheadVector intrinsics.
* config/riscv/autovec.md: Guard XTheadVector.
* config/riscv/riscv-string.cc (expand_block_move):
Guard XTheadVector.
* config/riscv/riscv-v.cc (legitimize_move):
New expansion.
(get_prefer_tail_policy): Give specific value for tail.
(get_prefer_mask_policy): Give specific value for mask.
(vls_mode_valid_p): Avoid autovec.
* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
(build_one): New function.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
(DEF_THEAD_RVV_FUNCTION): Add new marcos.
(check_required_extensions):
(handle_pragma_vector):
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR):
(RVV_REQUIRE_XTHEADVECTOR):
Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR.
(struct function_group_info):
* config/riscv/riscv-vector-switch.def (ENTRY):
Disable fractional mode for the XTheadVector extension.
(TUPLE_ENTRY): Likewise.
* config/riscv/riscv-vsetvl.cc: Add functions for xtheadvector.
* config/riscv/riscv.cc (riscv_v_ext_vls_mode_p):
Guard XTheadVect

Re：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector

[joshua]

H Juzhe,

This patch "RISC-V: Handle differences between XTheadvector and
Vector" is addressing some code generation issues for RVV1.0
instructions that xtheadvector does not have, not with intrinsics.

BTW, what about the following patch " RISC-V: Add support for
xtheadvector-specific intrinsics"? It adds support for new xtheadvector
instructions. Is it OK to be merged?

Joshua






--
发件人：juzhe.zh...@rivai.ai 
发送时间：2023年12月29日(星期五) 09:58
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主　题：Re: [PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and 
Vector


I am confused by the series patches.


I thought this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641417.html 
is enough to support partial theadvector that can leverage directly RVV1.0 ?


Could clean up and resend the patches base on patch above (supposed it is 
merged already) ?


juzhe.zh...@rivai.ai

 
From: Jun Sha (Joshua)
Date: 2023-12-29 09:46
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and 
Vector

This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 
 
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r and vsext.vf2.
 
gcc/ChangeLog:
 
* config.gcc:  Add files for XTheadVector intrinsics.
* config/riscv/autovec.md: Guard XTheadVector.
* config/riscv/riscv-string.cc (expand_block_move):
Guard XTheadVector.
* config/riscv/riscv-v.cc (legitimize_move):
New expansion.
(get_prefer_tail_policy): Give specific value for tail.
(get_prefer_mask_policy): Give specific value for mask.
(vls_mode_valid_p): Avoid autovec.
* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
(build_one): New function.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
(DEF_THEAD_RVV_FUNCTION): Add new marcos.
(check_required_extensions):
(handle_pragma_vector):
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR):
(RVV_REQUIRE_XTHEADVECTOR):
Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR.
(struct function_group_info):
* config/riscv/riscv-vector-switch.def (ENTRY):
Disable fractional mode for the XTheadVector extension.
(TUPLE_ENTRY): Likewise.
* config/riscv/riscv-vsetvl.cc: Add functions for xtheadvector.
* config/riscv/riscv.cc (riscv_v_ext_vls_mode_p):
Guard XTheadVector.
(riscv_v_adjust_bytesize): Likewise.
(riscv_preferred_simd_mode): Likewsie.
(riscv_autovectorize_vector_modes): Likewise.
(riscv_vector_mode_supported_any_target_p): Likewise.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
* config/riscv/vector-iterators.md: Remove fractional LMUL.
* config/riscv/vector.md: Include thead-vector.md.
* config/riscv/riscv_th_vector.h: New file.
* config/riscv/thead-vector.md: New file.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector.
* gcc.target/riscv/rvv/base/abi-1.c: Exclude XTheadVector.
* lib/target-supports.exp: Add target for XTheadVector.
 
Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config.gcc    |   2 +-
 gcc/config/riscv/autovec.md   |   2 +-
 gcc/config/riscv/predicates.md    |   8 +-
 gcc/config/riscv/riscv-string.cc  |   3 +
 gcc/config/riscv/riscv-v.cc   |  13 +-
 .../riscv/riscv-vector-builtins-bases.cc  |   3 +
 .../riscv/riscv-vector-builtins-shapes.cc |  23 +++
 gcc/config/riscv/riscv-vector-switch.def  | 150 +++---
 gcc/config/riscv/riscv-vsetvl.cc  |  10 +
 gcc/config/riscv/riscv.cc |  20 +-
 gcc/config/riscv/riscv_th_vector.h    |  49 +
 gcc/config/riscv/thead-vector.md  | 142 +
 gcc/config/riscv/vector-iterators.md  | 186 +-
 gcc/confi

回复：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector

[joshua]

H Juzhe,

This patch "RISC-V: Handle differences between XTheadvector and
Vector" is addressing some code generation issues for RVV1.0
instructions that xtheadvector does not have, not with intrinsics.

BTW, what about the following patch " RISC-V: Add support for
xtheadvector-specific intrinsics"?It adds support new xtheadvector
instructions. Is it OK to be merged?

Joshua






--
发件人：juzhe.zh...@rivai.ai 
发送时间：2023年12月29日(星期五) 09:58
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主　题：Re: [PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and 
Vector


I am confused by the series patches.


I thought this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641417.html 
is enough to support partial theadvector that can leverage directly RVV1.0 ?


Could clean up and resend the patches base on patch above (supposed it is 
merged already) ?


juzhe.zh...@rivai.ai

 
From: Jun Sha (Joshua)
Date: 2023-12-29 09:46
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
christoph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu
Subject: [PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and 
Vector

This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 
 
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r and vsext.vf2.
 
gcc/ChangeLog:
 
* config.gcc:  Add files for XTheadVector intrinsics.
* config/riscv/autovec.md: Guard XTheadVector.
* config/riscv/riscv-string.cc (expand_block_move):
Guard XTheadVector.
* config/riscv/riscv-v.cc (legitimize_move):
New expansion.
(get_prefer_tail_policy): Give specific value for tail.
(get_prefer_mask_policy): Give specific value for mask.
(vls_mode_valid_p): Avoid autovec.
* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
(build_one): New function.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
(DEF_THEAD_RVV_FUNCTION): Add new marcos.
(check_required_extensions):
(handle_pragma_vector):
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR):
(RVV_REQUIRE_XTHEADVECTOR):
Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR.
(struct function_group_info):
* config/riscv/riscv-vector-switch.def (ENTRY):
Disable fractional mode for the XTheadVector extension.
(TUPLE_ENTRY): Likewise.
* config/riscv/riscv-vsetvl.cc: Add functions for xtheadvector.
* config/riscv/riscv.cc (riscv_v_ext_vls_mode_p):
Guard XTheadVector.
(riscv_v_adjust_bytesize): Likewise.
(riscv_preferred_simd_mode): Likewsie.
(riscv_autovectorize_vector_modes): Likewise.
(riscv_vector_mode_supported_any_target_p): Likewise.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
* config/riscv/vector-iterators.md: Remove fractional LMUL.
* config/riscv/vector.md: Include thead-vector.md.
* config/riscv/riscv_th_vector.h: New file.
* config/riscv/thead-vector.md: New file.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector.
* gcc.target/riscv/rvv/base/abi-1.c: Exclude XTheadVector.
* lib/target-supports.exp: Add target for XTheadVector.
 
Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config.gcc    |   2 +-
 gcc/config/riscv/autovec.md   |   2 +-
 gcc/config/riscv/predicates.md    |   8 +-
 gcc/config/riscv/riscv-string.cc  |   3 +
 gcc/config/riscv/riscv-v.cc   |  13 +-
 .../riscv/riscv-vector-builtins-bases.cc  |   3 +
 .../riscv/riscv-vector-builtins-shapes.cc |  23 +++
 gcc/config/riscv/riscv-vector-switch.def  | 150 +++---
 gcc/config/riscv/riscv-vsetvl.cc  |  10 +
 gcc/config/riscv/riscv.cc |  20 +-
 gcc/config/riscv/riscv_th_vector.h    |  49 +
 gcc/config/riscv/thead-vector.md  | 142 +
 gcc/config/riscv/vector-iterators.md  | 186 +-
 gcc/confi

[PATCH v4 6/6] RISC-V: Add support for xtheadvector-specific intrinsics.

[Jun Sha (Joshua)]

re_width, none_m_preds, 
iu8_v_scalar_ptr_size_ops)
+DEF_RVV_FUNCTION (th_vssh, th_loadstore_width, none_m_preds, 
iu16_v_scalar_ptr_size_ops)
+DEF_RVV_FUNCTION (th_vssw, th_loadstore_width, none_m_preds, 
iu32_v_scalar_ptr_size_ops)
+DEF_RVV_FUNCTION (th_vlxb, th_indexed_loadstore_width, full_preds, 
i8_v_scalar_const_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vlxh, th_indexed_loadstore_width, full_preds, 
i16_v_scalar_const_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vlxw, th_indexed_loadstore_width, full_preds, 
i32_v_scalar_const_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vlxbu, th_indexed_loadstore_width, full_preds, 
u8_v_scalar_const_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vlxhu, th_indexed_loadstore_width, full_preds, 
u16_v_scalar_const_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vlxwu, th_indexed_loadstore_width, full_preds, 
u32_v_scalar_const_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsxb, th_indexed_loadstore_width, none_m_preds, 
iu8_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsxh, th_indexed_loadstore_width, none_m_preds, 
iu16_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsxw, th_indexed_loadstore_width, none_m_preds, 
iu32_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsuxb, th_indexed_loadstore_width, none_m_preds, 
iu8_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsuxh, th_indexed_loadstore_width, none_m_preds, 
iu16_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsuxw, th_indexed_loadstore_width, none_m_preds, 
iu32_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vext_x_v, th_extract, none_preds, iu_x_s_u_ops)
+#undef REQUIRED_EXTENSIONS
+
+#undef DEF_RVV_FUNCTION
diff --git a/gcc/config/riscv/thead-vector-builtins.cc 
b/gcc/config/riscv/thead-vector-builtins.cc
new file mode 100644
index 000..c0002f255ee
--- /dev/null
+++ b/gcc/config/riscv/thead-vector-builtins.cc
@@ -0,0 +1,200 @@
+/* function_base implementation for RISC-V XTheadVector Extension
+   for GNU compiler.
+   Copyright (C) 2022-2023 Free Software Foundation, Inc.
+   Contributed by Joshua (cooper.jos...@linux.alibaba.com), T-Head
+   Semiconductor Co., Ltd.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "tree.h"
+#include "rtl.h"
+#include "tm_p.h"
+#include "memmodel.h"
+#include "insn-codes.h"
+#include "optabs.h"
+#include "recog.h"
+#include "expr.h"
+#include "basic-block.h"
+#include "function.h"
+#include "fold-const.h"
+#include "gimple.h"
+#include "gimple-iterator.h"
+#include "gimplify.h"
+#include "explow.h"
+#include "emit-rtl.h"
+#include "tree-vector-builder.h"
+#include "rtx-vector-builder.h"
+#include "riscv-vector-builtins.h"
+#include "riscv-vector-builtins-shapes.h"
+#include "riscv-vector-builtins-bases.h"
+#include "thead-vector-builtins.h"
+
+using namespace riscv_vector;
+
+namespace riscv_vector {
+
+/* Implements
+ * th.vl(b/h/w)[u].v/th.vs(b/h/w)[u].v/th.vls(b/h/w)[u].v/th.vss(b/h/w)[u].v/
+ * th.vlx(b/h/w)[u].v/th.vs[u]x(b/h/w).v
+ * codegen.  */
+template
+class th_loadstore_width : public function_base
+{
+public:
+  bool apply_tail_policy_p () const override { return !STORE_P; }
+  bool apply_mask_policy_p () const override { return !STORE_P; }
+
+  unsigned int call_properties (const function_instance &) const override
+  {
+if (STORE_P)
+  return CP_WRITE_MEMORY;
+else
+  return CP_READ_MEMORY;
+  }
+
+  bool can_be_overloaded_p (enum predication_type_index pred) const override
+  {
+if (STORE_P || LST_TYPE == LST_INDEXED)
+  return true;
+return pred != PRED_TYPE_none;
+  }
+
+  rtx expand (function_expander ) const override
+  {
+gcc_assert (TARGET_XTHEADVECTOR);
+if (LST_TYPE == LST_INDEXED)
+  {
+   if (STORE_P)
+ return e.use_exact_insn (
+   code_for_pred_indexed_store_width (UNSPEC, UNSPEC,
+  e.vector_mode ()));
+   else
+ return e.use_exact_insn (
+   code_for_pred_indexed_load_width (UNSPEC, e.vector_mode ()));
+  }
+else if (LST_TYPE == LST_STRIDED)
+  {
+   if (STORE_P)
+ return e.use_contiguous_

[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector

[Jun Sha (Joshua)]

This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 

For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r and vsext.vf2.

gcc/ChangeLog:

* config.gcc:  Add files for XTheadVector intrinsics.
* config/riscv/autovec.md: Guard XTheadVector.
* config/riscv/riscv-string.cc (expand_block_move):
Guard XTheadVector.
* config/riscv/riscv-v.cc (legitimize_move):
New expansion.
(get_prefer_tail_policy): Give specific value for tail.
(get_prefer_mask_policy): Give specific value for mask.
(vls_mode_valid_p): Avoid autovec.
* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
(build_one): New function.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
(DEF_THEAD_RVV_FUNCTION): Add new marcos.
(check_required_extensions):
(handle_pragma_vector):
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR):
(RVV_REQUIRE_XTHEADVECTOR):
Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR.
(struct function_group_info):
* config/riscv/riscv-vector-switch.def (ENTRY):
Disable fractional mode for the XTheadVector extension.
(TUPLE_ENTRY): Likewise.
* config/riscv/riscv-vsetvl.cc: Add functions for xtheadvector.
* config/riscv/riscv.cc (riscv_v_ext_vls_mode_p):
Guard XTheadVector.
(riscv_v_adjust_bytesize): Likewise.
(riscv_preferred_simd_mode): Likewsie.
(riscv_autovectorize_vector_modes): Likewise.
(riscv_vector_mode_supported_any_target_p): Likewise.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
* config/riscv/vector-iterators.md: Remove fractional LMUL.
* config/riscv/vector.md: Include thead-vector.md.
* config/riscv/riscv_th_vector.h: New file.
* config/riscv/thead-vector.md: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector.
* gcc.target/riscv/rvv/base/abi-1.c: Exclude XTheadVector.
* lib/target-supports.exp: Add target for XTheadVector.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/autovec.md   |   2 +-
 gcc/config/riscv/predicates.md|   8 +-
 gcc/config/riscv/riscv-string.cc  |   3 +
 gcc/config/riscv/riscv-v.cc   |  13 +-
 .../riscv/riscv-vector-builtins-bases.cc  |   3 +
 .../riscv/riscv-vector-builtins-shapes.cc |  23 +++
 gcc/config/riscv/riscv-vector-switch.def  | 150 +++---
 gcc/config/riscv/riscv-vsetvl.cc  |  10 +
 gcc/config/riscv/riscv.cc |  20 +-
 gcc/config/riscv/riscv_th_vector.h|  49 +
 gcc/config/riscv/thead-vector.md  | 142 +
 gcc/config/riscv/vector-iterators.md  | 186 +-
 gcc/config/riscv/vector.md|  36 +++-
 .../gcc.target/riscv/rvv/base/abi-1.c |   2 +-
 .../gcc.target/riscv/rvv/base/pragma-1.c  |   2 +-
 gcc/testsuite/lib/target-supports.exp |  12 ++
 17 files changed, 474 insertions(+), 189 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_th_vector.h
 create mode 100644 gcc/config/riscv/thead-vector.md

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f0676c830e8..1445d98c147 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,7 +549,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_th_vector.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 8b8a92f10a1..1fac56c7095 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2579,7 +2579,7 @@
   [(match_operand  0 "register_operand")
(match_operand  1 "memory_operand")
(match_operand:ANYI 2 "const_int_operand")]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   {
 

回复：[PATCH v3 1/6] RISC-V: Refactor riscv-vector-builtins-bases.cc

[joshua]

Hi Jeff,

Perhaps fold_fault_load cannot be moved to riscv-protos.h since
gimple_folder is declared in riscv-vector-builtins.h. It's not reasonable
to include riscv-vector-builtins.h in riscv-protos.h. 

In fact, fold_fault_load is defined specially for some builtin functions, and
it would be better to just prototype in riscv-vector-builtins-bases.h.

Joshua






--
发件人：Jeff Law 
发送时间：2023年12月21日(星期四) 02:14
收件人："Jun Sha (Joshua)"; 
"gcc-patches"
抄　送："jim.wilson.gcc"; palmer; 
andrew; "philipp.tomsich"; 
"christoph.muellner"; 
"juzhe.zhong"; Jin Ma; Xianmiao 
Qu
主　题：Re: [PATCH v3 1/6] RISC-V: Refactor riscv-vector-builtins-bases.cc




On 12/20/23 05:25, Jun Sha (Joshua) wrote:
> This patch moves the definition of the enums lst_type and
> frm_op_type into riscv-vector-builtins-bases.h and removes
> the static visibility of fold_fault_load(), so these
> can be used in other compile units.
> 
> gcc/ChangeLog:
> 
>  * config/riscv/riscv-vector-builtins-bases.cc (enum lst_type):
>  (enum frm_op_type): move to riscv-vector-builtins-bases.h
>  * config/riscv/riscv-vector-builtins-bases.h
>  (GCC_RISCV_VECTOR_BUILTINS_BASES_H): Add header files.
>  (enum lst_type): move from
>  (enum frm_op_type): riscv-vector-builtins-bases.cc
>  (fold_fault_load): riscv-vector-builtins-bases.cc
I'm largely hoping to leave the heavy review lifting here to Juzhe who 
knows GCC's RV vector bits as well as anyone.

Just one small issue.  Would it be better to prototype fold_fault_load 
elsewhere and avoid the gimple.h inclusion in 
riscv-vector-builtins-bases.h?  Perhaps riscv-protos.h?

You might consider prefixing the function name with riscv_.  It's not 
strictly necessary, but it appears to be relatively common in risc-v port.

Thanks,
Jeff

回复：[PATCH v3 2/6] RISC-V: Split csr_operand in predicates.md for vector patterns.

[joshua]

Hi Jeff,

Yes, I will change soemthing in vector_csr_operand in the following
patches.

Constraints will be added that the AVL cannot be encoded as an
immediate for xtheadvecotr vsetvl.

Joshua







--
发件人：Jeff Law 
发送时间：2023年12月21日(星期四) 02:16
收件人："Jun Sha (Joshua)"; 
"gcc-patches"
抄　送："jim.wilson.gcc"; palmer; 
andrew; "philipp.tomsich"; 
"christoph.muellner"; 
"juzhe.zhong"; Jin Ma; Xianmiao 
Qu
主　题：Re: [PATCH v3 2/6] RISC-V: Split csr_operand in predicates.md for vector 
patterns.




On 12/20/23 05:27, Jun Sha (Joshua) wrote:
> This patch splits the definition of csr_operand in predicates.md.
> The newly defined vector_csr_operand has the same functionality
> as csr_operand but can only be used in vector patterns, so that
> changes for vector will not affect scalar patterns in files
> like riscv.md.
> 
> gcc/ChangeLog:
> 
>  * config/riscv/predicates.md (vector_csr_operand):
>  Define vector_csr_opeand for vector.
>  * config/riscv/vector.md:
>  Use newly defined csr_operand for vector.
So do you envision changing something in vector_csr_operand?  If not, 
then this doesn't make much sense.

Jeff

回复：[PATCH v3 1/6] RISC-V: Refactor riscv-vector-builtins-bases.cc

[joshua]

Hi Jeff,

Perhaps fold_fault_load cannot be moved to riscv-protos.h since
gimple_folder is declared in riscv-vector-builtins.h. It's not reasonable
to include riscv-vector-builtins.h in riscv-protos.h. 

In fact, fold_fault_load is defined specially for some builtin functions, and
it would be better to just prototype in riscv-vector-builtins-bases.h.

Joshua







--
发件人：Jeff Law 
发送时间：2023年12月21日(星期四) 02:14
收件人："Jun Sha (Joshua)"; 
"gcc-patches"
抄　送："jim.wilson.gcc"; palmer; 
andrew; "philipp.tomsich"; 
"christoph.muellner"; 
"juzhe.zhong"; Jin Ma; Xianmiao 
Qu
主　题：Re: [PATCH v3 1/6] RISC-V: Refactor riscv-vector-builtins-bases.cc




On 12/20/23 05:25, Jun Sha (Joshua) wrote:
> This patch moves the definition of the enums lst_type and
> frm_op_type into riscv-vector-builtins-bases.h and removes
> the static visibility of fold_fault_load(), so these
> can be used in other compile units.
> 
> gcc/ChangeLog:
> 
>  * config/riscv/riscv-vector-builtins-bases.cc (enum lst_type):
>  (enum frm_op_type): move to riscv-vector-builtins-bases.h
>  * config/riscv/riscv-vector-builtins-bases.h
>  (GCC_RISCV_VECTOR_BUILTINS_BASES_H): Add header files.
>  (enum lst_type): move from
>  (enum frm_op_type): riscv-vector-builtins-bases.cc
>  (fold_fault_load): riscv-vector-builtins-bases.cc
I'm largely hoping to leave the heavy review lifting here to Juzhe who 
knows GCC's RV vector bits as well as anyone.

Just one small issue.  Would it be better to prototype fold_fault_load 
elsewhere and avoid the gimple.h inclusion in 
riscv-vector-builtins-bases.h?  Perhaps riscv-protos.h?

You might consider prefixing the function name with riscv_.  It's not 
strictly necessary, but it appears to be relatively common in risc-v port.

Thanks,
Jeff

[PATCH v4 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

[Jun Sha (Joshua)]

This patch adds th. prefix to all XTheadVector instructions by
implementing new assembly output functions. In this version, we 
follow Kito's suggestions and only check the prefix is 'v', so that 
no extra attribute is needed.

gcc/ChangeLog:

* config/riscv/riscv-protos.h (riscv_asm_output_opcode): 
New function to add assembler insn code prefix/suffix.
* config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
* config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config/riscv/riscv-protos.h   |  1 +
 gcc/config/riscv/riscv.cc | 19 +++
 gcc/config/riscv/riscv.h  |  4 
 .../riscv/rvv/xtheadvector/prefix.c   | 12 
 4 files changed, 36 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 31049ef7523..5ea54b45703 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -102,6 +102,7 @@ struct riscv_address_info {
 };
 
 /* Routines implemented in riscv.cc.  */
+extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
 extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
 extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
 extern int riscv_float_const_rtx_index_for_fli (rtx);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0d1cbc5cb5f..30e6ced5f3f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5636,6 +5636,25 @@ riscv_get_v_regno_alignment (machine_mode mode)
   return lmul;
 }
 
+/* Define ASM_OUTPUT_OPCODE to do anything special before
+   emitting an opcode.  */
+const char *
+riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
+{
+  if (!TARGET_XTHEADVECTOR)
+return p;
+
+  if (current_output_insn == NULL_RTX)
+return p;
+
+  /* We need to add th. prefix to all the xtheadvector
+ insturctions here.*/
+  if (p[0] == 'v')
+fputs ("th.", asm_out_file);
+
+  return p;
+}
+
 /* Implement TARGET_PRINT_OPERAND.  The RISCV-specific operand codes are:
 
'h' Print the high-part relocation associated with OP, after stripping
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 6df9ec73c5e..c33361a254d 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -826,6 +826,10 @@ extern enum riscv_cc get_riscv_cc (const rtx use);
   asm_fprintf ((FILE), "%U%s", (NAME));\
   } while (0)
 
+#undef ASM_OUTPUT_OPCODE
+#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
+  (PTR) = riscv_asm_output_opcode(STREAM, PTR)
+
 #define JUMP_TABLES_IN_TEXT_SECTION 0
 #define CASE_VECTOR_MODE SImode
 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
new file mode 100644
index 000..48867f4ddfb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadvector -mabi=ilp32 -O0" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+prefix (vint32m1_t vx, vint32m1_t vy, size_t vl)
+{
+  return __riscv_vadd_vv_i32m1 (vx, vy, vl);
+}
+
+/* { dg-final { scan-assembler {\mth\.v\M} } } */
-- 
2.17.1

回复：[PATCH v4 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

[joshua]

+ if (current_output_insn == NULL_RTX)
+ return p;
This is for inline assembly case.
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2023年12月25日(星期一) 14:37
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
"cooper.joshua"; 
jinma; "cooper.qu"
主　题：Re: [PATCH v4 4/6] RISC-V: Adds the prefix "th." for the instructions of 
XTheadVector.
+ if (current_output_insn == NULL_RTX)
+ return p;
What is this used for ?
How about:
+ /* We need to add th. prefix to all the xtheadvector
+ insturctions here.*/
+ if (TARGET_XTHEADVECTOR && p[0] == 'v')
+ fputs ("th.", asm_out_file);
\ No newline at end of file
New line should be added into prefix.c
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua) <mailto:cooper.jos...@linux.alibaba.com >
Date: 2023-12-25 14:25
To: gcc-patches <mailto:gcc-patches@gcc.gnu.org >
CC: jim.wilson.gcc <mailto:jim.wilson@gmail.com >; palmer 
<mailto:pal...@dabbelt.com >; andrew <mailto:and...@sifive.com >; 
philipp.tomsich <mailto:philipp.toms...@vrull.eu >; jeffreyalaw 
<mailto:jeffreya...@gmail.com >; christoph.muellner 
<mailto:christoph.muell...@vrull.eu >; juzhe.zhong <mailto:juzhe.zh...@rivai.ai 
>; Jun Sha (Joshua) <mailto:cooper.jos...@linux.alibaba.com >; Jin Ma 
<mailto:ji...@linux.alibaba.com >; Xianmiao Qu 
<mailto:cooper...@linux.alibaba.com >
Subject: [PATCH v4 4/6] RISC-V: Adds the prefix "th." for the instructions of 
XTheadVector.
This patch adds th. prefix to all XTheadVector instructions by
implementing new assembly output functions. In this version, we 
follow Kito's suggestions and only check the prefix is 'v', so that 
no extra attribute is needed.
gcc/ChangeLog:
 * config/riscv/riscv-protos.h (riscv_asm_output_opcode): 
 New function to add assembler insn code prefix/suffix.
 * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
 * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config/riscv/riscv-protos.h | 1 +
 gcc/config/riscv/riscv.cc | 19 +++
 gcc/config/riscv/riscv.h | 4 
 .../riscv/rvv/xtheadvector/prefix.c | 12 
 4 files changed, 36 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 31049ef7523..5ea54b45703 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -102,6 +102,7 @@ struct riscv_address_info {
 };
 /* Routines implemented in riscv.cc. */
+extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
 extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
 extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
 extern int riscv_float_const_rtx_index_for_fli (rtx);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0d1cbc5cb5f..30e6ced5f3f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5636,6 +5636,25 @@ riscv_get_v_regno_alignment (machine_mode mode)
 return lmul;
 }
+/* Define ASM_OUTPUT_OPCODE to do anything special before
+ emitting an opcode. */
+const char *
+riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
+{
+ if (!TARGET_XTHEADVECTOR)
+ return p;
+
+ if (current_output_insn == NULL_RTX)
+ return p;
+
+ /* We need to add th. prefix to all the xtheadvector
+ insturctions here.*/
+ if (p[0] == 'v')
+ fputs ("th.", asm_out_file);
+
+ return p;
+}
+
 /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are:
 'h' Print the high-part relocation associated with OP, after stripping
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 6df9ec73c5e..c33361a254d 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -826,6 +826,10 @@ extern enum riscv_cc get_riscv_cc (const rtx use);
 asm_fprintf ((FILE), "%U%s", (NAME)); \
 } while (0)
+#undef ASM_OUTPUT_OPCODE
+#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
+ (PTR) = riscv_asm_output_opcode(STREAM, PTR)
+
 #define JUMP_TABLES_IN_TEXT_SECTION 0
 #define CASE_VECTOR_MODE SImode
 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
new file mode 100644
index 000..48867f4ddfb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadvector -mabi=ilp32 -O0" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+prefix (vint32m1_t vx, vint32m1_t vy, size_t vl)
+{
+ return __riscv_vadd_vv_i32m1 (vx, vy, vl);
+}
+
+/* { dg-final { scan-assembler {\mth\.v\M} } } */
\ No newline at end of file
-- 
2.17.1

[PATCH v4 6/6] RISC-V: Add support for xtheadvector-specific intrinsics.

[Jun Sha (Joshua)]

u32_v_scalar_const_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsxb, th_indexed_loadstore_width, none_m_preds, 
iu8_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsxh, th_indexed_loadstore_width, none_m_preds, 
iu16_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsxw, th_indexed_loadstore_width, none_m_preds, 
iu32_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsuxb, th_indexed_loadstore_width, none_m_preds, 
iu8_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsuxh, th_indexed_loadstore_width, none_m_preds, 
iu16_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsuxw, th_indexed_loadstore_width, none_m_preds, 
iu32_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vext_x_v, th_extract, none_preds, iu_x_s_u_ops)
+#undef REQUIRED_EXTENSIONS
+
+#undef DEF_RVV_FUNCTION
diff --git a/gcc/config/riscv/thead-vector-builtins.cc 
b/gcc/config/riscv/thead-vector-builtins.cc
new file mode 100644
index 000..c0002f255ee
--- /dev/null
+++ b/gcc/config/riscv/thead-vector-builtins.cc
@@ -0,0 +1,200 @@
+/* function_base implementation for RISC-V XTheadVector Extension
+   for GNU compiler.
+   Copyright (C) 2022-2023 Free Software Foundation, Inc.
+   Contributed by Joshua (cooper.jos...@linux.alibaba.com), T-Head
+   Semiconductor Co., Ltd.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "tree.h"
+#include "rtl.h"
+#include "tm_p.h"
+#include "memmodel.h"
+#include "insn-codes.h"
+#include "optabs.h"
+#include "recog.h"
+#include "expr.h"
+#include "basic-block.h"
+#include "function.h"
+#include "fold-const.h"
+#include "gimple.h"
+#include "gimple-iterator.h"
+#include "gimplify.h"
+#include "explow.h"
+#include "emit-rtl.h"
+#include "tree-vector-builder.h"
+#include "rtx-vector-builder.h"
+#include "riscv-vector-builtins.h"
+#include "riscv-vector-builtins-shapes.h"
+#include "riscv-vector-builtins-bases.h"
+#include "thead-vector-builtins.h"
+
+using namespace riscv_vector;
+
+namespace riscv_vector {
+
+/* Implements
+ * th.vl(b/h/w)[u].v/th.vs(b/h/w)[u].v/th.vls(b/h/w)[u].v/th.vss(b/h/w)[u].v/
+ * th.vlx(b/h/w)[u].v/th.vs[u]x(b/h/w).v
+ * codegen.  */
+template
+class th_loadstore_width : public function_base
+{
+public:
+  bool apply_tail_policy_p () const override { return !STORE_P; }
+  bool apply_mask_policy_p () const override { return !STORE_P; }
+
+  unsigned int call_properties (const function_instance &) const override
+  {
+if (STORE_P)
+  return CP_WRITE_MEMORY;
+else
+  return CP_READ_MEMORY;
+  }
+
+  bool can_be_overloaded_p (enum predication_type_index pred) const override
+  {
+if (STORE_P || LST_TYPE == LST_INDEXED)
+  return true;
+return pred != PRED_TYPE_none;
+  }
+
+  rtx expand (function_expander ) const override
+  {
+gcc_assert (TARGET_XTHEADVECTOR);
+if (LST_TYPE == LST_INDEXED)
+  {
+   if (STORE_P)
+ return e.use_exact_insn (
+   code_for_pred_indexed_store_width (UNSPEC, UNSPEC,
+  e.vector_mode ()));
+   else
+ return e.use_exact_insn (
+   code_for_pred_indexed_load_width (UNSPEC, e.vector_mode ()));
+  }
+else if (LST_TYPE == LST_STRIDED)
+  {
+   if (STORE_P)
+ return e.use_contiguous_store_insn (
+   code_for_pred_strided_store_width (UNSPEC, e.vector_mode ()));
+   else
+ return e.use_contiguous_load_insn (
+   code_for_pred_strided_load_width (UNSPEC, e.vector_mode ()));
+  }
+else
+  {
+   if (STORE_P)
+ return e.use_contiguous_store_insn (
+   code_for_pred_store_width (UNSPEC, e.vector_mode ()));
+   else
+ return e.use_contiguous_load_insn (
+   code_for_pred_mov_width (UNSPEC, e.vector_mode ()));
+  }
+  }
+};
+
+/* Implements vext.x.v.  */
+class th_extract : public function_base
+{
+public:
+  bool apply_vl_p () const override { return false; }
+  bool apply_tail_policy_p () const override { return false; }
+  bool apply_mask_policy_p () const override { return false; }
+  bool use_mask_predication_p () con

[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector

[Jun Sha (Joshua)]

This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share same patterns as RVV1.0 instructions, we will
use ASM targethook to rewrite the whole string of the instructions in
the following patches. 

For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in vector.md in order
not to generate instructions that xtheadvector does not support,
like vmv1r and vsext.vf2.

gcc/ChangeLog:

* config.gcc:  Add files for XTheadVector intrinsics.
* config/riscv/autovec.md: Guard XTheadVector.
* config/riscv/riscv-string.cc (expand_block_move):
Guard XTheadVector.
* config/riscv/riscv-v.cc (legitimize_move):
New expansion.
(get_prefer_tail_policy): Give specific value for tail.
(get_prefer_mask_policy): Give specific value for mask.
(vls_mode_valid_p): Avoid autovec.
* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
(build_one): New function.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
(DEF_THEAD_RVV_FUNCTION): Add new marcos.
(check_required_extensions):
(handle_pragma_vector):
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_VECTOR):
(RVV_REQUIRE_XTHEADVECTOR):
Add RVV_REQUIRE_VECTOR and RVV_REQUIRE_XTHEADVECTOR.
(struct function_group_info):
* config/riscv/riscv-vector-switch.def (ENTRY):
Disable fractional mode for the XTheadVector extension.
(TUPLE_ENTRY): Likewise.
* config/riscv/riscv-vsetvl.cc: Add functions for xtheadvector.
* config/riscv/riscv.cc (riscv_v_ext_vls_mode_p):
Guard XTheadVector.
(riscv_v_adjust_bytesize): Likewise.
(riscv_preferred_simd_mode): Likewsie.
(riscv_autovectorize_vector_modes): Likewise.
(riscv_vector_mode_supported_any_target_p): Likewise.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
* config/riscv/vector-iterators.md: Remove fractional LMUL.
* config/riscv/vector.md: Include thead-vector.md.
* config/riscv/riscv_th_vector.h: New file.
* config/riscv/thead-vector.md: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector.
* gcc.target/riscv/rvv/base/abi-1.c: Exclude XTheadVector.
* lib/target-supports.exp: Add target for XTheadVector.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/autovec.md   |   2 +-
 gcc/config/riscv/predicates.md|   8 +-
 gcc/config/riscv/riscv-string.cc  |   3 +
 gcc/config/riscv/riscv-v.cc   |  13 +-
 .../riscv/riscv-vector-builtins-shapes.cc |  23 +++
 gcc/config/riscv/riscv-vector-switch.def  | 150 +++---
 gcc/config/riscv/riscv-vsetvl.cc  |  10 +
 gcc/config/riscv/riscv.cc |  20 +-
 gcc/config/riscv/riscv_th_vector.h|  49 +
 gcc/config/riscv/thead-vector.md  | 120 +++
 gcc/config/riscv/vector-iterators.md  | 186 +-
 gcc/config/riscv/vector.md|  36 +++-
 .../gcc.target/riscv/rvv/base/abi-1.c |   2 +-
 .../gcc.target/riscv/rvv/base/pragma-1.c  |   2 +-
 gcc/testsuite/lib/target-supports.exp |  12 ++
 16 files changed, 449 insertions(+), 189 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_th_vector.h
 create mode 100644 gcc/config/riscv/thead-vector.md

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f0676c830e8..1445d98c147 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,7 +549,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_th_vector.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 8b8a92f10a1..1fac56c7095 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2579,7 +2579,7 @@
   [(match_operand  0 "register_operand")
(match_operand  1 "memory_operand")
(match_operand:ANYI 2 "const_int_operand")]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   {
 riscv_vector::expand_rawmemchr(mode, operands[0], operands[1],
 

[PATCH v4 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

[Jun Sha (Joshua)]

This patch adds th. prefix to all XTheadVector instructions by
implementing new assembly output functions. In this version, we 
follow Kito's suggestions and only check the prefix is 'v', so that 
no extra attribute is needed.

gcc/ChangeLog:

* config/riscv/riscv-protos.h (riscv_asm_output_opcode): 
New function to add assembler insn code prefix/suffix.
* config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
* config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config/riscv/riscv-protos.h   |  1 +
 gcc/config/riscv/riscv.cc | 19 +++
 gcc/config/riscv/riscv.h  |  4 
 .../riscv/rvv/xtheadvector/prefix.c   | 12 
 4 files changed, 36 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 31049ef7523..5ea54b45703 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -102,6 +102,7 @@ struct riscv_address_info {
 };
 
 /* Routines implemented in riscv.cc.  */
+extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p);
 extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
 extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
 extern int riscv_float_const_rtx_index_for_fli (rtx);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0d1cbc5cb5f..30e6ced5f3f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5636,6 +5636,25 @@ riscv_get_v_regno_alignment (machine_mode mode)
   return lmul;
 }
 
+/* Define ASM_OUTPUT_OPCODE to do anything special before
+   emitting an opcode.  */
+const char *
+riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
+{
+  if (!TARGET_XTHEADVECTOR)
+return p;
+
+  if (current_output_insn == NULL_RTX)
+return p;
+
+  /* We need to add th. prefix to all the xtheadvector
+ insturctions here.*/
+  if (p[0] == 'v')
+fputs ("th.", asm_out_file);
+
+  return p;
+}
+
 /* Implement TARGET_PRINT_OPERAND.  The RISCV-specific operand codes are:
 
'h' Print the high-part relocation associated with OP, after stripping
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 6df9ec73c5e..c33361a254d 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -826,6 +826,10 @@ extern enum riscv_cc get_riscv_cc (const rtx use);
   asm_fprintf ((FILE), "%U%s", (NAME));\
   } while (0)
 
+#undef ASM_OUTPUT_OPCODE
+#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
+  (PTR) = riscv_asm_output_opcode(STREAM, PTR)
+
 #define JUMP_TABLES_IN_TEXT_SECTION 0
 #define CASE_VECTOR_MODE SImode
 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
new file mode 100644
index 000..48867f4ddfb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadvector -mabi=ilp32 -O0" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+prefix (vint32m1_t vx, vint32m1_t vy, size_t vl)
+{
+  return __riscv_vadd_vv_i32m1 (vx, vy, vl);
+}
+
+/* { dg-final { scan-assembler {\mth\.v\M} } } */
\ No newline at end of file
-- 
2.17.1

回复：回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension

[joshua]

Hi Juzhe,
Sorry but I'm not quite familiar with the group_overlap framework. Could you 
take this pattern as an example to show how to disable an alternative in some 
target?
Joshua
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2023年12月22日(星期五) 18:32
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: 回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
Yeah.
(define_insn "@pred_msbc"
 [(set (match_operand: 0 "register_operand" "=vr, vr, ")
 (unspec:
 [(minus:VI
 (match_operand:VI 1 "register_operand" " 0, vr, vr")
 (match_operand:VI 2 "register_operand" " vr, 0, vr"))
 (match_operand: 3 "register_operand" " vm, vm, vm")
 (unspec:
 [(match_operand 4 "vector_length_operand" " rK, rK, rK")
 (match_operand 5 "const_int_operand" " i, i, i")
 (reg:SI VL_REGNUM)
 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
"TARGET_VECTOR"
"vmsbc.vvm\t%0,%1,%2,%3"
 [(set_attr "type" "vicalu")
 (set_attr "mode" "")
 (set_attr "vl_op_idx" "4")
 (set (attr "avl_type_idx") (const_int 5))])
You should use an attribute to disable alternative 0 and alternative 1 
constraint.
juzhe.zh...@rivai.ai
发件人： joshua <mailto:cooper.jos...@linux.alibaba.com >
发送时间： 2023-12-22 18:29
收件人： juzhe.zh...@rivai.ai <mailto:juzhe.zh...@rivai.ai >; gcc-patches 
<mailto:gcc-patches@gcc.gnu.org >
抄送： Jim Wilson <mailto:jim.wilson@gmail.com >; palmer 
<mailto:pal...@dabbelt.com >; andrew <mailto:and...@sifive.com >; 
philipp.tomsich <mailto:philipp.toms...@vrull.eu >; jeffreyalaw 
<mailto:jeffreya...@gmail.com >; christoph.muellner 
<mailto:christoph.muell...@vrull.eu >; jinma <mailto:ji...@linux.alibaba.com >; 
cooper.qu <mailto:cooper...@linux.alibaba.com >
主题： 回复：回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi Juzhe,
What xtheadvector needs to handle is just that destination vector register 
cannot overlap source vector register group for instructions like vmadc/vmsbc. 
That is not what group_overlap means. We nned to add "&" to the registers in 
the corresponding xtheadvector patterns while rvv 1.0 doesn't have this 
constraint.
(define_insn "@pred_th_msbc"
 [(set (match_operand: 0 "register_operand" "=")
 (unspec:
 [(minus:VI
 (match_operand:VI 1 "register_operand" " vr")
 (match_operand:VI 2 "register_operand" " vr"))
 (match_operand: 3 "register_operand" " vm")
 (unspec:
 [(match_operand 4 "vector_length_operand" " rK")
 (match_operand 5 "const_int_operand" " i")
 (reg:SI VL_REGNUM)
 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
 "TARGET_XTHEADVECTOR"
 "vmsbc.vvm\t%0,%1,%2,%3"
 [(set_attr "type" "vicalu")
 (set_attr "mode" "")
 (set_attr "vl_op_idx" "4")
 (set (attr "avl_type_idx") (const_int 5))])
Joshua
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2023年12月22日(星期五) 16:07
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: 回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
You mean theadvector doesn't want the current RVV1.0 register overlap magic as 
follows ?

 * 
The destination EEW is smaller than the source EEW and the overlap is in the 
lowest-numbered part of the source register group (e.g., when LMUL=1, vnsrl.wi 
v0, v0, 3 is legal, but a destination of v1 is not).

 * 
The destination EEW is greater than the source EEW, the source EMUL is at least 
1, and the overlap is in the highest-numbered part of the destination register 
group (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or 
v4 is not).
If yes, I suggest disable the overlap constraint using attribute, More details 
you can learn from 
(set_attr "group_overlap"
juzhe.zh...@rivai.ai
发件人： joshua <mailto:cooper.jos...@linux.alibaba.com >
发送时间： 2023-12-22 11:33
收件人： 钟居哲 <mailto:juzhe.zh...@rivai.ai >; gcc-patches 
<mailto:gcc-patches@gcc.gnu.org >
抄送： jim.wilson.gcc <mailto:jim.wilson@gmail.com >; palmer 
<mailto:pal...@dabbelt.com >; andrew <mailto:and...@sifive.com >; 
philipp.tomsich <mailto:philipp.toms...@vrull.eu >; Jeff Law 
<mailto:jeffreya...@gmail.com >; Christoph Müllner 
<mailto:christoph.muell...@vrull.eu >; jinma <mailto

回复：回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension

[joshua]

Hi Juzhe,
What xtheadvector needs to handle is just that destination vector register 
cannot overlap source vector register group for instructions like vmadc/vmsbc. 
That is not what group_overlap means. We nned to add "&" to the registers in 
the corresponding xtheadvector patterns while rvv 1.0 doesn't have this 
constraint.
(define_insn "@pred_th_msbc"
 [(set (match_operand: 0 "register_operand" "=")
 (unspec:
 [(minus:VI
 (match_operand:VI 1 "register_operand" " vr")
 (match_operand:VI 2 "register_operand" " vr"))
 (match_operand: 3 "register_operand" " vm")
 (unspec:
 [(match_operand 4 "vector_length_operand" " rK")
 (match_operand 5 "const_int_operand" " i")
 (reg:SI VL_REGNUM)
 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
 "TARGET_XTHEADVECTOR"
 "vmsbc.vvm\t%0,%1,%2,%3"
 [(set_attr "type" "vicalu")
 (set_attr "mode" "")
 (set_attr "vl_op_idx" "4")
 (set (attr "avl_type_idx") (const_int 5))])
Joshua
--
发件人：juzhe.zh...@rivai.ai 
发送时间：2023年12月22日(星期五) 16:07
收件人："cooper.joshua"; 
"gcc-patches"
抄　送：Jim Wilson; palmer; 
andrew; "philipp.tomsich"; 
jeffreyalaw; 
"christoph.muellner"; 
jinma; "cooper.qu"
主　题：Re: 回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
You mean theadvector doesn't want the current RVV1.0 register overlap magic as 
follows ?

 * 
The destination EEW is smaller than the source EEW and the overlap is in the 
lowest-numbered part of the source register group (e.g., when LMUL=1, vnsrl.wi 
v0, v0, 3 is legal, but a destination of v1 is not).

 * 
The destination EEW is greater than the source EEW, the source EMUL is at least 
1, and the overlap is in the highest-numbered part of the destination register 
group (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or 
v4 is not).
If yes, I suggest disable the overlap constraint using attribute, More details 
you can learn from 
(set_attr "group_overlap"
juzhe.zh...@rivai.ai
发件人： joshua <mailto:cooper.jos...@linux.alibaba.com >
发送时间： 2023-12-22 11:33
收件人： 钟居哲 <mailto:juzhe.zh...@rivai.ai >; gcc-patches 
<mailto:gcc-patches@gcc.gnu.org >
抄送： jim.wilson.gcc <mailto:jim.wilson@gmail.com >; palmer 
<mailto:pal...@dabbelt.com >; andrew <mailto:and...@sifive.com >; 
philipp.tomsich <mailto:philipp.toms...@vrull.eu >; Jeff Law 
<mailto:jeffreya...@gmail.com >; Christoph Müllner 
<mailto:christoph.muell...@vrull.eu >; jinma <mailto:ji...@linux.alibaba.com >; 
Cooper Qu <mailto:cooper...@linux.alibaba.com >
主题： 回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi Juzhe,
Thank you for your comprehensive comments.
Classifying theadvector intrinsics into 3 kinds is really important to make our 
patchset more organized. 
For 1) and 3), I will split out the patches soon and hope they will be merged 
quickly.
For 2), according to the differences between vector and xtheadvector, it can be 
classfied into 3 kinds.
First is renamed load/store, renamed narrowing integer right shift, renamed 
narrowing fixed-point clip, and etc. I think we can use ASM targethook to 
rewrite the whole string of the instructions, although it will still be a heavy 
work.
Second is no pseudo instruction like vneg/vfneg. We will add these pseudo 
instructions in binutils to make xtheadvector more compatible with vector.
Third is that destination vector register cannot overlap source vector register 
group for vmadc/vmsbc/widen arithmetic/narrow arithmetic. Currently I cannot 
come up with any better way than pattern copy. Do you have any suggestions?
Joshua
--
发件人：钟居哲 
发送时间：2023年12月21日(星期四) 07:04
收件人："cooper.joshua"; 
"gcc-patches"
抄　送："jim.wilson.gcc"; palmer; 
andrew; "philipp.tomsich"; Jeff 
Law; "Christoph Müllner"; 
"cooper.joshua"; 
jinma; Cooper Qu
主　题：Re: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi, Joshua.
Thanks for working hard on clean up codes and support tons of work on 
theadvector.
After fully review this patch, I understand you have 3 kinds of theadvector 
intrinsics from the codebase of current RVV1.0 GCC.
1). instructions that can leverage all current codes of RVV1.0 intrinsic with 
simply adding "th." prefix directly.
2). instructions that leverage current MD patterns but with some tweak and 
patterns copy since they are not simply added "th.".
3). new instructions that current RVV1.0 doesn't have like vlb instructions.
Overal, 1) and 3) look reasonable to me. But 2) need me some time to figure out 
the better way to do that (Current t

回复：[PATCH v3 0/6] RISC-V: Support XTheadVector extension

[joshua]

Hi Juzhe,
Thank you for your comprehensive comments.
Classifying theadvector intrinsics into 3 kinds is really important to make our 
patchset more organized. 
For 1) and 3), I will split out the patches soon and hope they will be merged 
quickly.
For 2), according to the differences between vector and xtheadvector, it can be 
classfied into 3 kinds.
First is renamed load/store, renamed narrowing integer right shift, renamed 
narrowing fixed-point clip, and etc. I think we can use ASM targethook to 
rewrite the whole string of the instructions, although it will still be a heavy 
work.
Second is no pseudo instruction like vneg/vfneg. We will add these pseudo 
instructions in binutils to make xtheadvector more compatible with vector.
Third is that destination vector register cannot overlap source vector register 
group for vmadc/vmsbc/widen arithmetic/narrow arithmetic. Currently I cannot 
come up with any better way than pattern copy. Do you have any suggestions?
Joshua
--
发件人：钟居哲 
发送时间：2023年12月21日(星期四) 07:04
收件人："cooper.joshua"; 
"gcc-patches"
抄　送："jim.wilson.gcc"; palmer; 
andrew; "philipp.tomsich"; Jeff 
Law; "Christoph Müllner"; 
"cooper.joshua"; 
jinma; Cooper Qu
主　题：Re: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
Hi, Joshua.
Thanks for working hard on clean up codes and support tons of work on 
theadvector.
After fully review this patch, I understand you have 3 kinds of theadvector 
intrinsics from the codebase of current RVV1.0 GCC.
1). instructions that can leverage all current codes of RVV1.0 intrinsic with 
simply adding "th." prefix directly.
2). instructions that leverage current MD patterns but with some tweak and 
patterns copy since they are not simply added "th.".
3). new instructions that current RVV1.0 doesn't have like vlb instructions.
Overal, 1) and 3) look reasonable to me. But 2) need me some time to figure out 
the better way to do that (Current this patch with copying patterns is not 
approach I like)
So, I hope you can break this big patch into 3 different series patches.
1. Support partial theadvector instructions which leverage directly from 
current RVV1.0 with simple adding "th." prefix.
2. Support totally different name theadvector instructions but share same 
patterns as RVV1.0 instructions.
3. Support new headvector instructions like vlib...etc.
I think 1 and 3 separate patches can be quickly merged after my more details 
reviewed and approved in the following patches you send like V4 ?.
For 2, it's a bit more complicate, but I think we can support like ARM and 
other targets, use ASM targethook to rewrite the whole string of the 
instructions.
For example, like strided load/store, you can know this instructions from 
attribute:
(set_attr "type" "vlds")
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua) <mailto:cooper.jos...@linux.alibaba.com >
Date: 2023-12-20 20:20
To: gcc-patches <mailto:gcc-patches@gcc.gnu.org >
CC: jim.wilson.gcc <mailto:jim.wilson@gmail.com >; palmer 
<mailto:pal...@dabbelt.com >; andrew <mailto:and...@sifive.com >; 
philipp.tomsich <mailto:philipp.toms...@vrull.eu >; jeffreyalaw 
<mailto:jeffreya...@gmail.com >; christoph.muellner 
<mailto:christoph.muell...@vrull.eu >; juzhe.zhong <mailto:juzhe.zh...@rivai.ai 
>; Jun Sha (Joshua) <mailto:cooper.jos...@linux.alibaba.com >; Jin Ma 
<mailto:ji...@linux.alibaba.com >; Xianmiao Qu 
<mailto:cooper...@linux.alibaba.com >
Subject: [PATCH v3 0/6] RISC-V: Support XTheadVector extension
This patch series presents gcc implementation of the XTheadVector
extension [1].
[1] https://github.com/T-head-Semi/thead-extension-spec/ 
<https://github.com/T-head-Semi/thead-extension-spec/ >
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in order not to
generate instructions that xtheadvector does not support,
causing 36 changes in vector.md.
For the th. prefix issue, we use current_output_insn and
the ASM_OUTPUT_OPCODE hook instead of directly modifying
patterns in vector.md.
We have run the GCC test suite and can confirm that there
are no regressions.
All the test results can be found in the following links,
Run without xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803686.html 
<https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803686.html >
Run with xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803687.html 
<https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803687.html >
Furthermore, we have run the tests in 
https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples 
<https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples >, 
and all the tests passed.
Co-authored-by: Jin Ma 
Co-authored-by: 

[PATCH v3 6/6] RISC-V: Add support for xtheadvector-specific intrinsics.

[Jun Sha (Joshua)]

This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(BASE): Define new builtin bases.
* config/riscv/riscv-vector-builtins-bases.h:
Define new builtin class.
* config/riscv/riscv-vector-builtins-functions.def (vlsegff):
Include thead-vector-builtins-functions.def.
* config/riscv/riscv-vector-builtins-shapes.cc
(struct th_loadstore_width_def): Define new builtin shapes.
(struct th_indexed_loadstore_width_def):
Define new builtin shapes.
(SHAPE): Define new builtin shapes.
* config/riscv/riscv-vector-builtins-shapes.h:
Define new builtin shapes.
* config/riscv/riscv-vector-builtins-types.def
(DEF_RVV_I8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I32_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U32_OPS): Add datatypes for XTheadVector.
(vint8m1_t): Add datatypes for XTheadVector.
(vint8m2_t): Likewise.
(vint8m4_t): Likewise.
(vint8m8_t): Likewise.
(vint16m1_t): Likewise.
(vint16m2_t): Likewise.
(vint16m4_t): Likewise.
(vint16m8_t): Likewise.
(vint32m1_t): Likewise.
(vint32m2_t): Likewise.
(vint32m4_t): Likewise.
(vint32m8_t): Likewise.
(vint64m1_t): Likewise.
(vint64m2_t): Likewise.
(vint64m4_t): Likewise.
(vint64m8_t): Likewise.
(vuint8m1_t): Likewise.
(vuint8m2_t): Likewise.
(vuint8m4_t): Likewise.
(vuint8m8_t): Likewise.
(vuint16m1_t): Likewise.
(vuint16m2_t): Likewise.
(vuint16m4_t): Likewise.
(vuint16m8_t): Likewise.
(vuint32m1_t): Likewise.
(vuint32m2_t): Likewise.
(vuint32m4_t): Likewise.
(vuint32m8_t): Likewise.
(vuint64m1_t): Likewise.
(vuint64m2_t): Likewise.
(vuint64m4_t): Likewise.
(vuint64m8_t): Likewise.
* config/riscv/riscv-vector-builtins.cc
(DEF_RVV_I8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I32_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U32_OPS): Add datatypes for XTheadVector.
* config/riscv/thead-vector-builtins-functions.def: New file.
* config/riscv/thead-vector.md: Add new patterns.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c: New test.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 .../riscv/riscv-vector-builtins-shapes.cc | 126 +++
 .../riscv/riscv-vector-builtins-shapes.h  |   3 +
 .../riscv/riscv-vector-builtins-types.def | 120 +++
 gcc/config/riscv/riscv-vector-builtins.cc | 308 +-
 .../riscv/thead-vector-builtins-functions.def |  32 ++
 gcc/config/riscv/thead-vector-builtins.cc | 141 
 gcc/config/riscv/thead-vector-builtins.h  |  31 ++
 gcc/config/riscv/thead-vector.md  | 255 ++-
 .../riscv/rvv/xtheadvector/vlb-vsb.c  |  68 
 .../riscv/rvv/xtheadvector/vlbu-vsb.c |  68 
 .../riscv/rvv/xtheadvector/vlh-vsh.c  |  68 
 .../riscv/rvv/xtheadvector/vlhu-vsh.c |  68 
 .../riscv/rvv/xtheadvector/vlw-vsw.c  |  68 
 .../riscv/rvv/xtheadvector/vlwu-vsw.c |  68 
 14 files changed, 1422 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c

diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc 
b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index 6b49404a1fa..7d7c1f6f4b1 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -211,6 +211,104 @@ struct 

[PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

[Jun Sha (Joshua)]

This patch adds th. prefix to all XTheadVector instructions by
implementing new assembly output functions.

gcc/ChangeLog:

* config/riscv/riscv-protos.h
(riscv_asm_output_opcode): New function.
* config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
* config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config/riscv/riscv-protos.h   |  1 +
 gcc/config/riscv/riscv.cc | 26 +++
 gcc/config/riscv/riscv.h  |  4 +++
 .../riscv/rvv/xtheadvector/prefix.c   | 12 +
 4 files changed, 43 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index eaee53ce94e..f0eee71a18a 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -101,6 +101,7 @@ struct riscv_address_info {
 };
 
 /* Routines implemented in riscv.cc.  */
+extern void riscv_asm_output_opcode(FILE *asm_out_file, const char *p);
 extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
 extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
 extern int riscv_float_const_rtx_index_for_fli (rtx);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8ae65760b6e..d3010bed8d8 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5595,6 +5595,32 @@ riscv_get_v_regno_alignment (machine_mode mode)
   return lmul;
 }
 
+void
+riscv_asm_output_opcode(FILE *asm_out_file, const char *p)
+{
+  if (!TARGET_XTHEADVECTOR)
+return;
+
+  if (current_output_insn == NULL_RTX)
+return;
+
+  /* We need to handle the 'vset' special case here since it cannot
+ be controlled by vector mode. */
+  if (!strncmp (p, "vset", 4))
+{
+  fputs ("th.", asm_out_file);
+  return;
+}
+
+  subrtx_iterator::array_type array;
+  FOR_EACH_SUBRTX (iter, array, PATTERN (current_output_insn), ALL)
+if (*iter && riscv_v_ext_mode_p (GET_MODE (*iter)) && p[0] == 'v')
+  {
+   fputs ("th.", asm_out_file);
+   return;
+  }
+}
+
 /* Implement TARGET_PRINT_OPERAND.  The RISCV-specific operand codes are:
 
'h' Print the high-part relocation associated with OP, after stripping
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 6df9ec73c5e..7bb9c9ee408 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -826,6 +826,10 @@ extern enum riscv_cc get_riscv_cc (const rtx use);
   asm_fprintf ((FILE), "%U%s", (NAME));\
   } while (0)
 
+#undef ASM_OUTPUT_OPCODE
+#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
+  riscv_asm_output_opcode(STREAM, PTR)
+
 #define JUMP_TABLES_IN_TEXT_SECTION 0
 #define CASE_VECTOR_MODE SImode
 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
new file mode 100644
index 000..48867f4ddfb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadvector -mabi=ilp32 -O0" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+prefix (vint32m1_t vx, vint32m1_t vy, size_t vl)
+{
+  return __riscv_vadd_vv_i32m1 (vx, vy, vl);
+}
+
+/* { dg-final { scan-assembler {\mth\.v\M} } } */
\ No newline at end of file
-- 
2.17.1

[PATCH v3 3/6] RISC-V: Introduce XTheadVector as a subset of V1.0.0

[Jun Sha (Joshua)]

This patch is to introduce basic XTheadVector support
(march string parsing and a test for __riscv_xtheadvector)
according to https://github.com/T-head-Semi/thead-extension-spec/

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_subset_list::parse): Add new vendor extension.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
Add test marco.
* config/riscv/riscv.opt:  Add new mask.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-__riscv_th_v_intrinsic.c: New test.
* gcc.target/riscv/rvv/xtheadvector.c: New test.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/common/config/riscv/riscv-common.cc   | 23 +++
 gcc/config/riscv/riscv-c.cc   |  8 +--
 gcc/config/riscv/riscv.opt|  2 ++
 .../riscv/predef-__riscv_th_v_intrinsic.c | 11 +
 .../gcc.target/riscv/rvv/xtheadvector.c   | 13 +++
 5 files changed, 55 insertions(+), 2 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index f20d179568d..66b20c154a9 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -368,6 +368,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadvector", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
 
@@ -1251,6 +1252,15 @@ riscv_subset_list::check_conflict_ext ()
   if (lookup ("zcmp"))
error_at (m_loc, "%<-march=%s%>: zcd conflicts with zcmp", m_arch);
 }
+
+  if ((lookup ("v") || lookup ("zve32x")
+|| lookup ("zve64x") || lookup ("zve32f")
+|| lookup ("zve64f") || lookup ("zve64d")
+|| lookup ("zvl32b") || lookup ("zvl64b")
+|| lookup ("zvl128b") || lookup ("zvfh"))
+&& lookup ("xtheadvector"))
+error_at (m_loc, "%<-march=%s%>: xtheadvector conflicts with vector "
+  "extension or its sub-extensions", m_arch);
 }
 
 /* Parsing function for multi-letter extensions.
@@ -1743,6 +1753,19 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"xtheadmemidx",  _options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
   {"xtheadmempair", _options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
   {"xtheadsync",_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
+  {"xtheadvector",  _options::x_riscv_xthead_subext, MASK_XTHEADVECTOR},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_32},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_64},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_32},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_64},
+  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_16},
+  {"xtheadvector",  _options::x_riscv_zvl_flags, MASK_ZVL32B},
+  {"xtheadvector",  _options::x_riscv_zvl_flags, MASK_ZVL64B},
+  {"xtheadvector",  _options::x_riscv_zvl_flags, MASK_ZVL128B},
+  {"xtheadvector",  _options::x_riscv_zf_subext, MASK_ZVFHMIN},
+  {"xtheadvector",  _options::x_riscv_zf_subext, MASK_ZVFH},
+  {"xtheadvector",  _options::x_target_flags, MASK_FULL_V},
+  {"xtheadvector",  _options::x_target_flags, MASK_VECTOR},
 
   {"xventanacondops", _options::x_riscv_xventana_subext, 
MASK_XVENTANACONDOPS},
 
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index d70eb8ed361..d7c63ead147 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -138,6 +138,10 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
 riscv_ext_version_value (0, 11));
 }
 
+   if (TARGET_XTHEADVECTOR)
+ builtin_define_with_int_value ("__riscv_th_v_intrinsic",
+riscv_ext_version_value (0, 11));
+
   /* Define architecture extension test macros.  */
   builtin_define_with_int_value ("__riscv_arch_test", 1);
 
@@ -191,8 +195,8 @@ riscv_pragma_intrinsic (cpp_reader *)
 {
   if (!TARGET_VECTOR)
{
- error ("%<#pragma riscv intrinsic%> option %qs needs 'V' extension "
-"enabled",
+ error ("%<#pragma riscv intrinsic%> option %qs needs 'V' or "
+"'XTHEADVECTOR' extension enabled",
 name);
  return;
}
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index ede2d655e73..7de5f18e11b 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -449,6 +449,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext)
 
 Mask(XTHEADSYNC)

[PATCH v3 2/6] RISC-V: Split csr_operand in predicates.md for vector patterns.

[Jun Sha (Joshua)]

This patch splits the definition of csr_operand in predicates.md.
The newly defined vector_csr_operand has the same functionality
as csr_operand but can only be used in vector patterns, so that
changes for vector will not affect scalar patterns in files
like riscv.md.

gcc/ChangeLog:

* config/riscv/predicates.md (vector_csr_operand):
Define vector_csr_opeand for vector.
* config/riscv/vector.md:
Use newly defined csr_operand for vector.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 gcc/config/riscv/predicates.md | 4 
 gcc/config/riscv/vector.md | 8 
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 6bf6e186641..1a3a4f1ecbb 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -63,6 +63,10 @@ (define_predicate "csr_operand"
   (ior (match_operand 0 "const_csr_operand")
(match_operand 0 "register_operand")))
 
+(define_predicate "vector_csr_operand"
+  (ior (match_operand 0 "const_csr_operand")
+   (match_operand 0 "register_operand")))
+
 ;; V has 32-bit unsigned immediates.  This happens to be the same constraint as
 ;; the csr_operand, but it's not CSR related.
 (define_predicate "vector_scalar_shift_operand"
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index f607d768b26..036b2425f32 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1496,7 +1496,7 @@ (define_insn_and_split "*vec_duplicate"
 
 (define_insn "@vsetvl"
   [(set (match_operand:P 0 "register_operand" "=r")
-   (unspec:P [(match_operand:P 1 "csr_operand" "rK")
+   (unspec:P [(match_operand:P 1 "vector_csr_operand" "rK")
   (match_operand 2 "const_int_operand" "i")
   (match_operand 3 "const_int_operand" "i")
   (match_operand 4 "const_int_operand" "i")
@@ -1542,7 +1542,7 @@ (define_insn "vsetvl_vtype_change_only"
 ;; in vsetvl instruction pattern.
 (define_insn "@vsetvl_discard_result"
   [(set (reg:SI VL_REGNUM)
-   (unspec:SI [(match_operand:P 0 "csr_operand" "rK")
+   (unspec:SI [(match_operand:P 0 "vector_csr_operand" "rK")
(match_operand 1 "const_int_operand" "i")
(match_operand 2 "const_int_operand" "i")] UNSPEC_VSETVL))
(set (reg:SI VTYPE_REGNUM)
@@ -1564,7 +1564,7 @@ (define_insn "@vsetvl_discard_result"
 ;; such pattern can allow us gain benefits of these optimizations.
 (define_insn_and_split "@vsetvl_no_side_effects"
   [(set (match_operand:P 0 "register_operand" "=r")
-   (unspec:P [(match_operand:P 1 "csr_operand" "rK")
+   (unspec:P [(match_operand:P 1 "vector_csr_operand" "rK")
   (match_operand 2 "const_int_operand" "i")
   (match_operand 3 "const_int_operand" "i")
   (match_operand 4 "const_int_operand" "i")
@@ -1608,7 +1608,7 @@ (define_insn_and_split 
"*vsetvldi_no_side_effects_si_extend"
   [(set (match_operand:DI 0 "register_operand")
 (sign_extend:DI
   (subreg:SI
-   (unspec:DI [(match_operand:P 1 "csr_operand")
+   (unspec:DI [(match_operand:P 1 "vector_csr_operand")
(match_operand 2 "const_int_operand")
(match_operand 3 "const_int_operand")
(match_operand 4 "const_int_operand")
-- 
2.17.1

[PATCH v3 1/6] RISC-V: Refactor riscv-vector-builtins-bases.cc

[Jun Sha (Joshua)]

This patch moves the definition of the enums lst_type and
frm_op_type into riscv-vector-builtins-bases.h and removes
the static visibility of fold_fault_load(), so these
can be used in other compile units.

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc (enum lst_type):
(enum frm_op_type): move to riscv-vector-builtins-bases.h
* config/riscv/riscv-vector-builtins-bases.h
(GCC_RISCV_VECTOR_BUILTINS_BASES_H): Add header files.
(enum lst_type): move from
(enum frm_op_type): riscv-vector-builtins-bases.cc
(fold_fault_load): riscv-vector-builtins-bases.cc

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 
---
 .../riscv/riscv-vector-builtins-bases.cc  | 18 +-
 .../riscv/riscv-vector-builtins-bases.h   | 19 +++
 2 files changed, 20 insertions(+), 17 deletions(-)

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index d70468542ee..c51affde353 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -48,24 +48,8 @@ using namespace riscv_vector;
 
 namespace riscv_vector {
 
-/* Enumerates types of loads/stores operations.
-   It's only used in here so we don't define it
-   in riscv-vector-builtins-bases.h.  */
-enum lst_type
-{
-  LST_UNIT_STRIDE,
-  LST_STRIDED,
-  LST_INDEXED,
-};
-
-enum frm_op_type
-{
-  NO_FRM,
-  HAS_FRM,
-};
-
 /* Helper function to fold vleff and vlsegff.  */
-static gimple *
+gimple *
 fold_fault_load (gimple_folder )
 {
   /* fold fault_load (const *base, size_t *new_vl, size_t vl)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h 
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 131041ea66f..42d0cd17dc1 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -21,8 +21,27 @@
 #ifndef GCC_RISCV_VECTOR_BUILTINS_BASES_H
 #define GCC_RISCV_VECTOR_BUILTINS_BASES_H
 
+#include "gimple.h"
+#include "riscv-vector-builtins.h"
+
 namespace riscv_vector {
 
+/* Enumerates types of loads/stores operations.  */
+enum lst_type
+{
+  LST_UNIT_STRIDE,
+  LST_STRIDED,
+  LST_INDEXED,
+};
+
+enum frm_op_type
+{
+  NO_FRM,
+  HAS_FRM,
+};
+
+extern gimple *fold_fault_load (gimple_folder );
+
 namespace bases {
 extern const function_base *const vsetvl;
 extern const function_base *const vsetvlmax;
-- 
2.17.1

[PATCH v3 0/6] RISC-V: Support XTheadVector extension

[Jun Sha (Joshua)]

This patch series presents gcc implementation of the XTheadVector
extension [1].

[1] https://github.com/T-head-Semi/thead-extension-spec/

For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in order not to
generate instructions that xtheadvector does not support,
causing 36 changes in vector.md.

For the th. prefix issue, we use current_output_insn and
the ASM_OUTPUT_OPCODE hook instead of directly modifying
patterns in vector.md.

We have run the GCC test suite and can confirm that there
are no regressions.

All the test results can be found in the following links,
Run without xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803686.html

Run with xtheadvector:
https://gcc.gnu.org/pipermail/gcc-testresults/2023-December/803687.html

Furthermore, we have run the tests in 
https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/examples, 
and all the tests passed.

Co-authored-by: Jin Ma 
Co-authored-by: Xianmiao Qu 
Co-authored-by: Christoph Müllner 

RISC-V: Refactor riscv-vector-builtins-bases.cc
RISC-V: Split csr_operand in predicates.md for vector patterns
RISC-V: Introduce XTheadVector as a subset of V1.0.0
RISC-V: Adds the prefix "th." for the instructions of XTheadVector
RISC-V: Handle differences between XTheadvector and Vector
RISC-V: Add support for xtheadvector-specific intrinsics

---
 gcc/common/config/riscv/riscv-common.cc   |   23 +
 gcc/config.gcc|4 +-
 gcc/config/riscv/autovec.md   |2 +-
 gcc/config/riscv/predicates.md|8 +-
 gcc/config/riscv/riscv-c.cc   |8 +-
 gcc/config/riscv/riscv-protos.h   |1 +
 gcc/config/riscv/riscv-string.cc  |3 +
 gcc/config/riscv/riscv-v.cc   |   13 +-
 .../riscv/riscv-vector-builtins-bases.cc  |   18 +-
 .../riscv/riscv-vector-builtins-bases.h   |   19 +
 .../riscv/riscv-vector-builtins-shapes.cc |  149 +
 .../riscv/riscv-vector-builtins-shapes.h  |3 +
 .../riscv/riscv-vector-builtins-types.def |  120 +
 gcc/config/riscv/riscv-vector-builtins.cc |  315 +-
 gcc/config/riscv/riscv-vector-builtins.h  |5 +-
 gcc/config/riscv/riscv-vector-switch.def  |  150 +-
 gcc/config/riscv/riscv.cc |   46 +-
 gcc/config/riscv/riscv.h  |4 +
 gcc/config/riscv/riscv.opt|2 +
 gcc/config/riscv/riscv_th_vector.h|   49 +
 gcc/config/riscv/t-riscv  |   16 +
 .../riscv/thead-vector-builtins-functions.def |  659 
 gcc/config/riscv/thead-vector-builtins.cc |  887 ++
 gcc/config/riscv/thead-vector-builtins.h  |  123 +
 gcc/config/riscv/thead-vector.md  | 2827 +
 gcc/config/riscv/vector-iterators.md  |  186 +-
 gcc/config/riscv/vector.md|   44 +-
 .../riscv/predef-__riscv_th_v_intrinsic.c |   11 +
 .../gcc.target/riscv/rvv/base/abi-1.c |2 +-
 .../gcc.target/riscv/rvv/base/pragma-1.c  |2 +-
 .../gcc.target/riscv/rvv/xtheadvector.c   |   13 +
 .../riscv/rvv/xtheadvector/prefix.c   |   12 +
 .../riscv/rvv/xtheadvector/vlb-vsb.c  |   68 +
 .../riscv/rvv/xtheadvector/vlbu-vsb.c |   68 +
 .../riscv/rvv/xtheadvector/vlh-vsh.c  |   68 +
 .../riscv/rvv/xtheadvector/vlhu-vsh.c |   68 +
 .../riscv/rvv/xtheadvector/vlw-vsw.c  |   68 +
 .../riscv/rvv/xtheadvector/vlwu-vsw.c |   68 +
 gcc/testsuite/lib/target-supports.exp |   12 +
 39 files changed, 5931 insertions(+), 213 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_th_vector.h
 create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def
 create mode 100644 gcc/config/riscv/thead-vector-builtins.cc
 create mode 100644 gcc/config/riscv/thead-vector-builtins.h
 create mode 100644 gcc/config/riscv/thead-vector.md
 create mode 100644 
gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c

回复：RISC-V: Support XTheadVector extensions

[joshua]

Hi Kito,
Thank you for your support. We will get involved into community work actively 
for our XTheadVector patches. Let's work on upstream together during this 
process.
Currently, we are polishing up our patches according to Ju-Zhe's suggestions. 
Patch v3 with higher quality and less invasion will come soon. 
Joshua
--
发件人：Kito Cheng 
发送时间：2023年11月18日(星期六) 18:33
收件人：Philipp Tomsich
抄　送：Jeff Law; 
"juzhe.zh...@rivai.ai"; 
"gcc-patches"; "kito.cheng"; 
"cooper.joshua"; Robin 
Dapp; jkridner
主　题：Re: RISC-V: Support XTheadVector extensions
I guess it would be worth to state my thought publicly:
I *support* adding the T-head vector (a.k.a. vector 0.7) to upstream
GCC since T-Head vector already ships a large enough number of boards,
also it's not really T-head's problem as Palmer described in another
mail.
My biggest concern before is T-head folks didn't involved into
community work too much, so accept that definitely will increasing
work for maintainers, however I saw T-head folks is trying to
contribute stuffs to upstream now, so may not a concern now, also I
believe accept this patch will encourage they work more on upstream
together, which is benefit to each other.
Back to the one of the biggest issues for the patch set: GCC 14 or GCC
15. My general thought is it may be OK if it's less invasive enough,
then should be OK for GCC 14, but I don't have a strong opinion, since
as you know I am not the main developer of the vector part, so I will
let Ju-Zhe make the final decision, because he is the one who
contributes most things to RISC-V vector gcc support.

[PATCH v2 9/9] RISC-V: Disable fractional type intrinsics for the XTheadVector extension

[Jun Sha (Joshua)]

Because the XTheadVector extension does not support fractional
operations, so we need to delete the related intrinsics.

The types involved are as follows:
v(u)int8mf8_t,
v(u)int8mf4_t,
v(u)int8mf2_t,
v(u)int16mf4_t,
v(u)int16mf2_t,
v(u)int32mf2_t,
vfloat16mf4_t,
vfloat16mf2_t,
vfloat32mf2_t

Contributors:
Jun Sha (Joshua) 
Jin Ma 
Christoph Müllner 

gcc/ChangeLog:

* config/riscv/riscv-protos.h (riscv_v_ext_mode_p):
New extern.
* config/riscv/riscv-vector-builtins-shapes.cc (check_type):
New function.
(build_one): If the checked types fail, no function is generated.
* config/riscv/riscv-vector-switch.def (ENTRY):
Disable fractional mode for the XTheadVector extension.
(TUPLE_ENTRY): Likewise.
* config/riscv/riscv.cc (riscv_v_ext_vls_mode_p): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/fractional-type.c: New test.
---
 gcc/config/riscv/riscv-protos.h   |   1 +
 .../riscv/riscv-vector-builtins-shapes.cc |  22 +++
 gcc/config/riscv/riscv-vector-switch.def  | 144 +-
 gcc/config/riscv/riscv.cc |   2 +-
 .../gcc.target/riscv/rvv/fractional-type.c|  79 ++
 5 files changed, 175 insertions(+), 73 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/fractional-type.c

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 8cdfadbcf10..7de4f81aa9a 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -153,6 +153,7 @@ extern poly_uint64 riscv_regmode_natural_size 
(machine_mode);
 extern bool riscv_v_ext_vector_mode_p (machine_mode);
 extern bool riscv_v_ext_tuple_mode_p (machine_mode);
 extern bool riscv_v_ext_vls_mode_p (machine_mode);
+extern bool riscv_v_ext_mode_p (machine_mode);
 extern int riscv_get_v_regno_alignment (machine_mode);
 extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT);
 extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *);
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc 
b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index e24c535e496..dcdb9506ff2 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -33,6 +33,24 @@
 
 namespace riscv_vector {
 
+/* Check whether the RET and ARGS are valid for the function.  */
+
+static bool
+check_type (tree ret, vec )
+{
+  tree arg;
+  unsigned i;
+
+  if (!ret || (builtin_type_p (ret) && !riscv_v_ext_mode_p (TYPE_MODE (ret
+return false;
+
+  FOR_EACH_VEC_ELT (args, i, arg)
+if (!arg || (builtin_type_p (arg) && !riscv_v_ext_mode_p (TYPE_MODE 
(arg
+  return false;
+
+  return true;
+}
+
 /* Add one function instance for GROUP, using operand suffix at index OI,
mode suffix at index PAIR && bi and predication suffix at index pred_idx.  
*/
 static void
@@ -49,6 +67,10 @@ build_one (function_builder , const function_group_info 
,
 group.ops_infos.types[vec_type_idx].index);
   b.allocate_argument_types (function_instance, argument_types);
   b.apply_predication (function_instance, return_type, argument_types);
+
+  if (TARGET_XTHEADVECTOR && !check_type (return_type, argument_types))
+return;
+
   b.add_overloaded_function (function_instance, *group.shape);
   b.add_unique_function (function_instance, (*group.shape), return_type,
 argument_types);
diff --git a/gcc/config/riscv/riscv-vector-switch.def 
b/gcc/config/riscv/riscv-vector-switch.def
index 5c9f9bcbc3e..f17f87f89c9 100644
--- a/gcc/config/riscv/riscv-vector-switch.def
+++ b/gcc/config/riscv/riscv-vector-switch.def
@@ -81,39 +81,39 @@ ENTRY (RVVM8QI, true, LMUL_8, 1)
 ENTRY (RVVM4QI, true, LMUL_4, 2)
 ENTRY (RVVM2QI, true, LMUL_2, 4)
 ENTRY (RVVM1QI, true, LMUL_1, 8)
-ENTRY (RVVMF2QI, true, LMUL_F2, 16)
-ENTRY (RVVMF4QI, true, LMUL_F4, 32)
-ENTRY (RVVMF8QI, TARGET_MIN_VLEN > 32, LMUL_F8, 64)
+ENTRY (RVVMF2QI, !TARGET_XTHEADVECTOR, LMUL_F2, 16)
+ENTRY (RVVMF4QI, !TARGET_XTHEADVECTOR, LMUL_F4, 32)
+ENTRY (RVVMF8QI, (TARGET_MIN_VLEN > 32) && !TARGET_XTHEADVECTOR, LMUL_F8, 64)
 
 /* Disable modes if TARGET_MIN_VLEN == 32.  */
 ENTRY (RVVM8HI, true, LMUL_8, 2)
 ENTRY (RVVM4HI, true, LMUL_4, 4)
 ENTRY (RVVM2HI, true, LMUL_2, 8)
 ENTRY (RVVM1HI, true, LMUL_1, 16)
-ENTRY (RVVMF2HI, true, LMUL_F2, 32)
-ENTRY (RVVMF4HI, TARGET_MIN_VLEN > 32, LMUL_F4, 64)
+ENTRY (RVVMF2HI, !TARGET_XTHEADVECTOR, LMUL_F2, 32)
+ENTRY (RVVMF4HI, (TARGET_MIN_VLEN > 32) && !TARGET_XTHEADVECTOR, LMUL_F4, 64)
 
 /* Disable modes if TARGET_MIN_VLEN == 32 or !TARGET_VECTOR_ELEN_FP_16.  */
 ENTRY (RVVM8HF, TARGET_VECTOR_ELEN_FP_16, LMUL_8, 2)
 ENTRY (RVVM4HF, TARGET_VECTOR_ELEN_FP_16, LMUL_4, 4)
 ENTRY (RVVM2HF, TARGET_VECTOR_ELEN_FP_16, LMUL_2, 8)
 ENTRY (RVVM1HF, TARGET_VECTOR_ELEN_FP_16, LMUL_1, 16)
-ENTRY (RVVMF2HF, TARGET_VECTOR_ELEN_FP

[PATCH v2 8/9] RISC-V: Add support for xtheadvector-specific load/store intrinsics

[Jun Sha (Joshua)]

This patch involves the generation of xtheadvector special
load/store instructions.

Contributors:
Jun Sha (Joshua) 
Jin Ma 
Christoph Müllner 

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(BASE): Define new builtin bases.
* config/riscv/riscv-vector-builtins-bases.h:
Define new builtin class.
* config/riscv/riscv-vector-builtins-functions.def (vlsegff):
Include thead-vector-builtins-functions.def.
* config/riscv/riscv-vector-builtins-shapes.cc
(struct th_loadstore_width_def): Define new builtin shapes.
(struct th_indexed_loadstore_width_def):
Define new builtin shapes.
(SHAPE): Define new builtin shapes.
* config/riscv/riscv-vector-builtins-shapes.h:
Define new builtin shapes.
* config/riscv/riscv-vector-builtins-types.def
(DEF_RVV_I8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I32_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U32_OPS): Add datatypes for XTheadVector.
(vint8m1_t): Add datatypes for XTheadVector.
(vint8m2_t): Likewise.
(vint8m4_t): Likewise.
(vint8m8_t): Likewise.
(vint16m1_t): Likewise.
(vint16m2_t): Likewise.
(vint16m4_t): Likewise.
(vint16m8_t): Likewise.
(vint32m1_t): Likewise.
(vint32m2_t): Likewise.
(vint32m4_t): Likewise.
(vint32m8_t): Likewise.
(vint64m1_t): Likewise.
(vint64m2_t): Likewise.
(vint64m4_t): Likewise.
(vint64m8_t): Likewise.
(vuint8m1_t): Likewise.
(vuint8m2_t): Likewise.
(vuint8m4_t): Likewise.
(vuint8m8_t): Likewise.
(vuint16m1_t): Likewise.
(vuint16m2_t): Likewise.
(vuint16m4_t): Likewise.
(vuint16m8_t): Likewise.
(vuint32m1_t): Likewise.
(vuint32m2_t): Likewise.
(vuint32m4_t): Likewise.
(vuint32m8_t): Likewise.
(vuint64m1_t): Likewise.
(vuint64m2_t): Likewise.
(vuint64m4_t): Likewise.
(vuint64m8_t): Likewise.
* config/riscv/riscv-vector-builtins.cc
(DEF_RVV_I8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_I32_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U8_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U16_OPS): Add datatypes for XTheadVector.
(DEF_RVV_U32_OPS): Add datatypes for XTheadVector.
* config/riscv/vector.md: Include thead-vector.md.
* config/riscv/thead-vector-builtins-functions.def: New file.
* config/riscv/thead-vector.md: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c: New test.
---
 .../riscv/riscv-vector-builtins-bases.cc  | 122 +++
 .../riscv/riscv-vector-builtins-bases.h   |  30 ++
 .../riscv/riscv-vector-builtins-functions.def |   2 +
 .../riscv/riscv-vector-builtins-shapes.cc | 100 ++
 .../riscv/riscv-vector-builtins-shapes.h  |   2 +
 .../riscv/riscv-vector-builtins-types.def | 120 +++
 gcc/config/riscv/riscv-vector-builtins.cc | 300 +-
 .../riscv/thead-vector-builtins-functions.def |  30 ++
 gcc/config/riscv/thead-vector.md  | 235 ++
 gcc/config/riscv/vector.md|   1 +
 .../riscv/rvv/xtheadvector/vlb-vsb.c  |  68 
 .../riscv/rvv/xtheadvector/vlbu-vsb.c |  68 
 .../riscv/rvv/xtheadvector/vlh-vsh.c  |  68 
 .../riscv/rvv/xtheadvector/vlhu-vsh.c |  68 
 .../riscv/rvv/xtheadvector/vlw-vsw.c  |  68 
 .../riscv/rvv/xtheadvector/vlwu-vsw.c |  68 
 16 files changed, 1349 insertions(+), 1 deletion(-)
 create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def
 create mode 100644 gcc/config/riscv/thead-vector.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c

diff --git a/gcc/config/riscv/riscv

[PATCH v2 6/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part4)

[Jun Sha (Joshua)]

For big changes in instruction generation, we can only duplicate
some typical tests in testsuite/gcc.target/riscv/rvv/base.

This patch is adding some tests for ternary and unary operations.

Contributors:
Jun Sha (Joshua) 
Jin Ma 
Christoph Müllner 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-1.c: New test.
* gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-2.c: New test.
* gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-3.c: New test.
* gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-4.c: New test.
* gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-5.c: New test.
* gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-6.c: New test.
* gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-1.c: New test.
* gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-2.c: New test.
* gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-3.c: New test.
* gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-4.c: New test.
* gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-5.c: New test.
* gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-6.c: New test.
* gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-7.c: New test.
* gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-8.c: New test.
* gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-9.c: New test.
* gcc.target/riscv/rvv/xtheadvector/unop_v_constraint-1.c: New test.
---
 .../rvv/xtheadvector/ternop_vv_constraint-1.c |  83 +++
 .../rvv/xtheadvector/ternop_vv_constraint-2.c |  83 +++
 .../rvv/xtheadvector/ternop_vv_constraint-3.c |  83 +++
 .../rvv/xtheadvector/ternop_vv_constraint-4.c |  83 +++
 .../rvv/xtheadvector/ternop_vv_constraint-5.c |  83 +++
 .../rvv/xtheadvector/ternop_vv_constraint-6.c |  83 +++
 .../rvv/xtheadvector/ternop_vx_constraint-1.c |  71 ++
 .../rvv/xtheadvector/ternop_vx_constraint-2.c |  38 +
 .../rvv/xtheadvector/ternop_vx_constraint-3.c | 125 +
 .../rvv/xtheadvector/ternop_vx_constraint-4.c | 123 +
 .../rvv/xtheadvector/ternop_vx_constraint-5.c | 123 +
 .../rvv/xtheadvector/ternop_vx_constraint-6.c | 130 ++
 .../rvv/xtheadvector/ternop_vx_constraint-7.c | 130 ++
 .../rvv/xtheadvector/ternop_vx_constraint-8.c |  71 ++
 .../rvv/xtheadvector/ternop_vx_constraint-9.c |  71 ++
 .../rvv/xtheadvector/unop_v_constraint-1.c|  68 +
 16 files changed, 1448 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-1.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-2.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-3.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-4.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-5.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-6.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-1.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-2.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-3.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-4.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-5.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-6.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-7.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-8.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vx_constraint-9.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/unop_v_constraint-1.c

diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-1.c
new file mode 100644
index 000..d98755e7040
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/ternop_vv_constraint-1.c
@@ -0,0 +1,83 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+**  ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+\)
+** th.vma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** th.vma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** th.vma[c-d][c-d]\.vv\tv[0-9]+,\s*v[

[PATCH v2 5/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part3)

[Jun Sha (Joshua)]

For big changes in instruction generation, we can only duplicate
some typical tests in testsuite/gcc.target/riscv/rvv/base.

This patch is adding some tests for binary operations.

Contributors:
Jun Sha (Joshua) 
Jin Ma 
Christoph Müllner 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-31.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-32.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-33.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-34.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-35.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-36.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-37.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-38.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-39.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-40.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-41.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-42.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-43.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-44.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-45.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-46.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-47.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-48.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-49.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-50.c: New test.
---
 .../rvv/xtheadvector/binop_vx_constraint-31.c |  73 +++
 .../rvv/xtheadvector/binop_vx_constraint-32.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-33.c |  73 +++
 .../rvv/xtheadvector/binop_vx_constraint-34.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-35.c |  73 +++
 .../rvv/xtheadvector/binop_vx_constraint-36.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-37.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-38.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-39.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-40.c |  73 +++
 .../rvv/xtheadvector/binop_vx_constraint-41.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-42.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-43.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-44.c |  73 +++
 .../rvv/xtheadvector/binop_vx_constraint-45.c | 123 ++
 .../rvv/xtheadvector/binop_vx_constraint-46.c |  72 ++
 .../rvv/xtheadvector/binop_vx_constraint-47.c |  16 +++
 .../rvv/xtheadvector/binop_vx_constraint-48.c |  16 +++
 .../rvv/xtheadvector/binop_vx_constraint-49.c |  16 +++
 .../rvv/xtheadvector/binop_vx_constraint-50.c |  18 +++
 20 files changed, 1238 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-31.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-33.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-34.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-35.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-36.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-37.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-38.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-39.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-40.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-41.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-42.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-43.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-44.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-45.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-46.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-47.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-48.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-49.c
 create mode

[PATCH v2 4/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part2)

[Jun Sha (Joshua)]

For big changes in instruction generation, we can only duplicate
some typical tests in testsuite/gcc.target/riscv/rvv/base.

This patch is adding some tests for binary operations.

Contributors:
Jun Sha (Joshua) 
Jin Ma 
Christoph Müllner 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-11.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-12.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-13.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-14.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-15.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-16.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-17.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-18.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-19.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-20.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-21.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-22.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-23.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-24.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-25.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-26.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-27.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-28.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-29.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-30.c: New test.
---
 .../rvv/xtheadvector/binop_vx_constraint-11.c | 68 +
 .../rvv/xtheadvector/binop_vx_constraint-12.c | 73 +++
 .../rvv/xtheadvector/binop_vx_constraint-13.c | 68 +
 .../rvv/xtheadvector/binop_vx_constraint-14.c | 68 +
 .../rvv/xtheadvector/binop_vx_constraint-15.c | 68 +
 .../rvv/xtheadvector/binop_vx_constraint-16.c | 73 +++
 .../rvv/xtheadvector/binop_vx_constraint-17.c | 73 +++
 .../rvv/xtheadvector/binop_vx_constraint-18.c | 68 +
 .../rvv/xtheadvector/binop_vx_constraint-19.c | 73 +++
 .../rvv/xtheadvector/binop_vx_constraint-20.c | 68 +
 .../rvv/xtheadvector/binop_vx_constraint-21.c | 73 +++
 .../rvv/xtheadvector/binop_vx_constraint-22.c | 68 +
 .../rvv/xtheadvector/binop_vx_constraint-23.c | 73 +++
 .../rvv/xtheadvector/binop_vx_constraint-24.c | 68 +
 .../rvv/xtheadvector/binop_vx_constraint-25.c | 73 +++
 .../rvv/xtheadvector/binop_vx_constraint-26.c | 68 +
 .../rvv/xtheadvector/binop_vx_constraint-27.c | 73 +++
 .../rvv/xtheadvector/binop_vx_constraint-28.c | 68 +
 .../rvv/xtheadvector/binop_vx_constraint-29.c | 73 +++
 .../rvv/xtheadvector/binop_vx_constraint-30.c | 68 +
 20 files changed, 1405 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-11.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-12.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-13.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-14.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-15.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-16.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-17.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-18.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-19.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-20.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-21.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-22.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-23.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-24.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-25.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-26.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-27.c
 create mode 100644 
gcc/testsuite/gcc.target

[PATCH v2 3/9] RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part1)

[Jun Sha (Joshua)]

For big changes in instruction generation, we can only duplicate
some typical tests in testsuite/gcc.target/riscv/rvv/base.

This patch is adding some tests for binary operations.

Contributors:
Jun Sha (Joshua) 
Jin Ma 
Christoph Müllner 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-1.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-3.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-4.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-5.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-6.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-7.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-1.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-10.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-2.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-3.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-4.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-5.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-6.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-7.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-8.c: New test.
* gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-9.c: New test.
* gcc.target/riscv/rvv/xtheadvector/rvv-xtheadvector.exp: New test.
---
 .../rvv/xtheadvector/binop_vv_constraint-1.c  | 68 +
 .../rvv/xtheadvector/binop_vv_constraint-3.c  | 27 +++
 .../rvv/xtheadvector/binop_vv_constraint-4.c  | 27 +++
 .../rvv/xtheadvector/binop_vv_constraint-5.c  | 29 
 .../rvv/xtheadvector/binop_vv_constraint-6.c  | 28 +++
 .../rvv/xtheadvector/binop_vv_constraint-7.c  | 29 
 .../rvv/xtheadvector/binop_vx_constraint-1.c  | 68 +
 .../rvv/xtheadvector/binop_vx_constraint-10.c | 68 +
 .../rvv/xtheadvector/binop_vx_constraint-2.c  | 68 +
 .../rvv/xtheadvector/binop_vx_constraint-3.c  | 68 +
 .../rvv/xtheadvector/binop_vx_constraint-4.c  | 73 +++
 .../rvv/xtheadvector/binop_vx_constraint-5.c  | 68 +
 .../rvv/xtheadvector/binop_vx_constraint-6.c  | 68 +
 .../rvv/xtheadvector/binop_vx_constraint-7.c  | 68 +
 .../rvv/xtheadvector/binop_vx_constraint-8.c  | 73 +++
 .../rvv/xtheadvector/binop_vx_constraint-9.c  | 68 +
 .../rvv/xtheadvector/rvv-xtheadvector.exp | 41 +++
 17 files changed, 939 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-1.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-3.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-4.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-5.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-6.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-7.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-1.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-10.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-2.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-3.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-4.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-5.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-6.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-7.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-8.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vx_constraint-9.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/rvv-xtheadvector.exp

diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-1.c
new file mode 100644
index 000..172dfb6c228
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/binop_vv_constraint-1.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+**  ...
+** th.vle\.v\tv[0-9]+,0\([a-x0-9]+

[PATCH v2 2/9] RISC-V: Handle differences between xtheadvector and vector

[Jun Sha (Joshua)]

This patch is to handle the differences in instruction generation
between vector and xtheadvector, mainly adding th. prefix
to all xtheadvector instructions.

Contributors:
Jun Sha (Joshua) 
Jin Ma 
Christoph Müllner 

gcc/ChangeLog:

* config.gcc: Add header for XTheadVector intrinsics.
* config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
Add XTheadVector.
* config/riscv/riscv.cc (riscv_print_operand):
Add new operand format directives.
(riscv_print_operand_punct_valid_p): Likewise.
* config/riscv/vector-iterators.md: Split any_int_unop
for not and neg.
* config/riscv/vector.md (@pred_):
Add th. for xtheadvector instructions.
* config/riscv/riscv_th_vector.h: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pragma-1.c: Add XTheadVector.
---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/riscv-c.cc   |   4 +-
 gcc/config/riscv/riscv.cc |  11 +-
 gcc/config/riscv/riscv_th_vector.h|  49 ++
 gcc/config/riscv/vector-iterators.md  |   4 +
 gcc/config/riscv/vector.md| 777 +-
 .../gcc.target/riscv/rvv/base/pragma-1.c  |   2 +-
 7 files changed, 466 insertions(+), 383 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_th_vector.h

diff --git a/gcc/config.gcc b/gcc/config.gcc
index ba6d63e33ac..e0fc2b1a27c 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -548,7 +548,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o"
d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_th_vector.h"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles 
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 184fff905b2..0a17d5f6656 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -194,8 +194,8 @@ riscv_pragma_intrinsic (cpp_reader *)
 {
   if (!TARGET_VECTOR)
{
- error ("%<#pragma riscv intrinsic%> option %qs needs 'V' extension "
-"enabled",
+ error ("%<#pragma riscv intrinsic%> option %qs needs 'V' or "
+"'XTHEADVECTOR' extension enabled",
 name);
  return;
}
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ecee7eb4727..754107cdaac 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5323,7 +5323,7 @@ riscv_get_v_regno_alignment (machine_mode mode)
 static void
 riscv_print_operand (FILE *file, rtx op, int letter)
 {
-  /* `~` does not take an operand so op will be null
+  /* `~` and '^' does not take an operand so op will be null
  Check for before accessing op.
   */
   if (letter == '~')
@@ -5332,6 +5332,13 @@ riscv_print_operand (FILE *file, rtx op, int letter)
fputc('w', file);
   return;
 }
+
+  if (letter == '^')
+{
+  if (TARGET_XTHEADVECTOR)
+   fputs ("th.", file);
+  return;
+}
   machine_mode mode = GET_MODE (op);
   enum rtx_code code = GET_CODE (op);
 
@@ -5584,7 +5591,7 @@ riscv_print_operand (FILE *file, rtx op, int letter)
 static bool
 riscv_print_operand_punct_valid_p (unsigned char code)
 {
-  return (code == '~');
+  return (code == '~' || code == '^');
 }
 
 /* Implement TARGET_PRINT_OPERAND_ADDRESS.  */
diff --git a/gcc/config/riscv/riscv_th_vector.h 
b/gcc/config/riscv/riscv_th_vector.h
new file mode 100644
index 000..194652032bc
--- /dev/null
+++ b/gcc/config/riscv/riscv_th_vector.h
@@ -0,0 +1,49 @@
+/* RISC-V 'XTheadVector' Extension intrinsics include file.
+   Copyright (C) 2022-2023 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this p

[PATCH v2 1/9] RISC-V: minimal support for xtheadvector

[Jun Sha (Joshua)]

This patch is to introduce basic XTheadVector support
(march string parsing and a test for __riscv_xtheadvector)
according to https://github.com/T-head-Semi/thead-extension-spec/

Contributors:
Jun Sha (Joshua) 
Jin Ma 
Christoph Müllner 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_subset_list::parse): : Add new vendor extension.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
Add test marco.
* config/riscv/riscv.opt: Add new mask.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-__riscv_th_v_intrinsic.c: New test.
* gcc.target/riscv/rvv/xtheadvector.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc | 10 ++
 gcc/config/riscv/riscv-c.cc |  4 
 gcc/config/riscv/riscv.opt  |  2 ++
 .../riscv/predef-__riscv_th_v_intrinsic.c   | 11 +++
 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c   | 13 +
 5 files changed, 40 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 526dbb7603b..914924171fd 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -75,6 +75,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
 
   {"v", "zvl128b"},
   {"v", "zve64d"},
+  {"xtheadvector", "zvl128b"},
+  {"xtheadvector", "zve64d"},
 
   {"zve32f", "f"},
   {"zve64f", "f"},
@@ -325,6 +327,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadvector", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
 
@@ -1495,6 +1498,10 @@ riscv_subset_list::parse (const char *arch, location_t 
loc)
 error_at (loc, "%<-march=%s%>: z*inx conflicts with floating-point "
   "extensions", arch);
 
+  if (subset_list->lookup ("v") && subset_list->lookup ("xtheadvector"))
+error_at (loc, "%<-march=%s%>: xtheadvector conflicts with vector "
+  "extensions", arch);
+
   /* 'H' hypervisor extension requires base ISA with 32 registers.  */
   if (subset_list->lookup ("e") && subset_list->lookup ("h"))
 error_at (loc, "%<-march=%s%>: h extension requires i extension", arch);
@@ -1680,6 +1687,9 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"xtheadmemidx",  _options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
   {"xtheadmempair", _options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
   {"xtheadsync",_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
+  {"xtheadvector",  _options::x_riscv_xthead_subext, MASK_XTHEADVECTOR},
+  {"xtheadvector",  _options::x_target_flags, MASK_FULL_V},
+  {"xtheadvector",  _options::x_target_flags, MASK_VECTOR},
 
   {"xventanacondops", _options::x_riscv_xventana_subext, 
MASK_XVENTANACONDOPS},
 
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index b7f9ba204f7..184fff905b2 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -137,6 +137,10 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
 riscv_ext_version_value (0, 11));
 }
 
+   if (TARGET_XTHEADVECTOR)
+ builtin_define_with_int_value ("__riscv_th_v_intrinsic",
+riscv_ext_version_value (0, 11));
+
   /* Define architecture extension test macros.  */
   builtin_define_with_int_value ("__riscv_arch_test", 1);
 
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 70d78151cee..72857aea352 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -438,6 +438,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext)
 
 Mask(XTHEADSYNC)Var(riscv_xthead_subext)
 
+Mask(XTHEADVECTOR)  Var(riscv_xthead_subext)
+
 TargetVariable
 int riscv_xventana_subext
 
diff --git a/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c 
b/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
new file mode 100644
index 000..1c764241db6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64imafdcxtheadvector -mabi=lp64d" } */
+
+int main () {
+
+#if __riscv_th_v_intr

[PATCH v2 0/9] RISC-V: Support XTheadVector extensions

[Jun Sha (Joshua)]

This patch series presents gcc implementation of the XTheadVector
extension [1].

[1] https://github.com/T-head-Semi/thead-extension-spec/

I updated my patch series, because I forgot to add co-authors in
the last version.

Contributors:
Jun Sha (Joshua) 
Jin Ma 
Christoph Müllner 

RISC-V: minimal support for xtheadvector
RISC-V: Handle differences between xtheadvector and vector
RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part1)
RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part2)
RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part3)
RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part4)
RISC-V: Tests for overlapping RVV and XTheadVector instructions (Part5)
RISC-V: Add support for xtheadvector-specific load/store intrinsics
RISC-V: Disable fractional type intrinsics for XTheadVector

---
 gcc/common/config/riscv/riscv-common.cc   |  10 +
 gcc/config.gcc|   2 +-
 gcc/config/riscv/riscv-c.cc   |   8 +-
 gcc/config/riscv/riscv-protos.h   |   1 +
 .../riscv/riscv-vector-builtins-bases.cc  | 122 +++
 .../riscv/riscv-vector-builtins-bases.h   |  30 +
 .../riscv/riscv-vector-builtins-functions.def |   2 +
 .../riscv/riscv-vector-builtins-shapes.cc | 122 +++
 .../riscv/riscv-vector-builtins-shapes.h  |   2 +
 .../riscv/riscv-vector-builtins-types.def | 120 +++
 gcc/config/riscv/riscv-vector-builtins.cc | 300 ++-
 gcc/config/riscv/riscv-vector-switch.def  | 144 ++--
 gcc/config/riscv/riscv.cc |  13 +-
 gcc/config/riscv/riscv.opt|   2 +
 gcc/config/riscv/riscv_th_vector.h|  49 ++
 .../riscv/thead-vector-builtins-functions.def |  30 +
 gcc/config/riscv/thead-vector.md  | 235 ++
 gcc/config/riscv/vector-iterators.md  |   4 +
 gcc/config/riscv/vector.md| 778 +-
 .../riscv/predef-__riscv_th_v_intrinsic.c |  11 +
 .../gcc.target/riscv/rvv/base/pragma-1.c  |   2 +-
 .../gcc.target/riscv/rvv/fractional-type.c|  79 ++
 .../gcc.target/riscv/rvv/xtheadvector.c   |  13 +
 .../rvv/xtheadvector/autovec/vadd-run-nofm.c  |   4 +
 .../riscv/rvv/xtheadvector/autovec/vadd-run.c |  81 ++
 .../xtheadvector/autovec/vadd-rv32gcv-nofm.c  |  10 +
 .../rvv/xtheadvector/autovec/vadd-rv32gcv.c   |   8 +
 .../xtheadvector/autovec/vadd-rv64gcv-nofm.c  |  10 +
 .../rvv/xtheadvector/autovec/vadd-rv64gcv.c   |   8 +
 .../rvv/xtheadvector/autovec/vadd-template.h  |  70 ++
 .../rvv/xtheadvector/autovec/vadd-zvfh-run.c  |  54 ++
 .../riscv/rvv/xtheadvector/autovec/vand-run.c |  75 ++
 .../rvv/xtheadvector/autovec/vand-rv32gcv.c   |   7 +
 .../rvv/xtheadvector/autovec/vand-rv64gcv.c   |   7 +
 .../rvv/xtheadvector/autovec/vand-template.h  |  61 ++
 .../rvv/xtheadvector/binop_vv_constraint-1.c  |  68 ++
 .../rvv/xtheadvector/binop_vv_constraint-3.c  |  27 +
 .../rvv/xtheadvector/binop_vv_constraint-4.c  |  27 +
 .../rvv/xtheadvector/binop_vv_constraint-5.c  |  29 +
 .../rvv/xtheadvector/binop_vv_constraint-6.c  |  28 +
 .../rvv/xtheadvector/binop_vv_constraint-7.c  |  29 +
 .../rvv/xtheadvector/binop_vx_constraint-1.c  |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-10.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-11.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-12.c |  73 ++
 .../rvv/xtheadvector/binop_vx_constraint-13.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-14.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-15.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-16.c |  73 ++
 .../rvv/xtheadvector/binop_vx_constraint-17.c |  73 ++
 .../rvv/xtheadvector/binop_vx_constraint-18.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-19.c |  73 ++
 .../rvv/xtheadvector/binop_vx_constraint-2.c  |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-20.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-21.c |  73 ++
 .../rvv/xtheadvector/binop_vx_constraint-22.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-23.c |  73 ++
 .../rvv/xtheadvector/binop_vx_constraint-24.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-25.c |  73 ++
 .../rvv/xtheadvector/binop_vx_constraint-26.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-27.c |  73 ++
 .../rvv/xtheadvector/binop_vx_constraint-28.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-29.c |  73 ++
 .../rvv/xtheadvector/binop_vx_constraint-3.c  |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-30.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-31.c |  73 ++
 .../rvv/xtheadvector/binop_vx_constraint-32.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-33.c |  73 ++
 .../rvv/xtheadvector/binop_vx_constraint-34.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-35.c |  73 ++
 .../rvv/xtheadvector/binop_vx_constraint-36.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-37.c |  68 ++
 .../rvv/xtheadvector/binop_vx_constraint-38.c |  68